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[deliverable/binutils-gdb.git] / opcodes / m32c-opc.c
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49f58d10
JB		 1/* Instruction opcode table for m32c.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
9b201bb5 5Copyright 1996-2007 Free Software Foundation, Inc.
49f58d10
JB		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9b201bb5
NC		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
49f58d10 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
49f58d10 18
9b201bb5
NC		 19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
49f58d10
JB		 22
23*/
24
25#include "sysdep.h"
26#include "ansidecl.h"
27#include "bfd.h"
28#include "symcat.h"
29#include "m32c-desc.h"
30#include "m32c-opc.h"
31#include "libiberty.h"
32
33/* -- opc.c */
34static unsigned int
35m32c_asm_hash (const char *mnem)
36{
37 unsigned int h;
38
39 /* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */
40 if (mnem[0] == 'j' && mnem[1] != 's')
41 return 'j';
42
43 /* Don't hash scCND */
44 if (mnem[0] == 's' && mnem[1] == 'c')
45 return 's';
46
c6552317
DD		 47 /* Don't hash bmCND */
48 if (mnem[0] == 'b' && mnem[1] == 'm')
49 return 'b';
50
49f58d10
JB		 51 for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
52 h += *mnem;
53 return h % CGEN_ASM_HASH_SIZE;
54}
55\f
56/* -- asm.c */
57/* The hash functions are recorded here to help keep assembler code out of
58 the disassembler and vice versa. */
59
e729279b
NC		 60static int asm_hash_insn_p (const CGEN_INSN *);
61static unsigned int asm_hash_insn (const char *);
62static int dis_hash_insn_p (const CGEN_INSN *);
63static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
49f58d10
JB		 64
65/* Instruction formats. */
66
67#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
68#define F(f) & m32c_cgen_ifld_table[M32C_##f]
69#else
70#define F(f) & m32c_cgen_ifld_table[M32C_/**/f]
71#endif
72static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
73 0, 0, 0x0, { { 0 } }
74};
75
76static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
77 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
78};
79
80static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
81 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
82};
83
84static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
85 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
86};
87
88static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
89 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
90};
91
92static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
93 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
94};
95
96static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
97 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
98};
99
100static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
101 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
102};
103
104static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
105 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
106};
107
108static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
109 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
110};
111
112static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
113 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
114};
115
116static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
117 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
118};
119
120static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
121 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
122};
123
124static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
125 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
126};
127
128static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
129 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
130};
131
132static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
133 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
134};
135
136static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
137 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
138};
139
140static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
141 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
142};
143
144static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
145 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
146};
147
148static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
149 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
150};
151
152static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
153 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
154};
155
156static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
157 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
158};
159
160static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
161 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
162};
163
164static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
165 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
166};
167
168static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
169 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
170};
171
172static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
173 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
174};
175
176static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
177 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
178};
179
180static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
181 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
182};
183
184static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
185 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
186};
187
188static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
189 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
190};
191
192static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
193 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
194};
195
196static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
197 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
198};
199
200static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
201 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
202};
203
204static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
205 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
206};
207
208static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
209 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
210};
211
212static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
213 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
214};
215
216static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
217 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
218};
219
220static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
221 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
222};
223
224static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
225 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
226};
227
228static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
229 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
230};
231
232static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
233 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
234};
235
236static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
237 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
238};
239
240static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
241 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
242};
243
244static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
245 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
246};
247
248static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
249 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
250};
251
252static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
253 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
254};
255
256static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
257 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
258};
259
260static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
261 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
262};
263
264static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
265 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
266};
267
268static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
269 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
270};
271
272static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
273 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
274};
275
276static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
277 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
278};
279
280static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
281 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
282};
283
284static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
285 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
286};
287
288static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
289 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
290};
291
292static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
293 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
294};
295
296static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
297 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
298};
299
300static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
301 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
302};
303
304static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
305 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
306};
307
308static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
309 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
310};
311
312static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
313 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
314};
315
316static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
317 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
318};
319
320static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
321 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
322};
323
324static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
325 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
326};
327
328static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
329 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
330};
331
332static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
333 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
334};
335
336static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
337 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
338};
339
340static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
341 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
342};
343
344static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
345 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
346};
347
348static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
349 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
350};
351
352static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
353 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
354};
355
356static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
357 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
358};
359
360static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
361 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
362};
363
364static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
365 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
366};
367
368static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
369 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
370};
371
372static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
373 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
374};
375
376static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
377 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
378};
379
380static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
381 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
382};
383
384static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
385 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
386};
387
388static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
389 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
390};
391
392static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
393 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
394};
395
396static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
397 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
398};
399
400static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
401 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
402};
403
404static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
405 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
406};
407
408static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
409 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
410};
411
412static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
413 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
414};
415
416static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
417 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
418};
419
420static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
421 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
422};
423
424static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
425 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
426};
427
428static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
429 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
430};
431
432static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
433 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
434};
435
436static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
437 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
438};
439
440static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
441 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
442};
443
444static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
445 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
446};
447
448static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
449 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
450};
451
452static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
453 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
454};
455
456static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
457 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
458};
459
460static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
461 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
462};
463
464static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
465 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
466};
467
468static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
469 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
470};
471
472static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
473 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
474};
475
476static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
477 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
478};
479
480static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
481 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
482};
483
484static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
485 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
486};
487
488static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
489 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
490};
491
492static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
493 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
494};
495
496static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
497 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
498};
499
500static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
501 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
502};
503
504static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
505 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
506};
507
508static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
509 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
510};
511
512static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
513 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
514};
515
516static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
517 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
518};
519
520static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
521 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
522};
523
524static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
525 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
526};
527
528static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
529 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
530};
531
532static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
533 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
534};
535
536static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
537 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
538};
539
540static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
541 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
542};
543
544static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
545 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
546};
547
548static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
549 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
550};
551
552static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
553 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
554};
555
556static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
557 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
558};
559
560static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
561 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
562};
563
564static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
565 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
566};
567
568static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
569 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
570};
571
572static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
573 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
574};
575
576static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
577 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
578};
579
580static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
581 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
582};
583
584static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
585 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
586};
587
588static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
589 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
590};
591
592static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
593 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
594};
595
596static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
597 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
598};
599
600static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
601 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
602};
603
604static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
605 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
606};
607
608static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
609 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
610};
611
612static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
613 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
614};
615
616static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
617 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
618};
619
620static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
621 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
622};
623
624static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
625 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
626};
627
628static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
629 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
630};
631
632static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
633 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
634};
635
636static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
637 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
638};
639
640static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
641 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
642};
643
644static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
645 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
646};
647
648static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
649 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
650};
651
652static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
653 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
654};
655
656static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
657 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
658};
659
660static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
661 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
662};
663
664static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
665 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
666};
667
668static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
669 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
670};
671
672static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
673 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
674};
675
676static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
677 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
678};
679
680static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
681 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
682};
683
684static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
685 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
686};
687
688static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
689 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
690};
691
692static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
693 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
694};
695
696static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
697 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
698};
699
700static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI ATTRIBUTE_UNUSED = {
701 16, 16, 0xfffd, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN_EXT) }, { F (F_15_1) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
702};
703
704static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI ATTRIBUTE_UNUSED = {
705 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
706};
707
708static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI ATTRIBUTE_UNUSED = {
709 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
710};
711
712static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI ATTRIBUTE_UNUSED = {
713 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
714};
715
716static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI ATTRIBUTE_UNUSED = {
717 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
718};
719
720static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI ATTRIBUTE_UNUSED = {
721 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
722};
723
724static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI ATTRIBUTE_UNUSED = {
725 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
726};
727
728static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI ATTRIBUTE_UNUSED = {
729 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
730};
731
732static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
733 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
734};
735
736static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
737 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
738};
739
740static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
741 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
742};
743
744static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
745 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
746};
747
748static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
749 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
750};
751
752static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
753 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
754};
755
756static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
757 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
758};
759
760static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
761 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
762};
763
764static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
765 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
766};
767
768static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
769 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
770};
771
772static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
773 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
774};
775
776static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
777 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
778};
779
780static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
781 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
782};
783
784static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
785 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
786};
787
788static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
789 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
790};
791
792static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
793 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
794};
795
796static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
797 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
798};
799
800static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
801 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
802};
803
804static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
805 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
806};
807
808static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
809 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
810};
811
812static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
813 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
814};
815
816static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
817 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
818};
819
820static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
821 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
822};
823
824static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
825 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
826};
827
828static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
829 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
830};
831
832static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
833 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
834};
835
836static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
837 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
838};
839
840static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
841 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
842};
843
844static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
845 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
846};
847
848static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
849 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
850};
851
852static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
853 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
854};
855
856static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
857 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
858};
859
860static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
861 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
862};
863
864static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
865 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
866};
867
868static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
869 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
870};
871
872static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
873 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
874};
875
876static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
877 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
878};
879
880static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
881 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
882};
883
884static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
885 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
886};
887
888static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
889 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
890};
891
892static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
893 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
894};
895
896static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
897 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
898};
899
900static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
901 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
902};
903
904static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
905 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
906};
907
908static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
909 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
910};
911
912static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
913 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
914};
915
916static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
917 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
918};
919
920static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
921 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
922};
923
924static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
925 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
926};
927
928static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
929 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
930};
931
932static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
933 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
934};
935
936static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
937 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
938};
939
940static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
941 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
942};
943
944static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
945 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
946};
947
948static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
949 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
950};
951
952static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
953 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
954};
955
956static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
957 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
958};
959
960static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
961 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
962};
963
964static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
965 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
966};
967
968static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
969 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
970};
971
972static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
973 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
974};
975
976static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
977 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
978};
979
980static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
981 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
982};
983
984static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
985 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
986};
987
988static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
989 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
990};
991
992static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
993 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
994};
995
996static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
997 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
998};
999
1000static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1001 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1002};
1003
1004static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1005 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1006};
1007
1008static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1009 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1010};
1011
1012static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1013 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1014};
1015
1016static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1017 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1018};
1019
1020static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1021 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1022};
1023
1024static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1025 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1026};
1027
1028static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1029 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1030};
1031
1032static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1033 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1034};
1035
1036static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1037 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1038};
1039
1040static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1041 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1042};
1043
1044static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1045 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1046};
1047
1048static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1049 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1050};
1051
1052static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1053 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1054};
1055
1056static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1057 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1058};
1059
1060static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1061 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1062};
1063
1064static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1065 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1066};
1067
1068static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1069 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1070};
1071
1072static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1073 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1074};
1075
1076static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1077 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1078};
1079
1080static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1081 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1082};
1083
1084static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1085 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1086};
1087
1088static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1089 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1090};
1091
1092static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1093 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1094};
1095
1096static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1097 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1098};
1099
1100static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1101 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1102};
1103
1104static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1105 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1106};
1107
1108static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1109 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1110};
1111
1112static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1113 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1114};
1115
1116static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1117 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1118};
1119
1120static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1121 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1122};
1123
1124static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1125 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1126};
1127
1128static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1129 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1130};
1131
1132static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1133 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1134};
1135
1136static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1137 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1138};
1139
1140static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1141 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1142};
1143
1144static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1145 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1146};
1147
1148static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1149 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1150};
1151
1152static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1153 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1154};
1155
1156static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1157 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1158};
1159
1160static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1161 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1162};
1163
1164static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1165 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1166};
1167
1168static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1169 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1170};
1171
1172static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1173 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1174};
1175
1176static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1177 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1178};
1179
1180static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1181 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1182};
1183
1184static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1185 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1186};
1187
1188static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1189 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1190};
1191
1192static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1193 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1194};
1195
1196static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1197 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1198};
1199
1200static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1201 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1202};
1203
1204static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1205 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1206};
1207
1208static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1209 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1210};
1211
1212static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1213 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1214};
1215
1216static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1217 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1218};
1219
1220static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1221 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1222};
1223
1224static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1225 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1226};
1227
1228static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1229 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1230};
1231
1232static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1233 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1234};
1235
1236static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1237 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1238};
1239
1240static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1241 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1242};
1243
1244static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1245 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1246};
1247
1248static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1249 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1250};
1251
1252static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1253 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1254};
1255
1256static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1257 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1258};
1259
1260static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1261 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1262};
1263
1264static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1265 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1266};
1267
1268static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1269 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1270};
1271
1272static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1273 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1274};
1275
1276static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1277 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1278};
1279
1280static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1281 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1282};
1283
1284static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1285 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1286};
1287
1288static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1289 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1290};
1291
1292static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1293 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1294};
1295
1296static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1297 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1298};
1299
1300static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1301 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1302};
1303
1304static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1305 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1306};
1307
1308static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1309 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1310};
1311
1312static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1313 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1314};
1315
1316static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1317 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1318};
1319
1320static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1321 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1322};
1323
1324static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1325 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1326};
1327
1328static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1329 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1330};
1331
1332static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1333 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1334};
1335
1336static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1337 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1338};
1339
1340static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1341 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1342};
1343
1344static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1345 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1346};
1347
1348static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1349 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1350};
1351
1352static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1353 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1354};
1355
1356static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1357 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1358};
1359
1360static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1361 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1362};
1363
1364static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1365 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1366};
1367
1368static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1369 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1370};
1371
1372static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1373 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1374};
1375
1376static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1377 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1378};
1379
1380static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1381 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1382};
1383
1384static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1385 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1386};
1387
1388static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1389 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1390};
1391
1392static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1393 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1394};
1395
1396static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1397 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1398};
1399
1400static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1401 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1402};
1403
1404static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1405 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1406};
1407
1408static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1409 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1410};
1411
1412static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1413 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1414};
1415
1416static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1417 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1418};
1419
1420static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1421 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1422};
1423
1424static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1425 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1426};
1427
1428static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1429 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1430};
1431
1432static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1433 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1434};
1435
1436static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1437 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1438};
1439
1440static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1441 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1442};
1443
1444static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1445 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1446};
1447
1448static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1449 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1450};
1451
1452static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1453 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1454};
1455
1456static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1457 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1458};
1459
1460static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1461 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1462};
1463
1464static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1465 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1466};
1467
1468static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1469 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1470};
1471
1472static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1473 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1474};
1475
1476static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1477 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1478};
1479
1480static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1481 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1482};
1483
1484static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1485 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1486};
1487
1488static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1489 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1490};
1491
1492static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1493 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1494};
1495
1496static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1497 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1498};
1499
1500static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1501 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1502};
1503
1504static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1505 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1506};
1507
1508static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1509 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1510};
1511
1512static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1513 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1514};
1515
1516static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1517 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1518};
1519
1520static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1521 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1522};
1523
1524static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1525 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1526};
1527
1528static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1529 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1530};
1531
1532static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1533 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1534};
1535
1536static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1537 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1538};
1539
1540static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1541 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1542};
1543
1544static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1545 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1546};
1547
1548static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1549 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1550};
1551
1552static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1553 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1554};
1555
1556static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1557 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1558};
1559
1560static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1561 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1562};
1563
1564static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1565 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1566};
1567
1568static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1569 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1570};
1571
1572static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1573 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1574};
1575
1576static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1577 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1578};
1579
1580static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1581 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1582};
1583
1584static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1585 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1586};
1587
1588static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1589 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1590};
1591
1592static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1593 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1594};
1595
1596static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1597 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1598};
1599
1600static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1601 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1602};
1603
1604static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1605 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1606};
1607
1608static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1609 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1610};
1611
1612static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1613 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1614};
1615
1616static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1617 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1618};
1619
1620static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1621 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1622};
1623
1624static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1625 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1626};
1627
1628static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1629 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1630};
1631
1632static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1633 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1634};
1635
1636static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1637 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1638};
1639
1640static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1641 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1642};
1643
1644static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1645 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1646};
1647
1648static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1649 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1650};
1651
1652static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1653 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1654};
1655
1656static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1657 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1658};
1659
1660static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1661 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1662};
1663
1664static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1665 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1666};
1667
1668static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1669 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1670};
1671
1672static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1673 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1674};
1675
1676static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1677 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1678};
1679
1680static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1681 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1682};
1683
1684static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1685 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1686};
1687
1688static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1689 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1690};
1691
1692static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1693 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1694};
1695
1696static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1697 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1698};
1699
1700static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1701 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1702};
1703
1704static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1705 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1706};
1707
1708static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1709 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1710};
1711
1712static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1713 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1714};
1715
1716static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1717 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1718};
1719
1720static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1721 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1722};
1723
1724static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1725 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1726};
1727
1728static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1729 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1730};
1731
1732static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1733 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1734};
1735
1736static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1737 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1738};
1739
1740static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1741 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1742};
1743
1744static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1745 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1746};
1747
1748static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1749 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1750};
1751
1752static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1753 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1754};
1755
1756static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1757 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1758};
1759
1760static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1761 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1762};
1763
1764static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1765 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1766};
1767
1768static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1769 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1770};
1771
1772static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1773 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1774};
1775
1776static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1777 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1778};
1779
1780static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1781 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1782};
1783
1784static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1785 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1786};
1787
1788static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1789 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1790};
1791
1792static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1793 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1794};
1795
1796static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1797 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1798};
1799
1800static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1801 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1802};
1803
1804static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1805 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1806};
1807
1808static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1809 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1810};
1811
1812static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1813 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1814};
1815
1816static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1817 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1818};
1819
1820static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1821 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1822};
1823
1824static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1825 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1826};
1827
1828static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1829 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1830};
1831
1832static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1833 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1834};
1835
1836static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1837 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1838};
1839
1840static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1841 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1842};
1843
1844static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1845 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1846};
1847
1848static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1849 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1850};
1851
1852static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1853 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1854};
1855
1856static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1857 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1858};
1859
1860static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1861 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1862};
1863
1864static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1865 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1866};
1867
1868static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1869 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1870};
1871
1872static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1873 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1874};
1875
1876static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1877 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1878};
1879
1880static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1881 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1882};
1883
1884static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1885 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1886};
1887
1888static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1889 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1890};
1891
1892static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1893 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1894};
1895
1896static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1897 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1898};
1899
1900static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1901 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1902};
1903
1904static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1905 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1906};
1907
1908static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1909 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1910};
1911
1912static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1913 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1914};
1915
1916static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1917 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1918};
1919
1920static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1921 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1922};
1923
1924static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1925 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1926};
1927
1928static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1929 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1930};
1931
1932static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1933 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1934};
1935
1936static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1937 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1938};
1939
1940static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1941 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1942};
1943
1944static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1945 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1946};
1947
1948static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1949 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1950};
1951
1952static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1953 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1954};
1955
1956static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1957 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1958};
1959
1960static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1961 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1962};
1963
1964static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1965 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1966};
1967
1968static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1969 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1970};
1971
1972static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1973 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1974};
1975
1976static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1977 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1978};
1979
1980static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1981 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1982};
1983
1984static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1985 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1986};
1987
1988static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1989 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1990};
1991
1992static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1993 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1994};
1995
1996static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1997 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1998};
1999
2000static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2001 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2002};
2003
2004static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2005 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2006};
2007
2008static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2009 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2010};
2011
2012static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2013 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2014};
2015
2016static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2017 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2018};
2019
2020static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2021 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2022};
2023
2024static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2025 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2026};
2027
2028static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2029 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2030};
2031
2032static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2033 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2034};
2035
2036static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2037 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2038};
2039
2040static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2041 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2042};
2043
2044static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2045 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2046};
2047
2048static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2049 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2050};
2051
2052static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2053 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2054};
2055
2056static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2057 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2058};
2059
2060static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2061 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2062};
2063
2064static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2065 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2066};
2067
2068static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2069 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2070};
2071
2072static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2073 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2074};
2075
2076static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2077 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2078};
2079
2080static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2081 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2082};
2083
2084static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2085 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2086};
2087
2088static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2089 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2090};
2091
2092static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2093 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2094};
2095
2096static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2097 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2098};
2099
2100static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2101 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2102};
2103
2104static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2105 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2106};
2107
2108static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2109 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2110};
2111
2112static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2113 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2114};
2115
2116static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2117 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2118};
2119
2120static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2121 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2122};
2123
2124static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2125 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2126};
2127
2128static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2129 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2130};
2131
2132static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2133 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2134};
2135
2136static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2137 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2138};
2139
2140static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2141 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2142};
2143
2144static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2145 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2146};
2147
2148static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2149 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2150};
2151
2152static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2153 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2154};
2155
2156static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2157 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2158};
2159
2160static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2161 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2162};
2163
2164static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2165 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2166};
2167
2168static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2169 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2170};
2171
2172static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2173 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2174};
2175
2176static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2177 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2178};
2179
2180static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2181 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2182};
2183
2184static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2185 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2186};
2187
2188static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2189 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2190};
2191
2192static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2193 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2194};
2195
2196static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2197 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2198};
2199
2200static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2201 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2202};
2203
2204static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2205 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2206};
2207
2208static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2209 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2210};
2211
2212static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2213 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2214};
2215
2216static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2217 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2218};
2219
2220static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2221 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2222};
2223
2224static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2225 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2226};
2227
2228static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2229 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2230};
2231
2232static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2233 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2234};
2235
2236static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2237 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2238};
2239
2240static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2241 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2242};
2243
2244static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2245 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2246};
2247
2248static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2249 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2250};
2251
2252static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2253 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2254};
2255
2256static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2257 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2258};
2259
2260static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2261 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2262};
2263
2264static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2265 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2266};
2267
2268static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2269 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2270};
2271
2272static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2273 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2274};
2275
2276static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2277 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2278};
2279
2280static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2281 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2282};
2283
2284static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2285 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2286};
2287
2288static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2289 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2290};
2291
2292static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2293 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2294};
2295
2296static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2297 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2298};
2299
2300static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2301 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2302};
2303
2304static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2305 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2306};
2307
2308static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2309 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2310};
2311
2312static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2313 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2314};
2315
2316static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2317 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2318};
2319
2320static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2321 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2322};
2323
2324static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2325 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2326};
2327
2328static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2329 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2330};
2331
2332static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2333 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2334};
2335
2336static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2337 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2338};
2339
2340static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2341 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2342};
2343
2344static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2345 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2346};
2347
2348static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2349 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2350};
2351
2352static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2353 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2354};
2355
2356static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2357 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2358};
2359
2360static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2361 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2362};
2363
2364static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2365 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2366};
2367
2368static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2369 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2370};
2371
2372static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2373 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2374};
2375
2376static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2377 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2378};
2379
2380static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2381 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2382};
2383
2384static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2385 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2386};
2387
2388static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2389 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2390};
2391
2392static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2393 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2394};
2395
2396static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2397 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2398};
2399
2400static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2401 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2402};
2403
2404static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2405 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2406};
2407
2408static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2409 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2410};
2411
2412static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2413 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2414};
2415
2416static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2417 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2418};
2419
2420static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2421 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2422};
2423
2424static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2425 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2426};
2427
2428static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2429 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2430};
2431
2432static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2433 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2434};
2435
2436static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2437 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2438};
2439
2440static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2441 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2442};
2443
2444static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2445 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2446};
2447
2448static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2449 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2450};
2451
2452static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2453 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2454};
2455
2456static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2457 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2458};
2459
2460static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2461 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2462};
2463
2464static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2465 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2466};
2467
2468static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2469 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2470};
2471
2472static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2473 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2474};
2475
2476static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2477 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2478};
2479
2480static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2481 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2482};
2483
2484static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2485 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2486};
2487
2488static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2489 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2490};
2491
2492static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2493 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2494};
2495
2496static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2497 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2498};
2499
2500static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2501 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2502};
2503
2504static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2505 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2506};
2507
2508static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2509 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2510};
2511
2512static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2513 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2514};
2515
2516static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2517 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2518};
2519
2520static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2521 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2522};
2523
2524static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2525 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2526};
2527
2528static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2529 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2530};
2531
2532static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2533 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2534};
2535
2536static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2537 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2538};
2539
2540static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
2541 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2542};
2543
2544static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2545 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2546};
2547
2548static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2549 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2550};
2551
2552static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2553 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2554};
2555
2556static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2557 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2558};
2559
2560static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2561 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2562};
2563
2564static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2565 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2566};
2567
2568static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2569 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2570};
2571
2572static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2573 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2574};
2575
2576static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2577 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2578};
2579
2580static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2581 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2582};
2583
2584static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2585 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2586};
2587
2588static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
2589 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2590};
2591
2592static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2593 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2594};
2595
2596static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2597 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2598};
2599
2600static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2601 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2602};
2603
2604static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2605 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2606};
2607
2608static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2609 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2610};
2611
2612static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2613 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2614};
2615
2616static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2617 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2618};
2619
2620static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2621 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2622};
2623
2624static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2625 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2626};
2627
2628static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2629 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2630};
2631
2632static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2633 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2634};
2635
2636static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2637 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2638};
2639
2640static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2641 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2642};
2643
2644static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2645 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2646};
2647
2648static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2649 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2650};
2651
2652static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2653 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2654};
2655
2656static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2657 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2658};
2659
2660static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2661 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2662};
2663
2664static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2665 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2666};
2667
2668static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2669 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2670};
2671
2672static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2673 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2674};
2675
2676static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2677 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2678};
2679
2680static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2681 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2682};
2683
2684static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2685 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2686};
2687
2688static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2689 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2690};
2691
2692static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2693 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2694};
2695
2696static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2697 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2698};
2699
2700static const CGEN_IFMT ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2701 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2702};
2703
2704static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2705 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2706};
2707
2708static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
2709 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2710};
2711
2712static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2713 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2714};
2715
2716static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2717 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2718};
2719
2720static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2721 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2722};
2723
2724static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2725 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2726};
2727
2728static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2729 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2730};
2731
2732static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2733 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2734};
2735
2736static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2737 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2738};
2739
2740static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2741 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2742};
2743
2744static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2745 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2746};
2747
2748static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2749 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2750};
2751
2752static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2753 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2754};
2755
2756static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
2757 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2758};
2759
2760static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2761 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2762};
2763
2764static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2765 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2766};
2767
2768static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2769 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2770};
2771
2772static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2773 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2774};
2775
2776static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2777 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2778};
2779
2780static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2781 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2782};
2783
2784static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2785 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2786};
2787
2788static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2789 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2790};
2791
2792static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2793 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2794};
2795
2796static const CGEN_IFMT ifmt_xchg16w_r3_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2797 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2798};
2799
2800static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2801 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2802};
2803
2804static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2805 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2806};
2807
2808static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2809 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2810};
2811
2812static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2813 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2814};
2815
2816static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2817 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2818};
2819
2820static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2821 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2822};
2823
2824static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2825 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2826};
2827
2828static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2829 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2830};
2831
a1a280bb 2832static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2833 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2834};
2835
a1a280bb 2836static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2837 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2838};
2839
a1a280bb 2840static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2841 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2842};
2843
a1a280bb 2844static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2845 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2846};
2847
a1a280bb 2848static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2849 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2850};
2851
a1a280bb 2852static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2853 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2854};
2855
a1a280bb 2856static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2857 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2858};
2859
a1a280bb 2860static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2861 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2862};
2863
a1a280bb 2864static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 2865 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2866};
2867
2868static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2869 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } }
2870};
2871
2872static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2873 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } }
2874};
2875
2876static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
2877 32, 40, 0xff000000, { { F (F_0_2) }, { F (F_DSP_24_S16) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2878};
2879
2880static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
2881 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S16) }, { 0 } }
2882};
2883
2884static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2885 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } }
2886};
2887
2888static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2889 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } }
2890};
2891
2892static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
2893 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_24_S8) }, { 0 } }
2894};
2895
2896static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
2897 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S8) }, { 0 } }
2898};
2899
2900static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2901 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2902};
2903
2904static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2905 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2906};
2907
2908static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2909 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2910};
2911
2912static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2913 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2914};
2915
2916static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2917 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2918};
2919
2920static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2921 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2922};
2923
2924static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2925 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2926};
2927
2928static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2929 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2930};
2931
2932static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2933 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2934};
2935
2936static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2937 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2938};
2939
2940static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2941 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2942};
2943
2944static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2945 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2946};
2947
2948static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2949 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2950};
2951
2952static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2953 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2954};
2955
2956static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2957 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2958};
2959
2960static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2961 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2962};
2963
2964static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2965 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2966};
2967
2968static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2969 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2970};
2971
2972static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2973 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2974};
2975
2976static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2977 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2978};
2979
2980static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2981 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2982};
2983
2984static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2985 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2986};
2987
2988static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2989 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2990};
2991
2992static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2993 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2994};
2995
2996static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2997 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2998};
2999
3000static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3001 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3002};
3003
3004static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3005 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3006};
3007
3008static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3009 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3010};
3011
3012static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3013 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3014};
3015
3016static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3017 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3018};
3019
3020static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3021 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3022};
3023
3024static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3025 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3026};
3027
3028static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3029 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3030};
3031
3032static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3033 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3034};
3035
3036static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3037 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3038};
3039
3040static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3041 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3042};
3043
3044static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3045 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3046};
3047
3048static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3049 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3050};
3051
3052static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3053 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3054};
3055
3056static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3057 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3058};
3059
3060static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3061 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3062};
3063
3064static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3065 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3066};
3067
3068static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3069 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3070};
3071
3072static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3073 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3074};
3075
3076static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3077 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3078};
3079
3080static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3081 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3082};
3083
3084static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3085 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3086};
3087
3088static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3089 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3090};
3091
3092static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3093 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3094};
3095
3096static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3097 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3098};
3099
3100static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3101 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3102};
3103
3104static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3105 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3106};
3107
3108static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3109 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3110};
3111
3112static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3113 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3114};
3115
3116static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3117 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3118};
3119
3120static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3121 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3122};
3123
3124static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3125 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3126};
3127
3128static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3129 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3130};
3131
3132static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3133 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3134};
3135
3136static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3137 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3138};
3139
3140static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3141 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3142};
3143
3144static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3145 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3146};
3147
3148static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3149 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3150};
3151
3152static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3153 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3154};
3155
3156static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3157 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3158};
3159
3160static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3161 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3162};
3163
3164static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3165 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3166};
3167
3168static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3169 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3170};
3171
3172static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3173 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3174};
3175
3176static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3177 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3178};
3179
3180static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3181 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3182};
3183
3184static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3185 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3186};
3187
3188static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3189 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3190};
3191
3192static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3193 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3194};
3195
3196static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3197 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3198};
3199
3200static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3201 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3202};
3203
3204static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3205 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3206};
3207
3208static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3209 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3210};
3211
3212static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3213 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3214};
3215
3216static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3217 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3218};
3219
3220static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3221 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3222};
3223
3224static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3225 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3226};
3227
3228static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3229 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3230};
3231
3232static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3233 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3234};
3235
3236static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3237 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3238};
3239
3240static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3241 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3242};
3243
3244static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3245 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3246};
3247
3248static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3249 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3250};
3251
3252static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3253 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3254};
3255
3256static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3257 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3258};
3259
3260static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3261 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3262};
3263
3264static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3265 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3266};
3267
3268static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3269 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3270};
3271
3272static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3273 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3274};
3275
3276static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3277 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3278};
3279
3280static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3281 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3282};
3283
3284static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3285 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3286};
3287
3288static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3289 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3290};
3291
3292static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3293 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3294};
3295
3296static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3297 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3298};
3299
3300static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3301 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3302};
3303
3304static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3305 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3306};
3307
3308static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3309 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3310};
3311
3312static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3313 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3314};
3315
3316static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3317 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3318};
3319
3320static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3321 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3322};
3323
3324static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3325 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3326};
3327
3328static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3329 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3330};
3331
3332static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3333 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3334};
3335
3336static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3337 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3338};
3339
3340static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3341 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3342};
3343
3344static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3345 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3346};
3347
3348static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3349 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3350};
3351
3352static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3353 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3354};
3355
3356static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3357 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3358};
3359
3360static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3361 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3362};
3363
3364static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3365 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3366};
3367
3368static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3369 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3370};
3371
3372static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3373 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3374};
3375
3376static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3377 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3378};
3379
3380static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3381 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3382};
3383
3384static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3385 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3386};
3387
3388static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3389 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3390};
3391
3392static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3393 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3394};
3395
3396static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3397 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3398};
3399
3400static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3401 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3402};
3403
3404static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3405 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3406};
3407
3408static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3409 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3410};
3411
3412static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3413 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3414};
3415
3416static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3417 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3418};
3419
3420static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3421 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3422};
3423
3424static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3425 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3426};
3427
3428static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3429 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3430};
3431
3432static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3433 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3434};
3435
3436static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3437 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3438};
3439
3440static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3441 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3442};
3443
3444static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3445 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3446};
3447
3448static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3449 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3450};
3451
3452static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3453 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3454};
3455
3456static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3457 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3458};
3459
3460static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3461 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3462};
3463
3464static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3465 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3466};
3467
3468static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3469 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3470};
3471
3472static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3473 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3474};
3475
3476static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3477 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3478};
3479
3480static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3481 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3482};
3483
3484static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3485 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3486};
3487
3488static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3489 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3490};
3491
3492static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3493 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3494};
3495
3496static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3497 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3498};
3499
3500static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3501 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3502};
3503
3504static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3505 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3506};
3507
3508static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3509 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3510};
3511
3512static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3513 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3514};
3515
3516static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3517 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3518};
3519
3520static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3521 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3522};
3523
3524static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3525 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3526};
3527
3528static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3529 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3530};
3531
3532static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3533 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3534};
3535
3536static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3537 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3538};
3539
3540static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3541 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3542};
3543
3544static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3545 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3546};
3547
3548static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3549 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3550};
3551
3552static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3553 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3554};
3555
3556static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3557 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3558};
3559
3560static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3561 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3562};
3563
3564static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3565 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3566};
3567
3568static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3569 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3570};
3571
3572static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3573 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3574};
3575
3576static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3577 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3578};
3579
3580static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3581 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3582};
3583
3584static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3585 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3586};
3587
3588static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3589 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3590};
3591
3592static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3593 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3594};
3595
3596static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3597 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3598};
3599
3600static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3601 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3602};
3603
3604static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3605 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3606};
3607
3608static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3609 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3610};
3611
3612static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3613 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3614};
3615
3616static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3617 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3618};
3619
3620static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3621 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3622};
3623
3624static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3625 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3626};
3627
3628static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3629 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3630};
3631
3632static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3633 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3634};
3635
3636static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3637 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3638};
3639
3640static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3641 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3642};
3643
3644static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3645 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3646};
3647
3648static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3649 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3650};
3651
3652static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3653 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3654};
3655
3656static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3657 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3658};
3659
3660static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3661 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3662};
3663
3664static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3665 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3666};
3667
3668static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3669 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3670};
3671
3672static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3673 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3674};
3675
3676static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3677 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3678};
3679
3680static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3681 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3682};
3683
3684static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3685 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3686};
3687
3688static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3689 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3690};
3691
3692static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3693 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3694};
3695
3696static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3697 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3698};
3699
3700static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3701 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3702};
3703
3704static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3705 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3706};
3707
3708static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3709 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3710};
3711
3712static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3713 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3714};
3715
3716static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3717 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3718};
3719
3720static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3721 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3722};
3723
3724static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3725 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3726};
3727
3728static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3729 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3730};
3731
3732static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3733 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3734};
3735
3736static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3737 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3738};
3739
3740static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3741 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3742};
3743
3744static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3745 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3746};
3747
3748static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3749 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3750};
3751
3752static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3753 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3754};
3755
3756static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3757 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3758};
3759
3760static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3761 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3762};
3763
3764static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3765 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3766};
3767
3768static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3769 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3770};
3771
3772static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3773 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3774};
3775
3776static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3777 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3778};
3779
3780static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3781 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3782};
3783
3784static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3785 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3786};
3787
3788static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3789 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3790};
3791
3792static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3793 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3794};
3795
3796static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3797 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3798};
3799
3800static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3801 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3802};
3803
3804static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3805 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3806};
3807
3808static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3809 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3810};
3811
3812static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3813 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3814};
3815
3816static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3817 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3818};
3819
3820static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3821 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3822};
3823
3824static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3825 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3826};
3827
3828static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3829 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3830};
3831
3832static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3833 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3834};
3835
3836static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3837 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3838};
3839
3840static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3841 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3842};
3843
3844static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3845 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3846};
3847
3848static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3849 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3850};
3851
3852static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3853 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3854};
3855
3856static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3857 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3858};
3859
3860static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3861 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3862};
3863
3864static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3865 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3866};
3867
3868static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3869 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3870};
3871
3872static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3873 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3874};
3875
3876static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3877 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3878};
3879
3880static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3881 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3882};
3883
3884static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3885 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3886};
3887
3888static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3889 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3890};
3891
3892static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3893 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3894};
3895
3896static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3897 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3898};
3899
3900static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3901 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3902};
3903
3904static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3905 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3906};
3907
3908static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3909 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3910};
3911
3912static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3913 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3914};
3915
3916static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3917 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3918};
3919
3920static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3921 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3922};
3923
3924static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3925 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3926};
3927
3928static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3929 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3930};
3931
3932static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3933 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3934};
3935
3936static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3937 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3938};
3939
3940static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3941 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3942};
3943
3944static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3945 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3946};
3947
3948static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3949 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3950};
3951
3952static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3953 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3954};
3955
3956static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3957 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3958};
3959
3960static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3961 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3962};
3963
3964static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3965 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3966};
3967
3968static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3969 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3970};
3971
3972static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3973 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3974};
3975
3976static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3977 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3978};
3979
3980static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3981 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3982};
3983
3984static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3985 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3986};
3987
3988static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3989 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3990};
3991
3992static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3993 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3994};
3995
3996static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3997 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3998};
3999
4000static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4001 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4002};
4003
4004static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4005 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4006};
4007
4008static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4009 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4010};
4011
4012static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4013 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4014};
4015
4016static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4017 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4018};
4019
4020static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4021 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4022};
4023
4024static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4025 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4026};
4027
4028static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4029 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4030};
4031
4032static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4033 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4034};
4035
4036static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4037 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4038};
4039
4040static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4041 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4042};
4043
4044static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4045 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4046};
4047
4048static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4049 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4050};
4051
4052static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4053 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4054};
4055
4056static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4057 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4058};
4059
4060static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4061 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4062};
4063
4064static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4065 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4066};
4067
4068static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4069 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4070};
4071
4072static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4073 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4074};
4075
4076static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4077 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4078};
4079
4080static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4081 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4082};
4083
4084static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4085 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4086};
4087
4088static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4089 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4090};
4091
4092static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4093 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4094};
4095
4096static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4097 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4098};
4099
4100static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4101 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4102};
4103
4104static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4105 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4106};
4107
4108static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4109 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4110};
4111
4112static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4113 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4114};
4115
4116static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4117 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4118};
4119
4120static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4121 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4122};
4123
4124static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4125 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4126};
4127
4128static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4129 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4130};
4131
4132static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4133 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4134};
4135
4136static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4137 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4138};
4139
4140static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4141 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4142};
4143
4144static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4145 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4146};
4147
4148static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4149 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4150};
4151
4152static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4153 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4154};
4155
4156static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4157 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4158};
4159
4160static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4161 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4162};
4163
4164static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4165 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4166};
4167
4168static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4169 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4170};
4171
4172static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4173 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4174};
4175
4176static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4177 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4178};
4179
4180static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4181 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4182};
4183
4184static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4185 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4186};
4187
4188static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4189 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4190};
4191
4192static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4193 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4194};
4195
4196static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4197 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4198};
4199
4200static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4201 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4202};
4203
4204static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4205 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4206};
4207
4208static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4209 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4210};
4211
4212static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4213 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4214};
4215
4216static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4217 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4218};
4219
4220static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4221 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4222};
4223
4224static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4225 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4226};
4227
4228static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4229 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4230};
4231
4232static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4233 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4234};
4235
4236static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4237 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4238};
4239
4240static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4241 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4242};
4243
4244static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4245 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4246};
4247
4248static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4249 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4250};
4251
4252static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4253 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4254};
4255
4256static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4257 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4258};
4259
4260static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4261 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4262};
4263
4264static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4265 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4266};
4267
4268static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4269 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4270};
4271
4272static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4273 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4274};
4275
4276static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4277 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4278};
4279
4280static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4281 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4282};
4283
4284static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4285 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4286};
4287
4288static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4289 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4290};
4291
4292static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4293 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4294};
4295
4296static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4297 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4298};
4299
4300static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4301 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4302};
4303
4304static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4305 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4306};
4307
4308static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4309 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4310};
4311
4312static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4313 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4314};
4315
4316static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4317 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4318};
4319
4320static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4321 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4322};
4323
4324static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4325 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4326};
4327
4328static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4329 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4330};
4331
4332static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4333 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4334};
4335
4336static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4337 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4338};
4339
4340static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4341 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4342};
4343
4344static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4345 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4346};
4347
4348static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4349 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4350};
4351
4352static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4353 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4354};
4355
4356static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4357 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4358};
4359
4360static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4361 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4362};
4363
4364static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4365 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4366};
4367
4368static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4369 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4370};
4371
4372static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4373 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4374};
4375
4376static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4377 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4378};
4379
4380static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4381 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4382};
4383
4384static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4385 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4386};
4387
4388static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4389 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4390};
4391
4392static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4393 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4394};
4395
4396static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4397 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4398};
4399
4400static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4401 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4402};
4403
4404static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4405 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4406};
4407
4408static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4409 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4410};
4411
4412static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4413 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4414};
4415
4416static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4417 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4418};
4419
4420static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4421 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4422};
4423
4424static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4425 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4426};
4427
4428static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4429 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4430};
4431
4432static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4433 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4434};
4435
4436static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4437 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4438};
4439
4440static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4441 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4442};
4443
4444static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4445 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4446};
4447
4448static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4449 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4450};
4451
4452static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4453 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4454};
4455
4456static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4457 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4458};
4459
4460static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4461 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4462};
4463
4464static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4465 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4466};
4467
4468static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4469 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4470};
4471
4472static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4473 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4474};
4475
4476static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4477 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4478};
4479
4480static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4481 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4482};
4483
4484static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4485 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4486};
4487
4488static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4489 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4490};
4491
4492static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4493 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4494};
4495
4496static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4497 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4498};
4499
4500static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4501 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4502};
4503
4504static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4505 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4506};
4507
4508static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4509 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4510};
4511
4512static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4513 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4514};
4515
4516static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4517 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4518};
4519
4520static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4521 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4522};
4523
4524static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4525 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4526};
4527
4528static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4529 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4530};
4531
4532static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4533 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4534};
4535
4536static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4537 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4538};
4539
4540static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4541 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4542};
4543
4544static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4545 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4546};
4547
4548static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4549 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4550};
4551
4552static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4553 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4554};
4555
4556static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4557 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4558};
4559
4560static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4561 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4562};
4563
4564static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4565 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4566};
4567
4568static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4569 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4570};
4571
4572static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4573 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4574};
4575
4576static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4577 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4578};
4579
4580static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4581 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4582};
4583
4584static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4585 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4586};
4587
4588static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4589 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4590};
4591
4592static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4593 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4594};
4595
4596static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4597 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4598};
4599
4600static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4601 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4602};
4603
4604static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4605 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4606};
4607
4608static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4609 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4610};
4611
4612static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4613 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4614};
4615
4616static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4617 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4618};
4619
4620static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4621 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4622};
4623
4624static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4625 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4626};
4627
4628static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4629 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4630};
4631
4632static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4633 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4634};
4635
4636static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4637 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4638};
4639
4640static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4641 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4642};
4643
4644static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4645 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4646};
4647
4648static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4649 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4650};
4651
4652static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4653 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4654};
4655
4656static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4657 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4658};
4659
4660static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4661 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4662};
4663
4664static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4665 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4666};
4667
4668static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4669 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4670};
4671
4672static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4673 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4674};
4675
4676static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4677 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4678};
4679
4680static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4681 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4682};
4683
4684static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
4685 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4686};
4687
4688static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4689 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4690};
4691
4692static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4693 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4694};
4695
4696static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4697 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4698};
4699
4700static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4701 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4702};
4703
4704static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4705 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4706};
4707
4708static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4709 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4710};
4711
4712static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4713 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4714};
4715
4716static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4717 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4718};
4719
4720static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4721 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4722};
4723
4724static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4725 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4726};
4727
4728static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4729 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4730};
4731
4732static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
4733 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4734};
4735
4736static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4737 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4738};
4739
4740static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4741 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4742};
4743
4744static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4745 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4746};
4747
4748static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4749 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4750};
4751
4752static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4753 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4754};
4755
4756static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4757 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4758};
4759
4760static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4761 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4762};
4763
4764static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4765 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } }
4766};
4767
4768static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4769 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } }
4770};
4771
4772static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
4773 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4774};
4775
4776static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
4777 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4778};
4779
4780static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
4781 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4782};
4783
4784static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
4785 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_S8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4786};
4787
4788static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI ATTRIBUTE_UNUSED = {
4789 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U16) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4790};
4791
4792static const CGEN_IFMT ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4793 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4794};
4795
4796static const CGEN_IFMT ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4797 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4798};
4799
4800static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4801 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4802};
4803
4804static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4805 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4806};
4807
4808static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4809 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4810};
4811
4812static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4813 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4814};
4815
4816static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4817 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4818};
4819
4820static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4821 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4822};
4823
4824static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4825 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4826};
4827
4828static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4829 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4830};
4831
4832static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4833 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4834};
4835
4836static const CGEN_IFMT ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4837 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4838};
4839
4840static const CGEN_IFMT ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
4841 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4842};
4843
4844static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4845 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4846};
4847
4848static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4849 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4850};
4851
4852static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4853 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4854};
4855
4856static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4857 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4858};
4859
4860static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4861 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4862};
4863
4864static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4865 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4866};
4867
4868static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4869 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4870};
4871
4872static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4873 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4874};
4875
4876static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4877 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4878};
4879
4880static const CGEN_IFMT ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4881 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4882};
4883
4884static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4885 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4886};
4887
4888static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
4889 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4890};
4891
4892static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4893 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4894};
4895
4896static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4897 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4898};
4899
4900static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4901 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4902};
4903
4904static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4905 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4906};
4907
4908static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4909 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4910};
4911
4912static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4913 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4914};
4915
4916static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4917 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4918};
4919
4920static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4921 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4922};
4923
4924static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4925 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4926};
4927
4928static const CGEN_IFMT ifmt_shl16_w_dst_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
4929 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4930};
4931
4932static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
4933 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4934};
4935
4936static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
4937 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4938};
4939
4940static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
4941 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4942};
4943
4944static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
4945 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4946};
4947
4948static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
4949 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4950};
4951
4952static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
4953 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4954};
4955
4956static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
4957 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4958};
4959
4960static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
4961 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4962};
4963
4964static const CGEN_IFMT ifmt_shl16_b_dst_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
4965 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4966};
4967
4968static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
4969 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4970};
4971
4972static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
4973 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4974};
4975
4976static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
4977 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4978};
4979
4980static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
4981 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4982};
4983
4984static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
4985 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4986};
4987
4988static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
4989 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4990};
4991
4992static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
4993 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4994};
4995
4996static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
4997 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4998};
4999
5000static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5001 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5002};
5003
5004static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5005 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5006};
5007
5008static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5009 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5010};
5011
5012static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5013 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5014};
5015
5016static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5017 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5018};
5019
5020static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5021 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5022};
5023
5024static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5025 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5026};
5027
5028static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5029 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5030};
5031
5032static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5033 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5034};
5035
5036static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5037 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5038};
5039
5040static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5041 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5042};
5043
5044static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5045 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5046};
5047
5048static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5049 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5050};
5051
5052static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5053 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5054};
5055
5056static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
5057 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5058};
5059
5060static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5061 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5062};
5063
5064static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5065 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5066};
5067
5068static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5069 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5070};
5071
5072static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5073 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5074};
5075
5076static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5077 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5078};
5079
5080static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5081 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5082};
5083
5084static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5085 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5086};
5087
5088static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5089 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5090};
5091
5092static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5093 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5094};
5095
5096static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5097 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5098};
5099
5100static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5101 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5102};
5103
5104static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5105 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5106};
5107
5108static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5109 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5110};
5111
5112static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5113 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5114};
5115
5116static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5117 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5118};
5119
5120static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5121 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5122};
5123
5124static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5125 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5126};
5127
5128static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5129 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5130};
5131
5132static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5133 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5134};
5135
5136static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5137 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5138};
5139
5140static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5141 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5142};
5143
5144static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5145 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5146};
5147
5148static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5149 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5150};
5151
5152static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5153 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5154};
5155
5156static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5157 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5158};
5159
5160static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5161 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5162};
5163
5164static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5165 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5166};
5167
5168static const CGEN_IFMT ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5169 16, 16, 0xff30, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5170};
5171
5172static const CGEN_IFMT ifmt_sccnd_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5173 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5174};
5175
5176static const CGEN_IFMT ifmt_sccnd_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5177 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5178};
5179
5180static const CGEN_IFMT ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5181 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5182};
5183
5184static const CGEN_IFMT ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5185 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5186};
5187
5188static const CGEN_IFMT ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5189 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5190};
5191
5192static const CGEN_IFMT ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5193 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5194};
5195
5196static const CGEN_IFMT ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5197 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5198};
5199
5200static const CGEN_IFMT ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5201 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5202};
5203
5204static const CGEN_IFMT ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5205 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5206};
5207
5208static const CGEN_IFMT ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5209 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5210};
5211
5212static const CGEN_IFMT ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5213 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5214};
5215
5216static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5217 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5218};
5219
5220static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5221 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5222};
5223
5224static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5225 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5226};
5227
5228static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5229 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5230};
5231
5232static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5233 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5234};
5235
5236static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5237 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5238};
5239
5240static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5241 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5242};
5243
5244static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5245 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5246};
5247
5248static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5249 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5250};
5251
5252static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5253 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5254};
5255
5256static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5257 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5258};
5259
5260static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5261 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5262};
5263
5264static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5265 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5266};
5267
5268static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5269 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5270};
5271
5272static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5273 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5274};
5275
5276static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5277 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5278};
5279
5280static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5281 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5282};
5283
5284static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5285 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5286};
5287
5288static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5289 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5290};
5291
5292static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5293 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5294};
5295
5296static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5297 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5298};
5299
5300static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5301 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5302};
5303
5304static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5305 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5306};
5307
5308static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
5309 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5310};
5311
5312static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 5313 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
49f58d10
JB		 5314};
5315
5316static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 5317 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
49f58d10
JB		 5318};
5319
5320static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 5321 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
49f58d10
JB		 5322};
5323
5324static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 5325 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
49f58d10
JB		 5326};
5327
5328static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 5329 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
49f58d10
JB		 5330};
5331
5332static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
144f4bc6 5333 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
49f58d10
JB		 5334};
5335
5336static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5337 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5338};
5339
5340static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5341 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5342};
5343
5344static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5345 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5346};
5347
5348static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 5349 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
49f58d10
JB		 5350};
5351
5352static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 5353 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
49f58d10
JB		 5354};
5355
5356static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 5357 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
49f58d10
JB		 5358};
5359
5360static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 5361 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
49f58d10
JB		 5362};
5363
5364static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 5365 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
49f58d10
JB		 5366};
5367
5368static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
144f4bc6 5369 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
49f58d10
JB		 5370};
5371
5372static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5373 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5374};
5375
5376static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5377 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5378};
5379
5380static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5381 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5382};
5383
5384static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
5385 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5386};
5387
5388static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
5389 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5390};
5391
5392static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
5393 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5394};
5395
5396static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5397 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5398};
5399
5400static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5401 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5402};
5403
5404static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5405 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5406};
5407
5408static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5409 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5410};
5411
5412static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5413 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5414};
5415
5416static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5417 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5418};
5419
5420static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
5421 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5422};
5423
5424static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5425 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5426};
5427
5428static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
5429 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5430};
5431
5432static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5433 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5434};
5435
5436static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5437 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5438};
5439
5440static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
5441 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5442};
5443
5444static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5445 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5446};
5447
5448static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5449 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5450};
5451
5452static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5453 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5454};
5455
5456static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5457 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5458};
5459
5460static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5461 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5462};
5463
5464static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5465 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5466};
5467
5468static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5469 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5470};
5471
5472static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5473 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5474};
5475
5476static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5477 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5478};
5479
5480static const CGEN_IFMT ifmt_rorc16_w_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5481 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5482};
5483
5484static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5485 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5486};
5487
5488static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5489 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5490};
5491
5492static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5493 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5494};
5495
5496static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5497 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5498};
5499
5500static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5501 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5502};
5503
5504static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5505 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5506};
5507
5508static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5509 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5510};
5511
5512static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5513 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5514};
5515
5516static const CGEN_IFMT ifmt_rorc16_b_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5517 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5518};
5519
5520static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5521 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5522};
5523
5524static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5525 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5526};
5527
5528static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5529 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5530};
5531
5532static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5533 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5534};
5535
5536static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5537 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5538};
5539
5540static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5541 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5542};
5543
5544static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5545 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5546};
5547
5548static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5549 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5550};
5551
5552static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5553 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5554};
5555
5556static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5557 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5558};
5559
5560static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5561 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5562};
5563
5564static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5565 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5566};
5567
5568static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5569 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5570};
5571
5572static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5573 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5574};
5575
5576static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5577 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5578};
5579
5580static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5581 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5582};
5583
5584static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5585 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5586};
5587
5588static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5589 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5590};
5591
5592static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI ATTRIBUTE_UNUSED = {
5593 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5594};
5595
5596static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI ATTRIBUTE_UNUSED = {
5597 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5598};
5599
5600static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI ATTRIBUTE_UNUSED = {
5601 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5602};
5603
5604static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5605 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5606};
5607
5608static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5609 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5610};
5611
5612static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5613 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5614};
5615
5616static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI ATTRIBUTE_UNUSED = {
5617 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5618};
5619
5620static const CGEN_IFMT ifmt_push16_b_s_an_An16_push_S_derived ATTRIBUTE_UNUSED = {
5621 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } }
5622};
5623
5624static const CGEN_IFMT ifmt_push16_b_s_rn_Rn16_push_S_derived ATTRIBUTE_UNUSED = {
5625 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } }
5626};
5627
5348b81e
DD		 5628static const CGEN_IFMT ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived ATTRIBUTE_UNUSED = {
5629 8, 8, 0xfb, { { F (F_0_4) }, { F (F_6_2) }, { F (F_5_1) }, { F (F_4_1) }, { 0 } }
5630};
5631
5632static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5633 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5634};
5635
5636static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5637 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5638};
5639
5640static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
5641 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5642};
5643
c6552317
DD		 5644static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
5645 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
5646};
5647
5648static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
5649 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
5650};
5651
5652static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5653 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { 0 } }
5654};
5655
5656static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5657 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { 0 } }
5658};
5659
5660static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI ATTRIBUTE_UNUSED = {
5661 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { 0 } }
5662};
5663
49f58d10
JB		 5664static const CGEN_IFMT ifmt_mulex_dst32_R3_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5665 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5666};
5667
253d272c
DD		 5668static const CGEN_IFMT ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
5669 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5670};
5671
5672static const CGEN_IFMT ifmt_mulu_l_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
5673 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5674};
5675
5676static const CGEN_IFMT ifmt_mulu_l_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = {
5677 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5678};
5679
5680static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5681 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5682};
5683
5684static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5685 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5686};
5687
5688static const CGEN_IFMT ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5689 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5690};
5691
5692static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5693 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5694};
5695
5696static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5697 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5698};
5699
5700static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5701 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5702};
5703
5704static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5705 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5706};
5707
5708static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
5709 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5710};
5711
5712static const CGEN_IFMT ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
5713 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5714};
5715
49f58d10
JB		 5716static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5717 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5718};
5719
5720static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5721 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5722};
5723
5724static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
5725 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5726};
5727
5728static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5729 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5730};
5731
5732static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5733 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5734};
5735
5736static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5737 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5738};
5739
5740static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5741 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5742};
5743
5744static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5745 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5746};
5747
5748static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5749 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5750};
5751
5752static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5753 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5754};
5755
5756static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5757 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5758};
5759
5760static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5761 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5762};
5763
5764static const CGEN_IFMT ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5765 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5766};
5767
5768static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5769 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5770};
5771
5772static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5773 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5774};
5775
5776static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5777 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5778};
5779
5780static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5781 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5782};
5783
5784static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5785 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5786};
5787
5788static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5789 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5790};
5791
5792static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5793 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5794};
5795
5796static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5797 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5798};
5799
5800static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5801 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5802};
5803
5804static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5805 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5806};
5807
5808static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5809 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5810};
5811
5812static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5813 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5814};
5815
5816static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5817 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5818};
5819
5820static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5821 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5822};
5823
5824static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5825 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5826};
5827
5828static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5829 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5830};
5831
5832static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5833 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5834};
5835
5836static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5837 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5838};
5839
5840static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5841 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5842};
5843
5844static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5845 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5846};
5847
5848static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5849 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5850};
5851
5852static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5853 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5854};
5855
5856static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5857 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5858};
5859
5860static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5861 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5862};
5863
5864static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5865 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5866};
5867
5868static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5869 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5870};
5871
5872static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5873 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5874};
5875
5876static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5877 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5878};
5879
5880static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5881 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5882};
5883
5884static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5885 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
49f58d10
JB		 5886};
5887
5888static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5889 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5890};
5891
5892static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5893 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5894};
5895
5896static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5897 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5898};
5899
5900static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5901 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5902};
5903
5904static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5905 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5906};
5907
5908static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5909 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5910};
5911
5912static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5913 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5914};
5915
5916static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5917 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5918};
5919
5920static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5921 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5922};
5923
5924static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5925 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5926};
5927
5928static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5929 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5930};
5931
5932static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
f75eb1c0 5933 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5934};
5935
5936static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5937 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5938};
5939
5940static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5941 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5942};
5943
5944static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5945 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
49f58d10
JB		 5946};
5947
5948static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5949 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5950};
5951
5952static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5953 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5954};
5955
5956static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5957 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 5958};
5959
5960static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5961 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5962};
5963
5964static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5965 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5966};
5967
5968static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
f75eb1c0 5969 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
49f58d10
JB		 5970};
5971
5972static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI ATTRIBUTE_UNUSED = {
5973 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5974};
5975
5976static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI ATTRIBUTE_UNUSED = {
5977 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5978};
5979
5980static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI ATTRIBUTE_UNUSED = {
5981 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5982};
5983
5984static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5985 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5986};
5987
5988static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5989 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5990};
5991
5992static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5993 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5994};
5995
5996static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5997 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5998};
5999
6000static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
6001 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
6002};
6003
6004static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
6005 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
6006};
6007
f75eb1c0 6008static const CGEN_IFMT ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6009 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
6010};
6011
6012static const CGEN_IFMT ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
6013 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
6014};
6015
49f58d10
JB		 6016static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6017 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6018};
6019
6020static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6021 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6022};
6023
6024static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6025 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6026};
6027
6028static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6029 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6030};
6031
6032static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6033 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6034};
6035
6036static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6037 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6038};
6039
6040static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6041 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6042};
6043
6044static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6045 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6046};
6047
6048static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6049 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6050};
6051
6052static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6053 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6054};
6055
6056static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6057 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6058};
6059
6060static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6061 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6062};
6063
6064static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6065 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6066};
6067
6068static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6069 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6070};
6071
6072static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6073 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6074};
6075
6076static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6077 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6078};
6079
6080static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6081 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6082};
6083
6084static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6085 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6086};
6087
6088static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6089 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6090};
6091
6092static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6093 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6094};
6095
6096static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6097 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6098};
6099
6100static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6101 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6102};
6103
6104static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6105 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6106};
6107
6108static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6109 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6110};
6111
6112static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6113 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6114};
6115
6116static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6117 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6118};
6119
6120static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6121 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6122};
6123
6124static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6125 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6126};
6127
6128static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6129 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6130};
6131
6132static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6133 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6134};
6135
6136static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6137 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6138};
6139
6140static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6141 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6142};
6143
6144static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6145 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6146};
6147
6148static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6149 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6150};
6151
6152static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6153 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6154};
6155
6156static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6157 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6158};
6159
6160static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6161 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6162};
6163
6164static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6165 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6166};
6167
6168static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6169 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6170};
6171
6172static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6173 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6174};
6175
6176static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6177 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6178};
6179
6180static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6181 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6182};
6183
6184static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6185 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6186};
6187
6188static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6189 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6190};
6191
6192static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6193 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6194};
6195
6196static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6197 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6198};
6199
6200static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6201 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6202};
6203
6204static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6205 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6206};
6207
6208static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6209 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6210};
6211
6212static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6213 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6214};
6215
6216static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6217 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6218};
6219
6220static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6221 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6222};
6223
6224static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6225 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6226};
6227
6228static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6229 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6230};
6231
6232static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6233 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6234};
6235
6236static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6237 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6238};
6239
6240static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6241 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6242};
6243
6244static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6245 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6246};
6247
6248static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6249 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6250};
6251
6252static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6253 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6254};
6255
6256static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6257 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6258};
6259
6260static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6261 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6262};
6263
6264static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6265 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6266};
6267
6268static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6269 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6270};
6271
6272static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6273 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6274};
6275
6276static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6277 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6278};
6279
6280static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6281 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6282};
6283
6284static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6285 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6286};
6287
6288static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6289 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6290};
6291
6292static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6293 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6294};
6295
6296static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6297 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6298};
6299
6300static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6301 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6302};
6303
6304static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6305 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6306};
6307
6308static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6309 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6310};
6311
6312static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6313 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6314};
6315
6316static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6317 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6318};
6319
6320static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6321 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6322};
6323
6324static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6325 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6326};
6327
6328static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6329 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6330};
6331
6332static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6333 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6334};
6335
6336static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6337 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6338};
6339
6340static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6341 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6342};
6343
6344static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6345 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6346};
6347
6348static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6349 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6350};
6351
6352static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6353 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6354};
6355
6356static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6357 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6358};
6359
6360static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6361 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6362};
6363
6364static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6365 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6366};
6367
6368static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6369 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6370};
6371
6372static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6373 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6374};
6375
6376static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6377 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6378};
6379
6380static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6381 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6382};
6383
6384static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6385 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6386};
6387
6388static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6389 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6390};
6391
6392static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6393 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6394};
6395
6396static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6397 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6398};
6399
6400static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6401 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6402};
6403
6404static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6405 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6406};
6407
6408static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6409 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6410};
6411
6412static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6413 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6414};
6415
6416static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6417 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6418};
6419
6420static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6421 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6422};
6423
6424static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6425 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6426};
6427
6428static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6429 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6430};
6431
6432static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6433 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6434};
6435
6436static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6437 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6438};
6439
6440static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6441 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6442};
6443
6444static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6445 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6446};
6447
6448static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6449 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6450};
6451
6452static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6453 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6454};
6455
6456static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6457 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6458};
6459
6460static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6461 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6462};
6463
6464static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6465 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6466};
6467
6468static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6469 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6470};
6471
6472static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6473 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6474};
6475
6476static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6477 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6478};
6479
6480static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6481 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6482};
6483
6484static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6485 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6486};
6487
6488static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6489 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6490};
6491
6492static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6493 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6494};
6495
6496static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6497 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6498};
6499
6500static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6501 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6502};
6503
6504static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6505 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6506};
6507
6508static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6509 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6510};
6511
6512static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6513 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6514};
6515
6516static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6517 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6518};
6519
6520static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6521 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6522};
6523
6524static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6525 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6526};
6527
6528static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6529 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6530};
6531
6532static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6533 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6534};
6535
6536static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6537 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6538};
6539
6540static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6541 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6542};
6543
6544static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6545 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6546};
6547
6548static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6549 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6550};
6551
6552static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6553 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6554};
6555
6556static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6557 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6558};
6559
6560static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6561 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6562};
6563
6564static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6565 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6566};
6567
6568static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6569 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6570};
6571
6572static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6573 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6574};
6575
6576static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6577 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6578};
6579
6580static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6581 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6582};
6583
6584static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6585 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6586};
6587
6588static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6589 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6590};
6591
6592static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6593 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6594};
6595
6596static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6597 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6598};
6599
6600static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
6601 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6602};
6603
49f58d10
JB		 6604static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
6605 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6606};
6607
6608static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
6609 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6610};
6611
6612static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
6613 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6614};
6615
6616static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6617 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6618};
6619
6620static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6621 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6622};
6623
6624static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6625 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6626};
6627
6628static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6629 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6630};
6631
6632static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6633 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6634};
6635
6636static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6637 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6638};
6639
6640static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6641 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6642};
6643
6644static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
6645 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6646};
6647
6648static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
6649 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6650};
6651
6652static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
6653 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6654};
6655
6656static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
6657 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6658};
6659
6660static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
6661 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6662};
6663
6664static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6665 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6666};
6667
6668static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6669 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6670};
6671
6672static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6673 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6674};
6675
6676static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6677 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6678};
6679
6680static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6681 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6682};
6683
6684static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6685 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6686};
6687
6688static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6689 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6690};
6691
6692static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
6693 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6694};
6695
6696static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
6697 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6698};
6699
db313fa6 6700static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6701 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6702};
6703
db313fa6 6704static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6705 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6706};
6707
db313fa6 6708static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6709 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6710};
6711
db313fa6 6712static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6713 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6714};
6715
db313fa6 6716static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6717 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6718};
6719
db313fa6 6720static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6721 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6722};
6723
db313fa6 6724static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6725 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6726};
6727
db313fa6 6728static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6729 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6730};
6731
db313fa6
DD		 6732static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
6733 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6734};
6735
6736static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
6737 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6738};
6739
6740static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
6741 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6742};
6743
6744static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
6745 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6746};
6747
6748static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
6749 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6750};
6751
6752static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
6753 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6754};
6755
6756static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6757 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6758};
6759
6760static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
6761 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6762};
6763
6764static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6765 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6766};
6767
6768static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6769 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6770};
6771
6772static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6773 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6774};
6775
6776static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6777 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6778};
6779
6780static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6781 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6782};
6783
6784static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6785 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6786};
6787
6788static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6789 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6790};
6791
6792static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6793 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6794};
6795
6796static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6797 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6798};
6799
6800static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6801 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6802};
6803
6804static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6805 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6806};
6807
6808static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6809 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6810};
6811
6812static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6813 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6814};
6815
6816static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6817 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6818};
6819
a1a280bb
DD		 6820static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
6821 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6822};
6823
a1a280bb
DD		 6824static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
6825 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6826};
6827
a1a280bb
DD		 6828static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
6829 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6830};
6831
a1a280bb
DD		 6832static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
6833 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6834};
6835
a1a280bb
DD		 6836static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
6837 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6838};
6839
a1a280bb
DD		 6840static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
6841 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6842};
6843
a1a280bb 6844static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6845 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6846};
6847
a1a280bb 6848static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6849 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6850};
6851
a1a280bb 6852static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6853 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6854};
6855
a1a280bb
DD		 6856static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
6857 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6858};
6859
a1a280bb
DD		 6860static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
6861 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6862};
6863
a1a280bb
DD		 6864static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
6865 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6866};
6867
a1a280bb
DD		 6868static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
6869 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6870};
6871
a1a280bb
DD		 6872static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6873 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6874};
6875
a1a280bb
DD		 6876static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6877 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
49f58d10
JB		 6878};
6879
a1a280bb 6880static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6881 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6882};
6883
a1a280bb 6884static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6885 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6886};
6887
a1a280bb 6888static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
49f58d10
JB		 6889 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6890};
6891
6892static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
6893 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6894};
6895
6896static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
6897 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6898};
6899
6900static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = {
6901 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6902};
6903
6904static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6905 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6906};
6907
6908static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6909 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6910};
6911
6912static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6913 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6914};
6915
6916static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6917 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6918};
6919
6920static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6921 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6922};
6923
6924static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6925 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6926};
6927
6928static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6929 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6930};
6931
6932static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
6933 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6934};
6935
6936static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
6937 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6938};
6939
6940static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6941 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6942};
6943
6944static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6945 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6946};
6947
6948static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6949 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6950};
6951
6952static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6953 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6954};
6955
6956static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6957 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6958};
6959
6960static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6961 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6962};
6963
6964static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6965 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6966};
6967
6968static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6969 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6970};
6971
6972static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6973 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6974};
6975
6976static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6977 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6978};
6979
6980static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6981 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6982};
6983
6984static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6985 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6986};
6987
6988static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
6989 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6990};
6991
6992static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
6993 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6994};
6995
6996static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
6997 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6998};
6999
7000static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7001 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7002};
7003
7004static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7005 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7006};
7007
7008static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7009 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7010};
7011
7012static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7013 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7014};
7015
7016static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7017 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7018};
7019
7020static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7021 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7022};
7023
7024static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7025 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7026};
7027
7028static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7029 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7030};
7031
7032static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7033 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7034};
7035
7036static const CGEN_IFMT ifmt_stc16_src_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
7037 16, 16, 0xff8c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7038};
7039
7040static const CGEN_IFMT ifmt_stc16_src_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
7041 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7042};
7043
7044static const CGEN_IFMT ifmt_stc16_src_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
7045 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7046};
7047
7048static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
7049 24, 24, 0xff8e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7050};
7051
7052static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
7053 32, 32, 0xff8e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7054};
7055
7056static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
7057 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7058};
7059
7060static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
7061 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7062};
7063
7064static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
7065 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7066};
7067
7068static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
7069 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7070};
7071
eda87aba
DD		 7072static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI ATTRIBUTE_UNUSED = {
7073 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7074};
7075
7076static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI ATTRIBUTE_UNUSED = {
7077 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7078};
7079
7080static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUTE_UNUSED = {
7081 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7082};
7083
75b06e7b 7084static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI ATTRIBUTE_UNUSED = {
49f58d10
JB		 7085 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7086};
7087
75b06e7b 7088static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI ATTRIBUTE_UNUSED = {
49f58d10
JB		 7089 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7090};
7091
7092static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI ATTRIBUTE_UNUSED = {
7093 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7094};
7095
7096static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI ATTRIBUTE_UNUSED = {
7097 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7098};
7099
7100static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI ATTRIBUTE_UNUSED = {
7101 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7102};
7103
75b06e7b
DD		 7104static const CGEN_IFMT ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI ATTRIBUTE_UNUSED = {
7105 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7106};
7107
7108static const CGEN_IFMT ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI ATTRIBUTE_UNUSED = {
7109 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7110};
7111
7112static const CGEN_IFMT ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = {
7113 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7114};
7115
49f58d10
JB		 7116static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
7117 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7118};
7119
7120static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
7121 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7122};
7123
7124static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
7125 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7126};
7127
7128static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
7129 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7130};
7131
7132static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
7133 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7134};
7135
7136static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
7137 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7138};
7139
49f58d10
JB		 7140static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
7141 32, 56, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7142};
7143
7144static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
7145 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7146};
7147
7148static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
7149 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7150};
7151
7152static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7153 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7154};
7155
7156static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7157 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7158};
7159
7160static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7161 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7162};
7163
7164static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7165 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7166};
7167
7168static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7169 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7170};
7171
7172static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7173 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7174};
7175
7176static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7177 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7178};
7179
7180static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7181 32, 80, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7182};
7183
7184static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7185 32, 80, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7186};
7187
7188static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
7189 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7190};
7191
7192static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
7193 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7194};
7195
7196static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
7197 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7198};
7199
7200static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7201 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7202};
7203
7204static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7205 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7206};
7207
7208static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7209 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7210};
7211
7212static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7213 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7214};
7215
7216static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7217 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7218};
7219
7220static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7221 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7222};
7223
7224static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
7225 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7226};
7227
7228static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7229 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } }
7230};
7231
7232static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
7233 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } }
7234};
7235
7236static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed ATTRIBUTE_UNUSED = {
7237 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7238};
7239
7240static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed ATTRIBUTE_UNUSED = {
7241 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7242};
7243
7244static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed ATTRIBUTE_UNUSED = {
7245 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7246};
7247
7248static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7249 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7250};
7251
7252static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7253 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7254};
7255
7256static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7257 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7258};
7259
7260static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed ATTRIBUTE_UNUSED = {
7261 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7262};
7263
7264static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed ATTRIBUTE_UNUSED = {
7265 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7266};
7267
7268static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed ATTRIBUTE_UNUSED = {
7269 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7270};
7271
7272static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed ATTRIBUTE_UNUSED = {
7273 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7274};
7275
7276static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed ATTRIBUTE_UNUSED = {
7277 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7278};
7279
7280static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed ATTRIBUTE_UNUSED = {
7281 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7282};
7283
7284static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_Rn_direct ATTRIBUTE_UNUSED = {
7285 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7286};
7287
7288static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_direct ATTRIBUTE_UNUSED = {
7289 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7290};
7291
7292static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_indirect ATTRIBUTE_UNUSED = {
7293 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7294};
7295
7296static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative ATTRIBUTE_UNUSED = {
7297 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7298};
7299
7300static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative ATTRIBUTE_UNUSED = {
7301 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7302};
7303
7304static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = {
7305 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7306};
7307
7308static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = {
7309 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7310};
7311
7312static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = {
7313 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7314};
7315
7316static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_absolute ATTRIBUTE_UNUSED = {
7317 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7318};
7319
7320static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = {
7321 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7322};
7323
7324static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = {
7325 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7326};
7327
7328static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = {
7329 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7330};
7331
7332static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7333 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7334};
7335
7336static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7337 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7338};
7339
7340static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7341 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7342};
7343
7344static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7345 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7346};
7347
7348static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7349 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7350};
7351
7352static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7353 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7354};
7355
7356static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7357 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7358};
7359
7360static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7361 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7362};
7363
7364static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7365 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7366};
7367
7368static const CGEN_IFMT ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S ATTRIBUTE_UNUSED = {
7369 16, 16, 0xf800, { { F (F_0_2) }, { F (F_BITBASE16_U11_S) }, { F (F_2_2) }, { F (F_4_1) }, { 0 } }
7370};
7371
7372static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = {
7373 24, 24, 0xff3800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7374};
7375
7376static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = {
7377 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7378};
7379
7380static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = {
7381 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7382};
7383
7384static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7385 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7386};
7387
7388static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7389 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7390};
7391
7392static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7393 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7394};
7395
7396static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7397 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7398};
7399
7400static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7401 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7402};
7403
7404static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7405 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7406};
7407
7408static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7409 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7410};
7411
7412static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7413 32, 48, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } }
7414};
7415
7416static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7417 32, 48, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } }
7418};
7419
7420static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct ATTRIBUTE_UNUSED = {
7421 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7422};
7423
7424static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct ATTRIBUTE_UNUSED = {
7425 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7426};
7427
7428static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative ATTRIBUTE_UNUSED = {
7429 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7430};
7431
7432static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = {
7433 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7434};
7435
7436static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = {
7437 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7438};
7439
7440static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative ATTRIBUTE_UNUSED = {
7441 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7442};
7443
7444static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = {
7445 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7446};
7447
7448static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute ATTRIBUTE_UNUSED = {
7449 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7450};
7451
7452static const CGEN_IFMT ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect ATTRIBUTE_UNUSED = {
7453 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
7454};
7455
c6552317
DD		 7456static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7457 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7458};
7459
7460static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7461 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7462};
7463
7464static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7465 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7466};
7467
7468static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7469 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7470};
7471
7472static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7473 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7474};
7475
7476static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7477 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7478};
7479
7480static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
7481 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7482};
7483
7484static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7485 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7486};
7487
7488static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
7489 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7490};
7491
7492static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
7493 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7494};
7495
7496static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
7497 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7498};
7499
7500static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
7501 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7502};
7503
7504static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7505 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7506};
7507
7508static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7509 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7510};
7511
7512static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7513 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7514};
7515
7516static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7517 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7518};
7519
7520static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7521 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7522};
7523
7524static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7525 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7526};
7527
7528static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
7529 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7530};
7531
7532static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7533 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7534};
7535
7536static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
7537 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7538};
7539
7540static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
7541 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7542};
7543
7544static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
7545 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7546};
7547
7548static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
7549 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7550};
7551
7552static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 7553 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
c6552317
DD		 7554};
7555
7556static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 7557 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
c6552317
DD		 7558};
7559
7560static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 7561 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
c6552317
DD		 7562};
7563
7564static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 7565 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
c6552317
DD		 7566};
7567
7568static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
144f4bc6 7569 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
c6552317
DD		 7570};
7571
7572static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
144f4bc6 7573 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
c6552317
DD		 7574};
7575
7576static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
7577 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7578};
7579
7580static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
7581 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7582};
7583
7584static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
7585 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7586};
7587
7588static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 7589 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
c6552317
DD		 7590};
7591
7592static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 7593 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
c6552317
DD		 7594};
7595
7596static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 7597 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
c6552317
DD		 7598};
7599
7600static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 7601 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
c6552317
DD		 7602};
7603
7604static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
144f4bc6 7605 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
c6552317
DD		 7606};
7607
7608static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
144f4bc6 7609 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
c6552317
DD		 7610};
7611
7612static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
7613 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7614};
7615
7616static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
7617 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7618};
7619
7620static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
7621 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7622};
7623
49f58d10
JB		 7624static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI ATTRIBUTE_UNUSED = {
7625 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } }
7626};
7627
7628static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI ATTRIBUTE_UNUSED = {
7629 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } }
7630};
7631
7632static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
7633 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7634};
7635
7636static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
7637 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7638};
7639
7640static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
7641 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7642};
7643
7644static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7645 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7646};
7647
7648static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7649 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7650};
7651
7652static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7653 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7654};
7655
7656static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7657 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7658};
7659
7660static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7661 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7662};
7663
7664static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7665 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7666};
7667
7668static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7669 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7670};
7671
7672static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
7673 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7674};
7675
7676static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
7677 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7678};
7679
92e0a941 7680static const CGEN_IFMT ifmt_add16_wQ_sp ATTRIBUTE_UNUSED = {
49f58d10
JB		 7681 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
7682};
7683
7684static const CGEN_IFMT ifmt_add16_b_G_sp ATTRIBUTE_UNUSED = {
7685 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7686};
7687
7688static const CGEN_IFMT ifmt_add16_w_G_sp ATTRIBUTE_UNUSED = {
7689 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7690};
7691
7692static const CGEN_IFMT ifmt_add32_l_imm3_Q ATTRIBUTE_UNUSED = {
7693 8, 8, 0xce, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { 0 } }
7694};
7695
7696static const CGEN_IFMT ifmt_add32_l_imm8_S ATTRIBUTE_UNUSED = {
7697 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7698};
7699
7700static const CGEN_IFMT ifmt_add32_l_imm16_G ATTRIBUTE_UNUSED = {
7701 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7702};
7703
7704static const CGEN_IFMT ifmt_dadc16_b_r0h_r0l ATTRIBUTE_UNUSED = {
7705 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } }
7706};
7707
7708static const CGEN_IFMT ifmt_bm16_c ATTRIBUTE_UNUSED = {
7709 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { 0 } }
7710};
7711
7712static const CGEN_IFMT ifmt_bm32_c ATTRIBUTE_UNUSED = {
7713 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_COND32) }, { F (F_10_3) }, { 0 } }
7714};
7715
7716static const CGEN_IFMT ifmt_brk16 ATTRIBUTE_UNUSED = {
7717 8, 8, 0xff, { { F (F_0_4) }, { F (F_4_4) }, { 0 } }
7718};
7719
5398310a
DD		 7720static const CGEN_IFMT ifmt_btst_s ATTRIBUTE_UNUSED = {
7721 24, 24, 0xce0000, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { F (F_DSP_8_U16) }, { 0 } }
7722};
7723
49f58d10
JB		 7724static const CGEN_IFMT ifmt_dec16_w ATTRIBUTE_UNUSED = {
7725 8, 8, 0xf7, { { F (F_0_4) }, { F (F_DST16_AN_S) }, { F (F_5_3) }, { 0 } }
7726};
7727
7728static const CGEN_IFMT ifmt_div32_b_Imm_16_QI ATTRIBUTE_UNUSED = {
7729 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7730};
7731
7732static const CGEN_IFMT ifmt_div32_w_Imm_16_HI ATTRIBUTE_UNUSED = {
7733 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7734};
7735
7736static const CGEN_IFMT ifmt_enter16 ATTRIBUTE_UNUSED = {
7737 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
7738};
7739
7740static const CGEN_IFMT ifmt_enter32 ATTRIBUTE_UNUSED = {
7741 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U8) }, { 0 } }
7742};
7743
7744static const CGEN_IFMT ifmt_fclr16 ATTRIBUTE_UNUSED = {
7745 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } }
7746};
7747
7748static const CGEN_IFMT ifmt_fclr ATTRIBUTE_UNUSED = {
7749 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7750};
7751
7752static const CGEN_IFMT ifmt_int16 ATTRIBUTE_UNUSED = {
7753 16, 16, 0xffc0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_2) }, { F (F_DSP_10_U6) }, { 0 } }
7754};
7755
7756static const CGEN_IFMT ifmt_int32 ATTRIBUTE_UNUSED = {
7757 16, 16, 0xff03, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U6) }, { F (F_14_2) }, { 0 } }
7758};
7759
7760static const CGEN_IFMT ifmt_jcnd16_5 ATTRIBUTE_UNUSED = {
7761 16, 16, 0xf800, { { F (F_0_4) }, { F (F_4_1) }, { F (F_COND16J_5) }, { F (F_LAB_8_8) }, { 0 } }
7762};
7763
7764static const CGEN_IFMT ifmt_jcnd16 ATTRIBUTE_UNUSED = {
7765 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { F (F_LAB_16_8) }, { 0 } }
7766};
7767
7768static const CGEN_IFMT ifmt_jcnd32 ATTRIBUTE_UNUSED = {
7769 16, 16, 0x8e00, { { F (F_0_1) }, { F (F_COND32J) }, { F (F_4_3) }, { F (F_LAB_8_8) }, { 0 } }
7770};
7771
7772static const CGEN_IFMT ifmt_jmp16_s ATTRIBUTE_UNUSED = {
7773 8, 8, 0xf8, { { F (F_0_4) }, { F (F_4_1) }, { F (F_LAB_5_3) }, { 0 } }
7774};
7775
7776static const CGEN_IFMT ifmt_jmp16_b ATTRIBUTE_UNUSED = {
7777 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_8) }, { 0 } }
7778};
7779
7780static const CGEN_IFMT ifmt_jmp16_w ATTRIBUTE_UNUSED = {
7781 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_16) }, { 0 } }
7782};
7783
7784static const CGEN_IFMT ifmt_jmp16_a ATTRIBUTE_UNUSED = {
7785 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_24) }, { 0 } }
7786};
7787
7788static const CGEN_IFMT ifmt_jmps16 ATTRIBUTE_UNUSED = {
7789 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { 0 } }
7790};
7791
7792static const CGEN_IFMT ifmt_jmp32_s ATTRIBUTE_UNUSED = {
7793 8, 8, 0xce, { { F (F_0_2) }, { F (F_LAB32_JMP_S) }, { F (F_4_3) }, { 0 } }
7794};
7795
7796static const CGEN_IFMT ifmt_ldc16_imm16 ATTRIBUTE_UNUSED = {
7797 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7798};
7799
7800static const CGEN_IFMT ifmt_ldc32_imm16_cr1 ATTRIBUTE_UNUSED = {
7801 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { F (F_DSP_16_S16) }, { 0 } }
7802};
7803
7804static const CGEN_IFMT ifmt_ldc32_imm16_cr2 ATTRIBUTE_UNUSED = {
7805 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7806};
7807
7808static const CGEN_IFMT ifmt_ldc32_imm16_cr3 ATTRIBUTE_UNUSED = {
7809 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7810};
7811
7812static const CGEN_IFMT ifmt_ldctx16 ATTRIBUTE_UNUSED = {
7813 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { 0 } }
7814};
7815
7816static const CGEN_IFMT ifmt_ldipl16_imm ATTRIBUTE_UNUSED = {
7817 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_IMM_13_U3) }, { 0 } }
7818};
7819
7820static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = {
7821 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S16) }, { 0 } }
7822};
7823
7824static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = {
f75eb1c0 7825 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S24) }, { 0 } }
49f58d10
JB		 7826};
7827
7828static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = {
7829 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } }
7830};
7831
7832static const CGEN_IFMT ifmt_popc32_imm16_cr1 ATTRIBUTE_UNUSED = {
7833 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7834};
7835
7836static const CGEN_IFMT ifmt_popc32_imm16_cr2 ATTRIBUTE_UNUSED = {
7837 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7838};
7839
7840static const CGEN_IFMT ifmt_popm16 ATTRIBUTE_UNUSED = {
7841 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } }
7842};
7843
7844static const CGEN_IFMT ifmt_pushm16 ATTRIBUTE_UNUSED = {
7845 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } }
7846};
7847
7848static const CGEN_IFMT ifmt_push32_l_imm ATTRIBUTE_UNUSED = {
7849 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } }
7850};
7851
7852static const CGEN_IFMT ifmt_sha16_L_imm_r2r0 ATTRIBUTE_UNUSED = {
7853 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
7854};
7855
7856static const CGEN_IFMT ifmt_stzx16_imm8_imm8_r0h ATTRIBUTE_UNUSED = {
7857 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { 0 } }
7858};
7859
7860static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8sb ATTRIBUTE_UNUSED = {
7861 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U8) }, { F (F_DSP_24_S8) }, { 0 } }
7862};
7863
c6552317
DD		 7864static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8fb ATTRIBUTE_UNUSED = {
7865 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
7866};
7867
49f58d10
JB		 7868static const CGEN_IFMT ifmt_stzx16_imm8_imm8_abs16 ATTRIBUTE_UNUSED = {
7869 32, 40, 0xff000000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U16) }, { 0 } }
7870};
7871
7872#undef F
7873
7874#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
7875#define A(a) (1 << CGEN_INSN_##a)
7876#else
7877#define A(a) (1 << CGEN_INSN_/**/a)
7878#endif
7879#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
7880#define OPERAND(op) M32C_OPERAND_##op
7881#else
7882#define OPERAND(op) M32C_OPERAND_/**/op
7883#endif
7884#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
7885#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
7886
7887/* The instruction table. */
7888
7889static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
7890{
7891 /* Special null first entry.
7892 A `num' value of zero is thus invalid.
7893 Also, the special `invalid' insn resides here. */
7894 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
7895/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7896 {
7897 { 0, 0, 0, 0 },
7898 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7899 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980b00 }
7900 },
7901/* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
7902 {
7903 { 0, 0, 0, 0 },
7904 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7905 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982b00 }
7906 },
7907/* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
7908 {
7909 { 0, 0, 0, 0 },
7910 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7911 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983b00 }
7912 },
7913/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7914 {
7915 { 0, 0, 0, 0 },
7916 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7917 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908b00 }
7918 },
7919/* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
7920 {
7921 { 0, 0, 0, 0 },
7922 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7923 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190ab00 }
7924 },
7925/* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
7926 {
7927 { 0, 0, 0, 0 },
7928 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7929 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190bb00 }
7930 },
7931/* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7932 {
7933 { 0, 0, 0, 0 },
7934 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7935 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900b00 }
7936 },
7937/* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
7938 {
7939 { 0, 0, 0, 0 },
7940 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7941 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902b00 }
7942 },
7943/* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
7944 {
7945 { 0, 0, 0, 0 },
7946 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7947 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903b00 }
7948 },
7949/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
7950 {
7951 { 0, 0, 0, 0 },
7952 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7953 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920b00 }
7954 },
7955/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7956 {
7957 { 0, 0, 0, 0 },
7958 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7959 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922b00 }
7960 },
7961/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7962 {
7963 { 0, 0, 0, 0 },
7964 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7965 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923b00 }
7966 },
7967/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
7968 {
7969 { 0, 0, 0, 0 },
7970 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7971 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940b00 }
7972 },
7973/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7974 {
7975 { 0, 0, 0, 0 },
7976 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7977 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942b00 }
7978 },
7979/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7980 {
7981 { 0, 0, 0, 0 },
7982 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7983 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943b00 }
7984 },
7985/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
7986 {
7987 { 0, 0, 0, 0 },
7988 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7989 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960b00 }
7990 },
7991/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7992 {
7993 { 0, 0, 0, 0 },
7994 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7995 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962b00 }
7996 },
7997/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7998 {
7999 { 0, 0, 0, 0 },
8000 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8001 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963b00 }
8002 },
8003/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8004 {
8005 { 0, 0, 0, 0 },
8006 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8007 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928b00 }
8008 },
8009/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8010 {
8011 { 0, 0, 0, 0 },
8012 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8013 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192ab00 }
8014 },
8015/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8016 {
8017 { 0, 0, 0, 0 },
8018 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8019 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192bb00 }
8020 },
8021/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8022 {
8023 { 0, 0, 0, 0 },
8024 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8025 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948b00 }
8026 },
8027/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8028 {
8029 { 0, 0, 0, 0 },
8030 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8031 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194ab00 }
8032 },
8033/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8034 {
8035 { 0, 0, 0, 0 },
8036 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8037 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194bb00 }
8038 },
8039/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8040 {
8041 { 0, 0, 0, 0 },
8042 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8043 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192cb00 }
8044 },
8045/* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8046 {
8047 { 0, 0, 0, 0 },
8048 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8049 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192eb00 }
8050 },
8051/* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8052 {
8053 { 0, 0, 0, 0 },
8054 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8055 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192fb00 }
8056 },
8057/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8058 {
8059 { 0, 0, 0, 0 },
8060 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8061 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194cb00 }
8062 },
8063/* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8064 {
8065 { 0, 0, 0, 0 },
8066 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8067 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194eb00 }
8068 },
8069/* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8070 {
8071 { 0, 0, 0, 0 },
8072 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8073 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194fb00 }
8074 },
8075/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8076 {
8077 { 0, 0, 0, 0 },
8078 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
8079 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196cb00 }
8080 },
8081/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8082 {
8083 { 0, 0, 0, 0 },
8084 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8085 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196eb00 }
8086 },
8087/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8088 {
8089 { 0, 0, 0, 0 },
8090 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8091 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196fb00 }
8092 },
8093/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8094 {
8095 { 0, 0, 0, 0 },
8096 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
8097 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968b00 }
8098 },
8099/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8100 {
8101 { 0, 0, 0, 0 },
8102 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8103 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196ab00 }
8104 },
8105/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8106 {
8107 { 0, 0, 0, 0 },
8108 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8109 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196bb00 }
8110 },
8111/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8112 {
8113 { 0, 0, 0, 0 },
8114 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8115 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80b00 }
8116 },
8117/* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
8118 {
8119 { 0, 0, 0, 0 },
8120 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8121 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82b00 }
8122 },
8123/* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
8124 {
8125 { 0, 0, 0, 0 },
8126 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8127 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83b00 }
8128 },
8129/* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
8130 {
8131 { 0, 0, 0, 0 },
8132 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
8133 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83b00 }
8134 },
8135/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8136 {
8137 { 0, 0, 0, 0 },
8138 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8139 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08b00 }
8140 },
8141/* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
8142 {
8143 { 0, 0, 0, 0 },
8144 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8145 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0ab00 }
8146 },
8147/* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
8148 {
8149 { 0, 0, 0, 0 },
8150 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8151 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0bb00 }
8152 },
8153/* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
8154 {
8155 { 0, 0, 0, 0 },
8156 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
8157 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0bb00 }
8158 },
8159/* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8160 {
8161 { 0, 0, 0, 0 },
8162 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8163 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00b00 }
8164 },
8165/* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8166 {
8167 { 0, 0, 0, 0 },
8168 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8169 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02b00 }
8170 },
8171/* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8172 {
8173 { 0, 0, 0, 0 },
8174 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8175 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03b00 }
8176 },
8177/* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
8178 {
8179 { 0, 0, 0, 0 },
8180 { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8181 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03b00 }
8182 },
8183/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8184 {
8185 { 0, 0, 0, 0 },
8186 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8187 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20b00 }
8188 },
8189/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8190 {
8191 { 0, 0, 0, 0 },
8192 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8193 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22b00 }
8194 },
8195/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8196 {
8197 { 0, 0, 0, 0 },
8198 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8199 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23b00 }
8200 },
8201/* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8202 {
8203 { 0, 0, 0, 0 },
8204 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8205 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23b00 }
8206 },
8207/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8208 {
8209 { 0, 0, 0, 0 },
8210 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8211 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40b00 }
8212 },
8213/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8214 {
8215 { 0, 0, 0, 0 },
8216 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8217 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42b00 }
8218 },
8219/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8220 {
8221 { 0, 0, 0, 0 },
8222 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8223 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43b00 }
8224 },
8225/* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8226 {
8227 { 0, 0, 0, 0 },
8228 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8229 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43b00 }
8230 },
8231/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8232 {
8233 { 0, 0, 0, 0 },
8234 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8235 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60b00 }
8236 },
8237/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8238 {
8239 { 0, 0, 0, 0 },
8240 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8241 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62b00 }
8242 },
8243/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8244 {
8245 { 0, 0, 0, 0 },
8246 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8247 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63b00 }
8248 },
8249/* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8250 {
8251 { 0, 0, 0, 0 },
8252 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8253 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63b00 }
8254 },
8255/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8256 {
8257 { 0, 0, 0, 0 },
8258 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8259 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28b00 }
8260 },
8261/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8262 {
8263 { 0, 0, 0, 0 },
8264 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8265 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2ab00 }
8266 },
8267/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8268 {
8269 { 0, 0, 0, 0 },
8270 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8271 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2bb00 }
8272 },
8273/* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8274 {
8275 { 0, 0, 0, 0 },
8276 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8277 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2bb00 }
8278 },
8279/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8280 {
8281 { 0, 0, 0, 0 },
8282 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8283 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48b00 }
8284 },
8285/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8286 {
8287 { 0, 0, 0, 0 },
8288 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8289 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4ab00 }
8290 },
8291/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8292 {
8293 { 0, 0, 0, 0 },
8294 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8295 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4bb00 }
8296 },
8297/* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8298 {
8299 { 0, 0, 0, 0 },
8300 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8301 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4bb00 }
8302 },
8303/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8304 {
8305 { 0, 0, 0, 0 },
8306 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8307 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2cb00 }
8308 },
8309/* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8310 {
8311 { 0, 0, 0, 0 },
8312 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8313 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2eb00 }
8314 },
8315/* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8316 {
8317 { 0, 0, 0, 0 },
8318 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8319 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2fb00 }
8320 },
8321/* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8322 {
8323 { 0, 0, 0, 0 },
8324 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8325 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2fb00 }
8326 },
8327/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8328 {
8329 { 0, 0, 0, 0 },
8330 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8331 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4cb00 }
8332 },
8333/* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8334 {
8335 { 0, 0, 0, 0 },
8336 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8337 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4eb00 }
8338 },
8339/* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8340 {
8341 { 0, 0, 0, 0 },
8342 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8343 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4fb00 }
8344 },
8345/* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8346 {
8347 { 0, 0, 0, 0 },
8348 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8349 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4fb00 }
8350 },
8351/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8352 {
8353 { 0, 0, 0, 0 },
8354 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
8355 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6cb00 }
8356 },
8357/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8358 {
8359 { 0, 0, 0, 0 },
8360 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8361 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6eb00 }
8362 },
8363/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8364 {
8365 { 0, 0, 0, 0 },
8366 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8367 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6fb00 }
8368 },
8369/* extz ${Dsp-24-u16},${Dsp-40-u16} */
8370 {
8371 { 0, 0, 0, 0 },
8372 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
8373 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6fb00 }
8374 },
8375/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8376 {
8377 { 0, 0, 0, 0 },
8378 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
8379 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68b00 }
8380 },
8381/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8382 {
8383 { 0, 0, 0, 0 },
8384 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8385 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6ab00 }
8386 },
8387/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8388 {
8389 { 0, 0, 0, 0 },
8390 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8391 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6bb00 }
8392 },
8393/* extz ${Dsp-24-u16},${Dsp-40-u24} */
8394 {
8395 { 0, 0, 0, 0 },
8396 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
8397 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6bb00 }
8398 },
8399/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8400 {
8401 { 0, 0, 0, 0 },
8402 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8403 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80b00 }
8404 },
8405/* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
8406 {
8407 { 0, 0, 0, 0 },
8408 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
8409 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82b00 }
8410 },
8411/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8412 {
8413 { 0, 0, 0, 0 },
8414 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8415 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08b00 }
8416 },
8417/* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
8418 {
8419 { 0, 0, 0, 0 },
8420 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
8421 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0ab00 }
8422 },
8423/* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8424 {
8425 { 0, 0, 0, 0 },
8426 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8427 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00b00 }
8428 },
8429/* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
8430 {
8431 { 0, 0, 0, 0 },
8432 { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8433 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02b00 }
8434 },
8435/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8436 {
8437 { 0, 0, 0, 0 },
8438 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8439 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20b00 }
8440 },
8441/* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8442 {
8443 { 0, 0, 0, 0 },
8444 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8445 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22b00 }
8446 },
8447/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8448 {
8449 { 0, 0, 0, 0 },
8450 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8451 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40b00 }
8452 },
8453/* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8454 {
8455 { 0, 0, 0, 0 },
8456 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8457 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42b00 }
8458 },
8459/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8460 {
8461 { 0, 0, 0, 0 },
8462 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8463 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60b00 }
8464 },
8465/* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8466 {
8467 { 0, 0, 0, 0 },
8468 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8469 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62b00 }
8470 },
8471/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8472 {
8473 { 0, 0, 0, 0 },
8474 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
8475 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28b00 }
8476 },
8477/* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8478 {
8479 { 0, 0, 0, 0 },
8480 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
8481 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2ab00 }
8482 },
8483/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8484 {
8485 { 0, 0, 0, 0 },
8486 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
8487 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48b00 }
8488 },
8489/* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8490 {
8491 { 0, 0, 0, 0 },
8492 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
8493 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4ab00 }
8494 },
8495/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8496 {
8497 { 0, 0, 0, 0 },
8498 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
8499 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2cb00 }
8500 },
8501/* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8502 {
8503 { 0, 0, 0, 0 },
8504 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
8505 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2eb00 }
8506 },
8507/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8508 {
8509 { 0, 0, 0, 0 },
8510 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
8511 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4cb00 }
8512 },
8513/* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8514 {
8515 { 0, 0, 0, 0 },
8516 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
8517 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4eb00 }
8518 },
8519/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8520 {
8521 { 0, 0, 0, 0 },
8522 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
8523 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6cb00 }
8524 },
8525/* extz ${Dsp-24-u24},${Dsp-48-u16} */
8526 {
8527 { 0, 0, 0, 0 },
8528 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
8529 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6eb00 }
8530 },
8531/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8532 {
8533 { 0, 0, 0, 0 },
8534 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
8535 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68b00 }
8536 },
8537/* extz ${Dsp-24-u24},${Dsp-48-u24} */
8538 {
8539 { 0, 0, 0, 0 },
8540 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
8541 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6ab00 }
8542 },
8543/* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
8544 {
8545 { 0, 0, 0, 0 },
8546 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } },
8547 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c80b }
8548 },
8549/* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
8550 {
8551 { 0, 0, 0, 0 },
8552 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8553 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1880b }
8554 },
8555/* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
8556 {
8557 { 0, 0, 0, 0 },
8558 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } },
8559 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c08b }
8560 },
8561/* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
8562 {
8563 { 0, 0, 0, 0 },
8564 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8565 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1808b }
8566 },
8567/* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
8568 {
8569 { 0, 0, 0, 0 },
8570 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8571 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c00b }
8572 },
8573/* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
8574 {
8575 { 0, 0, 0, 0 },
8576 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8577 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1800b }
8578 },
8579/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8580 {
8581 { 0, 0, 0, 0 },
8582 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8583 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20b00 }
8584 },
8585/* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
8586 {
8587 { 0, 0, 0, 0 },
8588 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8589 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820b00 }
8590 },
8591/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8592 {
8593 { 0, 0, 0, 0 },
8594 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8595 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40b00 }
8596 },
8597/* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
8598 {
8599 { 0, 0, 0, 0 },
8600 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8601 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840b00 }
8602 },
8603/* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8604 {
8605 { 0, 0, 0, 0 },
8606 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8607 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60b00 }
8608 },
8609/* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
8610 {
8611 { 0, 0, 0, 0 },
8612 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8613 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860b00 }
8614 },
8615/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
8616 {
8617 { 0, 0, 0, 0 },
8618 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
8619 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28b00 }
8620 },
8621/* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
8622 {
8623 { 0, 0, 0, 0 },
8624 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
8625 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828b00 }
8626 },
8627/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
8628 {
8629 { 0, 0, 0, 0 },
8630 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
8631 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48b00 }
8632 },
8633/* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
8634 {
8635 { 0, 0, 0, 0 },
8636 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
8637 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848b00 }
8638 },
8639/* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
8640 {
8641 { 0, 0, 0, 0 },
8642 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
8643 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2cb00 }
8644 },
8645/* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
8646 {
8647 { 0, 0, 0, 0 },
8648 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
8649 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182cb00 }
8650 },
8651/* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
8652 {
8653 { 0, 0, 0, 0 },
8654 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
8655 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4cb00 }
8656 },
8657/* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
8658 {
8659 { 0, 0, 0, 0 },
8660 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
8661 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184cb00 }
8662 },
8663/* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
8664 {
8665 { 0, 0, 0, 0 },
8666 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
8667 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6cb00 }
8668 },
8669/* extz [$Src32AnPrefixed],${Dsp-24-u16} */
8670 {
8671 { 0, 0, 0, 0 },
8672 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
8673 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186cb00 }
8674 },
8675/* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
8676 {
8677 { 0, 0, 0, 0 },
8678 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
8679 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68b00 }
8680 },
8681/* extz [$Src32AnPrefixed],${Dsp-24-u24} */
8682 {
8683 { 0, 0, 0, 0 },
8684 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
8685 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868b00 }
8686 },
8687/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8688 {
8689 { 0, 0, 0, 0 },
8690 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8691 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980700 }
8692 },
8693/* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
8694 {
8695 { 0, 0, 0, 0 },
8696 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8697 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982700 }
8698 },
8699/* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
8700 {
8701 { 0, 0, 0, 0 },
8702 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8703 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983700 }
8704 },
8705/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8706 {
8707 { 0, 0, 0, 0 },
8708 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8709 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908700 }
8710 },
8711/* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
8712 {
8713 { 0, 0, 0, 0 },
8714 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8715 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190a700 }
8716 },
8717/* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
8718 {
8719 { 0, 0, 0, 0 },
8720 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8721 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190b700 }
8722 },
8723/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8724 {
8725 { 0, 0, 0, 0 },
8726 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8727 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900700 }
8728 },
8729/* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
8730 {
8731 { 0, 0, 0, 0 },
8732 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8733 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902700 }
8734 },
8735/* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
8736 {
8737 { 0, 0, 0, 0 },
8738 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8739 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903700 }
8740 },
8741/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
8742 {
8743 { 0, 0, 0, 0 },
8744 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8745 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920700 }
8746 },
8747/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8748 {
8749 { 0, 0, 0, 0 },
8750 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8751 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922700 }
8752 },
8753/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8754 {
8755 { 0, 0, 0, 0 },
8756 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8757 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923700 }
8758 },
8759/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
8760 {
8761 { 0, 0, 0, 0 },
8762 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8763 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940700 }
8764 },
8765/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8766 {
8767 { 0, 0, 0, 0 },
8768 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8769 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942700 }
8770 },
8771/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8772 {
8773 { 0, 0, 0, 0 },
8774 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8775 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943700 }
8776 },
8777/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
8778 {
8779 { 0, 0, 0, 0 },
8780 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8781 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960700 }
8782 },
8783/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8784 {
8785 { 0, 0, 0, 0 },
8786 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8787 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962700 }
8788 },
8789/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8790 {
8791 { 0, 0, 0, 0 },
8792 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8793 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963700 }
8794 },
8795/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8796 {
8797 { 0, 0, 0, 0 },
8798 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8799 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928700 }
8800 },
8801/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8802 {
8803 { 0, 0, 0, 0 },
8804 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8805 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192a700 }
8806 },
8807/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8808 {
8809 { 0, 0, 0, 0 },
8810 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8811 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192b700 }
8812 },
8813/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8814 {
8815 { 0, 0, 0, 0 },
8816 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8817 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948700 }
8818 },
8819/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8820 {
8821 { 0, 0, 0, 0 },
8822 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8823 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194a700 }
8824 },
8825/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8826 {
8827 { 0, 0, 0, 0 },
8828 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8829 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194b700 }
8830 },
8831/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8832 {
8833 { 0, 0, 0, 0 },
8834 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8835 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192c700 }
8836 },
8837/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8838 {
8839 { 0, 0, 0, 0 },
8840 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8841 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192e700 }
8842 },
8843/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8844 {
8845 { 0, 0, 0, 0 },
8846 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8847 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192f700 }
8848 },
8849/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8850 {
8851 { 0, 0, 0, 0 },
8852 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8853 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194c700 }
8854 },
8855/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8856 {
8857 { 0, 0, 0, 0 },
8858 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8859 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194e700 }
8860 },
8861/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8862 {
8863 { 0, 0, 0, 0 },
8864 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8865 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194f700 }
8866 },
8867/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8868 {
8869 { 0, 0, 0, 0 },
8870 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
8871 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196c700 }
8872 },
8873/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8874 {
8875 { 0, 0, 0, 0 },
8876 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8877 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196e700 }
8878 },
8879/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8880 {
8881 { 0, 0, 0, 0 },
8882 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8883 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196f700 }
8884 },
8885/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8886 {
8887 { 0, 0, 0, 0 },
8888 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
8889 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968700 }
8890 },
8891/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8892 {
8893 { 0, 0, 0, 0 },
8894 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8895 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196a700 }
8896 },
8897/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8898 {
8899 { 0, 0, 0, 0 },
8900 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8901 & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196b700 }
8902 },
8903/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8904 {
8905 { 0, 0, 0, 0 },
8906 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8907 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80700 }
8908 },
8909/* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
8910 {
8911 { 0, 0, 0, 0 },
8912 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8913 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82700 }
8914 },
8915/* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
8916 {
8917 { 0, 0, 0, 0 },
8918 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8919 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83700 }
8920 },
8921/* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
8922 {
8923 { 0, 0, 0, 0 },
8924 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
8925 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83700 }
8926 },
8927/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8928 {
8929 { 0, 0, 0, 0 },
8930 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8931 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08700 }
8932 },
8933/* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
8934 {
8935 { 0, 0, 0, 0 },
8936 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8937 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0a700 }
8938 },
8939/* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
8940 {
8941 { 0, 0, 0, 0 },
8942 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8943 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0b700 }
8944 },
8945/* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
8946 {
8947 { 0, 0, 0, 0 },
8948 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
8949 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0b700 }
8950 },
8951/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8952 {
8953 { 0, 0, 0, 0 },
8954 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8955 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00700 }
8956 },
8957/* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8958 {
8959 { 0, 0, 0, 0 },
8960 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8961 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02700 }
8962 },
8963/* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8964 {
8965 { 0, 0, 0, 0 },
8966 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8967 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03700 }
8968 },
8969/* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
8970 {
8971 { 0, 0, 0, 0 },
8972 { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8973 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03700 }
8974 },
8975/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8976 {
8977 { 0, 0, 0, 0 },
8978 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8979 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20700 }
8980 },
8981/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8982 {
8983 { 0, 0, 0, 0 },
8984 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8985 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22700 }
8986 },
8987/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8988 {
8989 { 0, 0, 0, 0 },
8990 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8991 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23700 }
8992 },
8993/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8994 {
8995 { 0, 0, 0, 0 },
8996 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8997 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23700 }
8998 },
8999/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
9000 {
9001 { 0, 0, 0, 0 },
9002 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9003 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40700 }
9004 },
9005/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
9006 {
9007 { 0, 0, 0, 0 },
9008 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9009 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42700 }
9010 },
9011/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
9012 {
9013 { 0, 0, 0, 0 },
9014 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9015 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43700 }
9016 },
9017/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
9018 {
9019 { 0, 0, 0, 0 },
9020 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9021 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43700 }
9022 },
9023/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
9024 {
9025 { 0, 0, 0, 0 },
9026 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9027 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60700 }
9028 },
9029/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
9030 {
9031 { 0, 0, 0, 0 },
9032 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9033 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62700 }
9034 },
9035/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
9036 {
9037 { 0, 0, 0, 0 },
9038 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9039 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63700 }
9040 },
9041/* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
9042 {
9043 { 0, 0, 0, 0 },
9044 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9045 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63700 }
9046 },
9047/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
9048 {
9049 { 0, 0, 0, 0 },
9050 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9051 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28700 }
9052 },
9053/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
9054 {
9055 { 0, 0, 0, 0 },
9056 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9057 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2a700 }
9058 },
9059/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
9060 {
9061 { 0, 0, 0, 0 },
9062 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9063 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2b700 }
9064 },
9065/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
9066 {
9067 { 0, 0, 0, 0 },
9068 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9069 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2b700 }
9070 },
9071/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
9072 {
9073 { 0, 0, 0, 0 },
9074 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9075 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48700 }
9076 },
9077/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
9078 {
9079 { 0, 0, 0, 0 },
9080 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9081 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4a700 }
9082 },
9083/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
9084 {
9085 { 0, 0, 0, 0 },
9086 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9087 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4b700 }
9088 },
9089/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
9090 {
9091 { 0, 0, 0, 0 },
9092 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9093 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4b700 }
9094 },
9095/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
9096 {
9097 { 0, 0, 0, 0 },
9098 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9099 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2c700 }
9100 },
9101/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
9102 {
9103 { 0, 0, 0, 0 },
9104 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9105 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2e700 }
9106 },
9107/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
9108 {
9109 { 0, 0, 0, 0 },
9110 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9111 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2f700 }
9112 },
9113/* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
9114 {
9115 { 0, 0, 0, 0 },
9116 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9117 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2f700 }
9118 },
9119/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
9120 {
9121 { 0, 0, 0, 0 },
9122 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9123 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4c700 }
9124 },
9125/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
9126 {
9127 { 0, 0, 0, 0 },
9128 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9129 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4e700 }
9130 },
9131/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
9132 {
9133 { 0, 0, 0, 0 },
9134 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9135 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4f700 }
9136 },
9137/* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
9138 {
9139 { 0, 0, 0, 0 },
9140 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9141 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4f700 }
9142 },
9143/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
9144 {
9145 { 0, 0, 0, 0 },
9146 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
9147 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6c700 }
9148 },
9149/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
9150 {
9151 { 0, 0, 0, 0 },
9152 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
9153 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6e700 }
9154 },
9155/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
9156 {
9157 { 0, 0, 0, 0 },
9158 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
9159 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6f700 }
9160 },
9161/* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
9162 {
9163 { 0, 0, 0, 0 },
9164 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
9165 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6f700 }
9166 },
9167/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
9168 {
9169 { 0, 0, 0, 0 },
9170 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
9171 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68700 }
9172 },
9173/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
9174 {
9175 { 0, 0, 0, 0 },
9176 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
9177 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6a700 }
9178 },
9179/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
9180 {
9181 { 0, 0, 0, 0 },
9182 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
9183 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6b700 }
9184 },
9185/* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
9186 {
9187 { 0, 0, 0, 0 },
9188 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
9189 & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6b700 }
9190 },
9191/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
9192 {
9193 { 0, 0, 0, 0 },
9194 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
9195 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80700 }
9196 },
9197/* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
9198 {
9199 { 0, 0, 0, 0 },
9200 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
9201 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82700 }
9202 },
9203/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
9204 {
9205 { 0, 0, 0, 0 },
9206 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
9207 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08700 }
9208 },
9209/* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
9210 {
9211 { 0, 0, 0, 0 },
9212 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
9213 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0a700 }
9214 },
9215/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
9216 {
9217 { 0, 0, 0, 0 },
9218 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9219 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00700 }
9220 },
9221/* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
9222 {
9223 { 0, 0, 0, 0 },
9224 { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9225 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02700 }
9226 },
9227/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
9228 {
9229 { 0, 0, 0, 0 },
9230 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9231 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20700 }
9232 },
9233/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
9234 {
9235 { 0, 0, 0, 0 },
9236 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9237 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22700 }
9238 },
9239/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
9240 {
9241 { 0, 0, 0, 0 },
9242 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9243 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40700 }
9244 },
9245/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
9246 {
9247 { 0, 0, 0, 0 },
9248 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9249 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42700 }
9250 },
9251/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
9252 {
9253 { 0, 0, 0, 0 },
9254 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9255 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60700 }
9256 },
9257/* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
9258 {
9259 { 0, 0, 0, 0 },
9260 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9261 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62700 }
9262 },
9263/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
9264 {
9265 { 0, 0, 0, 0 },
9266 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
9267 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28700 }
9268 },
9269/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
9270 {
9271 { 0, 0, 0, 0 },
9272 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
9273 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2a700 }
9274 },
9275/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
9276 {
9277 { 0, 0, 0, 0 },
9278 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
9279 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48700 }
9280 },
9281/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
9282 {
9283 { 0, 0, 0, 0 },
9284 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
9285 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4a700 }
9286 },
9287/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
9288 {
9289 { 0, 0, 0, 0 },
9290 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
9291 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2c700 }
9292 },
9293/* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
9294 {
9295 { 0, 0, 0, 0 },
9296 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
9297 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2e700 }
9298 },
9299/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
9300 {
9301 { 0, 0, 0, 0 },
9302 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
9303 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4c700 }
9304 },
9305/* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
9306 {
9307 { 0, 0, 0, 0 },
9308 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
9309 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4e700 }
9310 },
9311/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
9312 {
9313 { 0, 0, 0, 0 },
9314 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
9315 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6c700 }
9316 },
9317/* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
9318 {
9319 { 0, 0, 0, 0 },
9320 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
9321 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6e700 }
9322 },
9323/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
9324 {
9325 { 0, 0, 0, 0 },
9326 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
9327 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68700 }
9328 },
9329/* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
9330 {
9331 { 0, 0, 0, 0 },
9332 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
9333 & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6a700 }
9334 },
9335/* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
9336 {
9337 { 0, 0, 0, 0 },
9338 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } },
9339 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c807 }
9340 },
9341/* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
9342 {
9343 { 0, 0, 0, 0 },
9344 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
9345 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x18807 }
9346 },
9347/* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
9348 {
9349 { 0, 0, 0, 0 },
9350 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } },
9351 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c087 }
9352 },
9353/* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
9354 {
9355 { 0, 0, 0, 0 },
9356 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
9357 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x18087 }
9358 },
9359/* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
9360 {
9361 { 0, 0, 0, 0 },
9362 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9363 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c007 }
9364 },
9365/* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
9366 {
9367 { 0, 0, 0, 0 },
9368 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9369 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x18007 }
9370 },
9371/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9372 {
9373 { 0, 0, 0, 0 },
9374 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9375 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20700 }
9376 },
9377/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
9378 {
9379 { 0, 0, 0, 0 },
9380 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9381 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820700 }
9382 },
9383/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9384 {
9385 { 0, 0, 0, 0 },
9386 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9387 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40700 }
9388 },
9389/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
9390 {
9391 { 0, 0, 0, 0 },
9392 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9393 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840700 }
9394 },
9395/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9396 {
9397 { 0, 0, 0, 0 },
9398 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9399 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60700 }
9400 },
9401/* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
9402 {
9403 { 0, 0, 0, 0 },
9404 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9405 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860700 }
9406 },
9407/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
9408 {
9409 { 0, 0, 0, 0 },
9410 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9411 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28700 }
9412 },
9413/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
9414 {
9415 { 0, 0, 0, 0 },
9416 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9417 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828700 }
9418 },
9419/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
9420 {
9421 { 0, 0, 0, 0 },
9422 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9423 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48700 }
9424 },
9425/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
9426 {
9427 { 0, 0, 0, 0 },
9428 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9429 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848700 }
9430 },
9431/* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
9432 {
9433 { 0, 0, 0, 0 },
9434 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9435 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2c700 }
9436 },
9437/* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
9438 {
9439 { 0, 0, 0, 0 },
9440 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9441 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182c700 }
9442 },
9443/* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
9444 {
9445 { 0, 0, 0, 0 },
9446 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9447 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4c700 }
9448 },
9449/* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
9450 {
9451 { 0, 0, 0, 0 },
9452 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9453 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184c700 }
9454 },
9455/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
9456 {
9457 { 0, 0, 0, 0 },
9458 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
9459 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6c700 }
9460 },
9461/* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
9462 {
9463 { 0, 0, 0, 0 },
9464 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
9465 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186c700 }
9466 },
9467/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
9468 {
9469 { 0, 0, 0, 0 },
9470 { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
9471 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68700 }
9472 },
9473/* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
9474 {
9475 { 0, 0, 0, 0 },
9476 { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
9477 & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868700 }
9478 },
9479/* exts.w $Dst32RnExtUnprefixedHI */
9480 {
9481 { 0, 0, 0, 0 },
9482 { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDHI), 0 } },
9483 & ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI, { 0xc99e }
9484 },
9485/* exts.w $Dst32AnUnprefixedSI */
9486 {
9487 { 0, 0, 0, 0 },
9488 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
9489 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc19e }
9490 },
9491/* exts.w [$Dst32AnExtUnprefixed] */
9492 {
9493 { 0, 0, 0, 0 },
9494 { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9495 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI, { 0xc11e }
9496 },
9497/* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
9498 {
9499 { 0, 0, 0, 0 },
9500 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9501 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI, { 0xc31e00 }
9502 },
9503/* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
9504 {
9505 { 0, 0, 0, 0 },
9506 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9507 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI, { 0xc51e0000 }
9508 },
9509/* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
9510 {
9511 { 0, 0, 0, 0 },
9512 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9513 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI, { 0xc71e0000 }
9514 },
9515/* exts.w ${Dsp-16-u8}[sb] */
9516 {
9517 { 0, 0, 0, 0 },
9518 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9519 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI, { 0xc39e00 }
9520 },
9521/* exts.w ${Dsp-16-u16}[sb] */
9522 {
9523 { 0, 0, 0, 0 },
9524 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9525 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI, { 0xc59e0000 }
9526 },
9527/* exts.w ${Dsp-16-s8}[fb] */
9528 {
9529 { 0, 0, 0, 0 },
9530 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9531 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI, { 0xc3de00 }
9532 },
9533/* exts.w ${Dsp-16-s16}[fb] */
9534 {
9535 { 0, 0, 0, 0 },
9536 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
9537 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI, { 0xc5de0000 }
9538 },
9539/* exts.w ${Dsp-16-u16} */
9540 {
9541 { 0, 0, 0, 0 },
9542 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9543 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI, { 0xc7de0000 }
9544 },
9545/* exts.w ${Dsp-16-u24} */
9546 {
9547 { 0, 0, 0, 0 },
9548 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
9549 & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI, { 0xc79e0000 }
9550 },
9551/* exts.b $Dst32RnExtUnprefixedQI */
9552 {
9553 { 0, 0, 0, 0 },
9554 { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDQI), 0 } },
9555 & ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI, { 0xc89e }
9556 },
9557/* exts.b $Dst32AnUnprefixedHI */
9558 {
9559 { 0, 0, 0, 0 },
9560 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
9561 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc09e }
9562 },
9563/* exts.b [$Dst32AnExtUnprefixed] */
9564 {
9565 { 0, 0, 0, 0 },
9566 { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9567 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI, { 0xc01e }
9568 },
9569/* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
9570 {
9571 { 0, 0, 0, 0 },
9572 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9573 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI, { 0xc21e00 }
9574 },
9575/* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
9576 {
9577 { 0, 0, 0, 0 },
9578 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9579 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI, { 0xc41e0000 }
9580 },
9581/* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
9582 {
9583 { 0, 0, 0, 0 },
9584 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9585 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI, { 0xc61e0000 }
9586 },
9587/* exts.b ${Dsp-16-u8}[sb] */
9588 {
9589 { 0, 0, 0, 0 },
9590 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9591 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI, { 0xc29e00 }
9592 },
9593/* exts.b ${Dsp-16-u16}[sb] */
9594 {
9595 { 0, 0, 0, 0 },
9596 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9597 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI, { 0xc49e0000 }
9598 },
9599/* exts.b ${Dsp-16-s8}[fb] */
9600 {
9601 { 0, 0, 0, 0 },
9602 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9603 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI, { 0xc2de00 }
9604 },
9605/* exts.b ${Dsp-16-s16}[fb] */
9606 {
9607 { 0, 0, 0, 0 },
9608 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
9609 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI, { 0xc4de0000 }
9610 },
9611/* exts.b ${Dsp-16-u16} */
9612 {
9613 { 0, 0, 0, 0 },
9614 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9615 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI, { 0xc6de0000 }
9616 },
9617/* exts.b ${Dsp-16-u24} */
9618 {
9619 { 0, 0, 0, 0 },
9620 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
9621 & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI, { 0xc69e0000 }
9622 },
9623/* exts.b $Dst16RnExtQI */
9624 {
9625 { 0, 0, 0, 0 },
9626 { { MNEM, ' ', OP (DST16RNEXTQI), 0 } },
9627 & ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI, { 0x7c60 }
9628 },
9629/* exts.b [$Dst16An] */
9630 {
9631 { 0, 0, 0, 0 },
9632 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
9633 & ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI, { 0x7c66 }
9634 },
9635/* exts.b ${Dsp-16-u8}[$Dst16An] */
9636 {
9637 { 0, 0, 0, 0 },
9638 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
9639 & ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI, { 0x7c6800 }
9640 },
9641/* exts.b ${Dsp-16-u16}[$Dst16An] */
9642 {
9643 { 0, 0, 0, 0 },
9644 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
9645 & ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI, { 0x7c6c0000 }
9646 },
9647/* exts.b ${Dsp-16-u8}[sb] */
9648 {
9649 { 0, 0, 0, 0 },
9650 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9651 & ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI, { 0x7c6a00 }
9652 },
9653/* exts.b ${Dsp-16-u16}[sb] */
9654 {
9655 { 0, 0, 0, 0 },
9656 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9657 & ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI, { 0x7c6e0000 }
9658 },
9659/* exts.b ${Dsp-16-s8}[fb] */
9660 {
9661 { 0, 0, 0, 0 },
9662 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9663 & ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI, { 0x7c6b00 }
9664 },
9665/* exts.b ${Dsp-16-u16} */
9666 {
9667 { 0, 0, 0, 0 },
9668 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9669 & ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI, { 0x7c6f0000 }
9670 },
9671/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
9672 {
9673 { 0, 0, 0, 0 },
9674 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9675 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990900 }
9676 },
9677/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
9678 {
9679 { 0, 0, 0, 0 },
9680 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9681 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992900 }
9682 },
9683/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
9684 {
9685 { 0, 0, 0, 0 },
9686 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9687 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993900 }
9688 },
9689/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
9690 {
9691 { 0, 0, 0, 0 },
9692 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9693 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918900 }
9694 },
9695/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
9696 {
9697 { 0, 0, 0, 0 },
9698 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9699 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a900 }
9700 },
9701/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
9702 {
9703 { 0, 0, 0, 0 },
9704 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9705 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b900 }
9706 },
9707/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
9708 {
9709 { 0, 0, 0, 0 },
9710 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9711 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910900 }
9712 },
9713/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
9714 {
9715 { 0, 0, 0, 0 },
9716 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9717 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912900 }
9718 },
9719/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
9720 {
9721 { 0, 0, 0, 0 },
9722 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9723 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913900 }
9724 },
9725/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9726 {
9727 { 0, 0, 0, 0 },
9728 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9729 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93090000 }
9730 },
9731/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9732 {
9733 { 0, 0, 0, 0 },
9734 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9735 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93290000 }
9736 },
9737/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9738 {
9739 { 0, 0, 0, 0 },
9740 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9741 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93390000 }
9742 },
9743/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9744 {
9745 { 0, 0, 0, 0 },
9746 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9747 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95090000 }
9748 },
9749/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9750 {
9751 { 0, 0, 0, 0 },
9752 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9753 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95290000 }
9754 },
9755/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9756 {
9757 { 0, 0, 0, 0 },
9758 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9759 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95390000 }
9760 },
9761/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9762 {
9763 { 0, 0, 0, 0 },
9764 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9765 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97090000 }
9766 },
9767/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9768 {
9769 { 0, 0, 0, 0 },
9770 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9771 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97290000 }
9772 },
9773/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9774 {
9775 { 0, 0, 0, 0 },
9776 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9777 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97390000 }
9778 },
9779/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
9780 {
9781 { 0, 0, 0, 0 },
9782 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9783 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93890000 }
9784 },
9785/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9786 {
9787 { 0, 0, 0, 0 },
9788 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9789 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a90000 }
9790 },
9791/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9792 {
9793 { 0, 0, 0, 0 },
9794 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9795 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b90000 }
9796 },
9797/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
9798 {
9799 { 0, 0, 0, 0 },
9800 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9801 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95890000 }
9802 },
9803/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9804 {
9805 { 0, 0, 0, 0 },
9806 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9807 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a90000 }
9808 },
9809/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9810 {
9811 { 0, 0, 0, 0 },
9812 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9813 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b90000 }
9814 },
9815/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
9816 {
9817 { 0, 0, 0, 0 },
9818 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9819 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c90000 }
9820 },
9821/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9822 {
9823 { 0, 0, 0, 0 },
9824 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9825 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e90000 }
9826 },
9827/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9828 {
9829 { 0, 0, 0, 0 },
9830 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9831 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f90000 }
9832 },
9833/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
9834 {
9835 { 0, 0, 0, 0 },
9836 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9837 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c90000 }
9838 },
9839/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
9840 {
9841 { 0, 0, 0, 0 },
9842 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9843 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e90000 }
9844 },
9845/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
9846 {
9847 { 0, 0, 0, 0 },
9848 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9849 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f90000 }
9850 },
9851/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
9852 {
9853 { 0, 0, 0, 0 },
9854 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
9855 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c90000 }
9856 },
9857/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9858 {
9859 { 0, 0, 0, 0 },
9860 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
9861 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e90000 }
9862 },
9863/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9864 {
9865 { 0, 0, 0, 0 },
9866 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
9867 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f90000 }
9868 },
9869/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
9870 {
9871 { 0, 0, 0, 0 },
9872 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
9873 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97890000 }
9874 },
9875/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
9876 {
9877 { 0, 0, 0, 0 },
9878 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
9879 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a90000 }
9880 },
9881/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
9882 {
9883 { 0, 0, 0, 0 },
9884 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
9885 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b90000 }
9886 },
9887/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
9888 {
9889 { 0, 0, 0, 0 },
9890 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9891 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9090000 }
9892 },
9893/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
9894 {
9895 { 0, 0, 0, 0 },
9896 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9897 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9290000 }
9898 },
9899/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
9900 {
9901 { 0, 0, 0, 0 },
9902 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9903 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9390000 }
9904 },
9905/* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
9906 {
9907 { 0, 0, 0, 0 },
9908 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9909 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9390000 }
9910 },
9911/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
9912 {
9913 { 0, 0, 0, 0 },
9914 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9915 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1890000 }
9916 },
9917/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
9918 {
9919 { 0, 0, 0, 0 },
9920 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9921 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a90000 }
9922 },
9923/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
9924 {
9925 { 0, 0, 0, 0 },
9926 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9927 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b90000 }
9928 },
9929/* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
9930 {
9931 { 0, 0, 0, 0 },
9932 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9933 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b90000 }
9934 },
9935/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
9936 {
9937 { 0, 0, 0, 0 },
9938 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9939 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1090000 }
9940 },
9941/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
9942 {
9943 { 0, 0, 0, 0 },
9944 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9945 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1290000 }
9946 },
9947/* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
9948 {
9949 { 0, 0, 0, 0 },
9950 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9951 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1390000 }
9952 },
9953/* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
9954 {
9955 { 0, 0, 0, 0 },
9956 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9957 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1390000 }
9958 },
9959/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9960 {
9961 { 0, 0, 0, 0 },
9962 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9963 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3090000 }
9964 },
9965/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9966 {
9967 { 0, 0, 0, 0 },
9968 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9969 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3290000 }
9970 },
9971/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9972 {
9973 { 0, 0, 0, 0 },
9974 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9975 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3390000 }
9976 },
9977/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
9978 {
9979 { 0, 0, 0, 0 },
9980 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9981 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3390000 }
9982 },
9983/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9984 {
9985 { 0, 0, 0, 0 },
9986 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9987 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5090000 }
9988 },
9989/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9990 {
9991 { 0, 0, 0, 0 },
9992 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9993 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5290000 }
9994 },
9995/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9996 {
9997 { 0, 0, 0, 0 },
9998 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9999 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5390000 }
10000 },
10001/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10002 {
10003 { 0, 0, 0, 0 },
10004 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10005 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5390000 }
10006 },
10007/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10008 {
10009 { 0, 0, 0, 0 },
10010 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10011 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7090000 }
10012 },
10013/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10014 {
10015 { 0, 0, 0, 0 },
10016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10017 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7290000 }
10018 },
10019/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10020 {
10021 { 0, 0, 0, 0 },
10022 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10023 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7390000 }
10024 },
10025/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10026 {
10027 { 0, 0, 0, 0 },
10028 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10029 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7390000 }
10030 },
10031/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10032 {
10033 { 0, 0, 0, 0 },
10034 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10035 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3890000 }
10036 },
10037/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10038 {
10039 { 0, 0, 0, 0 },
10040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10041 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a90000 }
10042 },
10043/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10044 {
10045 { 0, 0, 0, 0 },
10046 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10047 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b90000 }
10048 },
10049/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10050 {
10051 { 0, 0, 0, 0 },
10052 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10053 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b90000 }
10054 },
10055/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10056 {
10057 { 0, 0, 0, 0 },
10058 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10059 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5890000 }
10060 },
10061/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10062 {
10063 { 0, 0, 0, 0 },
10064 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10065 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a90000 }
10066 },
10067/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10068 {
10069 { 0, 0, 0, 0 },
10070 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10071 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b90000 }
10072 },
10073/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10074 {
10075 { 0, 0, 0, 0 },
10076 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10077 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b90000 }
10078 },
10079/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10080 {
10081 { 0, 0, 0, 0 },
10082 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10083 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c90000 }
10084 },
10085/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10086 {
10087 { 0, 0, 0, 0 },
10088 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10089 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e90000 }
10090 },
10091/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10092 {
10093 { 0, 0, 0, 0 },
10094 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10095 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f90000 }
10096 },
10097/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10098 {
10099 { 0, 0, 0, 0 },
10100 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10101 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f90000 }
10102 },
10103/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10104 {
10105 { 0, 0, 0, 0 },
10106 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10107 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c90000 }
10108 },
10109/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10110 {
10111 { 0, 0, 0, 0 },
10112 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10113 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e90000 }
10114 },
10115/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10116 {
10117 { 0, 0, 0, 0 },
10118 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10119 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f90000 }
10120 },
10121/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10122 {
10123 { 0, 0, 0, 0 },
10124 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10125 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f90000 }
10126 },
10127/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10128 {
10129 { 0, 0, 0, 0 },
10130 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
10131 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c90000 }
10132 },
10133/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10134 {
10135 { 0, 0, 0, 0 },
10136 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10137 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e90000 }
10138 },
10139/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10140 {
10141 { 0, 0, 0, 0 },
10142 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10143 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f90000 }
10144 },
10145/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
10146 {
10147 { 0, 0, 0, 0 },
10148 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
10149 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f90000 }
10150 },
10151/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10152 {
10153 { 0, 0, 0, 0 },
10154 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
10155 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7890000 }
10156 },
10157/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10158 {
10159 { 0, 0, 0, 0 },
10160 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
10161 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a90000 }
10162 },
10163/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10164 {
10165 { 0, 0, 0, 0 },
10166 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
10167 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b90000 }
10168 },
10169/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
10170 {
10171 { 0, 0, 0, 0 },
10172 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
10173 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b90000 }
10174 },
10175/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
10176 {
10177 { 0, 0, 0, 0 },
10178 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10179 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9090000 }
10180 },
10181/* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
10182 {
10183 { 0, 0, 0, 0 },
10184 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10185 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9290000 }
10186 },
10187/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
10188 {
10189 { 0, 0, 0, 0 },
10190 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10191 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1890000 }
10192 },
10193/* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
10194 {
10195 { 0, 0, 0, 0 },
10196 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10197 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a90000 }
10198 },
10199/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10200 {
10201 { 0, 0, 0, 0 },
10202 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10203 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1090000 }
10204 },
10205/* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10206 {
10207 { 0, 0, 0, 0 },
10208 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10209 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1290000 }
10210 },
10211/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10212 {
10213 { 0, 0, 0, 0 },
10214 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10215 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3090000 }
10216 },
10217/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10218 {
10219 { 0, 0, 0, 0 },
10220 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10221 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3290000 }
10222 },
10223/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10224 {
10225 { 0, 0, 0, 0 },
10226 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10227 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5090000 }
10228 },
10229/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10230 {
10231 { 0, 0, 0, 0 },
10232 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10233 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5290000 }
10234 },
10235/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10236 {
10237 { 0, 0, 0, 0 },
10238 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10239 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7090000 }
10240 },
10241/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10242 {
10243 { 0, 0, 0, 0 },
10244 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10245 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7290000 }
10246 },
10247/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10248 {
10249 { 0, 0, 0, 0 },
10250 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10251 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3890000 }
10252 },
10253/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10254 {
10255 { 0, 0, 0, 0 },
10256 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10257 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a90000 }
10258 },
10259/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10260 {
10261 { 0, 0, 0, 0 },
10262 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10263 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5890000 }
10264 },
10265/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10266 {
10267 { 0, 0, 0, 0 },
10268 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10269 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a90000 }
10270 },
10271/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10272 {
10273 { 0, 0, 0, 0 },
10274 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10275 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c90000 }
10276 },
10277/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10278 {
10279 { 0, 0, 0, 0 },
10280 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10281 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e90000 }
10282 },
10283/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10284 {
10285 { 0, 0, 0, 0 },
10286 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10287 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c90000 }
10288 },
10289/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10290 {
10291 { 0, 0, 0, 0 },
10292 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10293 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e90000 }
10294 },
10295/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10296 {
10297 { 0, 0, 0, 0 },
10298 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
10299 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c90000 }
10300 },
10301/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
10302 {
10303 { 0, 0, 0, 0 },
10304 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
10305 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e90000 }
10306 },
10307/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10308 {
10309 { 0, 0, 0, 0 },
10310 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
10311 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7890000 }
10312 },
10313/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
10314 {
10315 { 0, 0, 0, 0 },
10316 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
10317 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a90000 }
10318 },
10319/* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
10320 {
10321 { 0, 0, 0, 0 },
10322 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10323 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc909 }
10324 },
10325/* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
10326 {
10327 { 0, 0, 0, 0 },
10328 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10329 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8929 }
10330 },
10331/* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
10332 {
10333 { 0, 0, 0, 0 },
10334 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10335 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8909 }
10336 },
10337/* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
10338 {
10339 { 0, 0, 0, 0 },
10340 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10341 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc189 }
10342 },
10343/* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
10344 {
10345 { 0, 0, 0, 0 },
10346 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10347 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a9 }
10348 },
10349/* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
10350 {
10351 { 0, 0, 0, 0 },
10352 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10353 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8189 }
10354 },
10355/* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
10356 {
10357 { 0, 0, 0, 0 },
10358 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10359 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc109 }
10360 },
10361/* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
10362 {
10363 { 0, 0, 0, 0 },
10364 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10365 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8129 }
10366 },
10367/* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10368 {
10369 { 0, 0, 0, 0 },
10370 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10371 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8109 }
10372 },
10373/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10374 {
10375 { 0, 0, 0, 0 },
10376 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10377 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30900 }
10378 },
10379/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10380 {
10381 { 0, 0, 0, 0 },
10382 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10383 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832900 }
10384 },
10385/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10386 {
10387 { 0, 0, 0, 0 },
10388 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10389 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830900 }
10390 },
10391/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10392 {
10393 { 0, 0, 0, 0 },
10394 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10395 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5090000 }
10396 },
10397/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10398 {
10399 { 0, 0, 0, 0 },
10400 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10401 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85290000 }
10402 },
10403/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10404 {
10405 { 0, 0, 0, 0 },
10406 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10407 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85090000 }
10408 },
10409/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10410 {
10411 { 0, 0, 0, 0 },
10412 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10413 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7090000 }
10414 },
10415/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10416 {
10417 { 0, 0, 0, 0 },
10418 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10419 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87290000 }
10420 },
10421/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10422 {
10423 { 0, 0, 0, 0 },
10424 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10425 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87090000 }
10426 },
10427/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
10428 {
10429 { 0, 0, 0, 0 },
10430 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10431 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38900 }
10432 },
10433/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
10434 {
10435 { 0, 0, 0, 0 },
10436 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10437 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a900 }
10438 },
10439/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10440 {
10441 { 0, 0, 0, 0 },
10442 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10443 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838900 }
10444 },
10445/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
10446 {
10447 { 0, 0, 0, 0 },
10448 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10449 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5890000 }
10450 },
10451/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
10452 {
10453 { 0, 0, 0, 0 },
10454 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10455 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a90000 }
10456 },
10457/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10458 {
10459 { 0, 0, 0, 0 },
10460 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10461 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85890000 }
10462 },
10463/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
10464 {
10465 { 0, 0, 0, 0 },
10466 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10467 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c900 }
10468 },
10469/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
10470 {
10471 { 0, 0, 0, 0 },
10472 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10473 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e900 }
10474 },
10475/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10476 {
10477 { 0, 0, 0, 0 },
10478 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10479 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c900 }
10480 },
10481/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
10482 {
10483 { 0, 0, 0, 0 },
10484 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10485 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c90000 }
10486 },
10487/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
10488 {
10489 { 0, 0, 0, 0 },
10490 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10491 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e90000 }
10492 },
10493/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10494 {
10495 { 0, 0, 0, 0 },
10496 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10497 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c90000 }
10498 },
10499/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
10500 {
10501 { 0, 0, 0, 0 },
10502 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
10503 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c90000 }
10504 },
10505/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
10506 {
10507 { 0, 0, 0, 0 },
10508 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
10509 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e90000 }
10510 },
10511/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10512 {
10513 { 0, 0, 0, 0 },
10514 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
10515 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c90000 }
10516 },
10517/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
10518 {
10519 { 0, 0, 0, 0 },
10520 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
10521 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7890000 }
10522 },
10523/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
10524 {
10525 { 0, 0, 0, 0 },
10526 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
10527 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a90000 }
10528 },
10529/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10530 {
10531 { 0, 0, 0, 0 },
10532 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
10533 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87890000 }
10534 },
10535/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
10536 {
10537 { 0, 0, 0, 0 },
10538 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10539 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980900 }
10540 },
10541/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
10542 {
10543 { 0, 0, 0, 0 },
10544 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10545 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982900 }
10546 },
10547/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
10548 {
10549 { 0, 0, 0, 0 },
10550 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10551 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983900 }
10552 },
10553/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
10554 {
10555 { 0, 0, 0, 0 },
10556 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10557 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908900 }
10558 },
10559/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
10560 {
10561 { 0, 0, 0, 0 },
10562 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10563 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a900 }
10564 },
10565/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
10566 {
10567 { 0, 0, 0, 0 },
10568 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10569 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b900 }
10570 },
10571/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10572 {
10573 { 0, 0, 0, 0 },
10574 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10575 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900900 }
10576 },
10577/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10578 {
10579 { 0, 0, 0, 0 },
10580 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10581 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902900 }
10582 },
10583/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10584 {
10585 { 0, 0, 0, 0 },
10586 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10587 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903900 }
10588 },
10589/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10590 {
10591 { 0, 0, 0, 0 },
10592 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10593 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92090000 }
10594 },
10595/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10596 {
10597 { 0, 0, 0, 0 },
10598 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10599 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92290000 }
10600 },
10601/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10602 {
10603 { 0, 0, 0, 0 },
10604 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10605 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92390000 }
10606 },
10607/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10608 {
10609 { 0, 0, 0, 0 },
10610 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10611 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94090000 }
10612 },
10613/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10614 {
10615 { 0, 0, 0, 0 },
10616 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10617 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94290000 }
10618 },
10619/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10620 {
10621 { 0, 0, 0, 0 },
10622 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10623 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94390000 }
10624 },
10625/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10626 {
10627 { 0, 0, 0, 0 },
10628 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10629 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96090000 }
10630 },
10631/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10632 {
10633 { 0, 0, 0, 0 },
10634 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10635 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96290000 }
10636 },
10637/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10638 {
10639 { 0, 0, 0, 0 },
10640 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10641 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96390000 }
10642 },
10643/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10644 {
10645 { 0, 0, 0, 0 },
10646 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10647 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92890000 }
10648 },
10649/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10650 {
10651 { 0, 0, 0, 0 },
10652 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10653 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a90000 }
10654 },
10655/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10656 {
10657 { 0, 0, 0, 0 },
10658 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10659 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b90000 }
10660 },
10661/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10662 {
10663 { 0, 0, 0, 0 },
10664 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10665 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94890000 }
10666 },
10667/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10668 {
10669 { 0, 0, 0, 0 },
10670 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10671 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a90000 }
10672 },
10673/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10674 {
10675 { 0, 0, 0, 0 },
10676 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10677 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b90000 }
10678 },
10679/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10680 {
10681 { 0, 0, 0, 0 },
10682 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10683 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c90000 }
10684 },
10685/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10686 {
10687 { 0, 0, 0, 0 },
10688 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10689 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e90000 }
10690 },
10691/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10692 {
10693 { 0, 0, 0, 0 },
10694 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10695 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f90000 }
10696 },
10697/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10698 {
10699 { 0, 0, 0, 0 },
10700 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10701 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c90000 }
10702 },
10703/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10704 {
10705 { 0, 0, 0, 0 },
10706 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10707 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e90000 }
10708 },
10709/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10710 {
10711 { 0, 0, 0, 0 },
10712 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10713 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f90000 }
10714 },
10715/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10716 {
10717 { 0, 0, 0, 0 },
10718 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
10719 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c90000 }
10720 },
10721/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10722 {
10723 { 0, 0, 0, 0 },
10724 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
10725 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e90000 }
10726 },
10727/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10728 {
10729 { 0, 0, 0, 0 },
10730 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
10731 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f90000 }
10732 },
10733/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10734 {
10735 { 0, 0, 0, 0 },
10736 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
10737 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96890000 }
10738 },
10739/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10740 {
10741 { 0, 0, 0, 0 },
10742 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
10743 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a90000 }
10744 },
10745/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10746 {
10747 { 0, 0, 0, 0 },
10748 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
10749 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b90000 }
10750 },
10751/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
10752 {
10753 { 0, 0, 0, 0 },
10754 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10755 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8090000 }
10756 },
10757/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
10758 {
10759 { 0, 0, 0, 0 },
10760 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10761 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8290000 }
10762 },
10763/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
10764 {
10765 { 0, 0, 0, 0 },
10766 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10767 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8390000 }
10768 },
10769/* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
10770 {
10771 { 0, 0, 0, 0 },
10772 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10773 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8390000 }
10774 },
10775/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
10776 {
10777 { 0, 0, 0, 0 },
10778 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10779 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0890000 }
10780 },
10781/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
10782 {
10783 { 0, 0, 0, 0 },
10784 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10785 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a90000 }
10786 },
10787/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
10788 {
10789 { 0, 0, 0, 0 },
10790 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10791 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b90000 }
10792 },
10793/* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
10794 {
10795 { 0, 0, 0, 0 },
10796 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10797 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b90000 }
10798 },
10799/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10800 {
10801 { 0, 0, 0, 0 },
10802 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10803 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0090000 }
10804 },
10805/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10806 {
10807 { 0, 0, 0, 0 },
10808 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10809 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0290000 }
10810 },
10811/* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10812 {
10813 { 0, 0, 0, 0 },
10814 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10815 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0390000 }
10816 },
10817/* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10818 {
10819 { 0, 0, 0, 0 },
10820 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10821 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0390000 }
10822 },
10823/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10824 {
10825 { 0, 0, 0, 0 },
10826 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10827 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2090000 }
10828 },
10829/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10830 {
10831 { 0, 0, 0, 0 },
10832 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10833 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2290000 }
10834 },
10835/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10836 {
10837 { 0, 0, 0, 0 },
10838 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10839 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2390000 }
10840 },
10841/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10842 {
10843 { 0, 0, 0, 0 },
10844 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10845 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2390000 }
10846 },
10847/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10848 {
10849 { 0, 0, 0, 0 },
10850 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10851 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4090000 }
10852 },
10853/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10854 {
10855 { 0, 0, 0, 0 },
10856 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10857 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4290000 }
10858 },
10859/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10860 {
10861 { 0, 0, 0, 0 },
10862 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10863 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4390000 }
10864 },
10865/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10866 {
10867 { 0, 0, 0, 0 },
10868 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10869 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4390000 }
10870 },
10871/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10872 {
10873 { 0, 0, 0, 0 },
10874 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10875 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6090000 }
10876 },
10877/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10878 {
10879 { 0, 0, 0, 0 },
10880 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10881 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6290000 }
10882 },
10883/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10884 {
10885 { 0, 0, 0, 0 },
10886 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10887 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6390000 }
10888 },
10889/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10890 {
10891 { 0, 0, 0, 0 },
10892 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10893 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6390000 }
10894 },
10895/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10896 {
10897 { 0, 0, 0, 0 },
10898 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10899 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2890000 }
10900 },
10901/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10902 {
10903 { 0, 0, 0, 0 },
10904 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10905 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a90000 }
10906 },
10907/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10908 {
10909 { 0, 0, 0, 0 },
10910 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10911 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b90000 }
10912 },
10913/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10914 {
10915 { 0, 0, 0, 0 },
10916 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10917 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b90000 }
10918 },
10919/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10920 {
10921 { 0, 0, 0, 0 },
10922 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10923 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4890000 }
10924 },
10925/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10926 {
10927 { 0, 0, 0, 0 },
10928 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10929 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a90000 }
10930 },
10931/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10932 {
10933 { 0, 0, 0, 0 },
10934 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10935 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b90000 }
10936 },
10937/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10938 {
10939 { 0, 0, 0, 0 },
10940 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10941 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b90000 }
10942 },
10943/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10944 {
10945 { 0, 0, 0, 0 },
10946 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10947 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c90000 }
10948 },
10949/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10950 {
10951 { 0, 0, 0, 0 },
10952 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10953 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e90000 }
10954 },
10955/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10956 {
10957 { 0, 0, 0, 0 },
10958 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10959 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f90000 }
10960 },
10961/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10962 {
10963 { 0, 0, 0, 0 },
10964 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10965 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f90000 }
10966 },
10967/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10968 {
10969 { 0, 0, 0, 0 },
10970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10971 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c90000 }
10972 },
10973/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10974 {
10975 { 0, 0, 0, 0 },
10976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10977 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e90000 }
10978 },
10979/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10980 {
10981 { 0, 0, 0, 0 },
10982 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10983 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f90000 }
10984 },
10985/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10986 {
10987 { 0, 0, 0, 0 },
10988 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10989 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f90000 }
10990 },
10991/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10992 {
10993 { 0, 0, 0, 0 },
10994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
10995 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c90000 }
10996 },
10997/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10998 {
10999 { 0, 0, 0, 0 },
11000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
11001 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e90000 }
11002 },
11003/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
11004 {
11005 { 0, 0, 0, 0 },
11006 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
11007 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f90000 }
11008 },
11009/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
11010 {
11011 { 0, 0, 0, 0 },
11012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
11013 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f90000 }
11014 },
11015/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
11016 {
11017 { 0, 0, 0, 0 },
11018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
11019 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6890000 }
11020 },
11021/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
11022 {
11023 { 0, 0, 0, 0 },
11024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
11025 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a90000 }
11026 },
11027/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
11028 {
11029 { 0, 0, 0, 0 },
11030 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
11031 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b90000 }
11032 },
11033/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
11034 {
11035 { 0, 0, 0, 0 },
11036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
11037 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b90000 }
11038 },
11039/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
11040 {
11041 { 0, 0, 0, 0 },
11042 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11043 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8090000 }
11044 },
11045/* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
11046 {
11047 { 0, 0, 0, 0 },
11048 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11049 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8290000 }
11050 },
11051/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
11052 {
11053 { 0, 0, 0, 0 },
11054 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11055 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0890000 }
11056 },
11057/* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
11058 {
11059 { 0, 0, 0, 0 },
11060 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11061 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a90000 }
11062 },
11063/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
11064 {
11065 { 0, 0, 0, 0 },
11066 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11067 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0090000 }
11068 },
11069/* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
11070 {
11071 { 0, 0, 0, 0 },
11072 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11073 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0290000 }
11074 },
11075/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
11076 {
11077 { 0, 0, 0, 0 },
11078 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11079 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2090000 }
11080 },
11081/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
11082 {
11083 { 0, 0, 0, 0 },
11084 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11085 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2290000 }
11086 },
11087/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
11088 {
11089 { 0, 0, 0, 0 },
11090 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11091 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4090000 }
11092 },
11093/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
11094 {
11095 { 0, 0, 0, 0 },
11096 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11097 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4290000 }
11098 },
11099/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
11100 {
11101 { 0, 0, 0, 0 },
11102 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11103 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6090000 }
11104 },
11105/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
11106 {
11107 { 0, 0, 0, 0 },
11108 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11109 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6290000 }
11110 },
11111/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
11112 {
11113 { 0, 0, 0, 0 },
11114 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
11115 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2890000 }
11116 },
11117/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
11118 {
11119 { 0, 0, 0, 0 },
11120 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
11121 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a90000 }
11122 },
11123/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
11124 {
11125 { 0, 0, 0, 0 },
11126 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
11127 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4890000 }
11128 },
11129/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
11130 {
11131 { 0, 0, 0, 0 },
11132 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
11133 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a90000 }
11134 },
11135/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
11136 {
11137 { 0, 0, 0, 0 },
11138 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
11139 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c90000 }
11140 },
11141/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
11142 {
11143 { 0, 0, 0, 0 },
11144 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
11145 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e90000 }
11146 },
11147/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
11148 {
11149 { 0, 0, 0, 0 },
11150 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
11151 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c90000 }
11152 },
11153/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
11154 {
11155 { 0, 0, 0, 0 },
11156 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
11157 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e90000 }
11158 },
11159/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
11160 {
11161 { 0, 0, 0, 0 },
11162 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
11163 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c90000 }
11164 },
11165/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
11166 {
11167 { 0, 0, 0, 0 },
11168 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
11169 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e90000 }
11170 },
11171/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
11172 {
11173 { 0, 0, 0, 0 },
11174 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
11175 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6890000 }
11176 },
11177/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
11178 {
11179 { 0, 0, 0, 0 },
11180 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
11181 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a90000 }
11182 },
11183/* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
11184 {
11185 { 0, 0, 0, 0 },
11186 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11187 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc809 }
11188 },
11189/* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
11190 {
11191 { 0, 0, 0, 0 },
11192 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11193 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8829 }
11194 },
11195/* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
11196 {
11197 { 0, 0, 0, 0 },
11198 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11199 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8809 }
11200 },
11201/* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
11202 {
11203 { 0, 0, 0, 0 },
11204 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11205 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc089 }
11206 },
11207/* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
11208 {
11209 { 0, 0, 0, 0 },
11210 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11211 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a9 }
11212 },
11213/* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
11214 {
11215 { 0, 0, 0, 0 },
11216 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11217 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8089 }
11218 },
11219/* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
11220 {
11221 { 0, 0, 0, 0 },
11222 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11223 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc009 }
11224 },
11225/* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
11226 {
11227 { 0, 0, 0, 0 },
11228 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11229 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8029 }
11230 },
11231/* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
11232 {
11233 { 0, 0, 0, 0 },
11234 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11235 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8009 }
11236 },
11237/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11238 {
11239 { 0, 0, 0, 0 },
11240 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11241 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20900 }
11242 },
11243/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11244 {
11245 { 0, 0, 0, 0 },
11246 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11247 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822900 }
11248 },
11249/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
11250 {
11251 { 0, 0, 0, 0 },
11252 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11253 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820900 }
11254 },
11255/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11256 {
11257 { 0, 0, 0, 0 },
11258 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11259 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4090000 }
11260 },
11261/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11262 {
11263 { 0, 0, 0, 0 },
11264 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11265 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84290000 }
11266 },
11267/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
11268 {
11269 { 0, 0, 0, 0 },
11270 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11271 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84090000 }
11272 },
11273/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11274 {
11275 { 0, 0, 0, 0 },
11276 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11277 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6090000 }
11278 },
11279/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11280 {
11281 { 0, 0, 0, 0 },
11282 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11283 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86290000 }
11284 },
11285/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
11286 {
11287 { 0, 0, 0, 0 },
11288 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11289 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86090000 }
11290 },
11291/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
11292 {
11293 { 0, 0, 0, 0 },
11294 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11295 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28900 }
11296 },
11297/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
11298 {
11299 { 0, 0, 0, 0 },
11300 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11301 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a900 }
11302 },
11303/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
11304 {
11305 { 0, 0, 0, 0 },
11306 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11307 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828900 }
11308 },
11309/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
11310 {
11311 { 0, 0, 0, 0 },
11312 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11313 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4890000 }
11314 },
11315/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
11316 {
11317 { 0, 0, 0, 0 },
11318 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11319 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a90000 }
11320 },
11321/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
11322 {
11323 { 0, 0, 0, 0 },
11324 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11325 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84890000 }
11326 },
11327/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
11328 {
11329 { 0, 0, 0, 0 },
11330 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11331 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c900 }
11332 },
11333/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
11334 {
11335 { 0, 0, 0, 0 },
11336 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11337 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e900 }
11338 },
11339/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
11340 {
11341 { 0, 0, 0, 0 },
11342 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11343 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c900 }
11344 },
11345/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
11346 {
11347 { 0, 0, 0, 0 },
11348 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11349 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c90000 }
11350 },
11351/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
11352 {
11353 { 0, 0, 0, 0 },
11354 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11355 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e90000 }
11356 },
11357/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
11358 {
11359 { 0, 0, 0, 0 },
11360 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11361 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c90000 }
11362 },
11363/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
11364 {
11365 { 0, 0, 0, 0 },
11366 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
11367 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c90000 }
11368 },
11369/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
11370 {
11371 { 0, 0, 0, 0 },
11372 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
11373 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e90000 }
11374 },
11375/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
11376 {
11377 { 0, 0, 0, 0 },
11378 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
11379 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c90000 }
11380 },
11381/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
11382 {
11383 { 0, 0, 0, 0 },
11384 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
11385 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6890000 }
11386 },
11387/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
11388 {
11389 { 0, 0, 0, 0 },
11390 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
11391 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a90000 }
11392 },
11393/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
11394 {
11395 { 0, 0, 0, 0 },
11396 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
11397 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86890000 }
11398 },
11399/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
11400 {
11401 { 0, 0, 0, 0 },
11402 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11403 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x898000 }
11404 },
11405/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
11406 {
11407 { 0, 0, 0, 0 },
11408 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
11409 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x89a000 }
11410 },
11411/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
11412 {
11413 { 0, 0, 0, 0 },
11414 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
11415 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x89b000 }
11416 },
11417/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
11418 {
11419 { 0, 0, 0, 0 },
11420 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11421 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x898400 }
11422 },
11423/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
11424 {
11425 { 0, 0, 0, 0 },
11426 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
11427 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x89a400 }
11428 },
11429/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
11430 {
11431 { 0, 0, 0, 0 },
11432 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
11433 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x89b400 }
11434 },
11435/* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
11436 {
11437 { 0, 0, 0, 0 },
11438 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11439 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x898600 }
11440 },
11441/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
11442 {
11443 { 0, 0, 0, 0 },
11444 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11445 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x89a600 }
11446 },
11447/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
11448 {
11449 { 0, 0, 0, 0 },
11450 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11451 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x89b600 }
11452 },
11453/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
11454 {
11455 { 0, 0, 0, 0 },
11456 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11457 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x89880000 }
11458 },
11459/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
11460 {
11461 { 0, 0, 0, 0 },
11462 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11463 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x89a80000 }
11464 },
11465/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
11466 {
11467 { 0, 0, 0, 0 },
11468 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11469 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x89b80000 }
11470 },
11471/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
11472 {
11473 { 0, 0, 0, 0 },
11474 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11475 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x898c0000 }
11476 },
11477/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
11478 {
11479 { 0, 0, 0, 0 },
11480 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11481 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x89ac0000 }
11482 },
11483/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
11484 {
11485 { 0, 0, 0, 0 },
11486 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11487 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x89bc0000 }
11488 },
11489/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
11490 {
11491 { 0, 0, 0, 0 },
11492 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11493 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x898a0000 }
11494 },
11495/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
11496 {
11497 { 0, 0, 0, 0 },
11498 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11499 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89aa0000 }
11500 },
11501/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
11502 {
11503 { 0, 0, 0, 0 },
11504 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11505 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89ba0000 }
11506 },
11507/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
11508 {
11509 { 0, 0, 0, 0 },
11510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11511 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x898e0000 }
11512 },
11513/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
11514 {
11515 { 0, 0, 0, 0 },
11516 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11517 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89ae0000 }
11518 },
11519/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
11520 {
11521 { 0, 0, 0, 0 },
11522 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11523 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89be0000 }
11524 },
11525/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
11526 {
11527 { 0, 0, 0, 0 },
11528 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11529 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x898b0000 }
11530 },
11531/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
11532 {
11533 { 0, 0, 0, 0 },
11534 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11535 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89ab0000 }
11536 },
11537/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
11538 {
11539 { 0, 0, 0, 0 },
11540 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11541 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89bb0000 }
11542 },
11543/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
11544 {
11545 { 0, 0, 0, 0 },
11546 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
11547 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x898f0000 }
11548 },
11549/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
11550 {
11551 { 0, 0, 0, 0 },
11552 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11553 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x89af0000 }
11554 },
11555/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
11556 {
11557 { 0, 0, 0, 0 },
11558 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11559 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x89bf0000 }
11560 },
11561/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
11562 {
11563 { 0, 0, 0, 0 },
11564 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11565 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x89c00000 }
11566 },
11567/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
11568 {
11569 { 0, 0, 0, 0 },
11570 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
11571 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x89e00000 }
11572 },
11573/* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
11574 {
11575 { 0, 0, 0, 0 },
11576 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
11577 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x89f00000 }
11578 },
11579/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
11580 {
11581 { 0, 0, 0, 0 },
11582 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11583 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x89c40000 }
11584 },
11585/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
11586 {
11587 { 0, 0, 0, 0 },
11588 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
11589 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x89e40000 }
11590 },
11591/* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
11592 {
11593 { 0, 0, 0, 0 },
11594 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
11595 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x89f40000 }
11596 },
11597/* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
11598 {
11599 { 0, 0, 0, 0 },
11600 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11601 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x89c60000 }
11602 },
11603/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
11604 {
11605 { 0, 0, 0, 0 },
11606 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11607 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x89e60000 }
11608 },
11609/* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
11610 {
11611 { 0, 0, 0, 0 },
11612 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
11613 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x89f60000 }
11614 },
11615/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
11616 {
11617 { 0, 0, 0, 0 },
11618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11619 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x89c80000 }
11620 },
11621/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
11622 {
11623 { 0, 0, 0, 0 },
11624 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11625 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x89e80000 }
11626 },
11627/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
11628 {
11629 { 0, 0, 0, 0 },
11630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11631 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x89f80000 }
11632 },
11633/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
11634 {
11635 { 0, 0, 0, 0 },
11636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11637 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x89cc0000 }
11638 },
11639/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
11640 {
11641 { 0, 0, 0, 0 },
11642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11643 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x89ec0000 }
11644 },
11645/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
11646 {
11647 { 0, 0, 0, 0 },
11648 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11649 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x89fc0000 }
11650 },
11651/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
11652 {
11653 { 0, 0, 0, 0 },
11654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11655 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ca0000 }
11656 },
11657/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
11658 {
11659 { 0, 0, 0, 0 },
11660 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11661 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ea0000 }
11662 },
11663/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
11664 {
11665 { 0, 0, 0, 0 },
11666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11667 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x89fa0000 }
11668 },
11669/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
11670 {
11671 { 0, 0, 0, 0 },
11672 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11673 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ce0000 }
11674 },
11675/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
11676 {
11677 { 0, 0, 0, 0 },
11678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11679 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ee0000 }
11680 },
11681/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
11682 {
11683 { 0, 0, 0, 0 },
11684 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11685 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x89fe0000 }
11686 },
11687/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
11688 {
11689 { 0, 0, 0, 0 },
11690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11691 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x89cb0000 }
11692 },
11693/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
11694 {
11695 { 0, 0, 0, 0 },
11696 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11697 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x89eb0000 }
11698 },
11699/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
11700 {
11701 { 0, 0, 0, 0 },
11702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11703 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x89fb0000 }
11704 },
11705/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
11706 {
11707 { 0, 0, 0, 0 },
11708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
11709 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x89cf0000 }
11710 },
11711/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
11712 {
11713 { 0, 0, 0, 0 },
11714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
11715 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x89ef0000 }
11716 },
11717/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
11718 {
11719 { 0, 0, 0, 0 },
11720 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
11721 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x89ff0000 }
11722 },
11723/* xor.w${G} $Src16RnHI,$Dst16RnHI */
11724 {
11725 { 0, 0, 0, 0 },
11726 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
11727 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8900 }
11728 },
11729/* xor.w${G} $Src16AnHI,$Dst16RnHI */
11730 {
11731 { 0, 0, 0, 0 },
11732 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
11733 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8940 }
11734 },
11735/* xor.w${G} [$Src16An],$Dst16RnHI */
11736 {
11737 { 0, 0, 0, 0 },
11738 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11739 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8960 }
11740 },
11741/* xor.w${G} $Src16RnHI,$Dst16AnHI */
11742 {
11743 { 0, 0, 0, 0 },
11744 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
11745 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8904 }
11746 },
11747/* xor.w${G} $Src16AnHI,$Dst16AnHI */
11748 {
11749 { 0, 0, 0, 0 },
11750 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
11751 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8944 }
11752 },
11753/* xor.w${G} [$Src16An],$Dst16AnHI */
11754 {
11755 { 0, 0, 0, 0 },
11756 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11757 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8964 }
11758 },
11759/* xor.w${G} $Src16RnHI,[$Dst16An] */
11760 {
11761 { 0, 0, 0, 0 },
11762 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
11763 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8906 }
11764 },
11765/* xor.w${G} $Src16AnHI,[$Dst16An] */
11766 {
11767 { 0, 0, 0, 0 },
11768 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
11769 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8946 }
11770 },
11771/* xor.w${G} [$Src16An],[$Dst16An] */
11772 {
11773 { 0, 0, 0, 0 },
11774 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11775 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8966 }
11776 },
11777/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
11778 {
11779 { 0, 0, 0, 0 },
11780 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11781 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x890800 }
11782 },
11783/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
11784 {
11785 { 0, 0, 0, 0 },
11786 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11787 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x894800 }
11788 },
11789/* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
11790 {
11791 { 0, 0, 0, 0 },
11792 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11793 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x896800 }
11794 },
11795/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
11796 {
11797 { 0, 0, 0, 0 },
11798 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11799 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x890c0000 }
11800 },
11801/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
11802 {
11803 { 0, 0, 0, 0 },
11804 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11805 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x894c0000 }
11806 },
11807/* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
11808 {
11809 { 0, 0, 0, 0 },
11810 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11811 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x896c0000 }
11812 },
11813/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
11814 {
11815 { 0, 0, 0, 0 },
11816 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11817 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x890a00 }
11818 },
11819/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
11820 {
11821 { 0, 0, 0, 0 },
11822 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11823 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x894a00 }
11824 },
11825/* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
11826 {
11827 { 0, 0, 0, 0 },
11828 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11829 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x896a00 }
11830 },
11831/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
11832 {
11833 { 0, 0, 0, 0 },
11834 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11835 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x890e0000 }
11836 },
11837/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
11838 {
11839 { 0, 0, 0, 0 },
11840 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11841 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x894e0000 }
11842 },
11843/* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
11844 {
11845 { 0, 0, 0, 0 },
11846 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11847 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x896e0000 }
11848 },
11849/* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
11850 {
11851 { 0, 0, 0, 0 },
11852 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11853 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x890b00 }
11854 },
11855/* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
11856 {
11857 { 0, 0, 0, 0 },
11858 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11859 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x894b00 }
11860 },
11861/* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
11862 {
11863 { 0, 0, 0, 0 },
11864 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11865 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x896b00 }
11866 },
11867/* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
11868 {
11869 { 0, 0, 0, 0 },
11870 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
11871 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x890f0000 }
11872 },
11873/* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
11874 {
11875 { 0, 0, 0, 0 },
11876 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
11877 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x894f0000 }
11878 },
11879/* xor.w${G} [$Src16An],${Dsp-16-u16} */
11880 {
11881 { 0, 0, 0, 0 },
11882 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
11883 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x896f0000 }
11884 },
11885/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
11886 {
11887 { 0, 0, 0, 0 },
11888 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
11889 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x888000 }
11890 },
11891/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
11892 {
11893 { 0, 0, 0, 0 },
11894 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
11895 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x88a000 }
11896 },
11897/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
11898 {
11899 { 0, 0, 0, 0 },
11900 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
11901 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x88b000 }
11902 },
11903/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
11904 {
11905 { 0, 0, 0, 0 },
11906 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
11907 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x888400 }
11908 },
11909/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
11910 {
11911 { 0, 0, 0, 0 },
11912 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
11913 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x88a400 }
11914 },
11915/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
11916 {
11917 { 0, 0, 0, 0 },
11918 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
11919 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x88b400 }
11920 },
11921/* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
11922 {
11923 { 0, 0, 0, 0 },
11924 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11925 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x888600 }
11926 },
11927/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
11928 {
11929 { 0, 0, 0, 0 },
11930 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11931 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x88a600 }
11932 },
11933/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
11934 {
11935 { 0, 0, 0, 0 },
11936 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11937 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x88b600 }
11938 },
11939/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
11940 {
11941 { 0, 0, 0, 0 },
11942 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11943 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x88880000 }
11944 },
11945/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
11946 {
11947 { 0, 0, 0, 0 },
11948 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11949 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x88a80000 }
11950 },
11951/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
11952 {
11953 { 0, 0, 0, 0 },
11954 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11955 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x88b80000 }
11956 },
11957/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
11958 {
11959 { 0, 0, 0, 0 },
11960 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11961 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x888c0000 }
11962 },
11963/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
11964 {
11965 { 0, 0, 0, 0 },
11966 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11967 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x88ac0000 }
11968 },
11969/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
11970 {
11971 { 0, 0, 0, 0 },
11972 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11973 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x88bc0000 }
11974 },
11975/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
11976 {
11977 { 0, 0, 0, 0 },
11978 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11979 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x888a0000 }
11980 },
11981/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
11982 {
11983 { 0, 0, 0, 0 },
11984 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11985 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88aa0000 }
11986 },
11987/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
11988 {
11989 { 0, 0, 0, 0 },
11990 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11991 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88ba0000 }
11992 },
11993/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
11994 {
11995 { 0, 0, 0, 0 },
11996 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11997 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x888e0000 }
11998 },
11999/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
12000 {
12001 { 0, 0, 0, 0 },
12002 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
12003 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88ae0000 }
12004 },
12005/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
12006 {
12007 { 0, 0, 0, 0 },
12008 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
12009 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88be0000 }
12010 },
12011/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
12012 {
12013 { 0, 0, 0, 0 },
12014 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
12015 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x888b0000 }
12016 },
12017/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
12018 {
12019 { 0, 0, 0, 0 },
12020 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
12021 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88ab0000 }
12022 },
12023/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
12024 {
12025 { 0, 0, 0, 0 },
12026 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
12027 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88bb0000 }
12028 },
12029/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
12030 {
12031 { 0, 0, 0, 0 },
12032 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
12033 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x888f0000 }
12034 },
12035/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
12036 {
12037 { 0, 0, 0, 0 },
12038 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
12039 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x88af0000 }
12040 },
12041/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
12042 {
12043 { 0, 0, 0, 0 },
12044 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
12045 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x88bf0000 }
12046 },
12047/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
12048 {
12049 { 0, 0, 0, 0 },
12050 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
12051 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x88c00000 }
12052 },
12053/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
12054 {
12055 { 0, 0, 0, 0 },
12056 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
12057 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x88e00000 }
12058 },
12059/* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
12060 {
12061 { 0, 0, 0, 0 },
12062 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
12063 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x88f00000 }
12064 },
12065/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
12066 {
12067 { 0, 0, 0, 0 },
12068 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
12069 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x88c40000 }
12070 },
12071/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
12072 {
12073 { 0, 0, 0, 0 },
12074 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
12075 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x88e40000 }
12076 },
12077/* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
12078 {
12079 { 0, 0, 0, 0 },
12080 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
12081 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x88f40000 }
12082 },
12083/* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
12084 {
12085 { 0, 0, 0, 0 },
12086 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
12087 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x88c60000 }
12088 },
12089/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
12090 {
12091 { 0, 0, 0, 0 },
12092 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
12093 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x88e60000 }
12094 },
12095/* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
12096 {
12097 { 0, 0, 0, 0 },
12098 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
12099 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x88f60000 }
12100 },
12101/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
12102 {
12103 { 0, 0, 0, 0 },
12104 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
12105 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x88c80000 }
12106 },
12107/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
12108 {
12109 { 0, 0, 0, 0 },
12110 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
12111 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x88e80000 }
12112 },
12113/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
12114 {
12115 { 0, 0, 0, 0 },
12116 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
12117 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x88f80000 }
12118 },
12119/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
12120 {
12121 { 0, 0, 0, 0 },
12122 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
12123 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x88cc0000 }
12124 },
12125/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
12126 {
12127 { 0, 0, 0, 0 },
12128 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
12129 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x88ec0000 }
12130 },
12131/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
12132 {
12133 { 0, 0, 0, 0 },
12134 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
12135 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x88fc0000 }
12136 },
12137/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
12138 {
12139 { 0, 0, 0, 0 },
12140 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
12141 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ca0000 }
12142 },
12143/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
12144 {
12145 { 0, 0, 0, 0 },
12146 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
12147 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ea0000 }
12148 },
12149/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
12150 {
12151 { 0, 0, 0, 0 },
12152 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
12153 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x88fa0000 }
12154 },
12155/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
12156 {
12157 { 0, 0, 0, 0 },
12158 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
12159 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ce0000 }
12160 },
12161/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
12162 {
12163 { 0, 0, 0, 0 },
12164 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
12165 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ee0000 }
12166 },
12167/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
12168 {
12169 { 0, 0, 0, 0 },
12170 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
12171 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x88fe0000 }
12172 },
12173/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
12174 {
12175 { 0, 0, 0, 0 },
12176 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
12177 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x88cb0000 }
12178 },
12179/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
12180 {
12181 { 0, 0, 0, 0 },
12182 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
12183 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x88eb0000 }
12184 },
12185/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
12186 {
12187 { 0, 0, 0, 0 },
12188 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
12189 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x88fb0000 }
12190 },
12191/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
12192 {
12193 { 0, 0, 0, 0 },
12194 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
12195 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x88cf0000 }
12196 },
12197/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
12198 {
12199 { 0, 0, 0, 0 },
12200 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
12201 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x88ef0000 }
12202 },
12203/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
12204 {
12205 { 0, 0, 0, 0 },
12206 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
12207 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x88ff0000 }
12208 },
12209/* xor.b${G} $Src16RnQI,$Dst16RnQI */
12210 {
12211 { 0, 0, 0, 0 },
12212 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
12213 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8800 }
12214 },
12215/* xor.b${G} $Src16AnQI,$Dst16RnQI */
12216 {
12217 { 0, 0, 0, 0 },
12218 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
12219 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8840 }
12220 },
12221/* xor.b${G} [$Src16An],$Dst16RnQI */
12222 {
12223 { 0, 0, 0, 0 },
12224 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
12225 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8860 }
12226 },
12227/* xor.b${G} $Src16RnQI,$Dst16AnQI */
12228 {
12229 { 0, 0, 0, 0 },
12230 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
12231 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8804 }
12232 },
12233/* xor.b${G} $Src16AnQI,$Dst16AnQI */
12234 {
12235 { 0, 0, 0, 0 },
12236 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
12237 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8844 }
12238 },
12239/* xor.b${G} [$Src16An],$Dst16AnQI */
12240 {
12241 { 0, 0, 0, 0 },
12242 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
12243 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8864 }
12244 },
12245/* xor.b${G} $Src16RnQI,[$Dst16An] */
12246 {
12247 { 0, 0, 0, 0 },
12248 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
12249 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8806 }
12250 },
12251/* xor.b${G} $Src16AnQI,[$Dst16An] */
12252 {
12253 { 0, 0, 0, 0 },
12254 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
12255 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8846 }
12256 },
12257/* xor.b${G} [$Src16An],[$Dst16An] */
12258 {
12259 { 0, 0, 0, 0 },
12260 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
12261 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8866 }
12262 },
12263/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
12264 {
12265 { 0, 0, 0, 0 },
12266 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12267 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x880800 }
12268 },
12269/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
12270 {
12271 { 0, 0, 0, 0 },
12272 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12273 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x884800 }
12274 },
12275/* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
12276 {
12277 { 0, 0, 0, 0 },
12278 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12279 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x886800 }
12280 },
12281/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
12282 {
12283 { 0, 0, 0, 0 },
12284 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12285 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x880c0000 }
12286 },
12287/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
12288 {
12289 { 0, 0, 0, 0 },
12290 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12291 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x884c0000 }
12292 },
12293/* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
12294 {
12295 { 0, 0, 0, 0 },
12296 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12297 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x886c0000 }
12298 },
12299/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
12300 {
12301 { 0, 0, 0, 0 },
12302 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12303 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x880a00 }
12304 },
12305/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
12306 {
12307 { 0, 0, 0, 0 },
12308 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12309 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x884a00 }
12310 },
12311/* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
12312 {
12313 { 0, 0, 0, 0 },
12314 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12315 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x886a00 }
12316 },
12317/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
12318 {
12319 { 0, 0, 0, 0 },
12320 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12321 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x880e0000 }
12322 },
12323/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
12324 {
12325 { 0, 0, 0, 0 },
12326 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12327 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x884e0000 }
12328 },
12329/* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
12330 {
12331 { 0, 0, 0, 0 },
12332 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12333 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x886e0000 }
12334 },
12335/* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
12336 {
12337 { 0, 0, 0, 0 },
12338 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12339 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x880b00 }
12340 },
12341/* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
12342 {
12343 { 0, 0, 0, 0 },
12344 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12345 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x884b00 }
12346 },
12347/* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
12348 {
12349 { 0, 0, 0, 0 },
12350 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12351 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x886b00 }
12352 },
12353/* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
12354 {
12355 { 0, 0, 0, 0 },
12356 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
12357 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x880f0000 }
12358 },
12359/* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
12360 {
12361 { 0, 0, 0, 0 },
12362 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
12363 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x884f0000 }
12364 },
12365/* xor.b${G} [$Src16An],${Dsp-16-u16} */
12366 {
12367 { 0, 0, 0, 0 },
12368 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
12369 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x886f0000 }
12370 },
12371/* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
12372 {
12373 { 0, 0, 0, 0 },
12374 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12375 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990e0000 }
12376 },
12377/* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
12378 {
12379 { 0, 0, 0, 0 },
12380 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12381 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918e0000 }
12382 },
12383/* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
12384 {
12385 { 0, 0, 0, 0 },
12386 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12387 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910e0000 }
12388 },
12389/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12390 {
12391 { 0, 0, 0, 0 },
12392 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12393 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930e0000 }
12394 },
12395/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
12396 {
12397 { 0, 0, 0, 0 },
12398 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12399 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938e0000 }
12400 },
12401/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
12402 {
12403 { 0, 0, 0, 0 },
12404 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12405 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ce0000 }
12406 },
12407/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12408 {
12409 { 0, 0, 0, 0 },
12410 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12411 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950e0000 }
12412 },
12413/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
12414 {
12415 { 0, 0, 0, 0 },
12416 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12417 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958e0000 }
12418 },
12419/* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
12420 {
12421 { 0, 0, 0, 0 },
12422 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12423 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ce0000 }
12424 },
12425/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
12426 {
12427 { 0, 0, 0, 0 },
12428 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
12429 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ce0000 }
12430 },
12431/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12432 {
12433 { 0, 0, 0, 0 },
12434 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12435 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970e0000 }
12436 },
12437/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
12438 {
12439 { 0, 0, 0, 0 },
12440 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
12441 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978e0000 }
12442 },
12443/* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
12444 {
12445 { 0, 0, 0, 0 },
12446 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
12447 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980e00 }
12448 },
12449/* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
12450 {
12451 { 0, 0, 0, 0 },
12452 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
12453 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908e00 }
12454 },
12455/* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12456 {
12457 { 0, 0, 0, 0 },
12458 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12459 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900e00 }
12460 },
12461/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12462 {
12463 { 0, 0, 0, 0 },
12464 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12465 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920e0000 }
12466 },
12467/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12468 {
12469 { 0, 0, 0, 0 },
12470 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12471 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928e0000 }
12472 },
12473/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12474 {
12475 { 0, 0, 0, 0 },
12476 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12477 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ce0000 }
12478 },
12479/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12480 {
12481 { 0, 0, 0, 0 },
12482 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12483 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940e0000 }
12484 },
12485/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12486 {
12487 { 0, 0, 0, 0 },
12488 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12489 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948e0000 }
12490 },
12491/* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12492 {
12493 { 0, 0, 0, 0 },
12494 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12495 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ce0000 }
12496 },
12497/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
12498 {
12499 { 0, 0, 0, 0 },
12500 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
12501 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ce0000 }
12502 },
12503/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12504 {
12505 { 0, 0, 0, 0 },
12506 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12507 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960e0000 }
12508 },
12509/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
12510 {
12511 { 0, 0, 0, 0 },
12512 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
12513 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968e0000 }
12514 },
12515/* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
12516 {
12517 { 0, 0, 0, 0 },
12518 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
12519 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77100000 }
12520 },
12521/* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
12522 {
12523 { 0, 0, 0, 0 },
12524 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
12525 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77140000 }
12526 },
12527/* xor.w${G} #${Imm-16-HI},[$Dst16An] */
12528 {
12529 { 0, 0, 0, 0 },
12530 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
12531 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77160000 }
12532 },
12533/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
12534 {
12535 { 0, 0, 0, 0 },
12536 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12537 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77180000 }
12538 },
12539/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
12540 {
12541 { 0, 0, 0, 0 },
12542 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12543 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x771a0000 }
12544 },
12545/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
12546 {
12547 { 0, 0, 0, 0 },
12548 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12549 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x771b0000 }
12550 },
12551/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
12552 {
12553 { 0, 0, 0, 0 },
12554 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12555 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x771c0000 }
12556 },
12557/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
12558 {
12559 { 0, 0, 0, 0 },
12560 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12561 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x771e0000 }
12562 },
12563/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
12564 {
12565 { 0, 0, 0, 0 },
12566 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
12567 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x771f0000 }
12568 },
12569/* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
12570 {
12571 { 0, 0, 0, 0 },
12572 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
12573 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x761000 }
12574 },
12575/* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
12576 {
12577 { 0, 0, 0, 0 },
12578 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
12579 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x761400 }
12580 },
12581/* xor.b${G} #${Imm-16-QI},[$Dst16An] */
12582 {
12583 { 0, 0, 0, 0 },
12584 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
12585 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x761600 }
12586 },
12587/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
12588 {
12589 { 0, 0, 0, 0 },
12590 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12591 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76180000 }
12592 },
12593/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12594 {
12595 { 0, 0, 0, 0 },
12596 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12597 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x761a0000 }
12598 },
12599/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12600 {
12601 { 0, 0, 0, 0 },
12602 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12603 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x761b0000 }
12604 },
12605/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
12606 {
12607 { 0, 0, 0, 0 },
12608 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12609 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x761c0000 }
12610 },
12611/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12612 {
12613 { 0, 0, 0, 0 },
12614 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12615 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x761e0000 }
12616 },
12617/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
12618 {
12619 { 0, 0, 0, 0 },
12620 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
12621 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x761f0000 }
12622 },
12623/* xchg.w r3,$Dst32RnUnprefixedHI */
12624 {
12625 { 0, 0, 0, 0 },
12626 { { MNEM, ' ', 'r', '3', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12627 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90d }
12628 },
12629/* xchg.w r3,$Dst32AnUnprefixedHI */
12630 {
12631 { 0, 0, 0, 0 },
12632 { { MNEM, ' ', 'r', '3', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12633 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18d }
12634 },
12635/* xchg.w r3,[$Dst32AnUnprefixed] */
12636 {
12637 { 0, 0, 0, 0 },
12638 { { MNEM, ' ', 'r', '3', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12639 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10d }
12640 },
12641/* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12642 {
12643 { 0, 0, 0, 0 },
12644 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12645 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30d00 }
12646 },
12647/* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12648 {
12649 { 0, 0, 0, 0 },
12650 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12651 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50d0000 }
12652 },
12653/* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12654 {
12655 { 0, 0, 0, 0 },
12656 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12657 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70d0000 }
12658 },
12659/* xchg.w r3,${Dsp-16-u8}[sb] */
12660 {
12661 { 0, 0, 0, 0 },
12662 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12663 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38d00 }
12664 },
12665/* xchg.w r3,${Dsp-16-u16}[sb] */
12666 {
12667 { 0, 0, 0, 0 },
12668 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12669 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58d0000 }
12670 },
12671/* xchg.w r3,${Dsp-16-s8}[fb] */
12672 {
12673 { 0, 0, 0, 0 },
12674 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12675 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cd00 }
12676 },
12677/* xchg.w r3,${Dsp-16-s16}[fb] */
12678 {
12679 { 0, 0, 0, 0 },
12680 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12681 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cd0000 }
12682 },
12683/* xchg.w r3,${Dsp-16-u16} */
12684 {
12685 { 0, 0, 0, 0 },
12686 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } },
12687 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cd0000 }
12688 },
12689/* xchg.w r3,${Dsp-16-u24} */
12690 {
12691 { 0, 0, 0, 0 },
12692 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), 0 } },
12693 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78d0000 }
12694 },
12695/* xchg.w r2,$Dst32RnUnprefixedHI */
12696 {
12697 { 0, 0, 0, 0 },
12698 { { MNEM, ' ', 'r', '2', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12699 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90c }
12700 },
12701/* xchg.w r2,$Dst32AnUnprefixedHI */
12702 {
12703 { 0, 0, 0, 0 },
12704 { { MNEM, ' ', 'r', '2', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12705 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18c }
12706 },
12707/* xchg.w r2,[$Dst32AnUnprefixed] */
12708 {
12709 { 0, 0, 0, 0 },
12710 { { MNEM, ' ', 'r', '2', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12711 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10c }
12712 },
12713/* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12714 {
12715 { 0, 0, 0, 0 },
12716 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12717 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30c00 }
12718 },
12719/* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12720 {
12721 { 0, 0, 0, 0 },
12722 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12723 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50c0000 }
12724 },
12725/* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12726 {
12727 { 0, 0, 0, 0 },
12728 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12729 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70c0000 }
12730 },
12731/* xchg.w r2,${Dsp-16-u8}[sb] */
12732 {
12733 { 0, 0, 0, 0 },
12734 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12735 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38c00 }
12736 },
12737/* xchg.w r2,${Dsp-16-u16}[sb] */
12738 {
12739 { 0, 0, 0, 0 },
12740 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12741 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58c0000 }
12742 },
12743/* xchg.w r2,${Dsp-16-s8}[fb] */
12744 {
12745 { 0, 0, 0, 0 },
12746 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12747 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cc00 }
12748 },
12749/* xchg.w r2,${Dsp-16-s16}[fb] */
12750 {
12751 { 0, 0, 0, 0 },
12752 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12753 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cc0000 }
12754 },
12755/* xchg.w r2,${Dsp-16-u16} */
12756 {
12757 { 0, 0, 0, 0 },
12758 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } },
12759 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cc0000 }
12760 },
12761/* xchg.w r2,${Dsp-16-u24} */
12762 {
12763 { 0, 0, 0, 0 },
12764 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), 0 } },
12765 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78c0000 }
12766 },
12767/* xchg.w a1,$Dst32RnUnprefixedHI */
12768 {
12769 { 0, 0, 0, 0 },
12770 { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12771 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90b }
12772 },
12773/* xchg.w a1,$Dst32AnUnprefixedHI */
12774 {
12775 { 0, 0, 0, 0 },
12776 { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12777 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18b }
12778 },
12779/* xchg.w a1,[$Dst32AnUnprefixed] */
12780 {
12781 { 0, 0, 0, 0 },
12782 { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12783 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10b }
12784 },
12785/* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12786 {
12787 { 0, 0, 0, 0 },
12788 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12789 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30b00 }
12790 },
12791/* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12792 {
12793 { 0, 0, 0, 0 },
12794 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12795 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50b0000 }
12796 },
12797/* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12798 {
12799 { 0, 0, 0, 0 },
12800 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12801 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70b0000 }
12802 },
12803/* xchg.w a1,${Dsp-16-u8}[sb] */
12804 {
12805 { 0, 0, 0, 0 },
12806 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12807 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38b00 }
12808 },
12809/* xchg.w a1,${Dsp-16-u16}[sb] */
12810 {
12811 { 0, 0, 0, 0 },
12812 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12813 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58b0000 }
12814 },
12815/* xchg.w a1,${Dsp-16-s8}[fb] */
12816 {
12817 { 0, 0, 0, 0 },
12818 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12819 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cb00 }
12820 },
12821/* xchg.w a1,${Dsp-16-s16}[fb] */
12822 {
12823 { 0, 0, 0, 0 },
12824 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12825 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cb0000 }
12826 },
12827/* xchg.w a1,${Dsp-16-u16} */
12828 {
12829 { 0, 0, 0, 0 },
12830 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } },
12831 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cb0000 }
12832 },
12833/* xchg.w a1,${Dsp-16-u24} */
12834 {
12835 { 0, 0, 0, 0 },
12836 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } },
12837 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78b0000 }
12838 },
12839/* xchg.w a0,$Dst32RnUnprefixedHI */
12840 {
12841 { 0, 0, 0, 0 },
12842 { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12843 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90a }
12844 },
12845/* xchg.w a0,$Dst32AnUnprefixedHI */
12846 {
12847 { 0, 0, 0, 0 },
12848 { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12849 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18a }
12850 },
12851/* xchg.w a0,[$Dst32AnUnprefixed] */
12852 {
12853 { 0, 0, 0, 0 },
12854 { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12855 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10a }
12856 },
12857/* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12858 {
12859 { 0, 0, 0, 0 },
12860 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12861 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30a00 }
12862 },
12863/* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12864 {
12865 { 0, 0, 0, 0 },
12866 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12867 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50a0000 }
12868 },
12869/* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12870 {
12871 { 0, 0, 0, 0 },
12872 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12873 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70a0000 }
12874 },
12875/* xchg.w a0,${Dsp-16-u8}[sb] */
12876 {
12877 { 0, 0, 0, 0 },
12878 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12879 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38a00 }
12880 },
12881/* xchg.w a0,${Dsp-16-u16}[sb] */
12882 {
12883 { 0, 0, 0, 0 },
12884 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12885 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58a0000 }
12886 },
12887/* xchg.w a0,${Dsp-16-s8}[fb] */
12888 {
12889 { 0, 0, 0, 0 },
12890 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12891 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3ca00 }
12892 },
12893/* xchg.w a0,${Dsp-16-s16}[fb] */
12894 {
12895 { 0, 0, 0, 0 },
12896 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12897 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5ca0000 }
12898 },
12899/* xchg.w a0,${Dsp-16-u16} */
12900 {
12901 { 0, 0, 0, 0 },
12902 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } },
12903 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7ca0000 }
12904 },
12905/* xchg.w a0,${Dsp-16-u24} */
12906 {
12907 { 0, 0, 0, 0 },
12908 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } },
12909 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78a0000 }
12910 },
12911/* xchg.w r1,$Dst32RnUnprefixedHI */
12912 {
12913 { 0, 0, 0, 0 },
12914 { { MNEM, ' ', 'r', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12915 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd909 }
12916 },
12917/* xchg.w r1,$Dst32AnUnprefixedHI */
12918 {
12919 { 0, 0, 0, 0 },
12920 { { MNEM, ' ', 'r', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12921 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd189 }
12922 },
12923/* xchg.w r1,[$Dst32AnUnprefixed] */
12924 {
12925 { 0, 0, 0, 0 },
12926 { { MNEM, ' ', 'r', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12927 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd109 }
12928 },
12929/* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12930 {
12931 { 0, 0, 0, 0 },
12932 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12933 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30900 }
12934 },
12935/* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12936 {
12937 { 0, 0, 0, 0 },
12938 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12939 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5090000 }
12940 },
12941/* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12942 {
12943 { 0, 0, 0, 0 },
12944 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12945 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7090000 }
12946 },
12947/* xchg.w r1,${Dsp-16-u8}[sb] */
12948 {
12949 { 0, 0, 0, 0 },
12950 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12951 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38900 }
12952 },
12953/* xchg.w r1,${Dsp-16-u16}[sb] */
12954 {
12955 { 0, 0, 0, 0 },
12956 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12957 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5890000 }
12958 },
12959/* xchg.w r1,${Dsp-16-s8}[fb] */
12960 {
12961 { 0, 0, 0, 0 },
12962 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12963 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c900 }
12964 },
12965/* xchg.w r1,${Dsp-16-s16}[fb] */
12966 {
12967 { 0, 0, 0, 0 },
12968 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12969 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c90000 }
12970 },
12971/* xchg.w r1,${Dsp-16-u16} */
12972 {
12973 { 0, 0, 0, 0 },
12974 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } },
12975 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c90000 }
12976 },
12977/* xchg.w r1,${Dsp-16-u24} */
12978 {
12979 { 0, 0, 0, 0 },
12980 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), 0 } },
12981 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7890000 }
12982 },
12983/* xchg.w r0,$Dst32RnUnprefixedHI */
12984 {
12985 { 0, 0, 0, 0 },
12986 { { MNEM, ' ', 'r', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12987 & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd908 }
12988 },
12989/* xchg.w r0,$Dst32AnUnprefixedHI */
12990 {
12991 { 0, 0, 0, 0 },
12992 { { MNEM, ' ', 'r', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12993 & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd188 }
12994 },
12995/* xchg.w r0,[$Dst32AnUnprefixed] */
12996 {
12997 { 0, 0, 0, 0 },
12998 { { MNEM, ' ', 'r', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12999 & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd108 }
13000 },
13001/* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13002 {
13003 { 0, 0, 0, 0 },
13004 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13005 & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30800 }
13006 },
13007/* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13008 {
13009 { 0, 0, 0, 0 },
13010 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13011 & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5080000 }
13012 },
13013/* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13014 {
13015 { 0, 0, 0, 0 },
13016 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13017 & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7080000 }
13018 },
13019/* xchg.w r0,${Dsp-16-u8}[sb] */
13020 {
13021 { 0, 0, 0, 0 },
13022 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13023 & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38800 }
13024 },
13025/* xchg.w r0,${Dsp-16-u16}[sb] */
13026 {
13027 { 0, 0, 0, 0 },
13028 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13029 & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5880000 }
13030 },
13031/* xchg.w r0,${Dsp-16-s8}[fb] */
13032 {
13033 { 0, 0, 0, 0 },
13034 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13035 & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c800 }
13036 },
13037/* xchg.w r0,${Dsp-16-s16}[fb] */
13038 {
13039 { 0, 0, 0, 0 },
13040 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13041 & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c80000 }
13042 },
13043/* xchg.w r0,${Dsp-16-u16} */
13044 {
13045 { 0, 0, 0, 0 },
13046 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } },
13047 & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c80000 }
13048 },
13049/* xchg.w r0,${Dsp-16-u24} */
13050 {
13051 { 0, 0, 0, 0 },
13052 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), 0 } },
13053 & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7880000 }
13054 },
13055/* xchg.b r1h,$Dst32RnUnprefixedQI */
13056 {
13057 { 0, 0, 0, 0 },
13058 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13059 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80d }
13060 },
13061/* xchg.b r1h,$Dst32AnUnprefixedQI */
13062 {
13063 { 0, 0, 0, 0 },
13064 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13065 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08d }
13066 },
13067/* xchg.b r1h,[$Dst32AnUnprefixed] */
13068 {
13069 { 0, 0, 0, 0 },
13070 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13071 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00d }
13072 },
13073/* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13074 {
13075 { 0, 0, 0, 0 },
13076 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13077 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20d00 }
13078 },
13079/* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13080 {
13081 { 0, 0, 0, 0 },
13082 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13083 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40d0000 }
13084 },
13085/* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13086 {
13087 { 0, 0, 0, 0 },
13088 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13089 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60d0000 }
13090 },
13091/* xchg.b r1h,${Dsp-16-u8}[sb] */
13092 {
13093 { 0, 0, 0, 0 },
13094 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13095 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28d00 }
13096 },
13097/* xchg.b r1h,${Dsp-16-u16}[sb] */
13098 {
13099 { 0, 0, 0, 0 },
13100 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13101 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48d0000 }
13102 },
13103/* xchg.b r1h,${Dsp-16-s8}[fb] */
13104 {
13105 { 0, 0, 0, 0 },
13106 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13107 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cd00 }
13108 },
13109/* xchg.b r1h,${Dsp-16-s16}[fb] */
13110 {
13111 { 0, 0, 0, 0 },
13112 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13113 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cd0000 }
13114 },
13115/* xchg.b r1h,${Dsp-16-u16} */
13116 {
13117 { 0, 0, 0, 0 },
13118 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
13119 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cd0000 }
13120 },
13121/* xchg.b r1h,${Dsp-16-u24} */
13122 {
13123 { 0, 0, 0, 0 },
13124 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
13125 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68d0000 }
13126 },
13127/* xchg.b r0h,$Dst32RnUnprefixedQI */
13128 {
13129 { 0, 0, 0, 0 },
13130 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13131 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80c }
13132 },
13133/* xchg.b r0h,$Dst32AnUnprefixedQI */
13134 {
13135 { 0, 0, 0, 0 },
13136 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13137 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08c }
13138 },
13139/* xchg.b r0h,[$Dst32AnUnprefixed] */
13140 {
13141 { 0, 0, 0, 0 },
13142 { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13143 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00c }
13144 },
13145/* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13146 {
13147 { 0, 0, 0, 0 },
13148 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13149 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20c00 }
13150 },
13151/* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13152 {
13153 { 0, 0, 0, 0 },
13154 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13155 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40c0000 }
13156 },
13157/* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13158 {
13159 { 0, 0, 0, 0 },
13160 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13161 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60c0000 }
13162 },
13163/* xchg.b r0h,${Dsp-16-u8}[sb] */
13164 {
13165 { 0, 0, 0, 0 },
13166 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13167 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28c00 }
13168 },
13169/* xchg.b r0h,${Dsp-16-u16}[sb] */
13170 {
13171 { 0, 0, 0, 0 },
13172 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13173 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48c0000 }
13174 },
13175/* xchg.b r0h,${Dsp-16-s8}[fb] */
13176 {
13177 { 0, 0, 0, 0 },
13178 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13179 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cc00 }
13180 },
13181/* xchg.b r0h,${Dsp-16-s16}[fb] */
13182 {
13183 { 0, 0, 0, 0 },
13184 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13185 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cc0000 }
13186 },
13187/* xchg.b r0h,${Dsp-16-u16} */
13188 {
13189 { 0, 0, 0, 0 },
13190 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } },
13191 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cc0000 }
13192 },
13193/* xchg.b r0h,${Dsp-16-u24} */
13194 {
13195 { 0, 0, 0, 0 },
13196 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), 0 } },
13197 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68c0000 }
13198 },
13199/* xchg.b a1,$Dst32RnUnprefixedQI */
13200 {
13201 { 0, 0, 0, 0 },
13202 { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13203 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80b }
13204 },
13205/* xchg.b a1,$Dst32AnUnprefixedQI */
13206 {
13207 { 0, 0, 0, 0 },
13208 { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13209 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08b }
13210 },
13211/* xchg.b a1,[$Dst32AnUnprefixed] */
13212 {
13213 { 0, 0, 0, 0 },
13214 { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13215 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00b }
13216 },
13217/* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13218 {
13219 { 0, 0, 0, 0 },
13220 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13221 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20b00 }
13222 },
13223/* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13224 {
13225 { 0, 0, 0, 0 },
13226 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13227 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40b0000 }
13228 },
13229/* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13230 {
13231 { 0, 0, 0, 0 },
13232 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13233 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60b0000 }
13234 },
13235/* xchg.b a1,${Dsp-16-u8}[sb] */
13236 {
13237 { 0, 0, 0, 0 },
13238 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13239 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28b00 }
13240 },
13241/* xchg.b a1,${Dsp-16-u16}[sb] */
13242 {
13243 { 0, 0, 0, 0 },
13244 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13245 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48b0000 }
13246 },
13247/* xchg.b a1,${Dsp-16-s8}[fb] */
13248 {
13249 { 0, 0, 0, 0 },
13250 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13251 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cb00 }
13252 },
13253/* xchg.b a1,${Dsp-16-s16}[fb] */
13254 {
13255 { 0, 0, 0, 0 },
13256 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13257 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cb0000 }
13258 },
13259/* xchg.b a1,${Dsp-16-u16} */
13260 {
13261 { 0, 0, 0, 0 },
13262 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } },
13263 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cb0000 }
13264 },
13265/* xchg.b a1,${Dsp-16-u24} */
13266 {
13267 { 0, 0, 0, 0 },
13268 { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } },
13269 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68b0000 }
13270 },
13271/* xchg.b a0,$Dst32RnUnprefixedQI */
13272 {
13273 { 0, 0, 0, 0 },
13274 { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13275 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80a }
13276 },
13277/* xchg.b a0,$Dst32AnUnprefixedQI */
13278 {
13279 { 0, 0, 0, 0 },
13280 { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13281 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08a }
13282 },
13283/* xchg.b a0,[$Dst32AnUnprefixed] */
13284 {
13285 { 0, 0, 0, 0 },
13286 { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13287 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00a }
13288 },
13289/* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13290 {
13291 { 0, 0, 0, 0 },
13292 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13293 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20a00 }
13294 },
13295/* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13296 {
13297 { 0, 0, 0, 0 },
13298 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13299 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40a0000 }
13300 },
13301/* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13302 {
13303 { 0, 0, 0, 0 },
13304 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13305 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60a0000 }
13306 },
13307/* xchg.b a0,${Dsp-16-u8}[sb] */
13308 {
13309 { 0, 0, 0, 0 },
13310 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13311 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28a00 }
13312 },
13313/* xchg.b a0,${Dsp-16-u16}[sb] */
13314 {
13315 { 0, 0, 0, 0 },
13316 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13317 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48a0000 }
13318 },
13319/* xchg.b a0,${Dsp-16-s8}[fb] */
13320 {
13321 { 0, 0, 0, 0 },
13322 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13323 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2ca00 }
13324 },
13325/* xchg.b a0,${Dsp-16-s16}[fb] */
13326 {
13327 { 0, 0, 0, 0 },
13328 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13329 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4ca0000 }
13330 },
13331/* xchg.b a0,${Dsp-16-u16} */
13332 {
13333 { 0, 0, 0, 0 },
13334 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } },
13335 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6ca0000 }
13336 },
13337/* xchg.b a0,${Dsp-16-u24} */
13338 {
13339 { 0, 0, 0, 0 },
13340 { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } },
13341 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68a0000 }
13342 },
13343/* xchg.b r1l,$Dst32RnUnprefixedQI */
13344 {
13345 { 0, 0, 0, 0 },
13346 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13347 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd809 }
13348 },
13349/* xchg.b r1l,$Dst32AnUnprefixedQI */
13350 {
13351 { 0, 0, 0, 0 },
13352 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13353 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd089 }
13354 },
13355/* xchg.b r1l,[$Dst32AnUnprefixed] */
13356 {
13357 { 0, 0, 0, 0 },
13358 { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13359 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd009 }
13360 },
13361/* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13362 {
13363 { 0, 0, 0, 0 },
13364 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13365 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20900 }
13366 },
13367/* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13368 {
13369 { 0, 0, 0, 0 },
13370 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13371 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4090000 }
13372 },
13373/* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13374 {
13375 { 0, 0, 0, 0 },
13376 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13377 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6090000 }
13378 },
13379/* xchg.b r1l,${Dsp-16-u8}[sb] */
13380 {
13381 { 0, 0, 0, 0 },
13382 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13383 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28900 }
13384 },
13385/* xchg.b r1l,${Dsp-16-u16}[sb] */
13386 {
13387 { 0, 0, 0, 0 },
13388 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13389 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4890000 }
13390 },
13391/* xchg.b r1l,${Dsp-16-s8}[fb] */
13392 {
13393 { 0, 0, 0, 0 },
13394 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13395 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c900 }
13396 },
13397/* xchg.b r1l,${Dsp-16-s16}[fb] */
13398 {
13399 { 0, 0, 0, 0 },
13400 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13401 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c90000 }
13402 },
13403/* xchg.b r1l,${Dsp-16-u16} */
13404 {
13405 { 0, 0, 0, 0 },
13406 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } },
13407 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c90000 }
13408 },
13409/* xchg.b r1l,${Dsp-16-u24} */
13410 {
13411 { 0, 0, 0, 0 },
13412 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), 0 } },
13413 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6890000 }
13414 },
13415/* xchg.b r0l,$Dst32RnUnprefixedQI */
13416 {
13417 { 0, 0, 0, 0 },
13418 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13419 & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd808 }
13420 },
13421/* xchg.b r0l,$Dst32AnUnprefixedQI */
13422 {
13423 { 0, 0, 0, 0 },
13424 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13425 & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd088 }
13426 },
13427/* xchg.b r0l,[$Dst32AnUnprefixed] */
13428 {
13429 { 0, 0, 0, 0 },
13430 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13431 & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd008 }
13432 },
13433/* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13434 {
13435 { 0, 0, 0, 0 },
13436 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13437 & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20800 }
13438 },
13439/* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13440 {
13441 { 0, 0, 0, 0 },
13442 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13443 & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4080000 }
13444 },
13445/* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13446 {
13447 { 0, 0, 0, 0 },
13448 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13449 & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6080000 }
13450 },
13451/* xchg.b r0l,${Dsp-16-u8}[sb] */
13452 {
13453 { 0, 0, 0, 0 },
13454 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13455 & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28800 }
13456 },
13457/* xchg.b r0l,${Dsp-16-u16}[sb] */
13458 {
13459 { 0, 0, 0, 0 },
13460 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13461 & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4880000 }
13462 },
13463/* xchg.b r0l,${Dsp-16-s8}[fb] */
13464 {
13465 { 0, 0, 0, 0 },
13466 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13467 & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c800 }
13468 },
13469/* xchg.b r0l,${Dsp-16-s16}[fb] */
13470 {
13471 { 0, 0, 0, 0 },
13472 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13473 & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c80000 }
13474 },
13475/* xchg.b r0l,${Dsp-16-u16} */
13476 {
13477 { 0, 0, 0, 0 },
13478 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
13479 & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c80000 }
13480 },
13481/* xchg.b r0l,${Dsp-16-u24} */
13482 {
13483 { 0, 0, 0, 0 },
13484 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), 0 } },
13485 & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6880000 }
13486 },
13487/* xchg.w r3,$Dst16RnHI */
13488 {
13489 { 0, 0, 0, 0 },
13490 { { MNEM, ' ', 'r', '3', ',', OP (DST16RNHI), 0 } },
13491 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b30 }
13492 },
13493/* xchg.w r3,$Dst16AnHI */
13494 {
13495 { 0, 0, 0, 0 },
13496 { { MNEM, ' ', 'r', '3', ',', OP (DST16ANHI), 0 } },
13497 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b34 }
13498 },
13499/* xchg.w r3,[$Dst16An] */
13500 {
13501 { 0, 0, 0, 0 },
13502 { { MNEM, ' ', 'r', '3', ',', '[', OP (DST16AN), ']', 0 } },
13503 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b36 }
13504 },
13505/* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
13506 {
13507 { 0, 0, 0, 0 },
13508 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13509 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b3800 }
13510 },
13511/* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
13512 {
13513 { 0, 0, 0, 0 },
13514 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13515 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b3c0000 }
13516 },
13517/* xchg.w r3,${Dsp-16-u8}[sb] */
13518 {
13519 { 0, 0, 0, 0 },
13520 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13521 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b3a00 }
13522 },
13523/* xchg.w r3,${Dsp-16-u16}[sb] */
13524 {
13525 { 0, 0, 0, 0 },
13526 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13527 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b3e0000 }
13528 },
13529/* xchg.w r3,${Dsp-16-s8}[fb] */
13530 {
13531 { 0, 0, 0, 0 },
13532 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13533 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b3b00 }
13534 },
13535/* xchg.w r3,${Dsp-16-u16} */
13536 {
13537 { 0, 0, 0, 0 },
13538 { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } },
13539 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b3f0000 }
13540 },
13541/* xchg.w r2,$Dst16RnHI */
13542 {
13543 { 0, 0, 0, 0 },
13544 { { MNEM, ' ', 'r', '2', ',', OP (DST16RNHI), 0 } },
13545 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b20 }
13546 },
13547/* xchg.w r2,$Dst16AnHI */
13548 {
13549 { 0, 0, 0, 0 },
13550 { { MNEM, ' ', 'r', '2', ',', OP (DST16ANHI), 0 } },
13551 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b24 }
13552 },
13553/* xchg.w r2,[$Dst16An] */
13554 {
13555 { 0, 0, 0, 0 },
13556 { { MNEM, ' ', 'r', '2', ',', '[', OP (DST16AN), ']', 0 } },
13557 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b26 }
13558 },
13559/* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
13560 {
13561 { 0, 0, 0, 0 },
13562 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13563 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b2800 }
13564 },
13565/* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
13566 {
13567 { 0, 0, 0, 0 },
13568 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13569 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b2c0000 }
13570 },
13571/* xchg.w r2,${Dsp-16-u8}[sb] */
13572 {
13573 { 0, 0, 0, 0 },
13574 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13575 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b2a00 }
13576 },
13577/* xchg.w r2,${Dsp-16-u16}[sb] */
13578 {
13579 { 0, 0, 0, 0 },
13580 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13581 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b2e0000 }
13582 },
13583/* xchg.w r2,${Dsp-16-s8}[fb] */
13584 {
13585 { 0, 0, 0, 0 },
13586 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13587 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b2b00 }
13588 },
13589/* xchg.w r2,${Dsp-16-u16} */
13590 {
13591 { 0, 0, 0, 0 },
13592 { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } },
13593 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b2f0000 }
13594 },
13595/* xchg.w r1,$Dst16RnHI */
13596 {
13597 { 0, 0, 0, 0 },
13598 { { MNEM, ' ', 'r', '1', ',', OP (DST16RNHI), 0 } },
13599 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b10 }
13600 },
13601/* xchg.w r1,$Dst16AnHI */
13602 {
13603 { 0, 0, 0, 0 },
13604 { { MNEM, ' ', 'r', '1', ',', OP (DST16ANHI), 0 } },
13605 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b14 }
13606 },
13607/* xchg.w r1,[$Dst16An] */
13608 {
13609 { 0, 0, 0, 0 },
13610 { { MNEM, ' ', 'r', '1', ',', '[', OP (DST16AN), ']', 0 } },
13611 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b16 }
13612 },
13613/* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
13614 {
13615 { 0, 0, 0, 0 },
13616 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13617 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b1800 }
13618 },
13619/* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
13620 {
13621 { 0, 0, 0, 0 },
13622 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13623 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b1c0000 }
13624 },
13625/* xchg.w r1,${Dsp-16-u8}[sb] */
13626 {
13627 { 0, 0, 0, 0 },
13628 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13629 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b1a00 }
13630 },
13631/* xchg.w r1,${Dsp-16-u16}[sb] */
13632 {
13633 { 0, 0, 0, 0 },
13634 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13635 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b1e0000 }
13636 },
13637/* xchg.w r1,${Dsp-16-s8}[fb] */
13638 {
13639 { 0, 0, 0, 0 },
13640 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13641 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b1b00 }
13642 },
13643/* xchg.w r1,${Dsp-16-u16} */
13644 {
13645 { 0, 0, 0, 0 },
13646 { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } },
13647 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b1f0000 }
13648 },
a1a280bb 13649/* xchg.w r0,$Dst16RnHI */
49f58d10
JB		 13650 {
13651 { 0, 0, 0, 0 },
a1a280bb
DD		 13652 { { MNEM, ' ', 'r', '0', ',', OP (DST16RNHI), 0 } },
13653 & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b00 }
49f58d10 13654 },
a1a280bb 13655/* xchg.w r0,$Dst16AnHI */
49f58d10
JB		 13656 {
13657 { 0, 0, 0, 0 },
a1a280bb
DD		 13658 { { MNEM, ' ', 'r', '0', ',', OP (DST16ANHI), 0 } },
13659 & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b04 }
49f58d10
JB		 13660 },
13661/* xchg.w r0,[$Dst16An] */
13662 {
13663 { 0, 0, 0, 0 },
13664 { { MNEM, ' ', 'r', '0', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13665 & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b06 }
49f58d10
JB		 13666 },
13667/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
13668 {
13669 { 0, 0, 0, 0 },
13670 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13671 & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b0800 }
49f58d10
JB		 13672 },
13673/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
13674 {
13675 { 0, 0, 0, 0 },
13676 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13677 & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b0c0000 }
49f58d10
JB		 13678 },
13679/* xchg.w r0,${Dsp-16-u8}[sb] */
13680 {
13681 { 0, 0, 0, 0 },
13682 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13683 & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b0a00 }
49f58d10
JB		 13684 },
13685/* xchg.w r0,${Dsp-16-u16}[sb] */
13686 {
13687 { 0, 0, 0, 0 },
13688 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13689 & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b0e0000 }
49f58d10
JB		 13690 },
13691/* xchg.w r0,${Dsp-16-s8}[fb] */
13692 {
13693 { 0, 0, 0, 0 },
13694 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13695 & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b0b00 }
49f58d10
JB		 13696 },
13697/* xchg.w r0,${Dsp-16-u16} */
13698 {
13699 { 0, 0, 0, 0 },
13700 { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13701 & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b0f0000 }
49f58d10
JB		 13702 },
13703/* xchg.b r1h,$Dst16RnQI */
13704 {
13705 { 0, 0, 0, 0 },
13706 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
a1a280bb 13707 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a30 }
49f58d10
JB		 13708 },
13709/* xchg.b r1h,$Dst16AnQI */
13710 {
13711 { 0, 0, 0, 0 },
13712 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
a1a280bb 13713 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a34 }
49f58d10
JB		 13714 },
13715/* xchg.b r1h,[$Dst16An] */
13716 {
13717 { 0, 0, 0, 0 },
13718 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13719 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a36 }
49f58d10
JB		 13720 },
13721/* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
13722 {
13723 { 0, 0, 0, 0 },
13724 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13725 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a3800 }
49f58d10
JB		 13726 },
13727/* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
13728 {
13729 { 0, 0, 0, 0 },
13730 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13731 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a3c0000 }
49f58d10
JB		 13732 },
13733/* xchg.b r1h,${Dsp-16-u8}[sb] */
13734 {
13735 { 0, 0, 0, 0 },
13736 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13737 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a3a00 }
49f58d10
JB		 13738 },
13739/* xchg.b r1h,${Dsp-16-u16}[sb] */
13740 {
13741 { 0, 0, 0, 0 },
13742 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13743 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a3e0000 }
49f58d10
JB		 13744 },
13745/* xchg.b r1h,${Dsp-16-s8}[fb] */
13746 {
13747 { 0, 0, 0, 0 },
13748 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13749 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a3b00 }
49f58d10
JB		 13750 },
13751/* xchg.b r1h,${Dsp-16-u16} */
13752 {
13753 { 0, 0, 0, 0 },
13754 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13755 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a3f0000 }
49f58d10
JB		 13756 },
13757/* xchg.b r1l,$Dst16RnQI */
13758 {
13759 { 0, 0, 0, 0 },
13760 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16RNQI), 0 } },
a1a280bb 13761 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a20 }
49f58d10
JB		 13762 },
13763/* xchg.b r1l,$Dst16AnQI */
13764 {
13765 { 0, 0, 0, 0 },
13766 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16ANQI), 0 } },
a1a280bb 13767 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a24 }
49f58d10
JB		 13768 },
13769/* xchg.b r1l,[$Dst16An] */
13770 {
13771 { 0, 0, 0, 0 },
13772 { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13773 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a26 }
49f58d10
JB		 13774 },
13775/* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
13776 {
13777 { 0, 0, 0, 0 },
13778 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13779 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a2800 }
49f58d10
JB		 13780 },
13781/* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
13782 {
13783 { 0, 0, 0, 0 },
13784 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13785 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a2c0000 }
49f58d10
JB		 13786 },
13787/* xchg.b r1l,${Dsp-16-u8}[sb] */
13788 {
13789 { 0, 0, 0, 0 },
13790 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13791 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a2a00 }
49f58d10
JB		 13792 },
13793/* xchg.b r1l,${Dsp-16-u16}[sb] */
13794 {
13795 { 0, 0, 0, 0 },
13796 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13797 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a2e0000 }
49f58d10
JB		 13798 },
13799/* xchg.b r1l,${Dsp-16-s8}[fb] */
13800 {
13801 { 0, 0, 0, 0 },
13802 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13803 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a2b00 }
49f58d10
JB		 13804 },
13805/* xchg.b r1l,${Dsp-16-u16} */
13806 {
13807 { 0, 0, 0, 0 },
13808 { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13809 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a2f0000 }
49f58d10
JB		 13810 },
13811/* xchg.b r0h,$Dst16RnQI */
13812 {
13813 { 0, 0, 0, 0 },
13814 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16RNQI), 0 } },
a1a280bb 13815 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a10 }
49f58d10
JB		 13816 },
13817/* xchg.b r0h,$Dst16AnQI */
13818 {
13819 { 0, 0, 0, 0 },
13820 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16ANQI), 0 } },
a1a280bb 13821 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a14 }
49f58d10
JB		 13822 },
13823/* xchg.b r0h,[$Dst16An] */
13824 {
13825 { 0, 0, 0, 0 },
13826 { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13827 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a16 }
49f58d10
JB		 13828 },
13829/* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
13830 {
13831 { 0, 0, 0, 0 },
13832 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13833 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a1800 }
49f58d10
JB		 13834 },
13835/* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
13836 {
13837 { 0, 0, 0, 0 },
13838 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13839 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a1c0000 }
49f58d10
JB		 13840 },
13841/* xchg.b r0h,${Dsp-16-u8}[sb] */
13842 {
13843 { 0, 0, 0, 0 },
13844 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13845 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a1a00 }
49f58d10
JB		 13846 },
13847/* xchg.b r0h,${Dsp-16-u16}[sb] */
13848 {
13849 { 0, 0, 0, 0 },
13850 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13851 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a1e0000 }
49f58d10
JB		 13852 },
13853/* xchg.b r0h,${Dsp-16-s8}[fb] */
13854 {
13855 { 0, 0, 0, 0 },
13856 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13857 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a1b00 }
49f58d10
JB		 13858 },
13859/* xchg.b r0h,${Dsp-16-u16} */
13860 {
13861 { 0, 0, 0, 0 },
13862 { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13863 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a1f0000 }
49f58d10
JB		 13864 },
13865/* xchg.b r0l,$Dst16RnQI */
13866 {
13867 { 0, 0, 0, 0 },
13868 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
a1a280bb 13869 & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a00 }
49f58d10
JB		 13870 },
13871/* xchg.b r0l,$Dst16AnQI */
13872 {
13873 { 0, 0, 0, 0 },
13874 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
a1a280bb 13875 & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a04 }
49f58d10
JB		 13876 },
13877/* xchg.b r0l,[$Dst16An] */
13878 {
13879 { 0, 0, 0, 0 },
13880 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 13881 & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a06 }
49f58d10
JB		 13882 },
13883/* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
13884 {
13885 { 0, 0, 0, 0 },
13886 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13887 & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a0800 }
49f58d10
JB		 13888 },
13889/* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
13890 {
13891 { 0, 0, 0, 0 },
13892 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 13893 & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a0c0000 }
49f58d10
JB		 13894 },
13895/* xchg.b r0l,${Dsp-16-u8}[sb] */
13896 {
13897 { 0, 0, 0, 0 },
13898 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 13899 & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a0a00 }
49f58d10
JB		 13900 },
13901/* xchg.b r0l,${Dsp-16-u16}[sb] */
13902 {
13903 { 0, 0, 0, 0 },
13904 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 13905 & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a0e0000 }
49f58d10
JB		 13906 },
13907/* xchg.b r0l,${Dsp-16-s8}[fb] */
13908 {
13909 { 0, 0, 0, 0 },
13910 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 13911 & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a0b00 }
49f58d10
JB		 13912 },
13913/* xchg.b r0l,${Dsp-16-u16} */
13914 {
13915 { 0, 0, 0, 0 },
13916 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
a1a280bb 13917 & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a0f0000 }
49f58d10
JB		 13918 },
13919/* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
13920 {
13921 { 0, 0, 0, 0 },
13922 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
13923 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2d000000 }
13924 },
13925/* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
13926 {
13927 { 0, 0, 0, 0 },
13928 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
13929 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3d000000 }
13930 },
13931/* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
13932 {
13933 { 0, 0, 0, 0 },
13934 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
13935 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1d000000 }
13936 },
13937/* tst.w${S} #${Imm-8-HI},r0 */
13938 {
13939 { 0, 0, 0, 0 },
13940 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
13941 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xd0000 }
13942 },
13943/* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
13944 {
13945 { 0, 0, 0, 0 },
13946 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
13947 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2c0000 }
13948 },
13949/* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
13950 {
13951 { 0, 0, 0, 0 },
13952 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
13953 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3c0000 }
13954 },
13955/* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
13956 {
13957 { 0, 0, 0, 0 },
13958 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
13959 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1c000000 }
13960 },
13961/* tst.b${S} #${Imm-8-QI},r0l */
13962 {
13963 { 0, 0, 0, 0 },
13964 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
13965 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xc00 }
13966 },
f75eb1c0 13967/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 13968 {
13969 { 0, 0, 0, 0 },
f75eb1c0 13970 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 13971 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990900 }
13972 },
f75eb1c0 13973/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
49f58d10
JB		 13974 {
13975 { 0, 0, 0, 0 },
f75eb1c0 13976 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 13977 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992900 }
13978 },
f75eb1c0 13979/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
49f58d10
JB		 13980 {
13981 { 0, 0, 0, 0 },
f75eb1c0 13982 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 13983 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993900 }
13984 },
f75eb1c0 13985/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 13986 {
13987 { 0, 0, 0, 0 },
f75eb1c0 13988 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 13989 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918900 }
13990 },
f75eb1c0 13991/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
49f58d10
JB		 13992 {
13993 { 0, 0, 0, 0 },
f75eb1c0 13994 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 13995 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a900 }
13996 },
f75eb1c0 13997/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
49f58d10
JB		 13998 {
13999 { 0, 0, 0, 0 },
f75eb1c0 14000 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14001 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b900 }
14002 },
f75eb1c0 14003/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14004 {
14005 { 0, 0, 0, 0 },
f75eb1c0 14006 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14007 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910900 }
14008 },
f75eb1c0 14009/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 14010 {
14011 { 0, 0, 0, 0 },
f75eb1c0 14012 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14013 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912900 }
14014 },
f75eb1c0 14015/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 14016 {
14017 { 0, 0, 0, 0 },
f75eb1c0 14018 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14019 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913900 }
14020 },
f75eb1c0 14021/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14022 {
14023 { 0, 0, 0, 0 },
f75eb1c0 14024 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14025 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930900 }
14026 },
f75eb1c0 14027/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14028 {
14029 { 0, 0, 0, 0 },
f75eb1c0 14030 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14031 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932900 }
14032 },
f75eb1c0 14033/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14034 {
14035 { 0, 0, 0, 0 },
f75eb1c0 14036 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14037 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933900 }
14038 },
f75eb1c0 14039/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14040 {
14041 { 0, 0, 0, 0 },
f75eb1c0 14042 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14043 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950900 }
14044 },
f75eb1c0 14045/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14046 {
14047 { 0, 0, 0, 0 },
f75eb1c0 14048 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14049 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952900 }
14050 },
f75eb1c0 14051/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14052 {
14053 { 0, 0, 0, 0 },
f75eb1c0 14054 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14055 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953900 }
14056 },
f75eb1c0 14057/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14058 {
14059 { 0, 0, 0, 0 },
f75eb1c0 14060 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14061 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970900 }
14062 },
f75eb1c0 14063/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14064 {
14065 { 0, 0, 0, 0 },
f75eb1c0 14066 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14067 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972900 }
14068 },
f75eb1c0 14069/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14070 {
14071 { 0, 0, 0, 0 },
f75eb1c0 14072 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14073 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973900 }
14074 },
f75eb1c0 14075/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
49f58d10
JB		 14076 {
14077 { 0, 0, 0, 0 },
f75eb1c0 14078 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14079 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938900 }
14080 },
f75eb1c0 14081/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
49f58d10
JB		 14082 {
14083 { 0, 0, 0, 0 },
f75eb1c0 14084 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14085 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a900 }
14086 },
f75eb1c0 14087/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
49f58d10
JB		 14088 {
14089 { 0, 0, 0, 0 },
f75eb1c0 14090 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14091 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b900 }
14092 },
f75eb1c0 14093/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
49f58d10
JB		 14094 {
14095 { 0, 0, 0, 0 },
f75eb1c0 14096 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14097 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958900 }
14098 },
f75eb1c0 14099/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
49f58d10
JB		 14100 {
14101 { 0, 0, 0, 0 },
f75eb1c0 14102 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14103 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a900 }
14104 },
f75eb1c0 14105/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
49f58d10
JB		 14106 {
14107 { 0, 0, 0, 0 },
f75eb1c0 14108 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14109 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b900 }
14110 },
f75eb1c0 14111/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
49f58d10
JB		 14112 {
14113 { 0, 0, 0, 0 },
f75eb1c0 14114 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14115 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c900 }
14116 },
f75eb1c0 14117/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
49f58d10
JB		 14118 {
14119 { 0, 0, 0, 0 },
f75eb1c0 14120 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14121 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e900 }
14122 },
f75eb1c0 14123/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
49f58d10
JB		 14124 {
14125 { 0, 0, 0, 0 },
f75eb1c0 14126 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14127 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f900 }
14128 },
f75eb1c0 14129/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
49f58d10
JB		 14130 {
14131 { 0, 0, 0, 0 },
f75eb1c0 14132 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14133 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c900 }
14134 },
f75eb1c0 14135/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
49f58d10
JB		 14136 {
14137 { 0, 0, 0, 0 },
f75eb1c0 14138 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14139 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e900 }
14140 },
f75eb1c0 14141/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
49f58d10
JB		 14142 {
14143 { 0, 0, 0, 0 },
f75eb1c0 14144 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14145 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f900 }
14146 },
f75eb1c0 14147/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
49f58d10
JB		 14148 {
14149 { 0, 0, 0, 0 },
f75eb1c0 14150 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 14151 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c900 }
14152 },
f75eb1c0 14153/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
49f58d10
JB		 14154 {
14155 { 0, 0, 0, 0 },
f75eb1c0 14156 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 14157 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e900 }
14158 },
f75eb1c0 14159/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
49f58d10
JB		 14160 {
14161 { 0, 0, 0, 0 },
f75eb1c0 14162 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 14163 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f900 }
14164 },
f75eb1c0 14165/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
49f58d10
JB		 14166 {
14167 { 0, 0, 0, 0 },
f75eb1c0 14168 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 14169 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978900 }
14170 },
f75eb1c0 14171/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
49f58d10
JB		 14172 {
14173 { 0, 0, 0, 0 },
f75eb1c0 14174 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 14175 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a900 }
14176 },
f75eb1c0 14177/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
49f58d10
JB		 14178 {
14179 { 0, 0, 0, 0 },
f75eb1c0 14180 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 14181 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b900 }
14182 },
f75eb1c0 14183/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 14184 {
14185 { 0, 0, 0, 0 },
f75eb1c0 14186 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14187 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90900 }
14188 },
f75eb1c0 14189/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
49f58d10
JB		 14190 {
14191 { 0, 0, 0, 0 },
f75eb1c0 14192 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14193 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92900 }
14194 },
f75eb1c0 14195/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
49f58d10
JB		 14196 {
14197 { 0, 0, 0, 0 },
f75eb1c0 14198 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14199 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93900 }
14200 },
f75eb1c0 14201/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
49f58d10
JB		 14202 {
14203 { 0, 0, 0, 0 },
f75eb1c0 14204 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14205 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93900 }
14206 },
f75eb1c0 14207/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 14208 {
14209 { 0, 0, 0, 0 },
f75eb1c0 14210 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14211 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18900 }
14212 },
f75eb1c0 14213/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
49f58d10
JB		 14214 {
14215 { 0, 0, 0, 0 },
f75eb1c0 14216 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14217 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a900 }
14218 },
f75eb1c0 14219/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
49f58d10
JB		 14220 {
14221 { 0, 0, 0, 0 },
f75eb1c0 14222 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14223 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b900 }
14224 },
f75eb1c0 14225/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
49f58d10
JB		 14226 {
14227 { 0, 0, 0, 0 },
f75eb1c0 14228 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14229 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b900 }
14230 },
f75eb1c0 14231/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14232 {
14233 { 0, 0, 0, 0 },
f75eb1c0 14234 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14235 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10900 }
14236 },
f75eb1c0 14237/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 14238 {
14239 { 0, 0, 0, 0 },
f75eb1c0 14240 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14241 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12900 }
14242 },
f75eb1c0 14243/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 14244 {
14245 { 0, 0, 0, 0 },
f75eb1c0 14246 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14247 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13900 }
14248 },
f75eb1c0 14249/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
49f58d10
JB		 14250 {
14251 { 0, 0, 0, 0 },
f75eb1c0 14252 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14253 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13900 }
14254 },
f75eb1c0 14255/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14256 {
14257 { 0, 0, 0, 0 },
f75eb1c0 14258 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14259 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30900 }
14260 },
f75eb1c0 14261/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14262 {
14263 { 0, 0, 0, 0 },
f75eb1c0 14264 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14265 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32900 }
14266 },
f75eb1c0 14267/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14268 {
14269 { 0, 0, 0, 0 },
f75eb1c0 14270 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14271 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33900 }
14272 },
f75eb1c0 14273/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14274 {
14275 { 0, 0, 0, 0 },
f75eb1c0 14276 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14277 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33900 }
14278 },
f75eb1c0 14279/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14280 {
14281 { 0, 0, 0, 0 },
f75eb1c0 14282 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14283 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50900 }
14284 },
f75eb1c0 14285/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14286 {
14287 { 0, 0, 0, 0 },
f75eb1c0 14288 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14289 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52900 }
14290 },
f75eb1c0 14291/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14292 {
14293 { 0, 0, 0, 0 },
f75eb1c0 14294 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14295 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53900 }
14296 },
f75eb1c0 14297/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14298 {
14299 { 0, 0, 0, 0 },
f75eb1c0 14300 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14301 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53900 }
14302 },
f75eb1c0 14303/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14304 {
14305 { 0, 0, 0, 0 },
f75eb1c0 14306 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14307 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70900 }
14308 },
f75eb1c0 14309/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14310 {
14311 { 0, 0, 0, 0 },
f75eb1c0 14312 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14313 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72900 }
14314 },
f75eb1c0 14315/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14316 {
14317 { 0, 0, 0, 0 },
f75eb1c0 14318 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14319 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73900 }
14320 },
f75eb1c0 14321/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14322 {
14323 { 0, 0, 0, 0 },
f75eb1c0 14324 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14325 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73900 }
14326 },
f75eb1c0 14327/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
49f58d10
JB		 14328 {
14329 { 0, 0, 0, 0 },
f75eb1c0 14330 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14331 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38900 }
14332 },
f75eb1c0 14333/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
49f58d10
JB		 14334 {
14335 { 0, 0, 0, 0 },
f75eb1c0 14336 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14337 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a900 }
14338 },
f75eb1c0 14339/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
49f58d10
JB		 14340 {
14341 { 0, 0, 0, 0 },
f75eb1c0 14342 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14343 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b900 }
14344 },
f75eb1c0 14345/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
49f58d10
JB		 14346 {
14347 { 0, 0, 0, 0 },
f75eb1c0 14348 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14349 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b900 }
14350 },
f75eb1c0 14351/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
49f58d10
JB		 14352 {
14353 { 0, 0, 0, 0 },
f75eb1c0 14354 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14355 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58900 }
14356 },
f75eb1c0 14357/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
49f58d10
JB		 14358 {
14359 { 0, 0, 0, 0 },
f75eb1c0 14360 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14361 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a900 }
14362 },
f75eb1c0 14363/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
49f58d10
JB		 14364 {
14365 { 0, 0, 0, 0 },
f75eb1c0 14366 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14367 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b900 }
14368 },
f75eb1c0 14369/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
49f58d10
JB		 14370 {
14371 { 0, 0, 0, 0 },
f75eb1c0 14372 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14373 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b900 }
14374 },
f75eb1c0 14375/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
49f58d10
JB		 14376 {
14377 { 0, 0, 0, 0 },
f75eb1c0 14378 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14379 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c900 }
14380 },
f75eb1c0 14381/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
49f58d10
JB		 14382 {
14383 { 0, 0, 0, 0 },
f75eb1c0 14384 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14385 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e900 }
14386 },
f75eb1c0 14387/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
49f58d10
JB		 14388 {
14389 { 0, 0, 0, 0 },
f75eb1c0 14390 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14391 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f900 }
14392 },
f75eb1c0 14393/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
49f58d10
JB		 14394 {
14395 { 0, 0, 0, 0 },
f75eb1c0 14396 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14397 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f900 }
14398 },
f75eb1c0 14399/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
49f58d10
JB		 14400 {
14401 { 0, 0, 0, 0 },
f75eb1c0 14402 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14403 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c900 }
14404 },
f75eb1c0 14405/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
49f58d10
JB		 14406 {
14407 { 0, 0, 0, 0 },
f75eb1c0 14408 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14409 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e900 }
14410 },
f75eb1c0 14411/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
49f58d10
JB		 14412 {
14413 { 0, 0, 0, 0 },
f75eb1c0 14414 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14415 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f900 }
14416 },
f75eb1c0 14417/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
49f58d10
JB		 14418 {
14419 { 0, 0, 0, 0 },
f75eb1c0 14420 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14421 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f900 }
14422 },
f75eb1c0 14423/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
49f58d10
JB		 14424 {
14425 { 0, 0, 0, 0 },
f75eb1c0 14426 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14427 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c900 }
14428 },
f75eb1c0 14429/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
49f58d10
JB		 14430 {
14431 { 0, 0, 0, 0 },
f75eb1c0 14432 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14433 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e900 }
14434 },
f75eb1c0 14435/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
49f58d10
JB		 14436 {
14437 { 0, 0, 0, 0 },
f75eb1c0 14438 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14439 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f900 }
14440 },
f75eb1c0 14441/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
49f58d10
JB		 14442 {
14443 { 0, 0, 0, 0 },
f75eb1c0 14444 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 14445 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f900 }
14446 },
f75eb1c0 14447/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
49f58d10
JB		 14448 {
14449 { 0, 0, 0, 0 },
f75eb1c0 14450 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14451 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78900 }
14452 },
f75eb1c0 14453/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
49f58d10
JB		 14454 {
14455 { 0, 0, 0, 0 },
f75eb1c0 14456 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14457 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a900 }
14458 },
f75eb1c0 14459/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
49f58d10
JB		 14460 {
14461 { 0, 0, 0, 0 },
f75eb1c0 14462 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14463 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b900 }
14464 },
f75eb1c0 14465/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
49f58d10
JB		 14466 {
14467 { 0, 0, 0, 0 },
f75eb1c0 14468 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 14469 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b900 }
14470 },
f75eb1c0 14471/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 14472 {
14473 { 0, 0, 0, 0 },
f75eb1c0 14474 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14475 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90900 }
14476 },
f75eb1c0 14477/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
49f58d10
JB		 14478 {
14479 { 0, 0, 0, 0 },
f75eb1c0 14480 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14481 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92900 }
14482 },
f75eb1c0 14483/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 14484 {
14485 { 0, 0, 0, 0 },
f75eb1c0 14486 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14487 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18900 }
14488 },
f75eb1c0 14489/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
49f58d10
JB		 14490 {
14491 { 0, 0, 0, 0 },
f75eb1c0 14492 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14493 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a900 }
14494 },
f75eb1c0 14495/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14496 {
14497 { 0, 0, 0, 0 },
f75eb1c0 14498 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14499 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10900 }
14500 },
f75eb1c0 14501/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
49f58d10
JB		 14502 {
14503 { 0, 0, 0, 0 },
f75eb1c0 14504 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14505 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12900 }
14506 },
f75eb1c0 14507/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14508 {
14509 { 0, 0, 0, 0 },
f75eb1c0 14510 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14511 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30900 }
14512 },
f75eb1c0 14513/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14514 {
14515 { 0, 0, 0, 0 },
f75eb1c0 14516 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14517 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32900 }
14518 },
f75eb1c0 14519/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14520 {
14521 { 0, 0, 0, 0 },
f75eb1c0 14522 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14523 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50900 }
14524 },
f75eb1c0 14525/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14526 {
14527 { 0, 0, 0, 0 },
f75eb1c0 14528 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14529 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52900 }
14530 },
f75eb1c0 14531/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14532 {
14533 { 0, 0, 0, 0 },
f75eb1c0 14534 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14535 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70900 }
14536 },
f75eb1c0 14537/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14538 {
14539 { 0, 0, 0, 0 },
f75eb1c0 14540 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14541 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72900 }
14542 },
f75eb1c0 14543/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
49f58d10
JB		 14544 {
14545 { 0, 0, 0, 0 },
f75eb1c0 14546 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14547 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38900 }
14548 },
f75eb1c0 14549/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
49f58d10
JB		 14550 {
14551 { 0, 0, 0, 0 },
f75eb1c0 14552 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14553 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a900 }
14554 },
f75eb1c0 14555/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
49f58d10
JB		 14556 {
14557 { 0, 0, 0, 0 },
f75eb1c0 14558 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14559 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58900 }
14560 },
f75eb1c0 14561/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
49f58d10
JB		 14562 {
14563 { 0, 0, 0, 0 },
f75eb1c0 14564 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14565 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a900 }
14566 },
f75eb1c0 14567/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
49f58d10
JB		 14568 {
14569 { 0, 0, 0, 0 },
f75eb1c0 14570 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14571 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c900 }
14572 },
f75eb1c0 14573/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
49f58d10
JB		 14574 {
14575 { 0, 0, 0, 0 },
f75eb1c0 14576 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14577 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e900 }
14578 },
f75eb1c0 14579/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
49f58d10
JB		 14580 {
14581 { 0, 0, 0, 0 },
f75eb1c0 14582 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14583 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c900 }
14584 },
f75eb1c0 14585/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
49f58d10
JB		 14586 {
14587 { 0, 0, 0, 0 },
f75eb1c0 14588 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14589 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e900 }
14590 },
f75eb1c0 14591/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
49f58d10
JB		 14592 {
14593 { 0, 0, 0, 0 },
f75eb1c0 14594 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 14595 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c900 }
14596 },
f75eb1c0 14597/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
49f58d10
JB		 14598 {
14599 { 0, 0, 0, 0 },
f75eb1c0 14600 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 14601 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e900 }
14602 },
f75eb1c0 14603/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
49f58d10
JB		 14604 {
14605 { 0, 0, 0, 0 },
f75eb1c0 14606 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 14607 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78900 }
14608 },
f75eb1c0 14609/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
49f58d10
JB		 14610 {
14611 { 0, 0, 0, 0 },
f75eb1c0 14612 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 14613 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a900 }
14614 },
f75eb1c0 14615/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
49f58d10
JB		 14616 {
14617 { 0, 0, 0, 0 },
f75eb1c0 14618 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14619 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c909 }
14620 },
f75eb1c0 14621/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
49f58d10
JB		 14622 {
14623 { 0, 0, 0, 0 },
f75eb1c0 14624 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14625 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18929 }
14626 },
f75eb1c0 14627/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 14628 {
14629 { 0, 0, 0, 0 },
f75eb1c0 14630 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
49f58d10
JB		 14631 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18909 }
14632 },
f75eb1c0 14633/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
49f58d10
JB		 14634 {
14635 { 0, 0, 0, 0 },
f75eb1c0 14636 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14637 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c189 }
14638 },
f75eb1c0 14639/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
49f58d10
JB		 14640 {
14641 { 0, 0, 0, 0 },
f75eb1c0 14642 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14643 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a9 }
14644 },
f75eb1c0 14645/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 14646 {
14647 { 0, 0, 0, 0 },
f75eb1c0 14648 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
49f58d10
JB		 14649 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18189 }
14650 },
f75eb1c0 14651/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
49f58d10
JB		 14652 {
14653 { 0, 0, 0, 0 },
f75eb1c0 14654 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14655 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c109 }
14656 },
f75eb1c0 14657/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
49f58d10
JB		 14658 {
14659 { 0, 0, 0, 0 },
f75eb1c0 14660 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14661 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18129 }
14662 },
f75eb1c0 14663/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14664 {
14665 { 0, 0, 0, 0 },
f75eb1c0 14666 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14667 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18109 }
14668 },
f75eb1c0 14669/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14670 {
14671 { 0, 0, 0, 0 },
f75eb1c0 14672 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14673 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30900 }
14674 },
f75eb1c0 14675/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14676 {
14677 { 0, 0, 0, 0 },
f75eb1c0 14678 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14679 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832900 }
14680 },
f75eb1c0 14681/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14682 {
14683 { 0, 0, 0, 0 },
f75eb1c0 14684 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14685 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830900 }
14686 },
f75eb1c0 14687/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14688 {
14689 { 0, 0, 0, 0 },
f75eb1c0 14690 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14691 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50900 }
14692 },
f75eb1c0 14693/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14694 {
14695 { 0, 0, 0, 0 },
f75eb1c0 14696 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14697 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852900 }
14698 },
f75eb1c0 14699/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14700 {
14701 { 0, 0, 0, 0 },
f75eb1c0 14702 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14703 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850900 }
14704 },
f75eb1c0 14705/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14706 {
14707 { 0, 0, 0, 0 },
f75eb1c0 14708 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14709 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70900 }
14710 },
f75eb1c0 14711/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14712 {
14713 { 0, 0, 0, 0 },
f75eb1c0 14714 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14715 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872900 }
14716 },
f75eb1c0 14717/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14718 {
14719 { 0, 0, 0, 0 },
f75eb1c0 14720 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14721 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870900 }
14722 },
f75eb1c0 14723/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
49f58d10
JB		 14724 {
14725 { 0, 0, 0, 0 },
f75eb1c0 14726 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14727 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38900 }
14728 },
f75eb1c0 14729/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
49f58d10
JB		 14730 {
14731 { 0, 0, 0, 0 },
f75eb1c0 14732 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14733 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a900 }
14734 },
f75eb1c0 14735/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
49f58d10
JB		 14736 {
14737 { 0, 0, 0, 0 },
f75eb1c0 14738 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14739 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838900 }
14740 },
f75eb1c0 14741/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
49f58d10
JB		 14742 {
14743 { 0, 0, 0, 0 },
f75eb1c0 14744 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14745 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58900 }
14746 },
f75eb1c0 14747/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
49f58d10
JB		 14748 {
14749 { 0, 0, 0, 0 },
f75eb1c0 14750 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14751 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a900 }
14752 },
f75eb1c0 14753/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
49f58d10
JB		 14754 {
14755 { 0, 0, 0, 0 },
f75eb1c0 14756 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14757 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858900 }
14758 },
f75eb1c0 14759/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
49f58d10
JB		 14760 {
14761 { 0, 0, 0, 0 },
f75eb1c0 14762 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14763 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c900 }
14764 },
f75eb1c0 14765/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
49f58d10
JB		 14766 {
14767 { 0, 0, 0, 0 },
f75eb1c0 14768 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14769 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e900 }
14770 },
f75eb1c0 14771/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
49f58d10
JB		 14772 {
14773 { 0, 0, 0, 0 },
f75eb1c0 14774 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14775 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c900 }
14776 },
f75eb1c0 14777/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
49f58d10
JB		 14778 {
14779 { 0, 0, 0, 0 },
f75eb1c0 14780 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14781 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c900 }
14782 },
f75eb1c0 14783/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
49f58d10
JB		 14784 {
14785 { 0, 0, 0, 0 },
f75eb1c0 14786 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14787 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e900 }
14788 },
f75eb1c0 14789/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
49f58d10
JB		 14790 {
14791 { 0, 0, 0, 0 },
f75eb1c0 14792 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14793 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c900 }
14794 },
f75eb1c0 14795/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
49f58d10
JB		 14796 {
14797 { 0, 0, 0, 0 },
f75eb1c0 14798 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 14799 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c900 }
14800 },
f75eb1c0 14801/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
49f58d10
JB		 14802 {
14803 { 0, 0, 0, 0 },
f75eb1c0 14804 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 14805 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e900 }
14806 },
f75eb1c0 14807/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
49f58d10
JB		 14808 {
14809 { 0, 0, 0, 0 },
f75eb1c0 14810 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 14811 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c900 }
14812 },
f75eb1c0 14813/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
49f58d10
JB		 14814 {
14815 { 0, 0, 0, 0 },
f75eb1c0 14816 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 14817 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78900 }
14818 },
f75eb1c0 14819/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
49f58d10
JB		 14820 {
14821 { 0, 0, 0, 0 },
f75eb1c0 14822 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 14823 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a900 }
14824 },
f75eb1c0 14825/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
49f58d10
JB		 14826 {
14827 { 0, 0, 0, 0 },
f75eb1c0 14828 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 14829 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878900 }
14830 },
f75eb1c0 14831/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 14832 {
14833 { 0, 0, 0, 0 },
f75eb1c0 14834 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14835 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980900 }
14836 },
f75eb1c0 14837/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
49f58d10
JB		 14838 {
14839 { 0, 0, 0, 0 },
f75eb1c0 14840 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14841 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982900 }
14842 },
f75eb1c0 14843/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
49f58d10
JB		 14844 {
14845 { 0, 0, 0, 0 },
f75eb1c0 14846 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 14847 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983900 }
14848 },
f75eb1c0 14849/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 14850 {
14851 { 0, 0, 0, 0 },
f75eb1c0 14852 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14853 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908900 }
14854 },
f75eb1c0 14855/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
49f58d10
JB		 14856 {
14857 { 0, 0, 0, 0 },
f75eb1c0 14858 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14859 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a900 }
14860 },
f75eb1c0 14861/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
49f58d10
JB		 14862 {
14863 { 0, 0, 0, 0 },
f75eb1c0 14864 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 14865 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b900 }
14866 },
f75eb1c0 14867/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 14868 {
14869 { 0, 0, 0, 0 },
f75eb1c0 14870 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14871 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900900 }
14872 },
f75eb1c0 14873/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 14874 {
14875 { 0, 0, 0, 0 },
f75eb1c0 14876 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14877 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902900 }
14878 },
f75eb1c0 14879/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 14880 {
14881 { 0, 0, 0, 0 },
f75eb1c0 14882 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14883 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903900 }
14884 },
f75eb1c0 14885/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14886 {
14887 { 0, 0, 0, 0 },
f75eb1c0 14888 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14889 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920900 }
14890 },
f75eb1c0 14891/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14892 {
14893 { 0, 0, 0, 0 },
f75eb1c0 14894 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14895 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922900 }
14896 },
f75eb1c0 14897/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 14898 {
14899 { 0, 0, 0, 0 },
f75eb1c0 14900 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14901 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923900 }
14902 },
f75eb1c0 14903/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14904 {
14905 { 0, 0, 0, 0 },
f75eb1c0 14906 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14907 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940900 }
14908 },
f75eb1c0 14909/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14910 {
14911 { 0, 0, 0, 0 },
f75eb1c0 14912 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14913 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942900 }
14914 },
f75eb1c0 14915/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 14916 {
14917 { 0, 0, 0, 0 },
f75eb1c0 14918 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14919 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943900 }
14920 },
f75eb1c0 14921/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14922 {
14923 { 0, 0, 0, 0 },
f75eb1c0 14924 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14925 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960900 }
14926 },
f75eb1c0 14927/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14928 {
14929 { 0, 0, 0, 0 },
f75eb1c0 14930 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14931 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962900 }
14932 },
f75eb1c0 14933/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 14934 {
14935 { 0, 0, 0, 0 },
f75eb1c0 14936 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 14937 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963900 }
14938 },
f75eb1c0 14939/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
49f58d10
JB		 14940 {
14941 { 0, 0, 0, 0 },
f75eb1c0 14942 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14943 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928900 }
14944 },
f75eb1c0 14945/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
49f58d10
JB		 14946 {
14947 { 0, 0, 0, 0 },
f75eb1c0 14948 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14949 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a900 }
14950 },
f75eb1c0 14951/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
49f58d10
JB		 14952 {
14953 { 0, 0, 0, 0 },
f75eb1c0 14954 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14955 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b900 }
14956 },
f75eb1c0 14957/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
49f58d10
JB		 14958 {
14959 { 0, 0, 0, 0 },
f75eb1c0 14960 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14961 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948900 }
14962 },
f75eb1c0 14963/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
49f58d10
JB		 14964 {
14965 { 0, 0, 0, 0 },
f75eb1c0 14966 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14967 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a900 }
14968 },
f75eb1c0 14969/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
49f58d10
JB		 14970 {
14971 { 0, 0, 0, 0 },
f75eb1c0 14972 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 14973 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b900 }
14974 },
f75eb1c0 14975/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
49f58d10
JB		 14976 {
14977 { 0, 0, 0, 0 },
f75eb1c0 14978 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14979 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c900 }
14980 },
f75eb1c0 14981/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
49f58d10
JB		 14982 {
14983 { 0, 0, 0, 0 },
f75eb1c0 14984 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14985 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e900 }
14986 },
f75eb1c0 14987/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
49f58d10
JB		 14988 {
14989 { 0, 0, 0, 0 },
f75eb1c0 14990 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14991 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f900 }
14992 },
f75eb1c0 14993/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
49f58d10
JB		 14994 {
14995 { 0, 0, 0, 0 },
f75eb1c0 14996 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 14997 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c900 }
14998 },
f75eb1c0 14999/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
49f58d10
JB		 15000 {
15001 { 0, 0, 0, 0 },
f75eb1c0 15002 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15003 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e900 }
15004 },
f75eb1c0 15005/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
49f58d10
JB		 15006 {
15007 { 0, 0, 0, 0 },
f75eb1c0 15008 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15009 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f900 }
15010 },
f75eb1c0 15011/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
49f58d10
JB		 15012 {
15013 { 0, 0, 0, 0 },
f75eb1c0 15014 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 15015 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c900 }
15016 },
f75eb1c0 15017/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
49f58d10
JB		 15018 {
15019 { 0, 0, 0, 0 },
f75eb1c0 15020 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 15021 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e900 }
15022 },
f75eb1c0 15023/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
49f58d10
JB		 15024 {
15025 { 0, 0, 0, 0 },
f75eb1c0 15026 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49f58d10
JB		 15027 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f900 }
15028 },
f75eb1c0 15029/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
49f58d10
JB		 15030 {
15031 { 0, 0, 0, 0 },
f75eb1c0 15032 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 15033 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968900 }
15034 },
f75eb1c0 15035/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
49f58d10
JB		 15036 {
15037 { 0, 0, 0, 0 },
f75eb1c0 15038 { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 15039 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a900 }
15040 },
f75eb1c0 15041/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
49f58d10
JB		 15042 {
15043 { 0, 0, 0, 0 },
f75eb1c0 15044 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49f58d10
JB		 15045 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b900 }
15046 },
f75eb1c0 15047/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 15048 {
15049 { 0, 0, 0, 0 },
f75eb1c0 15050 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15051 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80900 }
15052 },
f75eb1c0 15053/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
49f58d10
JB		 15054 {
15055 { 0, 0, 0, 0 },
f75eb1c0 15056 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15057 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82900 }
15058 },
f75eb1c0 15059/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
49f58d10
JB		 15060 {
15061 { 0, 0, 0, 0 },
f75eb1c0 15062 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15063 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83900 }
15064 },
f75eb1c0 15065/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
49f58d10
JB		 15066 {
15067 { 0, 0, 0, 0 },
f75eb1c0 15068 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15069 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83900 }
15070 },
f75eb1c0 15071/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 15072 {
15073 { 0, 0, 0, 0 },
f75eb1c0 15074 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15075 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08900 }
15076 },
f75eb1c0 15077/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
49f58d10
JB		 15078 {
15079 { 0, 0, 0, 0 },
f75eb1c0 15080 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15081 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a900 }
15082 },
f75eb1c0 15083/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
49f58d10
JB		 15084 {
15085 { 0, 0, 0, 0 },
f75eb1c0 15086 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15087 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b900 }
15088 },
f75eb1c0 15089/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
49f58d10
JB		 15090 {
15091 { 0, 0, 0, 0 },
f75eb1c0 15092 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15093 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b900 }
15094 },
f75eb1c0 15095/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 15096 {
15097 { 0, 0, 0, 0 },
f75eb1c0 15098 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15099 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00900 }
15100 },
f75eb1c0 15101/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 15102 {
15103 { 0, 0, 0, 0 },
f75eb1c0 15104 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15105 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02900 }
15106 },
f75eb1c0 15107/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 15108 {
15109 { 0, 0, 0, 0 },
f75eb1c0 15110 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15111 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03900 }
15112 },
f75eb1c0 15113/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
49f58d10
JB		 15114 {
15115 { 0, 0, 0, 0 },
f75eb1c0 15116 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15117 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03900 }
15118 },
f75eb1c0 15119/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15120 {
15121 { 0, 0, 0, 0 },
f75eb1c0 15122 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15123 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20900 }
15124 },
f75eb1c0 15125/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15126 {
15127 { 0, 0, 0, 0 },
f75eb1c0 15128 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15129 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22900 }
15130 },
f75eb1c0 15131/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15132 {
15133 { 0, 0, 0, 0 },
f75eb1c0 15134 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15135 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23900 }
15136 },
f75eb1c0 15137/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15138 {
15139 { 0, 0, 0, 0 },
f75eb1c0 15140 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15141 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23900 }
15142 },
f75eb1c0 15143/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15144 {
15145 { 0, 0, 0, 0 },
f75eb1c0 15146 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15147 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40900 }
15148 },
f75eb1c0 15149/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15150 {
15151 { 0, 0, 0, 0 },
f75eb1c0 15152 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15153 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42900 }
15154 },
f75eb1c0 15155/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15156 {
15157 { 0, 0, 0, 0 },
f75eb1c0 15158 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15159 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43900 }
15160 },
f75eb1c0 15161/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15162 {
15163 { 0, 0, 0, 0 },
f75eb1c0 15164 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15165 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43900 }
15166 },
f75eb1c0 15167/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15168 {
15169 { 0, 0, 0, 0 },
f75eb1c0 15170 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15171 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60900 }
15172 },
f75eb1c0 15173/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15174 {
15175 { 0, 0, 0, 0 },
f75eb1c0 15176 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15177 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62900 }
15178 },
f75eb1c0 15179/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15180 {
15181 { 0, 0, 0, 0 },
f75eb1c0 15182 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15183 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63900 }
15184 },
f75eb1c0 15185/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15186 {
15187 { 0, 0, 0, 0 },
f75eb1c0 15188 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15189 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63900 }
15190 },
f75eb1c0 15191/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
49f58d10
JB		 15192 {
15193 { 0, 0, 0, 0 },
f75eb1c0 15194 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15195 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28900 }
15196 },
f75eb1c0 15197/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
49f58d10
JB		 15198 {
15199 { 0, 0, 0, 0 },
f75eb1c0 15200 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15201 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a900 }
15202 },
f75eb1c0 15203/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
49f58d10
JB		 15204 {
15205 { 0, 0, 0, 0 },
f75eb1c0 15206 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15207 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b900 }
15208 },
f75eb1c0 15209/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
49f58d10
JB		 15210 {
15211 { 0, 0, 0, 0 },
f75eb1c0 15212 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15213 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b900 }
15214 },
f75eb1c0 15215/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
49f58d10
JB		 15216 {
15217 { 0, 0, 0, 0 },
f75eb1c0 15218 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15219 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48900 }
15220 },
f75eb1c0 15221/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
49f58d10
JB		 15222 {
15223 { 0, 0, 0, 0 },
f75eb1c0 15224 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15225 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a900 }
15226 },
f75eb1c0 15227/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
49f58d10
JB		 15228 {
15229 { 0, 0, 0, 0 },
f75eb1c0 15230 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15231 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b900 }
15232 },
f75eb1c0 15233/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
49f58d10
JB		 15234 {
15235 { 0, 0, 0, 0 },
f75eb1c0 15236 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15237 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b900 }
15238 },
f75eb1c0 15239/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
49f58d10
JB		 15240 {
15241 { 0, 0, 0, 0 },
f75eb1c0 15242 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15243 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c900 }
15244 },
f75eb1c0 15245/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
49f58d10
JB		 15246 {
15247 { 0, 0, 0, 0 },
f75eb1c0 15248 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15249 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e900 }
15250 },
f75eb1c0 15251/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
49f58d10
JB		 15252 {
15253 { 0, 0, 0, 0 },
f75eb1c0 15254 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15255 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f900 }
15256 },
f75eb1c0 15257/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
49f58d10
JB		 15258 {
15259 { 0, 0, 0, 0 },
f75eb1c0 15260 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15261 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f900 }
15262 },
f75eb1c0 15263/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
49f58d10
JB		 15264 {
15265 { 0, 0, 0, 0 },
f75eb1c0 15266 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15267 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c900 }
15268 },
f75eb1c0 15269/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
49f58d10
JB		 15270 {
15271 { 0, 0, 0, 0 },
f75eb1c0 15272 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15273 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e900 }
15274 },
f75eb1c0 15275/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
49f58d10
JB		 15276 {
15277 { 0, 0, 0, 0 },
f75eb1c0 15278 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15279 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f900 }
15280 },
f75eb1c0 15281/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
49f58d10
JB		 15282 {
15283 { 0, 0, 0, 0 },
f75eb1c0 15284 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15285 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f900 }
15286 },
f75eb1c0 15287/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
49f58d10
JB		 15288 {
15289 { 0, 0, 0, 0 },
f75eb1c0 15290 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15291 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c900 }
15292 },
f75eb1c0 15293/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
49f58d10
JB		 15294 {
15295 { 0, 0, 0, 0 },
f75eb1c0 15296 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15297 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e900 }
15298 },
f75eb1c0 15299/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
49f58d10
JB		 15300 {
15301 { 0, 0, 0, 0 },
f75eb1c0 15302 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15303 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f900 }
15304 },
f75eb1c0 15305/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
49f58d10
JB		 15306 {
15307 { 0, 0, 0, 0 },
f75eb1c0 15308 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
49f58d10
JB		 15309 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f900 }
15310 },
f75eb1c0 15311/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
49f58d10
JB		 15312 {
15313 { 0, 0, 0, 0 },
f75eb1c0 15314 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15315 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68900 }
15316 },
f75eb1c0 15317/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
49f58d10
JB		 15318 {
15319 { 0, 0, 0, 0 },
f75eb1c0 15320 { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15321 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a900 }
15322 },
f75eb1c0 15323/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
49f58d10
JB		 15324 {
15325 { 0, 0, 0, 0 },
f75eb1c0 15326 { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15327 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b900 }
15328 },
f75eb1c0 15329/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
49f58d10
JB		 15330 {
15331 { 0, 0, 0, 0 },
f75eb1c0 15332 { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
49f58d10
JB		 15333 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b900 }
15334 },
f75eb1c0 15335/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 15336 {
15337 { 0, 0, 0, 0 },
f75eb1c0 15338 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15339 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80900 }
15340 },
f75eb1c0 15341/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
49f58d10
JB		 15342 {
15343 { 0, 0, 0, 0 },
f75eb1c0 15344 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15345 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82900 }
15346 },
f75eb1c0 15347/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 15348 {
15349 { 0, 0, 0, 0 },
f75eb1c0 15350 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15351 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08900 }
15352 },
f75eb1c0 15353/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
49f58d10
JB		 15354 {
15355 { 0, 0, 0, 0 },
f75eb1c0 15356 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15357 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a900 }
15358 },
f75eb1c0 15359/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 15360 {
15361 { 0, 0, 0, 0 },
f75eb1c0 15362 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15363 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00900 }
15364 },
f75eb1c0 15365/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
49f58d10
JB		 15366 {
15367 { 0, 0, 0, 0 },
f75eb1c0 15368 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15369 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02900 }
15370 },
f75eb1c0 15371/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15372 {
15373 { 0, 0, 0, 0 },
f75eb1c0 15374 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15375 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20900 }
15376 },
f75eb1c0 15377/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15378 {
15379 { 0, 0, 0, 0 },
f75eb1c0 15380 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15381 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22900 }
15382 },
f75eb1c0 15383/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15384 {
15385 { 0, 0, 0, 0 },
f75eb1c0 15386 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15387 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40900 }
15388 },
f75eb1c0 15389/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15390 {
15391 { 0, 0, 0, 0 },
f75eb1c0 15392 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15393 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42900 }
15394 },
f75eb1c0 15395/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15396 {
15397 { 0, 0, 0, 0 },
f75eb1c0 15398 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15399 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60900 }
15400 },
f75eb1c0 15401/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15402 {
15403 { 0, 0, 0, 0 },
f75eb1c0 15404 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15405 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62900 }
15406 },
f75eb1c0 15407/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
49f58d10
JB		 15408 {
15409 { 0, 0, 0, 0 },
f75eb1c0 15410 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15411 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28900 }
15412 },
f75eb1c0 15413/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
49f58d10
JB		 15414 {
15415 { 0, 0, 0, 0 },
f75eb1c0 15416 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15417 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a900 }
15418 },
f75eb1c0 15419/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
49f58d10
JB		 15420 {
15421 { 0, 0, 0, 0 },
f75eb1c0 15422 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15423 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48900 }
15424 },
f75eb1c0 15425/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
49f58d10
JB		 15426 {
15427 { 0, 0, 0, 0 },
f75eb1c0 15428 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15429 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a900 }
15430 },
f75eb1c0 15431/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
49f58d10
JB		 15432 {
15433 { 0, 0, 0, 0 },
f75eb1c0 15434 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15435 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c900 }
15436 },
f75eb1c0 15437/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
49f58d10
JB		 15438 {
15439 { 0, 0, 0, 0 },
f75eb1c0 15440 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15441 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e900 }
15442 },
f75eb1c0 15443/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
49f58d10
JB		 15444 {
15445 { 0, 0, 0, 0 },
f75eb1c0 15446 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15447 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c900 }
15448 },
f75eb1c0 15449/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
49f58d10
JB		 15450 {
15451 { 0, 0, 0, 0 },
f75eb1c0 15452 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15453 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e900 }
15454 },
f75eb1c0 15455/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
49f58d10
JB		 15456 {
15457 { 0, 0, 0, 0 },
f75eb1c0 15458 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 15459 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c900 }
15460 },
f75eb1c0 15461/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
49f58d10
JB		 15462 {
15463 { 0, 0, 0, 0 },
f75eb1c0 15464 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
49f58d10
JB		 15465 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e900 }
15466 },
f75eb1c0 15467/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
49f58d10
JB		 15468 {
15469 { 0, 0, 0, 0 },
f75eb1c0 15470 { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 15471 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68900 }
15472 },
f75eb1c0 15473/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
49f58d10
JB		 15474 {
15475 { 0, 0, 0, 0 },
f75eb1c0 15476 { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
49f58d10
JB		 15477 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a900 }
15478 },
f75eb1c0 15479/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
49f58d10
JB		 15480 {
15481 { 0, 0, 0, 0 },
f75eb1c0 15482 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15483 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c809 }
15484 },
f75eb1c0 15485/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
49f58d10
JB		 15486 {
15487 { 0, 0, 0, 0 },
f75eb1c0 15488 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15489 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18829 }
15490 },
f75eb1c0 15491/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 15492 {
15493 { 0, 0, 0, 0 },
f75eb1c0 15494 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
49f58d10
JB		 15495 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18809 }
15496 },
f75eb1c0 15497/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
49f58d10
JB		 15498 {
15499 { 0, 0, 0, 0 },
f75eb1c0 15500 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15501 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c089 }
15502 },
f75eb1c0 15503/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
49f58d10
JB		 15504 {
15505 { 0, 0, 0, 0 },
f75eb1c0 15506 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15507 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a9 }
15508 },
f75eb1c0 15509/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 15510 {
15511 { 0, 0, 0, 0 },
f75eb1c0 15512 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
49f58d10
JB		 15513 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18089 }
15514 },
f75eb1c0 15515/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
49f58d10
JB		 15516 {
15517 { 0, 0, 0, 0 },
f75eb1c0 15518 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15519 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c009 }
15520 },
f75eb1c0 15521/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
49f58d10
JB		 15522 {
15523 { 0, 0, 0, 0 },
f75eb1c0 15524 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15525 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18029 }
15526 },
f75eb1c0 15527/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 15528 {
15529 { 0, 0, 0, 0 },
f75eb1c0 15530 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15531 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18009 }
15532 },
f75eb1c0 15533/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15534 {
15535 { 0, 0, 0, 0 },
f75eb1c0 15536 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15537 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20900 }
15538 },
f75eb1c0 15539/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15540 {
15541 { 0, 0, 0, 0 },
f75eb1c0 15542 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15543 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822900 }
15544 },
f75eb1c0 15545/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 15546 {
15547 { 0, 0, 0, 0 },
f75eb1c0 15548 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15549 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820900 }
15550 },
f75eb1c0 15551/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15552 {
15553 { 0, 0, 0, 0 },
f75eb1c0 15554 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15555 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40900 }
15556 },
f75eb1c0 15557/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15558 {
15559 { 0, 0, 0, 0 },
f75eb1c0 15560 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15561 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842900 }
15562 },
f75eb1c0 15563/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 15564 {
15565 { 0, 0, 0, 0 },
f75eb1c0 15566 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15567 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840900 }
15568 },
f75eb1c0 15569/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15570 {
15571 { 0, 0, 0, 0 },
f75eb1c0 15572 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15573 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60900 }
15574 },
f75eb1c0 15575/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15576 {
15577 { 0, 0, 0, 0 },
f75eb1c0 15578 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15579 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862900 }
15580 },
f75eb1c0 15581/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 15582 {
15583 { 0, 0, 0, 0 },
f75eb1c0 15584 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
49f58d10
JB		 15585 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860900 }
15586 },
f75eb1c0 15587/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
49f58d10
JB		 15588 {
15589 { 0, 0, 0, 0 },
f75eb1c0 15590 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15591 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28900 }
15592 },
f75eb1c0 15593/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
49f58d10
JB		 15594 {
15595 { 0, 0, 0, 0 },
f75eb1c0 15596 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15597 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a900 }
15598 },
f75eb1c0 15599/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
49f58d10
JB		 15600 {
15601 { 0, 0, 0, 0 },
f75eb1c0 15602 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15603 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828900 }
15604 },
f75eb1c0 15605/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
49f58d10
JB		 15606 {
15607 { 0, 0, 0, 0 },
f75eb1c0 15608 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15609 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48900 }
15610 },
f75eb1c0 15611/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
49f58d10
JB		 15612 {
15613 { 0, 0, 0, 0 },
f75eb1c0 15614 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15615 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a900 }
15616 },
f75eb1c0 15617/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
49f58d10
JB		 15618 {
15619 { 0, 0, 0, 0 },
f75eb1c0 15620 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 15621 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848900 }
15622 },
f75eb1c0 15623/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
49f58d10
JB		 15624 {
15625 { 0, 0, 0, 0 },
f75eb1c0 15626 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15627 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c900 }
15628 },
f75eb1c0 15629/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
49f58d10
JB		 15630 {
15631 { 0, 0, 0, 0 },
f75eb1c0 15632 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15633 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e900 }
15634 },
f75eb1c0 15635/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
49f58d10
JB		 15636 {
15637 { 0, 0, 0, 0 },
f75eb1c0 15638 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15639 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c900 }
15640 },
f75eb1c0 15641/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
49f58d10
JB		 15642 {
15643 { 0, 0, 0, 0 },
f75eb1c0 15644 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15645 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c900 }
15646 },
f75eb1c0 15647/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
49f58d10
JB		 15648 {
15649 { 0, 0, 0, 0 },
f75eb1c0 15650 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15651 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e900 }
15652 },
f75eb1c0 15653/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
49f58d10
JB		 15654 {
15655 { 0, 0, 0, 0 },
f75eb1c0 15656 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 15657 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c900 }
15658 },
f75eb1c0 15659/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
49f58d10
JB		 15660 {
15661 { 0, 0, 0, 0 },
f75eb1c0 15662 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 15663 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c900 }
15664 },
f75eb1c0 15665/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
49f58d10
JB		 15666 {
15667 { 0, 0, 0, 0 },
f75eb1c0 15668 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 15669 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e900 }
15670 },
f75eb1c0 15671/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
49f58d10
JB		 15672 {
15673 { 0, 0, 0, 0 },
f75eb1c0 15674 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
49f58d10
JB		 15675 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c900 }
15676 },
f75eb1c0 15677/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
49f58d10
JB		 15678 {
15679 { 0, 0, 0, 0 },
f75eb1c0 15680 { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 15681 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68900 }
15682 },
f75eb1c0 15683/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
49f58d10
JB		 15684 {
15685 { 0, 0, 0, 0 },
f75eb1c0 15686 { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 15687 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a900 }
15688 },
f75eb1c0 15689/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
49f58d10
JB		 15690 {
15691 { 0, 0, 0, 0 },
f75eb1c0 15692 { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
49f58d10
JB		 15693 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868900 }
15694 },
15695/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
15696 {
15697 { 0, 0, 0, 0 },
15698 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
15699 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x818000 }
15700 },
15701/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
15702 {
15703 { 0, 0, 0, 0 },
15704 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
15705 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x81a000 }
15706 },
15707/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
15708 {
15709 { 0, 0, 0, 0 },
15710 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
15711 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x81b000 }
15712 },
15713/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
15714 {
15715 { 0, 0, 0, 0 },
15716 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
15717 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x818400 }
15718 },
15719/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
15720 {
15721 { 0, 0, 0, 0 },
15722 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
15723 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x81a400 }
15724 },
15725/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
15726 {
15727 { 0, 0, 0, 0 },
15728 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
15729 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x81b400 }
15730 },
15731/* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
15732 {
15733 { 0, 0, 0, 0 },
15734 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
15735 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x818600 }
15736 },
15737/* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
15738 {
15739 { 0, 0, 0, 0 },
15740 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15741 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x81a600 }
15742 },
15743/* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
15744 {
15745 { 0, 0, 0, 0 },
15746 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15747 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x81b600 }
15748 },
15749/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
15750 {
15751 { 0, 0, 0, 0 },
15752 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15753 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x81880000 }
15754 },
15755/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
15756 {
15757 { 0, 0, 0, 0 },
15758 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15759 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x81a80000 }
15760 },
15761/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
15762 {
15763 { 0, 0, 0, 0 },
15764 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15765 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x81b80000 }
15766 },
15767/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
15768 {
15769 { 0, 0, 0, 0 },
15770 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15771 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x818c0000 }
15772 },
15773/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
15774 {
15775 { 0, 0, 0, 0 },
15776 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15777 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x81ac0000 }
15778 },
15779/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
15780 {
15781 { 0, 0, 0, 0 },
15782 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15783 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x81bc0000 }
15784 },
15785/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
15786 {
15787 { 0, 0, 0, 0 },
15788 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15789 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x818a0000 }
15790 },
15791/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
15792 {
15793 { 0, 0, 0, 0 },
15794 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15795 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81aa0000 }
15796 },
15797/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
15798 {
15799 { 0, 0, 0, 0 },
15800 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15801 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81ba0000 }
15802 },
15803/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
15804 {
15805 { 0, 0, 0, 0 },
15806 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15807 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x818e0000 }
15808 },
15809/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
15810 {
15811 { 0, 0, 0, 0 },
15812 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15813 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81ae0000 }
15814 },
15815/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
15816 {
15817 { 0, 0, 0, 0 },
15818 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15819 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81be0000 }
15820 },
15821/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
15822 {
15823 { 0, 0, 0, 0 },
15824 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15825 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x818b0000 }
15826 },
15827/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
15828 {
15829 { 0, 0, 0, 0 },
15830 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15831 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81ab0000 }
15832 },
15833/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
15834 {
15835 { 0, 0, 0, 0 },
15836 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15837 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81bb0000 }
15838 },
15839/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
15840 {
15841 { 0, 0, 0, 0 },
15842 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
15843 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x818f0000 }
15844 },
15845/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
15846 {
15847 { 0, 0, 0, 0 },
15848 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
15849 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x81af0000 }
15850 },
15851/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
15852 {
15853 { 0, 0, 0, 0 },
15854 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
15855 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x81bf0000 }
15856 },
15857/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
15858 {
15859 { 0, 0, 0, 0 },
15860 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
15861 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x81c00000 }
15862 },
15863/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
15864 {
15865 { 0, 0, 0, 0 },
15866 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
15867 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x81e00000 }
15868 },
15869/* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
15870 {
15871 { 0, 0, 0, 0 },
15872 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
15873 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x81f00000 }
15874 },
15875/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
15876 {
15877 { 0, 0, 0, 0 },
15878 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
15879 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x81c40000 }
15880 },
15881/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
15882 {
15883 { 0, 0, 0, 0 },
15884 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
15885 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x81e40000 }
15886 },
15887/* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
15888 {
15889 { 0, 0, 0, 0 },
15890 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
15891 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x81f40000 }
15892 },
15893/* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
15894 {
15895 { 0, 0, 0, 0 },
15896 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
15897 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x81c60000 }
15898 },
15899/* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
15900 {
15901 { 0, 0, 0, 0 },
15902 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15903 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x81e60000 }
15904 },
15905/* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
15906 {
15907 { 0, 0, 0, 0 },
15908 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
15909 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x81f60000 }
15910 },
15911/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
15912 {
15913 { 0, 0, 0, 0 },
15914 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15915 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x81c80000 }
15916 },
15917/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
15918 {
15919 { 0, 0, 0, 0 },
15920 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15921 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x81e80000 }
15922 },
15923/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
15924 {
15925 { 0, 0, 0, 0 },
15926 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15927 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x81f80000 }
15928 },
15929/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
15930 {
15931 { 0, 0, 0, 0 },
15932 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15933 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x81cc0000 }
15934 },
15935/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
15936 {
15937 { 0, 0, 0, 0 },
15938 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15939 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x81ec0000 }
15940 },
15941/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
15942 {
15943 { 0, 0, 0, 0 },
15944 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15945 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x81fc0000 }
15946 },
15947/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
15948 {
15949 { 0, 0, 0, 0 },
15950 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15951 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ca0000 }
15952 },
15953/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
15954 {
15955 { 0, 0, 0, 0 },
15956 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15957 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ea0000 }
15958 },
15959/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
15960 {
15961 { 0, 0, 0, 0 },
15962 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15963 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x81fa0000 }
15964 },
15965/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
15966 {
15967 { 0, 0, 0, 0 },
15968 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15969 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ce0000 }
15970 },
15971/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
15972 {
15973 { 0, 0, 0, 0 },
15974 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15975 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ee0000 }
15976 },
15977/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
15978 {
15979 { 0, 0, 0, 0 },
15980 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15981 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x81fe0000 }
15982 },
15983/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
15984 {
15985 { 0, 0, 0, 0 },
15986 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15987 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x81cb0000 }
15988 },
15989/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
15990 {
15991 { 0, 0, 0, 0 },
15992 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15993 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x81eb0000 }
15994 },
15995/* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
15996 {
15997 { 0, 0, 0, 0 },
15998 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15999 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x81fb0000 }
16000 },
16001/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
16002 {
16003 { 0, 0, 0, 0 },
16004 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
16005 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x81cf0000 }
16006 },
16007/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
16008 {
16009 { 0, 0, 0, 0 },
16010 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
16011 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x81ef0000 }
16012 },
16013/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
16014 {
16015 { 0, 0, 0, 0 },
16016 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
16017 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x81ff0000 }
16018 },
16019/* tst.w${X} $Src16RnHI,$Dst16RnHI */
16020 {
16021 { 0, 0, 0, 0 },
16022 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
16023 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8100 }
16024 },
16025/* tst.w${X} $Src16AnHI,$Dst16RnHI */
16026 {
16027 { 0, 0, 0, 0 },
16028 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
16029 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8140 }
16030 },
16031/* tst.w${X} [$Src16An],$Dst16RnHI */
16032 {
16033 { 0, 0, 0, 0 },
16034 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
16035 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8160 }
16036 },
16037/* tst.w${X} $Src16RnHI,$Dst16AnHI */
16038 {
16039 { 0, 0, 0, 0 },
16040 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
16041 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8104 }
16042 },
16043/* tst.w${X} $Src16AnHI,$Dst16AnHI */
16044 {
16045 { 0, 0, 0, 0 },
16046 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
16047 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8144 }
16048 },
16049/* tst.w${X} [$Src16An],$Dst16AnHI */
16050 {
16051 { 0, 0, 0, 0 },
16052 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
16053 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8164 }
16054 },
16055/* tst.w${X} $Src16RnHI,[$Dst16An] */
16056 {
16057 { 0, 0, 0, 0 },
16058 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
16059 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8106 }
16060 },
16061/* tst.w${X} $Src16AnHI,[$Dst16An] */
16062 {
16063 { 0, 0, 0, 0 },
16064 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
16065 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8146 }
16066 },
16067/* tst.w${X} [$Src16An],[$Dst16An] */
16068 {
16069 { 0, 0, 0, 0 },
16070 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16071 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8166 }
16072 },
16073/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
16074 {
16075 { 0, 0, 0, 0 },
16076 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16077 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x810800 }
16078 },
16079/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
16080 {
16081 { 0, 0, 0, 0 },
16082 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16083 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x814800 }
16084 },
16085/* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
16086 {
16087 { 0, 0, 0, 0 },
16088 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16089 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x816800 }
16090 },
16091/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
16092 {
16093 { 0, 0, 0, 0 },
16094 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16095 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x810c0000 }
16096 },
16097/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
16098 {
16099 { 0, 0, 0, 0 },
16100 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16101 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x814c0000 }
16102 },
16103/* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
16104 {
16105 { 0, 0, 0, 0 },
16106 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16107 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x816c0000 }
16108 },
16109/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
16110 {
16111 { 0, 0, 0, 0 },
16112 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16113 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x810a00 }
16114 },
16115/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
16116 {
16117 { 0, 0, 0, 0 },
16118 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16119 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x814a00 }
16120 },
16121/* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
16122 {
16123 { 0, 0, 0, 0 },
16124 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16125 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x816a00 }
16126 },
16127/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
16128 {
16129 { 0, 0, 0, 0 },
16130 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16131 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x810e0000 }
16132 },
16133/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
16134 {
16135 { 0, 0, 0, 0 },
16136 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16137 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x814e0000 }
16138 },
16139/* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
16140 {
16141 { 0, 0, 0, 0 },
16142 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16143 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x816e0000 }
16144 },
16145/* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
16146 {
16147 { 0, 0, 0, 0 },
16148 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16149 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x810b00 }
16150 },
16151/* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
16152 {
16153 { 0, 0, 0, 0 },
16154 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16155 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x814b00 }
16156 },
16157/* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
16158 {
16159 { 0, 0, 0, 0 },
16160 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16161 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x816b00 }
16162 },
16163/* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
16164 {
16165 { 0, 0, 0, 0 },
16166 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
16167 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x810f0000 }
16168 },
16169/* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
16170 {
16171 { 0, 0, 0, 0 },
16172 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
16173 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x814f0000 }
16174 },
16175/* tst.w${X} [$Src16An],${Dsp-16-u16} */
16176 {
16177 { 0, 0, 0, 0 },
16178 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
16179 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x816f0000 }
16180 },
16181/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
16182 {
16183 { 0, 0, 0, 0 },
16184 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16185 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x808000 }
16186 },
16187/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
16188 {
16189 { 0, 0, 0, 0 },
16190 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
16191 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x80a000 }
16192 },
16193/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
16194 {
16195 { 0, 0, 0, 0 },
16196 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
16197 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x80b000 }
16198 },
16199/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
16200 {
16201 { 0, 0, 0, 0 },
16202 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16203 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x808400 }
16204 },
16205/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
16206 {
16207 { 0, 0, 0, 0 },
16208 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
16209 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x80a400 }
16210 },
16211/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
16212 {
16213 { 0, 0, 0, 0 },
16214 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
16215 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x80b400 }
16216 },
16217/* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
16218 {
16219 { 0, 0, 0, 0 },
16220 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16221 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x808600 }
16222 },
16223/* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
16224 {
16225 { 0, 0, 0, 0 },
16226 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16227 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x80a600 }
16228 },
16229/* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
16230 {
16231 { 0, 0, 0, 0 },
16232 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16233 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x80b600 }
16234 },
16235/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
16236 {
16237 { 0, 0, 0, 0 },
16238 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16239 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x80880000 }
16240 },
16241/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
16242 {
16243 { 0, 0, 0, 0 },
16244 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16245 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x80a80000 }
16246 },
16247/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
16248 {
16249 { 0, 0, 0, 0 },
16250 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16251 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x80b80000 }
16252 },
16253/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
16254 {
16255 { 0, 0, 0, 0 },
16256 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16257 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x808c0000 }
16258 },
16259/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
16260 {
16261 { 0, 0, 0, 0 },
16262 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16263 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x80ac0000 }
16264 },
16265/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
16266 {
16267 { 0, 0, 0, 0 },
16268 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16269 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x80bc0000 }
16270 },
16271/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
16272 {
16273 { 0, 0, 0, 0 },
16274 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16275 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x808a0000 }
16276 },
16277/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16278 {
16279 { 0, 0, 0, 0 },
16280 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16281 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80aa0000 }
16282 },
16283/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16284 {
16285 { 0, 0, 0, 0 },
16286 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16287 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80ba0000 }
16288 },
16289/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
16290 {
16291 { 0, 0, 0, 0 },
16292 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16293 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x808e0000 }
16294 },
16295/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16296 {
16297 { 0, 0, 0, 0 },
16298 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16299 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80ae0000 }
16300 },
16301/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16302 {
16303 { 0, 0, 0, 0 },
16304 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16305 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80be0000 }
16306 },
16307/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
16308 {
16309 { 0, 0, 0, 0 },
16310 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16311 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x808b0000 }
16312 },
16313/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16314 {
16315 { 0, 0, 0, 0 },
16316 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16317 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80ab0000 }
16318 },
16319/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16320 {
16321 { 0, 0, 0, 0 },
16322 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16323 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80bb0000 }
16324 },
16325/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
16326 {
16327 { 0, 0, 0, 0 },
16328 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
16329 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x808f0000 }
16330 },
16331/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16332 {
16333 { 0, 0, 0, 0 },
16334 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16335 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x80af0000 }
16336 },
16337/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16338 {
16339 { 0, 0, 0, 0 },
16340 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16341 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x80bf0000 }
16342 },
16343/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
16344 {
16345 { 0, 0, 0, 0 },
16346 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16347 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x80c00000 }
16348 },
16349/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
16350 {
16351 { 0, 0, 0, 0 },
16352 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
16353 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x80e00000 }
16354 },
16355/* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
16356 {
16357 { 0, 0, 0, 0 },
16358 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
16359 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x80f00000 }
16360 },
16361/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
16362 {
16363 { 0, 0, 0, 0 },
16364 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16365 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x80c40000 }
16366 },
16367/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
16368 {
16369 { 0, 0, 0, 0 },
16370 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
16371 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x80e40000 }
16372 },
16373/* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
16374 {
16375 { 0, 0, 0, 0 },
16376 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
16377 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x80f40000 }
16378 },
16379/* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
16380 {
16381 { 0, 0, 0, 0 },
16382 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16383 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x80c60000 }
16384 },
16385/* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
16386 {
16387 { 0, 0, 0, 0 },
16388 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16389 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x80e60000 }
16390 },
16391/* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
16392 {
16393 { 0, 0, 0, 0 },
16394 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
16395 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x80f60000 }
16396 },
16397/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
16398 {
16399 { 0, 0, 0, 0 },
16400 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16401 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x80c80000 }
16402 },
16403/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
16404 {
16405 { 0, 0, 0, 0 },
16406 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16407 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x80e80000 }
16408 },
16409/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
16410 {
16411 { 0, 0, 0, 0 },
16412 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16413 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x80f80000 }
16414 },
16415/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
16416 {
16417 { 0, 0, 0, 0 },
16418 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16419 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x80cc0000 }
16420 },
16421/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
16422 {
16423 { 0, 0, 0, 0 },
16424 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16425 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x80ec0000 }
16426 },
16427/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
16428 {
16429 { 0, 0, 0, 0 },
16430 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16431 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x80fc0000 }
16432 },
16433/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
16434 {
16435 { 0, 0, 0, 0 },
16436 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16437 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ca0000 }
16438 },
16439/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
16440 {
16441 { 0, 0, 0, 0 },
16442 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16443 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ea0000 }
16444 },
16445/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
16446 {
16447 { 0, 0, 0, 0 },
16448 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16449 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x80fa0000 }
16450 },
16451/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
16452 {
16453 { 0, 0, 0, 0 },
16454 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16455 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ce0000 }
16456 },
16457/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
16458 {
16459 { 0, 0, 0, 0 },
16460 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16461 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ee0000 }
16462 },
16463/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
16464 {
16465 { 0, 0, 0, 0 },
16466 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16467 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x80fe0000 }
16468 },
16469/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
16470 {
16471 { 0, 0, 0, 0 },
16472 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16473 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x80cb0000 }
16474 },
16475/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
16476 {
16477 { 0, 0, 0, 0 },
16478 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16479 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x80eb0000 }
16480 },
16481/* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
16482 {
16483 { 0, 0, 0, 0 },
16484 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16485 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x80fb0000 }
16486 },
16487/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
16488 {
16489 { 0, 0, 0, 0 },
16490 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
16491 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x80cf0000 }
16492 },
16493/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
16494 {
16495 { 0, 0, 0, 0 },
16496 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
16497 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x80ef0000 }
16498 },
16499/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
16500 {
16501 { 0, 0, 0, 0 },
16502 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
16503 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x80ff0000 }
16504 },
16505/* tst.b${X} $Src16RnQI,$Dst16RnQI */
16506 {
16507 { 0, 0, 0, 0 },
16508 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
16509 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8000 }
16510 },
16511/* tst.b${X} $Src16AnQI,$Dst16RnQI */
16512 {
16513 { 0, 0, 0, 0 },
16514 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
16515 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8040 }
16516 },
16517/* tst.b${X} [$Src16An],$Dst16RnQI */
16518 {
16519 { 0, 0, 0, 0 },
16520 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16521 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8060 }
16522 },
16523/* tst.b${X} $Src16RnQI,$Dst16AnQI */
16524 {
16525 { 0, 0, 0, 0 },
16526 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
16527 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8004 }
16528 },
16529/* tst.b${X} $Src16AnQI,$Dst16AnQI */
16530 {
16531 { 0, 0, 0, 0 },
16532 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
16533 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8044 }
16534 },
16535/* tst.b${X} [$Src16An],$Dst16AnQI */
16536 {
16537 { 0, 0, 0, 0 },
16538 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16539 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8064 }
16540 },
16541/* tst.b${X} $Src16RnQI,[$Dst16An] */
16542 {
16543 { 0, 0, 0, 0 },
16544 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
16545 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8006 }
16546 },
16547/* tst.b${X} $Src16AnQI,[$Dst16An] */
16548 {
16549 { 0, 0, 0, 0 },
16550 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
16551 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8046 }
16552 },
16553/* tst.b${X} [$Src16An],[$Dst16An] */
16554 {
16555 { 0, 0, 0, 0 },
16556 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16557 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8066 }
16558 },
16559/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
16560 {
16561 { 0, 0, 0, 0 },
16562 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16563 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x800800 }
16564 },
16565/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
16566 {
16567 { 0, 0, 0, 0 },
16568 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16569 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x804800 }
16570 },
16571/* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
16572 {
16573 { 0, 0, 0, 0 },
16574 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16575 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x806800 }
16576 },
16577/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
16578 {
16579 { 0, 0, 0, 0 },
16580 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16581 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x800c0000 }
16582 },
16583/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
16584 {
16585 { 0, 0, 0, 0 },
16586 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16587 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x804c0000 }
16588 },
16589/* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
16590 {
16591 { 0, 0, 0, 0 },
16592 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16593 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x806c0000 }
16594 },
16595/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
16596 {
16597 { 0, 0, 0, 0 },
16598 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16599 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x800a00 }
16600 },
16601/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
16602 {
16603 { 0, 0, 0, 0 },
16604 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16605 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x804a00 }
16606 },
16607/* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
16608 {
16609 { 0, 0, 0, 0 },
16610 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16611 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x806a00 }
16612 },
16613/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
16614 {
16615 { 0, 0, 0, 0 },
16616 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16617 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x800e0000 }
16618 },
16619/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
16620 {
16621 { 0, 0, 0, 0 },
16622 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16623 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x804e0000 }
16624 },
16625/* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
16626 {
16627 { 0, 0, 0, 0 },
16628 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16629 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x806e0000 }
16630 },
16631/* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
16632 {
16633 { 0, 0, 0, 0 },
16634 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16635 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x800b00 }
16636 },
16637/* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
16638 {
16639 { 0, 0, 0, 0 },
16640 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16641 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x804b00 }
16642 },
16643/* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
16644 {
16645 { 0, 0, 0, 0 },
16646 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16647 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x806b00 }
16648 },
16649/* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
16650 {
16651 { 0, 0, 0, 0 },
16652 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
16653 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x800f0000 }
16654 },
16655/* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
16656 {
16657 { 0, 0, 0, 0 },
16658 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
16659 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x804f0000 }
16660 },
16661/* tst.b${X} [$Src16An],${Dsp-16-u16} */
16662 {
16663 { 0, 0, 0, 0 },
16664 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
16665 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x806f0000 }
16666 },
f75eb1c0 16667/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
49f58d10
JB		 16668 {
16669 { 0, 0, 0, 0 },
f75eb1c0 16670 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49f58d10
JB		 16671 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993e0000 }
16672 },
f75eb1c0 16673/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
49f58d10
JB		 16674 {
16675 { 0, 0, 0, 0 },
f75eb1c0 16676 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49f58d10
JB		 16677 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91be0000 }
16678 },
f75eb1c0 16679/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
49f58d10
JB		 16680 {
16681 { 0, 0, 0, 0 },
f75eb1c0 16682 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16683 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913e0000 }
16684 },
f75eb1c0 16685/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 16686 {
16687 { 0, 0, 0, 0 },
f75eb1c0 16688 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16689 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933e0000 }
16690 },
f75eb1c0 16691/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16692 {
16693 { 0, 0, 0, 0 },
f75eb1c0 16694 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16695 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93be0000 }
16696 },
f75eb1c0 16697/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16698 {
16699 { 0, 0, 0, 0 },
f75eb1c0 16700 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16701 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93fe0000 }
16702 },
f75eb1c0 16703/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 16704 {
16705 { 0, 0, 0, 0 },
f75eb1c0 16706 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16707 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953e0000 }
16708 },
f75eb1c0 16709/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16710 {
16711 { 0, 0, 0, 0 },
f75eb1c0 16712 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16713 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95be0000 }
16714 },
f75eb1c0 16715/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
49f58d10
JB		 16716 {
16717 { 0, 0, 0, 0 },
f75eb1c0 16718 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16719 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95fe0000 }
16720 },
f75eb1c0 16721/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
49f58d10
JB		 16722 {
16723 { 0, 0, 0, 0 },
f75eb1c0 16724 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16725 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97fe0000 }
16726 },
f75eb1c0 16727/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 16728 {
16729 { 0, 0, 0, 0 },
f75eb1c0 16730 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16731 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973e0000 }
16732 },
f75eb1c0 16733/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
49f58d10
JB		 16734 {
16735 { 0, 0, 0, 0 },
f75eb1c0 16736 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 16737 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97be0000 }
16738 },
f75eb1c0 16739/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
49f58d10
JB		 16740 {
16741 { 0, 0, 0, 0 },
f75eb1c0 16742 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49f58d10
JB		 16743 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983e00 }
16744 },
f75eb1c0 16745/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
49f58d10
JB		 16746 {
16747 { 0, 0, 0, 0 },
f75eb1c0 16748 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49f58d10
JB		 16749 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90be00 }
16750 },
f75eb1c0 16751/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
49f58d10
JB		 16752 {
16753 { 0, 0, 0, 0 },
f75eb1c0 16754 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16755 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903e00 }
16756 },
f75eb1c0 16757/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 16758 {
16759 { 0, 0, 0, 0 },
f75eb1c0 16760 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16761 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923e0000 }
16762 },
f75eb1c0 16763/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16764 {
16765 { 0, 0, 0, 0 },
f75eb1c0 16766 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16767 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92be0000 }
16768 },
f75eb1c0 16769/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16770 {
16771 { 0, 0, 0, 0 },
f75eb1c0 16772 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16773 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92fe0000 }
16774 },
f75eb1c0 16775/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 16776 {
16777 { 0, 0, 0, 0 },
f75eb1c0 16778 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16779 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943e0000 }
16780 },
f75eb1c0 16781/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16782 {
16783 { 0, 0, 0, 0 },
f75eb1c0 16784 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16785 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94be0000 }
16786 },
f75eb1c0 16787/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
49f58d10
JB		 16788 {
16789 { 0, 0, 0, 0 },
f75eb1c0 16790 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16791 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94fe0000 }
16792 },
f75eb1c0 16793/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 16794 {
16795 { 0, 0, 0, 0 },
f75eb1c0 16796 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16797 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96fe0000 }
16798 },
f75eb1c0 16799/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 16800 {
16801 { 0, 0, 0, 0 },
f75eb1c0 16802 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 16803 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963e0000 }
16804 },
f75eb1c0 16805/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
49f58d10
JB		 16806 {
16807 { 0, 0, 0, 0 },
f75eb1c0 16808 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 16809 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96be0000 }
16810 },
f75eb1c0 16811/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
49f58d10
JB		 16812 {
16813 { 0, 0, 0, 0 },
f75eb1c0 16814 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
49f58d10
JB		 16815 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77000000 }
16816 },
f75eb1c0 16817/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
49f58d10
JB		 16818 {
16819 { 0, 0, 0, 0 },
f75eb1c0 16820 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
49f58d10
JB		 16821 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77040000 }
16822 },
f75eb1c0 16823/* tst.w${G} #${Imm-16-HI},[$Dst16An] */
49f58d10
JB		 16824 {
16825 { 0, 0, 0, 0 },
f75eb1c0 16826 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16827 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77060000 }
16828 },
f75eb1c0 16829/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 16830 {
16831 { 0, 0, 0, 0 },
f75eb1c0 16832 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16833 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77080000 }
16834 },
f75eb1c0 16835/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16836 {
16837 { 0, 0, 0, 0 },
f75eb1c0 16838 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16839 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x770a0000 }
16840 },
f75eb1c0 16841/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16842 {
16843 { 0, 0, 0, 0 },
f75eb1c0 16844 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16845 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x770b0000 }
16846 },
f75eb1c0 16847/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 16848 {
16849 { 0, 0, 0, 0 },
f75eb1c0 16850 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16851 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x770c0000 }
16852 },
f75eb1c0 16853/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16854 {
16855 { 0, 0, 0, 0 },
f75eb1c0 16856 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16857 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x770e0000 }
16858 },
f75eb1c0 16859/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
49f58d10
JB		 16860 {
16861 { 0, 0, 0, 0 },
f75eb1c0 16862 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16863 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x770f0000 }
16864 },
f75eb1c0 16865/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
49f58d10
JB		 16866 {
16867 { 0, 0, 0, 0 },
f75eb1c0 16868 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
49f58d10
JB		 16869 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x760000 }
16870 },
f75eb1c0 16871/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
49f58d10
JB		 16872 {
16873 { 0, 0, 0, 0 },
f75eb1c0 16874 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
49f58d10
JB		 16875 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x760400 }
16876 },
f75eb1c0 16877/* tst.b${G} #${Imm-16-QI},[$Dst16An] */
49f58d10
JB		 16878 {
16879 { 0, 0, 0, 0 },
f75eb1c0 16880 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16881 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x760600 }
16882 },
f75eb1c0 16883/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 16884 {
16885 { 0, 0, 0, 0 },
f75eb1c0 16886 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16887 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76080000 }
16888 },
f75eb1c0 16889/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 16890 {
16891 { 0, 0, 0, 0 },
f75eb1c0 16892 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16893 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x760a0000 }
16894 },
f75eb1c0 16895/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 16896 {
16897 { 0, 0, 0, 0 },
f75eb1c0 16898 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 16899 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x760b0000 }
16900 },
f75eb1c0 16901/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 16902 {
16903 { 0, 0, 0, 0 },
f75eb1c0 16904 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 16905 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x760c0000 }
16906 },
f75eb1c0 16907/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
49f58d10
JB		 16908 {
16909 { 0, 0, 0, 0 },
f75eb1c0 16910 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 16911 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x760e0000 }
16912 },
f75eb1c0 16913/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 16914 {
16915 { 0, 0, 0, 0 },
f75eb1c0 16916 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 16917 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x760f0000 }
16918 },
16919/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
16920 {
16921 { 0, 0, 0, 0 },
16922 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16923 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980000 }
16924 },
16925/* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
16926 {
16927 { 0, 0, 0, 0 },
16928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16929 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982000 }
16930 },
16931/* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
16932 {
16933 { 0, 0, 0, 0 },
16934 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16935 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983000 }
16936 },
16937/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
16938 {
16939 { 0, 0, 0, 0 },
16940 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16941 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908000 }
16942 },
16943/* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
16944 {
16945 { 0, 0, 0, 0 },
16946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16947 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a000 }
16948 },
16949/* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
16950 {
16951 { 0, 0, 0, 0 },
16952 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16953 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b000 }
16954 },
16955/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16956 {
16957 { 0, 0, 0, 0 },
16958 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16959 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900000 }
16960 },
16961/* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16962 {
16963 { 0, 0, 0, 0 },
16964 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16965 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902000 }
16966 },
16967/* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16968 {
16969 { 0, 0, 0, 0 },
16970 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16971 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903000 }
16972 },
16973/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16974 {
16975 { 0, 0, 0, 0 },
16976 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16977 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92000000 }
16978 },
16979/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16980 {
16981 { 0, 0, 0, 0 },
16982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16983 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92200000 }
16984 },
16985/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16986 {
16987 { 0, 0, 0, 0 },
16988 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16989 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92300000 }
16990 },
16991/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16992 {
16993 { 0, 0, 0, 0 },
16994 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16995 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94000000 }
16996 },
16997/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16998 {
16999 { 0, 0, 0, 0 },
17000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17001 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94200000 }
17002 },
17003/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17004 {
17005 { 0, 0, 0, 0 },
17006 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17007 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94300000 }
17008 },
17009/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17010 {
17011 { 0, 0, 0, 0 },
17012 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17013 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96000000 }
17014 },
17015/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17016 {
17017 { 0, 0, 0, 0 },
17018 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17019 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96200000 }
17020 },
17021/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17022 {
17023 { 0, 0, 0, 0 },
17024 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17025 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96300000 }
17026 },
17027/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
17028 {
17029 { 0, 0, 0, 0 },
17030 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
17031 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92800000 }
17032 },
17033/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
17034 {
17035 { 0, 0, 0, 0 },
17036 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
17037 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a00000 }
17038 },
17039/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
17040 {
17041 { 0, 0, 0, 0 },
17042 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
17043 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b00000 }
17044 },
17045/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
17046 {
17047 { 0, 0, 0, 0 },
17048 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
17049 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94800000 }
17050 },
17051/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
17052 {
17053 { 0, 0, 0, 0 },
17054 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
17055 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a00000 }
17056 },
17057/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
17058 {
17059 { 0, 0, 0, 0 },
17060 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
17061 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b00000 }
17062 },
17063/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
17064 {
17065 { 0, 0, 0, 0 },
17066 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
17067 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c00000 }
17068 },
17069/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
17070 {
17071 { 0, 0, 0, 0 },
17072 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
17073 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e00000 }
17074 },
17075/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
17076 {
17077 { 0, 0, 0, 0 },
17078 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
17079 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f00000 }
17080 },
17081/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
17082 {
17083 { 0, 0, 0, 0 },
17084 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
17085 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c00000 }
17086 },
17087/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
17088 {
17089 { 0, 0, 0, 0 },
17090 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
17091 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e00000 }
17092 },
17093/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
17094 {
17095 { 0, 0, 0, 0 },
17096 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
17097 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f00000 }
17098 },
17099/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
17100 {
17101 { 0, 0, 0, 0 },
17102 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
17103 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c00000 }
17104 },
17105/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
17106 {
17107 { 0, 0, 0, 0 },
17108 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
17109 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e00000 }
17110 },
17111/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
17112 {
17113 { 0, 0, 0, 0 },
17114 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
17115 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f00000 }
17116 },
17117/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
17118 {
17119 { 0, 0, 0, 0 },
17120 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
17121 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96800000 }
17122 },
17123/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
17124 {
17125 { 0, 0, 0, 0 },
17126 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
17127 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a00000 }
17128 },
17129/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
17130 {
17131 { 0, 0, 0, 0 },
17132 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
17133 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b00000 }
17134 },
17135/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17136 {
17137 { 0, 0, 0, 0 },
17138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17139 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8000000 }
17140 },
17141/* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
17142 {
17143 { 0, 0, 0, 0 },
17144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17145 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8200000 }
17146 },
17147/* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
17148 {
17149 { 0, 0, 0, 0 },
17150 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17151 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8300000 }
17152 },
17153/* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
17154 {
17155 { 0, 0, 0, 0 },
17156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17157 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8300000 }
17158 },
17159/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17160 {
17161 { 0, 0, 0, 0 },
17162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17163 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0800000 }
17164 },
17165/* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
17166 {
17167 { 0, 0, 0, 0 },
17168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17169 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a00000 }
17170 },
17171/* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
17172 {
17173 { 0, 0, 0, 0 },
17174 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17175 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b00000 }
17176 },
17177/* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
17178 {
17179 { 0, 0, 0, 0 },
17180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17181 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b00000 }
17182 },
17183/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17184 {
17185 { 0, 0, 0, 0 },
17186 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17187 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0000000 }
17188 },
17189/* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17190 {
17191 { 0, 0, 0, 0 },
17192 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17193 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0200000 }
17194 },
17195/* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17196 {
17197 { 0, 0, 0, 0 },
17198 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17199 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0300000 }
17200 },
17201/* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17202 {
17203 { 0, 0, 0, 0 },
17204 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17205 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0300000 }
17206 },
17207/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17208 {
17209 { 0, 0, 0, 0 },
17210 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17211 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2000000 }
17212 },
17213/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17214 {
17215 { 0, 0, 0, 0 },
17216 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17217 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2200000 }
17218 },
17219/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17220 {
17221 { 0, 0, 0, 0 },
17222 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17223 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2300000 }
17224 },
17225/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17226 {
17227 { 0, 0, 0, 0 },
17228 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17229 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2300000 }
17230 },
17231/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17232 {
17233 { 0, 0, 0, 0 },
17234 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17235 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4000000 }
17236 },
17237/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17238 {
17239 { 0, 0, 0, 0 },
17240 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17241 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4200000 }
17242 },
17243/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17244 {
17245 { 0, 0, 0, 0 },
17246 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17247 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4300000 }
17248 },
17249/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17250 {
17251 { 0, 0, 0, 0 },
17252 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17253 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4300000 }
17254 },
17255/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17256 {
17257 { 0, 0, 0, 0 },
17258 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17259 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6000000 }
17260 },
17261/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17262 {
17263 { 0, 0, 0, 0 },
17264 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17265 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6200000 }
17266 },
17267/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17268 {
17269 { 0, 0, 0, 0 },
17270 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17271 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6300000 }
17272 },
17273/* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17274 {
17275 { 0, 0, 0, 0 },
17276 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17277 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6300000 }
17278 },
17279/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17280 {
17281 { 0, 0, 0, 0 },
17282 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17283 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2800000 }
17284 },
17285/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17286 {
17287 { 0, 0, 0, 0 },
17288 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17289 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a00000 }
17290 },
17291/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17292 {
17293 { 0, 0, 0, 0 },
17294 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17295 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b00000 }
17296 },
17297/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17298 {
17299 { 0, 0, 0, 0 },
17300 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17301 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b00000 }
17302 },
17303/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17304 {
17305 { 0, 0, 0, 0 },
17306 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17307 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4800000 }
17308 },
17309/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17310 {
17311 { 0, 0, 0, 0 },
17312 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17313 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a00000 }
17314 },
17315/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17316 {
17317 { 0, 0, 0, 0 },
17318 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17319 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b00000 }
17320 },
17321/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17322 {
17323 { 0, 0, 0, 0 },
17324 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17325 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b00000 }
17326 },
17327/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17328 {
17329 { 0, 0, 0, 0 },
17330 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17331 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c00000 }
17332 },
17333/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17334 {
17335 { 0, 0, 0, 0 },
17336 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17337 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e00000 }
17338 },
17339/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17340 {
17341 { 0, 0, 0, 0 },
17342 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17343 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f00000 }
17344 },
17345/* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17346 {
17347 { 0, 0, 0, 0 },
17348 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17349 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f00000 }
17350 },
17351/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17352 {
17353 { 0, 0, 0, 0 },
17354 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17355 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c00000 }
17356 },
17357/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17358 {
17359 { 0, 0, 0, 0 },
17360 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17361 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e00000 }
17362 },
17363/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17364 {
17365 { 0, 0, 0, 0 },
17366 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17367 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f00000 }
17368 },
17369/* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17370 {
17371 { 0, 0, 0, 0 },
17372 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17373 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f00000 }
17374 },
17375/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17376 {
17377 { 0, 0, 0, 0 },
17378 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
17379 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c00000 }
17380 },
17381/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17382 {
17383 { 0, 0, 0, 0 },
17384 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
17385 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e00000 }
17386 },
17387/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17388 {
17389 { 0, 0, 0, 0 },
17390 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
17391 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f00000 }
17392 },
17393/* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
17394 {
17395 { 0, 0, 0, 0 },
17396 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
17397 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f00000 }
17398 },
17399/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17400 {
17401 { 0, 0, 0, 0 },
17402 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
17403 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6800000 }
17404 },
17405/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17406 {
17407 { 0, 0, 0, 0 },
17408 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
17409 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a00000 }
17410 },
17411/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17412 {
17413 { 0, 0, 0, 0 },
17414 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
17415 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b00000 }
17416 },
17417/* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
17418 {
17419 { 0, 0, 0, 0 },
17420 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
17421 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b00000 }
17422 },
17423/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17424 {
17425 { 0, 0, 0, 0 },
17426 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17427 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8000000 }
17428 },
17429/* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
17430 {
17431 { 0, 0, 0, 0 },
17432 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17433 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8200000 }
17434 },
17435/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17436 {
17437 { 0, 0, 0, 0 },
17438 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17439 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0800000 }
17440 },
17441/* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
17442 {
17443 { 0, 0, 0, 0 },
17444 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17445 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a00000 }
17446 },
17447/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17448 {
17449 { 0, 0, 0, 0 },
17450 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17451 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0000000 }
17452 },
17453/* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17454 {
17455 { 0, 0, 0, 0 },
17456 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17457 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0200000 }
17458 },
17459/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17460 {
17461 { 0, 0, 0, 0 },
17462 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17463 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2000000 }
17464 },
17465/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17466 {
17467 { 0, 0, 0, 0 },
17468 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17469 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2200000 }
17470 },
17471/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17472 {
17473 { 0, 0, 0, 0 },
17474 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17475 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4000000 }
17476 },
17477/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17478 {
17479 { 0, 0, 0, 0 },
17480 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17481 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4200000 }
17482 },
17483/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17484 {
17485 { 0, 0, 0, 0 },
17486 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17487 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6000000 }
17488 },
17489/* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17490 {
17491 { 0, 0, 0, 0 },
17492 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17493 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6200000 }
17494 },
17495/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17496 {
17497 { 0, 0, 0, 0 },
17498 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
17499 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2800000 }
17500 },
17501/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17502 {
17503 { 0, 0, 0, 0 },
17504 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
17505 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a00000 }
17506 },
17507/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17508 {
17509 { 0, 0, 0, 0 },
17510 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
17511 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4800000 }
17512 },
17513/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17514 {
17515 { 0, 0, 0, 0 },
17516 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
17517 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a00000 }
17518 },
17519/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17520 {
17521 { 0, 0, 0, 0 },
17522 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
17523 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c00000 }
17524 },
17525/* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17526 {
17527 { 0, 0, 0, 0 },
17528 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
17529 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e00000 }
17530 },
17531/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17532 {
17533 { 0, 0, 0, 0 },
17534 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
17535 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c00000 }
17536 },
17537/* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17538 {
17539 { 0, 0, 0, 0 },
17540 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
17541 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e00000 }
17542 },
17543/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17544 {
17545 { 0, 0, 0, 0 },
17546 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
17547 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c00000 }
17548 },
17549/* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
17550 {
17551 { 0, 0, 0, 0 },
17552 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
17553 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e00000 }
17554 },
17555/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17556 {
17557 { 0, 0, 0, 0 },
17558 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
17559 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6800000 }
17560 },
17561/* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
17562 {
17563 { 0, 0, 0, 0 },
17564 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
17565 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a00000 }
17566 },
17567/* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
17568 {
17569 { 0, 0, 0, 0 },
17570 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17571 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc800 }
17572 },
17573/* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
17574 {
17575 { 0, 0, 0, 0 },
17576 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17577 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8820 }
17578 },
17579/* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17580 {
17581 { 0, 0, 0, 0 },
17582 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17583 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8800 }
17584 },
17585/* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
17586 {
17587 { 0, 0, 0, 0 },
17588 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17589 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc080 }
17590 },
17591/* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
17592 {
17593 { 0, 0, 0, 0 },
17594 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17595 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a0 }
17596 },
17597/* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17598 {
17599 { 0, 0, 0, 0 },
17600 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17601 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8080 }
17602 },
17603/* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
17604 {
17605 { 0, 0, 0, 0 },
17606 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17607 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc000 }
17608 },
17609/* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
17610 {
17611 { 0, 0, 0, 0 },
17612 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17613 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8020 }
17614 },
17615/* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17616 {
17617 { 0, 0, 0, 0 },
17618 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17619 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8000 }
17620 },
17621/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17622 {
17623 { 0, 0, 0, 0 },
17624 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17625 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20000 }
17626 },
17627/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17628 {
17629 { 0, 0, 0, 0 },
17630 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17631 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822000 }
17632 },
17633/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17634 {
17635 { 0, 0, 0, 0 },
17636 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17637 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820000 }
17638 },
17639/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17640 {
17641 { 0, 0, 0, 0 },
17642 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17643 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4000000 }
17644 },
17645/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17646 {
17647 { 0, 0, 0, 0 },
17648 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17649 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84200000 }
17650 },
17651/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17652 {
17653 { 0, 0, 0, 0 },
17654 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17655 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84000000 }
17656 },
17657/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17658 {
17659 { 0, 0, 0, 0 },
17660 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17661 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6000000 }
17662 },
17663/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17664 {
17665 { 0, 0, 0, 0 },
17666 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17667 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86200000 }
17668 },
17669/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17670 {
17671 { 0, 0, 0, 0 },
17672 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17673 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86000000 }
17674 },
17675/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
17676 {
17677 { 0, 0, 0, 0 },
17678 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17679 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28000 }
17680 },
17681/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
17682 {
17683 { 0, 0, 0, 0 },
17684 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17685 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a000 }
17686 },
17687/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17688 {
17689 { 0, 0, 0, 0 },
17690 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17691 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828000 }
17692 },
17693/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
17694 {
17695 { 0, 0, 0, 0 },
17696 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17697 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4800000 }
17698 },
17699/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
17700 {
17701 { 0, 0, 0, 0 },
17702 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17703 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a00000 }
17704 },
17705/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17706 {
17707 { 0, 0, 0, 0 },
17708 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17709 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84800000 }
17710 },
17711/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
17712 {
17713 { 0, 0, 0, 0 },
17714 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17715 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c000 }
17716 },
17717/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
17718 {
17719 { 0, 0, 0, 0 },
17720 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17721 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e000 }
17722 },
17723/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17724 {
17725 { 0, 0, 0, 0 },
17726 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17727 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c000 }
17728 },
17729/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
17730 {
17731 { 0, 0, 0, 0 },
17732 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17733 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c00000 }
17734 },
17735/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
17736 {
17737 { 0, 0, 0, 0 },
17738 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17739 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e00000 }
17740 },
17741/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17742 {
17743 { 0, 0, 0, 0 },
17744 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17745 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c00000 }
17746 },
17747/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
17748 {
17749 { 0, 0, 0, 0 },
17750 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
17751 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c00000 }
17752 },
17753/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
17754 {
17755 { 0, 0, 0, 0 },
17756 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
17757 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e00000 }
17758 },
17759/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17760 {
17761 { 0, 0, 0, 0 },
17762 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
17763 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c00000 }
17764 },
17765/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
17766 {
17767 { 0, 0, 0, 0 },
17768 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
17769 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6800000 }
17770 },
17771/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
17772 {
17773 { 0, 0, 0, 0 },
17774 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
17775 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a00000 }
17776 },
17777/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17778 {
17779 { 0, 0, 0, 0 },
17780 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
17781 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86800000 }
17782 },
17783/* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
17784 {
17785 { 0, 0, 0, 0 },
17786 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17787 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x981100 }
17788 },
17789/* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
17790 {
17791 { 0, 0, 0, 0 },
17792 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17793 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x909100 }
17794 },
17795/* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
17796 {
17797 { 0, 0, 0, 0 },
17798 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17799 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x901100 }
17800 },
17801/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17802 {
17803 { 0, 0, 0, 0 },
17804 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17805 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92110000 }
17806 },
17807/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
17808 {
17809 { 0, 0, 0, 0 },
17810 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17811 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92910000 }
17812 },
17813/* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
17814 {
17815 { 0, 0, 0, 0 },
17816 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17817 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92d10000 }
17818 },
17819/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17820 {
17821 { 0, 0, 0, 0 },
17822 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17823 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94110000 }
17824 },
17825/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
17826 {
17827 { 0, 0, 0, 0 },
17828 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17829 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94910000 }
17830 },
17831/* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
17832 {
17833 { 0, 0, 0, 0 },
17834 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17835 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94d10000 }
17836 },
17837/* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
17838 {
17839 { 0, 0, 0, 0 },
17840 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
17841 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96d10000 }
17842 },
17843/* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17844 {
17845 { 0, 0, 0, 0 },
17846 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17847 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96110000 }
17848 },
17849/* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
17850 {
17851 { 0, 0, 0, 0 },
17852 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
17853 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96910000 }
17854 },
17855/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
17856 {
17857 { 0, 0, 0, 0 },
17858 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
17859 & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993f0000 }
17860 },
17861/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
17862 {
17863 { 0, 0, 0, 0 },
17864 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
17865 & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91bf0000 }
17866 },
17867/* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
17868 {
17869 { 0, 0, 0, 0 },
17870 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17871 & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913f0000 }
17872 },
17873/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17874 {
17875 { 0, 0, 0, 0 },
17876 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17877 & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933f0000 }
17878 },
17879/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
17880 {
17881 { 0, 0, 0, 0 },
17882 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17883 & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93bf0000 }
17884 },
17885/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
17886 {
17887 { 0, 0, 0, 0 },
17888 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17889 & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ff0000 }
17890 },
17891/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17892 {
17893 { 0, 0, 0, 0 },
17894 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17895 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953f0000 }
17896 },
17897/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
17898 {
17899 { 0, 0, 0, 0 },
17900 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17901 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95bf0000 }
17902 },
17903/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
17904 {
17905 { 0, 0, 0, 0 },
17906 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17907 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ff0000 }
17908 },
17909/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
17910 {
17911 { 0, 0, 0, 0 },
17912 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), 0 } },
17913 & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ff0000 }
17914 },
17915/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17916 {
17917 { 0, 0, 0, 0 },
17918 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17919 & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973f0000 }
17920 },
17921/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
17922 {
17923 { 0, 0, 0, 0 },
17924 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), 0 } },
17925 & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97bf0000 }
17926 },
17927/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
17928 {
17929 { 0, 0, 0, 0 },
17930 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
17931 & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983f0000 }
17932 },
17933/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
17934 {
17935 { 0, 0, 0, 0 },
17936 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
17937 & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90bf0000 }
17938 },
17939/* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
17940 {
17941 { 0, 0, 0, 0 },
17942 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17943 & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903f0000 }
17944 },
17945/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17946 {
17947 { 0, 0, 0, 0 },
17948 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17949 & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923f0000 }
17950 },
17951/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
17952 {
17953 { 0, 0, 0, 0 },
17954 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17955 & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92bf0000 }
17956 },
17957/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
17958 {
17959 { 0, 0, 0, 0 },
17960 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17961 & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ff0000 }
17962 },
17963/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17964 {
17965 { 0, 0, 0, 0 },
17966 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17967 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943f0000 }
17968 },
17969/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
17970 {
17971 { 0, 0, 0, 0 },
17972 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17973 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94bf0000 }
17974 },
17975/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
17976 {
17977 { 0, 0, 0, 0 },
17978 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17979 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ff0000 }
17980 },
17981/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
17982 {
17983 { 0, 0, 0, 0 },
17984 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), 0 } },
17985 & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ff0000 }
17986 },
17987/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17988 {
17989 { 0, 0, 0, 0 },
17990 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17991 & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963f0000 }
17992 },
17993/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
17994 {
17995 { 0, 0, 0, 0 },
17996 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), 0 } },
17997 & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96bf0000 }
17998 },
17999/* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
18000 {
18001 { 0, 0, 0, 0 },
18002 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18003 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990f0000 }
18004 },
18005/* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
18006 {
18007 { 0, 0, 0, 0 },
18008 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18009 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918f0000 }
18010 },
18011/* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
18012 {
18013 { 0, 0, 0, 0 },
18014 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18015 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910f0000 }
18016 },
18017/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18018 {
18019 { 0, 0, 0, 0 },
18020 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18021 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930f0000 }
18022 },
18023/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
18024 {
18025 { 0, 0, 0, 0 },
18026 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18027 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938f0000 }
18028 },
18029/* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
18030 {
18031 { 0, 0, 0, 0 },
18032 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18033 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93cf0000 }
18034 },
18035/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18036 {
18037 { 0, 0, 0, 0 },
18038 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18039 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950f0000 }
18040 },
18041/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
18042 {
18043 { 0, 0, 0, 0 },
18044 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18045 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958f0000 }
18046 },
18047/* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
18048 {
18049 { 0, 0, 0, 0 },
18050 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18051 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95cf0000 }
18052 },
18053/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
18054 {
18055 { 0, 0, 0, 0 },
18056 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
18057 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97cf0000 }
18058 },
18059/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18060 {
18061 { 0, 0, 0, 0 },
18062 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18063 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970f0000 }
18064 },
18065/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
18066 {
18067 { 0, 0, 0, 0 },
18068 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
18069 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978f0000 }
18070 },
18071/* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
18072 {
18073 { 0, 0, 0, 0 },
18074 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18075 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980f00 }
18076 },
18077/* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
18078 {
18079 { 0, 0, 0, 0 },
18080 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18081 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908f00 }
18082 },
18083/* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18084 {
18085 { 0, 0, 0, 0 },
18086 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18087 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900f00 }
18088 },
18089/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18090 {
18091 { 0, 0, 0, 0 },
18092 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18093 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920f0000 }
18094 },
18095/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18096 {
18097 { 0, 0, 0, 0 },
18098 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18099 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928f0000 }
18100 },
18101/* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18102 {
18103 { 0, 0, 0, 0 },
18104 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18105 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92cf0000 }
18106 },
18107/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18108 {
18109 { 0, 0, 0, 0 },
18110 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18111 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940f0000 }
18112 },
18113/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18114 {
18115 { 0, 0, 0, 0 },
18116 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18117 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948f0000 }
18118 },
18119/* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18120 {
18121 { 0, 0, 0, 0 },
18122 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18123 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94cf0000 }
18124 },
18125/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
18126 {
18127 { 0, 0, 0, 0 },
18128 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18129 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96cf0000 }
18130 },
18131/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18132 {
18133 { 0, 0, 0, 0 },
18134 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18135 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960f0000 }
18136 },
18137/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
18138 {
18139 { 0, 0, 0, 0 },
18140 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18141 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968f0000 }
18142 },
18143/* stz${S} #${Imm-8-QI},r0l */
18144 {
18145 { 0, 0, 0, 0 },
18146 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
18147 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xcc00 }
18148 },
18149/* stz${S} #${Imm-8-QI},r0h */
18150 {
18151 { 0, 0, 0, 0 },
18152 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
18153 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xcb00 }
18154 },
18155/* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
18156 {
18157 { 0, 0, 0, 0 },
18158 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18159 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xcd0000 }
18160 },
18161/* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
18162 {
18163 { 0, 0, 0, 0 },
18164 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18165 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xce0000 }
18166 },
18167/* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
18168 {
18169 { 0, 0, 0, 0 },
18170 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
18171 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xcf000000 }
18172 },
18173/* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
18174 {
18175 { 0, 0, 0, 0 },
18176 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18177 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x991f0000 }
18178 },
18179/* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
18180 {
18181 { 0, 0, 0, 0 },
18182 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18183 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x919f0000 }
18184 },
18185/* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
18186 {
18187 { 0, 0, 0, 0 },
18188 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18189 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x911f0000 }
18190 },
18191/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18192 {
18193 { 0, 0, 0, 0 },
18194 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18195 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x931f0000 }
18196 },
18197/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
18198 {
18199 { 0, 0, 0, 0 },
18200 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18201 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939f0000 }
18202 },
18203/* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
18204 {
18205 { 0, 0, 0, 0 },
18206 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18207 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93df0000 }
18208 },
18209/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18210 {
18211 { 0, 0, 0, 0 },
18212 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18213 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x951f0000 }
18214 },
18215/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
18216 {
18217 { 0, 0, 0, 0 },
18218 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18219 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959f0000 }
18220 },
18221/* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
18222 {
18223 { 0, 0, 0, 0 },
18224 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18225 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95df0000 }
18226 },
18227/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
18228 {
18229 { 0, 0, 0, 0 },
18230 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
18231 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97df0000 }
18232 },
18233/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18234 {
18235 { 0, 0, 0, 0 },
18236 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18237 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x971f0000 }
18238 },
18239/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
18240 {
18241 { 0, 0, 0, 0 },
18242 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
18243 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x979f0000 }
18244 },
18245/* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
18246 {
18247 { 0, 0, 0, 0 },
18248 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18249 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x981f00 }
18250 },
18251/* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
18252 {
18253 { 0, 0, 0, 0 },
18254 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18255 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x909f00 }
18256 },
18257/* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18258 {
18259 { 0, 0, 0, 0 },
18260 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18261 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x901f00 }
18262 },
18263/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18264 {
18265 { 0, 0, 0, 0 },
18266 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18267 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x921f0000 }
18268 },
18269/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18270 {
18271 { 0, 0, 0, 0 },
18272 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18273 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929f0000 }
18274 },
18275/* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18276 {
18277 { 0, 0, 0, 0 },
18278 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18279 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92df0000 }
18280 },
18281/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18282 {
18283 { 0, 0, 0, 0 },
18284 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18285 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x941f0000 }
18286 },
18287/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18288 {
18289 { 0, 0, 0, 0 },
18290 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18291 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949f0000 }
18292 },
18293/* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18294 {
18295 { 0, 0, 0, 0 },
18296 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18297 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94df0000 }
18298 },
18299/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
18300 {
18301 { 0, 0, 0, 0 },
18302 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18303 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96df0000 }
18304 },
18305/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18306 {
18307 { 0, 0, 0, 0 },
18308 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18309 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x961f0000 }
18310 },
18311/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
18312 {
18313 { 0, 0, 0, 0 },
18314 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18315 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x969f0000 }
18316 },
18317/* stnz${S} #${Imm-8-QI},r0l */
18318 {
18319 { 0, 0, 0, 0 },
18320 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
18321 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xd400 }
18322 },
18323/* stnz${S} #${Imm-8-QI},r0h */
18324 {
18325 { 0, 0, 0, 0 },
18326 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
18327 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xd300 }
18328 },
18329/* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
18330 {
18331 { 0, 0, 0, 0 },
18332 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18333 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xd50000 }
18334 },
18335/* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
18336 {
18337 { 0, 0, 0, 0 },
18338 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18339 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xd60000 }
18340 },
18341/* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
18342 {
18343 { 0, 0, 0, 0 },
18344 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
18345 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xd7000000 }
18346 },
18347/* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
18348 {
18349 { 0, 0, 0, 0 },
18350 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18351 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x882100 }
18352 },
18353/* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
18354 {
18355 { 0, 0, 0, 0 },
18356 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18357 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80a100 }
18358 },
18359/* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18360 {
18361 { 0, 0, 0, 0 },
18362 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18363 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x802100 }
18364 },
18365/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18366 {
18367 { 0, 0, 0, 0 },
18368 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18369 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82210000 }
18370 },
18371/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18372 {
18373 { 0, 0, 0, 0 },
18374 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18375 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a10000 }
18376 },
18377/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18378 {
18379 { 0, 0, 0, 0 },
18380 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18381 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e10000 }
18382 },
18383/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18384 {
18385 { 0, 0, 0, 0 },
18386 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18387 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84210000 }
18388 },
18389/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18390 {
18391 { 0, 0, 0, 0 },
18392 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18393 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a10000 }
18394 },
18395/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18396 {
18397 { 0, 0, 0, 0 },
18398 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18399 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e10000 }
18400 },
18401/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
18402 {
18403 { 0, 0, 0, 0 },
18404 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18405 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86e10000 }
18406 },
18407/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18408 {
18409 { 0, 0, 0, 0 },
18410 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18411 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86210000 }
18412 },
18413/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
18414 {
18415 { 0, 0, 0, 0 },
18416 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18417 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86a10000 }
18418 },
18419/* shl.l r1h,$Dst32RnUnprefixedSI */
18420 {
18421 { 0, 0, 0, 0 },
18422 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18423 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc801 }
18424 },
18425/* shl.l r1h,$Dst32AnUnprefixedSI */
18426 {
18427 { 0, 0, 0, 0 },
18428 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18429 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc081 }
18430 },
18431/* shl.l r1h,[$Dst32AnUnprefixed] */
18432 {
18433 { 0, 0, 0, 0 },
18434 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18435 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc001 }
18436 },
18437/* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18438 {
18439 { 0, 0, 0, 0 },
18440 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18441 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20100 }
18442 },
18443/* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18444 {
18445 { 0, 0, 0, 0 },
18446 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18447 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4010000 }
18448 },
18449/* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18450 {
18451 { 0, 0, 0, 0 },
18452 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18453 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6010000 }
18454 },
18455/* shl.l r1h,${Dsp-16-u8}[sb] */
18456 {
18457 { 0, 0, 0, 0 },
18458 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18459 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28100 }
18460 },
18461/* shl.l r1h,${Dsp-16-u16}[sb] */
18462 {
18463 { 0, 0, 0, 0 },
18464 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18465 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4810000 }
18466 },
18467/* shl.l r1h,${Dsp-16-s8}[fb] */
18468 {
18469 { 0, 0, 0, 0 },
18470 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18471 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c100 }
18472 },
18473/* shl.l r1h,${Dsp-16-s16}[fb] */
18474 {
18475 { 0, 0, 0, 0 },
18476 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18477 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c10000 }
18478 },
18479/* shl.l r1h,${Dsp-16-u16} */
18480 {
18481 { 0, 0, 0, 0 },
18482 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18483 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c10000 }
18484 },
18485/* shl.l r1h,${Dsp-16-u24} */
18486 {
18487 { 0, 0, 0, 0 },
18488 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18489 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6810000 }
18490 },
18491/* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
18492 {
18493 { 0, 0, 0, 0 },
18494 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18495 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x982100 }
18496 },
18497/* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
18498 {
18499 { 0, 0, 0, 0 },
18500 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18501 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90a100 }
18502 },
18503/* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18504 {
18505 { 0, 0, 0, 0 },
18506 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18507 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x902100 }
18508 },
18509/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18510 {
18511 { 0, 0, 0, 0 },
18512 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18513 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92210000 }
18514 },
18515/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18516 {
18517 { 0, 0, 0, 0 },
18518 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18519 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92a10000 }
18520 },
18521/* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18522 {
18523 { 0, 0, 0, 0 },
18524 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18525 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92e10000 }
18526 },
18527/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18528 {
18529 { 0, 0, 0, 0 },
18530 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18531 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94210000 }
18532 },
18533/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18534 {
18535 { 0, 0, 0, 0 },
18536 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18537 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94a10000 }
18538 },
18539/* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18540 {
18541 { 0, 0, 0, 0 },
18542 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18543 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94e10000 }
18544 },
18545/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
18546 {
18547 { 0, 0, 0, 0 },
18548 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18549 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96e10000 }
18550 },
18551/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18552 {
18553 { 0, 0, 0, 0 },
18554 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18555 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96210000 }
18556 },
18557/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
18558 {
18559 { 0, 0, 0, 0 },
18560 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18561 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96a10000 }
18562 },
18563/* shl.w r1h,$Dst32RnUnprefixedHI */
18564 {
18565 { 0, 0, 0, 0 },
18566 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18567 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93e }
18568 },
18569/* shl.w r1h,$Dst32AnUnprefixedHI */
18570 {
18571 { 0, 0, 0, 0 },
18572 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18573 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1be }
18574 },
18575/* shl.w r1h,[$Dst32AnUnprefixed] */
18576 {
18577 { 0, 0, 0, 0 },
18578 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18579 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13e }
18580 },
18581/* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18582 {
18583 { 0, 0, 0, 0 },
18584 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18585 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33e00 }
18586 },
18587/* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18588 {
18589 { 0, 0, 0, 0 },
18590 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18591 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53e0000 }
18592 },
18593/* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18594 {
18595 { 0, 0, 0, 0 },
18596 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18597 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73e0000 }
18598 },
18599/* shl.w r1h,${Dsp-16-u8}[sb] */
18600 {
18601 { 0, 0, 0, 0 },
18602 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18603 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3be00 }
18604 },
18605/* shl.w r1h,${Dsp-16-u16}[sb] */
18606 {
18607 { 0, 0, 0, 0 },
18608 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18609 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5be0000 }
18610 },
18611/* shl.w r1h,${Dsp-16-s8}[fb] */
18612 {
18613 { 0, 0, 0, 0 },
18614 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18615 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3fe00 }
18616 },
18617/* shl.w r1h,${Dsp-16-s16}[fb] */
18618 {
18619 { 0, 0, 0, 0 },
18620 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18621 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5fe0000 }
18622 },
18623/* shl.w r1h,${Dsp-16-u16} */
18624 {
18625 { 0, 0, 0, 0 },
18626 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18627 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7fe0000 }
18628 },
18629/* shl.w r1h,${Dsp-16-u24} */
18630 {
18631 { 0, 0, 0, 0 },
18632 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18633 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7be0000 }
18634 },
18635/* shl.b r1h,$Dst32RnUnprefixedQI */
18636 {
18637 { 0, 0, 0, 0 },
18638 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18639 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83e }
18640 },
18641/* shl.b r1h,$Dst32AnUnprefixedQI */
18642 {
18643 { 0, 0, 0, 0 },
18644 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18645 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0be }
18646 },
18647/* shl.b r1h,[$Dst32AnUnprefixed] */
18648 {
18649 { 0, 0, 0, 0 },
18650 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18651 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03e }
18652 },
18653/* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18654 {
18655 { 0, 0, 0, 0 },
18656 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18657 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23e00 }
18658 },
18659/* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18660 {
18661 { 0, 0, 0, 0 },
18662 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18663 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43e0000 }
18664 },
18665/* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18666 {
18667 { 0, 0, 0, 0 },
18668 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18669 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63e0000 }
18670 },
18671/* shl.b r1h,${Dsp-16-u8}[sb] */
18672 {
18673 { 0, 0, 0, 0 },
18674 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18675 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2be00 }
18676 },
18677/* shl.b r1h,${Dsp-16-u16}[sb] */
18678 {
18679 { 0, 0, 0, 0 },
18680 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18681 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4be0000 }
18682 },
18683/* shl.b r1h,${Dsp-16-s8}[fb] */
18684 {
18685 { 0, 0, 0, 0 },
18686 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18687 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2fe00 }
18688 },
18689/* shl.b r1h,${Dsp-16-s16}[fb] */
18690 {
18691 { 0, 0, 0, 0 },
18692 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18693 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4fe0000 }
18694 },
18695/* shl.b r1h,${Dsp-16-u16} */
18696 {
18697 { 0, 0, 0, 0 },
18698 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18699 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6fe0000 }
18700 },
18701/* shl.b r1h,${Dsp-16-u24} */
18702 {
18703 { 0, 0, 0, 0 },
18704 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18705 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6be0000 }
18706 },
18707/* shl.w r1h,$Dst16RnHI */
18708 {
18709 { 0, 0, 0, 0 },
18710 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
18711 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75e0 }
18712 },
18713/* shl.w r1h,$Dst16AnHI */
18714 {
18715 { 0, 0, 0, 0 },
18716 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
18717 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75e4 }
18718 },
18719/* shl.w r1h,[$Dst16An] */
18720 {
18721 { 0, 0, 0, 0 },
18722 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
18723 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75e6 }
18724 },
18725/* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
18726 {
18727 { 0, 0, 0, 0 },
18728 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18729 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75e800 }
18730 },
18731/* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
18732 {
18733 { 0, 0, 0, 0 },
18734 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18735 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75ec0000 }
18736 },
18737/* shl.w r1h,${Dsp-16-u8}[sb] */
18738 {
18739 { 0, 0, 0, 0 },
18740 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18741 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75ea00 }
18742 },
18743/* shl.w r1h,${Dsp-16-u16}[sb] */
18744 {
18745 { 0, 0, 0, 0 },
18746 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18747 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75ee0000 }
18748 },
18749/* shl.w r1h,${Dsp-16-s8}[fb] */
18750 {
18751 { 0, 0, 0, 0 },
18752 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18753 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75eb00 }
18754 },
18755/* shl.w r1h,${Dsp-16-u16} */
18756 {
18757 { 0, 0, 0, 0 },
18758 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18759 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ef0000 }
18760 },
18761/* shl.b r1h,$Dst16RnQI */
18762 {
18763 { 0, 0, 0, 0 },
18764 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
18765 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74e0 }
18766 },
18767/* shl.b r1h,$Dst16AnQI */
18768 {
18769 { 0, 0, 0, 0 },
18770 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
18771 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74e4 }
18772 },
18773/* shl.b r1h,[$Dst16An] */
18774 {
18775 { 0, 0, 0, 0 },
18776 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
18777 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74e6 }
18778 },
18779/* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
18780 {
18781 { 0, 0, 0, 0 },
18782 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18783 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74e800 }
18784 },
18785/* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
18786 {
18787 { 0, 0, 0, 0 },
18788 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18789 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74ec0000 }
18790 },
18791/* shl.b r1h,${Dsp-16-u8}[sb] */
18792 {
18793 { 0, 0, 0, 0 },
18794 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18795 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74ea00 }
18796 },
18797/* shl.b r1h,${Dsp-16-u16}[sb] */
18798 {
18799 { 0, 0, 0, 0 },
18800 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18801 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74ee0000 }
18802 },
18803/* shl.b r1h,${Dsp-16-s8}[fb] */
18804 {
18805 { 0, 0, 0, 0 },
18806 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18807 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74eb00 }
18808 },
18809/* shl.b r1h,${Dsp-16-u16} */
18810 {
18811 { 0, 0, 0, 0 },
18812 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18813 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ef0000 }
18814 },
18815/* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
18816 {
18817 { 0, 0, 0, 0 },
18818 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18819 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe900 }
18820 },
18821/* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
18822 {
18823 { 0, 0, 0, 0 },
18824 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18825 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe180 }
18826 },
18827/* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
18828 {
18829 { 0, 0, 0, 0 },
18830 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18831 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe100 }
18832 },
18833/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18834 {
18835 { 0, 0, 0, 0 },
18836 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18837 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe30000 }
18838 },
18839/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18840 {
18841 { 0, 0, 0, 0 },
18842 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18843 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5000000 }
18844 },
18845/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18846 {
18847 { 0, 0, 0, 0 },
18848 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18849 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7000000 }
18850 },
18851/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
18852 {
18853 { 0, 0, 0, 0 },
18854 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18855 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe38000 }
18856 },
18857/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
18858 {
18859 { 0, 0, 0, 0 },
18860 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18861 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5800000 }
18862 },
18863/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
18864 {
18865 { 0, 0, 0, 0 },
18866 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18867 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3c000 }
18868 },
18869/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
18870 {
18871 { 0, 0, 0, 0 },
18872 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18873 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5c00000 }
18874 },
18875/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
18876 {
18877 { 0, 0, 0, 0 },
18878 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
18879 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7c00000 }
18880 },
18881/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
18882 {
18883 { 0, 0, 0, 0 },
18884 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
18885 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7800000 }
18886 },
18887/* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
18888 {
18889 { 0, 0, 0, 0 },
18890 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18891 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe800 }
18892 },
18893/* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
18894 {
18895 { 0, 0, 0, 0 },
18896 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18897 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe080 }
18898 },
18899/* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
18900 {
18901 { 0, 0, 0, 0 },
18902 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18903 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe000 }
18904 },
18905/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18906 {
18907 { 0, 0, 0, 0 },
18908 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18909 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe20000 }
18910 },
18911/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18912 {
18913 { 0, 0, 0, 0 },
18914 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18915 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4000000 }
18916 },
18917/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18918 {
18919 { 0, 0, 0, 0 },
18920 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18921 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6000000 }
18922 },
18923/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
18924 {
18925 { 0, 0, 0, 0 },
18926 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18927 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe28000 }
18928 },
18929/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
18930 {
18931 { 0, 0, 0, 0 },
18932 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18933 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4800000 }
18934 },
18935/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
18936 {
18937 { 0, 0, 0, 0 },
18938 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18939 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2c000 }
18940 },
18941/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
18942 {
18943 { 0, 0, 0, 0 },
18944 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18945 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4c00000 }
18946 },
18947/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
18948 {
18949 { 0, 0, 0, 0 },
18950 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
18951 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6c00000 }
18952 },
18953/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
18954 {
18955 { 0, 0, 0, 0 },
18956 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
18957 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6800000 }
18958 },
18959/* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
18960 {
18961 { 0, 0, 0, 0 },
18962 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
18963 & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe900 }
18964 },
18965/* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
18966 {
18967 { 0, 0, 0, 0 },
18968 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
18969 & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe904 }
18970 },
18971/* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
18972 {
18973 { 0, 0, 0, 0 },
18974 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
18975 & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe906 }
18976 },
18977/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
18978 {
18979 { 0, 0, 0, 0 },
18980 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18981 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe90800 }
18982 },
18983/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
18984 {
18985 { 0, 0, 0, 0 },
18986 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18987 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe90c0000 }
18988 },
18989/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
18990 {
18991 { 0, 0, 0, 0 },
18992 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18993 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe90a00 }
18994 },
18995/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
18996 {
18997 { 0, 0, 0, 0 },
18998 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18999 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe90e0000 }
19000 },
19001/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19002 {
19003 { 0, 0, 0, 0 },
19004 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19005 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe90b00 }
19006 },
19007/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19008 {
19009 { 0, 0, 0, 0 },
19010 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19011 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe90f0000 }
19012 },
19013/* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
19014 {
19015 { 0, 0, 0, 0 },
19016 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
19017 & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe800 }
19018 },
19019/* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
19020 {
19021 { 0, 0, 0, 0 },
19022 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
19023 & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe804 }
19024 },
19025/* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
19026 {
19027 { 0, 0, 0, 0 },
19028 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19029 & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe806 }
19030 },
19031/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19032 {
19033 { 0, 0, 0, 0 },
19034 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19035 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe80800 }
19036 },
19037/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19038 {
19039 { 0, 0, 0, 0 },
19040 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19041 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe80c0000 }
19042 },
19043/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19044 {
19045 { 0, 0, 0, 0 },
19046 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19047 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe80a00 }
19048 },
19049/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19050 {
19051 { 0, 0, 0, 0 },
19052 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19053 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe80e0000 }
19054 },
19055/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19056 {
19057 { 0, 0, 0, 0 },
19058 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19059 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe80b00 }
19060 },
19061/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19062 {
19063 { 0, 0, 0, 0 },
19064 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19065 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe80f0000 }
19066 },
19067/* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
19068 {
19069 { 0, 0, 0, 0 },
19070 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
19071 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xc82100 }
19072 },
19073/* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
19074 {
19075 { 0, 0, 0, 0 },
19076 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
19077 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xc0a100 }
19078 },
19079/* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19080 {
19081 { 0, 0, 0, 0 },
19082 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19083 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xc02100 }
19084 },
19085/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19086 {
19087 { 0, 0, 0, 0 },
19088 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19089 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xc2210000 }
19090 },
19091/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19092 {
19093 { 0, 0, 0, 0 },
19094 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19095 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc2a10000 }
19096 },
19097/* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19098 {
19099 { 0, 0, 0, 0 },
19100 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19101 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2e10000 }
19102 },
19103/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19104 {
19105 { 0, 0, 0, 0 },
19106 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19107 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4210000 }
19108 },
19109/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19110 {
19111 { 0, 0, 0, 0 },
19112 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19113 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4a10000 }
19114 },
19115/* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19116 {
19117 { 0, 0, 0, 0 },
19118 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19119 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4e10000 }
19120 },
19121/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
19122 {
19123 { 0, 0, 0, 0 },
19124 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
19125 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xc6e10000 }
19126 },
19127/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19128 {
19129 { 0, 0, 0, 0 },
19130 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19131 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6210000 }
19132 },
19133/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
19134 {
19135 { 0, 0, 0, 0 },
19136 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
19137 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xc6a10000 }
19138 },
19139/* sha.l r1h,$Dst32RnUnprefixedSI */
19140 {
19141 { 0, 0, 0, 0 },
19142 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
19143 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc811 }
19144 },
19145/* sha.l r1h,$Dst32AnUnprefixedSI */
19146 {
19147 { 0, 0, 0, 0 },
19148 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
19149 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc091 }
19150 },
19151/* sha.l r1h,[$Dst32AnUnprefixed] */
19152 {
19153 { 0, 0, 0, 0 },
19154 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19155 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc011 }
19156 },
19157/* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19158 {
19159 { 0, 0, 0, 0 },
19160 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19161 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc21100 }
19162 },
19163/* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19164 {
19165 { 0, 0, 0, 0 },
19166 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19167 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4110000 }
19168 },
19169/* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19170 {
19171 { 0, 0, 0, 0 },
19172 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19173 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6110000 }
19174 },
19175/* sha.l r1h,${Dsp-16-u8}[sb] */
19176 {
19177 { 0, 0, 0, 0 },
19178 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19179 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc29100 }
19180 },
19181/* sha.l r1h,${Dsp-16-u16}[sb] */
19182 {
19183 { 0, 0, 0, 0 },
19184 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19185 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4910000 }
19186 },
19187/* sha.l r1h,${Dsp-16-s8}[fb] */
19188 {
19189 { 0, 0, 0, 0 },
19190 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19191 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2d100 }
19192 },
19193/* sha.l r1h,${Dsp-16-s16}[fb] */
19194 {
19195 { 0, 0, 0, 0 },
19196 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19197 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4d10000 }
19198 },
19199/* sha.l r1h,${Dsp-16-u16} */
19200 {
19201 { 0, 0, 0, 0 },
19202 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19203 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6d10000 }
19204 },
19205/* sha.l r1h,${Dsp-16-u24} */
19206 {
19207 { 0, 0, 0, 0 },
19208 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19209 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6910000 }
19210 },
19211/* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
19212 {
19213 { 0, 0, 0, 0 },
19214 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
19215 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa82100 }
19216 },
19217/* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
19218 {
19219 { 0, 0, 0, 0 },
19220 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
19221 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0a100 }
19222 },
19223/* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19224 {
19225 { 0, 0, 0, 0 },
19226 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19227 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa02100 }
19228 },
19229/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19230 {
19231 { 0, 0, 0, 0 },
19232 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19233 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2210000 }
19234 },
19235/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19236 {
19237 { 0, 0, 0, 0 },
19238 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19239 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2a10000 }
19240 },
19241/* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19242 {
19243 { 0, 0, 0, 0 },
19244 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19245 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2e10000 }
19246 },
19247/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19248 {
19249 { 0, 0, 0, 0 },
19250 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19251 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4210000 }
19252 },
19253/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19254 {
19255 { 0, 0, 0, 0 },
19256 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19257 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4a10000 }
19258 },
19259/* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19260 {
19261 { 0, 0, 0, 0 },
19262 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19263 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4e10000 }
19264 },
19265/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
19266 {
19267 { 0, 0, 0, 0 },
19268 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
19269 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6e10000 }
19270 },
19271/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19272 {
19273 { 0, 0, 0, 0 },
19274 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19275 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6210000 }
19276 },
19277/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
19278 {
19279 { 0, 0, 0, 0 },
19280 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
19281 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6a10000 }
19282 },
19283/* sha.w r1h,$Dst32RnUnprefixedHI */
19284 {
19285 { 0, 0, 0, 0 },
19286 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
19287 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb93e }
19288 },
19289/* sha.w r1h,$Dst32AnUnprefixedHI */
19290 {
19291 { 0, 0, 0, 0 },
19292 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
19293 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1be }
19294 },
19295/* sha.w r1h,[$Dst32AnUnprefixed] */
19296 {
19297 { 0, 0, 0, 0 },
19298 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19299 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb13e }
19300 },
19301/* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19302 {
19303 { 0, 0, 0, 0 },
19304 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19305 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33e00 }
19306 },
19307/* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19308 {
19309 { 0, 0, 0, 0 },
19310 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19311 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb53e0000 }
19312 },
19313/* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19314 {
19315 { 0, 0, 0, 0 },
19316 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19317 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb73e0000 }
19318 },
19319/* sha.w r1h,${Dsp-16-u8}[sb] */
19320 {
19321 { 0, 0, 0, 0 },
19322 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19323 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3be00 }
19324 },
19325/* sha.w r1h,${Dsp-16-u16}[sb] */
19326 {
19327 { 0, 0, 0, 0 },
19328 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19329 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5be0000 }
19330 },
19331/* sha.w r1h,${Dsp-16-s8}[fb] */
19332 {
19333 { 0, 0, 0, 0 },
19334 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19335 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3fe00 }
19336 },
19337/* sha.w r1h,${Dsp-16-s16}[fb] */
19338 {
19339 { 0, 0, 0, 0 },
19340 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19341 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5fe0000 }
19342 },
19343/* sha.w r1h,${Dsp-16-u16} */
19344 {
19345 { 0, 0, 0, 0 },
19346 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19347 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7fe0000 }
19348 },
19349/* sha.w r1h,${Dsp-16-u24} */
19350 {
19351 { 0, 0, 0, 0 },
19352 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19353 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7be0000 }
19354 },
19355/* sha.b r1h,$Dst32RnUnprefixedQI */
19356 {
19357 { 0, 0, 0, 0 },
19358 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
19359 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb83e }
19360 },
19361/* sha.b r1h,$Dst32AnUnprefixedQI */
19362 {
19363 { 0, 0, 0, 0 },
19364 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
19365 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0be }
19366 },
19367/* sha.b r1h,[$Dst32AnUnprefixed] */
19368 {
19369 { 0, 0, 0, 0 },
19370 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19371 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb03e }
19372 },
19373/* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19374 {
19375 { 0, 0, 0, 0 },
19376 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19377 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb23e00 }
19378 },
19379/* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19380 {
19381 { 0, 0, 0, 0 },
19382 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19383 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb43e0000 }
19384 },
19385/* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19386 {
19387 { 0, 0, 0, 0 },
19388 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19389 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb63e0000 }
19390 },
19391/* sha.b r1h,${Dsp-16-u8}[sb] */
19392 {
19393 { 0, 0, 0, 0 },
19394 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19395 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2be00 }
19396 },
19397/* sha.b r1h,${Dsp-16-u16}[sb] */
19398 {
19399 { 0, 0, 0, 0 },
19400 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19401 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4be0000 }
19402 },
19403/* sha.b r1h,${Dsp-16-s8}[fb] */
19404 {
19405 { 0, 0, 0, 0 },
19406 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19407 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2fe00 }
19408 },
19409/* sha.b r1h,${Dsp-16-s16}[fb] */
19410 {
19411 { 0, 0, 0, 0 },
19412 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19413 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4fe0000 }
19414 },
19415/* sha.b r1h,${Dsp-16-u16} */
19416 {
19417 { 0, 0, 0, 0 },
19418 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19419 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6fe0000 }
19420 },
19421/* sha.b r1h,${Dsp-16-u24} */
19422 {
19423 { 0, 0, 0, 0 },
19424 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19425 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6be0000 }
19426 },
19427/* sha.w r1h,$Dst16RnHI */
19428 {
19429 { 0, 0, 0, 0 },
19430 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
19431 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75f0 }
19432 },
19433/* sha.w r1h,$Dst16AnHI */
19434 {
19435 { 0, 0, 0, 0 },
19436 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
19437 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75f4 }
19438 },
19439/* sha.w r1h,[$Dst16An] */
19440 {
19441 { 0, 0, 0, 0 },
19442 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
19443 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75f6 }
19444 },
19445/* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
19446 {
19447 { 0, 0, 0, 0 },
19448 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19449 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75f800 }
19450 },
19451/* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
19452 {
19453 { 0, 0, 0, 0 },
19454 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19455 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75fc0000 }
19456 },
19457/* sha.w r1h,${Dsp-16-u8}[sb] */
19458 {
19459 { 0, 0, 0, 0 },
19460 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19461 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75fa00 }
19462 },
19463/* sha.w r1h,${Dsp-16-u16}[sb] */
19464 {
19465 { 0, 0, 0, 0 },
19466 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19467 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75fe0000 }
19468 },
19469/* sha.w r1h,${Dsp-16-s8}[fb] */
19470 {
19471 { 0, 0, 0, 0 },
19472 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19473 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75fb00 }
19474 },
19475/* sha.w r1h,${Dsp-16-u16} */
19476 {
19477 { 0, 0, 0, 0 },
19478 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19479 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ff0000 }
19480 },
19481/* sha.b r1h,$Dst16RnQI */
19482 {
19483 { 0, 0, 0, 0 },
19484 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
19485 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74f0 }
19486 },
19487/* sha.b r1h,$Dst16AnQI */
19488 {
19489 { 0, 0, 0, 0 },
19490 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
19491 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74f4 }
19492 },
19493/* sha.b r1h,[$Dst16An] */
19494 {
19495 { 0, 0, 0, 0 },
19496 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
19497 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74f6 }
19498 },
19499/* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
19500 {
19501 { 0, 0, 0, 0 },
19502 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19503 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74f800 }
19504 },
19505/* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
19506 {
19507 { 0, 0, 0, 0 },
19508 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19509 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74fc0000 }
19510 },
19511/* sha.b r1h,${Dsp-16-u8}[sb] */
19512 {
19513 { 0, 0, 0, 0 },
19514 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19515 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74fa00 }
19516 },
19517/* sha.b r1h,${Dsp-16-u16}[sb] */
19518 {
19519 { 0, 0, 0, 0 },
19520 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19521 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74fe0000 }
19522 },
19523/* sha.b r1h,${Dsp-16-s8}[fb] */
19524 {
19525 { 0, 0, 0, 0 },
19526 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19527 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74fb00 }
19528 },
19529/* sha.b r1h,${Dsp-16-u16} */
19530 {
19531 { 0, 0, 0, 0 },
19532 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19533 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ff0000 }
19534 },
19535/* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
19536 {
19537 { 0, 0, 0, 0 },
19538 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
19539 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf900 }
19540 },
19541/* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
19542 {
19543 { 0, 0, 0, 0 },
19544 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
19545 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf180 }
19546 },
19547/* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
19548 {
19549 { 0, 0, 0, 0 },
19550 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19551 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf100 }
19552 },
19553/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19554 {
19555 { 0, 0, 0, 0 },
19556 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19557 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf30000 }
19558 },
19559/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19560 {
19561 { 0, 0, 0, 0 },
19562 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19563 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5000000 }
19564 },
19565/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19566 {
19567 { 0, 0, 0, 0 },
19568 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19569 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7000000 }
19570 },
19571/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
19572 {
19573 { 0, 0, 0, 0 },
19574 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19575 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf38000 }
19576 },
19577/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
19578 {
19579 { 0, 0, 0, 0 },
19580 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19581 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5800000 }
19582 },
19583/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
19584 {
19585 { 0, 0, 0, 0 },
19586 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19587 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3c000 }
19588 },
19589/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
19590 {
19591 { 0, 0, 0, 0 },
19592 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19593 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5c00000 }
19594 },
19595/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
19596 {
19597 { 0, 0, 0, 0 },
19598 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
19599 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7c00000 }
19600 },
19601/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
19602 {
19603 { 0, 0, 0, 0 },
19604 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
19605 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7800000 }
19606 },
19607/* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
19608 {
19609 { 0, 0, 0, 0 },
19610 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
19611 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf800 }
19612 },
19613/* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
19614 {
19615 { 0, 0, 0, 0 },
19616 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
19617 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf080 }
19618 },
19619/* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
19620 {
19621 { 0, 0, 0, 0 },
19622 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19623 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf000 }
19624 },
19625/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19626 {
19627 { 0, 0, 0, 0 },
19628 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19629 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf20000 }
19630 },
19631/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19632 {
19633 { 0, 0, 0, 0 },
19634 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19635 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4000000 }
19636 },
19637/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19638 {
19639 { 0, 0, 0, 0 },
19640 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19641 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6000000 }
19642 },
19643/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
19644 {
19645 { 0, 0, 0, 0 },
19646 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19647 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf28000 }
19648 },
19649/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
19650 {
19651 { 0, 0, 0, 0 },
19652 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19653 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4800000 }
19654 },
19655/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
19656 {
19657 { 0, 0, 0, 0 },
19658 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19659 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2c000 }
19660 },
19661/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
19662 {
19663 { 0, 0, 0, 0 },
19664 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19665 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4c00000 }
19666 },
19667/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
19668 {
19669 { 0, 0, 0, 0 },
19670 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
19671 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6c00000 }
19672 },
19673/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
19674 {
19675 { 0, 0, 0, 0 },
19676 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
19677 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6800000 }
19678 },
19679/* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
19680 {
19681 { 0, 0, 0, 0 },
19682 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
19683 & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xf100 }
19684 },
19685/* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
19686 {
19687 { 0, 0, 0, 0 },
19688 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
19689 & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xf104 }
19690 },
19691/* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
19692 {
19693 { 0, 0, 0, 0 },
19694 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19695 & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xf106 }
19696 },
19697/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19698 {
19699 { 0, 0, 0, 0 },
19700 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19701 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xf10800 }
19702 },
19703/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19704 {
19705 { 0, 0, 0, 0 },
19706 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19707 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xf10c0000 }
19708 },
19709/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19710 {
19711 { 0, 0, 0, 0 },
19712 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19713 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xf10a00 }
19714 },
19715/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19716 {
19717 { 0, 0, 0, 0 },
19718 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19719 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xf10e0000 }
19720 },
19721/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19722 {
19723 { 0, 0, 0, 0 },
19724 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19725 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xf10b00 }
19726 },
19727/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19728 {
19729 { 0, 0, 0, 0 },
19730 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19731 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xf10f0000 }
19732 },
19733/* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
19734 {
19735 { 0, 0, 0, 0 },
19736 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
19737 & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xf000 }
19738 },
19739/* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
19740 {
19741 { 0, 0, 0, 0 },
19742 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
19743 & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xf004 }
19744 },
19745/* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
19746 {
19747 { 0, 0, 0, 0 },
19748 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19749 & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xf006 }
19750 },
19751/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19752 {
19753 { 0, 0, 0, 0 },
19754 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19755 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xf00800 }
19756 },
19757/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19758 {
19759 { 0, 0, 0, 0 },
19760 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19761 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xf00c0000 }
19762 },
19763/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19764 {
19765 { 0, 0, 0, 0 },
19766 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19767 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xf00a00 }
19768 },
19769/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19770 {
19771 { 0, 0, 0, 0 },
19772 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19773 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xf00e0000 }
19774 },
19775/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19776 {
19777 { 0, 0, 0, 0 },
19778 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19779 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xf00b00 }
19780 },
19781/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19782 {
19783 { 0, 0, 0, 0 },
19784 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19785 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xf00f0000 }
19786 },
19787/* sc${sccond32} $Dst32RnUnprefixedHI */
19788 {
19789 { 0, 0, 0, 0 },
19790 { { MNEM, OP (SCCOND32), ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
19791 & ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI, { 0xd930 }
19792 },
19793/* sc${sccond32} $Dst32AnUnprefixedHI */
19794 {
19795 { 0, 0, 0, 0 },
19796 { { MNEM, OP (SCCOND32), ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
19797 & ifmt_sccnd_dst32_An_direct_Unprefixed_HI, { 0xd1b0 }
19798 },
19799/* sc${sccond32} [$Dst32AnUnprefixed] */
19800 {
19801 { 0, 0, 0, 0 },
19802 { { MNEM, OP (SCCOND32), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19803 & ifmt_sccnd_dst32_An_indirect_Unprefixed_HI, { 0xd130 }
19804 },
19805/* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19806 {
19807 { 0, 0, 0, 0 },
19808 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19809 & ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI, { 0xd33000 }
19810 },
19811/* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19812 {
19813 { 0, 0, 0, 0 },
19814 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19815 & ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5300000 }
19816 },
19817/* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19818 {
19819 { 0, 0, 0, 0 },
19820 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19821 & ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7300000 }
19822 },
19823/* sc${sccond32} ${Dsp-16-u8}[sb] */
19824 {
19825 { 0, 0, 0, 0 },
19826 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19827 & ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd3b000 }
19828 },
19829/* sc${sccond32} ${Dsp-16-u16}[sb] */
19830 {
19831 { 0, 0, 0, 0 },
19832 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19833 & ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5b00000 }
19834 },
19835/* sc${sccond32} ${Dsp-16-s8}[fb] */
19836 {
19837 { 0, 0, 0, 0 },
19838 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19839 & ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3f000 }
19840 },
19841/* sc${sccond32} ${Dsp-16-s16}[fb] */
19842 {
19843 { 0, 0, 0, 0 },
19844 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19845 & ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5f00000 }
19846 },
19847/* sc${sccond32} ${Dsp-16-u16} */
19848 {
19849 { 0, 0, 0, 0 },
19850 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), 0 } },
19851 & ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI, { 0xd7f00000 }
19852 },
19853/* sc${sccond32} ${Dsp-16-u24} */
19854 {
19855 { 0, 0, 0, 0 },
19856 { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), 0 } },
19857 & ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI, { 0xd7b00000 }
19858 },
c6552317 19859/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
49f58d10
JB		 19860 {
19861 { 0, 0, 0, 0 },
c6552317 19862 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 19863 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
19864 },
c6552317 19865/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 19866 {
19867 { 0, 0, 0, 0 },
c6552317 19868 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 19869 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
19870 },
c6552317 19871/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 19872 {
19873 { 0, 0, 0, 0 },
c6552317 19874 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 19875 & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
19876 },
c6552317 19877/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
49f58d10
JB		 19878 {
19879 { 0, 0, 0, 0 },
c6552317 19880 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19881 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
19882 },
c6552317 19883/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 19884 {
19885 { 0, 0, 0, 0 },
c6552317 19886 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19887 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
19888 },
c6552317 19889/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
49f58d10
JB		 19890 {
19891 { 0, 0, 0, 0 },
c6552317 19892 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19893 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
19894 },
c6552317 19895/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 19896 {
19897 { 0, 0, 0, 0 },
c6552317 19898 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19899 & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
19900 },
c6552317 19901/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
49f58d10
JB		 19902 {
19903 { 0, 0, 0, 0 },
c6552317 19904 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
49f58d10
JB		 19905 & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
19906 },
c6552317 19907/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
49f58d10
JB		 19908 {
19909 { 0, 0, 0, 0 },
c6552317 19910 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
49f58d10
JB		 19911 & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
19912 },
c6552317 19913/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
49f58d10
JB		 19914 {
19915 { 0, 0, 0, 0 },
c6552317 19916 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 19917 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
19918 },
c6552317 19919/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
49f58d10
JB		 19920 {
19921 { 0, 0, 0, 0 },
c6552317 19922 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 19923 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
19924 },
c6552317 19925/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
49f58d10
JB		 19926 {
19927 { 0, 0, 0, 0 },
c6552317 19928 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 19929 & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
19930 },
c6552317 19931/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
49f58d10
JB		 19932 {
19933 { 0, 0, 0, 0 },
c6552317 19934 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 19935 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
19936 },
c6552317 19937/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 19938 {
19939 { 0, 0, 0, 0 },
c6552317 19940 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 19941 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
19942 },
c6552317 19943/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 19944 {
19945 { 0, 0, 0, 0 },
c6552317 19946 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 19947 & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
19948 },
c6552317 19949/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
49f58d10
JB		 19950 {
19951 { 0, 0, 0, 0 },
c6552317 19952 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19953 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
19954 },
c6552317 19955/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 19956 {
19957 { 0, 0, 0, 0 },
c6552317 19958 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19959 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
19960 },
c6552317 19961/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
49f58d10
JB		 19962 {
19963 { 0, 0, 0, 0 },
c6552317 19964 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19965 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
19966 },
c6552317 19967/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 19968 {
19969 { 0, 0, 0, 0 },
c6552317 19970 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 19971 & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
19972 },
c6552317 19973/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
49f58d10
JB		 19974 {
19975 { 0, 0, 0, 0 },
c6552317 19976 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
49f58d10
JB		 19977 & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
19978 },
c6552317 19979/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
49f58d10
JB		 19980 {
19981 { 0, 0, 0, 0 },
c6552317 19982 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
49f58d10
JB		 19983 & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
19984 },
c6552317 19985/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
49f58d10
JB		 19986 {
19987 { 0, 0, 0, 0 },
c6552317 19988 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 19989 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
19990 },
c6552317 19991/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
49f58d10
JB		 19992 {
19993 { 0, 0, 0, 0 },
c6552317 19994 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 19995 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
19996 },
c6552317 19997/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
49f58d10
JB		 19998 {
19999 { 0, 0, 0, 0 },
c6552317 20000 { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 20001 & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
20002 },
c6552317 20003/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
49f58d10
JB		 20004 {
20005 { 0, 0, 0, 0 },
c6552317 20006 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 20007 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
20008 },
c6552317 20009/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 20010 {
20011 { 0, 0, 0, 0 },
c6552317 20012 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 20013 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
20014 },
c6552317 20015/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 20016 {
20017 { 0, 0, 0, 0 },
c6552317 20018 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 20019 & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
20020 },
c6552317 20021/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
49f58d10
JB		 20022 {
20023 { 0, 0, 0, 0 },
c6552317 20024 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 20025 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
20026 },
c6552317 20027/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 20028 {
20029 { 0, 0, 0, 0 },
c6552317 20030 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 20031 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
20032 },
c6552317 20033/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 20034 {
20035 { 0, 0, 0, 0 },
c6552317 20036 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 20037 & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
20038 },
c6552317 20039/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
49f58d10
JB		 20040 {
20041 { 0, 0, 0, 0 },
c6552317 20042 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 20043 & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
20044 },
c6552317 20045/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
49f58d10
JB		 20046 {
20047 { 0, 0, 0, 0 },
c6552317 20048 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 20049 & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
20050 },
c6552317 20051/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
49f58d10
JB		 20052 {
20053 { 0, 0, 0, 0 },
c6552317 20054 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 20055 & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
20056 },
c6552317 20057/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
49f58d10
JB		 20058 {
20059 { 0, 0, 0, 0 },
c6552317 20060 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 20061 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
20062 },
c6552317 20063/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 20064 {
20065 { 0, 0, 0, 0 },
c6552317 20066 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 20067 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
20068 },
c6552317 20069/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 20070 {
20071 { 0, 0, 0, 0 },
c6552317 20072 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
49f58d10
JB		 20073 & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
20074 },
c6552317 20075/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
49f58d10
JB		 20076 {
20077 { 0, 0, 0, 0 },
c6552317 20078 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 20079 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
20080 },
c6552317 20081/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 20082 {
20083 { 0, 0, 0, 0 },
c6552317 20084 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 20085 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
20086 },
c6552317 20087/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 20088 {
20089 { 0, 0, 0, 0 },
c6552317 20090 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
49f58d10
JB		 20091 & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
20092 },
c6552317 20093/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
49f58d10
JB		 20094 {
20095 { 0, 0, 0, 0 },
c6552317 20096 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 20097 & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
20098 },
c6552317 20099/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
49f58d10
JB		 20100 {
20101 { 0, 0, 0, 0 },
c6552317 20102 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 20103 & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
20104 },
c6552317 20105/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
49f58d10
JB		 20106 {
20107 { 0, 0, 0, 0 },
c6552317 20108 { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
49f58d10
JB		 20109 & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
20110 },
20111/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20112 {
20113 { 0, 0, 0, 0 },
20114 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20115 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990600 }
20116 },
20117/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
20118 {
20119 { 0, 0, 0, 0 },
20120 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20121 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992600 }
20122 },
20123/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
20124 {
20125 { 0, 0, 0, 0 },
20126 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20127 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993600 }
20128 },
20129/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20130 {
20131 { 0, 0, 0, 0 },
20132 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20133 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918600 }
20134 },
20135/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
20136 {
20137 { 0, 0, 0, 0 },
20138 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20139 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a600 }
20140 },
20141/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
20142 {
20143 { 0, 0, 0, 0 },
20144 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20145 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b600 }
20146 },
20147/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20148 {
20149 { 0, 0, 0, 0 },
20150 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20151 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910600 }
20152 },
20153/* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
20154 {
20155 { 0, 0, 0, 0 },
20156 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20157 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912600 }
20158 },
20159/* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
20160 {
20161 { 0, 0, 0, 0 },
20162 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20163 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913600 }
20164 },
20165/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
20166 {
20167 { 0, 0, 0, 0 },
20168 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20169 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930600 }
20170 },
20171/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
20172 {
20173 { 0, 0, 0, 0 },
20174 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20175 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932600 }
20176 },
20177/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
20178 {
20179 { 0, 0, 0, 0 },
20180 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20181 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933600 }
20182 },
20183/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
20184 {
20185 { 0, 0, 0, 0 },
20186 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20187 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950600 }
20188 },
20189/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20190 {
20191 { 0, 0, 0, 0 },
20192 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20193 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952600 }
20194 },
20195/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20196 {
20197 { 0, 0, 0, 0 },
20198 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20199 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953600 }
20200 },
20201/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
20202 {
20203 { 0, 0, 0, 0 },
20204 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20205 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970600 }
20206 },
20207/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20208 {
20209 { 0, 0, 0, 0 },
20210 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20211 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972600 }
20212 },
20213/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20214 {
20215 { 0, 0, 0, 0 },
20216 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20217 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973600 }
20218 },
20219/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
20220 {
20221 { 0, 0, 0, 0 },
20222 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20223 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938600 }
20224 },
20225/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
20226 {
20227 { 0, 0, 0, 0 },
20228 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20229 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a600 }
20230 },
20231/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
20232 {
20233 { 0, 0, 0, 0 },
20234 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20235 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b600 }
20236 },
20237/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
20238 {
20239 { 0, 0, 0, 0 },
20240 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20241 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958600 }
20242 },
20243/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
20244 {
20245 { 0, 0, 0, 0 },
20246 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20247 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a600 }
20248 },
20249/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
20250 {
20251 { 0, 0, 0, 0 },
20252 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20253 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b600 }
20254 },
20255/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
20256 {
20257 { 0, 0, 0, 0 },
20258 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20259 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c600 }
20260 },
20261/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
20262 {
20263 { 0, 0, 0, 0 },
20264 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20265 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e600 }
20266 },
20267/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
20268 {
20269 { 0, 0, 0, 0 },
20270 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20271 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f600 }
20272 },
20273/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
20274 {
20275 { 0, 0, 0, 0 },
20276 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20277 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c600 }
20278 },
20279/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
20280 {
20281 { 0, 0, 0, 0 },
20282 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20283 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e600 }
20284 },
20285/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
20286 {
20287 { 0, 0, 0, 0 },
20288 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20289 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f600 }
20290 },
20291/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
20292 {
20293 { 0, 0, 0, 0 },
20294 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
20295 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c600 }
20296 },
20297/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
20298 {
20299 { 0, 0, 0, 0 },
20300 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20301 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e600 }
20302 },
20303/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
20304 {
20305 { 0, 0, 0, 0 },
20306 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20307 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f600 }
20308 },
20309/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
20310 {
20311 { 0, 0, 0, 0 },
20312 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
20313 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978600 }
20314 },
20315/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
20316 {
20317 { 0, 0, 0, 0 },
20318 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
20319 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a600 }
20320 },
20321/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
20322 {
20323 { 0, 0, 0, 0 },
20324 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
20325 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b600 }
20326 },
20327/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20328 {
20329 { 0, 0, 0, 0 },
20330 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20331 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90600 }
20332 },
20333/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
20334 {
20335 { 0, 0, 0, 0 },
20336 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20337 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92600 }
20338 },
20339/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
20340 {
20341 { 0, 0, 0, 0 },
20342 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20343 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93600 }
20344 },
20345/* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
20346 {
20347 { 0, 0, 0, 0 },
20348 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
20349 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93600 }
20350 },
20351/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20352 {
20353 { 0, 0, 0, 0 },
20354 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20355 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18600 }
20356 },
20357/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
20358 {
20359 { 0, 0, 0, 0 },
20360 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20361 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a600 }
20362 },
20363/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
20364 {
20365 { 0, 0, 0, 0 },
20366 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20367 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b600 }
20368 },
20369/* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
20370 {
20371 { 0, 0, 0, 0 },
20372 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
20373 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b600 }
20374 },
20375/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20376 {
20377 { 0, 0, 0, 0 },
20378 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20379 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10600 }
20380 },
20381/* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
20382 {
20383 { 0, 0, 0, 0 },
20384 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20385 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12600 }
20386 },
20387/* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
20388 {
20389 { 0, 0, 0, 0 },
20390 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20391 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13600 }
20392 },
20393/* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
20394 {
20395 { 0, 0, 0, 0 },
20396 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20397 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13600 }
20398 },
20399/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
20400 {
20401 { 0, 0, 0, 0 },
20402 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20403 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30600 }
20404 },
20405/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
20406 {
20407 { 0, 0, 0, 0 },
20408 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20409 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32600 }
20410 },
20411/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
20412 {
20413 { 0, 0, 0, 0 },
20414 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20415 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33600 }
20416 },
20417/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
20418 {
20419 { 0, 0, 0, 0 },
20420 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20421 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33600 }
20422 },
20423/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
20424 {
20425 { 0, 0, 0, 0 },
20426 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20427 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50600 }
20428 },
20429/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
20430 {
20431 { 0, 0, 0, 0 },
20432 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20433 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52600 }
20434 },
20435/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
20436 {
20437 { 0, 0, 0, 0 },
20438 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20439 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53600 }
20440 },
20441/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
20442 {
20443 { 0, 0, 0, 0 },
20444 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20445 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53600 }
20446 },
20447/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
20448 {
20449 { 0, 0, 0, 0 },
20450 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20451 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70600 }
20452 },
20453/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
20454 {
20455 { 0, 0, 0, 0 },
20456 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20457 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72600 }
20458 },
20459/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
20460 {
20461 { 0, 0, 0, 0 },
20462 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20463 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73600 }
20464 },
20465/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
20466 {
20467 { 0, 0, 0, 0 },
20468 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20469 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73600 }
20470 },
20471/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
20472 {
20473 { 0, 0, 0, 0 },
20474 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20475 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38600 }
20476 },
20477/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
20478 {
20479 { 0, 0, 0, 0 },
20480 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20481 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a600 }
20482 },
20483/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
20484 {
20485 { 0, 0, 0, 0 },
20486 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20487 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b600 }
20488 },
20489/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
20490 {
20491 { 0, 0, 0, 0 },
20492 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20493 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b600 }
20494 },
20495/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
20496 {
20497 { 0, 0, 0, 0 },
20498 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20499 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58600 }
20500 },
20501/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
20502 {
20503 { 0, 0, 0, 0 },
20504 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20505 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a600 }
20506 },
20507/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
20508 {
20509 { 0, 0, 0, 0 },
20510 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20511 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b600 }
20512 },
20513/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
20514 {
20515 { 0, 0, 0, 0 },
20516 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20517 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b600 }
20518 },
20519/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
20520 {
20521 { 0, 0, 0, 0 },
20522 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20523 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c600 }
20524 },
20525/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
20526 {
20527 { 0, 0, 0, 0 },
20528 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20529 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e600 }
20530 },
20531/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
20532 {
20533 { 0, 0, 0, 0 },
20534 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20535 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f600 }
20536 },
20537/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
20538 {
20539 { 0, 0, 0, 0 },
20540 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20541 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f600 }
20542 },
20543/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
20544 {
20545 { 0, 0, 0, 0 },
20546 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20547 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c600 }
20548 },
20549/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
20550 {
20551 { 0, 0, 0, 0 },
20552 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20553 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e600 }
20554 },
20555/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
20556 {
20557 { 0, 0, 0, 0 },
20558 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20559 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f600 }
20560 },
20561/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
20562 {
20563 { 0, 0, 0, 0 },
20564 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20565 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f600 }
20566 },
20567/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
20568 {
20569 { 0, 0, 0, 0 },
20570 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
20571 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c600 }
20572 },
20573/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
20574 {
20575 { 0, 0, 0, 0 },
20576 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
20577 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e600 }
20578 },
20579/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
20580 {
20581 { 0, 0, 0, 0 },
20582 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
20583 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f600 }
20584 },
20585/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
20586 {
20587 { 0, 0, 0, 0 },
20588 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
20589 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f600 }
20590 },
20591/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
20592 {
20593 { 0, 0, 0, 0 },
20594 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
20595 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78600 }
20596 },
20597/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
20598 {
20599 { 0, 0, 0, 0 },
20600 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
20601 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a600 }
20602 },
20603/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
20604 {
20605 { 0, 0, 0, 0 },
20606 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
20607 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b600 }
20608 },
20609/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
20610 {
20611 { 0, 0, 0, 0 },
20612 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
20613 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b600 }
20614 },
20615/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20616 {
20617 { 0, 0, 0, 0 },
20618 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20619 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90600 }
20620 },
20621/* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
20622 {
20623 { 0, 0, 0, 0 },
20624 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
20625 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92600 }
20626 },
20627/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20628 {
20629 { 0, 0, 0, 0 },
20630 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20631 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18600 }
20632 },
20633/* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
20634 {
20635 { 0, 0, 0, 0 },
20636 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
20637 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a600 }
20638 },
20639/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20640 {
20641 { 0, 0, 0, 0 },
20642 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20643 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10600 }
20644 },
20645/* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
20646 {
20647 { 0, 0, 0, 0 },
20648 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20649 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12600 }
20650 },
20651/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
20652 {
20653 { 0, 0, 0, 0 },
20654 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20655 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30600 }
20656 },
20657/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
20658 {
20659 { 0, 0, 0, 0 },
20660 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20661 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32600 }
20662 },
20663/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
20664 {
20665 { 0, 0, 0, 0 },
20666 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20667 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50600 }
20668 },
20669/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
20670 {
20671 { 0, 0, 0, 0 },
20672 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20673 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52600 }
20674 },
20675/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
20676 {
20677 { 0, 0, 0, 0 },
20678 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20679 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70600 }
20680 },
20681/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
20682 {
20683 { 0, 0, 0, 0 },
20684 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20685 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72600 }
20686 },
20687/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
20688 {
20689 { 0, 0, 0, 0 },
20690 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
20691 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38600 }
20692 },
20693/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
20694 {
20695 { 0, 0, 0, 0 },
20696 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
20697 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a600 }
20698 },
20699/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
20700 {
20701 { 0, 0, 0, 0 },
20702 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
20703 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58600 }
20704 },
20705/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
20706 {
20707 { 0, 0, 0, 0 },
20708 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
20709 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a600 }
20710 },
20711/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
20712 {
20713 { 0, 0, 0, 0 },
20714 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
20715 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c600 }
20716 },
20717/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
20718 {
20719 { 0, 0, 0, 0 },
20720 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
20721 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e600 }
20722 },
20723/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
20724 {
20725 { 0, 0, 0, 0 },
20726 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
20727 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c600 }
20728 },
20729/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
20730 {
20731 { 0, 0, 0, 0 },
20732 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
20733 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e600 }
20734 },
20735/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
20736 {
20737 { 0, 0, 0, 0 },
20738 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
20739 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c600 }
20740 },
20741/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
20742 {
20743 { 0, 0, 0, 0 },
20744 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
20745 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e600 }
20746 },
20747/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
20748 {
20749 { 0, 0, 0, 0 },
20750 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
20751 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78600 }
20752 },
20753/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
20754 {
20755 { 0, 0, 0, 0 },
20756 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
20757 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a600 }
20758 },
20759/* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
20760 {
20761 { 0, 0, 0, 0 },
20762 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
20763 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c906 }
20764 },
20765/* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
20766 {
20767 { 0, 0, 0, 0 },
20768 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
20769 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18926 }
20770 },
20771/* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
20772 {
20773 { 0, 0, 0, 0 },
20774 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20775 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18906 }
20776 },
20777/* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
20778 {
20779 { 0, 0, 0, 0 },
20780 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
20781 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c186 }
20782 },
20783/* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
20784 {
20785 { 0, 0, 0, 0 },
20786 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
20787 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a6 }
20788 },
20789/* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
20790 {
20791 { 0, 0, 0, 0 },
20792 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20793 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18186 }
20794 },
20795/* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
20796 {
20797 { 0, 0, 0, 0 },
20798 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20799 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c106 }
20800 },
20801/* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
20802 {
20803 { 0, 0, 0, 0 },
20804 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20805 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18126 }
20806 },
20807/* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
20808 {
20809 { 0, 0, 0, 0 },
20810 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20811 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18106 }
20812 },
20813/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
20814 {
20815 { 0, 0, 0, 0 },
20816 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20817 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30600 }
20818 },
20819/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
20820 {
20821 { 0, 0, 0, 0 },
20822 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20823 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832600 }
20824 },
20825/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
20826 {
20827 { 0, 0, 0, 0 },
20828 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20829 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830600 }
20830 },
20831/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
20832 {
20833 { 0, 0, 0, 0 },
20834 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20835 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50600 }
20836 },
20837/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
20838 {
20839 { 0, 0, 0, 0 },
20840 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20841 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852600 }
20842 },
20843/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
20844 {
20845 { 0, 0, 0, 0 },
20846 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20847 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850600 }
20848 },
20849/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
20850 {
20851 { 0, 0, 0, 0 },
20852 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20853 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70600 }
20854 },
20855/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
20856 {
20857 { 0, 0, 0, 0 },
20858 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20859 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872600 }
20860 },
20861/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
20862 {
20863 { 0, 0, 0, 0 },
20864 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20865 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870600 }
20866 },
20867/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
20868 {
20869 { 0, 0, 0, 0 },
20870 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20871 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38600 }
20872 },
20873/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
20874 {
20875 { 0, 0, 0, 0 },
20876 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20877 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a600 }
20878 },
20879/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
20880 {
20881 { 0, 0, 0, 0 },
20882 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20883 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838600 }
20884 },
20885/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
20886 {
20887 { 0, 0, 0, 0 },
20888 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20889 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58600 }
20890 },
20891/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
20892 {
20893 { 0, 0, 0, 0 },
20894 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20895 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a600 }
20896 },
20897/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
20898 {
20899 { 0, 0, 0, 0 },
20900 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20901 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858600 }
20902 },
20903/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
20904 {
20905 { 0, 0, 0, 0 },
20906 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20907 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c600 }
20908 },
20909/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
20910 {
20911 { 0, 0, 0, 0 },
20912 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20913 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e600 }
20914 },
20915/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
20916 {
20917 { 0, 0, 0, 0 },
20918 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20919 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c600 }
20920 },
20921/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
20922 {
20923 { 0, 0, 0, 0 },
20924 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20925 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c600 }
20926 },
20927/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
20928 {
20929 { 0, 0, 0, 0 },
20930 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20931 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e600 }
20932 },
20933/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
20934 {
20935 { 0, 0, 0, 0 },
20936 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20937 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c600 }
20938 },
20939/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
20940 {
20941 { 0, 0, 0, 0 },
20942 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
20943 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c600 }
20944 },
20945/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
20946 {
20947 { 0, 0, 0, 0 },
20948 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
20949 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e600 }
20950 },
20951/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
20952 {
20953 { 0, 0, 0, 0 },
20954 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
20955 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c600 }
20956 },
20957/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
20958 {
20959 { 0, 0, 0, 0 },
20960 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
20961 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78600 }
20962 },
20963/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
20964 {
20965 { 0, 0, 0, 0 },
20966 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
20967 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a600 }
20968 },
20969/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
20970 {
20971 { 0, 0, 0, 0 },
20972 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
20973 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878600 }
20974 },
20975/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
20976 {
20977 { 0, 0, 0, 0 },
20978 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20979 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980600 }
20980 },
20981/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
20982 {
20983 { 0, 0, 0, 0 },
20984 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20985 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982600 }
20986 },
20987/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
20988 {
20989 { 0, 0, 0, 0 },
20990 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20991 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983600 }
20992 },
20993/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
20994 {
20995 { 0, 0, 0, 0 },
20996 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
20997 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908600 }
20998 },
20999/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
21000 {
21001 { 0, 0, 0, 0 },
21002 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21003 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a600 }
21004 },
21005/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
21006 {
21007 { 0, 0, 0, 0 },
21008 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21009 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b600 }
21010 },
21011/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21012 {
21013 { 0, 0, 0, 0 },
21014 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21015 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900600 }
21016 },
21017/* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
21018 {
21019 { 0, 0, 0, 0 },
21020 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21021 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902600 }
21022 },
21023/* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
21024 {
21025 { 0, 0, 0, 0 },
21026 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21027 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903600 }
21028 },
21029/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
21030 {
21031 { 0, 0, 0, 0 },
21032 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21033 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920600 }
21034 },
21035/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
21036 {
21037 { 0, 0, 0, 0 },
21038 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21039 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922600 }
21040 },
21041/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
21042 {
21043 { 0, 0, 0, 0 },
21044 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21045 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923600 }
21046 },
21047/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
21048 {
21049 { 0, 0, 0, 0 },
21050 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21051 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940600 }
21052 },
21053/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
21054 {
21055 { 0, 0, 0, 0 },
21056 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21057 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942600 }
21058 },
21059/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
21060 {
21061 { 0, 0, 0, 0 },
21062 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21063 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943600 }
21064 },
21065/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
21066 {
21067 { 0, 0, 0, 0 },
21068 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21069 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960600 }
21070 },
21071/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
21072 {
21073 { 0, 0, 0, 0 },
21074 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21075 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962600 }
21076 },
21077/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
21078 {
21079 { 0, 0, 0, 0 },
21080 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21081 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963600 }
21082 },
21083/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
21084 {
21085 { 0, 0, 0, 0 },
21086 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21087 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928600 }
21088 },
21089/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
21090 {
21091 { 0, 0, 0, 0 },
21092 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21093 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a600 }
21094 },
21095/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
21096 {
21097 { 0, 0, 0, 0 },
21098 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21099 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b600 }
21100 },
21101/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
21102 {
21103 { 0, 0, 0, 0 },
21104 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21105 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948600 }
21106 },
21107/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
21108 {
21109 { 0, 0, 0, 0 },
21110 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21111 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a600 }
21112 },
21113/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
21114 {
21115 { 0, 0, 0, 0 },
21116 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21117 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b600 }
21118 },
21119/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
21120 {
21121 { 0, 0, 0, 0 },
21122 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21123 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c600 }
21124 },
21125/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
21126 {
21127 { 0, 0, 0, 0 },
21128 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21129 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e600 }
21130 },
21131/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
21132 {
21133 { 0, 0, 0, 0 },
21134 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21135 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f600 }
21136 },
21137/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
21138 {
21139 { 0, 0, 0, 0 },
21140 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
21141 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c600 }
21142 },
21143/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
21144 {
21145 { 0, 0, 0, 0 },
21146 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
21147 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e600 }
21148 },
21149/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
21150 {
21151 { 0, 0, 0, 0 },
21152 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
21153 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f600 }
21154 },
21155/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
21156 {
21157 { 0, 0, 0, 0 },
21158 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
21159 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c600 }
21160 },
21161/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
21162 {
21163 { 0, 0, 0, 0 },
21164 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
21165 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e600 }
21166 },
21167/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
21168 {
21169 { 0, 0, 0, 0 },
21170 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
21171 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f600 }
21172 },
21173/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
21174 {
21175 { 0, 0, 0, 0 },
21176 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
21177 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968600 }
21178 },
21179/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
21180 {
21181 { 0, 0, 0, 0 },
21182 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
21183 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a600 }
21184 },
21185/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
21186 {
21187 { 0, 0, 0, 0 },
21188 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
21189 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b600 }
21190 },
21191/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
21192 {
21193 { 0, 0, 0, 0 },
21194 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21195 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80600 }
21196 },
21197/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
21198 {
21199 { 0, 0, 0, 0 },
21200 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21201 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82600 }
21202 },
21203/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
21204 {
21205 { 0, 0, 0, 0 },
21206 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21207 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83600 }
21208 },
21209/* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
21210 {
21211 { 0, 0, 0, 0 },
21212 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
21213 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83600 }
21214 },
21215/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
21216 {
21217 { 0, 0, 0, 0 },
21218 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21219 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08600 }
21220 },
21221/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
21222 {
21223 { 0, 0, 0, 0 },
21224 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21225 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a600 }
21226 },
21227/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
21228 {
21229 { 0, 0, 0, 0 },
21230 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21231 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b600 }
21232 },
21233/* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
21234 {
21235 { 0, 0, 0, 0 },
21236 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
21237 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b600 }
21238 },
21239/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21240 {
21241 { 0, 0, 0, 0 },
21242 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21243 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00600 }
21244 },
21245/* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
21246 {
21247 { 0, 0, 0, 0 },
21248 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21249 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02600 }
21250 },
21251/* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
21252 {
21253 { 0, 0, 0, 0 },
21254 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21255 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03600 }
21256 },
21257/* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
21258 {
21259 { 0, 0, 0, 0 },
21260 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21261 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03600 }
21262 },
21263/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
21264 {
21265 { 0, 0, 0, 0 },
21266 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21267 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20600 }
21268 },
21269/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
21270 {
21271 { 0, 0, 0, 0 },
21272 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21273 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22600 }
21274 },
21275/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
21276 {
21277 { 0, 0, 0, 0 },
21278 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21279 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23600 }
21280 },
21281/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
21282 {
21283 { 0, 0, 0, 0 },
21284 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21285 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23600 }
21286 },
21287/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
21288 {
21289 { 0, 0, 0, 0 },
21290 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21291 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40600 }
21292 },
21293/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
21294 {
21295 { 0, 0, 0, 0 },
21296 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21297 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42600 }
21298 },
21299/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
21300 {
21301 { 0, 0, 0, 0 },
21302 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21303 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43600 }
21304 },
21305/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
21306 {
21307 { 0, 0, 0, 0 },
21308 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21309 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43600 }
21310 },
21311/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
21312 {
21313 { 0, 0, 0, 0 },
21314 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21315 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60600 }
21316 },
21317/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
21318 {
21319 { 0, 0, 0, 0 },
21320 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21321 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62600 }
21322 },
21323/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
21324 {
21325 { 0, 0, 0, 0 },
21326 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21327 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63600 }
21328 },
21329/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
21330 {
21331 { 0, 0, 0, 0 },
21332 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21333 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63600 }
21334 },
21335/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
21336 {
21337 { 0, 0, 0, 0 },
21338 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21339 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28600 }
21340 },
21341/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
21342 {
21343 { 0, 0, 0, 0 },
21344 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21345 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a600 }
21346 },
21347/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
21348 {
21349 { 0, 0, 0, 0 },
21350 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21351 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b600 }
21352 },
21353/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
21354 {
21355 { 0, 0, 0, 0 },
21356 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21357 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b600 }
21358 },
21359/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
21360 {
21361 { 0, 0, 0, 0 },
21362 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21363 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48600 }
21364 },
21365/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
21366 {
21367 { 0, 0, 0, 0 },
21368 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21369 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a600 }
21370 },
21371/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
21372 {
21373 { 0, 0, 0, 0 },
21374 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21375 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b600 }
21376 },
21377/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
21378 {
21379 { 0, 0, 0, 0 },
21380 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21381 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b600 }
21382 },
21383/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
21384 {
21385 { 0, 0, 0, 0 },
21386 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21387 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c600 }
21388 },
21389/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
21390 {
21391 { 0, 0, 0, 0 },
21392 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21393 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e600 }
21394 },
21395/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
21396 {
21397 { 0, 0, 0, 0 },
21398 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21399 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f600 }
21400 },
21401/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
21402 {
21403 { 0, 0, 0, 0 },
21404 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21405 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f600 }
21406 },
21407/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
21408 {
21409 { 0, 0, 0, 0 },
21410 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21411 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c600 }
21412 },
21413/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
21414 {
21415 { 0, 0, 0, 0 },
21416 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21417 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e600 }
21418 },
21419/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
21420 {
21421 { 0, 0, 0, 0 },
21422 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21423 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f600 }
21424 },
21425/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
21426 {
21427 { 0, 0, 0, 0 },
21428 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21429 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f600 }
21430 },
21431/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
21432 {
21433 { 0, 0, 0, 0 },
21434 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
21435 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c600 }
21436 },
21437/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
21438 {
21439 { 0, 0, 0, 0 },
21440 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
21441 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e600 }
21442 },
21443/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
21444 {
21445 { 0, 0, 0, 0 },
21446 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
21447 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f600 }
21448 },
21449/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
21450 {
21451 { 0, 0, 0, 0 },
21452 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
21453 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f600 }
21454 },
21455/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
21456 {
21457 { 0, 0, 0, 0 },
21458 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
21459 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68600 }
21460 },
21461/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
21462 {
21463 { 0, 0, 0, 0 },
21464 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
21465 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a600 }
21466 },
21467/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
21468 {
21469 { 0, 0, 0, 0 },
21470 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
21471 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b600 }
21472 },
21473/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
21474 {
21475 { 0, 0, 0, 0 },
21476 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
21477 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b600 }
21478 },
21479/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
21480 {
21481 { 0, 0, 0, 0 },
21482 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21483 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80600 }
21484 },
21485/* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
21486 {
21487 { 0, 0, 0, 0 },
21488 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
21489 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82600 }
21490 },
21491/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
21492 {
21493 { 0, 0, 0, 0 },
21494 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21495 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08600 }
21496 },
21497/* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
21498 {
21499 { 0, 0, 0, 0 },
21500 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
21501 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a600 }
21502 },
21503/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21504 {
21505 { 0, 0, 0, 0 },
21506 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21507 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00600 }
21508 },
21509/* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
21510 {
21511 { 0, 0, 0, 0 },
21512 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21513 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02600 }
21514 },
21515/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
21516 {
21517 { 0, 0, 0, 0 },
21518 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21519 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20600 }
21520 },
21521/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
21522 {
21523 { 0, 0, 0, 0 },
21524 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21525 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22600 }
21526 },
21527/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
21528 {
21529 { 0, 0, 0, 0 },
21530 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21531 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40600 }
21532 },
21533/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
21534 {
21535 { 0, 0, 0, 0 },
21536 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21537 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42600 }
21538 },
21539/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
21540 {
21541 { 0, 0, 0, 0 },
21542 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21543 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60600 }
21544 },
21545/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
21546 {
21547 { 0, 0, 0, 0 },
21548 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21549 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62600 }
21550 },
21551/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
21552 {
21553 { 0, 0, 0, 0 },
21554 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
21555 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28600 }
21556 },
21557/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
21558 {
21559 { 0, 0, 0, 0 },
21560 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
21561 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a600 }
21562 },
21563/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
21564 {
21565 { 0, 0, 0, 0 },
21566 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
21567 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48600 }
21568 },
21569/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
21570 {
21571 { 0, 0, 0, 0 },
21572 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
21573 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a600 }
21574 },
21575/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
21576 {
21577 { 0, 0, 0, 0 },
21578 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
21579 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c600 }
21580 },
21581/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
21582 {
21583 { 0, 0, 0, 0 },
21584 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
21585 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e600 }
21586 },
21587/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
21588 {
21589 { 0, 0, 0, 0 },
21590 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
21591 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c600 }
21592 },
21593/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
21594 {
21595 { 0, 0, 0, 0 },
21596 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
21597 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e600 }
21598 },
21599/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
21600 {
21601 { 0, 0, 0, 0 },
21602 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
21603 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c600 }
21604 },
21605/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
21606 {
21607 { 0, 0, 0, 0 },
21608 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
21609 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e600 }
21610 },
21611/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
21612 {
21613 { 0, 0, 0, 0 },
21614 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
21615 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68600 }
21616 },
21617/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
21618 {
21619 { 0, 0, 0, 0 },
21620 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
21621 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a600 }
21622 },
21623/* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
21624 {
21625 { 0, 0, 0, 0 },
21626 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
21627 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c806 }
21628 },
21629/* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
21630 {
21631 { 0, 0, 0, 0 },
21632 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
21633 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18826 }
21634 },
21635/* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
21636 {
21637 { 0, 0, 0, 0 },
21638 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21639 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18806 }
21640 },
21641/* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
21642 {
21643 { 0, 0, 0, 0 },
21644 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
21645 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c086 }
21646 },
21647/* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
21648 {
21649 { 0, 0, 0, 0 },
21650 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
21651 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a6 }
21652 },
21653/* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
21654 {
21655 { 0, 0, 0, 0 },
21656 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21657 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18086 }
21658 },
21659/* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
21660 {
21661 { 0, 0, 0, 0 },
21662 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21663 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c006 }
21664 },
21665/* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
21666 {
21667 { 0, 0, 0, 0 },
21668 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21669 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18026 }
21670 },
21671/* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
21672 {
21673 { 0, 0, 0, 0 },
21674 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21675 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18006 }
21676 },
21677/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
21678 {
21679 { 0, 0, 0, 0 },
21680 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21681 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20600 }
21682 },
21683/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
21684 {
21685 { 0, 0, 0, 0 },
21686 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21687 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822600 }
21688 },
21689/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
21690 {
21691 { 0, 0, 0, 0 },
21692 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21693 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820600 }
21694 },
21695/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
21696 {
21697 { 0, 0, 0, 0 },
21698 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21699 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40600 }
21700 },
21701/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
21702 {
21703 { 0, 0, 0, 0 },
21704 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21705 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842600 }
21706 },
21707/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
21708 {
21709 { 0, 0, 0, 0 },
21710 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21711 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840600 }
21712 },
21713/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
21714 {
21715 { 0, 0, 0, 0 },
21716 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21717 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60600 }
21718 },
21719/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
21720 {
21721 { 0, 0, 0, 0 },
21722 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21723 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862600 }
21724 },
21725/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
21726 {
21727 { 0, 0, 0, 0 },
21728 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21729 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860600 }
21730 },
21731/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
21732 {
21733 { 0, 0, 0, 0 },
21734 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21735 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28600 }
21736 },
21737/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
21738 {
21739 { 0, 0, 0, 0 },
21740 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21741 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a600 }
21742 },
21743/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
21744 {
21745 { 0, 0, 0, 0 },
21746 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21747 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828600 }
21748 },
21749/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
21750 {
21751 { 0, 0, 0, 0 },
21752 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21753 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48600 }
21754 },
21755/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
21756 {
21757 { 0, 0, 0, 0 },
21758 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21759 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a600 }
21760 },
21761/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
21762 {
21763 { 0, 0, 0, 0 },
21764 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21765 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848600 }
21766 },
21767/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
21768 {
21769 { 0, 0, 0, 0 },
21770 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21771 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c600 }
21772 },
21773/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
21774 {
21775 { 0, 0, 0, 0 },
21776 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21777 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e600 }
21778 },
21779/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
21780 {
21781 { 0, 0, 0, 0 },
21782 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21783 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c600 }
21784 },
21785/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
21786 {
21787 { 0, 0, 0, 0 },
21788 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21789 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c600 }
21790 },
21791/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
21792 {
21793 { 0, 0, 0, 0 },
21794 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21795 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e600 }
21796 },
21797/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
21798 {
21799 { 0, 0, 0, 0 },
21800 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21801 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c600 }
21802 },
21803/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
21804 {
21805 { 0, 0, 0, 0 },
21806 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
21807 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c600 }
21808 },
21809/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
21810 {
21811 { 0, 0, 0, 0 },
21812 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
21813 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e600 }
21814 },
21815/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
21816 {
21817 { 0, 0, 0, 0 },
21818 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
21819 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c600 }
21820 },
21821/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
21822 {
21823 { 0, 0, 0, 0 },
21824 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
21825 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68600 }
21826 },
21827/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
21828 {
21829 { 0, 0, 0, 0 },
21830 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
21831 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a600 }
21832 },
21833/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
21834 {
21835 { 0, 0, 0, 0 },
21836 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
21837 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868600 }
21838 },
21839/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21840 {
21841 { 0, 0, 0, 0 },
21842 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
21843 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb98000 }
21844 },
21845/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
21846 {
21847 { 0, 0, 0, 0 },
21848 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
21849 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9a000 }
21850 },
21851/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
21852 {
21853 { 0, 0, 0, 0 },
21854 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
21855 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb9b000 }
21856 },
21857/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21858 {
21859 { 0, 0, 0, 0 },
21860 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
21861 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb98400 }
21862 },
21863/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
21864 {
21865 { 0, 0, 0, 0 },
21866 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
21867 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb9a400 }
21868 },
21869/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
21870 {
21871 { 0, 0, 0, 0 },
21872 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
21873 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb9b400 }
21874 },
21875/* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21876 {
21877 { 0, 0, 0, 0 },
21878 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
21879 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb98600 }
21880 },
21881/* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
21882 {
21883 { 0, 0, 0, 0 },
21884 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
21885 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb9a600 }
21886 },
21887/* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
21888 {
21889 { 0, 0, 0, 0 },
21890 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
21891 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb9b600 }
21892 },
21893/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21894 {
21895 { 0, 0, 0, 0 },
21896 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21897 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb9880000 }
21898 },
21899/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21900 {
21901 { 0, 0, 0, 0 },
21902 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21903 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9a80000 }
21904 },
21905/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21906 {
21907 { 0, 0, 0, 0 },
21908 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21909 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9b80000 }
21910 },
21911/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21912 {
21913 { 0, 0, 0, 0 },
21914 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21915 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb98c0000 }
21916 },
21917/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21918 {
21919 { 0, 0, 0, 0 },
21920 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21921 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9ac0000 }
21922 },
21923/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21924 {
21925 { 0, 0, 0, 0 },
21926 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21927 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9bc0000 }
21928 },
21929/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21930 {
21931 { 0, 0, 0, 0 },
21932 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21933 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb98a0000 }
21934 },
21935/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21936 {
21937 { 0, 0, 0, 0 },
21938 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21939 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9aa0000 }
21940 },
21941/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21942 {
21943 { 0, 0, 0, 0 },
21944 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21945 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9ba0000 }
21946 },
21947/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21948 {
21949 { 0, 0, 0, 0 },
21950 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21951 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb98e0000 }
21952 },
21953/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21954 {
21955 { 0, 0, 0, 0 },
21956 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21957 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9ae0000 }
21958 },
21959/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21960 {
21961 { 0, 0, 0, 0 },
21962 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21963 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9be0000 }
21964 },
21965/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21966 {
21967 { 0, 0, 0, 0 },
21968 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21969 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb98b0000 }
21970 },
21971/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21972 {
21973 { 0, 0, 0, 0 },
21974 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21975 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9ab0000 }
21976 },
21977/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21978 {
21979 { 0, 0, 0, 0 },
21980 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21981 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9bb0000 }
21982 },
21983/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21984 {
21985 { 0, 0, 0, 0 },
21986 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
21987 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb98f0000 }
21988 },
21989/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21990 {
21991 { 0, 0, 0, 0 },
21992 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
21993 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb9af0000 }
21994 },
21995/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21996 {
21997 { 0, 0, 0, 0 },
21998 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
21999 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb9bf0000 }
22000 },
22001/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
22002 {
22003 { 0, 0, 0, 0 },
22004 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
22005 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb9c00000 }
22006 },
22007/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
22008 {
22009 { 0, 0, 0, 0 },
22010 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
22011 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9e00000 }
22012 },
22013/* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
22014 {
22015 { 0, 0, 0, 0 },
22016 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
22017 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb9f00000 }
22018 },
22019/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
22020 {
22021 { 0, 0, 0, 0 },
22022 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
22023 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb9c40000 }
22024 },
22025/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
22026 {
22027 { 0, 0, 0, 0 },
22028 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
22029 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb9e40000 }
22030 },
22031/* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
22032 {
22033 { 0, 0, 0, 0 },
22034 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
22035 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb9f40000 }
22036 },
22037/* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
22038 {
22039 { 0, 0, 0, 0 },
22040 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22041 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb9c60000 }
22042 },
22043/* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
22044 {
22045 { 0, 0, 0, 0 },
22046 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22047 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb9e60000 }
22048 },
22049/* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
22050 {
22051 { 0, 0, 0, 0 },
22052 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
22053 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb9f60000 }
22054 },
22055/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
22056 {
22057 { 0, 0, 0, 0 },
22058 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22059 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb9c80000 }
22060 },
22061/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
22062 {
22063 { 0, 0, 0, 0 },
22064 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22065 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb9e80000 }
22066 },
22067/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
22068 {
22069 { 0, 0, 0, 0 },
22070 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22071 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb9f80000 }
22072 },
22073/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
22074 {
22075 { 0, 0, 0, 0 },
22076 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22077 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb9cc0000 }
22078 },
22079/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
22080 {
22081 { 0, 0, 0, 0 },
22082 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22083 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb9ec0000 }
22084 },
22085/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
22086 {
22087 { 0, 0, 0, 0 },
22088 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22089 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb9fc0000 }
22090 },
22091/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
22092 {
22093 { 0, 0, 0, 0 },
22094 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22095 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ca0000 }
22096 },
22097/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22098 {
22099 { 0, 0, 0, 0 },
22100 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22101 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ea0000 }
22102 },
22103/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22104 {
22105 { 0, 0, 0, 0 },
22106 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22107 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb9fa0000 }
22108 },
22109/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
22110 {
22111 { 0, 0, 0, 0 },
22112 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22113 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ce0000 }
22114 },
22115/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22116 {
22117 { 0, 0, 0, 0 },
22118 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22119 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ee0000 }
22120 },
22121/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22122 {
22123 { 0, 0, 0, 0 },
22124 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22125 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb9fe0000 }
22126 },
22127/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
22128 {
22129 { 0, 0, 0, 0 },
22130 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22131 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9cb0000 }
22132 },
22133/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22134 {
22135 { 0, 0, 0, 0 },
22136 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22137 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9eb0000 }
22138 },
22139/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22140 {
22141 { 0, 0, 0, 0 },
22142 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22143 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb9fb0000 }
22144 },
22145/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
22146 {
22147 { 0, 0, 0, 0 },
22148 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
22149 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb9cf0000 }
22150 },
22151/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22152 {
22153 { 0, 0, 0, 0 },
22154 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
22155 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb9ef0000 }
22156 },
22157/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
22158 {
22159 { 0, 0, 0, 0 },
22160 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
22161 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb9ff0000 }
22162 },
22163/* sbb.w${X} $Src16RnHI,$Dst16RnHI */
22164 {
22165 { 0, 0, 0, 0 },
22166 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
22167 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb900 }
22168 },
22169/* sbb.w${X} $Src16AnHI,$Dst16RnHI */
22170 {
22171 { 0, 0, 0, 0 },
22172 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
22173 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb940 }
22174 },
22175/* sbb.w${X} [$Src16An],$Dst16RnHI */
22176 {
22177 { 0, 0, 0, 0 },
22178 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
22179 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb960 }
22180 },
22181/* sbb.w${X} $Src16RnHI,$Dst16AnHI */
22182 {
22183 { 0, 0, 0, 0 },
22184 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
22185 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb904 }
22186 },
22187/* sbb.w${X} $Src16AnHI,$Dst16AnHI */
22188 {
22189 { 0, 0, 0, 0 },
22190 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
22191 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb944 }
22192 },
22193/* sbb.w${X} [$Src16An],$Dst16AnHI */
22194 {
22195 { 0, 0, 0, 0 },
22196 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
22197 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb964 }
22198 },
22199/* sbb.w${X} $Src16RnHI,[$Dst16An] */
22200 {
22201 { 0, 0, 0, 0 },
22202 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
22203 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb906 }
22204 },
22205/* sbb.w${X} $Src16AnHI,[$Dst16An] */
22206 {
22207 { 0, 0, 0, 0 },
22208 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
22209 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb946 }
22210 },
22211/* sbb.w${X} [$Src16An],[$Dst16An] */
22212 {
22213 { 0, 0, 0, 0 },
22214 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22215 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb966 }
22216 },
22217/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
22218 {
22219 { 0, 0, 0, 0 },
22220 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22221 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb90800 }
22222 },
22223/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
22224 {
22225 { 0, 0, 0, 0 },
22226 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22227 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb94800 }
22228 },
22229/* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
22230 {
22231 { 0, 0, 0, 0 },
22232 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22233 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb96800 }
22234 },
22235/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
22236 {
22237 { 0, 0, 0, 0 },
22238 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22239 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb90c0000 }
22240 },
22241/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
22242 {
22243 { 0, 0, 0, 0 },
22244 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22245 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb94c0000 }
22246 },
22247/* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
22248 {
22249 { 0, 0, 0, 0 },
22250 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22251 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb96c0000 }
22252 },
22253/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
22254 {
22255 { 0, 0, 0, 0 },
22256 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22257 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb90a00 }
22258 },
22259/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
22260 {
22261 { 0, 0, 0, 0 },
22262 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22263 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb94a00 }
22264 },
22265/* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
22266 {
22267 { 0, 0, 0, 0 },
22268 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22269 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb96a00 }
22270 },
22271/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
22272 {
22273 { 0, 0, 0, 0 },
22274 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22275 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb90e0000 }
22276 },
22277/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
22278 {
22279 { 0, 0, 0, 0 },
22280 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22281 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb94e0000 }
22282 },
22283/* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
22284 {
22285 { 0, 0, 0, 0 },
22286 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22287 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb96e0000 }
22288 },
22289/* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
22290 {
22291 { 0, 0, 0, 0 },
22292 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22293 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb90b00 }
22294 },
22295/* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
22296 {
22297 { 0, 0, 0, 0 },
22298 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22299 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb94b00 }
22300 },
22301/* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
22302 {
22303 { 0, 0, 0, 0 },
22304 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22305 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb96b00 }
22306 },
22307/* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
22308 {
22309 { 0, 0, 0, 0 },
22310 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
22311 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb90f0000 }
22312 },
22313/* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
22314 {
22315 { 0, 0, 0, 0 },
22316 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
22317 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb94f0000 }
22318 },
22319/* sbb.w${X} [$Src16An],${Dsp-16-u16} */
22320 {
22321 { 0, 0, 0, 0 },
22322 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
22323 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb96f0000 }
22324 },
22325/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
22326 {
22327 { 0, 0, 0, 0 },
22328 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22329 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb88000 }
22330 },
22331/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
22332 {
22333 { 0, 0, 0, 0 },
22334 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
22335 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8a000 }
22336 },
22337/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
22338 {
22339 { 0, 0, 0, 0 },
22340 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
22341 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb8b000 }
22342 },
22343/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
22344 {
22345 { 0, 0, 0, 0 },
22346 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22347 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb88400 }
22348 },
22349/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
22350 {
22351 { 0, 0, 0, 0 },
22352 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
22353 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb8a400 }
22354 },
22355/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
22356 {
22357 { 0, 0, 0, 0 },
22358 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
22359 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb8b400 }
22360 },
22361/* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
22362 {
22363 { 0, 0, 0, 0 },
22364 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22365 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb88600 }
22366 },
22367/* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
22368 {
22369 { 0, 0, 0, 0 },
22370 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22371 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb8a600 }
22372 },
22373/* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
22374 {
22375 { 0, 0, 0, 0 },
22376 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22377 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb8b600 }
22378 },
22379/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
22380 {
22381 { 0, 0, 0, 0 },
22382 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22383 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb8880000 }
22384 },
22385/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
22386 {
22387 { 0, 0, 0, 0 },
22388 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22389 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8a80000 }
22390 },
22391/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
22392 {
22393 { 0, 0, 0, 0 },
22394 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22395 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8b80000 }
22396 },
22397/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
22398 {
22399 { 0, 0, 0, 0 },
22400 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22401 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb88c0000 }
22402 },
22403/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
22404 {
22405 { 0, 0, 0, 0 },
22406 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22407 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8ac0000 }
22408 },
22409/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
22410 {
22411 { 0, 0, 0, 0 },
22412 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22413 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8bc0000 }
22414 },
22415/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
22416 {
22417 { 0, 0, 0, 0 },
22418 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22419 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb88a0000 }
22420 },
22421/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22422 {
22423 { 0, 0, 0, 0 },
22424 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22425 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8aa0000 }
22426 },
22427/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22428 {
22429 { 0, 0, 0, 0 },
22430 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22431 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8ba0000 }
22432 },
22433/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
22434 {
22435 { 0, 0, 0, 0 },
22436 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22437 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb88e0000 }
22438 },
22439/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22440 {
22441 { 0, 0, 0, 0 },
22442 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22443 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8ae0000 }
22444 },
22445/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22446 {
22447 { 0, 0, 0, 0 },
22448 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22449 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8be0000 }
22450 },
22451/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
22452 {
22453 { 0, 0, 0, 0 },
22454 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22455 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb88b0000 }
22456 },
22457/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22458 {
22459 { 0, 0, 0, 0 },
22460 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22461 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8ab0000 }
22462 },
22463/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22464 {
22465 { 0, 0, 0, 0 },
22466 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22467 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8bb0000 }
22468 },
22469/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
22470 {
22471 { 0, 0, 0, 0 },
22472 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
22473 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb88f0000 }
22474 },
22475/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22476 {
22477 { 0, 0, 0, 0 },
22478 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
22479 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb8af0000 }
22480 },
22481/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22482 {
22483 { 0, 0, 0, 0 },
22484 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
22485 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb8bf0000 }
22486 },
22487/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
22488 {
22489 { 0, 0, 0, 0 },
22490 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22491 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb8c00000 }
22492 },
22493/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
22494 {
22495 { 0, 0, 0, 0 },
22496 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
22497 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8e00000 }
22498 },
22499/* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
22500 {
22501 { 0, 0, 0, 0 },
22502 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
22503 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb8f00000 }
22504 },
22505/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
22506 {
22507 { 0, 0, 0, 0 },
22508 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22509 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb8c40000 }
22510 },
22511/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
22512 {
22513 { 0, 0, 0, 0 },
22514 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
22515 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb8e40000 }
22516 },
22517/* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
22518 {
22519 { 0, 0, 0, 0 },
22520 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
22521 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb8f40000 }
22522 },
22523/* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
22524 {
22525 { 0, 0, 0, 0 },
22526 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22527 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb8c60000 }
22528 },
22529/* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
22530 {
22531 { 0, 0, 0, 0 },
22532 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22533 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb8e60000 }
22534 },
22535/* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
22536 {
22537 { 0, 0, 0, 0 },
22538 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
22539 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb8f60000 }
22540 },
22541/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
22542 {
22543 { 0, 0, 0, 0 },
22544 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22545 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb8c80000 }
22546 },
22547/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
22548 {
22549 { 0, 0, 0, 0 },
22550 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22551 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb8e80000 }
22552 },
22553/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
22554 {
22555 { 0, 0, 0, 0 },
22556 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22557 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb8f80000 }
22558 },
22559/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
22560 {
22561 { 0, 0, 0, 0 },
22562 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22563 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb8cc0000 }
22564 },
22565/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
22566 {
22567 { 0, 0, 0, 0 },
22568 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22569 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb8ec0000 }
22570 },
22571/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
22572 {
22573 { 0, 0, 0, 0 },
22574 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22575 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb8fc0000 }
22576 },
22577/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
22578 {
22579 { 0, 0, 0, 0 },
22580 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22581 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ca0000 }
22582 },
22583/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22584 {
22585 { 0, 0, 0, 0 },
22586 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22587 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ea0000 }
22588 },
22589/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22590 {
22591 { 0, 0, 0, 0 },
22592 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22593 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb8fa0000 }
22594 },
22595/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
22596 {
22597 { 0, 0, 0, 0 },
22598 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22599 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ce0000 }
22600 },
22601/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22602 {
22603 { 0, 0, 0, 0 },
22604 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22605 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ee0000 }
22606 },
22607/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22608 {
22609 { 0, 0, 0, 0 },
22610 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22611 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb8fe0000 }
22612 },
22613/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
22614 {
22615 { 0, 0, 0, 0 },
22616 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22617 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8cb0000 }
22618 },
22619/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22620 {
22621 { 0, 0, 0, 0 },
22622 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22623 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8eb0000 }
22624 },
22625/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22626 {
22627 { 0, 0, 0, 0 },
22628 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22629 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb8fb0000 }
22630 },
22631/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
22632 {
22633 { 0, 0, 0, 0 },
22634 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
22635 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb8cf0000 }
22636 },
22637/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22638 {
22639 { 0, 0, 0, 0 },
22640 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
22641 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb8ef0000 }
22642 },
22643/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
22644 {
22645 { 0, 0, 0, 0 },
22646 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
22647 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb8ff0000 }
22648 },
22649/* sbb.b${X} $Src16RnQI,$Dst16RnQI */
22650 {
22651 { 0, 0, 0, 0 },
22652 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
22653 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb800 }
22654 },
22655/* sbb.b${X} $Src16AnQI,$Dst16RnQI */
22656 {
22657 { 0, 0, 0, 0 },
22658 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
22659 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb840 }
22660 },
22661/* sbb.b${X} [$Src16An],$Dst16RnQI */
22662 {
22663 { 0, 0, 0, 0 },
22664 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22665 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb860 }
22666 },
22667/* sbb.b${X} $Src16RnQI,$Dst16AnQI */
22668 {
22669 { 0, 0, 0, 0 },
22670 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
22671 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb804 }
22672 },
22673/* sbb.b${X} $Src16AnQI,$Dst16AnQI */
22674 {
22675 { 0, 0, 0, 0 },
22676 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
22677 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb844 }
22678 },
22679/* sbb.b${X} [$Src16An],$Dst16AnQI */
22680 {
22681 { 0, 0, 0, 0 },
22682 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22683 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb864 }
22684 },
22685/* sbb.b${X} $Src16RnQI,[$Dst16An] */
22686 {
22687 { 0, 0, 0, 0 },
22688 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
22689 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb806 }
22690 },
22691/* sbb.b${X} $Src16AnQI,[$Dst16An] */
22692 {
22693 { 0, 0, 0, 0 },
22694 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
22695 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb846 }
22696 },
22697/* sbb.b${X} [$Src16An],[$Dst16An] */
22698 {
22699 { 0, 0, 0, 0 },
22700 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22701 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb866 }
22702 },
22703/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
22704 {
22705 { 0, 0, 0, 0 },
22706 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22707 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb80800 }
22708 },
22709/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
22710 {
22711 { 0, 0, 0, 0 },
22712 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22713 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb84800 }
22714 },
22715/* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
22716 {
22717 { 0, 0, 0, 0 },
22718 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22719 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb86800 }
22720 },
22721/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
22722 {
22723 { 0, 0, 0, 0 },
22724 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22725 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb80c0000 }
22726 },
22727/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
22728 {
22729 { 0, 0, 0, 0 },
22730 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22731 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb84c0000 }
22732 },
22733/* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
22734 {
22735 { 0, 0, 0, 0 },
22736 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22737 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb86c0000 }
22738 },
22739/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
22740 {
22741 { 0, 0, 0, 0 },
22742 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22743 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb80a00 }
22744 },
22745/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
22746 {
22747 { 0, 0, 0, 0 },
22748 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22749 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb84a00 }
22750 },
22751/* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
22752 {
22753 { 0, 0, 0, 0 },
22754 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22755 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb86a00 }
22756 },
22757/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
22758 {
22759 { 0, 0, 0, 0 },
22760 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22761 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb80e0000 }
22762 },
22763/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
22764 {
22765 { 0, 0, 0, 0 },
22766 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22767 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb84e0000 }
22768 },
22769/* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
22770 {
22771 { 0, 0, 0, 0 },
22772 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22773 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb86e0000 }
22774 },
22775/* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
22776 {
22777 { 0, 0, 0, 0 },
22778 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22779 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb80b00 }
22780 },
22781/* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
22782 {
22783 { 0, 0, 0, 0 },
22784 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22785 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb84b00 }
22786 },
22787/* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
22788 {
22789 { 0, 0, 0, 0 },
22790 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22791 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb86b00 }
22792 },
22793/* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
22794 {
22795 { 0, 0, 0, 0 },
22796 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
22797 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb80f0000 }
22798 },
22799/* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
22800 {
22801 { 0, 0, 0, 0 },
22802 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
22803 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb84f0000 }
22804 },
22805/* sbb.b${X} [$Src16An],${Dsp-16-u16} */
22806 {
22807 { 0, 0, 0, 0 },
22808 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
22809 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb86f0000 }
22810 },
22811/* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
22812 {
22813 { 0, 0, 0, 0 },
22814 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
22815 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1992e00 }
22816 },
22817/* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
22818 {
22819 { 0, 0, 0, 0 },
22820 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
22821 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x191ae00 }
22822 },
22823/* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
22824 {
22825 { 0, 0, 0, 0 },
22826 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
22827 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1912e00 }
22828 },
22829/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
22830 {
22831 { 0, 0, 0, 0 },
22832 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
22833 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1932e00 }
22834 },
22835/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
22836 {
22837 { 0, 0, 0, 0 },
22838 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22839 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x193ae00 }
22840 },
22841/* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
22842 {
22843 { 0, 0, 0, 0 },
22844 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22845 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ee00 }
22846 },
22847/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
22848 {
22849 { 0, 0, 0, 0 },
22850 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
22851 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1952e00 }
22852 },
22853/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
22854 {
22855 { 0, 0, 0, 0 },
22856 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22857 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x195ae00 }
22858 },
22859/* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
22860 {
22861 { 0, 0, 0, 0 },
22862 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
22863 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ee00 }
22864 },
22865/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
22866 {
22867 { 0, 0, 0, 0 },
22868 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
22869 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ee00 }
22870 },
22871/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
22872 {
22873 { 0, 0, 0, 0 },
22874 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
22875 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1972e00 }
22876 },
22877/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
22878 {
22879 { 0, 0, 0, 0 },
22880 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
22881 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x197ae00 }
22882 },
22883/* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
22884 {
22885 { 0, 0, 0, 0 },
22886 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
22887 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1982e00 }
22888 },
22889/* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
22890 {
22891 { 0, 0, 0, 0 },
22892 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
22893 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x190ae00 }
22894 },
22895/* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
22896 {
22897 { 0, 0, 0, 0 },
22898 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
22899 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1902e00 }
22900 },
22901/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
22902 {
22903 { 0, 0, 0, 0 },
22904 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
22905 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1922e00 }
22906 },
22907/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
22908 {
22909 { 0, 0, 0, 0 },
22910 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22911 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x192ae00 }
22912 },
22913/* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
22914 {
22915 { 0, 0, 0, 0 },
22916 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22917 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ee00 }
22918 },
22919/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
22920 {
22921 { 0, 0, 0, 0 },
22922 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
22923 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1942e00 }
22924 },
22925/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
22926 {
22927 { 0, 0, 0, 0 },
22928 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22929 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x194ae00 }
22930 },
22931/* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
22932 {
22933 { 0, 0, 0, 0 },
22934 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
22935 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ee00 }
22936 },
22937/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
22938 {
22939 { 0, 0, 0, 0 },
22940 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
22941 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ee00 }
22942 },
22943/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
22944 {
22945 { 0, 0, 0, 0 },
22946 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
22947 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1962e00 }
22948 },
22949/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
22950 {
22951 { 0, 0, 0, 0 },
22952 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
22953 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x196ae00 }
22954 },
22955/* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
22956 {
22957 { 0, 0, 0, 0 },
22958 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
22959 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77700000 }
22960 },
22961/* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
22962 {
22963 { 0, 0, 0, 0 },
22964 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
22965 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77740000 }
22966 },
22967/* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
22968 {
22969 { 0, 0, 0, 0 },
22970 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
22971 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77760000 }
22972 },
22973/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22974 {
22975 { 0, 0, 0, 0 },
22976 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22977 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77780000 }
22978 },
22979/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22980 {
22981 { 0, 0, 0, 0 },
22982 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22983 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x777a0000 }
22984 },
22985/* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22986 {
22987 { 0, 0, 0, 0 },
22988 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22989 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x777b0000 }
22990 },
22991/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22992 {
22993 { 0, 0, 0, 0 },
22994 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22995 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x777c0000 }
22996 },
22997/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22998 {
22999 { 0, 0, 0, 0 },
23000 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23001 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x777e0000 }
23002 },
23003/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
23004 {
23005 { 0, 0, 0, 0 },
23006 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
23007 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x777f0000 }
23008 },
23009/* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
23010 {
23011 { 0, 0, 0, 0 },
23012 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
23013 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x767000 }
23014 },
23015/* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
23016 {
23017 { 0, 0, 0, 0 },
23018 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
23019 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x767400 }
23020 },
23021/* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
23022 {
23023 { 0, 0, 0, 0 },
23024 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
23025 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x767600 }
23026 },
23027/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
23028 {
23029 { 0, 0, 0, 0 },
23030 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23031 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76780000 }
23032 },
23033/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
23034 {
23035 { 0, 0, 0, 0 },
23036 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23037 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x767a0000 }
23038 },
23039/* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
23040 {
23041 { 0, 0, 0, 0 },
23042 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23043 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x767b0000 }
23044 },
23045/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
23046 {
23047 { 0, 0, 0, 0 },
23048 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23049 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x767c0000 }
23050 },
23051/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
23052 {
23053 { 0, 0, 0, 0 },
23054 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23055 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x767e0000 }
23056 },
23057/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
23058 {
23059 { 0, 0, 0, 0 },
23060 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
23061 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x767f0000 }
23062 },
a1a280bb 23063/* rot.w r1h,$Dst32RnUnprefixedHI */
49f58d10
JB		 23064 {
23065 { 0, 0, 0, 0 },
a1a280bb
DD		 23066 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
23067 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93f }
49f58d10 23068 },
a1a280bb 23069/* rot.w r1h,$Dst32AnUnprefixedHI */
49f58d10
JB		 23070 {
23071 { 0, 0, 0, 0 },
a1a280bb
DD		 23072 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
23073 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1bf }
49f58d10
JB		 23074 },
23075/* rot.w r1h,[$Dst32AnUnprefixed] */
23076 {
23077 { 0, 0, 0, 0 },
23078 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23079 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13f }
49f58d10
JB		 23080 },
23081/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23082 {
23083 { 0, 0, 0, 0 },
23084 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23085 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33f00 }
49f58d10
JB		 23086 },
23087/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23088 {
23089 { 0, 0, 0, 0 },
23090 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23091 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53f0000 }
49f58d10
JB		 23092 },
23093/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23094 {
23095 { 0, 0, 0, 0 },
23096 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23097 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73f0000 }
49f58d10
JB		 23098 },
23099/* rot.w r1h,${Dsp-16-u8}[sb] */
23100 {
23101 { 0, 0, 0, 0 },
23102 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 23103 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3bf00 }
49f58d10
JB		 23104 },
23105/* rot.w r1h,${Dsp-16-u16}[sb] */
23106 {
23107 { 0, 0, 0, 0 },
23108 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 23109 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5bf0000 }
49f58d10
JB		 23110 },
23111/* rot.w r1h,${Dsp-16-s8}[fb] */
23112 {
23113 { 0, 0, 0, 0 },
23114 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 23115 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ff00 }
49f58d10
JB		 23116 },
23117/* rot.w r1h,${Dsp-16-s16}[fb] */
23118 {
23119 { 0, 0, 0, 0 },
23120 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 23121 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ff0000 }
49f58d10
JB		 23122 },
23123/* rot.w r1h,${Dsp-16-u16} */
23124 {
23125 { 0, 0, 0, 0 },
23126 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 23127 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ff0000 }
49f58d10
JB		 23128 },
23129/* rot.w r1h,${Dsp-16-u24} */
23130 {
23131 { 0, 0, 0, 0 },
23132 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
a1a280bb 23133 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7bf0000 }
49f58d10 23134 },
a1a280bb 23135/* rot.b r1h,$Dst32RnUnprefixedQI */
49f58d10
JB		 23136 {
23137 { 0, 0, 0, 0 },
a1a280bb
DD		 23138 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
23139 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83f }
49f58d10 23140 },
a1a280bb 23141/* rot.b r1h,$Dst32AnUnprefixedQI */
49f58d10
JB		 23142 {
23143 { 0, 0, 0, 0 },
a1a280bb
DD		 23144 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
23145 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0bf }
49f58d10
JB		 23146 },
23147/* rot.b r1h,[$Dst32AnUnprefixed] */
23148 {
23149 { 0, 0, 0, 0 },
23150 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23151 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03f }
49f58d10
JB		 23152 },
23153/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23154 {
23155 { 0, 0, 0, 0 },
23156 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23157 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23f00 }
49f58d10
JB		 23158 },
23159/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23160 {
23161 { 0, 0, 0, 0 },
23162 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23163 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43f0000 }
49f58d10
JB		 23164 },
23165/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23166 {
23167 { 0, 0, 0, 0 },
23168 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
a1a280bb 23169 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63f0000 }
49f58d10
JB		 23170 },
23171/* rot.b r1h,${Dsp-16-u8}[sb] */
23172 {
23173 { 0, 0, 0, 0 },
23174 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 23175 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2bf00 }
49f58d10
JB		 23176 },
23177/* rot.b r1h,${Dsp-16-u16}[sb] */
23178 {
23179 { 0, 0, 0, 0 },
23180 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 23181 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4bf0000 }
49f58d10
JB		 23182 },
23183/* rot.b r1h,${Dsp-16-s8}[fb] */
23184 {
23185 { 0, 0, 0, 0 },
23186 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 23187 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ff00 }
49f58d10
JB		 23188 },
23189/* rot.b r1h,${Dsp-16-s16}[fb] */
23190 {
23191 { 0, 0, 0, 0 },
23192 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
a1a280bb 23193 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ff0000 }
49f58d10
JB		 23194 },
23195/* rot.b r1h,${Dsp-16-u16} */
23196 {
23197 { 0, 0, 0, 0 },
23198 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 23199 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ff0000 }
49f58d10
JB		 23200 },
23201/* rot.b r1h,${Dsp-16-u24} */
23202 {
23203 { 0, 0, 0, 0 },
23204 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
a1a280bb 23205 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6bf0000 }
49f58d10
JB		 23206 },
23207/* rot.w r1h,$Dst16RnHI */
23208 {
23209 { 0, 0, 0, 0 },
23210 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
23211 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7560 }
23212 },
23213/* rot.w r1h,$Dst16AnHI */
23214 {
23215 { 0, 0, 0, 0 },
23216 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
23217 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7564 }
23218 },
23219/* rot.w r1h,[$Dst16An] */
23220 {
23221 { 0, 0, 0, 0 },
23222 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
23223 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7566 }
23224 },
23225/* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
23226 {
23227 { 0, 0, 0, 0 },
23228 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23229 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x756800 }
23230 },
23231/* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
23232 {
23233 { 0, 0, 0, 0 },
23234 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23235 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x756c0000 }
23236 },
23237/* rot.w r1h,${Dsp-16-u8}[sb] */
23238 {
23239 { 0, 0, 0, 0 },
23240 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23241 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x756a00 }
23242 },
23243/* rot.w r1h,${Dsp-16-u16}[sb] */
23244 {
23245 { 0, 0, 0, 0 },
23246 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23247 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x756e0000 }
23248 },
23249/* rot.w r1h,${Dsp-16-s8}[fb] */
23250 {
23251 { 0, 0, 0, 0 },
23252 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23253 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x756b00 }
23254 },
23255/* rot.w r1h,${Dsp-16-u16} */
23256 {
23257 { 0, 0, 0, 0 },
23258 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
23259 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x756f0000 }
23260 },
a1a280bb 23261/* rot.b r1h,$Dst16RnQI */
49f58d10
JB		 23262 {
23263 { 0, 0, 0, 0 },
a1a280bb
DD		 23264 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
23265 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7460 }
49f58d10 23266 },
a1a280bb 23267/* rot.b r1h,$Dst16AnQI */
49f58d10
JB		 23268 {
23269 { 0, 0, 0, 0 },
a1a280bb
DD		 23270 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
23271 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7464 }
49f58d10
JB		 23272 },
23273/* rot.b r1h,[$Dst16An] */
23274 {
23275 { 0, 0, 0, 0 },
23276 { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 23277 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7466 }
49f58d10
JB		 23278 },
23279/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
23280 {
23281 { 0, 0, 0, 0 },
23282 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
a1a280bb 23283 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x746800 }
49f58d10
JB		 23284 },
23285/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
23286 {
23287 { 0, 0, 0, 0 },
23288 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 23289 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x746c0000 }
49f58d10
JB		 23290 },
23291/* rot.b r1h,${Dsp-16-u8}[sb] */
23292 {
23293 { 0, 0, 0, 0 },
23294 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
a1a280bb 23295 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x746a00 }
49f58d10
JB		 23296 },
23297/* rot.b r1h,${Dsp-16-u16}[sb] */
23298 {
23299 { 0, 0, 0, 0 },
23300 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 23301 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x746e0000 }
49f58d10
JB		 23302 },
23303/* rot.b r1h,${Dsp-16-s8}[fb] */
23304 {
23305 { 0, 0, 0, 0 },
23306 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
a1a280bb 23307 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x746b00 }
49f58d10
JB		 23308 },
23309/* rot.b r1h,${Dsp-16-u16} */
23310 {
23311 { 0, 0, 0, 0 },
23312 { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
a1a280bb 23313 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x746f0000 }
49f58d10
JB		 23314 },
23315/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
23316 {
23317 { 0, 0, 0, 0 },
23318 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
23319 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe920 }
23320 },
23321/* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
23322 {
23323 { 0, 0, 0, 0 },
23324 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
23325 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1a0 }
23326 },
23327/* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
23328 {
23329 { 0, 0, 0, 0 },
23330 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23331 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe120 }
23332 },
23333/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
23334 {
23335 { 0, 0, 0, 0 },
23336 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23337 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe32000 }
23338 },
23339/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
23340 {
23341 { 0, 0, 0, 0 },
23342 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23343 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5200000 }
23344 },
23345/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
23346 {
23347 { 0, 0, 0, 0 },
23348 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23349 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7200000 }
23350 },
23351/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
23352 {
23353 { 0, 0, 0, 0 },
23354 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23355 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3a000 }
23356 },
23357/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
23358 {
23359 { 0, 0, 0, 0 },
23360 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23361 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5a00000 }
23362 },
23363/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
23364 {
23365 { 0, 0, 0, 0 },
23366 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23367 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3e000 }
23368 },
23369/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
23370 {
23371 { 0, 0, 0, 0 },
23372 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23373 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5e00000 }
23374 },
23375/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
23376 {
23377 { 0, 0, 0, 0 },
23378 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
23379 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7e00000 }
23380 },
23381/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
23382 {
23383 { 0, 0, 0, 0 },
23384 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
23385 & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7a00000 }
23386 },
23387/* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
23388 {
23389 { 0, 0, 0, 0 },
23390 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
23391 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe820 }
23392 },
23393/* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
23394 {
23395 { 0, 0, 0, 0 },
23396 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
23397 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0a0 }
23398 },
23399/* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
23400 {
23401 { 0, 0, 0, 0 },
23402 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23403 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe020 }
23404 },
23405/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
23406 {
23407 { 0, 0, 0, 0 },
23408 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23409 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe22000 }
23410 },
23411/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
23412 {
23413 { 0, 0, 0, 0 },
23414 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23415 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4200000 }
23416 },
23417/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
23418 {
23419 { 0, 0, 0, 0 },
23420 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23421 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6200000 }
23422 },
23423/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
23424 {
23425 { 0, 0, 0, 0 },
23426 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23427 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2a000 }
23428 },
23429/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
23430 {
23431 { 0, 0, 0, 0 },
23432 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23433 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4a00000 }
23434 },
23435/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
23436 {
23437 { 0, 0, 0, 0 },
23438 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23439 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2e000 }
23440 },
23441/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
23442 {
23443 { 0, 0, 0, 0 },
23444 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23445 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4e00000 }
23446 },
23447/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
23448 {
23449 { 0, 0, 0, 0 },
23450 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
23451 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6e00000 }
23452 },
23453/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
23454 {
23455 { 0, 0, 0, 0 },
23456 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
23457 & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6a00000 }
23458 },
23459/* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
23460 {
23461 { 0, 0, 0, 0 },
23462 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
23463 & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe100 }
23464 },
23465/* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
23466 {
23467 { 0, 0, 0, 0 },
23468 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
23469 & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe104 }
23470 },
23471/* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
23472 {
23473 { 0, 0, 0, 0 },
23474 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
23475 & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe106 }
23476 },
23477/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
23478 {
23479 { 0, 0, 0, 0 },
23480 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23481 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe10800 }
23482 },
23483/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
23484 {
23485 { 0, 0, 0, 0 },
23486 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23487 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe10c0000 }
23488 },
23489/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
23490 {
23491 { 0, 0, 0, 0 },
23492 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23493 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe10a00 }
23494 },
23495/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
23496 {
23497 { 0, 0, 0, 0 },
23498 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23499 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe10e0000 }
23500 },
23501/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
23502 {
23503 { 0, 0, 0, 0 },
23504 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23505 & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe10b00 }
23506 },
23507/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
23508 {
23509 { 0, 0, 0, 0 },
23510 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
23511 & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe10f0000 }
23512 },
23513/* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
23514 {
23515 { 0, 0, 0, 0 },
23516 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
23517 & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe000 }
23518 },
23519/* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
23520 {
23521 { 0, 0, 0, 0 },
23522 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
23523 & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe004 }
23524 },
23525/* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
23526 {
23527 { 0, 0, 0, 0 },
23528 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
23529 & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe006 }
23530 },
23531/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
23532 {
23533 { 0, 0, 0, 0 },
23534 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23535 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe00800 }
23536 },
23537/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
23538 {
23539 { 0, 0, 0, 0 },
23540 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23541 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe00c0000 }
23542 },
23543/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
23544 {
23545 { 0, 0, 0, 0 },
23546 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23547 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe00a00 }
23548 },
23549/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
23550 {
23551 { 0, 0, 0, 0 },
23552 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23553 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe00e0000 }
23554 },
23555/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
23556 {
23557 { 0, 0, 0, 0 },
23558 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23559 & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe00b00 }
23560 },
23561/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
23562 {
23563 { 0, 0, 0, 0 },
23564 { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
23565 & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe00f0000 }
23566 },
23567/* rorc.w $Dst32RnUnprefixedHI */
23568 {
23569 { 0, 0, 0, 0 },
23570 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
23571 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92e }
23572 },
23573/* rorc.w $Dst32AnUnprefixedHI */
23574 {
23575 { 0, 0, 0, 0 },
23576 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
23577 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1ae }
23578 },
23579/* rorc.w [$Dst32AnUnprefixed] */
23580 {
23581 { 0, 0, 0, 0 },
23582 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23583 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12e }
23584 },
23585/* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23586 {
23587 { 0, 0, 0, 0 },
23588 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23589 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32e00 }
23590 },
23591/* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23592 {
23593 { 0, 0, 0, 0 },
23594 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23595 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52e0000 }
23596 },
23597/* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23598 {
23599 { 0, 0, 0, 0 },
23600 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23601 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72e0000 }
23602 },
23603/* rorc.w ${Dsp-16-u8}[sb] */
23604 {
23605 { 0, 0, 0, 0 },
23606 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23607 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3ae00 }
23608 },
23609/* rorc.w ${Dsp-16-u16}[sb] */
23610 {
23611 { 0, 0, 0, 0 },
23612 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23613 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5ae0000 }
23614 },
23615/* rorc.w ${Dsp-16-s8}[fb] */
23616 {
23617 { 0, 0, 0, 0 },
23618 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23619 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ee00 }
23620 },
23621/* rorc.w ${Dsp-16-s16}[fb] */
23622 {
23623 { 0, 0, 0, 0 },
23624 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23625 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ee0000 }
23626 },
23627/* rorc.w ${Dsp-16-u16} */
23628 {
23629 { 0, 0, 0, 0 },
23630 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23631 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ee0000 }
23632 },
23633/* rorc.w ${Dsp-16-u24} */
23634 {
23635 { 0, 0, 0, 0 },
23636 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23637 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7ae0000 }
23638 },
23639/* rorc.b $Dst32RnUnprefixedQI */
23640 {
23641 { 0, 0, 0, 0 },
23642 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
23643 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82e }
23644 },
23645/* rorc.b $Dst32AnUnprefixedQI */
23646 {
23647 { 0, 0, 0, 0 },
23648 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
23649 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0ae }
23650 },
23651/* rorc.b [$Dst32AnUnprefixed] */
23652 {
23653 { 0, 0, 0, 0 },
23654 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23655 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02e }
23656 },
23657/* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23658 {
23659 { 0, 0, 0, 0 },
23660 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23661 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22e00 }
23662 },
23663/* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23664 {
23665 { 0, 0, 0, 0 },
23666 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23667 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42e0000 }
23668 },
23669/* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23670 {
23671 { 0, 0, 0, 0 },
23672 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23673 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62e0000 }
23674 },
23675/* rorc.b ${Dsp-16-u8}[sb] */
23676 {
23677 { 0, 0, 0, 0 },
23678 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23679 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2ae00 }
23680 },
23681/* rorc.b ${Dsp-16-u16}[sb] */
23682 {
23683 { 0, 0, 0, 0 },
23684 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23685 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4ae0000 }
23686 },
23687/* rorc.b ${Dsp-16-s8}[fb] */
23688 {
23689 { 0, 0, 0, 0 },
23690 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23691 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ee00 }
23692 },
23693/* rorc.b ${Dsp-16-s16}[fb] */
23694 {
23695 { 0, 0, 0, 0 },
23696 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23697 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ee0000 }
23698 },
23699/* rorc.b ${Dsp-16-u16} */
23700 {
23701 { 0, 0, 0, 0 },
23702 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23703 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ee0000 }
23704 },
23705/* rorc.b ${Dsp-16-u24} */
23706 {
23707 { 0, 0, 0, 0 },
23708 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23709 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6ae0000 }
23710 },
23711/* rorc.w $Dst16RnHI */
23712 {
23713 { 0, 0, 0, 0 },
23714 { { MNEM, ' ', OP (DST16RNHI), 0 } },
23715 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77b0 }
23716 },
23717/* rorc.w $Dst16AnHI */
23718 {
23719 { 0, 0, 0, 0 },
23720 { { MNEM, ' ', OP (DST16ANHI), 0 } },
23721 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77b4 }
23722 },
23723/* rorc.w [$Dst16An] */
23724 {
23725 { 0, 0, 0, 0 },
23726 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23727 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77b6 }
23728 },
23729/* rorc.w ${Dsp-16-u8}[$Dst16An] */
23730 {
23731 { 0, 0, 0, 0 },
23732 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23733 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77b800 }
23734 },
23735/* rorc.w ${Dsp-16-u16}[$Dst16An] */
23736 {
23737 { 0, 0, 0, 0 },
23738 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23739 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77bc0000 }
23740 },
23741/* rorc.w ${Dsp-16-u8}[sb] */
23742 {
23743 { 0, 0, 0, 0 },
23744 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23745 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ba00 }
23746 },
23747/* rorc.w ${Dsp-16-u16}[sb] */
23748 {
23749 { 0, 0, 0, 0 },
23750 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23751 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77be0000 }
23752 },
23753/* rorc.w ${Dsp-16-s8}[fb] */
23754 {
23755 { 0, 0, 0, 0 },
23756 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23757 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77bb00 }
23758 },
23759/* rorc.w ${Dsp-16-u16} */
23760 {
23761 { 0, 0, 0, 0 },
23762 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23763 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77bf0000 }
23764 },
23765/* rorc.b $Dst16RnQI */
23766 {
23767 { 0, 0, 0, 0 },
23768 { { MNEM, ' ', OP (DST16RNQI), 0 } },
23769 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76b0 }
23770 },
23771/* rorc.b $Dst16AnQI */
23772 {
23773 { 0, 0, 0, 0 },
23774 { { MNEM, ' ', OP (DST16ANQI), 0 } },
23775 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76b4 }
23776 },
23777/* rorc.b [$Dst16An] */
23778 {
23779 { 0, 0, 0, 0 },
23780 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23781 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76b6 }
23782 },
23783/* rorc.b ${Dsp-16-u8}[$Dst16An] */
23784 {
23785 { 0, 0, 0, 0 },
23786 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23787 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76b800 }
23788 },
23789/* rorc.b ${Dsp-16-u16}[$Dst16An] */
23790 {
23791 { 0, 0, 0, 0 },
23792 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23793 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76bc0000 }
23794 },
23795/* rorc.b ${Dsp-16-u8}[sb] */
23796 {
23797 { 0, 0, 0, 0 },
23798 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23799 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ba00 }
23800 },
23801/* rorc.b ${Dsp-16-u16}[sb] */
23802 {
23803 { 0, 0, 0, 0 },
23804 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23805 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76be0000 }
23806 },
23807/* rorc.b ${Dsp-16-s8}[fb] */
23808 {
23809 { 0, 0, 0, 0 },
23810 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23811 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76bb00 }
23812 },
23813/* rorc.b ${Dsp-16-u16} */
23814 {
23815 { 0, 0, 0, 0 },
23816 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23817 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76bf0000 }
23818 },
23819/* rolc.w $Dst32RnUnprefixedHI */
23820 {
23821 { 0, 0, 0, 0 },
23822 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
23823 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92e }
23824 },
23825/* rolc.w $Dst32AnUnprefixedHI */
23826 {
23827 { 0, 0, 0, 0 },
23828 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
23829 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1ae }
23830 },
23831/* rolc.w [$Dst32AnUnprefixed] */
23832 {
23833 { 0, 0, 0, 0 },
23834 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23835 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12e }
23836 },
23837/* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23838 {
23839 { 0, 0, 0, 0 },
23840 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23841 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32e00 }
23842 },
23843/* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23844 {
23845 { 0, 0, 0, 0 },
23846 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23847 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52e0000 }
23848 },
23849/* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23850 {
23851 { 0, 0, 0, 0 },
23852 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23853 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72e0000 }
23854 },
23855/* rolc.w ${Dsp-16-u8}[sb] */
23856 {
23857 { 0, 0, 0, 0 },
23858 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23859 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3ae00 }
23860 },
23861/* rolc.w ${Dsp-16-u16}[sb] */
23862 {
23863 { 0, 0, 0, 0 },
23864 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23865 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5ae0000 }
23866 },
23867/* rolc.w ${Dsp-16-s8}[fb] */
23868 {
23869 { 0, 0, 0, 0 },
23870 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23871 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ee00 }
23872 },
23873/* rolc.w ${Dsp-16-s16}[fb] */
23874 {
23875 { 0, 0, 0, 0 },
23876 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23877 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ee0000 }
23878 },
23879/* rolc.w ${Dsp-16-u16} */
23880 {
23881 { 0, 0, 0, 0 },
23882 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23883 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ee0000 }
23884 },
23885/* rolc.w ${Dsp-16-u24} */
23886 {
23887 { 0, 0, 0, 0 },
23888 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23889 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7ae0000 }
23890 },
23891/* rolc.b $Dst32RnUnprefixedQI */
23892 {
23893 { 0, 0, 0, 0 },
23894 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
23895 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82e }
23896 },
23897/* rolc.b $Dst32AnUnprefixedQI */
23898 {
23899 { 0, 0, 0, 0 },
23900 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
23901 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0ae }
23902 },
23903/* rolc.b [$Dst32AnUnprefixed] */
23904 {
23905 { 0, 0, 0, 0 },
23906 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23907 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02e }
23908 },
23909/* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23910 {
23911 { 0, 0, 0, 0 },
23912 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23913 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22e00 }
23914 },
23915/* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23916 {
23917 { 0, 0, 0, 0 },
23918 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23919 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42e0000 }
23920 },
23921/* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23922 {
23923 { 0, 0, 0, 0 },
23924 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23925 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62e0000 }
23926 },
23927/* rolc.b ${Dsp-16-u8}[sb] */
23928 {
23929 { 0, 0, 0, 0 },
23930 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23931 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2ae00 }
23932 },
23933/* rolc.b ${Dsp-16-u16}[sb] */
23934 {
23935 { 0, 0, 0, 0 },
23936 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23937 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4ae0000 }
23938 },
23939/* rolc.b ${Dsp-16-s8}[fb] */
23940 {
23941 { 0, 0, 0, 0 },
23942 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23943 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ee00 }
23944 },
23945/* rolc.b ${Dsp-16-s16}[fb] */
23946 {
23947 { 0, 0, 0, 0 },
23948 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23949 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ee0000 }
23950 },
23951/* rolc.b ${Dsp-16-u16} */
23952 {
23953 { 0, 0, 0, 0 },
23954 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23955 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ee0000 }
23956 },
23957/* rolc.b ${Dsp-16-u24} */
23958 {
23959 { 0, 0, 0, 0 },
23960 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23961 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6ae0000 }
23962 },
23963/* rolc.w $Dst16RnHI */
23964 {
23965 { 0, 0, 0, 0 },
23966 { { MNEM, ' ', OP (DST16RNHI), 0 } },
23967 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77a0 }
23968 },
23969/* rolc.w $Dst16AnHI */
23970 {
23971 { 0, 0, 0, 0 },
23972 { { MNEM, ' ', OP (DST16ANHI), 0 } },
23973 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77a4 }
23974 },
23975/* rolc.w [$Dst16An] */
23976 {
23977 { 0, 0, 0, 0 },
23978 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23979 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77a6 }
23980 },
23981/* rolc.w ${Dsp-16-u8}[$Dst16An] */
23982 {
23983 { 0, 0, 0, 0 },
23984 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23985 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77a800 }
23986 },
23987/* rolc.w ${Dsp-16-u16}[$Dst16An] */
23988 {
23989 { 0, 0, 0, 0 },
23990 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23991 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ac0000 }
23992 },
23993/* rolc.w ${Dsp-16-u8}[sb] */
23994 {
23995 { 0, 0, 0, 0 },
23996 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23997 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77aa00 }
23998 },
23999/* rolc.w ${Dsp-16-u16}[sb] */
24000 {
24001 { 0, 0, 0, 0 },
24002 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24003 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ae0000 }
24004 },
24005/* rolc.w ${Dsp-16-s8}[fb] */
24006 {
24007 { 0, 0, 0, 0 },
24008 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24009 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77ab00 }
24010 },
24011/* rolc.w ${Dsp-16-u16} */
24012 {
24013 { 0, 0, 0, 0 },
24014 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24015 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77af0000 }
24016 },
24017/* rolc.b $Dst16RnQI */
24018 {
24019 { 0, 0, 0, 0 },
24020 { { MNEM, ' ', OP (DST16RNQI), 0 } },
24021 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76a0 }
24022 },
24023/* rolc.b $Dst16AnQI */
24024 {
24025 { 0, 0, 0, 0 },
24026 { { MNEM, ' ', OP (DST16ANQI), 0 } },
24027 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76a4 }
24028 },
24029/* rolc.b [$Dst16An] */
24030 {
24031 { 0, 0, 0, 0 },
24032 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24033 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76a6 }
24034 },
24035/* rolc.b ${Dsp-16-u8}[$Dst16An] */
24036 {
24037 { 0, 0, 0, 0 },
24038 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24039 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76a800 }
24040 },
24041/* rolc.b ${Dsp-16-u16}[$Dst16An] */
24042 {
24043 { 0, 0, 0, 0 },
24044 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24045 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ac0000 }
24046 },
24047/* rolc.b ${Dsp-16-u8}[sb] */
24048 {
24049 { 0, 0, 0, 0 },
24050 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24051 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76aa00 }
24052 },
24053/* rolc.b ${Dsp-16-u16}[sb] */
24054 {
24055 { 0, 0, 0, 0 },
24056 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24057 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ae0000 }
24058 },
24059/* rolc.b ${Dsp-16-s8}[fb] */
24060 {
24061 { 0, 0, 0, 0 },
24062 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24063 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76ab00 }
24064 },
24065/* rolc.b ${Dsp-16-u16} */
24066 {
24067 { 0, 0, 0, 0 },
24068 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24069 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76af0000 }
24070 },
24071/* pusha [$Dst32AnUnprefixed] */
24072 {
24073 { 0, 0, 0, 0 },
24074 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24075 & ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI, { 0xb001 }
24076 },
24077/* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24078 {
24079 { 0, 0, 0, 0 },
24080 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24081 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xb20100 }
24082 },
24083/* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24084 {
24085 { 0, 0, 0, 0 },
24086 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24087 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xb4010000 }
24088 },
24089/* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24090 {
24091 { 0, 0, 0, 0 },
24092 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24093 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xb6010000 }
24094 },
24095/* pusha ${Dsp-16-u8}[sb] */
24096 {
24097 { 0, 0, 0, 0 },
24098 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24099 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xb28100 }
24100 },
24101/* pusha ${Dsp-16-u16}[sb] */
24102 {
24103 { 0, 0, 0, 0 },
24104 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24105 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xb4810000 }
24106 },
24107/* pusha ${Dsp-16-s8}[fb] */
24108 {
24109 { 0, 0, 0, 0 },
24110 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24111 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xb2c100 }
24112 },
24113/* pusha ${Dsp-16-s16}[fb] */
24114 {
24115 { 0, 0, 0, 0 },
24116 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24117 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xb4c10000 }
24118 },
24119/* pusha ${Dsp-16-u16} */
24120 {
24121 { 0, 0, 0, 0 },
24122 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24123 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xb6c10000 }
24124 },
24125/* pusha ${Dsp-16-u24} */
24126 {
24127 { 0, 0, 0, 0 },
24128 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24129 & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xb6810000 }
24130 },
24131/* pusha [$Dst16An] */
24132 {
24133 { 0, 0, 0, 0 },
24134 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24135 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0x7d96 }
24136 },
24137/* pusha ${Dsp-16-u8}[$Dst16An] */
24138 {
24139 { 0, 0, 0, 0 },
24140 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24141 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0x7d9800 }
24142 },
24143/* pusha ${Dsp-16-u16}[$Dst16An] */
24144 {
24145 { 0, 0, 0, 0 },
24146 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24147 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0x7d9c0000 }
24148 },
24149/* pusha ${Dsp-16-u8}[sb] */
24150 {
24151 { 0, 0, 0, 0 },
24152 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24153 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0x7d9a00 }
24154 },
24155/* pusha ${Dsp-16-u16}[sb] */
24156 {
24157 { 0, 0, 0, 0 },
24158 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24159 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0x7d9e0000 }
24160 },
24161/* pusha ${Dsp-16-s8}[fb] */
24162 {
24163 { 0, 0, 0, 0 },
24164 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24165 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0x7d9b00 }
24166 },
24167/* pusha ${Dsp-16-u16} */
24168 {
24169 { 0, 0, 0, 0 },
24170 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24171 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0x7d9f0000 }
24172 },
24173/* push.l $Dst32RnUnprefixedSI */
24174 {
24175 { 0, 0, 0, 0 },
24176 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
24177 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa801 }
24178 },
24179/* push.l $Dst32AnUnprefixedSI */
24180 {
24181 { 0, 0, 0, 0 },
24182 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
24183 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa081 }
24184 },
24185/* push.l [$Dst32AnUnprefixed] */
24186 {
24187 { 0, 0, 0, 0 },
24188 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24189 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa001 }
24190 },
24191/* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24192 {
24193 { 0, 0, 0, 0 },
24194 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24195 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa20100 }
24196 },
24197/* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24198 {
24199 { 0, 0, 0, 0 },
24200 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24201 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4010000 }
24202 },
24203/* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24204 {
24205 { 0, 0, 0, 0 },
24206 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24207 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6010000 }
24208 },
24209/* push.l ${Dsp-16-u8}[sb] */
24210 {
24211 { 0, 0, 0, 0 },
24212 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24213 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa28100 }
24214 },
24215/* push.l ${Dsp-16-u16}[sb] */
24216 {
24217 { 0, 0, 0, 0 },
24218 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24219 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4810000 }
24220 },
24221/* push.l ${Dsp-16-s8}[fb] */
24222 {
24223 { 0, 0, 0, 0 },
24224 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24225 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2c100 }
24226 },
24227/* push.l ${Dsp-16-s16}[fb] */
24228 {
24229 { 0, 0, 0, 0 },
24230 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24231 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4c10000 }
24232 },
24233/* push.l ${Dsp-16-u16} */
24234 {
24235 { 0, 0, 0, 0 },
24236 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24237 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6c10000 }
24238 },
24239/* push.l ${Dsp-16-u24} */
24240 {
24241 { 0, 0, 0, 0 },
24242 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24243 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6810000 }
24244 },
24245/* push.w${S} ${An16-push-S} */
24246 {
24247 { 0, 0, 0, 0 },
24248 { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } },
24249 & ifmt_push16_b_s_an_An16_push_S_derived, { 0xc2 }
24250 },
24251/* push.b${S} ${Rn16-push-S} */
24252 {
24253 { 0, 0, 0, 0 },
24254 { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } },
24255 & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x82 }
24256 },
24257/* push.w $Dst32RnUnprefixedHI */
24258 {
24259 { 0, 0, 0, 0 },
24260 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
24261 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90e }
24262 },
24263/* push.w $Dst32AnUnprefixedHI */
24264 {
24265 { 0, 0, 0, 0 },
24266 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
24267 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18e }
24268 },
24269/* push.w [$Dst32AnUnprefixed] */
24270 {
24271 { 0, 0, 0, 0 },
24272 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24273 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10e }
24274 },
24275/* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24276 {
24277 { 0, 0, 0, 0 },
24278 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24279 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30e00 }
24280 },
24281/* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24282 {
24283 { 0, 0, 0, 0 },
24284 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24285 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50e0000 }
24286 },
24287/* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24288 {
24289 { 0, 0, 0, 0 },
24290 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24291 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70e0000 }
24292 },
24293/* push.w ${Dsp-16-u8}[sb] */
24294 {
24295 { 0, 0, 0, 0 },
24296 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24297 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38e00 }
24298 },
24299/* push.w ${Dsp-16-u16}[sb] */
24300 {
24301 { 0, 0, 0, 0 },
24302 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24303 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58e0000 }
24304 },
24305/* push.w ${Dsp-16-s8}[fb] */
24306 {
24307 { 0, 0, 0, 0 },
24308 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24309 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ce00 }
24310 },
24311/* push.w ${Dsp-16-s16}[fb] */
24312 {
24313 { 0, 0, 0, 0 },
24314 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24315 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ce0000 }
24316 },
24317/* push.w ${Dsp-16-u16} */
24318 {
24319 { 0, 0, 0, 0 },
24320 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24321 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ce0000 }
24322 },
24323/* push.w ${Dsp-16-u24} */
24324 {
24325 { 0, 0, 0, 0 },
24326 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24327 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78e0000 }
24328 },
24329/* push.b $Dst32RnUnprefixedQI */
24330 {
24331 { 0, 0, 0, 0 },
24332 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
24333 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc80e }
24334 },
24335/* push.b $Dst32AnUnprefixedQI */
24336 {
24337 { 0, 0, 0, 0 },
24338 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
24339 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc08e }
24340 },
24341/* push.b [$Dst32AnUnprefixed] */
24342 {
24343 { 0, 0, 0, 0 },
24344 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24345 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc00e }
24346 },
24347/* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24348 {
24349 { 0, 0, 0, 0 },
24350 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24351 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20e00 }
24352 },
24353/* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24354 {
24355 { 0, 0, 0, 0 },
24356 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24357 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40e0000 }
24358 },
24359/* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24360 {
24361 { 0, 0, 0, 0 },
24362 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24363 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60e0000 }
24364 },
24365/* push.b ${Dsp-16-u8}[sb] */
24366 {
24367 { 0, 0, 0, 0 },
24368 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24369 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28e00 }
24370 },
24371/* push.b ${Dsp-16-u16}[sb] */
24372 {
24373 { 0, 0, 0, 0 },
24374 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24375 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48e0000 }
24376 },
24377/* push.b ${Dsp-16-s8}[fb] */
24378 {
24379 { 0, 0, 0, 0 },
24380 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24381 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ce00 }
24382 },
24383/* push.b ${Dsp-16-s16}[fb] */
24384 {
24385 { 0, 0, 0, 0 },
24386 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24387 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ce0000 }
24388 },
24389/* push.b ${Dsp-16-u16} */
24390 {
24391 { 0, 0, 0, 0 },
24392 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24393 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ce0000 }
24394 },
24395/* push.b ${Dsp-16-u24} */
24396 {
24397 { 0, 0, 0, 0 },
24398 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24399 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc68e0000 }
24400 },
c6552317 24401/* push.w${G} $Dst16RnHI */
49f58d10
JB		 24402 {
24403 { 0, 0, 0, 0 },
c6552317 24404 { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
49f58d10
JB		 24405 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7540 }
24406 },
c6552317 24407/* push.w${G} $Dst16AnHI */
49f58d10
JB		 24408 {
24409 { 0, 0, 0, 0 },
c6552317 24410 { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
49f58d10
JB		 24411 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7544 }
24412 },
c6552317 24413/* push.w${G} [$Dst16An] */
49f58d10
JB		 24414 {
24415 { 0, 0, 0, 0 },
c6552317 24416 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24417 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7546 }
24418 },
c6552317 24419/* push.w${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 24420 {
24421 { 0, 0, 0, 0 },
c6552317 24422 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24423 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x754800 }
24424 },
c6552317 24425/* push.w${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 24426 {
24427 { 0, 0, 0, 0 },
c6552317 24428 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24429 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x754c0000 }
24430 },
c6552317 24431/* push.w${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 24432 {
24433 { 0, 0, 0, 0 },
c6552317 24434 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24435 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x754a00 }
24436 },
c6552317 24437/* push.w${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 24438 {
24439 { 0, 0, 0, 0 },
c6552317 24440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24441 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x754e0000 }
24442 },
c6552317 24443/* push.w${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 24444 {
24445 { 0, 0, 0, 0 },
c6552317 24446 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 24447 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x754b00 }
24448 },
c6552317 24449/* push.w${G} ${Dsp-16-u16} */
49f58d10
JB		 24450 {
24451 { 0, 0, 0, 0 },
c6552317 24452 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 24453 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x754f0000 }
24454 },
c6552317 24455/* push.b${G} $Dst16RnQI */
49f58d10
JB		 24456 {
24457 { 0, 0, 0, 0 },
c6552317 24458 { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
49f58d10
JB		 24459 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7440 }
24460 },
c6552317 24461/* push.b${G} $Dst16AnQI */
49f58d10
JB		 24462 {
24463 { 0, 0, 0, 0 },
c6552317 24464 { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
49f58d10
JB		 24465 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7444 }
24466 },
c6552317 24467/* push.b${G} [$Dst16An] */
49f58d10
JB		 24468 {
24469 { 0, 0, 0, 0 },
c6552317 24470 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24471 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7446 }
24472 },
c6552317 24473/* push.b${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 24474 {
24475 { 0, 0, 0, 0 },
c6552317 24476 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24477 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x744800 }
24478 },
c6552317 24479/* push.b${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 24480 {
24481 { 0, 0, 0, 0 },
c6552317 24482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24483 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x744c0000 }
24484 },
c6552317 24485/* push.b${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 24486 {
24487 { 0, 0, 0, 0 },
c6552317 24488 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24489 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x744a00 }
24490 },
c6552317 24491/* push.b${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 24492 {
24493 { 0, 0, 0, 0 },
c6552317 24494 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24495 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x744e0000 }
24496 },
c6552317 24497/* push.b${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 24498 {
24499 { 0, 0, 0, 0 },
c6552317 24500 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 24501 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x744b00 }
24502 },
c6552317 24503/* push.b${G} ${Dsp-16-u16} */
49f58d10
JB		 24504 {
24505 { 0, 0, 0, 0 },
c6552317 24506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 24507 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x744f0000 }
24508 },
24509/* pop.w${S} ${An16-push-S} */
24510 {
24511 { 0, 0, 0, 0 },
24512 { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } },
24513 & ifmt_push16_b_s_an_An16_push_S_derived, { 0xd2 }
24514 },
24515/* pop.b${S} ${Rn16-push-S} */
24516 {
24517 { 0, 0, 0, 0 },
24518 { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } },
24519 & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x92 }
24520 },
24521/* pop.w $Dst32RnUnprefixedHI */
24522 {
24523 { 0, 0, 0, 0 },
24524 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
24525 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92f }
24526 },
24527/* pop.w $Dst32AnUnprefixedHI */
24528 {
24529 { 0, 0, 0, 0 },
24530 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
24531 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1af }
24532 },
24533/* pop.w [$Dst32AnUnprefixed] */
24534 {
24535 { 0, 0, 0, 0 },
24536 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24537 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12f }
24538 },
24539/* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24540 {
24541 { 0, 0, 0, 0 },
24542 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24543 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32f00 }
24544 },
24545/* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24546 {
24547 { 0, 0, 0, 0 },
24548 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24549 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52f0000 }
24550 },
24551/* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24552 {
24553 { 0, 0, 0, 0 },
24554 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24555 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72f0000 }
24556 },
24557/* pop.w ${Dsp-16-u8}[sb] */
24558 {
24559 { 0, 0, 0, 0 },
24560 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24561 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3af00 }
24562 },
24563/* pop.w ${Dsp-16-u16}[sb] */
24564 {
24565 { 0, 0, 0, 0 },
24566 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24567 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5af0000 }
24568 },
24569/* pop.w ${Dsp-16-s8}[fb] */
24570 {
24571 { 0, 0, 0, 0 },
24572 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24573 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ef00 }
24574 },
24575/* pop.w ${Dsp-16-s16}[fb] */
24576 {
24577 { 0, 0, 0, 0 },
24578 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24579 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ef0000 }
24580 },
24581/* pop.w ${Dsp-16-u16} */
24582 {
24583 { 0, 0, 0, 0 },
24584 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24585 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ef0000 }
24586 },
24587/* pop.w ${Dsp-16-u24} */
24588 {
24589 { 0, 0, 0, 0 },
24590 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24591 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7af0000 }
24592 },
24593/* pop.b $Dst32RnUnprefixedQI */
24594 {
24595 { 0, 0, 0, 0 },
24596 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
24597 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82f }
24598 },
24599/* pop.b $Dst32AnUnprefixedQI */
24600 {
24601 { 0, 0, 0, 0 },
24602 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
24603 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0af }
24604 },
24605/* pop.b [$Dst32AnUnprefixed] */
24606 {
24607 { 0, 0, 0, 0 },
24608 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24609 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02f }
24610 },
24611/* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24612 {
24613 { 0, 0, 0, 0 },
24614 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24615 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22f00 }
24616 },
24617/* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24618 {
24619 { 0, 0, 0, 0 },
24620 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24621 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42f0000 }
24622 },
24623/* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24624 {
24625 { 0, 0, 0, 0 },
24626 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24627 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62f0000 }
24628 },
24629/* pop.b ${Dsp-16-u8}[sb] */
24630 {
24631 { 0, 0, 0, 0 },
24632 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24633 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2af00 }
24634 },
24635/* pop.b ${Dsp-16-u16}[sb] */
24636 {
24637 { 0, 0, 0, 0 },
24638 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24639 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4af0000 }
24640 },
24641/* pop.b ${Dsp-16-s8}[fb] */
24642 {
24643 { 0, 0, 0, 0 },
24644 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24645 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ef00 }
24646 },
24647/* pop.b ${Dsp-16-s16}[fb] */
24648 {
24649 { 0, 0, 0, 0 },
24650 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24651 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ef0000 }
24652 },
24653/* pop.b ${Dsp-16-u16} */
24654 {
24655 { 0, 0, 0, 0 },
24656 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24657 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ef0000 }
24658 },
24659/* pop.b ${Dsp-16-u24} */
24660 {
24661 { 0, 0, 0, 0 },
24662 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24663 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6af0000 }
24664 },
5348b81e 24665/* pop.w${G} $Dst16RnHI */
49f58d10
JB		 24666 {
24667 { 0, 0, 0, 0 },
5348b81e 24668 { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
49f58d10
JB		 24669 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75d0 }
24670 },
5348b81e 24671/* pop.w${G} $Dst16AnHI */
49f58d10
JB		 24672 {
24673 { 0, 0, 0, 0 },
5348b81e 24674 { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
49f58d10
JB		 24675 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75d4 }
24676 },
5348b81e 24677/* pop.w${G} [$Dst16An] */
49f58d10
JB		 24678 {
24679 { 0, 0, 0, 0 },
5348b81e 24680 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24681 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75d6 }
24682 },
5348b81e 24683/* pop.w${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 24684 {
24685 { 0, 0, 0, 0 },
5348b81e 24686 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24687 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75d800 }
24688 },
5348b81e 24689/* pop.w${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 24690 {
24691 { 0, 0, 0, 0 },
5348b81e 24692 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24693 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75dc0000 }
24694 },
5348b81e 24695/* pop.w${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 24696 {
24697 { 0, 0, 0, 0 },
5348b81e 24698 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24699 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75da00 }
24700 },
5348b81e 24701/* pop.w${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 24702 {
24703 { 0, 0, 0, 0 },
5348b81e 24704 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24705 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75de0000 }
24706 },
5348b81e 24707/* pop.w${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 24708 {
24709 { 0, 0, 0, 0 },
5348b81e 24710 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 24711 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75db00 }
24712 },
5348b81e 24713/* pop.w${G} ${Dsp-16-u16} */
49f58d10
JB		 24714 {
24715 { 0, 0, 0, 0 },
5348b81e 24716 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 24717 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75df0000 }
24718 },
5348b81e 24719/* pop.b${G} $Dst16RnQI */
49f58d10
JB		 24720 {
24721 { 0, 0, 0, 0 },
5348b81e 24722 { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
49f58d10
JB		 24723 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74d0 }
24724 },
5348b81e 24725/* pop.b${G} $Dst16AnQI */
49f58d10
JB		 24726 {
24727 { 0, 0, 0, 0 },
5348b81e 24728 { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
49f58d10
JB		 24729 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74d4 }
24730 },
5348b81e 24731/* pop.b${G} [$Dst16An] */
49f58d10
JB		 24732 {
24733 { 0, 0, 0, 0 },
5348b81e 24734 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24735 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74d6 }
24736 },
5348b81e 24737/* pop.b${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 24738 {
24739 { 0, 0, 0, 0 },
5348b81e 24740 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24741 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74d800 }
24742 },
5348b81e 24743/* pop.b${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 24744 {
24745 { 0, 0, 0, 0 },
5348b81e 24746 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 24747 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74dc0000 }
24748 },
5348b81e 24749/* pop.b${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 24750 {
24751 { 0, 0, 0, 0 },
5348b81e 24752 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24753 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74da00 }
24754 },
5348b81e 24755/* pop.b${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 24756 {
24757 { 0, 0, 0, 0 },
5348b81e 24758 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 24759 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74de0000 }
24760 },
5348b81e 24761/* pop.b${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 24762 {
24763 { 0, 0, 0, 0 },
5348b81e 24764 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 24765 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74db00 }
24766 },
5348b81e 24767/* pop.b${G} ${Dsp-16-u16} */
49f58d10
JB		 24768 {
24769 { 0, 0, 0, 0 },
5348b81e 24770 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 24771 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74df0000 }
24772 },
5348b81e
DD		 24773/* or.b${S} ${SrcDst16-r0l-r0h-S-normal} */
24774 {
24775 { 0, 0, 0, 0 },
24776 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
24777 & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x18 }
24778 },
24779/* or.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
24780 {
24781 { 0, 0, 0, 0 },
24782 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
24783 & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1900 }
24784 },
24785/* or.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
24786 {
24787 { 0, 0, 0, 0 },
24788 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
24789 & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1a00 }
24790 },
24791/* or.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
24792 {
24793 { 0, 0, 0, 0 },
24794 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
24795 & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x1b0000 }
24796 },
49f58d10
JB		 24797/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
24798 {
24799 { 0, 0, 0, 0 },
24800 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24801 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990500 }
24802 },
24803/* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
24804 {
24805 { 0, 0, 0, 0 },
24806 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24807 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992500 }
24808 },
24809/* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
24810 {
24811 { 0, 0, 0, 0 },
24812 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24813 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993500 }
24814 },
24815/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
24816 {
24817 { 0, 0, 0, 0 },
24818 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24819 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918500 }
24820 },
24821/* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
24822 {
24823 { 0, 0, 0, 0 },
24824 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24825 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a500 }
24826 },
24827/* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
24828 {
24829 { 0, 0, 0, 0 },
24830 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24831 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b500 }
24832 },
24833/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
24834 {
24835 { 0, 0, 0, 0 },
24836 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24837 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910500 }
24838 },
24839/* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
24840 {
24841 { 0, 0, 0, 0 },
24842 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24843 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912500 }
24844 },
24845/* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
24846 {
24847 { 0, 0, 0, 0 },
24848 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24849 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913500 }
24850 },
24851/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24852 {
24853 { 0, 0, 0, 0 },
24854 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24855 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93050000 }
24856 },
24857/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24858 {
24859 { 0, 0, 0, 0 },
24860 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24861 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93250000 }
24862 },
24863/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24864 {
24865 { 0, 0, 0, 0 },
24866 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24867 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93350000 }
24868 },
24869/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24870 {
24871 { 0, 0, 0, 0 },
24872 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24873 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95050000 }
24874 },
24875/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24876 {
24877 { 0, 0, 0, 0 },
24878 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24879 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95250000 }
24880 },
24881/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24882 {
24883 { 0, 0, 0, 0 },
24884 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24885 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95350000 }
24886 },
24887/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24888 {
24889 { 0, 0, 0, 0 },
24890 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24891 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97050000 }
24892 },
24893/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24894 {
24895 { 0, 0, 0, 0 },
24896 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24897 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97250000 }
24898 },
24899/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24900 {
24901 { 0, 0, 0, 0 },
24902 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24903 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97350000 }
24904 },
24905/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
24906 {
24907 { 0, 0, 0, 0 },
24908 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24909 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93850000 }
24910 },
24911/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24912 {
24913 { 0, 0, 0, 0 },
24914 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24915 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a50000 }
24916 },
24917/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24918 {
24919 { 0, 0, 0, 0 },
24920 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24921 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b50000 }
24922 },
24923/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
24924 {
24925 { 0, 0, 0, 0 },
24926 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24927 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95850000 }
24928 },
24929/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24930 {
24931 { 0, 0, 0, 0 },
24932 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24933 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a50000 }
24934 },
24935/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24936 {
24937 { 0, 0, 0, 0 },
24938 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24939 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b50000 }
24940 },
24941/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
24942 {
24943 { 0, 0, 0, 0 },
24944 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24945 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c50000 }
24946 },
24947/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24948 {
24949 { 0, 0, 0, 0 },
24950 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24951 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e50000 }
24952 },
24953/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24954 {
24955 { 0, 0, 0, 0 },
24956 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24957 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f50000 }
24958 },
24959/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
24960 {
24961 { 0, 0, 0, 0 },
24962 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24963 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c50000 }
24964 },
24965/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
24966 {
24967 { 0, 0, 0, 0 },
24968 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24969 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e50000 }
24970 },
24971/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
24972 {
24973 { 0, 0, 0, 0 },
24974 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24975 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f50000 }
24976 },
24977/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
24978 {
24979 { 0, 0, 0, 0 },
24980 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
24981 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c50000 }
24982 },
24983/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24984 {
24985 { 0, 0, 0, 0 },
24986 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
24987 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e50000 }
24988 },
24989/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24990 {
24991 { 0, 0, 0, 0 },
24992 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
24993 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f50000 }
24994 },
24995/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
24996 {
24997 { 0, 0, 0, 0 },
24998 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
24999 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97850000 }
25000 },
25001/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
25002 {
25003 { 0, 0, 0, 0 },
25004 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25005 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a50000 }
25006 },
25007/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
25008 {
25009 { 0, 0, 0, 0 },
25010 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25011 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b50000 }
25012 },
25013/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25014 {
25015 { 0, 0, 0, 0 },
25016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25017 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9050000 }
25018 },
25019/* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
25020 {
25021 { 0, 0, 0, 0 },
25022 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25023 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9250000 }
25024 },
25025/* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
25026 {
25027 { 0, 0, 0, 0 },
25028 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25029 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9350000 }
25030 },
25031/* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
25032 {
25033 { 0, 0, 0, 0 },
25034 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25035 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9350000 }
25036 },
25037/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25038 {
25039 { 0, 0, 0, 0 },
25040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25041 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1850000 }
25042 },
25043/* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
25044 {
25045 { 0, 0, 0, 0 },
25046 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25047 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a50000 }
25048 },
25049/* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
25050 {
25051 { 0, 0, 0, 0 },
25052 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25053 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b50000 }
25054 },
25055/* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
25056 {
25057 { 0, 0, 0, 0 },
25058 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25059 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b50000 }
25060 },
25061/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25062 {
25063 { 0, 0, 0, 0 },
25064 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25065 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1050000 }
25066 },
25067/* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
25068 {
25069 { 0, 0, 0, 0 },
25070 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25071 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1250000 }
25072 },
25073/* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
25074 {
25075 { 0, 0, 0, 0 },
25076 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25077 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1350000 }
25078 },
25079/* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
25080 {
25081 { 0, 0, 0, 0 },
25082 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25083 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1350000 }
25084 },
25085/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25086 {
25087 { 0, 0, 0, 0 },
25088 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25089 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3050000 }
25090 },
25091/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25092 {
25093 { 0, 0, 0, 0 },
25094 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25095 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3250000 }
25096 },
25097/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25098 {
25099 { 0, 0, 0, 0 },
25100 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25101 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3350000 }
25102 },
25103/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
25104 {
25105 { 0, 0, 0, 0 },
25106 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25107 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3350000 }
25108 },
25109/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25110 {
25111 { 0, 0, 0, 0 },
25112 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25113 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5050000 }
25114 },
25115/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25116 {
25117 { 0, 0, 0, 0 },
25118 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25119 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5250000 }
25120 },
25121/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25122 {
25123 { 0, 0, 0, 0 },
25124 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25125 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5350000 }
25126 },
25127/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
25128 {
25129 { 0, 0, 0, 0 },
25130 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25131 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5350000 }
25132 },
25133/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25134 {
25135 { 0, 0, 0, 0 },
25136 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25137 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7050000 }
25138 },
25139/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25140 {
25141 { 0, 0, 0, 0 },
25142 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25143 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7250000 }
25144 },
25145/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25146 {
25147 { 0, 0, 0, 0 },
25148 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25149 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7350000 }
25150 },
25151/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
25152 {
25153 { 0, 0, 0, 0 },
25154 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25155 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7350000 }
25156 },
25157/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
25158 {
25159 { 0, 0, 0, 0 },
25160 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25161 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3850000 }
25162 },
25163/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
25164 {
25165 { 0, 0, 0, 0 },
25166 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25167 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a50000 }
25168 },
25169/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
25170 {
25171 { 0, 0, 0, 0 },
25172 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25173 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b50000 }
25174 },
25175/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
25176 {
25177 { 0, 0, 0, 0 },
25178 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25179 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b50000 }
25180 },
25181/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
25182 {
25183 { 0, 0, 0, 0 },
25184 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25185 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5850000 }
25186 },
25187/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
25188 {
25189 { 0, 0, 0, 0 },
25190 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25191 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a50000 }
25192 },
25193/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
25194 {
25195 { 0, 0, 0, 0 },
25196 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25197 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b50000 }
25198 },
25199/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
25200 {
25201 { 0, 0, 0, 0 },
25202 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25203 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b50000 }
25204 },
25205/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
25206 {
25207 { 0, 0, 0, 0 },
25208 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25209 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c50000 }
25210 },
25211/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
25212 {
25213 { 0, 0, 0, 0 },
25214 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25215 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e50000 }
25216 },
25217/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
25218 {
25219 { 0, 0, 0, 0 },
25220 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25221 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f50000 }
25222 },
25223/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
25224 {
25225 { 0, 0, 0, 0 },
25226 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25227 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f50000 }
25228 },
25229/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
25230 {
25231 { 0, 0, 0, 0 },
25232 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25233 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c50000 }
25234 },
25235/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
25236 {
25237 { 0, 0, 0, 0 },
25238 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25239 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e50000 }
25240 },
25241/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
25242 {
25243 { 0, 0, 0, 0 },
25244 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25245 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f50000 }
25246 },
25247/* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
25248 {
25249 { 0, 0, 0, 0 },
25250 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25251 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f50000 }
25252 },
25253/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
25254 {
25255 { 0, 0, 0, 0 },
25256 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
25257 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c50000 }
25258 },
25259/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
25260 {
25261 { 0, 0, 0, 0 },
25262 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25263 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e50000 }
25264 },
25265/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
25266 {
25267 { 0, 0, 0, 0 },
25268 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25269 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f50000 }
25270 },
25271/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
25272 {
25273 { 0, 0, 0, 0 },
25274 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
25275 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f50000 }
25276 },
25277/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
25278 {
25279 { 0, 0, 0, 0 },
25280 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
25281 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7850000 }
25282 },
25283/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
25284 {
25285 { 0, 0, 0, 0 },
25286 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25287 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a50000 }
25288 },
25289/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
25290 {
25291 { 0, 0, 0, 0 },
25292 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25293 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b50000 }
25294 },
25295/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
25296 {
25297 { 0, 0, 0, 0 },
25298 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
25299 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b50000 }
25300 },
25301/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25302 {
25303 { 0, 0, 0, 0 },
25304 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25305 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9050000 }
25306 },
25307/* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
25308 {
25309 { 0, 0, 0, 0 },
25310 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25311 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9250000 }
25312 },
25313/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25314 {
25315 { 0, 0, 0, 0 },
25316 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25317 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1850000 }
25318 },
25319/* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
25320 {
25321 { 0, 0, 0, 0 },
25322 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25323 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a50000 }
25324 },
25325/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25326 {
25327 { 0, 0, 0, 0 },
25328 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25329 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1050000 }
25330 },
25331/* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
25332 {
25333 { 0, 0, 0, 0 },
25334 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25335 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1250000 }
25336 },
25337/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
25338 {
25339 { 0, 0, 0, 0 },
25340 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25341 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3050000 }
25342 },
25343/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
25344 {
25345 { 0, 0, 0, 0 },
25346 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25347 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3250000 }
25348 },
25349/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
25350 {
25351 { 0, 0, 0, 0 },
25352 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25353 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5050000 }
25354 },
25355/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
25356 {
25357 { 0, 0, 0, 0 },
25358 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25359 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5250000 }
25360 },
25361/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
25362 {
25363 { 0, 0, 0, 0 },
25364 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25365 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7050000 }
25366 },
25367/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
25368 {
25369 { 0, 0, 0, 0 },
25370 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25371 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7250000 }
25372 },
25373/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
25374 {
25375 { 0, 0, 0, 0 },
25376 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
25377 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3850000 }
25378 },
25379/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
25380 {
25381 { 0, 0, 0, 0 },
25382 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
25383 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a50000 }
25384 },
25385/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
25386 {
25387 { 0, 0, 0, 0 },
25388 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
25389 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5850000 }
25390 },
25391/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
25392 {
25393 { 0, 0, 0, 0 },
25394 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
25395 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a50000 }
25396 },
25397/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
25398 {
25399 { 0, 0, 0, 0 },
25400 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
25401 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c50000 }
25402 },
25403/* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
25404 {
25405 { 0, 0, 0, 0 },
25406 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
25407 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e50000 }
25408 },
25409/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
25410 {
25411 { 0, 0, 0, 0 },
25412 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
25413 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c50000 }
25414 },
25415/* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
25416 {
25417 { 0, 0, 0, 0 },
25418 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
25419 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e50000 }
25420 },
25421/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
25422 {
25423 { 0, 0, 0, 0 },
25424 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
25425 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c50000 }
25426 },
25427/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
25428 {
25429 { 0, 0, 0, 0 },
25430 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
25431 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e50000 }
25432 },
25433/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
25434 {
25435 { 0, 0, 0, 0 },
25436 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
25437 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7850000 }
25438 },
25439/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
25440 {
25441 { 0, 0, 0, 0 },
25442 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
25443 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a50000 }
25444 },
25445/* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
25446 {
25447 { 0, 0, 0, 0 },
25448 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25449 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc905 }
25450 },
25451/* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
25452 {
25453 { 0, 0, 0, 0 },
25454 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25455 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8925 }
25456 },
25457/* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25458 {
25459 { 0, 0, 0, 0 },
25460 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25461 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8905 }
25462 },
25463/* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
25464 {
25465 { 0, 0, 0, 0 },
25466 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25467 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc185 }
25468 },
25469/* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
25470 {
25471 { 0, 0, 0, 0 },
25472 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25473 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a5 }
25474 },
25475/* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25476 {
25477 { 0, 0, 0, 0 },
25478 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25479 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8185 }
25480 },
25481/* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
25482 {
25483 { 0, 0, 0, 0 },
25484 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25485 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc105 }
25486 },
25487/* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
25488 {
25489 { 0, 0, 0, 0 },
25490 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25491 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8125 }
25492 },
25493/* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25494 {
25495 { 0, 0, 0, 0 },
25496 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25497 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8105 }
25498 },
25499/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
25500 {
25501 { 0, 0, 0, 0 },
25502 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25503 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30500 }
25504 },
25505/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
25506 {
25507 { 0, 0, 0, 0 },
25508 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25509 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832500 }
25510 },
25511/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
25512 {
25513 { 0, 0, 0, 0 },
25514 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25515 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830500 }
25516 },
25517/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
25518 {
25519 { 0, 0, 0, 0 },
25520 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25521 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5050000 }
25522 },
25523/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
25524 {
25525 { 0, 0, 0, 0 },
25526 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25527 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85250000 }
25528 },
25529/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
25530 {
25531 { 0, 0, 0, 0 },
25532 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25533 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85050000 }
25534 },
25535/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
25536 {
25537 { 0, 0, 0, 0 },
25538 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25539 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7050000 }
25540 },
25541/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
25542 {
25543 { 0, 0, 0, 0 },
25544 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25545 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87250000 }
25546 },
25547/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
25548 {
25549 { 0, 0, 0, 0 },
25550 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25551 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87050000 }
25552 },
25553/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
25554 {
25555 { 0, 0, 0, 0 },
25556 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25557 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38500 }
25558 },
25559/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
25560 {
25561 { 0, 0, 0, 0 },
25562 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25563 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a500 }
25564 },
25565/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
25566 {
25567 { 0, 0, 0, 0 },
25568 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25569 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838500 }
25570 },
25571/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
25572 {
25573 { 0, 0, 0, 0 },
25574 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25575 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5850000 }
25576 },
25577/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
25578 {
25579 { 0, 0, 0, 0 },
25580 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25581 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a50000 }
25582 },
25583/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
25584 {
25585 { 0, 0, 0, 0 },
25586 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25587 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85850000 }
25588 },
25589/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
25590 {
25591 { 0, 0, 0, 0 },
25592 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25593 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c500 }
25594 },
25595/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
25596 {
25597 { 0, 0, 0, 0 },
25598 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25599 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e500 }
25600 },
25601/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
25602 {
25603 { 0, 0, 0, 0 },
25604 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25605 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c500 }
25606 },
25607/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
25608 {
25609 { 0, 0, 0, 0 },
25610 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25611 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c50000 }
25612 },
25613/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
25614 {
25615 { 0, 0, 0, 0 },
25616 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25617 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e50000 }
25618 },
25619/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
25620 {
25621 { 0, 0, 0, 0 },
25622 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25623 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c50000 }
25624 },
25625/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
25626 {
25627 { 0, 0, 0, 0 },
25628 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
25629 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c50000 }
25630 },
25631/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
25632 {
25633 { 0, 0, 0, 0 },
25634 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
25635 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e50000 }
25636 },
25637/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
25638 {
25639 { 0, 0, 0, 0 },
25640 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
25641 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c50000 }
25642 },
25643/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
25644 {
25645 { 0, 0, 0, 0 },
25646 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
25647 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7850000 }
25648 },
25649/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
25650 {
25651 { 0, 0, 0, 0 },
25652 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
25653 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a50000 }
25654 },
25655/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
25656 {
25657 { 0, 0, 0, 0 },
25658 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
25659 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87850000 }
25660 },
25661/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
25662 {
25663 { 0, 0, 0, 0 },
25664 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25665 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980500 }
25666 },
25667/* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
25668 {
25669 { 0, 0, 0, 0 },
25670 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25671 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982500 }
25672 },
25673/* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
25674 {
25675 { 0, 0, 0, 0 },
25676 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25677 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983500 }
25678 },
25679/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
25680 {
25681 { 0, 0, 0, 0 },
25682 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25683 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908500 }
25684 },
25685/* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
25686 {
25687 { 0, 0, 0, 0 },
25688 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25689 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a500 }
25690 },
25691/* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
25692 {
25693 { 0, 0, 0, 0 },
25694 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25695 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b500 }
25696 },
25697/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25698 {
25699 { 0, 0, 0, 0 },
25700 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25701 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900500 }
25702 },
25703/* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
25704 {
25705 { 0, 0, 0, 0 },
25706 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25707 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902500 }
25708 },
25709/* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
25710 {
25711 { 0, 0, 0, 0 },
25712 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25713 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903500 }
25714 },
25715/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25716 {
25717 { 0, 0, 0, 0 },
25718 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25719 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92050000 }
25720 },
25721/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25722 {
25723 { 0, 0, 0, 0 },
25724 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25725 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92250000 }
25726 },
25727/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25728 {
25729 { 0, 0, 0, 0 },
25730 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25731 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92350000 }
25732 },
25733/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25734 {
25735 { 0, 0, 0, 0 },
25736 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25737 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94050000 }
25738 },
25739/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25740 {
25741 { 0, 0, 0, 0 },
25742 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25743 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94250000 }
25744 },
25745/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25746 {
25747 { 0, 0, 0, 0 },
25748 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25749 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94350000 }
25750 },
25751/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25752 {
25753 { 0, 0, 0, 0 },
25754 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25755 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96050000 }
25756 },
25757/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25758 {
25759 { 0, 0, 0, 0 },
25760 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25761 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96250000 }
25762 },
25763/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25764 {
25765 { 0, 0, 0, 0 },
25766 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25767 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96350000 }
25768 },
25769/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
25770 {
25771 { 0, 0, 0, 0 },
25772 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25773 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92850000 }
25774 },
25775/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
25776 {
25777 { 0, 0, 0, 0 },
25778 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25779 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a50000 }
25780 },
25781/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
25782 {
25783 { 0, 0, 0, 0 },
25784 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25785 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b50000 }
25786 },
25787/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
25788 {
25789 { 0, 0, 0, 0 },
25790 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25791 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94850000 }
25792 },
25793/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
25794 {
25795 { 0, 0, 0, 0 },
25796 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25797 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a50000 }
25798 },
25799/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
25800 {
25801 { 0, 0, 0, 0 },
25802 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25803 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b50000 }
25804 },
25805/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
25806 {
25807 { 0, 0, 0, 0 },
25808 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25809 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c50000 }
25810 },
25811/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
25812 {
25813 { 0, 0, 0, 0 },
25814 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25815 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e50000 }
25816 },
25817/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
25818 {
25819 { 0, 0, 0, 0 },
25820 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25821 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f50000 }
25822 },
25823/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
25824 {
25825 { 0, 0, 0, 0 },
25826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25827 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c50000 }
25828 },
25829/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
25830 {
25831 { 0, 0, 0, 0 },
25832 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25833 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e50000 }
25834 },
25835/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
25836 {
25837 { 0, 0, 0, 0 },
25838 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25839 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f50000 }
25840 },
25841/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
25842 {
25843 { 0, 0, 0, 0 },
25844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
25845 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c50000 }
25846 },
25847/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
25848 {
25849 { 0, 0, 0, 0 },
25850 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
25851 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e50000 }
25852 },
25853/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
25854 {
25855 { 0, 0, 0, 0 },
25856 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
25857 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f50000 }
25858 },
25859/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
25860 {
25861 { 0, 0, 0, 0 },
25862 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
25863 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96850000 }
25864 },
25865/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
25866 {
25867 { 0, 0, 0, 0 },
25868 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25869 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a50000 }
25870 },
25871/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
25872 {
25873 { 0, 0, 0, 0 },
25874 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25875 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b50000 }
25876 },
25877/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
25878 {
25879 { 0, 0, 0, 0 },
25880 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25881 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8050000 }
25882 },
25883/* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
25884 {
25885 { 0, 0, 0, 0 },
25886 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25887 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8250000 }
25888 },
25889/* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
25890 {
25891 { 0, 0, 0, 0 },
25892 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25893 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8350000 }
25894 },
25895/* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
25896 {
25897 { 0, 0, 0, 0 },
25898 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25899 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8350000 }
25900 },
25901/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
25902 {
25903 { 0, 0, 0, 0 },
25904 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25905 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0850000 }
25906 },
25907/* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
25908 {
25909 { 0, 0, 0, 0 },
25910 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25911 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a50000 }
25912 },
25913/* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
25914 {
25915 { 0, 0, 0, 0 },
25916 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25917 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b50000 }
25918 },
25919/* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
25920 {
25921 { 0, 0, 0, 0 },
25922 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25923 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b50000 }
25924 },
25925/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25926 {
25927 { 0, 0, 0, 0 },
25928 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25929 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0050000 }
25930 },
25931/* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
25932 {
25933 { 0, 0, 0, 0 },
25934 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25935 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0250000 }
25936 },
25937/* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
25938 {
25939 { 0, 0, 0, 0 },
25940 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25941 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0350000 }
25942 },
25943/* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
25944 {
25945 { 0, 0, 0, 0 },
25946 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25947 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0350000 }
25948 },
25949/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25950 {
25951 { 0, 0, 0, 0 },
25952 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25953 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2050000 }
25954 },
25955/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25956 {
25957 { 0, 0, 0, 0 },
25958 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25959 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2250000 }
25960 },
25961/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25962 {
25963 { 0, 0, 0, 0 },
25964 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25965 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2350000 }
25966 },
25967/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
25968 {
25969 { 0, 0, 0, 0 },
25970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25971 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2350000 }
25972 },
25973/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25974 {
25975 { 0, 0, 0, 0 },
25976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25977 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4050000 }
25978 },
25979/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25980 {
25981 { 0, 0, 0, 0 },
25982 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25983 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4250000 }
25984 },
25985/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25986 {
25987 { 0, 0, 0, 0 },
25988 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25989 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4350000 }
25990 },
25991/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
25992 {
25993 { 0, 0, 0, 0 },
25994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25995 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4350000 }
25996 },
25997/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25998 {
25999 { 0, 0, 0, 0 },
26000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26001 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6050000 }
26002 },
26003/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26004 {
26005 { 0, 0, 0, 0 },
26006 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26007 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6250000 }
26008 },
26009/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26010 {
26011 { 0, 0, 0, 0 },
26012 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26013 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6350000 }
26014 },
26015/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
26016 {
26017 { 0, 0, 0, 0 },
26018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26019 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6350000 }
26020 },
26021/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
26022 {
26023 { 0, 0, 0, 0 },
26024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26025 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2850000 }
26026 },
26027/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26028 {
26029 { 0, 0, 0, 0 },
26030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26031 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a50000 }
26032 },
26033/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
26034 {
26035 { 0, 0, 0, 0 },
26036 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26037 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b50000 }
26038 },
26039/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26040 {
26041 { 0, 0, 0, 0 },
26042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26043 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b50000 }
26044 },
26045/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
26046 {
26047 { 0, 0, 0, 0 },
26048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26049 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4850000 }
26050 },
26051/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26052 {
26053 { 0, 0, 0, 0 },
26054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26055 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a50000 }
26056 },
26057/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
26058 {
26059 { 0, 0, 0, 0 },
26060 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26061 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b50000 }
26062 },
26063/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26064 {
26065 { 0, 0, 0, 0 },
26066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26067 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b50000 }
26068 },
26069/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
26070 {
26071 { 0, 0, 0, 0 },
26072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26073 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c50000 }
26074 },
26075/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26076 {
26077 { 0, 0, 0, 0 },
26078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26079 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e50000 }
26080 },
26081/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
26082 {
26083 { 0, 0, 0, 0 },
26084 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26085 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f50000 }
26086 },
26087/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26088 {
26089 { 0, 0, 0, 0 },
26090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26091 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f50000 }
26092 },
26093/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
26094 {
26095 { 0, 0, 0, 0 },
26096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26097 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c50000 }
26098 },
26099/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
26100 {
26101 { 0, 0, 0, 0 },
26102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26103 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e50000 }
26104 },
26105/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
26106 {
26107 { 0, 0, 0, 0 },
26108 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26109 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f50000 }
26110 },
26111/* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
26112 {
26113 { 0, 0, 0, 0 },
26114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26115 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f50000 }
26116 },
26117/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
26118 {
26119 { 0, 0, 0, 0 },
26120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
26121 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c50000 }
26122 },
26123/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26124 {
26125 { 0, 0, 0, 0 },
26126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
26127 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e50000 }
26128 },
26129/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
26130 {
26131 { 0, 0, 0, 0 },
26132 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
26133 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f50000 }
26134 },
26135/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
26136 {
26137 { 0, 0, 0, 0 },
26138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
26139 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f50000 }
26140 },
26141/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
26142 {
26143 { 0, 0, 0, 0 },
26144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
26145 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6850000 }
26146 },
26147/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
26148 {
26149 { 0, 0, 0, 0 },
26150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
26151 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a50000 }
26152 },
26153/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
26154 {
26155 { 0, 0, 0, 0 },
26156 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
26157 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b50000 }
26158 },
26159/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
26160 {
26161 { 0, 0, 0, 0 },
26162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
26163 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b50000 }
26164 },
26165/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
26166 {
26167 { 0, 0, 0, 0 },
26168 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26169 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8050000 }
26170 },
26171/* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
26172 {
26173 { 0, 0, 0, 0 },
26174 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26175 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8250000 }
26176 },
26177/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
26178 {
26179 { 0, 0, 0, 0 },
26180 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26181 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0850000 }
26182 },
26183/* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
26184 {
26185 { 0, 0, 0, 0 },
26186 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26187 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a50000 }
26188 },
26189/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26190 {
26191 { 0, 0, 0, 0 },
26192 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26193 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0050000 }
26194 },
26195/* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
26196 {
26197 { 0, 0, 0, 0 },
26198 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26199 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0250000 }
26200 },
26201/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
26202 {
26203 { 0, 0, 0, 0 },
26204 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26205 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2050000 }
26206 },
26207/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
26208 {
26209 { 0, 0, 0, 0 },
26210 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26211 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2250000 }
26212 },
26213/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
26214 {
26215 { 0, 0, 0, 0 },
26216 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26217 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4050000 }
26218 },
26219/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
26220 {
26221 { 0, 0, 0, 0 },
26222 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26223 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4250000 }
26224 },
26225/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
26226 {
26227 { 0, 0, 0, 0 },
26228 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26229 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6050000 }
26230 },
26231/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
26232 {
26233 { 0, 0, 0, 0 },
26234 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26235 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6250000 }
26236 },
26237/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
26238 {
26239 { 0, 0, 0, 0 },
26240 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
26241 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2850000 }
26242 },
26243/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
26244 {
26245 { 0, 0, 0, 0 },
26246 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
26247 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a50000 }
26248 },
26249/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
26250 {
26251 { 0, 0, 0, 0 },
26252 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
26253 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4850000 }
26254 },
26255/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
26256 {
26257 { 0, 0, 0, 0 },
26258 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
26259 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a50000 }
26260 },
26261/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
26262 {
26263 { 0, 0, 0, 0 },
26264 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
26265 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c50000 }
26266 },
26267/* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
26268 {
26269 { 0, 0, 0, 0 },
26270 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
26271 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e50000 }
26272 },
26273/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
26274 {
26275 { 0, 0, 0, 0 },
26276 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
26277 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c50000 }
26278 },
26279/* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
26280 {
26281 { 0, 0, 0, 0 },
26282 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
26283 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e50000 }
26284 },
26285/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
26286 {
26287 { 0, 0, 0, 0 },
26288 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
26289 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c50000 }
26290 },
26291/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
26292 {
26293 { 0, 0, 0, 0 },
26294 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
26295 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e50000 }
26296 },
26297/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
26298 {
26299 { 0, 0, 0, 0 },
26300 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
26301 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6850000 }
26302 },
26303/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
26304 {
26305 { 0, 0, 0, 0 },
26306 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
26307 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a50000 }
26308 },
26309/* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
26310 {
26311 { 0, 0, 0, 0 },
26312 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26313 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc805 }
26314 },
26315/* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
26316 {
26317 { 0, 0, 0, 0 },
26318 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26319 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8825 }
26320 },
26321/* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
26322 {
26323 { 0, 0, 0, 0 },
26324 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26325 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8805 }
26326 },
26327/* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
26328 {
26329 { 0, 0, 0, 0 },
26330 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26331 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc085 }
26332 },
26333/* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
26334 {
26335 { 0, 0, 0, 0 },
26336 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26337 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a5 }
26338 },
26339/* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
26340 {
26341 { 0, 0, 0, 0 },
26342 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26343 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8085 }
26344 },
26345/* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
26346 {
26347 { 0, 0, 0, 0 },
26348 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26349 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc005 }
26350 },
26351/* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
26352 {
26353 { 0, 0, 0, 0 },
26354 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26355 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8025 }
26356 },
26357/* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26358 {
26359 { 0, 0, 0, 0 },
26360 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26361 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8005 }
26362 },
26363/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
26364 {
26365 { 0, 0, 0, 0 },
26366 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26367 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20500 }
26368 },
26369/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
26370 {
26371 { 0, 0, 0, 0 },
26372 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26373 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822500 }
26374 },
26375/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26376 {
26377 { 0, 0, 0, 0 },
26378 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26379 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820500 }
26380 },
26381/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
26382 {
26383 { 0, 0, 0, 0 },
26384 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26385 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4050000 }
26386 },
26387/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
26388 {
26389 { 0, 0, 0, 0 },
26390 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26391 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84250000 }
26392 },
26393/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26394 {
26395 { 0, 0, 0, 0 },
26396 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26397 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84050000 }
26398 },
26399/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
26400 {
26401 { 0, 0, 0, 0 },
26402 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26403 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6050000 }
26404 },
26405/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
26406 {
26407 { 0, 0, 0, 0 },
26408 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26409 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86250000 }
26410 },
26411/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26412 {
26413 { 0, 0, 0, 0 },
26414 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26415 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86050000 }
26416 },
26417/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
26418 {
26419 { 0, 0, 0, 0 },
26420 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26421 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28500 }
26422 },
26423/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
26424 {
26425 { 0, 0, 0, 0 },
26426 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26427 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a500 }
26428 },
26429/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
26430 {
26431 { 0, 0, 0, 0 },
26432 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26433 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828500 }
26434 },
26435/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
26436 {
26437 { 0, 0, 0, 0 },
26438 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26439 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4850000 }
26440 },
26441/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
26442 {
26443 { 0, 0, 0, 0 },
26444 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26445 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a50000 }
26446 },
26447/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
26448 {
26449 { 0, 0, 0, 0 },
26450 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26451 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84850000 }
26452 },
26453/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
26454 {
26455 { 0, 0, 0, 0 },
26456 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26457 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c500 }
26458 },
26459/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
26460 {
26461 { 0, 0, 0, 0 },
26462 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26463 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e500 }
26464 },
26465/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
26466 {
26467 { 0, 0, 0, 0 },
26468 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26469 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c500 }
26470 },
26471/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
26472 {
26473 { 0, 0, 0, 0 },
26474 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26475 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c50000 }
26476 },
26477/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
26478 {
26479 { 0, 0, 0, 0 },
26480 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26481 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e50000 }
26482 },
26483/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
26484 {
26485 { 0, 0, 0, 0 },
26486 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26487 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c50000 }
26488 },
26489/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
26490 {
26491 { 0, 0, 0, 0 },
26492 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
26493 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c50000 }
26494 },
26495/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
26496 {
26497 { 0, 0, 0, 0 },
26498 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
26499 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e50000 }
26500 },
26501/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
26502 {
26503 { 0, 0, 0, 0 },
26504 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
26505 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c50000 }
26506 },
26507/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
26508 {
26509 { 0, 0, 0, 0 },
26510 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
26511 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6850000 }
26512 },
26513/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
26514 {
26515 { 0, 0, 0, 0 },
26516 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
26517 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a50000 }
26518 },
26519/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
26520 {
26521 { 0, 0, 0, 0 },
26522 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
26523 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86850000 }
26524 },
26525/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
26526 {
26527 { 0, 0, 0, 0 },
26528 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26529 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x998000 }
26530 },
26531/* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
26532 {
26533 { 0, 0, 0, 0 },
26534 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
26535 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x99a000 }
26536 },
26537/* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
26538 {
26539 { 0, 0, 0, 0 },
26540 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
26541 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x99b000 }
26542 },
26543/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
26544 {
26545 { 0, 0, 0, 0 },
26546 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26547 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x998400 }
26548 },
26549/* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
26550 {
26551 { 0, 0, 0, 0 },
26552 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
26553 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x99a400 }
26554 },
26555/* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
26556 {
26557 { 0, 0, 0, 0 },
26558 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
26559 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x99b400 }
26560 },
26561/* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
26562 {
26563 { 0, 0, 0, 0 },
26564 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26565 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x998600 }
26566 },
26567/* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
26568 {
26569 { 0, 0, 0, 0 },
26570 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26571 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x99a600 }
26572 },
26573/* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
26574 {
26575 { 0, 0, 0, 0 },
26576 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26577 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x99b600 }
26578 },
26579/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
26580 {
26581 { 0, 0, 0, 0 },
26582 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26583 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x99880000 }
26584 },
26585/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
26586 {
26587 { 0, 0, 0, 0 },
26588 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26589 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x99a80000 }
26590 },
26591/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
26592 {
26593 { 0, 0, 0, 0 },
26594 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26595 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x99b80000 }
26596 },
26597/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
26598 {
26599 { 0, 0, 0, 0 },
26600 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26601 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x998c0000 }
26602 },
26603/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
26604 {
26605 { 0, 0, 0, 0 },
26606 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26607 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x99ac0000 }
26608 },
26609/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
26610 {
26611 { 0, 0, 0, 0 },
26612 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26613 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x99bc0000 }
26614 },
26615/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
26616 {
26617 { 0, 0, 0, 0 },
26618 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26619 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x998a0000 }
26620 },
26621/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26622 {
26623 { 0, 0, 0, 0 },
26624 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26625 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99aa0000 }
26626 },
26627/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26628 {
26629 { 0, 0, 0, 0 },
26630 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26631 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99ba0000 }
26632 },
26633/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
26634 {
26635 { 0, 0, 0, 0 },
26636 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26637 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x998e0000 }
26638 },
26639/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26640 {
26641 { 0, 0, 0, 0 },
26642 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26643 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99ae0000 }
26644 },
26645/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26646 {
26647 { 0, 0, 0, 0 },
26648 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26649 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99be0000 }
26650 },
26651/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
26652 {
26653 { 0, 0, 0, 0 },
26654 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26655 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x998b0000 }
26656 },
26657/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26658 {
26659 { 0, 0, 0, 0 },
26660 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26661 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99ab0000 }
26662 },
26663/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26664 {
26665 { 0, 0, 0, 0 },
26666 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26667 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99bb0000 }
26668 },
26669/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
26670 {
26671 { 0, 0, 0, 0 },
26672 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
26673 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x998f0000 }
26674 },
26675/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26676 {
26677 { 0, 0, 0, 0 },
26678 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26679 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x99af0000 }
26680 },
26681/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26682 {
26683 { 0, 0, 0, 0 },
26684 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26685 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x99bf0000 }
26686 },
26687/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
26688 {
26689 { 0, 0, 0, 0 },
26690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26691 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x99c00000 }
26692 },
26693/* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
26694 {
26695 { 0, 0, 0, 0 },
26696 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
26697 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x99e00000 }
26698 },
26699/* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
26700 {
26701 { 0, 0, 0, 0 },
26702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
26703 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x99f00000 }
26704 },
26705/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
26706 {
26707 { 0, 0, 0, 0 },
26708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26709 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x99c40000 }
26710 },
26711/* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
26712 {
26713 { 0, 0, 0, 0 },
26714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
26715 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x99e40000 }
26716 },
26717/* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
26718 {
26719 { 0, 0, 0, 0 },
26720 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
26721 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x99f40000 }
26722 },
26723/* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
26724 {
26725 { 0, 0, 0, 0 },
26726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26727 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x99c60000 }
26728 },
26729/* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
26730 {
26731 { 0, 0, 0, 0 },
26732 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26733 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x99e60000 }
26734 },
26735/* or.w${G} ${Dsp-16-u16},[$Dst16An] */
26736 {
26737 { 0, 0, 0, 0 },
26738 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
26739 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x99f60000 }
26740 },
26741/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
26742 {
26743 { 0, 0, 0, 0 },
26744 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26745 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x99c80000 }
26746 },
26747/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
26748 {
26749 { 0, 0, 0, 0 },
26750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26751 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x99e80000 }
26752 },
26753/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
26754 {
26755 { 0, 0, 0, 0 },
26756 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26757 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x99f80000 }
26758 },
26759/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
26760 {
26761 { 0, 0, 0, 0 },
26762 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26763 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x99cc0000 }
26764 },
26765/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
26766 {
26767 { 0, 0, 0, 0 },
26768 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26769 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x99ec0000 }
26770 },
26771/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
26772 {
26773 { 0, 0, 0, 0 },
26774 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26775 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x99fc0000 }
26776 },
26777/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
26778 {
26779 { 0, 0, 0, 0 },
26780 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26781 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ca0000 }
26782 },
26783/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26784 {
26785 { 0, 0, 0, 0 },
26786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26787 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ea0000 }
26788 },
26789/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26790 {
26791 { 0, 0, 0, 0 },
26792 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26793 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x99fa0000 }
26794 },
26795/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
26796 {
26797 { 0, 0, 0, 0 },
26798 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26799 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ce0000 }
26800 },
26801/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26802 {
26803 { 0, 0, 0, 0 },
26804 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26805 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ee0000 }
26806 },
26807/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26808 {
26809 { 0, 0, 0, 0 },
26810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26811 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x99fe0000 }
26812 },
26813/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
26814 {
26815 { 0, 0, 0, 0 },
26816 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26817 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x99cb0000 }
26818 },
26819/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26820 {
26821 { 0, 0, 0, 0 },
26822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26823 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x99eb0000 }
26824 },
26825/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26826 {
26827 { 0, 0, 0, 0 },
26828 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26829 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x99fb0000 }
26830 },
26831/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
26832 {
26833 { 0, 0, 0, 0 },
26834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
26835 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x99cf0000 }
26836 },
26837/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26838 {
26839 { 0, 0, 0, 0 },
26840 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
26841 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x99ef0000 }
26842 },
26843/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
26844 {
26845 { 0, 0, 0, 0 },
26846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
26847 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x99ff0000 }
26848 },
26849/* or.w${G} $Src16RnHI,$Dst16RnHI */
26850 {
26851 { 0, 0, 0, 0 },
26852 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
26853 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9900 }
26854 },
26855/* or.w${G} $Src16AnHI,$Dst16RnHI */
26856 {
26857 { 0, 0, 0, 0 },
26858 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
26859 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9940 }
26860 },
26861/* or.w${G} [$Src16An],$Dst16RnHI */
26862 {
26863 { 0, 0, 0, 0 },
26864 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26865 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9960 }
26866 },
26867/* or.w${G} $Src16RnHI,$Dst16AnHI */
26868 {
26869 { 0, 0, 0, 0 },
26870 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
26871 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9904 }
26872 },
26873/* or.w${G} $Src16AnHI,$Dst16AnHI */
26874 {
26875 { 0, 0, 0, 0 },
26876 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
26877 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9944 }
26878 },
26879/* or.w${G} [$Src16An],$Dst16AnHI */
26880 {
26881 { 0, 0, 0, 0 },
26882 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26883 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9964 }
26884 },
26885/* or.w${G} $Src16RnHI,[$Dst16An] */
26886 {
26887 { 0, 0, 0, 0 },
26888 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
26889 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9906 }
26890 },
26891/* or.w${G} $Src16AnHI,[$Dst16An] */
26892 {
26893 { 0, 0, 0, 0 },
26894 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
26895 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9946 }
26896 },
26897/* or.w${G} [$Src16An],[$Dst16An] */
26898 {
26899 { 0, 0, 0, 0 },
26900 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26901 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9966 }
26902 },
26903/* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
26904 {
26905 { 0, 0, 0, 0 },
26906 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26907 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x990800 }
26908 },
26909/* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
26910 {
26911 { 0, 0, 0, 0 },
26912 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26913 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x994800 }
26914 },
26915/* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
26916 {
26917 { 0, 0, 0, 0 },
26918 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26919 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x996800 }
26920 },
26921/* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
26922 {
26923 { 0, 0, 0, 0 },
26924 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26925 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x990c0000 }
26926 },
26927/* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
26928 {
26929 { 0, 0, 0, 0 },
26930 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26931 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x994c0000 }
26932 },
26933/* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
26934 {
26935 { 0, 0, 0, 0 },
26936 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26937 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x996c0000 }
26938 },
26939/* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
26940 {
26941 { 0, 0, 0, 0 },
26942 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26943 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x990a00 }
26944 },
26945/* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
26946 {
26947 { 0, 0, 0, 0 },
26948 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26949 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x994a00 }
26950 },
26951/* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
26952 {
26953 { 0, 0, 0, 0 },
26954 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26955 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x996a00 }
26956 },
26957/* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
26958 {
26959 { 0, 0, 0, 0 },
26960 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26961 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x990e0000 }
26962 },
26963/* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
26964 {
26965 { 0, 0, 0, 0 },
26966 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26967 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x994e0000 }
26968 },
26969/* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
26970 {
26971 { 0, 0, 0, 0 },
26972 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26973 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x996e0000 }
26974 },
26975/* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
26976 {
26977 { 0, 0, 0, 0 },
26978 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26979 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x990b00 }
26980 },
26981/* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
26982 {
26983 { 0, 0, 0, 0 },
26984 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26985 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x994b00 }
26986 },
26987/* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
26988 {
26989 { 0, 0, 0, 0 },
26990 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26991 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x996b00 }
26992 },
26993/* or.w${G} $Src16RnHI,${Dsp-16-u16} */
26994 {
26995 { 0, 0, 0, 0 },
26996 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
26997 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x990f0000 }
26998 },
26999/* or.w${G} $Src16AnHI,${Dsp-16-u16} */
27000 {
27001 { 0, 0, 0, 0 },
27002 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
27003 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x994f0000 }
27004 },
27005/* or.w${G} [$Src16An],${Dsp-16-u16} */
27006 {
27007 { 0, 0, 0, 0 },
27008 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
27009 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x996f0000 }
27010 },
27011/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
27012 {
27013 { 0, 0, 0, 0 },
27014 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
27015 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x988000 }
27016 },
27017/* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
27018 {
27019 { 0, 0, 0, 0 },
27020 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
27021 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x98a000 }
27022 },
27023/* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
27024 {
27025 { 0, 0, 0, 0 },
27026 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
27027 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x98b000 }
27028 },
27029/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
27030 {
27031 { 0, 0, 0, 0 },
27032 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
27033 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x988400 }
27034 },
27035/* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
27036 {
27037 { 0, 0, 0, 0 },
27038 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
27039 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x98a400 }
27040 },
27041/* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
27042 {
27043 { 0, 0, 0, 0 },
27044 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
27045 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x98b400 }
27046 },
27047/* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
27048 {
27049 { 0, 0, 0, 0 },
27050 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27051 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x988600 }
27052 },
27053/* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
27054 {
27055 { 0, 0, 0, 0 },
27056 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
27057 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x98a600 }
27058 },
27059/* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
27060 {
27061 { 0, 0, 0, 0 },
27062 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
27063 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x98b600 }
27064 },
27065/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
27066 {
27067 { 0, 0, 0, 0 },
27068 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
27069 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x98880000 }
27070 },
27071/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
27072 {
27073 { 0, 0, 0, 0 },
27074 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
27075 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x98a80000 }
27076 },
27077/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
27078 {
27079 { 0, 0, 0, 0 },
27080 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
27081 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x98b80000 }
27082 },
27083/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
27084 {
27085 { 0, 0, 0, 0 },
27086 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
27087 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x988c0000 }
27088 },
27089/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
27090 {
27091 { 0, 0, 0, 0 },
27092 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
27093 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x98ac0000 }
27094 },
27095/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
27096 {
27097 { 0, 0, 0, 0 },
27098 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
27099 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x98bc0000 }
27100 },
27101/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
27102 {
27103 { 0, 0, 0, 0 },
27104 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
27105 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x988a0000 }
27106 },
27107/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
27108 {
27109 { 0, 0, 0, 0 },
27110 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
27111 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98aa0000 }
27112 },
27113/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
27114 {
27115 { 0, 0, 0, 0 },
27116 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
27117 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98ba0000 }
27118 },
27119/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
27120 {
27121 { 0, 0, 0, 0 },
27122 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
27123 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x988e0000 }
27124 },
27125/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
27126 {
27127 { 0, 0, 0, 0 },
27128 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
27129 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98ae0000 }
27130 },
27131/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
27132 {
27133 { 0, 0, 0, 0 },
27134 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
27135 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98be0000 }
27136 },
27137/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
27138 {
27139 { 0, 0, 0, 0 },
27140 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
27141 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x988b0000 }
27142 },
27143/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
27144 {
27145 { 0, 0, 0, 0 },
27146 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
27147 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98ab0000 }
27148 },
27149/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
27150 {
27151 { 0, 0, 0, 0 },
27152 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
27153 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98bb0000 }
27154 },
27155/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
27156 {
27157 { 0, 0, 0, 0 },
27158 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
27159 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x988f0000 }
27160 },
27161/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
27162 {
27163 { 0, 0, 0, 0 },
27164 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
27165 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x98af0000 }
27166 },
27167/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
27168 {
27169 { 0, 0, 0, 0 },
27170 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
27171 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x98bf0000 }
27172 },
27173/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
27174 {
27175 { 0, 0, 0, 0 },
27176 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
27177 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x98c00000 }
27178 },
27179/* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
27180 {
27181 { 0, 0, 0, 0 },
27182 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
27183 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x98e00000 }
27184 },
27185/* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
27186 {
27187 { 0, 0, 0, 0 },
27188 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
27189 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x98f00000 }
27190 },
27191/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
27192 {
27193 { 0, 0, 0, 0 },
27194 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
27195 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x98c40000 }
27196 },
27197/* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
27198 {
27199 { 0, 0, 0, 0 },
27200 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
27201 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x98e40000 }
27202 },
27203/* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
27204 {
27205 { 0, 0, 0, 0 },
27206 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
27207 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x98f40000 }
27208 },
27209/* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
27210 {
27211 { 0, 0, 0, 0 },
27212 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27213 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x98c60000 }
27214 },
27215/* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
27216 {
27217 { 0, 0, 0, 0 },
27218 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
27219 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x98e60000 }
27220 },
27221/* or.b${G} ${Dsp-16-u16},[$Dst16An] */
27222 {
27223 { 0, 0, 0, 0 },
27224 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
27225 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x98f60000 }
27226 },
27227/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
27228 {
27229 { 0, 0, 0, 0 },
27230 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27231 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x98c80000 }
27232 },
27233/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
27234 {
27235 { 0, 0, 0, 0 },
27236 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27237 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x98e80000 }
27238 },
27239/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
27240 {
27241 { 0, 0, 0, 0 },
27242 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27243 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x98f80000 }
27244 },
27245/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
27246 {
27247 { 0, 0, 0, 0 },
27248 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27249 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x98cc0000 }
27250 },
27251/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
27252 {
27253 { 0, 0, 0, 0 },
27254 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27255 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x98ec0000 }
27256 },
27257/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
27258 {
27259 { 0, 0, 0, 0 },
27260 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27261 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x98fc0000 }
27262 },
27263/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
27264 {
27265 { 0, 0, 0, 0 },
27266 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27267 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ca0000 }
27268 },
27269/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27270 {
27271 { 0, 0, 0, 0 },
27272 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27273 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ea0000 }
27274 },
27275/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27276 {
27277 { 0, 0, 0, 0 },
27278 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27279 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x98fa0000 }
27280 },
27281/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
27282 {
27283 { 0, 0, 0, 0 },
27284 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27285 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ce0000 }
27286 },
27287/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27288 {
27289 { 0, 0, 0, 0 },
27290 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27291 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ee0000 }
27292 },
27293/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27294 {
27295 { 0, 0, 0, 0 },
27296 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27297 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x98fe0000 }
27298 },
27299/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
27300 {
27301 { 0, 0, 0, 0 },
27302 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27303 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x98cb0000 }
27304 },
27305/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27306 {
27307 { 0, 0, 0, 0 },
27308 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27309 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x98eb0000 }
27310 },
27311/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27312 {
27313 { 0, 0, 0, 0 },
27314 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27315 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x98fb0000 }
27316 },
27317/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
27318 {
27319 { 0, 0, 0, 0 },
27320 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
27321 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x98cf0000 }
27322 },
27323/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27324 {
27325 { 0, 0, 0, 0 },
27326 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
27327 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x98ef0000 }
27328 },
27329/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
27330 {
27331 { 0, 0, 0, 0 },
27332 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
27333 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x98ff0000 }
27334 },
27335/* or.b${G} $Src16RnQI,$Dst16RnQI */
27336 {
27337 { 0, 0, 0, 0 },
27338 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
27339 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9800 }
27340 },
27341/* or.b${G} $Src16AnQI,$Dst16RnQI */
27342 {
27343 { 0, 0, 0, 0 },
27344 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
27345 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9840 }
27346 },
27347/* or.b${G} [$Src16An],$Dst16RnQI */
27348 {
27349 { 0, 0, 0, 0 },
27350 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
27351 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9860 }
27352 },
27353/* or.b${G} $Src16RnQI,$Dst16AnQI */
27354 {
27355 { 0, 0, 0, 0 },
27356 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
27357 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9804 }
27358 },
27359/* or.b${G} $Src16AnQI,$Dst16AnQI */
27360 {
27361 { 0, 0, 0, 0 },
27362 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
27363 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9844 }
27364 },
27365/* or.b${G} [$Src16An],$Dst16AnQI */
27366 {
27367 { 0, 0, 0, 0 },
27368 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
27369 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9864 }
27370 },
27371/* or.b${G} $Src16RnQI,[$Dst16An] */
27372 {
27373 { 0, 0, 0, 0 },
27374 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
27375 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9806 }
27376 },
27377/* or.b${G} $Src16AnQI,[$Dst16An] */
27378 {
27379 { 0, 0, 0, 0 },
27380 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
27381 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9846 }
27382 },
27383/* or.b${G} [$Src16An],[$Dst16An] */
27384 {
27385 { 0, 0, 0, 0 },
27386 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27387 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9866 }
27388 },
27389/* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
27390 {
27391 { 0, 0, 0, 0 },
27392 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27393 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x980800 }
27394 },
27395/* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
27396 {
27397 { 0, 0, 0, 0 },
27398 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27399 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x984800 }
27400 },
27401/* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
27402 {
27403 { 0, 0, 0, 0 },
27404 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27405 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x986800 }
27406 },
27407/* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
27408 {
27409 { 0, 0, 0, 0 },
27410 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27411 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x980c0000 }
27412 },
27413/* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
27414 {
27415 { 0, 0, 0, 0 },
27416 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27417 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x984c0000 }
27418 },
27419/* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
27420 {
27421 { 0, 0, 0, 0 },
27422 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27423 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x986c0000 }
27424 },
27425/* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
27426 {
27427 { 0, 0, 0, 0 },
27428 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27429 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x980a00 }
27430 },
27431/* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
27432 {
27433 { 0, 0, 0, 0 },
27434 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27435 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x984a00 }
27436 },
27437/* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
27438 {
27439 { 0, 0, 0, 0 },
27440 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27441 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x986a00 }
27442 },
27443/* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
27444 {
27445 { 0, 0, 0, 0 },
27446 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27447 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x980e0000 }
27448 },
27449/* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
27450 {
27451 { 0, 0, 0, 0 },
27452 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27453 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x984e0000 }
27454 },
27455/* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
27456 {
27457 { 0, 0, 0, 0 },
27458 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27459 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x986e0000 }
27460 },
27461/* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
27462 {
27463 { 0, 0, 0, 0 },
27464 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27465 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x980b00 }
27466 },
27467/* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
27468 {
27469 { 0, 0, 0, 0 },
27470 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27471 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x984b00 }
27472 },
27473/* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
27474 {
27475 { 0, 0, 0, 0 },
27476 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27477 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x986b00 }
27478 },
27479/* or.b${G} $Src16RnQI,${Dsp-16-u16} */
27480 {
27481 { 0, 0, 0, 0 },
27482 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
27483 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x980f0000 }
27484 },
27485/* or.b${G} $Src16AnQI,${Dsp-16-u16} */
27486 {
27487 { 0, 0, 0, 0 },
27488 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
27489 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x984f0000 }
27490 },
27491/* or.b${G} [$Src16An],${Dsp-16-u16} */
27492 {
27493 { 0, 0, 0, 0 },
27494 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
27495 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x986f0000 }
27496 },
27497/* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
27498 {
27499 { 0, 0, 0, 0 },
27500 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27501 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x65000000 }
27502 },
27503/* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
27504 {
27505 { 0, 0, 0, 0 },
27506 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27507 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x75000000 }
27508 },
27509/* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
27510 {
27511 { 0, 0, 0, 0 },
27512 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
27513 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x55000000 }
27514 },
27515/* or.w${S} #${Imm-8-HI},r0 */
27516 {
27517 { 0, 0, 0, 0 },
27518 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
27519 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x450000 }
27520 },
27521/* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
27522 {
27523 { 0, 0, 0, 0 },
27524 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27525 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x640000 }
27526 },
27527/* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
27528 {
27529 { 0, 0, 0, 0 },
27530 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27531 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x740000 }
27532 },
27533/* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
27534 {
27535 { 0, 0, 0, 0 },
27536 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
27537 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x54000000 }
27538 },
27539/* or.b${S} #${Imm-8-QI},r0l */
27540 {
27541 { 0, 0, 0, 0 },
27542 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
27543 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4400 }
27544 },
27545/* or.b${S} #${Imm-8-QI},r0l */
27546 {
27547 { 0, 0, 0, 0 },
27548 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
27549 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9c00 }
27550 },
27551/* or.b${S} #${Imm-8-QI},r0h */
27552 {
27553 { 0, 0, 0, 0 },
27554 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
27555 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9b00 }
27556 },
27557/* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
27558 {
27559 { 0, 0, 0, 0 },
27560 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27561 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x9d0000 }
27562 },
27563/* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
27564 {
27565 { 0, 0, 0, 0 },
27566 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27567 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x9e0000 }
27568 },
27569/* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
27570 {
27571 { 0, 0, 0, 0 },
27572 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
27573 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x9f000000 }
27574 },
27575/* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
27576 {
27577 { 0, 0, 0, 0 },
27578 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
27579 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892f0000 }
27580 },
27581/* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
27582 {
27583 { 0, 0, 0, 0 },
27584 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
27585 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81af0000 }
27586 },
27587/* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
27588 {
27589 { 0, 0, 0, 0 },
27590 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27591 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812f0000 }
27592 },
27593/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
27594 {
27595 { 0, 0, 0, 0 },
27596 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27597 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832f0000 }
27598 },
27599/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
27600 {
27601 { 0, 0, 0, 0 },
27602 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27603 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83af0000 }
27604 },
27605/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
27606 {
27607 { 0, 0, 0, 0 },
27608 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27609 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ef0000 }
27610 },
27611/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
27612 {
27613 { 0, 0, 0, 0 },
27614 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27615 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852f0000 }
27616 },
27617/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
27618 {
27619 { 0, 0, 0, 0 },
27620 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27621 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85af0000 }
27622 },
27623/* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
27624 {
27625 { 0, 0, 0, 0 },
27626 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27627 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ef0000 }
27628 },
27629/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
27630 {
27631 { 0, 0, 0, 0 },
27632 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
27633 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ef0000 }
27634 },
27635/* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
27636 {
27637 { 0, 0, 0, 0 },
27638 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27639 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872f0000 }
27640 },
27641/* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
27642 {
27643 { 0, 0, 0, 0 },
27644 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
27645 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87af0000 }
27646 },
27647/* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
27648 {
27649 { 0, 0, 0, 0 },
27650 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
27651 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882f00 }
27652 },
27653/* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
27654 {
27655 { 0, 0, 0, 0 },
27656 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
27657 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80af00 }
27658 },
27659/* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
27660 {
27661 { 0, 0, 0, 0 },
27662 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27663 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802f00 }
27664 },
27665/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
27666 {
27667 { 0, 0, 0, 0 },
27668 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27669 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822f0000 }
27670 },
27671/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
27672 {
27673 { 0, 0, 0, 0 },
27674 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27675 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82af0000 }
27676 },
27677/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
27678 {
27679 { 0, 0, 0, 0 },
27680 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27681 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ef0000 }
27682 },
27683/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
27684 {
27685 { 0, 0, 0, 0 },
27686 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27687 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842f0000 }
27688 },
27689/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
27690 {
27691 { 0, 0, 0, 0 },
27692 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27693 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84af0000 }
27694 },
27695/* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
27696 {
27697 { 0, 0, 0, 0 },
27698 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27699 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ef0000 }
27700 },
27701/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
27702 {
27703 { 0, 0, 0, 0 },
27704 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
27705 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ef0000 }
27706 },
27707/* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
27708 {
27709 { 0, 0, 0, 0 },
27710 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27711 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862f0000 }
27712 },
27713/* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
27714 {
27715 { 0, 0, 0, 0 },
27716 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
27717 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86af0000 }
27718 },
27719/* or.w${G} #${Imm-16-HI},$Dst16RnHI */
27720 {
27721 { 0, 0, 0, 0 },
27722 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
27723 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77300000 }
27724 },
27725/* or.w${G} #${Imm-16-HI},$Dst16AnHI */
27726 {
27727 { 0, 0, 0, 0 },
27728 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
27729 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77340000 }
27730 },
27731/* or.w${G} #${Imm-16-HI},[$Dst16An] */
27732 {
27733 { 0, 0, 0, 0 },
27734 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
27735 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77360000 }
27736 },
27737/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
27738 {
27739 { 0, 0, 0, 0 },
27740 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27741 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77380000 }
27742 },
27743/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
27744 {
27745 { 0, 0, 0, 0 },
27746 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27747 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x773a0000 }
27748 },
27749/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
27750 {
27751 { 0, 0, 0, 0 },
27752 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27753 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x773b0000 }
27754 },
27755/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
27756 {
27757 { 0, 0, 0, 0 },
27758 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27759 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x773c0000 }
27760 },
27761/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
27762 {
27763 { 0, 0, 0, 0 },
27764 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27765 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x773e0000 }
27766 },
27767/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
27768 {
27769 { 0, 0, 0, 0 },
27770 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
27771 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x773f0000 }
27772 },
27773/* or.b${G} #${Imm-16-QI},$Dst16RnQI */
27774 {
27775 { 0, 0, 0, 0 },
27776 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
27777 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x763000 }
27778 },
27779/* or.b${G} #${Imm-16-QI},$Dst16AnQI */
27780 {
27781 { 0, 0, 0, 0 },
27782 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
27783 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x763400 }
27784 },
27785/* or.b${G} #${Imm-16-QI},[$Dst16An] */
27786 {
27787 { 0, 0, 0, 0 },
27788 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
27789 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x763600 }
27790 },
27791/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
27792 {
27793 { 0, 0, 0, 0 },
27794 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27795 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76380000 }
27796 },
27797/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
27798 {
27799 { 0, 0, 0, 0 },
27800 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27801 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x763a0000 }
27802 },
27803/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
27804 {
27805 { 0, 0, 0, 0 },
27806 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27807 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x763b0000 }
27808 },
27809/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
27810 {
27811 { 0, 0, 0, 0 },
27812 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27813 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x763c0000 }
27814 },
27815/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
27816 {
27817 { 0, 0, 0, 0 },
27818 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27819 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x763e0000 }
27820 },
27821/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
27822 {
27823 { 0, 0, 0, 0 },
27824 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
27825 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x763f0000 }
27826 },
c6552317 27827/* not.b:s r0l */
49f58d10
JB		 27828 {
27829 { 0, 0, 0, 0 },
c6552317
DD		 27830 { { MNEM, ' ', 'r', '0', 'l', 0 } },
27831 & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xbc }
27832 },
27833/* not.b:s r0h */
27834 {
27835 { 0, 0, 0, 0 },
27836 { { MNEM, ' ', 'r', '0', 'h', 0 } },
27837 & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xbb }
27838 },
27839/* not.b:s ${Dsp-8-u8}[sb] */
27840 {
27841 { 0, 0, 0, 0 },
27842 { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27843 & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xbd00 }
27844 },
27845/* not.b:s ${Dsp-8-s8}[fb] */
27846 {
27847 { 0, 0, 0, 0 },
27848 { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27849 & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xbe00 }
27850 },
27851/* not.b:s ${Dsp-8-u16} */
27852 {
27853 { 0, 0, 0, 0 },
27854 { { MNEM, ' ', OP (DSP_8_U16), 0 } },
27855 & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xbf0000 }
27856 },
27857/* not.w${G} $Dst32RnUnprefixedHI */
27858 {
27859 { 0, 0, 0, 0 },
27860 { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
49f58d10
JB		 27861 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91e }
27862 },
c6552317 27863/* not.w${G} $Dst32AnUnprefixedHI */
49f58d10
JB		 27864 {
27865 { 0, 0, 0, 0 },
c6552317 27866 { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
49f58d10
JB		 27867 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19e }
27868 },
c6552317 27869/* not.w${G} [$Dst32AnUnprefixed] */
49f58d10
JB		 27870 {
27871 { 0, 0, 0, 0 },
c6552317 27872 { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27873 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11e }
27874 },
c6552317 27875/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 27876 {
27877 { 0, 0, 0, 0 },
c6552317 27878 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27879 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31e00 }
27880 },
c6552317 27881/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 27882 {
27883 { 0, 0, 0, 0 },
c6552317 27884 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27885 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51e0000 }
27886 },
c6552317 27887/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 27888 {
27889 { 0, 0, 0, 0 },
c6552317 27890 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27891 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71e0000 }
27892 },
c6552317 27893/* not.w${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 27894 {
27895 { 0, 0, 0, 0 },
c6552317 27896 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 27897 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39e00 }
27898 },
c6552317 27899/* not.w${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 27900 {
27901 { 0, 0, 0, 0 },
c6552317 27902 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 27903 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59e0000 }
27904 },
c6552317 27905/* not.w${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 27906 {
27907 { 0, 0, 0, 0 },
c6552317 27908 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 27909 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3de00 }
27910 },
c6552317 27911/* not.w${G} ${Dsp-16-s16}[fb] */
49f58d10
JB		 27912 {
27913 { 0, 0, 0, 0 },
c6552317 27914 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 27915 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5de0000 }
27916 },
c6552317 27917/* not.w${G} ${Dsp-16-u16} */
49f58d10
JB		 27918 {
27919 { 0, 0, 0, 0 },
c6552317 27920 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 27921 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7de0000 }
27922 },
c6552317 27923/* not.w${G} ${Dsp-16-u24} */
49f58d10
JB		 27924 {
27925 { 0, 0, 0, 0 },
c6552317 27926 { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } },
49f58d10
JB		 27927 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79e0000 }
27928 },
c6552317 27929/* not.b${G} $Dst32RnUnprefixedQI */
49f58d10
JB		 27930 {
27931 { 0, 0, 0, 0 },
c6552317 27932 { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
49f58d10
JB		 27933 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81e }
27934 },
c6552317 27935/* not.b${G} $Dst32AnUnprefixedQI */
49f58d10
JB		 27936 {
27937 { 0, 0, 0, 0 },
c6552317 27938 { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
49f58d10
JB		 27939 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09e }
27940 },
c6552317 27941/* not.b${G} [$Dst32AnUnprefixed] */
49f58d10
JB		 27942 {
27943 { 0, 0, 0, 0 },
c6552317 27944 { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27945 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01e }
27946 },
c6552317 27947/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 27948 {
27949 { 0, 0, 0, 0 },
c6552317 27950 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27951 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21e00 }
27952 },
c6552317 27953/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 27954 {
27955 { 0, 0, 0, 0 },
c6552317 27956 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27957 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41e0000 }
27958 },
c6552317 27959/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 27960 {
27961 { 0, 0, 0, 0 },
c6552317 27962 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 27963 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61e0000 }
27964 },
c6552317 27965/* not.b${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 27966 {
27967 { 0, 0, 0, 0 },
c6552317 27968 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 27969 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29e00 }
27970 },
c6552317 27971/* not.b${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 27972 {
27973 { 0, 0, 0, 0 },
c6552317 27974 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 27975 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49e0000 }
27976 },
c6552317 27977/* not.b${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 27978 {
27979 { 0, 0, 0, 0 },
c6552317 27980 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 27981 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2de00 }
27982 },
c6552317 27983/* not.b${G} ${Dsp-16-s16}[fb] */
49f58d10
JB		 27984 {
27985 { 0, 0, 0, 0 },
c6552317 27986 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 27987 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4de0000 }
27988 },
c6552317 27989/* not.b${G} ${Dsp-16-u16} */
49f58d10
JB		 27990 {
27991 { 0, 0, 0, 0 },
c6552317 27992 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 27993 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6de0000 }
27994 },
c6552317 27995/* not.b${G} ${Dsp-16-u24} */
49f58d10
JB		 27996 {
27997 { 0, 0, 0, 0 },
c6552317 27998 { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } },
49f58d10
JB		 27999 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69e0000 }
28000 },
c6552317 28001/* not.w${G} $Dst16RnHI */
49f58d10
JB		 28002 {
28003 { 0, 0, 0, 0 },
c6552317 28004 { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
49f58d10
JB		 28005 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7570 }
28006 },
c6552317 28007/* not.w${G} $Dst16AnHI */
49f58d10
JB		 28008 {
28009 { 0, 0, 0, 0 },
c6552317 28010 { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
49f58d10
JB		 28011 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7574 }
28012 },
c6552317 28013/* not.w${G} [$Dst16An] */
49f58d10
JB		 28014 {
28015 { 0, 0, 0, 0 },
c6552317 28016 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 28017 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7576 }
28018 },
c6552317 28019/* not.w${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 28020 {
28021 { 0, 0, 0, 0 },
c6552317 28022 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 28023 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x757800 }
28024 },
c6552317 28025/* not.w${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 28026 {
28027 { 0, 0, 0, 0 },
c6552317 28028 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 28029 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x757c0000 }
28030 },
c6552317 28031/* not.w${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 28032 {
28033 { 0, 0, 0, 0 },
c6552317 28034 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 28035 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x757a00 }
28036 },
c6552317 28037/* not.w${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 28038 {
28039 { 0, 0, 0, 0 },
c6552317 28040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 28041 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x757e0000 }
28042 },
c6552317 28043/* not.w${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 28044 {
28045 { 0, 0, 0, 0 },
c6552317 28046 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 28047 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x757b00 }
28048 },
c6552317 28049/* not.w${G} ${Dsp-16-u16} */
49f58d10
JB		 28050 {
28051 { 0, 0, 0, 0 },
c6552317 28052 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 28053 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x757f0000 }
28054 },
c6552317 28055/* not.b${G} $Dst16RnQI */
49f58d10
JB		 28056 {
28057 { 0, 0, 0, 0 },
c6552317 28058 { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
49f58d10
JB		 28059 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7470 }
28060 },
c6552317 28061/* not.b${G} $Dst16AnQI */
49f58d10
JB		 28062 {
28063 { 0, 0, 0, 0 },
c6552317 28064 { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
49f58d10
JB		 28065 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7474 }
28066 },
c6552317 28067/* not.b${G} [$Dst16An] */
49f58d10
JB		 28068 {
28069 { 0, 0, 0, 0 },
c6552317 28070 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 28071 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7476 }
28072 },
c6552317 28073/* not.b${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 28074 {
28075 { 0, 0, 0, 0 },
c6552317 28076 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 28077 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x747800 }
28078 },
c6552317 28079/* not.b${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 28080 {
28081 { 0, 0, 0, 0 },
c6552317 28082 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 28083 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x747c0000 }
28084 },
c6552317 28085/* not.b${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 28086 {
28087 { 0, 0, 0, 0 },
c6552317 28088 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 28089 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x747a00 }
28090 },
c6552317 28091/* not.b${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 28092 {
28093 { 0, 0, 0, 0 },
c6552317 28094 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 28095 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x747e0000 }
28096 },
c6552317 28097/* not.b${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 28098 {
28099 { 0, 0, 0, 0 },
c6552317 28100 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 28101 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x747b00 }
28102 },
c6552317 28103/* not.b${G} ${Dsp-16-u16} */
49f58d10
JB		 28104 {
28105 { 0, 0, 0, 0 },
c6552317 28106 { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
49f58d10
JB		 28107 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x747f0000 }
28108 },
28109/* neg.w $Dst32RnUnprefixedHI */
28110 {
28111 { 0, 0, 0, 0 },
28112 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
28113 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92f }
28114 },
28115/* neg.w $Dst32AnUnprefixedHI */
28116 {
28117 { 0, 0, 0, 0 },
28118 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
28119 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1af }
28120 },
28121/* neg.w [$Dst32AnUnprefixed] */
28122 {
28123 { 0, 0, 0, 0 },
28124 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28125 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12f }
28126 },
28127/* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
28128 {
28129 { 0, 0, 0, 0 },
28130 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28131 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32f00 }
28132 },
28133/* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
28134 {
28135 { 0, 0, 0, 0 },
28136 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28137 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52f0000 }
28138 },
28139/* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
28140 {
28141 { 0, 0, 0, 0 },
28142 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28143 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72f0000 }
28144 },
28145/* neg.w ${Dsp-16-u8}[sb] */
28146 {
28147 { 0, 0, 0, 0 },
28148 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28149 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3af00 }
28150 },
28151/* neg.w ${Dsp-16-u16}[sb] */
28152 {
28153 { 0, 0, 0, 0 },
28154 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28155 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5af0000 }
28156 },
28157/* neg.w ${Dsp-16-s8}[fb] */
28158 {
28159 { 0, 0, 0, 0 },
28160 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28161 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ef00 }
28162 },
28163/* neg.w ${Dsp-16-s16}[fb] */
28164 {
28165 { 0, 0, 0, 0 },
28166 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
28167 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ef0000 }
28168 },
28169/* neg.w ${Dsp-16-u16} */
28170 {
28171 { 0, 0, 0, 0 },
28172 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28173 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ef0000 }
28174 },
28175/* neg.w ${Dsp-16-u24} */
28176 {
28177 { 0, 0, 0, 0 },
28178 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
28179 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7af0000 }
28180 },
28181/* neg.b $Dst32RnUnprefixedQI */
28182 {
28183 { 0, 0, 0, 0 },
28184 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
28185 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82f }
28186 },
28187/* neg.b $Dst32AnUnprefixedQI */
28188 {
28189 { 0, 0, 0, 0 },
28190 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
28191 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0af }
28192 },
28193/* neg.b [$Dst32AnUnprefixed] */
28194 {
28195 { 0, 0, 0, 0 },
28196 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28197 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02f }
28198 },
28199/* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
28200 {
28201 { 0, 0, 0, 0 },
28202 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28203 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22f00 }
28204 },
28205/* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
28206 {
28207 { 0, 0, 0, 0 },
28208 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28209 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42f0000 }
28210 },
28211/* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
28212 {
28213 { 0, 0, 0, 0 },
28214 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28215 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62f0000 }
28216 },
28217/* neg.b ${Dsp-16-u8}[sb] */
28218 {
28219 { 0, 0, 0, 0 },
28220 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28221 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2af00 }
28222 },
28223/* neg.b ${Dsp-16-u16}[sb] */
28224 {
28225 { 0, 0, 0, 0 },
28226 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28227 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4af0000 }
28228 },
28229/* neg.b ${Dsp-16-s8}[fb] */
28230 {
28231 { 0, 0, 0, 0 },
28232 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28233 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ef00 }
28234 },
28235/* neg.b ${Dsp-16-s16}[fb] */
28236 {
28237 { 0, 0, 0, 0 },
28238 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
28239 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ef0000 }
28240 },
28241/* neg.b ${Dsp-16-u16} */
28242 {
28243 { 0, 0, 0, 0 },
28244 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28245 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ef0000 }
28246 },
28247/* neg.b ${Dsp-16-u24} */
28248 {
28249 { 0, 0, 0, 0 },
28250 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
28251 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6af0000 }
28252 },
28253/* neg.w $Dst16RnHI */
28254 {
28255 { 0, 0, 0, 0 },
28256 { { MNEM, ' ', OP (DST16RNHI), 0 } },
28257 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7550 }
28258 },
28259/* neg.w $Dst16AnHI */
28260 {
28261 { 0, 0, 0, 0 },
28262 { { MNEM, ' ', OP (DST16ANHI), 0 } },
28263 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7554 }
28264 },
28265/* neg.w [$Dst16An] */
28266 {
28267 { 0, 0, 0, 0 },
28268 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
28269 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7556 }
28270 },
28271/* neg.w ${Dsp-16-u8}[$Dst16An] */
28272 {
28273 { 0, 0, 0, 0 },
28274 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28275 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x755800 }
28276 },
28277/* neg.w ${Dsp-16-u16}[$Dst16An] */
28278 {
28279 { 0, 0, 0, 0 },
28280 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28281 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x755c0000 }
28282 },
28283/* neg.w ${Dsp-16-u8}[sb] */
28284 {
28285 { 0, 0, 0, 0 },
28286 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28287 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x755a00 }
28288 },
28289/* neg.w ${Dsp-16-u16}[sb] */
28290 {
28291 { 0, 0, 0, 0 },
28292 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28293 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x755e0000 }
28294 },
28295/* neg.w ${Dsp-16-s8}[fb] */
28296 {
28297 { 0, 0, 0, 0 },
28298 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28299 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x755b00 }
28300 },
28301/* neg.w ${Dsp-16-u16} */
28302 {
28303 { 0, 0, 0, 0 },
28304 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28305 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x755f0000 }
28306 },
28307/* neg.b $Dst16RnQI */
28308 {
28309 { 0, 0, 0, 0 },
28310 { { MNEM, ' ', OP (DST16RNQI), 0 } },
28311 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7450 }
28312 },
28313/* neg.b $Dst16AnQI */
28314 {
28315 { 0, 0, 0, 0 },
28316 { { MNEM, ' ', OP (DST16ANQI), 0 } },
28317 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7454 }
28318 },
28319/* neg.b [$Dst16An] */
28320 {
28321 { 0, 0, 0, 0 },
28322 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
28323 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7456 }
28324 },
28325/* neg.b ${Dsp-16-u8}[$Dst16An] */
28326 {
28327 { 0, 0, 0, 0 },
28328 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28329 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x745800 }
28330 },
28331/* neg.b ${Dsp-16-u16}[$Dst16An] */
28332 {
28333 { 0, 0, 0, 0 },
28334 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28335 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x745c0000 }
28336 },
28337/* neg.b ${Dsp-16-u8}[sb] */
28338 {
28339 { 0, 0, 0, 0 },
28340 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28341 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x745a00 }
28342 },
28343/* neg.b ${Dsp-16-u16}[sb] */
28344 {
28345 { 0, 0, 0, 0 },
28346 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28347 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x745e0000 }
28348 },
28349/* neg.b ${Dsp-16-s8}[fb] */
28350 {
28351 { 0, 0, 0, 0 },
28352 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28353 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x745b00 }
28354 },
28355/* neg.b ${Dsp-16-u16} */
28356 {
28357 { 0, 0, 0, 0 },
28358 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28359 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x745f0000 }
28360 },
28361/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28362 {
28363 { 0, 0, 0, 0 },
28364 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28365 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990400 }
28366 },
28367/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
28368 {
28369 { 0, 0, 0, 0 },
28370 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28371 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992400 }
28372 },
28373/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
28374 {
28375 { 0, 0, 0, 0 },
28376 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28377 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993400 }
28378 },
28379/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28380 {
28381 { 0, 0, 0, 0 },
28382 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28383 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918400 }
28384 },
28385/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
28386 {
28387 { 0, 0, 0, 0 },
28388 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28389 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a400 }
28390 },
28391/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
28392 {
28393 { 0, 0, 0, 0 },
28394 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28395 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b400 }
28396 },
28397/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28398 {
28399 { 0, 0, 0, 0 },
28400 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28401 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910400 }
28402 },
28403/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28404 {
28405 { 0, 0, 0, 0 },
28406 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28407 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912400 }
28408 },
28409/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28410 {
28411 { 0, 0, 0, 0 },
28412 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28413 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913400 }
28414 },
28415/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28416 {
28417 { 0, 0, 0, 0 },
28418 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28419 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93040000 }
28420 },
28421/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28422 {
28423 { 0, 0, 0, 0 },
28424 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28425 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93240000 }
28426 },
28427/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28428 {
28429 { 0, 0, 0, 0 },
28430 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28431 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93340000 }
28432 },
28433/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28434 {
28435 { 0, 0, 0, 0 },
28436 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28437 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95040000 }
28438 },
28439/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28440 {
28441 { 0, 0, 0, 0 },
28442 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28443 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95240000 }
28444 },
28445/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28446 {
28447 { 0, 0, 0, 0 },
28448 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28449 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95340000 }
28450 },
28451/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28452 {
28453 { 0, 0, 0, 0 },
28454 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28455 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97040000 }
28456 },
28457/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28458 {
28459 { 0, 0, 0, 0 },
28460 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28461 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97240000 }
28462 },
28463/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28464 {
28465 { 0, 0, 0, 0 },
28466 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28467 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97340000 }
28468 },
28469/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28470 {
28471 { 0, 0, 0, 0 },
28472 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28473 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93840000 }
28474 },
28475/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28476 {
28477 { 0, 0, 0, 0 },
28478 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28479 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a40000 }
28480 },
28481/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28482 {
28483 { 0, 0, 0, 0 },
28484 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28485 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b40000 }
28486 },
28487/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28488 {
28489 { 0, 0, 0, 0 },
28490 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28491 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95840000 }
28492 },
28493/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28494 {
28495 { 0, 0, 0, 0 },
28496 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28497 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a40000 }
28498 },
28499/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28500 {
28501 { 0, 0, 0, 0 },
28502 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28503 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b40000 }
28504 },
28505/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28506 {
28507 { 0, 0, 0, 0 },
28508 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28509 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c40000 }
28510 },
28511/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28512 {
28513 { 0, 0, 0, 0 },
28514 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28515 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e40000 }
28516 },
28517/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28518 {
28519 { 0, 0, 0, 0 },
28520 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28521 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f40000 }
28522 },
28523/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28524 {
28525 { 0, 0, 0, 0 },
28526 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28527 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c40000 }
28528 },
28529/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28530 {
28531 { 0, 0, 0, 0 },
28532 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28533 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e40000 }
28534 },
28535/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28536 {
28537 { 0, 0, 0, 0 },
28538 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28539 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f40000 }
28540 },
28541/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28542 {
28543 { 0, 0, 0, 0 },
28544 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
28545 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c40000 }
28546 },
28547/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28548 {
28549 { 0, 0, 0, 0 },
28550 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
28551 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e40000 }
28552 },
28553/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28554 {
28555 { 0, 0, 0, 0 },
28556 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
28557 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f40000 }
28558 },
28559/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28560 {
28561 { 0, 0, 0, 0 },
28562 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
28563 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97840000 }
28564 },
28565/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28566 {
28567 { 0, 0, 0, 0 },
28568 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
28569 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a40000 }
28570 },
28571/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28572 {
28573 { 0, 0, 0, 0 },
28574 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
28575 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b40000 }
28576 },
28577/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28578 {
28579 { 0, 0, 0, 0 },
28580 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28581 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9040000 }
28582 },
28583/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
28584 {
28585 { 0, 0, 0, 0 },
28586 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28587 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9240000 }
28588 },
28589/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
28590 {
28591 { 0, 0, 0, 0 },
28592 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28593 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9340000 }
28594 },
28595/* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
28596 {
28597 { 0, 0, 0, 0 },
28598 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28599 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9340000 }
28600 },
28601/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28602 {
28603 { 0, 0, 0, 0 },
28604 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28605 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1840000 }
28606 },
28607/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
28608 {
28609 { 0, 0, 0, 0 },
28610 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28611 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a40000 }
28612 },
28613/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
28614 {
28615 { 0, 0, 0, 0 },
28616 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28617 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b40000 }
28618 },
28619/* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
28620 {
28621 { 0, 0, 0, 0 },
28622 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28623 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b40000 }
28624 },
28625/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28626 {
28627 { 0, 0, 0, 0 },
28628 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28629 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1040000 }
28630 },
28631/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28632 {
28633 { 0, 0, 0, 0 },
28634 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28635 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1240000 }
28636 },
28637/* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28638 {
28639 { 0, 0, 0, 0 },
28640 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28641 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1340000 }
28642 },
28643/* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28644 {
28645 { 0, 0, 0, 0 },
28646 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28647 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1340000 }
28648 },
28649/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28650 {
28651 { 0, 0, 0, 0 },
28652 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28653 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3040000 }
28654 },
28655/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28656 {
28657 { 0, 0, 0, 0 },
28658 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28659 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3240000 }
28660 },
28661/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28662 {
28663 { 0, 0, 0, 0 },
28664 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28665 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3340000 }
28666 },
28667/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28668 {
28669 { 0, 0, 0, 0 },
28670 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28671 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3340000 }
28672 },
28673/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28674 {
28675 { 0, 0, 0, 0 },
28676 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28677 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5040000 }
28678 },
28679/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28680 {
28681 { 0, 0, 0, 0 },
28682 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28683 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5240000 }
28684 },
28685/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28686 {
28687 { 0, 0, 0, 0 },
28688 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28689 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5340000 }
28690 },
28691/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28692 {
28693 { 0, 0, 0, 0 },
28694 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28695 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5340000 }
28696 },
28697/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28698 {
28699 { 0, 0, 0, 0 },
28700 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28701 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7040000 }
28702 },
28703/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28704 {
28705 { 0, 0, 0, 0 },
28706 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28707 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7240000 }
28708 },
28709/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28710 {
28711 { 0, 0, 0, 0 },
28712 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28713 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7340000 }
28714 },
28715/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28716 {
28717 { 0, 0, 0, 0 },
28718 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28719 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7340000 }
28720 },
28721/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28722 {
28723 { 0, 0, 0, 0 },
28724 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28725 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3840000 }
28726 },
28727/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28728 {
28729 { 0, 0, 0, 0 },
28730 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28731 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a40000 }
28732 },
28733/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28734 {
28735 { 0, 0, 0, 0 },
28736 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28737 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b40000 }
28738 },
28739/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28740 {
28741 { 0, 0, 0, 0 },
28742 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28743 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b40000 }
28744 },
28745/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28746 {
28747 { 0, 0, 0, 0 },
28748 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28749 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5840000 }
28750 },
28751/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28752 {
28753 { 0, 0, 0, 0 },
28754 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28755 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a40000 }
28756 },
28757/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28758 {
28759 { 0, 0, 0, 0 },
28760 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28761 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b40000 }
28762 },
28763/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28764 {
28765 { 0, 0, 0, 0 },
28766 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28767 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b40000 }
28768 },
28769/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28770 {
28771 { 0, 0, 0, 0 },
28772 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28773 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c40000 }
28774 },
28775/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28776 {
28777 { 0, 0, 0, 0 },
28778 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28779 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e40000 }
28780 },
28781/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28782 {
28783 { 0, 0, 0, 0 },
28784 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28785 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f40000 }
28786 },
28787/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28788 {
28789 { 0, 0, 0, 0 },
28790 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28791 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f40000 }
28792 },
28793/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28794 {
28795 { 0, 0, 0, 0 },
28796 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28797 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c40000 }
28798 },
28799/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28800 {
28801 { 0, 0, 0, 0 },
28802 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28803 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e40000 }
28804 },
28805/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28806 {
28807 { 0, 0, 0, 0 },
28808 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28809 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f40000 }
28810 },
28811/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28812 {
28813 { 0, 0, 0, 0 },
28814 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28815 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f40000 }
28816 },
28817/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28818 {
28819 { 0, 0, 0, 0 },
28820 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
28821 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c40000 }
28822 },
28823/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28824 {
28825 { 0, 0, 0, 0 },
28826 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
28827 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e40000 }
28828 },
28829/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28830 {
28831 { 0, 0, 0, 0 },
28832 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
28833 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f40000 }
28834 },
28835/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
28836 {
28837 { 0, 0, 0, 0 },
28838 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
28839 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f40000 }
28840 },
28841/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28842 {
28843 { 0, 0, 0, 0 },
28844 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
28845 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7840000 }
28846 },
28847/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28848 {
28849 { 0, 0, 0, 0 },
28850 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
28851 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a40000 }
28852 },
28853/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28854 {
28855 { 0, 0, 0, 0 },
28856 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
28857 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b40000 }
28858 },
28859/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
28860 {
28861 { 0, 0, 0, 0 },
28862 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
28863 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b40000 }
28864 },
28865/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28866 {
28867 { 0, 0, 0, 0 },
28868 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28869 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9040000 }
28870 },
28871/* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
28872 {
28873 { 0, 0, 0, 0 },
28874 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28875 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9240000 }
28876 },
28877/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28878 {
28879 { 0, 0, 0, 0 },
28880 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28881 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1840000 }
28882 },
28883/* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
28884 {
28885 { 0, 0, 0, 0 },
28886 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28887 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a40000 }
28888 },
28889/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28890 {
28891 { 0, 0, 0, 0 },
28892 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28893 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1040000 }
28894 },
28895/* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28896 {
28897 { 0, 0, 0, 0 },
28898 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28899 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1240000 }
28900 },
28901/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28902 {
28903 { 0, 0, 0, 0 },
28904 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28905 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3040000 }
28906 },
28907/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28908 {
28909 { 0, 0, 0, 0 },
28910 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28911 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3240000 }
28912 },
28913/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28914 {
28915 { 0, 0, 0, 0 },
28916 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28917 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5040000 }
28918 },
28919/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28920 {
28921 { 0, 0, 0, 0 },
28922 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28923 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5240000 }
28924 },
28925/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28926 {
28927 { 0, 0, 0, 0 },
28928 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28929 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7040000 }
28930 },
28931/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28932 {
28933 { 0, 0, 0, 0 },
28934 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28935 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7240000 }
28936 },
28937/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28938 {
28939 { 0, 0, 0, 0 },
28940 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
28941 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3840000 }
28942 },
28943/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28944 {
28945 { 0, 0, 0, 0 },
28946 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
28947 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a40000 }
28948 },
28949/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28950 {
28951 { 0, 0, 0, 0 },
28952 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
28953 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5840000 }
28954 },
28955/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28956 {
28957 { 0, 0, 0, 0 },
28958 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
28959 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a40000 }
28960 },
28961/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28962 {
28963 { 0, 0, 0, 0 },
28964 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
28965 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c40000 }
28966 },
28967/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28968 {
28969 { 0, 0, 0, 0 },
28970 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
28971 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e40000 }
28972 },
28973/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28974 {
28975 { 0, 0, 0, 0 },
28976 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
28977 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c40000 }
28978 },
28979/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28980 {
28981 { 0, 0, 0, 0 },
28982 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
28983 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e40000 }
28984 },
28985/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28986 {
28987 { 0, 0, 0, 0 },
28988 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
28989 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c40000 }
28990 },
28991/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
28992 {
28993 { 0, 0, 0, 0 },
28994 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
28995 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e40000 }
28996 },
28997/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28998 {
28999 { 0, 0, 0, 0 },
29000 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
29001 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7840000 }
29002 },
29003/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
29004 {
29005 { 0, 0, 0, 0 },
29006 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
29007 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a40000 }
29008 },
29009/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
29010 {
29011 { 0, 0, 0, 0 },
29012 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
29013 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc904 }
29014 },
29015/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
29016 {
29017 { 0, 0, 0, 0 },
29018 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
29019 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8924 }
29020 },
29021/* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
29022 {
29023 { 0, 0, 0, 0 },
29024 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
29025 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8904 }
29026 },
29027/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
29028 {
29029 { 0, 0, 0, 0 },
29030 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
29031 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc184 }
29032 },
29033/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
29034 {
29035 { 0, 0, 0, 0 },
29036 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
29037 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a4 }
29038 },
29039/* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
29040 {
29041 { 0, 0, 0, 0 },
29042 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
29043 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8184 }
29044 },
29045/* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
29046 {
29047 { 0, 0, 0, 0 },
29048 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29049 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc104 }
29050 },
29051/* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
29052 {
29053 { 0, 0, 0, 0 },
29054 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29055 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8124 }
29056 },
29057/* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29058 {
29059 { 0, 0, 0, 0 },
29060 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29061 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8104 }
29062 },
29063/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29064 {
29065 { 0, 0, 0, 0 },
29066 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29067 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30400 }
29068 },
29069/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29070 {
29071 { 0, 0, 0, 0 },
29072 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29073 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832400 }
29074 },
29075/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
29076 {
29077 { 0, 0, 0, 0 },
29078 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29079 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830400 }
29080 },
29081/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29082 {
29083 { 0, 0, 0, 0 },
29084 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29085 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5040000 }
29086 },
29087/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29088 {
29089 { 0, 0, 0, 0 },
29090 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29091 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85240000 }
29092 },
29093/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
29094 {
29095 { 0, 0, 0, 0 },
29096 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29097 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85040000 }
29098 },
29099/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29100 {
29101 { 0, 0, 0, 0 },
29102 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29103 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7040000 }
29104 },
29105/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29106 {
29107 { 0, 0, 0, 0 },
29108 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29109 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87240000 }
29110 },
29111/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
29112 {
29113 { 0, 0, 0, 0 },
29114 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29115 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87040000 }
29116 },
29117/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
29118 {
29119 { 0, 0, 0, 0 },
29120 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29121 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38400 }
29122 },
29123/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
29124 {
29125 { 0, 0, 0, 0 },
29126 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29127 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a400 }
29128 },
29129/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
29130 {
29131 { 0, 0, 0, 0 },
29132 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29133 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838400 }
29134 },
29135/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
29136 {
29137 { 0, 0, 0, 0 },
29138 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29139 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5840000 }
29140 },
29141/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
29142 {
29143 { 0, 0, 0, 0 },
29144 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29145 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a40000 }
29146 },
29147/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
29148 {
29149 { 0, 0, 0, 0 },
29150 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29151 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85840000 }
29152 },
29153/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
29154 {
29155 { 0, 0, 0, 0 },
29156 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29157 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c400 }
29158 },
29159/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
29160 {
29161 { 0, 0, 0, 0 },
29162 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29163 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e400 }
29164 },
29165/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
29166 {
29167 { 0, 0, 0, 0 },
29168 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29169 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c400 }
29170 },
29171/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
29172 {
29173 { 0, 0, 0, 0 },
29174 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29175 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c40000 }
29176 },
29177/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
29178 {
29179 { 0, 0, 0, 0 },
29180 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29181 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e40000 }
29182 },
29183/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
29184 {
29185 { 0, 0, 0, 0 },
29186 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29187 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c40000 }
29188 },
29189/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
29190 {
29191 { 0, 0, 0, 0 },
29192 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
29193 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c40000 }
29194 },
29195/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
29196 {
29197 { 0, 0, 0, 0 },
29198 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
29199 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e40000 }
29200 },
29201/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
29202 {
29203 { 0, 0, 0, 0 },
29204 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
29205 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c40000 }
29206 },
29207/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
29208 {
29209 { 0, 0, 0, 0 },
29210 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
29211 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7840000 }
29212 },
29213/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
29214 {
29215 { 0, 0, 0, 0 },
29216 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
29217 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a40000 }
29218 },
29219/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
29220 {
29221 { 0, 0, 0, 0 },
29222 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
29223 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87840000 }
29224 },
29225/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29226 {
29227 { 0, 0, 0, 0 },
29228 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29229 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980400 }
29230 },
29231/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
29232 {
29233 { 0, 0, 0, 0 },
29234 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29235 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982400 }
29236 },
29237/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
29238 {
29239 { 0, 0, 0, 0 },
29240 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29241 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983400 }
29242 },
29243/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29244 {
29245 { 0, 0, 0, 0 },
29246 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29247 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908400 }
29248 },
29249/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
29250 {
29251 { 0, 0, 0, 0 },
29252 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29253 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a400 }
29254 },
29255/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
29256 {
29257 { 0, 0, 0, 0 },
29258 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29259 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b400 }
29260 },
29261/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29262 {
29263 { 0, 0, 0, 0 },
29264 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29265 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900400 }
29266 },
29267/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
29268 {
29269 { 0, 0, 0, 0 },
29270 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29271 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902400 }
29272 },
29273/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
29274 {
29275 { 0, 0, 0, 0 },
29276 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29277 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903400 }
29278 },
29279/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29280 {
29281 { 0, 0, 0, 0 },
29282 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29283 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92040000 }
29284 },
29285/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29286 {
29287 { 0, 0, 0, 0 },
29288 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29289 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92240000 }
29290 },
29291/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29292 {
29293 { 0, 0, 0, 0 },
29294 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29295 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92340000 }
29296 },
29297/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29298 {
29299 { 0, 0, 0, 0 },
29300 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29301 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94040000 }
29302 },
29303/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29304 {
29305 { 0, 0, 0, 0 },
29306 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29307 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94240000 }
29308 },
29309/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29310 {
29311 { 0, 0, 0, 0 },
29312 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29313 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94340000 }
29314 },
29315/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29316 {
29317 { 0, 0, 0, 0 },
29318 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29319 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96040000 }
29320 },
29321/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29322 {
29323 { 0, 0, 0, 0 },
29324 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29325 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96240000 }
29326 },
29327/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29328 {
29329 { 0, 0, 0, 0 },
29330 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29331 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96340000 }
29332 },
29333/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
29334 {
29335 { 0, 0, 0, 0 },
29336 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29337 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92840000 }
29338 },
29339/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29340 {
29341 { 0, 0, 0, 0 },
29342 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29343 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a40000 }
29344 },
29345/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29346 {
29347 { 0, 0, 0, 0 },
29348 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29349 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b40000 }
29350 },
29351/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
29352 {
29353 { 0, 0, 0, 0 },
29354 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29355 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94840000 }
29356 },
29357/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29358 {
29359 { 0, 0, 0, 0 },
29360 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29361 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a40000 }
29362 },
29363/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29364 {
29365 { 0, 0, 0, 0 },
29366 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29367 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b40000 }
29368 },
29369/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
29370 {
29371 { 0, 0, 0, 0 },
29372 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29373 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c40000 }
29374 },
29375/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29376 {
29377 { 0, 0, 0, 0 },
29378 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29379 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e40000 }
29380 },
29381/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29382 {
29383 { 0, 0, 0, 0 },
29384 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29385 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f40000 }
29386 },
29387/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
29388 {
29389 { 0, 0, 0, 0 },
29390 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29391 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c40000 }
29392 },
29393/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
29394 {
29395 { 0, 0, 0, 0 },
29396 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29397 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e40000 }
29398 },
29399/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
29400 {
29401 { 0, 0, 0, 0 },
29402 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29403 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f40000 }
29404 },
29405/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
29406 {
29407 { 0, 0, 0, 0 },
29408 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
29409 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c40000 }
29410 },
29411/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29412 {
29413 { 0, 0, 0, 0 },
29414 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
29415 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e40000 }
29416 },
29417/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29418 {
29419 { 0, 0, 0, 0 },
29420 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
29421 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f40000 }
29422 },
29423/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
29424 {
29425 { 0, 0, 0, 0 },
29426 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
29427 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96840000 }
29428 },
29429/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
29430 {
29431 { 0, 0, 0, 0 },
29432 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
29433 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a40000 }
29434 },
29435/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
29436 {
29437 { 0, 0, 0, 0 },
29438 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
29439 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b40000 }
29440 },
29441/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29442 {
29443 { 0, 0, 0, 0 },
29444 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29445 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8040000 }
29446 },
29447/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
29448 {
29449 { 0, 0, 0, 0 },
29450 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29451 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8240000 }
29452 },
29453/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
29454 {
29455 { 0, 0, 0, 0 },
29456 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29457 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8340000 }
29458 },
29459/* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
29460 {
29461 { 0, 0, 0, 0 },
29462 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29463 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8340000 }
29464 },
29465/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29466 {
29467 { 0, 0, 0, 0 },
29468 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29469 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0840000 }
29470 },
29471/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
29472 {
29473 { 0, 0, 0, 0 },
29474 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29475 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a40000 }
29476 },
29477/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
29478 {
29479 { 0, 0, 0, 0 },
29480 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29481 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b40000 }
29482 },
29483/* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
29484 {
29485 { 0, 0, 0, 0 },
29486 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29487 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b40000 }
29488 },
29489/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29490 {
29491 { 0, 0, 0, 0 },
29492 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29493 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0040000 }
29494 },
29495/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
29496 {
29497 { 0, 0, 0, 0 },
29498 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29499 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0240000 }
29500 },
29501/* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
29502 {
29503 { 0, 0, 0, 0 },
29504 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29505 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0340000 }
29506 },
29507/* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
29508 {
29509 { 0, 0, 0, 0 },
29510 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29511 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0340000 }
29512 },
29513/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29514 {
29515 { 0, 0, 0, 0 },
29516 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29517 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2040000 }
29518 },
29519/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29520 {
29521 { 0, 0, 0, 0 },
29522 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29523 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2240000 }
29524 },
29525/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29526 {
29527 { 0, 0, 0, 0 },
29528 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29529 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2340000 }
29530 },
29531/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
29532 {
29533 { 0, 0, 0, 0 },
29534 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29535 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2340000 }
29536 },
29537/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29538 {
29539 { 0, 0, 0, 0 },
29540 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29541 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4040000 }
29542 },
29543/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29544 {
29545 { 0, 0, 0, 0 },
29546 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29547 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4240000 }
29548 },
29549/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29550 {
29551 { 0, 0, 0, 0 },
29552 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29553 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4340000 }
29554 },
29555/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
29556 {
29557 { 0, 0, 0, 0 },
29558 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29559 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4340000 }
29560 },
29561/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29562 {
29563 { 0, 0, 0, 0 },
29564 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29565 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6040000 }
29566 },
29567/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29568 {
29569 { 0, 0, 0, 0 },
29570 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29571 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6240000 }
29572 },
29573/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29574 {
29575 { 0, 0, 0, 0 },
29576 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29577 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6340000 }
29578 },
29579/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
29580 {
29581 { 0, 0, 0, 0 },
29582 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29583 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6340000 }
29584 },
29585/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
29586 {
29587 { 0, 0, 0, 0 },
29588 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29589 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2840000 }
29590 },
29591/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29592 {
29593 { 0, 0, 0, 0 },
29594 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29595 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a40000 }
29596 },
29597/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
29598 {
29599 { 0, 0, 0, 0 },
29600 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29601 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b40000 }
29602 },
29603/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29604 {
29605 { 0, 0, 0, 0 },
29606 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29607 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b40000 }
29608 },
29609/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
29610 {
29611 { 0, 0, 0, 0 },
29612 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29613 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4840000 }
29614 },
29615/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29616 {
29617 { 0, 0, 0, 0 },
29618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29619 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a40000 }
29620 },
29621/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
29622 {
29623 { 0, 0, 0, 0 },
29624 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29625 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b40000 }
29626 },
29627/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29628 {
29629 { 0, 0, 0, 0 },
29630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29631 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b40000 }
29632 },
29633/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
29634 {
29635 { 0, 0, 0, 0 },
29636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29637 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c40000 }
29638 },
29639/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29640 {
29641 { 0, 0, 0, 0 },
29642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29643 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e40000 }
29644 },
29645/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
29646 {
29647 { 0, 0, 0, 0 },
29648 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29649 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f40000 }
29650 },
29651/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29652 {
29653 { 0, 0, 0, 0 },
29654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29655 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f40000 }
29656 },
29657/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
29658 {
29659 { 0, 0, 0, 0 },
29660 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29661 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c40000 }
29662 },
29663/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
29664 {
29665 { 0, 0, 0, 0 },
29666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29667 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e40000 }
29668 },
29669/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
29670 {
29671 { 0, 0, 0, 0 },
29672 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29673 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f40000 }
29674 },
29675/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
29676 {
29677 { 0, 0, 0, 0 },
29678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29679 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f40000 }
29680 },
29681/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
29682 {
29683 { 0, 0, 0, 0 },
29684 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
29685 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c40000 }
29686 },
29687/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29688 {
29689 { 0, 0, 0, 0 },
29690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
29691 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e40000 }
29692 },
29693/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
29694 {
29695 { 0, 0, 0, 0 },
29696 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
29697 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f40000 }
29698 },
29699/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29700 {
29701 { 0, 0, 0, 0 },
29702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
29703 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f40000 }
29704 },
29705/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
29706 {
29707 { 0, 0, 0, 0 },
29708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
29709 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6840000 }
29710 },
29711/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
29712 {
29713 { 0, 0, 0, 0 },
29714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
29715 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a40000 }
29716 },
29717/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
29718 {
29719 { 0, 0, 0, 0 },
29720 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
29721 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b40000 }
29722 },
29723/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
29724 {
29725 { 0, 0, 0, 0 },
29726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
29727 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b40000 }
29728 },
29729/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29730 {
29731 { 0, 0, 0, 0 },
29732 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29733 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8040000 }
29734 },
29735/* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
29736 {
29737 { 0, 0, 0, 0 },
29738 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29739 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8240000 }
29740 },
29741/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29742 {
29743 { 0, 0, 0, 0 },
29744 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29745 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0840000 }
29746 },
29747/* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
29748 {
29749 { 0, 0, 0, 0 },
29750 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29751 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a40000 }
29752 },
29753/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29754 {
29755 { 0, 0, 0, 0 },
29756 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29757 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0040000 }
29758 },
29759/* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
29760 {
29761 { 0, 0, 0, 0 },
29762 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29763 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0240000 }
29764 },
29765/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
29766 {
29767 { 0, 0, 0, 0 },
29768 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29769 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2040000 }
29770 },
29771/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
29772 {
29773 { 0, 0, 0, 0 },
29774 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29775 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2240000 }
29776 },
29777/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
29778 {
29779 { 0, 0, 0, 0 },
29780 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29781 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4040000 }
29782 },
29783/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
29784 {
29785 { 0, 0, 0, 0 },
29786 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29787 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4240000 }
29788 },
29789/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
29790 {
29791 { 0, 0, 0, 0 },
29792 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29793 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6040000 }
29794 },
29795/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
29796 {
29797 { 0, 0, 0, 0 },
29798 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29799 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6240000 }
29800 },
29801/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
29802 {
29803 { 0, 0, 0, 0 },
29804 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
29805 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2840000 }
29806 },
29807/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
29808 {
29809 { 0, 0, 0, 0 },
29810 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
29811 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a40000 }
29812 },
29813/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
29814 {
29815 { 0, 0, 0, 0 },
29816 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
29817 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4840000 }
29818 },
29819/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
29820 {
29821 { 0, 0, 0, 0 },
29822 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
29823 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a40000 }
29824 },
29825/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
29826 {
29827 { 0, 0, 0, 0 },
29828 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
29829 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c40000 }
29830 },
29831/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
29832 {
29833 { 0, 0, 0, 0 },
29834 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
29835 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e40000 }
29836 },
29837/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
29838 {
29839 { 0, 0, 0, 0 },
29840 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
29841 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c40000 }
29842 },
29843/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
29844 {
29845 { 0, 0, 0, 0 },
29846 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
29847 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e40000 }
29848 },
29849/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
29850 {
29851 { 0, 0, 0, 0 },
29852 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
29853 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c40000 }
29854 },
29855/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
29856 {
29857 { 0, 0, 0, 0 },
29858 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
29859 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e40000 }
29860 },
29861/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
29862 {
29863 { 0, 0, 0, 0 },
29864 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
29865 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6840000 }
29866 },
29867/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
29868 {
29869 { 0, 0, 0, 0 },
29870 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
29871 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a40000 }
29872 },
29873/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
29874 {
29875 { 0, 0, 0, 0 },
29876 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29877 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc804 }
29878 },
29879/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
29880 {
29881 { 0, 0, 0, 0 },
29882 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29883 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8824 }
29884 },
29885/* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29886 {
29887 { 0, 0, 0, 0 },
29888 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29889 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8804 }
29890 },
29891/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
29892 {
29893 { 0, 0, 0, 0 },
29894 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29895 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc084 }
29896 },
29897/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
29898 {
29899 { 0, 0, 0, 0 },
29900 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29901 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a4 }
29902 },
29903/* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29904 {
29905 { 0, 0, 0, 0 },
29906 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29907 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8084 }
29908 },
29909/* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
29910 {
29911 { 0, 0, 0, 0 },
29912 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29913 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc004 }
29914 },
29915/* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
29916 {
29917 { 0, 0, 0, 0 },
29918 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29919 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8024 }
29920 },
29921/* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29922 {
29923 { 0, 0, 0, 0 },
29924 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29925 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8004 }
29926 },
29927/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29928 {
29929 { 0, 0, 0, 0 },
29930 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29931 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20400 }
29932 },
29933/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29934 {
29935 { 0, 0, 0, 0 },
29936 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29937 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822400 }
29938 },
29939/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
29940 {
29941 { 0, 0, 0, 0 },
29942 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29943 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820400 }
29944 },
29945/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29946 {
29947 { 0, 0, 0, 0 },
29948 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29949 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4040000 }
29950 },
29951/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29952 {
29953 { 0, 0, 0, 0 },
29954 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29955 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84240000 }
29956 },
29957/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
29958 {
29959 { 0, 0, 0, 0 },
29960 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29961 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84040000 }
29962 },
29963/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29964 {
29965 { 0, 0, 0, 0 },
29966 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29967 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6040000 }
29968 },
29969/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29970 {
29971 { 0, 0, 0, 0 },
29972 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29973 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86240000 }
29974 },
29975/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
29976 {
29977 { 0, 0, 0, 0 },
29978 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29979 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86040000 }
29980 },
29981/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
29982 {
29983 { 0, 0, 0, 0 },
29984 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29985 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28400 }
29986 },
29987/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
29988 {
29989 { 0, 0, 0, 0 },
29990 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29991 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a400 }
29992 },
29993/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
29994 {
29995 { 0, 0, 0, 0 },
29996 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29997 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828400 }
29998 },
29999/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
30000 {
30001 { 0, 0, 0, 0 },
30002 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30003 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4840000 }
30004 },
30005/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
30006 {
30007 { 0, 0, 0, 0 },
30008 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30009 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a40000 }
30010 },
30011/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
30012 {
30013 { 0, 0, 0, 0 },
30014 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30015 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84840000 }
30016 },
30017/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
30018 {
30019 { 0, 0, 0, 0 },
30020 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30021 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c400 }
30022 },
30023/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
30024 {
30025 { 0, 0, 0, 0 },
30026 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30027 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e400 }
30028 },
30029/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
30030 {
30031 { 0, 0, 0, 0 },
30032 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30033 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c400 }
30034 },
30035/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
30036 {
30037 { 0, 0, 0, 0 },
30038 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30039 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c40000 }
30040 },
30041/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
30042 {
30043 { 0, 0, 0, 0 },
30044 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30045 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e40000 }
30046 },
30047/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
30048 {
30049 { 0, 0, 0, 0 },
30050 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30051 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c40000 }
30052 },
30053/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
30054 {
30055 { 0, 0, 0, 0 },
30056 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
30057 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c40000 }
30058 },
30059/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
30060 {
30061 { 0, 0, 0, 0 },
30062 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
30063 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e40000 }
30064 },
30065/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
30066 {
30067 { 0, 0, 0, 0 },
30068 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
30069 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c40000 }
30070 },
30071/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
30072 {
30073 { 0, 0, 0, 0 },
30074 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
30075 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6840000 }
30076 },
30077/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
30078 {
30079 { 0, 0, 0, 0 },
30080 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
30081 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a40000 }
30082 },
30083/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
30084 {
30085 { 0, 0, 0, 0 },
30086 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
30087 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86840000 }
30088 },
30089/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
30090 {
30091 { 0, 0, 0, 0 },
30092 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30093 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x718000 }
30094 },
30095/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
30096 {
30097 { 0, 0, 0, 0 },
30098 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
30099 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x71a000 }
30100 },
30101/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
30102 {
30103 { 0, 0, 0, 0 },
30104 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
30105 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x71b000 }
30106 },
30107/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
30108 {
30109 { 0, 0, 0, 0 },
30110 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30111 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x718400 }
30112 },
30113/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
30114 {
30115 { 0, 0, 0, 0 },
30116 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
30117 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x71a400 }
30118 },
30119/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
30120 {
30121 { 0, 0, 0, 0 },
30122 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
30123 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x71b400 }
30124 },
30125/* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
30126 {
30127 { 0, 0, 0, 0 },
30128 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30129 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x718600 }
30130 },
30131/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
30132 {
30133 { 0, 0, 0, 0 },
30134 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30135 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x71a600 }
30136 },
30137/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
30138 {
30139 { 0, 0, 0, 0 },
30140 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30141 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x71b600 }
30142 },
30143/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
30144 {
30145 { 0, 0, 0, 0 },
30146 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30147 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x71880000 }
30148 },
30149/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
30150 {
30151 { 0, 0, 0, 0 },
30152 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30153 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x71a80000 }
30154 },
30155/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
30156 {
30157 { 0, 0, 0, 0 },
30158 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30159 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x71b80000 }
30160 },
30161/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
30162 {
30163 { 0, 0, 0, 0 },
30164 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30165 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x718c0000 }
30166 },
30167/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
30168 {
30169 { 0, 0, 0, 0 },
30170 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30171 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x71ac0000 }
30172 },
30173/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
30174 {
30175 { 0, 0, 0, 0 },
30176 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30177 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x71bc0000 }
30178 },
30179/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
30180 {
30181 { 0, 0, 0, 0 },
30182 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30183 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x718a0000 }
30184 },
30185/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
30186 {
30187 { 0, 0, 0, 0 },
30188 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30189 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71aa0000 }
30190 },
30191/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
30192 {
30193 { 0, 0, 0, 0 },
30194 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30195 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71ba0000 }
30196 },
30197/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
30198 {
30199 { 0, 0, 0, 0 },
30200 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30201 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x718e0000 }
30202 },
30203/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
30204 {
30205 { 0, 0, 0, 0 },
30206 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30207 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71ae0000 }
30208 },
30209/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
30210 {
30211 { 0, 0, 0, 0 },
30212 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30213 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71be0000 }
30214 },
30215/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
30216 {
30217 { 0, 0, 0, 0 },
30218 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30219 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x718b0000 }
30220 },
30221/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
30222 {
30223 { 0, 0, 0, 0 },
30224 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30225 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71ab0000 }
30226 },
30227/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
30228 {
30229 { 0, 0, 0, 0 },
30230 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30231 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71bb0000 }
30232 },
30233/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
30234 {
30235 { 0, 0, 0, 0 },
30236 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
30237 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x718f0000 }
30238 },
30239/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
30240 {
30241 { 0, 0, 0, 0 },
30242 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30243 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x71af0000 }
30244 },
30245/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
30246 {
30247 { 0, 0, 0, 0 },
30248 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30249 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x71bf0000 }
30250 },
30251/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
30252 {
30253 { 0, 0, 0, 0 },
30254 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30255 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x71c00000 }
30256 },
30257/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
30258 {
30259 { 0, 0, 0, 0 },
30260 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
30261 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x71e00000 }
30262 },
30263/* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
30264 {
30265 { 0, 0, 0, 0 },
30266 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
30267 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x71f00000 }
30268 },
30269/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
30270 {
30271 { 0, 0, 0, 0 },
30272 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30273 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x71c40000 }
30274 },
30275/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
30276 {
30277 { 0, 0, 0, 0 },
30278 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
30279 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x71e40000 }
30280 },
30281/* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
30282 {
30283 { 0, 0, 0, 0 },
30284 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
30285 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x71f40000 }
30286 },
30287/* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
30288 {
30289 { 0, 0, 0, 0 },
30290 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30291 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x71c60000 }
30292 },
30293/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
30294 {
30295 { 0, 0, 0, 0 },
30296 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30297 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x71e60000 }
30298 },
30299/* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
30300 {
30301 { 0, 0, 0, 0 },
30302 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
30303 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x71f60000 }
30304 },
30305/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
30306 {
30307 { 0, 0, 0, 0 },
30308 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30309 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x71c80000 }
30310 },
30311/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
30312 {
30313 { 0, 0, 0, 0 },
30314 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30315 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x71e80000 }
30316 },
30317/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
30318 {
30319 { 0, 0, 0, 0 },
30320 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30321 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x71f80000 }
30322 },
30323/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
30324 {
30325 { 0, 0, 0, 0 },
30326 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30327 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x71cc0000 }
30328 },
30329/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
30330 {
30331 { 0, 0, 0, 0 },
30332 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30333 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x71ec0000 }
30334 },
30335/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
30336 {
30337 { 0, 0, 0, 0 },
30338 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30339 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x71fc0000 }
30340 },
30341/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
30342 {
30343 { 0, 0, 0, 0 },
30344 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30345 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ca0000 }
30346 },
30347/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
30348 {
30349 { 0, 0, 0, 0 },
30350 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30351 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ea0000 }
30352 },
30353/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
30354 {
30355 { 0, 0, 0, 0 },
30356 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30357 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x71fa0000 }
30358 },
30359/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
30360 {
30361 { 0, 0, 0, 0 },
30362 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30363 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ce0000 }
30364 },
30365/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
30366 {
30367 { 0, 0, 0, 0 },
30368 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30369 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ee0000 }
30370 },
30371/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
30372 {
30373 { 0, 0, 0, 0 },
30374 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30375 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x71fe0000 }
30376 },
30377/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
30378 {
30379 { 0, 0, 0, 0 },
30380 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30381 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x71cb0000 }
30382 },
30383/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
30384 {
30385 { 0, 0, 0, 0 },
30386 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30387 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x71eb0000 }
30388 },
30389/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
30390 {
30391 { 0, 0, 0, 0 },
30392 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30393 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x71fb0000 }
30394 },
30395/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
30396 {
30397 { 0, 0, 0, 0 },
30398 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
30399 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x71cf0000 }
30400 },
30401/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
30402 {
30403 { 0, 0, 0, 0 },
30404 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
30405 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x71ef0000 }
30406 },
30407/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
30408 {
30409 { 0, 0, 0, 0 },
30410 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
30411 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x71ff0000 }
30412 },
30413/* mulu.w${G} $Src16RnHI,$Dst16RnHI */
30414 {
30415 { 0, 0, 0, 0 },
30416 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
30417 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7100 }
30418 },
30419/* mulu.w${G} $Src16AnHI,$Dst16RnHI */
30420 {
30421 { 0, 0, 0, 0 },
30422 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
30423 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7140 }
30424 },
30425/* mulu.w${G} [$Src16An],$Dst16RnHI */
30426 {
30427 { 0, 0, 0, 0 },
30428 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30429 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7160 }
30430 },
30431/* mulu.w${G} $Src16RnHI,$Dst16AnHI */
30432 {
30433 { 0, 0, 0, 0 },
30434 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
30435 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7104 }
30436 },
30437/* mulu.w${G} $Src16AnHI,$Dst16AnHI */
30438 {
30439 { 0, 0, 0, 0 },
30440 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
30441 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7144 }
30442 },
30443/* mulu.w${G} [$Src16An],$Dst16AnHI */
30444 {
30445 { 0, 0, 0, 0 },
30446 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30447 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7164 }
30448 },
30449/* mulu.w${G} $Src16RnHI,[$Dst16An] */
30450 {
30451 { 0, 0, 0, 0 },
30452 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
30453 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7106 }
30454 },
30455/* mulu.w${G} $Src16AnHI,[$Dst16An] */
30456 {
30457 { 0, 0, 0, 0 },
30458 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
30459 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7146 }
30460 },
30461/* mulu.w${G} [$Src16An],[$Dst16An] */
30462 {
30463 { 0, 0, 0, 0 },
30464 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30465 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7166 }
30466 },
30467/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
30468 {
30469 { 0, 0, 0, 0 },
30470 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30471 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x710800 }
30472 },
30473/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
30474 {
30475 { 0, 0, 0, 0 },
30476 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30477 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x714800 }
30478 },
30479/* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
30480 {
30481 { 0, 0, 0, 0 },
30482 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30483 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x716800 }
30484 },
30485/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
30486 {
30487 { 0, 0, 0, 0 },
30488 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30489 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x710c0000 }
30490 },
30491/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
30492 {
30493 { 0, 0, 0, 0 },
30494 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30495 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x714c0000 }
30496 },
30497/* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
30498 {
30499 { 0, 0, 0, 0 },
30500 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30501 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x716c0000 }
30502 },
30503/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
30504 {
30505 { 0, 0, 0, 0 },
30506 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30507 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x710a00 }
30508 },
30509/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
30510 {
30511 { 0, 0, 0, 0 },
30512 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30513 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x714a00 }
30514 },
30515/* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
30516 {
30517 { 0, 0, 0, 0 },
30518 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30519 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x716a00 }
30520 },
30521/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
30522 {
30523 { 0, 0, 0, 0 },
30524 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30525 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x710e0000 }
30526 },
30527/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
30528 {
30529 { 0, 0, 0, 0 },
30530 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30531 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x714e0000 }
30532 },
30533/* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
30534 {
30535 { 0, 0, 0, 0 },
30536 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30537 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x716e0000 }
30538 },
30539/* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
30540 {
30541 { 0, 0, 0, 0 },
30542 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30543 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x710b00 }
30544 },
30545/* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
30546 {
30547 { 0, 0, 0, 0 },
30548 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30549 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x714b00 }
30550 },
30551/* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
30552 {
30553 { 0, 0, 0, 0 },
30554 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30555 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x716b00 }
30556 },
30557/* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
30558 {
30559 { 0, 0, 0, 0 },
30560 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
30561 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x710f0000 }
30562 },
30563/* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
30564 {
30565 { 0, 0, 0, 0 },
30566 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
30567 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x714f0000 }
30568 },
30569/* mulu.w${G} [$Src16An],${Dsp-16-u16} */
30570 {
30571 { 0, 0, 0, 0 },
30572 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
30573 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x716f0000 }
30574 },
30575/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
30576 {
30577 { 0, 0, 0, 0 },
30578 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30579 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x708000 }
30580 },
30581/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
30582 {
30583 { 0, 0, 0, 0 },
30584 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
30585 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x70a000 }
30586 },
30587/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
30588 {
30589 { 0, 0, 0, 0 },
30590 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
30591 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x70b000 }
30592 },
30593/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
30594 {
30595 { 0, 0, 0, 0 },
30596 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30597 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x708400 }
30598 },
30599/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
30600 {
30601 { 0, 0, 0, 0 },
30602 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
30603 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x70a400 }
30604 },
30605/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
30606 {
30607 { 0, 0, 0, 0 },
30608 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
30609 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x70b400 }
30610 },
30611/* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
30612 {
30613 { 0, 0, 0, 0 },
30614 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30615 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x708600 }
30616 },
30617/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
30618 {
30619 { 0, 0, 0, 0 },
30620 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30621 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x70a600 }
30622 },
30623/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
30624 {
30625 { 0, 0, 0, 0 },
30626 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30627 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x70b600 }
30628 },
30629/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
30630 {
30631 { 0, 0, 0, 0 },
30632 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30633 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x70880000 }
30634 },
30635/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
30636 {
30637 { 0, 0, 0, 0 },
30638 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30639 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x70a80000 }
30640 },
30641/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
30642 {
30643 { 0, 0, 0, 0 },
30644 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30645 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x70b80000 }
30646 },
30647/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
30648 {
30649 { 0, 0, 0, 0 },
30650 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30651 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x708c0000 }
30652 },
30653/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
30654 {
30655 { 0, 0, 0, 0 },
30656 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30657 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x70ac0000 }
30658 },
30659/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
30660 {
30661 { 0, 0, 0, 0 },
30662 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30663 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x70bc0000 }
30664 },
30665/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
30666 {
30667 { 0, 0, 0, 0 },
30668 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30669 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x708a0000 }
30670 },
30671/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
30672 {
30673 { 0, 0, 0, 0 },
30674 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30675 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70aa0000 }
30676 },
30677/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
30678 {
30679 { 0, 0, 0, 0 },
30680 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30681 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70ba0000 }
30682 },
30683/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
30684 {
30685 { 0, 0, 0, 0 },
30686 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30687 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x708e0000 }
30688 },
30689/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
30690 {
30691 { 0, 0, 0, 0 },
30692 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30693 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70ae0000 }
30694 },
30695/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
30696 {
30697 { 0, 0, 0, 0 },
30698 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30699 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70be0000 }
30700 },
30701/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
30702 {
30703 { 0, 0, 0, 0 },
30704 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30705 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x708b0000 }
30706 },
30707/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
30708 {
30709 { 0, 0, 0, 0 },
30710 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30711 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70ab0000 }
30712 },
30713/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
30714 {
30715 { 0, 0, 0, 0 },
30716 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30717 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70bb0000 }
30718 },
30719/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
30720 {
30721 { 0, 0, 0, 0 },
30722 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
30723 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x708f0000 }
30724 },
30725/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
30726 {
30727 { 0, 0, 0, 0 },
30728 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30729 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x70af0000 }
30730 },
30731/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
30732 {
30733 { 0, 0, 0, 0 },
30734 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30735 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x70bf0000 }
30736 },
30737/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
30738 {
30739 { 0, 0, 0, 0 },
30740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30741 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x70c00000 }
30742 },
30743/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
30744 {
30745 { 0, 0, 0, 0 },
30746 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
30747 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x70e00000 }
30748 },
30749/* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
30750 {
30751 { 0, 0, 0, 0 },
30752 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
30753 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x70f00000 }
30754 },
30755/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
30756 {
30757 { 0, 0, 0, 0 },
30758 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30759 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x70c40000 }
30760 },
30761/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
30762 {
30763 { 0, 0, 0, 0 },
30764 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
30765 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x70e40000 }
30766 },
30767/* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
30768 {
30769 { 0, 0, 0, 0 },
30770 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
30771 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x70f40000 }
30772 },
30773/* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
30774 {
30775 { 0, 0, 0, 0 },
30776 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30777 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x70c60000 }
30778 },
30779/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
30780 {
30781 { 0, 0, 0, 0 },
30782 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30783 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x70e60000 }
30784 },
30785/* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
30786 {
30787 { 0, 0, 0, 0 },
30788 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
30789 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x70f60000 }
30790 },
30791/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
30792 {
30793 { 0, 0, 0, 0 },
30794 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30795 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x70c80000 }
30796 },
30797/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
30798 {
30799 { 0, 0, 0, 0 },
30800 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30801 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x70e80000 }
30802 },
30803/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
30804 {
30805 { 0, 0, 0, 0 },
30806 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30807 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x70f80000 }
30808 },
30809/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
30810 {
30811 { 0, 0, 0, 0 },
30812 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30813 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x70cc0000 }
30814 },
30815/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
30816 {
30817 { 0, 0, 0, 0 },
30818 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30819 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x70ec0000 }
30820 },
30821/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
30822 {
30823 { 0, 0, 0, 0 },
30824 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30825 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x70fc0000 }
30826 },
30827/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
30828 {
30829 { 0, 0, 0, 0 },
30830 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30831 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ca0000 }
30832 },
30833/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
30834 {
30835 { 0, 0, 0, 0 },
30836 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30837 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ea0000 }
30838 },
30839/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
30840 {
30841 { 0, 0, 0, 0 },
30842 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30843 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x70fa0000 }
30844 },
30845/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
30846 {
30847 { 0, 0, 0, 0 },
30848 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30849 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ce0000 }
30850 },
30851/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
30852 {
30853 { 0, 0, 0, 0 },
30854 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30855 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ee0000 }
30856 },
30857/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
30858 {
30859 { 0, 0, 0, 0 },
30860 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30861 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x70fe0000 }
30862 },
30863/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
30864 {
30865 { 0, 0, 0, 0 },
30866 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30867 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x70cb0000 }
30868 },
30869/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
30870 {
30871 { 0, 0, 0, 0 },
30872 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30873 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x70eb0000 }
30874 },
30875/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
30876 {
30877 { 0, 0, 0, 0 },
30878 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30879 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x70fb0000 }
30880 },
30881/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
30882 {
30883 { 0, 0, 0, 0 },
30884 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
30885 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x70cf0000 }
30886 },
30887/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
30888 {
30889 { 0, 0, 0, 0 },
30890 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
30891 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x70ef0000 }
30892 },
30893/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
30894 {
30895 { 0, 0, 0, 0 },
30896 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
30897 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x70ff0000 }
30898 },
30899/* mulu.b${G} $Src16RnQI,$Dst16RnQI */
30900 {
30901 { 0, 0, 0, 0 },
30902 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
30903 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7000 }
30904 },
30905/* mulu.b${G} $Src16AnQI,$Dst16RnQI */
30906 {
30907 { 0, 0, 0, 0 },
30908 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
30909 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7040 }
30910 },
30911/* mulu.b${G} [$Src16An],$Dst16RnQI */
30912 {
30913 { 0, 0, 0, 0 },
30914 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30915 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7060 }
30916 },
30917/* mulu.b${G} $Src16RnQI,$Dst16AnQI */
30918 {
30919 { 0, 0, 0, 0 },
30920 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
30921 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7004 }
30922 },
30923/* mulu.b${G} $Src16AnQI,$Dst16AnQI */
30924 {
30925 { 0, 0, 0, 0 },
30926 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
30927 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7044 }
30928 },
30929/* mulu.b${G} [$Src16An],$Dst16AnQI */
30930 {
30931 { 0, 0, 0, 0 },
30932 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30933 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7064 }
30934 },
30935/* mulu.b${G} $Src16RnQI,[$Dst16An] */
30936 {
30937 { 0, 0, 0, 0 },
30938 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
30939 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7006 }
30940 },
30941/* mulu.b${G} $Src16AnQI,[$Dst16An] */
30942 {
30943 { 0, 0, 0, 0 },
30944 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
30945 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7046 }
30946 },
30947/* mulu.b${G} [$Src16An],[$Dst16An] */
30948 {
30949 { 0, 0, 0, 0 },
30950 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30951 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7066 }
30952 },
30953/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
30954 {
30955 { 0, 0, 0, 0 },
30956 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30957 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x700800 }
30958 },
30959/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
30960 {
30961 { 0, 0, 0, 0 },
30962 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30963 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x704800 }
30964 },
30965/* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
30966 {
30967 { 0, 0, 0, 0 },
30968 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30969 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x706800 }
30970 },
30971/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
30972 {
30973 { 0, 0, 0, 0 },
30974 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30975 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x700c0000 }
30976 },
30977/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
30978 {
30979 { 0, 0, 0, 0 },
30980 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30981 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x704c0000 }
30982 },
30983/* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
30984 {
30985 { 0, 0, 0, 0 },
30986 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30987 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x706c0000 }
30988 },
30989/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
30990 {
30991 { 0, 0, 0, 0 },
30992 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30993 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x700a00 }
30994 },
30995/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
30996 {
30997 { 0, 0, 0, 0 },
30998 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30999 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x704a00 }
31000 },
31001/* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
31002 {
31003 { 0, 0, 0, 0 },
31004 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31005 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x706a00 }
31006 },
31007/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
31008 {
31009 { 0, 0, 0, 0 },
31010 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31011 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x700e0000 }
31012 },
31013/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
31014 {
31015 { 0, 0, 0, 0 },
31016 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31017 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x704e0000 }
31018 },
31019/* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
31020 {
31021 { 0, 0, 0, 0 },
31022 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31023 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x706e0000 }
31024 },
31025/* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
31026 {
31027 { 0, 0, 0, 0 },
31028 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31029 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x700b00 }
31030 },
31031/* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
31032 {
31033 { 0, 0, 0, 0 },
31034 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31035 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x704b00 }
31036 },
31037/* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
31038 {
31039 { 0, 0, 0, 0 },
31040 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31041 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x706b00 }
31042 },
31043/* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
31044 {
31045 { 0, 0, 0, 0 },
31046 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
31047 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x700f0000 }
31048 },
31049/* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
31050 {
31051 { 0, 0, 0, 0 },
31052 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
31053 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x704f0000 }
31054 },
31055/* mulu.b${G} [$Src16An],${Dsp-16-u16} */
31056 {
31057 { 0, 0, 0, 0 },
31058 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
31059 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x706f0000 }
31060 },
31061/* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
31062 {
31063 { 0, 0, 0, 0 },
31064 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31065 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x890f0000 }
31066 },
31067/* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
31068 {
31069 { 0, 0, 0, 0 },
31070 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31071 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x818f0000 }
31072 },
31073/* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
31074 {
31075 { 0, 0, 0, 0 },
31076 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31077 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x810f0000 }
31078 },
31079/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
31080 {
31081 { 0, 0, 0, 0 },
31082 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31083 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x830f0000 }
31084 },
31085/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
31086 {
31087 { 0, 0, 0, 0 },
31088 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31089 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838f0000 }
31090 },
31091/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
31092 {
31093 { 0, 0, 0, 0 },
31094 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31095 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cf0000 }
31096 },
31097/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
31098 {
31099 { 0, 0, 0, 0 },
31100 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31101 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x850f0000 }
31102 },
31103/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
31104 {
31105 { 0, 0, 0, 0 },
31106 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31107 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858f0000 }
31108 },
31109/* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
31110 {
31111 { 0, 0, 0, 0 },
31112 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31113 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cf0000 }
31114 },
31115/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
31116 {
31117 { 0, 0, 0, 0 },
31118 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
31119 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87cf0000 }
31120 },
31121/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
31122 {
31123 { 0, 0, 0, 0 },
31124 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31125 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x870f0000 }
31126 },
31127/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
31128 {
31129 { 0, 0, 0, 0 },
31130 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
31131 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x878f0000 }
31132 },
31133/* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
31134 {
31135 { 0, 0, 0, 0 },
31136 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
31137 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x880f00 }
31138 },
31139/* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
31140 {
31141 { 0, 0, 0, 0 },
31142 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
31143 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x808f00 }
31144 },
31145/* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
31146 {
31147 { 0, 0, 0, 0 },
31148 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31149 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x800f00 }
31150 },
31151/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
31152 {
31153 { 0, 0, 0, 0 },
31154 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31155 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x820f0000 }
31156 },
31157/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
31158 {
31159 { 0, 0, 0, 0 },
31160 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31161 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828f0000 }
31162 },
31163/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
31164 {
31165 { 0, 0, 0, 0 },
31166 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31167 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cf0000 }
31168 },
31169/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
31170 {
31171 { 0, 0, 0, 0 },
31172 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31173 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x840f0000 }
31174 },
31175/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
31176 {
31177 { 0, 0, 0, 0 },
31178 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31179 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848f0000 }
31180 },
31181/* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
31182 {
31183 { 0, 0, 0, 0 },
31184 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31185 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cf0000 }
31186 },
31187/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
31188 {
31189 { 0, 0, 0, 0 },
31190 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
31191 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86cf0000 }
31192 },
31193/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
31194 {
31195 { 0, 0, 0, 0 },
31196 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31197 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x860f0000 }
31198 },
31199/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
31200 {
31201 { 0, 0, 0, 0 },
31202 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
31203 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x868f0000 }
31204 },
31205/* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
31206 {
31207 { 0, 0, 0, 0 },
31208 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
31209 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d400000 }
31210 },
31211/* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
31212 {
31213 { 0, 0, 0, 0 },
31214 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
31215 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d440000 }
31216 },
31217/* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
31218 {
31219 { 0, 0, 0, 0 },
31220 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
31221 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d460000 }
31222 },
31223/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
31224 {
31225 { 0, 0, 0, 0 },
31226 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
31227 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d480000 }
31228 },
31229/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
31230 {
31231 { 0, 0, 0, 0 },
31232 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31233 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d4a0000 }
31234 },
31235/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
31236 {
31237 { 0, 0, 0, 0 },
31238 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31239 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d4b0000 }
31240 },
31241/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
31242 {
31243 { 0, 0, 0, 0 },
31244 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
31245 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d4c0000 }
31246 },
31247/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
31248 {
31249 { 0, 0, 0, 0 },
31250 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31251 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d4e0000 }
31252 },
31253/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
31254 {
31255 { 0, 0, 0, 0 },
31256 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
31257 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d4f0000 }
31258 },
31259/* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
31260 {
31261 { 0, 0, 0, 0 },
31262 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
31263 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c4000 }
31264 },
31265/* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
31266 {
31267 { 0, 0, 0, 0 },
31268 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
31269 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c4400 }
31270 },
31271/* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
31272 {
31273 { 0, 0, 0, 0 },
31274 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
31275 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c4600 }
31276 },
31277/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
31278 {
31279 { 0, 0, 0, 0 },
31280 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
31281 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c480000 }
31282 },
31283/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
31284 {
31285 { 0, 0, 0, 0 },
31286 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31287 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c4a0000 }
31288 },
31289/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
31290 {
31291 { 0, 0, 0, 0 },
31292 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31293 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c4b0000 }
31294 },
31295/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
31296 {
31297 { 0, 0, 0, 0 },
31298 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
31299 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c4c0000 }
31300 },
31301/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
31302 {
31303 { 0, 0, 0, 0 },
31304 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31305 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c4e0000 }
31306 },
31307/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
31308 {
31309 { 0, 0, 0, 0 },
31310 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
31311 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c4f0000 }
31312 },
31313/* mulex $R3 */
31314 {
31315 { 0, 0, 0, 0 },
31316 { { MNEM, ' ', OP (R3), 0 } },
31317 & ifmt_mulex_dst32_R3_direct_Unprefixed_HI, { 0xc97e }
31318 },
31319/* mulex $Dst32AnUnprefixedHI */
31320 {
31321 { 0, 0, 0, 0 },
31322 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
31323 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1be }
31324 },
31325/* mulex [$Dst32AnUnprefixed] */
31326 {
31327 { 0, 0, 0, 0 },
31328 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31329 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc13e }
31330 },
31331/* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
31332 {
31333 { 0, 0, 0, 0 },
31334 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31335 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33e00 }
31336 },
31337/* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
31338 {
31339 { 0, 0, 0, 0 },
31340 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31341 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc53e0000 }
31342 },
31343/* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
31344 {
31345 { 0, 0, 0, 0 },
31346 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31347 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc73e0000 }
31348 },
31349/* mulex ${Dsp-16-u8}[sb] */
31350 {
31351 { 0, 0, 0, 0 },
31352 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31353 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3be00 }
31354 },
31355/* mulex ${Dsp-16-u16}[sb] */
31356 {
31357 { 0, 0, 0, 0 },
31358 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31359 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5be0000 }
31360 },
31361/* mulex ${Dsp-16-s8}[fb] */
31362 {
31363 { 0, 0, 0, 0 },
31364 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31365 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3fe00 }
31366 },
31367/* mulex ${Dsp-16-s16}[fb] */
31368 {
31369 { 0, 0, 0, 0 },
31370 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31371 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5fe0000 }
31372 },
31373/* mulex ${Dsp-16-u16} */
31374 {
31375 { 0, 0, 0, 0 },
31376 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
31377 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7fe0000 }
31378 },
31379/* mulex ${Dsp-16-u24} */
31380 {
31381 { 0, 0, 0, 0 },
31382 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
31383 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7be0000 }
31384 },
253d272c
DD		 31385/* mulu.l $Dst32RnPrefixedSI,r2r0 */
31386 {
31387 { 0, 0, 0, 0 },
31388 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31389 & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1890f }
31390 },
31391/* mulu.l $Dst32AnPrefixedSI,r2r0 */
31392 {
31393 { 0, 0, 0, 0 },
31394 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31395 & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1818f }
31396 },
31397/* mulu.l [$Dst32AnPrefixed],r2r0 */
31398 {
31399 { 0, 0, 0, 0 },
31400 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31401 & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1810f }
31402 },
31403/* mulu.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */
31404 {
31405 { 0, 0, 0, 0 },
31406 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31407 & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1830f00 }
31408 },
31409/* mulu.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */
31410 {
31411 { 0, 0, 0, 0 },
31412 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31413 & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1850f00 }
31414 },
31415/* mulu.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */
31416 {
31417 { 0, 0, 0, 0 },
31418 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31419 & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1870f00 }
31420 },
31421/* mulu.l ${Dsp-24-u8}[sb],r2r0 */
31422 {
31423 { 0, 0, 0, 0 },
31424 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31425 & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1838f00 }
31426 },
31427/* mulu.l ${Dsp-24-u16}[sb],r2r0 */
31428 {
31429 { 0, 0, 0, 0 },
31430 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31431 & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1858f00 }
31432 },
31433/* mulu.l ${Dsp-24-s8}[fb],r2r0 */
31434 {
31435 { 0, 0, 0, 0 },
31436 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31437 & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x183cf00 }
31438 },
31439/* mulu.l ${Dsp-24-s16}[fb],r2r0 */
31440 {
31441 { 0, 0, 0, 0 },
31442 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31443 & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x185cf00 }
31444 },
31445/* mulu.l ${Dsp-24-u16},r2r0 */
31446 {
31447 { 0, 0, 0, 0 },
31448 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '2', 'r', '0', 0 } },
31449 & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x187cf00 }
31450 },
31451/* mulu.l ${Dsp-24-u24},r2r0 */
31452 {
31453 { 0, 0, 0, 0 },
31454 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '2', 'r', '0', 0 } },
31455 & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1878f00 }
31456 },
31457/* mul.l $Dst32RnPrefixedSI,r2r0 */
31458 {
31459 { 0, 0, 0, 0 },
31460 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31461 & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1891f }
31462 },
31463/* mul.l $Dst32AnPrefixedSI,r2r0 */
31464 {
31465 { 0, 0, 0, 0 },
31466 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31467 & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1819f }
31468 },
31469/* mul.l [$Dst32AnPrefixed],r2r0 */
31470 {
31471 { 0, 0, 0, 0 },
31472 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31473 & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1811f }
31474 },
31475/* mul.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */
31476 {
31477 { 0, 0, 0, 0 },
31478 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31479 & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1831f00 }
31480 },
31481/* mul.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */
31482 {
31483 { 0, 0, 0, 0 },
31484 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31485 & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1851f00 }
31486 },
31487/* mul.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */
31488 {
31489 { 0, 0, 0, 0 },
31490 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31491 & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1871f00 }
31492 },
31493/* mul.l ${Dsp-24-u8}[sb],r2r0 */
31494 {
31495 { 0, 0, 0, 0 },
31496 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31497 & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1839f00 }
31498 },
31499/* mul.l ${Dsp-24-u16}[sb],r2r0 */
31500 {
31501 { 0, 0, 0, 0 },
31502 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31503 & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1859f00 }
31504 },
31505/* mul.l ${Dsp-24-s8}[fb],r2r0 */
31506 {
31507 { 0, 0, 0, 0 },
31508 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31509 & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x183df00 }
31510 },
31511/* mul.l ${Dsp-24-s16}[fb],r2r0 */
31512 {
31513 { 0, 0, 0, 0 },
31514 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31515 & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x185df00 }
31516 },
31517/* mul.l ${Dsp-24-u16},r2r0 */
31518 {
31519 { 0, 0, 0, 0 },
31520 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '2', 'r', '0', 0 } },
31521 & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x187df00 }
31522 },
31523/* mul.l ${Dsp-24-u24},r2r0 */
31524 {
31525 { 0, 0, 0, 0 },
31526 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '2', 'r', '0', 0 } },
31527 & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1879f00 }
31528 },
49f58d10
JB		 31529/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31530 {
31531 { 0, 0, 0, 0 },
31532 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31533 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990c00 }
31534 },
31535/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
31536 {
31537 { 0, 0, 0, 0 },
31538 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31539 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992c00 }
31540 },
31541/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
31542 {
31543 { 0, 0, 0, 0 },
31544 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31545 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993c00 }
31546 },
31547/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31548 {
31549 { 0, 0, 0, 0 },
31550 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31551 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918c00 }
31552 },
31553/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
31554 {
31555 { 0, 0, 0, 0 },
31556 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31557 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ac00 }
31558 },
31559/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
31560 {
31561 { 0, 0, 0, 0 },
31562 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31563 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bc00 }
31564 },
31565/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31566 {
31567 { 0, 0, 0, 0 },
31568 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31569 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910c00 }
31570 },
31571/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
31572 {
31573 { 0, 0, 0, 0 },
31574 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31575 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912c00 }
31576 },
31577/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
31578 {
31579 { 0, 0, 0, 0 },
31580 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31581 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913c00 }
31582 },
31583/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31584 {
31585 { 0, 0, 0, 0 },
31586 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31587 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930c0000 }
31588 },
31589/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31590 {
31591 { 0, 0, 0, 0 },
31592 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31593 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932c0000 }
31594 },
31595/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31596 {
31597 { 0, 0, 0, 0 },
31598 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31599 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933c0000 }
31600 },
31601/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31602 {
31603 { 0, 0, 0, 0 },
31604 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31605 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950c0000 }
31606 },
31607/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31608 {
31609 { 0, 0, 0, 0 },
31610 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31611 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952c0000 }
31612 },
31613/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31614 {
31615 { 0, 0, 0, 0 },
31616 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31617 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953c0000 }
31618 },
31619/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31620 {
31621 { 0, 0, 0, 0 },
31622 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31623 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970c0000 }
31624 },
31625/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31626 {
31627 { 0, 0, 0, 0 },
31628 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31629 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972c0000 }
31630 },
31631/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31632 {
31633 { 0, 0, 0, 0 },
31634 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31635 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973c0000 }
31636 },
31637/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
31638 {
31639 { 0, 0, 0, 0 },
31640 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31641 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938c0000 }
31642 },
31643/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
31644 {
31645 { 0, 0, 0, 0 },
31646 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31647 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ac0000 }
31648 },
31649/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
31650 {
31651 { 0, 0, 0, 0 },
31652 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31653 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bc0000 }
31654 },
31655/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
31656 {
31657 { 0, 0, 0, 0 },
31658 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31659 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958c0000 }
31660 },
31661/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
31662 {
31663 { 0, 0, 0, 0 },
31664 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31665 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ac0000 }
31666 },
31667/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
31668 {
31669 { 0, 0, 0, 0 },
31670 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31671 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bc0000 }
31672 },
31673/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
31674 {
31675 { 0, 0, 0, 0 },
31676 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31677 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cc0000 }
31678 },
31679/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
31680 {
31681 { 0, 0, 0, 0 },
31682 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31683 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ec0000 }
31684 },
31685/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
31686 {
31687 { 0, 0, 0, 0 },
31688 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31689 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fc0000 }
31690 },
31691/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
31692 {
31693 { 0, 0, 0, 0 },
31694 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31695 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cc0000 }
31696 },
31697/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
31698 {
31699 { 0, 0, 0, 0 },
31700 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31701 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ec0000 }
31702 },
31703/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
31704 {
31705 { 0, 0, 0, 0 },
31706 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31707 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fc0000 }
31708 },
31709/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
31710 {
31711 { 0, 0, 0, 0 },
31712 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
31713 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cc0000 }
31714 },
31715/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
31716 {
31717 { 0, 0, 0, 0 },
31718 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
31719 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ec0000 }
31720 },
31721/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
31722 {
31723 { 0, 0, 0, 0 },
31724 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
31725 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fc0000 }
31726 },
31727/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
31728 {
31729 { 0, 0, 0, 0 },
31730 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
31731 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978c0000 }
31732 },
31733/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
31734 {
31735 { 0, 0, 0, 0 },
31736 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
31737 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ac0000 }
31738 },
31739/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
31740 {
31741 { 0, 0, 0, 0 },
31742 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
31743 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bc0000 }
31744 },
31745/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31746 {
31747 { 0, 0, 0, 0 },
31748 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31749 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90c0000 }
31750 },
31751/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
31752 {
31753 { 0, 0, 0, 0 },
31754 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31755 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92c0000 }
31756 },
31757/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
31758 {
31759 { 0, 0, 0, 0 },
31760 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31761 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93c0000 }
31762 },
31763/* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
31764 {
31765 { 0, 0, 0, 0 },
31766 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31767 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93c0000 }
31768 },
31769/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31770 {
31771 { 0, 0, 0, 0 },
31772 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31773 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18c0000 }
31774 },
31775/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
31776 {
31777 { 0, 0, 0, 0 },
31778 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31779 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ac0000 }
31780 },
31781/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
31782 {
31783 { 0, 0, 0, 0 },
31784 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31785 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bc0000 }
31786 },
31787/* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
31788 {
31789 { 0, 0, 0, 0 },
31790 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31791 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bc0000 }
31792 },
31793/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31794 {
31795 { 0, 0, 0, 0 },
31796 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31797 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10c0000 }
31798 },
31799/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
31800 {
31801 { 0, 0, 0, 0 },
31802 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31803 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12c0000 }
31804 },
31805/* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
31806 {
31807 { 0, 0, 0, 0 },
31808 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31809 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13c0000 }
31810 },
31811/* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
31812 {
31813 { 0, 0, 0, 0 },
31814 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31815 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13c0000 }
31816 },
31817/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31818 {
31819 { 0, 0, 0, 0 },
31820 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31821 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30c0000 }
31822 },
31823/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31824 {
31825 { 0, 0, 0, 0 },
31826 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31827 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32c0000 }
31828 },
31829/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31830 {
31831 { 0, 0, 0, 0 },
31832 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31833 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33c0000 }
31834 },
31835/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
31836 {
31837 { 0, 0, 0, 0 },
31838 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31839 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33c0000 }
31840 },
31841/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31842 {
31843 { 0, 0, 0, 0 },
31844 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31845 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50c0000 }
31846 },
31847/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31848 {
31849 { 0, 0, 0, 0 },
31850 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31851 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52c0000 }
31852 },
31853/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31854 {
31855 { 0, 0, 0, 0 },
31856 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31857 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53c0000 }
31858 },
31859/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
31860 {
31861 { 0, 0, 0, 0 },
31862 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31863 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53c0000 }
31864 },
31865/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31866 {
31867 { 0, 0, 0, 0 },
31868 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31869 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70c0000 }
31870 },
31871/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31872 {
31873 { 0, 0, 0, 0 },
31874 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31875 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72c0000 }
31876 },
31877/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31878 {
31879 { 0, 0, 0, 0 },
31880 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31881 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73c0000 }
31882 },
31883/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
31884 {
31885 { 0, 0, 0, 0 },
31886 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31887 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73c0000 }
31888 },
31889/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
31890 {
31891 { 0, 0, 0, 0 },
31892 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31893 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38c0000 }
31894 },
31895/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
31896 {
31897 { 0, 0, 0, 0 },
31898 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31899 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ac0000 }
31900 },
31901/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
31902 {
31903 { 0, 0, 0, 0 },
31904 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31905 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bc0000 }
31906 },
31907/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
31908 {
31909 { 0, 0, 0, 0 },
31910 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31911 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bc0000 }
31912 },
31913/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
31914 {
31915 { 0, 0, 0, 0 },
31916 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31917 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58c0000 }
31918 },
31919/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
31920 {
31921 { 0, 0, 0, 0 },
31922 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31923 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ac0000 }
31924 },
31925/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
31926 {
31927 { 0, 0, 0, 0 },
31928 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31929 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bc0000 }
31930 },
31931/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
31932 {
31933 { 0, 0, 0, 0 },
31934 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31935 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bc0000 }
31936 },
31937/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
31938 {
31939 { 0, 0, 0, 0 },
31940 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31941 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cc0000 }
31942 },
31943/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
31944 {
31945 { 0, 0, 0, 0 },
31946 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31947 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ec0000 }
31948 },
31949/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
31950 {
31951 { 0, 0, 0, 0 },
31952 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31953 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fc0000 }
31954 },
31955/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
31956 {
31957 { 0, 0, 0, 0 },
31958 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31959 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fc0000 }
31960 },
31961/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
31962 {
31963 { 0, 0, 0, 0 },
31964 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31965 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cc0000 }
31966 },
31967/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
31968 {
31969 { 0, 0, 0, 0 },
31970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31971 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ec0000 }
31972 },
31973/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
31974 {
31975 { 0, 0, 0, 0 },
31976 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31977 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fc0000 }
31978 },
31979/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
31980 {
31981 { 0, 0, 0, 0 },
31982 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31983 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fc0000 }
31984 },
31985/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
31986 {
31987 { 0, 0, 0, 0 },
31988 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
31989 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cc0000 }
31990 },
31991/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
31992 {
31993 { 0, 0, 0, 0 },
31994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
31995 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ec0000 }
31996 },
31997/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
31998 {
31999 { 0, 0, 0, 0 },
32000 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
32001 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fc0000 }
32002 },
32003/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
32004 {
32005 { 0, 0, 0, 0 },
32006 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
32007 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fc0000 }
32008 },
32009/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
32010 {
32011 { 0, 0, 0, 0 },
32012 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
32013 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78c0000 }
32014 },
32015/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
32016 {
32017 { 0, 0, 0, 0 },
32018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32019 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ac0000 }
32020 },
32021/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
32022 {
32023 { 0, 0, 0, 0 },
32024 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32025 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bc0000 }
32026 },
32027/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
32028 {
32029 { 0, 0, 0, 0 },
32030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
32031 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bc0000 }
32032 },
32033/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
32034 {
32035 { 0, 0, 0, 0 },
32036 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32037 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90c0000 }
32038 },
32039/* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
32040 {
32041 { 0, 0, 0, 0 },
32042 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32043 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92c0000 }
32044 },
32045/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
32046 {
32047 { 0, 0, 0, 0 },
32048 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32049 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18c0000 }
32050 },
32051/* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
32052 {
32053 { 0, 0, 0, 0 },
32054 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32055 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ac0000 }
32056 },
32057/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32058 {
32059 { 0, 0, 0, 0 },
32060 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32061 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10c0000 }
32062 },
32063/* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
32064 {
32065 { 0, 0, 0, 0 },
32066 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32067 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12c0000 }
32068 },
32069/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
32070 {
32071 { 0, 0, 0, 0 },
32072 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32073 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30c0000 }
32074 },
32075/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
32076 {
32077 { 0, 0, 0, 0 },
32078 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32079 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32c0000 }
32080 },
32081/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
32082 {
32083 { 0, 0, 0, 0 },
32084 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32085 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50c0000 }
32086 },
32087/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
32088 {
32089 { 0, 0, 0, 0 },
32090 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32091 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52c0000 }
32092 },
32093/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
32094 {
32095 { 0, 0, 0, 0 },
32096 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32097 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70c0000 }
32098 },
32099/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
32100 {
32101 { 0, 0, 0, 0 },
32102 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32103 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72c0000 }
32104 },
32105/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
32106 {
32107 { 0, 0, 0, 0 },
32108 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32109 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38c0000 }
32110 },
32111/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
32112 {
32113 { 0, 0, 0, 0 },
32114 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32115 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ac0000 }
32116 },
32117/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
32118 {
32119 { 0, 0, 0, 0 },
32120 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32121 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58c0000 }
32122 },
32123/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
32124 {
32125 { 0, 0, 0, 0 },
32126 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32127 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ac0000 }
32128 },
32129/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
32130 {
32131 { 0, 0, 0, 0 },
32132 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32133 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cc0000 }
32134 },
32135/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
32136 {
32137 { 0, 0, 0, 0 },
32138 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32139 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ec0000 }
32140 },
32141/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
32142 {
32143 { 0, 0, 0, 0 },
32144 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
32145 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cc0000 }
32146 },
32147/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
32148 {
32149 { 0, 0, 0, 0 },
32150 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
32151 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ec0000 }
32152 },
32153/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
32154 {
32155 { 0, 0, 0, 0 },
32156 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
32157 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cc0000 }
32158 },
32159/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
32160 {
32161 { 0, 0, 0, 0 },
32162 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
32163 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ec0000 }
32164 },
32165/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
32166 {
32167 { 0, 0, 0, 0 },
32168 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
32169 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78c0000 }
32170 },
32171/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
32172 {
32173 { 0, 0, 0, 0 },
32174 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
32175 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ac0000 }
32176 },
32177/* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
32178 {
32179 { 0, 0, 0, 0 },
32180 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32181 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90c }
32182 },
32183/* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
32184 {
32185 { 0, 0, 0, 0 },
32186 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32187 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892c }
32188 },
32189/* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
32190 {
32191 { 0, 0, 0, 0 },
32192 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32193 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890c }
32194 },
32195/* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
32196 {
32197 { 0, 0, 0, 0 },
32198 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32199 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18c }
32200 },
32201/* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
32202 {
32203 { 0, 0, 0, 0 },
32204 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32205 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ac }
32206 },
32207/* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
32208 {
32209 { 0, 0, 0, 0 },
32210 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32211 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818c }
32212 },
32213/* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
32214 {
32215 { 0, 0, 0, 0 },
32216 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32217 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10c }
32218 },
32219/* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
32220 {
32221 { 0, 0, 0, 0 },
32222 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32223 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812c }
32224 },
32225/* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32226 {
32227 { 0, 0, 0, 0 },
32228 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32229 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810c }
32230 },
32231/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
32232 {
32233 { 0, 0, 0, 0 },
32234 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32235 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30c00 }
32236 },
32237/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
32238 {
32239 { 0, 0, 0, 0 },
32240 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32241 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832c00 }
32242 },
32243/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
32244 {
32245 { 0, 0, 0, 0 },
32246 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32247 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830c00 }
32248 },
32249/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
32250 {
32251 { 0, 0, 0, 0 },
32252 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32253 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50c0000 }
32254 },
32255/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
32256 {
32257 { 0, 0, 0, 0 },
32258 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32259 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852c0000 }
32260 },
32261/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
32262 {
32263 { 0, 0, 0, 0 },
32264 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32265 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850c0000 }
32266 },
32267/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
32268 {
32269 { 0, 0, 0, 0 },
32270 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32271 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70c0000 }
32272 },
32273/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
32274 {
32275 { 0, 0, 0, 0 },
32276 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32277 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872c0000 }
32278 },
32279/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
32280 {
32281 { 0, 0, 0, 0 },
32282 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32283 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870c0000 }
32284 },
32285/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
32286 {
32287 { 0, 0, 0, 0 },
32288 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32289 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38c00 }
32290 },
32291/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
32292 {
32293 { 0, 0, 0, 0 },
32294 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32295 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ac00 }
32296 },
32297/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
32298 {
32299 { 0, 0, 0, 0 },
32300 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32301 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838c00 }
32302 },
32303/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
32304 {
32305 { 0, 0, 0, 0 },
32306 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32307 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58c0000 }
32308 },
32309/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
32310 {
32311 { 0, 0, 0, 0 },
32312 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32313 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ac0000 }
32314 },
32315/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
32316 {
32317 { 0, 0, 0, 0 },
32318 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32319 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858c0000 }
32320 },
32321/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
32322 {
32323 { 0, 0, 0, 0 },
32324 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32325 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cc00 }
32326 },
32327/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
32328 {
32329 { 0, 0, 0, 0 },
32330 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32331 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ec00 }
32332 },
32333/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
32334 {
32335 { 0, 0, 0, 0 },
32336 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32337 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cc00 }
32338 },
32339/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
32340 {
32341 { 0, 0, 0, 0 },
32342 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32343 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cc0000 }
32344 },
32345/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
32346 {
32347 { 0, 0, 0, 0 },
32348 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32349 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ec0000 }
32350 },
32351/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
32352 {
32353 { 0, 0, 0, 0 },
32354 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32355 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cc0000 }
32356 },
32357/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
32358 {
32359 { 0, 0, 0, 0 },
32360 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
32361 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cc0000 }
32362 },
32363/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
32364 {
32365 { 0, 0, 0, 0 },
32366 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
32367 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ec0000 }
32368 },
32369/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
32370 {
32371 { 0, 0, 0, 0 },
32372 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
32373 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cc0000 }
32374 },
32375/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
32376 {
32377 { 0, 0, 0, 0 },
32378 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
32379 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78c0000 }
32380 },
32381/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
32382 {
32383 { 0, 0, 0, 0 },
32384 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
32385 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ac0000 }
32386 },
32387/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
32388 {
32389 { 0, 0, 0, 0 },
32390 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
32391 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878c0000 }
32392 },
32393/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32394 {
32395 { 0, 0, 0, 0 },
32396 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32397 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980c00 }
32398 },
32399/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
32400 {
32401 { 0, 0, 0, 0 },
32402 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32403 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982c00 }
32404 },
32405/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
32406 {
32407 { 0, 0, 0, 0 },
32408 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32409 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983c00 }
32410 },
32411/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32412 {
32413 { 0, 0, 0, 0 },
32414 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32415 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908c00 }
32416 },
32417/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
32418 {
32419 { 0, 0, 0, 0 },
32420 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32421 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ac00 }
32422 },
32423/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
32424 {
32425 { 0, 0, 0, 0 },
32426 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32427 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bc00 }
32428 },
32429/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32430 {
32431 { 0, 0, 0, 0 },
32432 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32433 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900c00 }
32434 },
32435/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
32436 {
32437 { 0, 0, 0, 0 },
32438 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32439 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902c00 }
32440 },
32441/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
32442 {
32443 { 0, 0, 0, 0 },
32444 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32445 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903c00 }
32446 },
32447/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32448 {
32449 { 0, 0, 0, 0 },
32450 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32451 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920c0000 }
32452 },
32453/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32454 {
32455 { 0, 0, 0, 0 },
32456 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32457 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922c0000 }
32458 },
32459/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32460 {
32461 { 0, 0, 0, 0 },
32462 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32463 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923c0000 }
32464 },
32465/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32466 {
32467 { 0, 0, 0, 0 },
32468 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32469 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940c0000 }
32470 },
32471/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32472 {
32473 { 0, 0, 0, 0 },
32474 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32475 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942c0000 }
32476 },
32477/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32478 {
32479 { 0, 0, 0, 0 },
32480 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32481 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943c0000 }
32482 },
32483/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32484 {
32485 { 0, 0, 0, 0 },
32486 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32487 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960c0000 }
32488 },
32489/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32490 {
32491 { 0, 0, 0, 0 },
32492 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32493 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962c0000 }
32494 },
32495/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32496 {
32497 { 0, 0, 0, 0 },
32498 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32499 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963c0000 }
32500 },
32501/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
32502 {
32503 { 0, 0, 0, 0 },
32504 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32505 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928c0000 }
32506 },
32507/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
32508 {
32509 { 0, 0, 0, 0 },
32510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32511 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ac0000 }
32512 },
32513/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
32514 {
32515 { 0, 0, 0, 0 },
32516 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32517 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bc0000 }
32518 },
32519/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
32520 {
32521 { 0, 0, 0, 0 },
32522 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32523 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948c0000 }
32524 },
32525/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
32526 {
32527 { 0, 0, 0, 0 },
32528 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32529 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ac0000 }
32530 },
32531/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
32532 {
32533 { 0, 0, 0, 0 },
32534 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32535 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bc0000 }
32536 },
32537/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
32538 {
32539 { 0, 0, 0, 0 },
32540 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32541 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cc0000 }
32542 },
32543/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
32544 {
32545 { 0, 0, 0, 0 },
32546 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32547 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ec0000 }
32548 },
32549/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
32550 {
32551 { 0, 0, 0, 0 },
32552 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32553 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fc0000 }
32554 },
32555/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
32556 {
32557 { 0, 0, 0, 0 },
32558 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32559 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cc0000 }
32560 },
32561/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
32562 {
32563 { 0, 0, 0, 0 },
32564 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32565 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ec0000 }
32566 },
32567/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
32568 {
32569 { 0, 0, 0, 0 },
32570 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32571 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fc0000 }
32572 },
32573/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
32574 {
32575 { 0, 0, 0, 0 },
32576 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
32577 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cc0000 }
32578 },
32579/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
32580 {
32581 { 0, 0, 0, 0 },
32582 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
32583 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ec0000 }
32584 },
32585/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
32586 {
32587 { 0, 0, 0, 0 },
32588 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
32589 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fc0000 }
32590 },
32591/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
32592 {
32593 { 0, 0, 0, 0 },
32594 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
32595 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968c0000 }
32596 },
32597/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
32598 {
32599 { 0, 0, 0, 0 },
32600 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
32601 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ac0000 }
32602 },
32603/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
32604 {
32605 { 0, 0, 0, 0 },
32606 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
32607 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bc0000 }
32608 },
32609/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32610 {
32611 { 0, 0, 0, 0 },
32612 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32613 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80c0000 }
32614 },
32615/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
32616 {
32617 { 0, 0, 0, 0 },
32618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32619 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82c0000 }
32620 },
32621/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
32622 {
32623 { 0, 0, 0, 0 },
32624 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32625 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83c0000 }
32626 },
32627/* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
32628 {
32629 { 0, 0, 0, 0 },
32630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32631 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83c0000 }
32632 },
32633/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32634 {
32635 { 0, 0, 0, 0 },
32636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32637 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08c0000 }
32638 },
32639/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
32640 {
32641 { 0, 0, 0, 0 },
32642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32643 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ac0000 }
32644 },
32645/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
32646 {
32647 { 0, 0, 0, 0 },
32648 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32649 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bc0000 }
32650 },
32651/* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
32652 {
32653 { 0, 0, 0, 0 },
32654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32655 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bc0000 }
32656 },
32657/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32658 {
32659 { 0, 0, 0, 0 },
32660 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32661 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00c0000 }
32662 },
32663/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
32664 {
32665 { 0, 0, 0, 0 },
32666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32667 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02c0000 }
32668 },
32669/* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
32670 {
32671 { 0, 0, 0, 0 },
32672 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32673 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03c0000 }
32674 },
32675/* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
32676 {
32677 { 0, 0, 0, 0 },
32678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32679 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03c0000 }
32680 },
32681/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32682 {
32683 { 0, 0, 0, 0 },
32684 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32685 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20c0000 }
32686 },
32687/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32688 {
32689 { 0, 0, 0, 0 },
32690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32691 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22c0000 }
32692 },
32693/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32694 {
32695 { 0, 0, 0, 0 },
32696 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32697 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23c0000 }
32698 },
32699/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
32700 {
32701 { 0, 0, 0, 0 },
32702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32703 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23c0000 }
32704 },
32705/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32706 {
32707 { 0, 0, 0, 0 },
32708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32709 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40c0000 }
32710 },
32711/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32712 {
32713 { 0, 0, 0, 0 },
32714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32715 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42c0000 }
32716 },
32717/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32718 {
32719 { 0, 0, 0, 0 },
32720 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32721 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43c0000 }
32722 },
32723/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
32724 {
32725 { 0, 0, 0, 0 },
32726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32727 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43c0000 }
32728 },
32729/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32730 {
32731 { 0, 0, 0, 0 },
32732 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32733 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60c0000 }
32734 },
32735/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32736 {
32737 { 0, 0, 0, 0 },
32738 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32739 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62c0000 }
32740 },
32741/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32742 {
32743 { 0, 0, 0, 0 },
32744 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32745 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63c0000 }
32746 },
32747/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
32748 {
32749 { 0, 0, 0, 0 },
32750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32751 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63c0000 }
32752 },
32753/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
32754 {
32755 { 0, 0, 0, 0 },
32756 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32757 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28c0000 }
32758 },
32759/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
32760 {
32761 { 0, 0, 0, 0 },
32762 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32763 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ac0000 }
32764 },
32765/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
32766 {
32767 { 0, 0, 0, 0 },
32768 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32769 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bc0000 }
32770 },
32771/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
32772 {
32773 { 0, 0, 0, 0 },
32774 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32775 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bc0000 }
32776 },
32777/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
32778 {
32779 { 0, 0, 0, 0 },
32780 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32781 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48c0000 }
32782 },
32783/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
32784 {
32785 { 0, 0, 0, 0 },
32786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32787 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ac0000 }
32788 },
32789/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
32790 {
32791 { 0, 0, 0, 0 },
32792 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32793 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bc0000 }
32794 },
32795/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
32796 {
32797 { 0, 0, 0, 0 },
32798 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32799 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bc0000 }
32800 },
32801/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
32802 {
32803 { 0, 0, 0, 0 },
32804 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32805 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cc0000 }
32806 },
32807/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
32808 {
32809 { 0, 0, 0, 0 },
32810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32811 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ec0000 }
32812 },
32813/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
32814 {
32815 { 0, 0, 0, 0 },
32816 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32817 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fc0000 }
32818 },
32819/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
32820 {
32821 { 0, 0, 0, 0 },
32822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32823 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fc0000 }
32824 },
32825/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
32826 {
32827 { 0, 0, 0, 0 },
32828 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32829 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cc0000 }
32830 },
32831/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
32832 {
32833 { 0, 0, 0, 0 },
32834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32835 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ec0000 }
32836 },
32837/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
32838 {
32839 { 0, 0, 0, 0 },
32840 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32841 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fc0000 }
32842 },
32843/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
32844 {
32845 { 0, 0, 0, 0 },
32846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32847 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fc0000 }
32848 },
32849/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
32850 {
32851 { 0, 0, 0, 0 },
32852 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
32853 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cc0000 }
32854 },
32855/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
32856 {
32857 { 0, 0, 0, 0 },
32858 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
32859 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ec0000 }
32860 },
32861/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
32862 {
32863 { 0, 0, 0, 0 },
32864 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
32865 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fc0000 }
32866 },
32867/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
32868 {
32869 { 0, 0, 0, 0 },
32870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
32871 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fc0000 }
32872 },
32873/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
32874 {
32875 { 0, 0, 0, 0 },
32876 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
32877 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68c0000 }
32878 },
32879/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
32880 {
32881 { 0, 0, 0, 0 },
32882 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32883 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ac0000 }
32884 },
32885/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
32886 {
32887 { 0, 0, 0, 0 },
32888 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32889 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bc0000 }
32890 },
32891/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
32892 {
32893 { 0, 0, 0, 0 },
32894 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
32895 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bc0000 }
32896 },
32897/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32898 {
32899 { 0, 0, 0, 0 },
32900 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32901 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80c0000 }
32902 },
32903/* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
32904 {
32905 { 0, 0, 0, 0 },
32906 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32907 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82c0000 }
32908 },
32909/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32910 {
32911 { 0, 0, 0, 0 },
32912 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32913 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08c0000 }
32914 },
32915/* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
32916 {
32917 { 0, 0, 0, 0 },
32918 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32919 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ac0000 }
32920 },
32921/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32922 {
32923 { 0, 0, 0, 0 },
32924 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32925 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00c0000 }
32926 },
32927/* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
32928 {
32929 { 0, 0, 0, 0 },
32930 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32931 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02c0000 }
32932 },
32933/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
32934 {
32935 { 0, 0, 0, 0 },
32936 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32937 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20c0000 }
32938 },
32939/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
32940 {
32941 { 0, 0, 0, 0 },
32942 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32943 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22c0000 }
32944 },
32945/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
32946 {
32947 { 0, 0, 0, 0 },
32948 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32949 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40c0000 }
32950 },
32951/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
32952 {
32953 { 0, 0, 0, 0 },
32954 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32955 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42c0000 }
32956 },
32957/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
32958 {
32959 { 0, 0, 0, 0 },
32960 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32961 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60c0000 }
32962 },
32963/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
32964 {
32965 { 0, 0, 0, 0 },
32966 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32967 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62c0000 }
32968 },
32969/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
32970 {
32971 { 0, 0, 0, 0 },
32972 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32973 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28c0000 }
32974 },
32975/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
32976 {
32977 { 0, 0, 0, 0 },
32978 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32979 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ac0000 }
32980 },
32981/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
32982 {
32983 { 0, 0, 0, 0 },
32984 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32985 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48c0000 }
32986 },
32987/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
32988 {
32989 { 0, 0, 0, 0 },
32990 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32991 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ac0000 }
32992 },
32993/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
32994 {
32995 { 0, 0, 0, 0 },
32996 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32997 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cc0000 }
32998 },
32999/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
33000 {
33001 { 0, 0, 0, 0 },
33002 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
33003 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ec0000 }
33004 },
33005/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
33006 {
33007 { 0, 0, 0, 0 },
33008 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
33009 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cc0000 }
33010 },
33011/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
33012 {
33013 { 0, 0, 0, 0 },
33014 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
33015 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ec0000 }
33016 },
33017/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
33018 {
33019 { 0, 0, 0, 0 },
33020 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
33021 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cc0000 }
33022 },
33023/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
33024 {
33025 { 0, 0, 0, 0 },
33026 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
33027 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ec0000 }
33028 },
33029/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
33030 {
33031 { 0, 0, 0, 0 },
33032 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
33033 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68c0000 }
33034 },
33035/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
33036 {
33037 { 0, 0, 0, 0 },
33038 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
33039 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ac0000 }
33040 },
33041/* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
33042 {
33043 { 0, 0, 0, 0 },
33044 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
33045 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80c }
33046 },
33047/* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
33048 {
33049 { 0, 0, 0, 0 },
33050 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
33051 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882c }
33052 },
33053/* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
33054 {
33055 { 0, 0, 0, 0 },
33056 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
33057 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880c }
33058 },
33059/* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
33060 {
33061 { 0, 0, 0, 0 },
33062 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
33063 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08c }
33064 },
33065/* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
33066 {
33067 { 0, 0, 0, 0 },
33068 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
33069 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ac }
33070 },
33071/* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
33072 {
33073 { 0, 0, 0, 0 },
33074 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
33075 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808c }
33076 },
33077/* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
33078 {
33079 { 0, 0, 0, 0 },
33080 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33081 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00c }
33082 },
33083/* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
33084 {
33085 { 0, 0, 0, 0 },
33086 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33087 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802c }
33088 },
33089/* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
33090 {
33091 { 0, 0, 0, 0 },
33092 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33093 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800c }
33094 },
33095/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
33096 {
33097 { 0, 0, 0, 0 },
33098 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33099 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20c00 }
33100 },
33101/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
33102 {
33103 { 0, 0, 0, 0 },
33104 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33105 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822c00 }
33106 },
33107/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
33108 {
33109 { 0, 0, 0, 0 },
33110 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33111 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820c00 }
33112 },
33113/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
33114 {
33115 { 0, 0, 0, 0 },
33116 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33117 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40c0000 }
33118 },
33119/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
33120 {
33121 { 0, 0, 0, 0 },
33122 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33123 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842c0000 }
33124 },
33125/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
33126 {
33127 { 0, 0, 0, 0 },
33128 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33129 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840c0000 }
33130 },
33131/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
33132 {
33133 { 0, 0, 0, 0 },
33134 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33135 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60c0000 }
33136 },
33137/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
33138 {
33139 { 0, 0, 0, 0 },
33140 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33141 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862c0000 }
33142 },
33143/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
33144 {
33145 { 0, 0, 0, 0 },
33146 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33147 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860c0000 }
33148 },
33149/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
33150 {
33151 { 0, 0, 0, 0 },
33152 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33153 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28c00 }
33154 },
33155/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
33156 {
33157 { 0, 0, 0, 0 },
33158 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33159 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ac00 }
33160 },
33161/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
33162 {
33163 { 0, 0, 0, 0 },
33164 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33165 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828c00 }
33166 },
33167/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
33168 {
33169 { 0, 0, 0, 0 },
33170 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33171 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48c0000 }
33172 },
33173/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
33174 {
33175 { 0, 0, 0, 0 },
33176 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33177 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ac0000 }
33178 },
33179/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
33180 {
33181 { 0, 0, 0, 0 },
33182 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33183 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848c0000 }
33184 },
33185/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
33186 {
33187 { 0, 0, 0, 0 },
33188 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33189 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cc00 }
33190 },
33191/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
33192 {
33193 { 0, 0, 0, 0 },
33194 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33195 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ec00 }
33196 },
33197/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
33198 {
33199 { 0, 0, 0, 0 },
33200 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33201 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cc00 }
33202 },
33203/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
33204 {
33205 { 0, 0, 0, 0 },
33206 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33207 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cc0000 }
33208 },
33209/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
33210 {
33211 { 0, 0, 0, 0 },
33212 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33213 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ec0000 }
33214 },
33215/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
33216 {
33217 { 0, 0, 0, 0 },
33218 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33219 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cc0000 }
33220 },
33221/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
33222 {
33223 { 0, 0, 0, 0 },
33224 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
33225 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cc0000 }
33226 },
33227/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
33228 {
33229 { 0, 0, 0, 0 },
33230 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
33231 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ec0000 }
33232 },
33233/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
33234 {
33235 { 0, 0, 0, 0 },
33236 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
33237 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cc0000 }
33238 },
33239/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
33240 {
33241 { 0, 0, 0, 0 },
33242 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
33243 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68c0000 }
33244 },
33245/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
33246 {
33247 { 0, 0, 0, 0 },
33248 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
33249 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ac0000 }
33250 },
33251/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
33252 {
33253 { 0, 0, 0, 0 },
33254 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
33255 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868c0000 }
33256 },
33257/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
33258 {
33259 { 0, 0, 0, 0 },
33260 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33261 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x798000 }
33262 },
33263/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
33264 {
33265 { 0, 0, 0, 0 },
33266 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
33267 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x79a000 }
33268 },
33269/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
33270 {
33271 { 0, 0, 0, 0 },
33272 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
33273 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x79b000 }
33274 },
33275/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
33276 {
33277 { 0, 0, 0, 0 },
33278 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33279 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x798400 }
33280 },
33281/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
33282 {
33283 { 0, 0, 0, 0 },
33284 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
33285 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x79a400 }
33286 },
33287/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
33288 {
33289 { 0, 0, 0, 0 },
33290 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
33291 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x79b400 }
33292 },
33293/* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
33294 {
33295 { 0, 0, 0, 0 },
33296 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33297 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x798600 }
33298 },
33299/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
33300 {
33301 { 0, 0, 0, 0 },
33302 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33303 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x79a600 }
33304 },
33305/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
33306 {
33307 { 0, 0, 0, 0 },
33308 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33309 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x79b600 }
33310 },
33311/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
33312 {
33313 { 0, 0, 0, 0 },
33314 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33315 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x79880000 }
33316 },
33317/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
33318 {
33319 { 0, 0, 0, 0 },
33320 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33321 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x79a80000 }
33322 },
33323/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
33324 {
33325 { 0, 0, 0, 0 },
33326 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33327 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x79b80000 }
33328 },
33329/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
33330 {
33331 { 0, 0, 0, 0 },
33332 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33333 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x798c0000 }
33334 },
33335/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
33336 {
33337 { 0, 0, 0, 0 },
33338 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33339 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x79ac0000 }
33340 },
33341/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
33342 {
33343 { 0, 0, 0, 0 },
33344 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33345 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x79bc0000 }
33346 },
33347/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
33348 {
33349 { 0, 0, 0, 0 },
33350 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33351 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x798a0000 }
33352 },
33353/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
33354 {
33355 { 0, 0, 0, 0 },
33356 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33357 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79aa0000 }
33358 },
33359/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
33360 {
33361 { 0, 0, 0, 0 },
33362 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33363 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79ba0000 }
33364 },
33365/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
33366 {
33367 { 0, 0, 0, 0 },
33368 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33369 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x798e0000 }
33370 },
33371/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
33372 {
33373 { 0, 0, 0, 0 },
33374 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33375 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79ae0000 }
33376 },
33377/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
33378 {
33379 { 0, 0, 0, 0 },
33380 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33381 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79be0000 }
33382 },
33383/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
33384 {
33385 { 0, 0, 0, 0 },
33386 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33387 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x798b0000 }
33388 },
33389/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
33390 {
33391 { 0, 0, 0, 0 },
33392 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33393 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79ab0000 }
33394 },
33395/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
33396 {
33397 { 0, 0, 0, 0 },
33398 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33399 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79bb0000 }
33400 },
33401/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
33402 {
33403 { 0, 0, 0, 0 },
33404 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
33405 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x798f0000 }
33406 },
33407/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
33408 {
33409 { 0, 0, 0, 0 },
33410 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33411 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x79af0000 }
33412 },
33413/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
33414 {
33415 { 0, 0, 0, 0 },
33416 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33417 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x79bf0000 }
33418 },
33419/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
33420 {
33421 { 0, 0, 0, 0 },
33422 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33423 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x79c00000 }
33424 },
33425/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
33426 {
33427 { 0, 0, 0, 0 },
33428 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
33429 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x79e00000 }
33430 },
33431/* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
33432 {
33433 { 0, 0, 0, 0 },
33434 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
33435 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x79f00000 }
33436 },
33437/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
33438 {
33439 { 0, 0, 0, 0 },
33440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33441 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x79c40000 }
33442 },
33443/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
33444 {
33445 { 0, 0, 0, 0 },
33446 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
33447 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x79e40000 }
33448 },
33449/* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
33450 {
33451 { 0, 0, 0, 0 },
33452 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
33453 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x79f40000 }
33454 },
33455/* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
33456 {
33457 { 0, 0, 0, 0 },
33458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33459 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x79c60000 }
33460 },
33461/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
33462 {
33463 { 0, 0, 0, 0 },
33464 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33465 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x79e60000 }
33466 },
33467/* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
33468 {
33469 { 0, 0, 0, 0 },
33470 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
33471 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x79f60000 }
33472 },
33473/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
33474 {
33475 { 0, 0, 0, 0 },
33476 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33477 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x79c80000 }
33478 },
33479/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
33480 {
33481 { 0, 0, 0, 0 },
33482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33483 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x79e80000 }
33484 },
33485/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
33486 {
33487 { 0, 0, 0, 0 },
33488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33489 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x79f80000 }
33490 },
33491/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
33492 {
33493 { 0, 0, 0, 0 },
33494 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33495 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x79cc0000 }
33496 },
33497/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
33498 {
33499 { 0, 0, 0, 0 },
33500 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33501 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x79ec0000 }
33502 },
33503/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
33504 {
33505 { 0, 0, 0, 0 },
33506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33507 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x79fc0000 }
33508 },
33509/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
33510 {
33511 { 0, 0, 0, 0 },
33512 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33513 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ca0000 }
33514 },
33515/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
33516 {
33517 { 0, 0, 0, 0 },
33518 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33519 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ea0000 }
33520 },
33521/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
33522 {
33523 { 0, 0, 0, 0 },
33524 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33525 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x79fa0000 }
33526 },
33527/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
33528 {
33529 { 0, 0, 0, 0 },
33530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33531 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ce0000 }
33532 },
33533/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
33534 {
33535 { 0, 0, 0, 0 },
33536 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33537 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ee0000 }
33538 },
33539/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
33540 {
33541 { 0, 0, 0, 0 },
33542 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33543 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x79fe0000 }
33544 },
33545/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
33546 {
33547 { 0, 0, 0, 0 },
33548 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33549 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x79cb0000 }
33550 },
33551/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
33552 {
33553 { 0, 0, 0, 0 },
33554 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33555 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x79eb0000 }
33556 },
33557/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
33558 {
33559 { 0, 0, 0, 0 },
33560 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33561 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x79fb0000 }
33562 },
33563/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
33564 {
33565 { 0, 0, 0, 0 },
33566 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
33567 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x79cf0000 }
33568 },
33569/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
33570 {
33571 { 0, 0, 0, 0 },
33572 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
33573 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x79ef0000 }
33574 },
33575/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
33576 {
33577 { 0, 0, 0, 0 },
33578 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
33579 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x79ff0000 }
33580 },
33581/* mul.w${G} $Src16RnHI,$Dst16RnHI */
33582 {
33583 { 0, 0, 0, 0 },
33584 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
33585 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7900 }
33586 },
33587/* mul.w${G} $Src16AnHI,$Dst16RnHI */
33588 {
33589 { 0, 0, 0, 0 },
33590 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
33591 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7940 }
33592 },
33593/* mul.w${G} [$Src16An],$Dst16RnHI */
33594 {
33595 { 0, 0, 0, 0 },
33596 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33597 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7960 }
33598 },
33599/* mul.w${G} $Src16RnHI,$Dst16AnHI */
33600 {
33601 { 0, 0, 0, 0 },
33602 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
33603 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7904 }
33604 },
33605/* mul.w${G} $Src16AnHI,$Dst16AnHI */
33606 {
33607 { 0, 0, 0, 0 },
33608 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
33609 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7944 }
33610 },
33611/* mul.w${G} [$Src16An],$Dst16AnHI */
33612 {
33613 { 0, 0, 0, 0 },
33614 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33615 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7964 }
33616 },
33617/* mul.w${G} $Src16RnHI,[$Dst16An] */
33618 {
33619 { 0, 0, 0, 0 },
33620 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
33621 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7906 }
33622 },
33623/* mul.w${G} $Src16AnHI,[$Dst16An] */
33624 {
33625 { 0, 0, 0, 0 },
33626 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
33627 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7946 }
33628 },
33629/* mul.w${G} [$Src16An],[$Dst16An] */
33630 {
33631 { 0, 0, 0, 0 },
33632 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33633 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7966 }
33634 },
33635/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
33636 {
33637 { 0, 0, 0, 0 },
33638 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33639 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x790800 }
33640 },
33641/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
33642 {
33643 { 0, 0, 0, 0 },
33644 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33645 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x794800 }
33646 },
33647/* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
33648 {
33649 { 0, 0, 0, 0 },
33650 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33651 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x796800 }
33652 },
33653/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
33654 {
33655 { 0, 0, 0, 0 },
33656 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33657 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x790c0000 }
33658 },
33659/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
33660 {
33661 { 0, 0, 0, 0 },
33662 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33663 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x794c0000 }
33664 },
33665/* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
33666 {
33667 { 0, 0, 0, 0 },
33668 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33669 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x796c0000 }
33670 },
33671/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
33672 {
33673 { 0, 0, 0, 0 },
33674 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33675 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x790a00 }
33676 },
33677/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
33678 {
33679 { 0, 0, 0, 0 },
33680 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33681 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x794a00 }
33682 },
33683/* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
33684 {
33685 { 0, 0, 0, 0 },
33686 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33687 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x796a00 }
33688 },
33689/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
33690 {
33691 { 0, 0, 0, 0 },
33692 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33693 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x790e0000 }
33694 },
33695/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
33696 {
33697 { 0, 0, 0, 0 },
33698 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33699 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x794e0000 }
33700 },
33701/* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
33702 {
33703 { 0, 0, 0, 0 },
33704 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33705 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x796e0000 }
33706 },
33707/* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
33708 {
33709 { 0, 0, 0, 0 },
33710 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33711 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x790b00 }
33712 },
33713/* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
33714 {
33715 { 0, 0, 0, 0 },
33716 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33717 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x794b00 }
33718 },
33719/* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
33720 {
33721 { 0, 0, 0, 0 },
33722 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33723 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x796b00 }
33724 },
33725/* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
33726 {
33727 { 0, 0, 0, 0 },
33728 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
33729 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x790f0000 }
33730 },
33731/* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
33732 {
33733 { 0, 0, 0, 0 },
33734 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
33735 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x794f0000 }
33736 },
33737/* mul.w${G} [$Src16An],${Dsp-16-u16} */
33738 {
33739 { 0, 0, 0, 0 },
33740 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
33741 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x796f0000 }
33742 },
33743/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
33744 {
33745 { 0, 0, 0, 0 },
33746 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
33747 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x788000 }
33748 },
33749/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
33750 {
33751 { 0, 0, 0, 0 },
33752 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
33753 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x78a000 }
33754 },
33755/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
33756 {
33757 { 0, 0, 0, 0 },
33758 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
33759 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x78b000 }
33760 },
33761/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
33762 {
33763 { 0, 0, 0, 0 },
33764 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
33765 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x788400 }
33766 },
33767/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
33768 {
33769 { 0, 0, 0, 0 },
33770 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
33771 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x78a400 }
33772 },
33773/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
33774 {
33775 { 0, 0, 0, 0 },
33776 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
33777 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x78b400 }
33778 },
33779/* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
33780 {
33781 { 0, 0, 0, 0 },
33782 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33783 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x788600 }
33784 },
33785/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
33786 {
33787 { 0, 0, 0, 0 },
33788 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33789 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x78a600 }
33790 },
33791/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
33792 {
33793 { 0, 0, 0, 0 },
33794 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33795 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x78b600 }
33796 },
33797/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
33798 {
33799 { 0, 0, 0, 0 },
33800 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33801 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x78880000 }
33802 },
33803/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
33804 {
33805 { 0, 0, 0, 0 },
33806 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33807 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x78a80000 }
33808 },
33809/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
33810 {
33811 { 0, 0, 0, 0 },
33812 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33813 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x78b80000 }
33814 },
33815/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
33816 {
33817 { 0, 0, 0, 0 },
33818 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33819 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x788c0000 }
33820 },
33821/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
33822 {
33823 { 0, 0, 0, 0 },
33824 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33825 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x78ac0000 }
33826 },
33827/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
33828 {
33829 { 0, 0, 0, 0 },
33830 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33831 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x78bc0000 }
33832 },
33833/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
33834 {
33835 { 0, 0, 0, 0 },
33836 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33837 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x788a0000 }
33838 },
33839/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
33840 {
33841 { 0, 0, 0, 0 },
33842 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33843 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78aa0000 }
33844 },
33845/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
33846 {
33847 { 0, 0, 0, 0 },
33848 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33849 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78ba0000 }
33850 },
33851/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
33852 {
33853 { 0, 0, 0, 0 },
33854 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33855 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x788e0000 }
33856 },
33857/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
33858 {
33859 { 0, 0, 0, 0 },
33860 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33861 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78ae0000 }
33862 },
33863/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
33864 {
33865 { 0, 0, 0, 0 },
33866 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33867 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78be0000 }
33868 },
33869/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
33870 {
33871 { 0, 0, 0, 0 },
33872 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33873 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x788b0000 }
33874 },
33875/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
33876 {
33877 { 0, 0, 0, 0 },
33878 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33879 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78ab0000 }
33880 },
33881/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
33882 {
33883 { 0, 0, 0, 0 },
33884 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33885 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78bb0000 }
33886 },
33887/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
33888 {
33889 { 0, 0, 0, 0 },
33890 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
33891 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x788f0000 }
33892 },
33893/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
33894 {
33895 { 0, 0, 0, 0 },
33896 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33897 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x78af0000 }
33898 },
33899/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
33900 {
33901 { 0, 0, 0, 0 },
33902 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33903 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x78bf0000 }
33904 },
33905/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
33906 {
33907 { 0, 0, 0, 0 },
33908 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
33909 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x78c00000 }
33910 },
33911/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
33912 {
33913 { 0, 0, 0, 0 },
33914 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
33915 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x78e00000 }
33916 },
33917/* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
33918 {
33919 { 0, 0, 0, 0 },
33920 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
33921 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x78f00000 }
33922 },
33923/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
33924 {
33925 { 0, 0, 0, 0 },
33926 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
33927 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x78c40000 }
33928 },
33929/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
33930 {
33931 { 0, 0, 0, 0 },
33932 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
33933 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x78e40000 }
33934 },
33935/* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
33936 {
33937 { 0, 0, 0, 0 },
33938 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
33939 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x78f40000 }
33940 },
33941/* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
33942 {
33943 { 0, 0, 0, 0 },
33944 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33945 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x78c60000 }
33946 },
33947/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
33948 {
33949 { 0, 0, 0, 0 },
33950 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33951 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x78e60000 }
33952 },
33953/* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
33954 {
33955 { 0, 0, 0, 0 },
33956 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
33957 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x78f60000 }
33958 },
33959/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
33960 {
33961 { 0, 0, 0, 0 },
33962 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33963 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x78c80000 }
33964 },
33965/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
33966 {
33967 { 0, 0, 0, 0 },
33968 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33969 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x78e80000 }
33970 },
33971/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
33972 {
33973 { 0, 0, 0, 0 },
33974 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33975 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x78f80000 }
33976 },
33977/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
33978 {
33979 { 0, 0, 0, 0 },
33980 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33981 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x78cc0000 }
33982 },
33983/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
33984 {
33985 { 0, 0, 0, 0 },
33986 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33987 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x78ec0000 }
33988 },
33989/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
33990 {
33991 { 0, 0, 0, 0 },
33992 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33993 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x78fc0000 }
33994 },
33995/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
33996 {
33997 { 0, 0, 0, 0 },
33998 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33999 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ca0000 }
34000 },
34001/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
34002 {
34003 { 0, 0, 0, 0 },
34004 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
34005 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ea0000 }
34006 },
34007/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
34008 {
34009 { 0, 0, 0, 0 },
34010 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
34011 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x78fa0000 }
34012 },
34013/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
34014 {
34015 { 0, 0, 0, 0 },
34016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
34017 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ce0000 }
34018 },
34019/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
34020 {
34021 { 0, 0, 0, 0 },
34022 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
34023 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ee0000 }
34024 },
34025/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
34026 {
34027 { 0, 0, 0, 0 },
34028 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
34029 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x78fe0000 }
34030 },
34031/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
34032 {
34033 { 0, 0, 0, 0 },
34034 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
34035 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x78cb0000 }
34036 },
34037/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
34038 {
34039 { 0, 0, 0, 0 },
34040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
34041 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x78eb0000 }
34042 },
34043/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
34044 {
34045 { 0, 0, 0, 0 },
34046 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
34047 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x78fb0000 }
34048 },
34049/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
34050 {
34051 { 0, 0, 0, 0 },
34052 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
34053 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x78cf0000 }
34054 },
34055/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
34056 {
34057 { 0, 0, 0, 0 },
34058 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
34059 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x78ef0000 }
34060 },
34061/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
34062 {
34063 { 0, 0, 0, 0 },
34064 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
34065 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x78ff0000 }
34066 },
34067/* mul.b${G} $Src16RnQI,$Dst16RnQI */
34068 {
34069 { 0, 0, 0, 0 },
34070 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
34071 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7800 }
34072 },
34073/* mul.b${G} $Src16AnQI,$Dst16RnQI */
34074 {
34075 { 0, 0, 0, 0 },
34076 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
34077 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7840 }
34078 },
34079/* mul.b${G} [$Src16An],$Dst16RnQI */
34080 {
34081 { 0, 0, 0, 0 },
34082 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
34083 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7860 }
34084 },
34085/* mul.b${G} $Src16RnQI,$Dst16AnQI */
34086 {
34087 { 0, 0, 0, 0 },
34088 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
34089 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7804 }
34090 },
34091/* mul.b${G} $Src16AnQI,$Dst16AnQI */
34092 {
34093 { 0, 0, 0, 0 },
34094 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
34095 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7844 }
34096 },
34097/* mul.b${G} [$Src16An],$Dst16AnQI */
34098 {
34099 { 0, 0, 0, 0 },
34100 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
34101 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7864 }
34102 },
34103/* mul.b${G} $Src16RnQI,[$Dst16An] */
34104 {
34105 { 0, 0, 0, 0 },
34106 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
34107 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7806 }
34108 },
34109/* mul.b${G} $Src16AnQI,[$Dst16An] */
34110 {
34111 { 0, 0, 0, 0 },
34112 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
34113 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7846 }
34114 },
34115/* mul.b${G} [$Src16An],[$Dst16An] */
34116 {
34117 { 0, 0, 0, 0 },
34118 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
34119 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7866 }
34120 },
34121/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
34122 {
34123 { 0, 0, 0, 0 },
34124 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34125 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x780800 }
34126 },
34127/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
34128 {
34129 { 0, 0, 0, 0 },
34130 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34131 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x784800 }
34132 },
34133/* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
34134 {
34135 { 0, 0, 0, 0 },
34136 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34137 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x786800 }
34138 },
34139/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
34140 {
34141 { 0, 0, 0, 0 },
34142 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34143 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x780c0000 }
34144 },
34145/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
34146 {
34147 { 0, 0, 0, 0 },
34148 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34149 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x784c0000 }
34150 },
34151/* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
34152 {
34153 { 0, 0, 0, 0 },
34154 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34155 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x786c0000 }
34156 },
34157/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
34158 {
34159 { 0, 0, 0, 0 },
34160 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34161 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x780a00 }
34162 },
34163/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
34164 {
34165 { 0, 0, 0, 0 },
34166 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34167 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x784a00 }
34168 },
34169/* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
34170 {
34171 { 0, 0, 0, 0 },
34172 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34173 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x786a00 }
34174 },
34175/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
34176 {
34177 { 0, 0, 0, 0 },
34178 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34179 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x780e0000 }
34180 },
34181/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
34182 {
34183 { 0, 0, 0, 0 },
34184 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34185 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x784e0000 }
34186 },
34187/* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
34188 {
34189 { 0, 0, 0, 0 },
34190 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34191 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x786e0000 }
34192 },
34193/* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
34194 {
34195 { 0, 0, 0, 0 },
34196 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34197 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x780b00 }
34198 },
34199/* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
34200 {
34201 { 0, 0, 0, 0 },
34202 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34203 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x784b00 }
34204 },
34205/* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
34206 {
34207 { 0, 0, 0, 0 },
34208 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34209 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x786b00 }
34210 },
34211/* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
34212 {
34213 { 0, 0, 0, 0 },
34214 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
34215 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x780f0000 }
34216 },
34217/* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
34218 {
34219 { 0, 0, 0, 0 },
34220 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
34221 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x784f0000 }
34222 },
34223/* mul.b${G} [$Src16An],${Dsp-16-u16} */
34224 {
34225 { 0, 0, 0, 0 },
34226 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
34227 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x786f0000 }
34228 },
34229/* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
34230 {
34231 { 0, 0, 0, 0 },
34232 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
34233 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x891f0000 }
34234 },
34235/* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
34236 {
34237 { 0, 0, 0, 0 },
34238 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
34239 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x819f0000 }
34240 },
34241/* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
34242 {
34243 { 0, 0, 0, 0 },
34244 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34245 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x811f0000 }
34246 },
34247/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
34248 {
34249 { 0, 0, 0, 0 },
34250 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34251 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x831f0000 }
34252 },
34253/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
34254 {
34255 { 0, 0, 0, 0 },
34256 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34257 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839f0000 }
34258 },
34259/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
34260 {
34261 { 0, 0, 0, 0 },
34262 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34263 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83df0000 }
34264 },
34265/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
34266 {
34267 { 0, 0, 0, 0 },
34268 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34269 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x851f0000 }
34270 },
34271/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
34272 {
34273 { 0, 0, 0, 0 },
34274 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34275 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859f0000 }
34276 },
34277/* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
34278 {
34279 { 0, 0, 0, 0 },
34280 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
34281 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85df0000 }
34282 },
34283/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
34284 {
34285 { 0, 0, 0, 0 },
34286 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
34287 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87df0000 }
34288 },
34289/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
34290 {
34291 { 0, 0, 0, 0 },
34292 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34293 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x871f0000 }
34294 },
34295/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
34296 {
34297 { 0, 0, 0, 0 },
34298 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
34299 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x879f0000 }
34300 },
34301/* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
34302 {
34303 { 0, 0, 0, 0 },
34304 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
34305 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x881f00 }
34306 },
34307/* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
34308 {
34309 { 0, 0, 0, 0 },
34310 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
34311 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x809f00 }
34312 },
34313/* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
34314 {
34315 { 0, 0, 0, 0 },
34316 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34317 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x801f00 }
34318 },
34319/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
34320 {
34321 { 0, 0, 0, 0 },
34322 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34323 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x821f0000 }
34324 },
34325/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34326 {
34327 { 0, 0, 0, 0 },
34328 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34329 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829f0000 }
34330 },
34331/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34332 {
34333 { 0, 0, 0, 0 },
34334 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34335 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82df0000 }
34336 },
34337/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
34338 {
34339 { 0, 0, 0, 0 },
34340 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34341 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x841f0000 }
34342 },
34343/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34344 {
34345 { 0, 0, 0, 0 },
34346 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34347 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849f0000 }
34348 },
34349/* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
34350 {
34351 { 0, 0, 0, 0 },
34352 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
34353 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84df0000 }
34354 },
34355/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
34356 {
34357 { 0, 0, 0, 0 },
34358 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34359 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86df0000 }
34360 },
34361/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
34362 {
34363 { 0, 0, 0, 0 },
34364 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34365 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x861f0000 }
34366 },
34367/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
34368 {
34369 { 0, 0, 0, 0 },
34370 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
34371 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x869f0000 }
34372 },
34373/* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
34374 {
34375 { 0, 0, 0, 0 },
34376 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
34377 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d500000 }
34378 },
34379/* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
34380 {
34381 { 0, 0, 0, 0 },
34382 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
34383 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d540000 }
34384 },
34385/* mul.w${G} #${Imm-16-HI},[$Dst16An] */
34386 {
34387 { 0, 0, 0, 0 },
34388 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
34389 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d560000 }
34390 },
34391/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
34392 {
34393 { 0, 0, 0, 0 },
34394 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34395 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d580000 }
34396 },
34397/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
34398 {
34399 { 0, 0, 0, 0 },
34400 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34401 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d5a0000 }
34402 },
34403/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
34404 {
34405 { 0, 0, 0, 0 },
34406 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34407 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d5b0000 }
34408 },
34409/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
34410 {
34411 { 0, 0, 0, 0 },
34412 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34413 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d5c0000 }
34414 },
34415/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
34416 {
34417 { 0, 0, 0, 0 },
34418 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34419 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d5e0000 }
34420 },
34421/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
34422 {
34423 { 0, 0, 0, 0 },
34424 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
34425 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d5f0000 }
34426 },
34427/* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
34428 {
34429 { 0, 0, 0, 0 },
34430 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
34431 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c5000 }
34432 },
34433/* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
34434 {
34435 { 0, 0, 0, 0 },
34436 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
34437 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c5400 }
34438 },
34439/* mul.b${G} #${Imm-16-QI},[$Dst16An] */
34440 {
34441 { 0, 0, 0, 0 },
34442 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
34443 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c5600 }
34444 },
34445/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
34446 {
34447 { 0, 0, 0, 0 },
34448 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34449 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c580000 }
34450 },
34451/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34452 {
34453 { 0, 0, 0, 0 },
34454 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34455 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c5a0000 }
34456 },
34457/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34458 {
34459 { 0, 0, 0, 0 },
34460 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34461 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c5b0000 }
34462 },
34463/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
34464 {
34465 { 0, 0, 0, 0 },
34466 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34467 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c5c0000 }
34468 },
34469/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34470 {
34471 { 0, 0, 0, 0 },
34472 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34473 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c5e0000 }
34474 },
34475/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
34476 {
34477 { 0, 0, 0, 0 },
34478 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34479 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c5f0000 }
34480 },
34481/* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
34482 {
34483 { 0, 0, 0, 0 },
34484 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
34485 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb81100 }
34486 },
34487/* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
34488 {
34489 { 0, 0, 0, 0 },
34490 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
34491 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb09100 }
34492 },
34493/* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
34494 {
34495 { 0, 0, 0, 0 },
34496 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34497 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb01100 }
34498 },
34499/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
34500 {
34501 { 0, 0, 0, 0 },
34502 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34503 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2110000 }
34504 },
34505/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34506 {
34507 { 0, 0, 0, 0 },
34508 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34509 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2910000 }
34510 },
34511/* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34512 {
34513 { 0, 0, 0, 0 },
34514 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34515 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2d10000 }
34516 },
34517/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
34518 {
34519 { 0, 0, 0, 0 },
34520 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34521 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4110000 }
34522 },
34523/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34524 {
34525 { 0, 0, 0, 0 },
34526 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34527 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4910000 }
34528 },
34529/* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
34530 {
34531 { 0, 0, 0, 0 },
34532 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
34533 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4d10000 }
34534 },
34535/* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
34536 {
34537 { 0, 0, 0, 0 },
34538 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34539 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6d10000 }
34540 },
34541/* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
34542 {
34543 { 0, 0, 0, 0 },
34544 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34545 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6110000 }
34546 },
34547/* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
34548 {
34549 { 0, 0, 0, 0 },
34550 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
34551 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6910000 }
34552 },
34553/* movhh $Dst32RnPrefixedQI,r0l */
34554 {
34555 { 0, 0, 0, 0 },
34556 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34557 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a83e }
34558 },
34559/* movhh $Dst32AnPrefixedQI,r0l */
34560 {
34561 { 0, 0, 0, 0 },
34562 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34563 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0be }
34564 },
34565/* movhh [$Dst32AnPrefixed],r0l */
34566 {
34567 { 0, 0, 0, 0 },
34568 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34569 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a03e }
34570 },
34571/* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34572 {
34573 { 0, 0, 0, 0 },
34574 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34575 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a23e00 }
34576 },
34577/* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34578 {
34579 { 0, 0, 0, 0 },
34580 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34581 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a43e00 }
34582 },
34583/* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34584 {
34585 { 0, 0, 0, 0 },
34586 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34587 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a63e00 }
34588 },
34589/* movhh ${Dsp-24-u8}[sb],r0l */
34590 {
34591 { 0, 0, 0, 0 },
34592 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34593 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2be00 }
34594 },
34595/* movhh ${Dsp-24-u16}[sb],r0l */
34596 {
34597 { 0, 0, 0, 0 },
34598 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34599 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4be00 }
34600 },
34601/* movhh ${Dsp-24-s8}[fb],r0l */
34602 {
34603 { 0, 0, 0, 0 },
34604 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34605 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2fe00 }
34606 },
34607/* movhh ${Dsp-24-s16}[fb],r0l */
34608 {
34609 { 0, 0, 0, 0 },
34610 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34611 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4fe00 }
34612 },
34613/* movhh ${Dsp-24-u16},r0l */
34614 {
34615 { 0, 0, 0, 0 },
34616 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34617 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6fe00 }
34618 },
34619/* movhh ${Dsp-24-u24},r0l */
34620 {
34621 { 0, 0, 0, 0 },
34622 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34623 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6be00 }
34624 },
34625/* movhl $Dst32RnPrefixedQI,r0l */
34626 {
34627 { 0, 0, 0, 0 },
34628 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34629 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a82e }
34630 },
34631/* movhl $Dst32AnPrefixedQI,r0l */
34632 {
34633 { 0, 0, 0, 0 },
34634 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34635 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0ae }
34636 },
34637/* movhl [$Dst32AnPrefixed],r0l */
34638 {
34639 { 0, 0, 0, 0 },
34640 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34641 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a02e }
34642 },
34643/* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34644 {
34645 { 0, 0, 0, 0 },
34646 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34647 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a22e00 }
34648 },
34649/* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34650 {
34651 { 0, 0, 0, 0 },
34652 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34653 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a42e00 }
34654 },
34655/* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34656 {
34657 { 0, 0, 0, 0 },
34658 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34659 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a62e00 }
34660 },
34661/* movhl ${Dsp-24-u8}[sb],r0l */
34662 {
34663 { 0, 0, 0, 0 },
34664 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34665 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2ae00 }
34666 },
34667/* movhl ${Dsp-24-u16}[sb],r0l */
34668 {
34669 { 0, 0, 0, 0 },
34670 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34671 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4ae00 }
34672 },
34673/* movhl ${Dsp-24-s8}[fb],r0l */
34674 {
34675 { 0, 0, 0, 0 },
34676 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34677 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ee00 }
34678 },
34679/* movhl ${Dsp-24-s16}[fb],r0l */
34680 {
34681 { 0, 0, 0, 0 },
34682 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34683 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ee00 }
34684 },
34685/* movhl ${Dsp-24-u16},r0l */
34686 {
34687 { 0, 0, 0, 0 },
34688 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34689 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ee00 }
34690 },
34691/* movhl ${Dsp-24-u24},r0l */
34692 {
34693 { 0, 0, 0, 0 },
34694 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34695 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6ae00 }
34696 },
34697/* movlh $Dst32RnPrefixedQI,r0l */
34698 {
34699 { 0, 0, 0, 0 },
34700 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34701 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a81e }
34702 },
34703/* movlh $Dst32AnPrefixedQI,r0l */
34704 {
34705 { 0, 0, 0, 0 },
34706 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34707 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a09e }
34708 },
34709/* movlh [$Dst32AnPrefixed],r0l */
34710 {
34711 { 0, 0, 0, 0 },
34712 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34713 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a01e }
34714 },
34715/* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34716 {
34717 { 0, 0, 0, 0 },
34718 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34719 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a21e00 }
34720 },
34721/* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34722 {
34723 { 0, 0, 0, 0 },
34724 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34725 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a41e00 }
34726 },
34727/* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34728 {
34729 { 0, 0, 0, 0 },
34730 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34731 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a61e00 }
34732 },
34733/* movlh ${Dsp-24-u8}[sb],r0l */
34734 {
34735 { 0, 0, 0, 0 },
34736 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34737 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a29e00 }
34738 },
34739/* movlh ${Dsp-24-u16}[sb],r0l */
34740 {
34741 { 0, 0, 0, 0 },
34742 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34743 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a49e00 }
34744 },
34745/* movlh ${Dsp-24-s8}[fb],r0l */
34746 {
34747 { 0, 0, 0, 0 },
34748 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34749 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2de00 }
34750 },
34751/* movlh ${Dsp-24-s16}[fb],r0l */
34752 {
34753 { 0, 0, 0, 0 },
34754 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34755 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4de00 }
34756 },
34757/* movlh ${Dsp-24-u16},r0l */
34758 {
34759 { 0, 0, 0, 0 },
34760 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34761 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6de00 }
34762 },
34763/* movlh ${Dsp-24-u24},r0l */
34764 {
34765 { 0, 0, 0, 0 },
34766 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34767 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a69e00 }
34768 },
34769/* movll $Dst32RnPrefixedQI,r0l */
34770 {
34771 { 0, 0, 0, 0 },
34772 { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34773 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a80e }
34774 },
34775/* movll $Dst32AnPrefixedQI,r0l */
34776 {
34777 { 0, 0, 0, 0 },
34778 { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34779 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a08e }
34780 },
34781/* movll [$Dst32AnPrefixed],r0l */
34782 {
34783 { 0, 0, 0, 0 },
34784 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34785 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a00e }
34786 },
34787/* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34788 {
34789 { 0, 0, 0, 0 },
34790 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34791 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a20e00 }
34792 },
34793/* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34794 {
34795 { 0, 0, 0, 0 },
34796 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34797 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a40e00 }
34798 },
34799/* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34800 {
34801 { 0, 0, 0, 0 },
34802 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34803 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a60e00 }
34804 },
34805/* movll ${Dsp-24-u8}[sb],r0l */
34806 {
34807 { 0, 0, 0, 0 },
34808 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34809 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a28e00 }
34810 },
34811/* movll ${Dsp-24-u16}[sb],r0l */
34812 {
34813 { 0, 0, 0, 0 },
34814 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34815 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a48e00 }
34816 },
34817/* movll ${Dsp-24-s8}[fb],r0l */
34818 {
34819 { 0, 0, 0, 0 },
34820 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34821 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ce00 }
34822 },
34823/* movll ${Dsp-24-s16}[fb],r0l */
34824 {
34825 { 0, 0, 0, 0 },
34826 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34827 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ce00 }
34828 },
34829/* movll ${Dsp-24-u16},r0l */
34830 {
34831 { 0, 0, 0, 0 },
34832 { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34833 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ce00 }
34834 },
34835/* movll ${Dsp-24-u24},r0l */
34836 {
34837 { 0, 0, 0, 0 },
34838 { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34839 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a68e00 }
34840 },
34841/* movhh r0l,$Dst32RnPrefixedQI */
34842 {
34843 { 0, 0, 0, 0 },
34844 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34845 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b83e }
34846 },
34847/* movhh r0l,$Dst32AnPrefixedQI */
34848 {
34849 { 0, 0, 0, 0 },
34850 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34851 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0be }
34852 },
34853/* movhh r0l,[$Dst32AnPrefixed] */
34854 {
34855 { 0, 0, 0, 0 },
34856 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34857 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b03e }
34858 },
34859/* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34860 {
34861 { 0, 0, 0, 0 },
34862 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34863 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b23e00 }
34864 },
34865/* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34866 {
34867 { 0, 0, 0, 0 },
34868 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34869 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b43e00 }
34870 },
34871/* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34872 {
34873 { 0, 0, 0, 0 },
34874 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34875 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b63e00 }
34876 },
34877/* movhh r0l,${Dsp-24-u8}[sb] */
34878 {
34879 { 0, 0, 0, 0 },
34880 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34881 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2be00 }
34882 },
34883/* movhh r0l,${Dsp-24-u16}[sb] */
34884 {
34885 { 0, 0, 0, 0 },
34886 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34887 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4be00 }
34888 },
34889/* movhh r0l,${Dsp-24-s8}[fb] */
34890 {
34891 { 0, 0, 0, 0 },
34892 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34893 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2fe00 }
34894 },
34895/* movhh r0l,${Dsp-24-s16}[fb] */
34896 {
34897 { 0, 0, 0, 0 },
34898 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34899 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4fe00 }
34900 },
34901/* movhh r0l,${Dsp-24-u16} */
34902 {
34903 { 0, 0, 0, 0 },
34904 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34905 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6fe00 }
34906 },
34907/* movhh r0l,${Dsp-24-u24} */
34908 {
34909 { 0, 0, 0, 0 },
34910 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34911 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6be00 }
34912 },
34913/* movhl r0l,$Dst32RnPrefixedQI */
34914 {
34915 { 0, 0, 0, 0 },
34916 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34917 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b82e }
34918 },
34919/* movhl r0l,$Dst32AnPrefixedQI */
34920 {
34921 { 0, 0, 0, 0 },
34922 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34923 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0ae }
34924 },
34925/* movhl r0l,[$Dst32AnPrefixed] */
34926 {
34927 { 0, 0, 0, 0 },
34928 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34929 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b02e }
34930 },
34931/* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34932 {
34933 { 0, 0, 0, 0 },
34934 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34935 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b22e00 }
34936 },
34937/* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34938 {
34939 { 0, 0, 0, 0 },
34940 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34941 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b42e00 }
34942 },
34943/* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34944 {
34945 { 0, 0, 0, 0 },
34946 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34947 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b62e00 }
34948 },
34949/* movhl r0l,${Dsp-24-u8}[sb] */
34950 {
34951 { 0, 0, 0, 0 },
34952 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34953 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2ae00 }
34954 },
34955/* movhl r0l,${Dsp-24-u16}[sb] */
34956 {
34957 { 0, 0, 0, 0 },
34958 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34959 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4ae00 }
34960 },
34961/* movhl r0l,${Dsp-24-s8}[fb] */
34962 {
34963 { 0, 0, 0, 0 },
34964 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34965 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ee00 }
34966 },
34967/* movhl r0l,${Dsp-24-s16}[fb] */
34968 {
34969 { 0, 0, 0, 0 },
34970 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34971 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ee00 }
34972 },
34973/* movhl r0l,${Dsp-24-u16} */
34974 {
34975 { 0, 0, 0, 0 },
34976 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34977 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ee00 }
34978 },
34979/* movhl r0l,${Dsp-24-u24} */
34980 {
34981 { 0, 0, 0, 0 },
34982 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34983 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6ae00 }
34984 },
34985/* movlh r0l,$Dst32RnPrefixedQI */
34986 {
34987 { 0, 0, 0, 0 },
34988 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34989 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b81e }
34990 },
34991/* movlh r0l,$Dst32AnPrefixedQI */
34992 {
34993 { 0, 0, 0, 0 },
34994 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34995 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b09e }
34996 },
34997/* movlh r0l,[$Dst32AnPrefixed] */
34998 {
34999 { 0, 0, 0, 0 },
35000 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
35001 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b01e }
35002 },
35003/* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
35004 {
35005 { 0, 0, 0, 0 },
35006 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
35007 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b21e00 }
35008 },
35009/* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
35010 {
35011 { 0, 0, 0, 0 },
35012 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
35013 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b41e00 }
35014 },
35015/* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
35016 {
35017 { 0, 0, 0, 0 },
35018 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
35019 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b61e00 }
35020 },
35021/* movlh r0l,${Dsp-24-u8}[sb] */
35022 {
35023 { 0, 0, 0, 0 },
35024 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
35025 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b29e00 }
35026 },
35027/* movlh r0l,${Dsp-24-u16}[sb] */
35028 {
35029 { 0, 0, 0, 0 },
35030 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
35031 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b49e00 }
35032 },
35033/* movlh r0l,${Dsp-24-s8}[fb] */
35034 {
35035 { 0, 0, 0, 0 },
35036 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
35037 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2de00 }
35038 },
35039/* movlh r0l,${Dsp-24-s16}[fb] */
35040 {
35041 { 0, 0, 0, 0 },
35042 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
35043 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4de00 }
35044 },
35045/* movlh r0l,${Dsp-24-u16} */
35046 {
35047 { 0, 0, 0, 0 },
35048 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
35049 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6de00 }
35050 },
35051/* movlh r0l,${Dsp-24-u24} */
35052 {
35053 { 0, 0, 0, 0 },
35054 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
35055 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b69e00 }
35056 },
35057/* movll r0l,$Dst32RnPrefixedQI */
35058 {
35059 { 0, 0, 0, 0 },
35060 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
35061 & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b80e }
35062 },
35063/* movll r0l,$Dst32AnPrefixedQI */
35064 {
35065 { 0, 0, 0, 0 },
35066 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
35067 & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b08e }
35068 },
35069/* movll r0l,[$Dst32AnPrefixed] */
35070 {
35071 { 0, 0, 0, 0 },
35072 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
35073 & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b00e }
35074 },
35075/* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
35076 {
35077 { 0, 0, 0, 0 },
35078 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
35079 & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b20e00 }
35080 },
35081/* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
35082 {
35083 { 0, 0, 0, 0 },
35084 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
35085 & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b40e00 }
35086 },
35087/* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
35088 {
35089 { 0, 0, 0, 0 },
35090 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
35091 & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b60e00 }
35092 },
35093/* movll r0l,${Dsp-24-u8}[sb] */
35094 {
35095 { 0, 0, 0, 0 },
35096 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
35097 & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b28e00 }
35098 },
35099/* movll r0l,${Dsp-24-u16}[sb] */
35100 {
35101 { 0, 0, 0, 0 },
35102 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
35103 & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b48e00 }
35104 },
35105/* movll r0l,${Dsp-24-s8}[fb] */
35106 {
35107 { 0, 0, 0, 0 },
35108 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
35109 & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ce00 }
35110 },
35111/* movll r0l,${Dsp-24-s16}[fb] */
35112 {
35113 { 0, 0, 0, 0 },
35114 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
35115 & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ce00 }
35116 },
35117/* movll r0l,${Dsp-24-u16} */
35118 {
35119 { 0, 0, 0, 0 },
35120 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
35121 & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ce00 }
35122 },
35123/* movll r0l,${Dsp-24-u24} */
35124 {
35125 { 0, 0, 0, 0 },
35126 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
35127 & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b68e00 }
35128 },
35129/* movhh $Dst16RnQI,r0l */
35130 {
35131 { 0, 0, 0, 0 },
35132 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35133 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c30 }
35134 },
35135/* movhh $Dst16AnQI,r0l */
35136 {
35137 { 0, 0, 0, 0 },
35138 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35139 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c34 }
35140 },
35141/* movhh [$Dst16An],r0l */
35142 {
35143 { 0, 0, 0, 0 },
35144 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35145 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c36 }
35146 },
35147/* movhh ${Dsp-16-u8}[$Dst16An],r0l */
35148 {
35149 { 0, 0, 0, 0 },
35150 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35151 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c3800 }
35152 },
35153/* movhh ${Dsp-16-u16}[$Dst16An],r0l */
35154 {
35155 { 0, 0, 0, 0 },
35156 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35157 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c3c0000 }
35158 },
35159/* movhh ${Dsp-16-u8}[sb],r0l */
35160 {
35161 { 0, 0, 0, 0 },
35162 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35163 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c3a00 }
35164 },
35165/* movhh ${Dsp-16-u16}[sb],r0l */
35166 {
35167 { 0, 0, 0, 0 },
35168 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35169 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c3e0000 }
35170 },
35171/* movhh ${Dsp-16-s8}[fb],r0l */
35172 {
35173 { 0, 0, 0, 0 },
35174 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35175 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c3b00 }
35176 },
35177/* movhh ${Dsp-16-u16},r0l */
35178 {
35179 { 0, 0, 0, 0 },
35180 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35181 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c3f0000 }
35182 },
35183/* movhl $Dst16RnQI,r0l */
35184 {
35185 { 0, 0, 0, 0 },
35186 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35187 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c10 }
35188 },
35189/* movhl $Dst16AnQI,r0l */
35190 {
35191 { 0, 0, 0, 0 },
35192 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35193 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c14 }
35194 },
35195/* movhl [$Dst16An],r0l */
35196 {
35197 { 0, 0, 0, 0 },
35198 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35199 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c16 }
35200 },
35201/* movhl ${Dsp-16-u8}[$Dst16An],r0l */
35202 {
35203 { 0, 0, 0, 0 },
35204 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35205 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c1800 }
35206 },
35207/* movhl ${Dsp-16-u16}[$Dst16An],r0l */
35208 {
35209 { 0, 0, 0, 0 },
35210 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35211 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c1c0000 }
35212 },
35213/* movhl ${Dsp-16-u8}[sb],r0l */
35214 {
35215 { 0, 0, 0, 0 },
35216 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35217 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c1a00 }
35218 },
35219/* movhl ${Dsp-16-u16}[sb],r0l */
35220 {
35221 { 0, 0, 0, 0 },
35222 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35223 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c1e0000 }
35224 },
35225/* movhl ${Dsp-16-s8}[fb],r0l */
35226 {
35227 { 0, 0, 0, 0 },
35228 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35229 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c1b00 }
35230 },
35231/* movhl ${Dsp-16-u16},r0l */
35232 {
35233 { 0, 0, 0, 0 },
35234 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35235 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c1f0000 }
35236 },
35237/* movlh $Dst16RnQI,r0l */
35238 {
35239 { 0, 0, 0, 0 },
35240 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35241 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c20 }
35242 },
35243/* movlh $Dst16AnQI,r0l */
35244 {
35245 { 0, 0, 0, 0 },
35246 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35247 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c24 }
35248 },
35249/* movlh [$Dst16An],r0l */
35250 {
35251 { 0, 0, 0, 0 },
35252 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35253 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c26 }
35254 },
35255/* movlh ${Dsp-16-u8}[$Dst16An],r0l */
35256 {
35257 { 0, 0, 0, 0 },
35258 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35259 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c2800 }
35260 },
35261/* movlh ${Dsp-16-u16}[$Dst16An],r0l */
35262 {
35263 { 0, 0, 0, 0 },
35264 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35265 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c2c0000 }
35266 },
35267/* movlh ${Dsp-16-u8}[sb],r0l */
35268 {
35269 { 0, 0, 0, 0 },
35270 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35271 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c2a00 }
35272 },
35273/* movlh ${Dsp-16-u16}[sb],r0l */
35274 {
35275 { 0, 0, 0, 0 },
35276 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35277 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c2e0000 }
35278 },
35279/* movlh ${Dsp-16-s8}[fb],r0l */
35280 {
35281 { 0, 0, 0, 0 },
35282 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35283 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c2b00 }
35284 },
35285/* movlh ${Dsp-16-u16},r0l */
35286 {
35287 { 0, 0, 0, 0 },
35288 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35289 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c2f0000 }
35290 },
35291/* movll $Dst16RnQI,r0l */
35292 {
35293 { 0, 0, 0, 0 },
35294 { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35295 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c00 }
35296 },
35297/* movll $Dst16AnQI,r0l */
35298 {
35299 { 0, 0, 0, 0 },
35300 { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35301 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c04 }
35302 },
35303/* movll [$Dst16An],r0l */
35304 {
35305 { 0, 0, 0, 0 },
35306 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35307 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c06 }
35308 },
35309/* movll ${Dsp-16-u8}[$Dst16An],r0l */
35310 {
35311 { 0, 0, 0, 0 },
35312 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35313 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c0800 }
35314 },
35315/* movll ${Dsp-16-u16}[$Dst16An],r0l */
35316 {
35317 { 0, 0, 0, 0 },
35318 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35319 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c0c0000 }
35320 },
35321/* movll ${Dsp-16-u8}[sb],r0l */
35322 {
35323 { 0, 0, 0, 0 },
35324 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35325 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c0a00 }
35326 },
35327/* movll ${Dsp-16-u16}[sb],r0l */
35328 {
35329 { 0, 0, 0, 0 },
35330 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35331 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c0e0000 }
35332 },
35333/* movll ${Dsp-16-s8}[fb],r0l */
35334 {
35335 { 0, 0, 0, 0 },
35336 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35337 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c0b00 }
35338 },
35339/* movll ${Dsp-16-u16},r0l */
35340 {
35341 { 0, 0, 0, 0 },
35342 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35343 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c0f0000 }
35344 },
35345/* movhh r0l,$Dst16RnQI */
35346 {
35347 { 0, 0, 0, 0 },
35348 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35349 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7cb0 }
35350 },
35351/* movhh r0l,$Dst16AnQI */
35352 {
35353 { 0, 0, 0, 0 },
35354 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35355 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7cb4 }
35356 },
35357/* movhh r0l,[$Dst16An] */
35358 {
35359 { 0, 0, 0, 0 },
35360 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35361 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7cb6 }
35362 },
35363/* movhh r0l,${Dsp-16-u8}[$Dst16An] */
35364 {
35365 { 0, 0, 0, 0 },
35366 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35367 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7cb800 }
35368 },
35369/* movhh r0l,${Dsp-16-u16}[$Dst16An] */
35370 {
35371 { 0, 0, 0, 0 },
35372 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35373 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cbc0000 }
35374 },
35375/* movhh r0l,${Dsp-16-u8}[sb] */
35376 {
35377 { 0, 0, 0, 0 },
35378 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35379 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7cba00 }
35380 },
35381/* movhh r0l,${Dsp-16-u16}[sb] */
35382 {
35383 { 0, 0, 0, 0 },
35384 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35385 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cbe0000 }
35386 },
35387/* movhh r0l,${Dsp-16-s8}[fb] */
35388 {
35389 { 0, 0, 0, 0 },
35390 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35391 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cbb00 }
35392 },
35393/* movhh r0l,${Dsp-16-u16} */
35394 {
35395 { 0, 0, 0, 0 },
35396 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35397 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7cbf0000 }
35398 },
35399/* movhl r0l,$Dst16RnQI */
35400 {
35401 { 0, 0, 0, 0 },
35402 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35403 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c90 }
35404 },
35405/* movhl r0l,$Dst16AnQI */
35406 {
35407 { 0, 0, 0, 0 },
35408 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35409 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c94 }
35410 },
35411/* movhl r0l,[$Dst16An] */
35412 {
35413 { 0, 0, 0, 0 },
35414 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35415 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c96 }
35416 },
35417/* movhl r0l,${Dsp-16-u8}[$Dst16An] */
35418 {
35419 { 0, 0, 0, 0 },
35420 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35421 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c9800 }
35422 },
35423/* movhl r0l,${Dsp-16-u16}[$Dst16An] */
35424 {
35425 { 0, 0, 0, 0 },
35426 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35427 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c9c0000 }
35428 },
35429/* movhl r0l,${Dsp-16-u8}[sb] */
35430 {
35431 { 0, 0, 0, 0 },
35432 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35433 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c9a00 }
35434 },
35435/* movhl r0l,${Dsp-16-u16}[sb] */
35436 {
35437 { 0, 0, 0, 0 },
35438 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35439 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c9e0000 }
35440 },
35441/* movhl r0l,${Dsp-16-s8}[fb] */
35442 {
35443 { 0, 0, 0, 0 },
35444 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35445 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c9b00 }
35446 },
35447/* movhl r0l,${Dsp-16-u16} */
35448 {
35449 { 0, 0, 0, 0 },
35450 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35451 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c9f0000 }
35452 },
35453/* movlh r0l,$Dst16RnQI */
35454 {
35455 { 0, 0, 0, 0 },
35456 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35457 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7ca0 }
35458 },
35459/* movlh r0l,$Dst16AnQI */
35460 {
35461 { 0, 0, 0, 0 },
35462 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35463 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7ca4 }
35464 },
35465/* movlh r0l,[$Dst16An] */
35466 {
35467 { 0, 0, 0, 0 },
35468 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35469 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7ca6 }
35470 },
35471/* movlh r0l,${Dsp-16-u8}[$Dst16An] */
35472 {
35473 { 0, 0, 0, 0 },
35474 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35475 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7ca800 }
35476 },
35477/* movlh r0l,${Dsp-16-u16}[$Dst16An] */
35478 {
35479 { 0, 0, 0, 0 },
35480 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35481 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cac0000 }
35482 },
35483/* movlh r0l,${Dsp-16-u8}[sb] */
35484 {
35485 { 0, 0, 0, 0 },
35486 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35487 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7caa00 }
35488 },
35489/* movlh r0l,${Dsp-16-u16}[sb] */
35490 {
35491 { 0, 0, 0, 0 },
35492 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35493 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cae0000 }
35494 },
35495/* movlh r0l,${Dsp-16-s8}[fb] */
35496 {
35497 { 0, 0, 0, 0 },
35498 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35499 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cab00 }
35500 },
35501/* movlh r0l,${Dsp-16-u16} */
35502 {
35503 { 0, 0, 0, 0 },
35504 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35505 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7caf0000 }
35506 },
35507/* movll r0l,$Dst16RnQI */
35508 {
35509 { 0, 0, 0, 0 },
35510 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35511 & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c80 }
35512 },
35513/* movll r0l,$Dst16AnQI */
35514 {
35515 { 0, 0, 0, 0 },
35516 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35517 & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c84 }
35518 },
35519/* movll r0l,[$Dst16An] */
35520 {
35521 { 0, 0, 0, 0 },
35522 { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35523 & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c86 }
35524 },
35525/* movll r0l,${Dsp-16-u8}[$Dst16An] */
35526 {
35527 { 0, 0, 0, 0 },
35528 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35529 & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c8800 }
35530 },
35531/* movll r0l,${Dsp-16-u16}[$Dst16An] */
35532 {
35533 { 0, 0, 0, 0 },
35534 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35535 & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c8c0000 }
35536 },
35537/* movll r0l,${Dsp-16-u8}[sb] */
35538 {
35539 { 0, 0, 0, 0 },
35540 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35541 & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c8a00 }
35542 },
35543/* movll r0l,${Dsp-16-u16}[sb] */
35544 {
35545 { 0, 0, 0, 0 },
35546 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35547 & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c8e0000 }
35548 },
35549/* movll r0l,${Dsp-16-s8}[fb] */
35550 {
35551 { 0, 0, 0, 0 },
35552 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35553 & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c8b00 }
35554 },
35555/* movll r0l,${Dsp-16-u16} */
35556 {
35557 { 0, 0, 0, 0 },
35558 { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35559 & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c8f0000 }
35560 },
35561/* mova [$Dst32AnUnprefixed],a1 */
35562 {
35563 { 0, 0, 0, 0 },
35564 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35565 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11b }
35566 },
35567/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
35568 {
35569 { 0, 0, 0, 0 },
35570 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35571 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31b00 }
35572 },
35573/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
35574 {
35575 { 0, 0, 0, 0 },
35576 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35577 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51b0000 }
35578 },
35579/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
35580 {
35581 { 0, 0, 0, 0 },
35582 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35583 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71b0000 }
35584 },
35585/* mova ${Dsp-16-u8}[sb],a1 */
35586 {
35587 { 0, 0, 0, 0 },
35588 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35589 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39b00 }
35590 },
35591/* mova ${Dsp-16-u16}[sb],a1 */
35592 {
35593 { 0, 0, 0, 0 },
35594 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35595 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59b0000 }
35596 },
35597/* mova ${Dsp-16-s8}[fb],a1 */
35598 {
35599 { 0, 0, 0, 0 },
35600 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35601 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3db00 }
35602 },
35603/* mova ${Dsp-16-s16}[fb],a1 */
35604 {
35605 { 0, 0, 0, 0 },
35606 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35607 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5db0000 }
35608 },
35609/* mova ${Dsp-16-u16},a1 */
35610 {
35611 { 0, 0, 0, 0 },
35612 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } },
35613 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7db0000 }
35614 },
35615/* mova ${Dsp-16-u24},a1 */
35616 {
35617 { 0, 0, 0, 0 },
35618 { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '1', 0 } },
35619 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79b0000 }
35620 },
35621/* mova [$Dst32AnUnprefixed],a0 */
35622 {
35623 { 0, 0, 0, 0 },
35624 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35625 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11a }
35626 },
35627/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
35628 {
35629 { 0, 0, 0, 0 },
35630 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35631 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31a00 }
35632 },
35633/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
35634 {
35635 { 0, 0, 0, 0 },
35636 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35637 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51a0000 }
35638 },
35639/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
35640 {
35641 { 0, 0, 0, 0 },
35642 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35643 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71a0000 }
35644 },
35645/* mova ${Dsp-16-u8}[sb],a0 */
35646 {
35647 { 0, 0, 0, 0 },
35648 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35649 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39a00 }
35650 },
35651/* mova ${Dsp-16-u16}[sb],a0 */
35652 {
35653 { 0, 0, 0, 0 },
35654 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35655 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59a0000 }
35656 },
35657/* mova ${Dsp-16-s8}[fb],a0 */
35658 {
35659 { 0, 0, 0, 0 },
35660 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35661 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3da00 }
35662 },
35663/* mova ${Dsp-16-s16}[fb],a0 */
35664 {
35665 { 0, 0, 0, 0 },
35666 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35667 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5da0000 }
35668 },
35669/* mova ${Dsp-16-u16},a0 */
35670 {
35671 { 0, 0, 0, 0 },
35672 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } },
35673 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7da0000 }
35674 },
35675/* mova ${Dsp-16-u24},a0 */
35676 {
35677 { 0, 0, 0, 0 },
35678 { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '0', 0 } },
35679 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79a0000 }
35680 },
35681/* mova [$Dst32AnUnprefixed],r3r1 */
35682 {
35683 { 0, 0, 0, 0 },
35684 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35685 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd119 }
35686 },
35687/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
35688 {
35689 { 0, 0, 0, 0 },
35690 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35691 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31900 }
35692 },
35693/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
35694 {
35695 { 0, 0, 0, 0 },
35696 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35697 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5190000 }
35698 },
35699/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
35700 {
35701 { 0, 0, 0, 0 },
35702 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35703 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7190000 }
35704 },
35705/* mova ${Dsp-16-u8}[sb],r3r1 */
35706 {
35707 { 0, 0, 0, 0 },
35708 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35709 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39900 }
35710 },
35711/* mova ${Dsp-16-u16}[sb],r3r1 */
35712 {
35713 { 0, 0, 0, 0 },
35714 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35715 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5990000 }
35716 },
35717/* mova ${Dsp-16-s8}[fb],r3r1 */
35718 {
35719 { 0, 0, 0, 0 },
35720 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35721 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d900 }
35722 },
35723/* mova ${Dsp-16-s16}[fb],r3r1 */
35724 {
35725 { 0, 0, 0, 0 },
35726 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35727 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d90000 }
35728 },
35729/* mova ${Dsp-16-u16},r3r1 */
35730 {
35731 { 0, 0, 0, 0 },
35732 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 'r', '1', 0 } },
35733 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d90000 }
35734 },
35735/* mova ${Dsp-16-u24},r3r1 */
35736 {
35737 { 0, 0, 0, 0 },
35738 { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '3', 'r', '1', 0 } },
35739 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7990000 }
35740 },
35741/* mova [$Dst32AnUnprefixed],r2r0 */
35742 {
35743 { 0, 0, 0, 0 },
35744 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35745 & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd118 }
35746 },
35747/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
35748 {
35749 { 0, 0, 0, 0 },
35750 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35751 & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31800 }
35752 },
35753/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
35754 {
35755 { 0, 0, 0, 0 },
35756 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35757 & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5180000 }
35758 },
35759/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
35760 {
35761 { 0, 0, 0, 0 },
35762 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35763 & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7180000 }
35764 },
35765/* mova ${Dsp-16-u8}[sb],r2r0 */
35766 {
35767 { 0, 0, 0, 0 },
35768 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35769 & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39800 }
35770 },
35771/* mova ${Dsp-16-u16}[sb],r2r0 */
35772 {
35773 { 0, 0, 0, 0 },
35774 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35775 & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5980000 }
35776 },
35777/* mova ${Dsp-16-s8}[fb],r2r0 */
35778 {
35779 { 0, 0, 0, 0 },
35780 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35781 & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d800 }
35782 },
35783/* mova ${Dsp-16-s16}[fb],r2r0 */
35784 {
35785 { 0, 0, 0, 0 },
35786 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35787 & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d80000 }
35788 },
35789/* mova ${Dsp-16-u16},r2r0 */
35790 {
35791 { 0, 0, 0, 0 },
35792 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 'r', '0', 0 } },
35793 & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d80000 }
35794 },
35795/* mova ${Dsp-16-u24},r2r0 */
35796 {
35797 { 0, 0, 0, 0 },
35798 { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '2', 'r', '0', 0 } },
35799 & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7980000 }
35800 },
35801/* mova [$Dst16An],a1 */
35802 {
35803 { 0, 0, 0, 0 },
35804 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35805 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb56 }
35806 },
35807/* mova ${Dsp-16-u8}[$Dst16An],a1 */
35808 {
35809 { 0, 0, 0, 0 },
35810 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35811 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb5800 }
35812 },
35813/* mova ${Dsp-16-u16}[$Dst16An],a1 */
35814 {
35815 { 0, 0, 0, 0 },
35816 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35817 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb5c0000 }
35818 },
35819/* mova ${Dsp-16-u8}[sb],a1 */
35820 {
35821 { 0, 0, 0, 0 },
35822 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35823 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb5a00 }
35824 },
35825/* mova ${Dsp-16-u16}[sb],a1 */
35826 {
35827 { 0, 0, 0, 0 },
35828 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35829 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb5e0000 }
35830 },
35831/* mova ${Dsp-16-s8}[fb],a1 */
35832 {
35833 { 0, 0, 0, 0 },
35834 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35835 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb5b00 }
35836 },
35837/* mova ${Dsp-16-u16},a1 */
35838 {
35839 { 0, 0, 0, 0 },
35840 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } },
35841 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb5f0000 }
35842 },
35843/* mova [$Dst16An],a0 */
35844 {
35845 { 0, 0, 0, 0 },
35846 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35847 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb46 }
35848 },
35849/* mova ${Dsp-16-u8}[$Dst16An],a0 */
35850 {
35851 { 0, 0, 0, 0 },
35852 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35853 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb4800 }
35854 },
35855/* mova ${Dsp-16-u16}[$Dst16An],a0 */
35856 {
35857 { 0, 0, 0, 0 },
35858 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35859 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb4c0000 }
35860 },
35861/* mova ${Dsp-16-u8}[sb],a0 */
35862 {
35863 { 0, 0, 0, 0 },
35864 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35865 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb4a00 }
35866 },
35867/* mova ${Dsp-16-u16}[sb],a0 */
35868 {
35869 { 0, 0, 0, 0 },
35870 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35871 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb4e0000 }
35872 },
35873/* mova ${Dsp-16-s8}[fb],a0 */
35874 {
35875 { 0, 0, 0, 0 },
35876 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35877 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb4b00 }
35878 },
35879/* mova ${Dsp-16-u16},a0 */
35880 {
35881 { 0, 0, 0, 0 },
35882 { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } },
35883 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb4f0000 }
35884 },
35885/* mova [$Dst16An],r3 */
35886 {
35887 { 0, 0, 0, 0 },
35888 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35889 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb36 }
35890 },
35891/* mova ${Dsp-16-u8}[$Dst16An],r3 */
35892 {
35893 { 0, 0, 0, 0 },
35894 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35895 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb3800 }
35896 },
35897/* mova ${Dsp-16-u16}[$Dst16An],r3 */
35898 {
35899 { 0, 0, 0, 0 },
35900 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35901 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb3c0000 }
35902 },
35903/* mova ${Dsp-16-u8}[sb],r3 */
35904 {
35905 { 0, 0, 0, 0 },
35906 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 0 } },
35907 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb3a00 }
35908 },
35909/* mova ${Dsp-16-u16}[sb],r3 */
35910 {
35911 { 0, 0, 0, 0 },
35912 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 0 } },
35913 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb3e0000 }
35914 },
35915/* mova ${Dsp-16-s8}[fb],r3 */
35916 {
35917 { 0, 0, 0, 0 },
35918 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 0 } },
35919 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb3b00 }
35920 },
35921/* mova ${Dsp-16-u16},r3 */
35922 {
35923 { 0, 0, 0, 0 },
35924 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 0 } },
35925 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb3f0000 }
35926 },
35927/* mova [$Dst16An],r2 */
35928 {
35929 { 0, 0, 0, 0 },
35930 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35931 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb26 }
35932 },
35933/* mova ${Dsp-16-u8}[$Dst16An],r2 */
35934 {
35935 { 0, 0, 0, 0 },
35936 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35937 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb2800 }
35938 },
35939/* mova ${Dsp-16-u16}[$Dst16An],r2 */
35940 {
35941 { 0, 0, 0, 0 },
35942 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35943 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb2c0000 }
35944 },
35945/* mova ${Dsp-16-u8}[sb],r2 */
35946 {
35947 { 0, 0, 0, 0 },
35948 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 0 } },
35949 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb2a00 }
35950 },
35951/* mova ${Dsp-16-u16}[sb],r2 */
35952 {
35953 { 0, 0, 0, 0 },
35954 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 0 } },
35955 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb2e0000 }
35956 },
35957/* mova ${Dsp-16-s8}[fb],r2 */
35958 {
35959 { 0, 0, 0, 0 },
35960 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 0 } },
35961 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb2b00 }
35962 },
35963/* mova ${Dsp-16-u16},r2 */
35964 {
35965 { 0, 0, 0, 0 },
35966 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 0 } },
35967 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb2f0000 }
35968 },
35969/* mova [$Dst16An],r1 */
35970 {
35971 { 0, 0, 0, 0 },
35972 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35973 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb16 }
35974 },
35975/* mova ${Dsp-16-u8}[$Dst16An],r1 */
35976 {
35977 { 0, 0, 0, 0 },
35978 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35979 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb1800 }
35980 },
35981/* mova ${Dsp-16-u16}[$Dst16An],r1 */
35982 {
35983 { 0, 0, 0, 0 },
35984 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35985 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb1c0000 }
35986 },
35987/* mova ${Dsp-16-u8}[sb],r1 */
35988 {
35989 { 0, 0, 0, 0 },
35990 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
35991 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb1a00 }
35992 },
35993/* mova ${Dsp-16-u16}[sb],r1 */
35994 {
35995 { 0, 0, 0, 0 },
35996 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
35997 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb1e0000 }
35998 },
35999/* mova ${Dsp-16-s8}[fb],r1 */
36000 {
36001 { 0, 0, 0, 0 },
36002 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } },
36003 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb1b00 }
36004 },
36005/* mova ${Dsp-16-u16},r1 */
36006 {
36007 { 0, 0, 0, 0 },
36008 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '1', 0 } },
36009 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb1f0000 }
36010 },
36011/* mova [$Dst16An],r0 */
36012 {
36013 { 0, 0, 0, 0 },
36014 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
36015 & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb06 }
36016 },
36017/* mova ${Dsp-16-u8}[$Dst16An],r0 */
36018 {
36019 { 0, 0, 0, 0 },
36020 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
36021 & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb0800 }
36022 },
36023/* mova ${Dsp-16-u16}[$Dst16An],r0 */
36024 {
36025 { 0, 0, 0, 0 },
36026 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
36027 & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb0c0000 }
36028 },
36029/* mova ${Dsp-16-u8}[sb],r0 */
36030 {
36031 { 0, 0, 0, 0 },
36032 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
36033 & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb0a00 }
36034 },
36035/* mova ${Dsp-16-u16}[sb],r0 */
36036 {
36037 { 0, 0, 0, 0 },
36038 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
36039 & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb0e0000 }
36040 },
36041/* mova ${Dsp-16-s8}[fb],r0 */
36042 {
36043 { 0, 0, 0, 0 },
36044 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } },
36045 & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb0b00 }
36046 },
36047/* mova ${Dsp-16-u16},r0 */
36048 {
36049 { 0, 0, 0, 0 },
36050 { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 0 } },
36051 & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb0f0000 }
36052 },
f75eb1c0 36053/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
49f58d10
JB		 36054 {
36055 { 0, 0, 0, 0 },
f75eb1c0 36056 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36057 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30f0000 }
36058 },
f75eb1c0 36059/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36060 {
36061 { 0, 0, 0, 0 },
f75eb1c0 36062 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36063 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38f0000 }
36064 },
f75eb1c0 36065/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36066 {
36067 { 0, 0, 0, 0 },
f75eb1c0 36068 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36069 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3cf0000 }
36070 },
f75eb1c0 36071/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
49f58d10
JB		 36072 {
36073 { 0, 0, 0, 0 },
f75eb1c0 36074 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36075 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50f0000 }
36076 },
f75eb1c0 36077/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 36078 {
36079 { 0, 0, 0, 0 },
f75eb1c0 36080 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36081 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58f0000 }
36082 },
f75eb1c0 36083/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
49f58d10
JB		 36084 {
36085 { 0, 0, 0, 0 },
f75eb1c0 36086 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36087 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5cf0000 }
36088 },
f75eb1c0 36089/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 36090 {
36091 { 0, 0, 0, 0 },
f75eb1c0 36092 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36093 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xa7cf0000 }
36094 },
f75eb1c0 36095/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
49f58d10
JB		 36096 {
36097 { 0, 0, 0, 0 },
f75eb1c0 36098 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36099 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70f0000 }
36100 },
f75eb1c0 36101/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
49f58d10
JB		 36102 {
36103 { 0, 0, 0, 0 },
f75eb1c0 36104 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36105 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xa78f0000 }
36106 },
f75eb1c0 36107/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36108 {
36109 { 0, 0, 0, 0 },
f75eb1c0 36110 { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36111 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xa90f00 }
36112 },
f75eb1c0 36113/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36114 {
36115 { 0, 0, 0, 0 },
f75eb1c0 36116 { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36117 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18f00 }
36118 },
f75eb1c0 36119/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
49f58d10
JB		 36120 {
36121 { 0, 0, 0, 0 },
f75eb1c0 36122 { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36123 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xa10f00 }
36124 },
f75eb1c0 36125/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
49f58d10
JB		 36126 {
36127 { 0, 0, 0, 0 },
f75eb1c0 36128 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36129 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20f0000 }
36130 },
f75eb1c0 36131/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36132 {
36133 { 0, 0, 0, 0 },
f75eb1c0 36134 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36135 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28f0000 }
36136 },
f75eb1c0 36137/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36138 {
36139 { 0, 0, 0, 0 },
f75eb1c0 36140 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36141 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2cf0000 }
36142 },
f75eb1c0 36143/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
49f58d10
JB		 36144 {
36145 { 0, 0, 0, 0 },
f75eb1c0 36146 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36147 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40f0000 }
36148 },
f75eb1c0 36149/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 36150 {
36151 { 0, 0, 0, 0 },
f75eb1c0 36152 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36153 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48f0000 }
36154 },
f75eb1c0 36155/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
49f58d10
JB		 36156 {
36157 { 0, 0, 0, 0 },
f75eb1c0 36158 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36159 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4cf0000 }
36160 },
f75eb1c0 36161/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 36162 {
36163 { 0, 0, 0, 0 },
f75eb1c0 36164 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36165 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xa6cf0000 }
36166 },
f75eb1c0 36167/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
49f58d10
JB		 36168 {
36169 { 0, 0, 0, 0 },
f75eb1c0 36170 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36171 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60f0000 }
36172 },
f75eb1c0 36173/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
49f58d10
JB		 36174 {
36175 { 0, 0, 0, 0 },
f75eb1c0 36176 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36177 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xa68f0000 }
36178 },
f75eb1c0 36179/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36180 {
36181 { 0, 0, 0, 0 },
f75eb1c0 36182 { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36183 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xa80f00 }
36184 },
f75eb1c0 36185/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36186 {
36187 { 0, 0, 0, 0 },
f75eb1c0 36188 { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36189 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xa08f00 }
36190 },
f75eb1c0 36191/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
49f58d10
JB		 36192 {
36193 { 0, 0, 0, 0 },
f75eb1c0 36194 { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36195 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xa00f00 }
36196 },
f75eb1c0 36197/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
49f58d10
JB		 36198 {
36199 { 0, 0, 0, 0 },
f75eb1c0 36200 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36201 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75380000 }
36202 },
f75eb1c0 36203/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36204 {
36205 { 0, 0, 0, 0 },
f75eb1c0 36206 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36207 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x753a0000 }
36208 },
f75eb1c0 36209/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36210 {
36211 { 0, 0, 0, 0 },
f75eb1c0 36212 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36213 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x753b0000 }
36214 },
f75eb1c0 36215/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
49f58d10
JB		 36216 {
36217 { 0, 0, 0, 0 },
f75eb1c0 36218 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36219 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x753c0000 }
36220 },
f75eb1c0 36221/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 36222 {
36223 { 0, 0, 0, 0 },
f75eb1c0 36224 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36225 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x753e0000 }
36226 },
f75eb1c0 36227/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 36228 {
36229 { 0, 0, 0, 0 },
f75eb1c0 36230 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36231 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x753f0000 }
36232 },
f75eb1c0 36233/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36234 {
36235 { 0, 0, 0, 0 },
f75eb1c0 36236 { { MNEM, OP (G), ' ', OP (DST16RNHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36237 & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x753000 }
36238 },
f75eb1c0 36239/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36240 {
36241 { 0, 0, 0, 0 },
f75eb1c0 36242 { { MNEM, OP (G), ' ', OP (DST16ANHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36243 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x753400 }
36244 },
f75eb1c0 36245/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
49f58d10
JB		 36246 {
36247 { 0, 0, 0, 0 },
f75eb1c0 36248 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36249 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x753600 }
36250 },
f75eb1c0 36251/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
49f58d10
JB		 36252 {
36253 { 0, 0, 0, 0 },
f75eb1c0 36254 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36255 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74380000 }
36256 },
f75eb1c0 36257/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36258 {
36259 { 0, 0, 0, 0 },
f75eb1c0 36260 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36261 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x743a0000 }
36262 },
f75eb1c0 36263/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 36264 {
36265 { 0, 0, 0, 0 },
f75eb1c0 36266 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36267 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x743b0000 }
36268 },
f75eb1c0 36269/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
49f58d10
JB		 36270 {
36271 { 0, 0, 0, 0 },
f75eb1c0 36272 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36273 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x743c0000 }
36274 },
f75eb1c0 36275/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 36276 {
36277 { 0, 0, 0, 0 },
f75eb1c0 36278 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36279 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x743e0000 }
36280 },
f75eb1c0 36281/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 36282 {
36283 { 0, 0, 0, 0 },
f75eb1c0 36284 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36285 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x743f0000 }
36286 },
f75eb1c0 36287/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36288 {
36289 { 0, 0, 0, 0 },
f75eb1c0 36290 { { MNEM, OP (G), ' ', OP (DST16RNQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36291 & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x743000 }
36292 },
f75eb1c0 36293/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 36294 {
36295 { 0, 0, 0, 0 },
f75eb1c0 36296 { { MNEM, OP (G), ' ', OP (DST16ANQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36297 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x743400 }
36298 },
f75eb1c0 36299/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
49f58d10
JB		 36300 {
36301 { 0, 0, 0, 0 },
f75eb1c0 36302 { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
49f58d10
JB		 36303 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x743600 }
36304 },
f75eb1c0 36305/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 36306 {
36307 { 0, 0, 0, 0 },
f75eb1c0 36308 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36309 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30f0000 }
36310 },
f75eb1c0 36311/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 36312 {
36313 { 0, 0, 0, 0 },
f75eb1c0 36314 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36315 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38f0000 }
36316 },
f75eb1c0 36317/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 36318 {
36319 { 0, 0, 0, 0 },
f75eb1c0 36320 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36321 & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3cf0000 }
36322 },
f75eb1c0 36323/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 36324 {
36325 { 0, 0, 0, 0 },
f75eb1c0 36326 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36327 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50f0000 }
36328 },
f75eb1c0 36329/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 36330 {
36331 { 0, 0, 0, 0 },
f75eb1c0 36332 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36333 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58f0000 }
36334 },
f75eb1c0 36335/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
49f58d10
JB		 36336 {
36337 { 0, 0, 0, 0 },
f75eb1c0 36338 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36339 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5cf0000 }
36340 },
f75eb1c0 36341/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 36342 {
36343 { 0, 0, 0, 0 },
f75eb1c0 36344 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 36345 & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xb7cf0000 }
36346 },
f75eb1c0 36347/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 36348 {
36349 { 0, 0, 0, 0 },
f75eb1c0 36350 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36351 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70f0000 }
36352 },
f75eb1c0 36353/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
49f58d10
JB		 36354 {
36355 { 0, 0, 0, 0 },
f75eb1c0 36356 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 36357 & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xb78f0000 }
36358 },
f75eb1c0 36359/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
49f58d10
JB		 36360 {
36361 { 0, 0, 0, 0 },
f75eb1c0 36362 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49f58d10
JB		 36363 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xb90f00 }
36364 },
f75eb1c0 36365/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
49f58d10
JB		 36366 {
36367 { 0, 0, 0, 0 },
f75eb1c0 36368 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49f58d10
JB		 36369 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18f00 }
36370 },
f75eb1c0 36371/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
49f58d10
JB		 36372 {
36373 { 0, 0, 0, 0 },
f75eb1c0 36374 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36375 & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xb10f00 }
36376 },
f75eb1c0 36377/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 36378 {
36379 { 0, 0, 0, 0 },
f75eb1c0 36380 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36381 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20f0000 }
36382 },
f75eb1c0 36383/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 36384 {
36385 { 0, 0, 0, 0 },
f75eb1c0 36386 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36387 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28f0000 }
36388 },
f75eb1c0 36389/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 36390 {
36391 { 0, 0, 0, 0 },
f75eb1c0 36392 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36393 & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2cf0000 }
36394 },
f75eb1c0 36395/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 36396 {
36397 { 0, 0, 0, 0 },
f75eb1c0 36398 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36399 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40f0000 }
36400 },
f75eb1c0 36401/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 36402 {
36403 { 0, 0, 0, 0 },
f75eb1c0 36404 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36405 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48f0000 }
36406 },
f75eb1c0 36407/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
49f58d10
JB		 36408 {
36409 { 0, 0, 0, 0 },
f75eb1c0 36410 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36411 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4cf0000 }
36412 },
f75eb1c0 36413/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 36414 {
36415 { 0, 0, 0, 0 },
f75eb1c0 36416 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 36417 & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xb6cf0000 }
36418 },
f75eb1c0 36419/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 36420 {
36421 { 0, 0, 0, 0 },
f75eb1c0 36422 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36423 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60f0000 }
36424 },
f75eb1c0 36425/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
49f58d10
JB		 36426 {
36427 { 0, 0, 0, 0 },
f75eb1c0 36428 { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
49f58d10
JB		 36429 & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xb68f0000 }
36430 },
f75eb1c0 36431/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
49f58d10
JB		 36432 {
36433 { 0, 0, 0, 0 },
f75eb1c0 36434 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49f58d10
JB		 36435 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xb80f00 }
36436 },
f75eb1c0 36437/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
49f58d10
JB		 36438 {
36439 { 0, 0, 0, 0 },
f75eb1c0 36440 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49f58d10
JB		 36441 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xb08f00 }
36442 },
f75eb1c0 36443/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
49f58d10
JB		 36444 {
36445 { 0, 0, 0, 0 },
f75eb1c0 36446 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 36447 & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xb00f00 }
36448 },
f75eb1c0 36449/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 36450 {
36451 { 0, 0, 0, 0 },
f75eb1c0 36452 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36453 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75b80000 }
36454 },
f75eb1c0 36455/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 36456 {
36457 { 0, 0, 0, 0 },
f75eb1c0 36458 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36459 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x75ba0000 }
36460 },
f75eb1c0 36461/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 36462 {
36463 { 0, 0, 0, 0 },
f75eb1c0 36464 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36465 & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x75bb0000 }
36466 },
f75eb1c0 36467/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 36468 {
36469 { 0, 0, 0, 0 },
f75eb1c0 36470 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36471 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x75bc0000 }
36472 },
f75eb1c0 36473/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 36474 {
36475 { 0, 0, 0, 0 },
f75eb1c0 36476 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36477 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x75be0000 }
36478 },
f75eb1c0 36479/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 36480 {
36481 { 0, 0, 0, 0 },
f75eb1c0 36482 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 36483 & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x75bf0000 }
36484 },
f75eb1c0 36485/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
49f58d10
JB		 36486 {
36487 { 0, 0, 0, 0 },
f75eb1c0 36488 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNHI), 0 } },
49f58d10
JB		 36489 & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75b000 }
36490 },
f75eb1c0 36491/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
49f58d10
JB		 36492 {
36493 { 0, 0, 0, 0 },
f75eb1c0 36494 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANHI), 0 } },
49f58d10
JB		 36495 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75b400 }
36496 },
f75eb1c0 36497/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
49f58d10
JB		 36498 {
36499 { 0, 0, 0, 0 },
f75eb1c0 36500 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36501 & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75b600 }
36502 },
f75eb1c0 36503/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 36504 {
36505 { 0, 0, 0, 0 },
f75eb1c0 36506 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36507 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74b80000 }
36508 },
f75eb1c0 36509/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 36510 {
36511 { 0, 0, 0, 0 },
f75eb1c0 36512 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36513 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x74ba0000 }
36514 },
f75eb1c0 36515/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 36516 {
36517 { 0, 0, 0, 0 },
f75eb1c0 36518 { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 36519 & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x74bb0000 }
36520 },
f75eb1c0 36521/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 36522 {
36523 { 0, 0, 0, 0 },
f75eb1c0 36524 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36525 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x74bc0000 }
36526 },
f75eb1c0 36527/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 36528 {
36529 { 0, 0, 0, 0 },
f75eb1c0 36530 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 36531 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x74be0000 }
36532 },
f75eb1c0 36533/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 36534 {
36535 { 0, 0, 0, 0 },
f75eb1c0 36536 { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
49f58d10
JB		 36537 & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x74bf0000 }
36538 },
f75eb1c0 36539/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
49f58d10
JB		 36540 {
36541 { 0, 0, 0, 0 },
f75eb1c0 36542 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNQI), 0 } },
49f58d10
JB		 36543 & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74b000 }
36544 },
f75eb1c0 36545/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
49f58d10
JB		 36546 {
36547 { 0, 0, 0, 0 },
f75eb1c0 36548 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANQI), 0 } },
49f58d10
JB		 36549 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74b400 }
36550 },
f75eb1c0 36551/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
49f58d10
JB		 36552 {
36553 { 0, 0, 0, 0 },
f75eb1c0 36554 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
49f58d10
JB		 36555 & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74b600 }
36556 },
36557/* mov.l${S} ${Dsp-8-u8}[sb],a1 */
36558 {
36559 { 0, 0, 0, 0 },
36560 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
36561 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6900 }
36562 },
36563/* mov.l${S} ${Dsp-8-s8}[fb],a1 */
36564 {
36565 { 0, 0, 0, 0 },
36566 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
36567 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7900 }
36568 },
36569/* mov.l${S} ${Dsp-8-u8}[sb],a0 */
36570 {
36571 { 0, 0, 0, 0 },
36572 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
36573 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6800 }
36574 },
36575/* mov.l${S} ${Dsp-8-s8}[fb],a0 */
36576 {
36577 { 0, 0, 0, 0 },
36578 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
36579 & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7800 }
36580 },
36581/* mov.l${S} ${Dsp-8-u16},a1 */
36582 {
36583 { 0, 0, 0, 0 },
36584 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '1', 0 } },
36585 & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x590000 }
36586 },
36587/* mov.l${S} ${Dsp-8-u16},a0 */
36588 {
36589 { 0, 0, 0, 0 },
36590 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '0', 0 } },
36591 & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x580000 }
36592 },
36593/* mov.w${S} r0,${Dsp-8-u8}[sb] */
36594 {
36595 { 0, 0, 0, 0 },
36596 { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36597 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2100 }
36598 },
36599/* mov.w${S} r0,${Dsp-8-s8}[fb] */
36600 {
36601 { 0, 0, 0, 0 },
36602 { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36603 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3100 }
36604 },
36605/* mov.b${S} r0l,${Dsp-8-u8}[sb] */
36606 {
36607 { 0, 0, 0, 0 },
36608 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36609 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2000 }
36610 },
36611/* mov.b${S} r0l,${Dsp-8-s8}[fb] */
36612 {
36613 { 0, 0, 0, 0 },
36614 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36615 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3000 }
36616 },
36617/* mov.w${S} r0,${Dsp-8-u16} */
36618 {
36619 { 0, 0, 0, 0 },
36620 { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U16), 0 } },
36621 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x110000 }
36622 },
36623/* mov.b${S} r0l,${Dsp-8-u16} */
36624 {
36625 { 0, 0, 0, 0 },
36626 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U16), 0 } },
36627 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x100000 }
36628 },
36629/* mov.w${S} ${Dsp-8-u8}[sb],r1 */
36630 {
36631 { 0, 0, 0, 0 },
36632 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
36633 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6f00 }
36634 },
36635/* mov.w${S} ${Dsp-8-s8}[fb],r1 */
36636 {
36637 { 0, 0, 0, 0 },
36638 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } },
36639 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7f00 }
36640 },
36641/* mov.b${S} ${Dsp-8-u8}[sb],r1l */
36642 {
36643 { 0, 0, 0, 0 },
36644 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 'l', 0 } },
36645 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6e00 }
36646 },
36647/* mov.b${S} ${Dsp-8-s8}[fb],r1l */
36648 {
36649 { 0, 0, 0, 0 },
36650 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 'l', 0 } },
36651 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7e00 }
36652 },
36653/* mov.w${S} ${Dsp-8-u16},r1 */
36654 {
36655 { 0, 0, 0, 0 },
36656 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 0 } },
36657 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x5f0000 }
36658 },
36659/* mov.b${S} ${Dsp-8-u16},r1l */
36660 {
36661 { 0, 0, 0, 0 },
36662 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 'l', 0 } },
36663 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x5e0000 }
36664 },
f75eb1c0 36665/* mov.w${S} r0,r1 */
49f58d10
JB		 36666 {
36667 { 0, 0, 0, 0 },
f75eb1c0
DD		 36668 { { MNEM, OP (S), ' ', 'r', '0', ',', 'r', '1', 0 } },
36669 & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x4f }
49f58d10
JB		 36670 },
36671/* mov.b${S} r0l,r1l */
36672 {
36673 { 0, 0, 0, 0 },
36674 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'r', '1', 'l', 0 } },
36675 & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x4e }
36676 },
36677/* mov.w${S} ${Dsp-8-u8}[sb],r0 */
36678 {
36679 { 0, 0, 0, 0 },
36680 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
36681 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2900 }
36682 },
36683/* mov.w${S} ${Dsp-8-s8}[fb],r0 */
36684 {
36685 { 0, 0, 0, 0 },
36686 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } },
36687 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3900 }
36688 },
36689/* mov.b${S} ${Dsp-8-u8}[sb],r0l */
36690 {
36691 { 0, 0, 0, 0 },
36692 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
36693 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2800 }
36694 },
36695/* mov.b${S} ${Dsp-8-s8}[fb],r0l */
36696 {
36697 { 0, 0, 0, 0 },
36698 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
36699 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3800 }
36700 },
36701/* mov.w${S} ${Dsp-8-u16},r0 */
36702 {
36703 { 0, 0, 0, 0 },
36704 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 0 } },
36705 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x190000 }
36706 },
36707/* mov.b${S} ${Dsp-8-u16},r0l */
36708 {
36709 { 0, 0, 0, 0 },
36710 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 'l', 0 } },
36711 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x180000 }
36712 },
36713/* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36714 {
36715 { 0, 0, 0, 0 },
36716 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
5348b81e 36717 & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x8 }
49f58d10
JB		 36718 },
36719/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36720 {
36721 { 0, 0, 0, 0 },
36722 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 36723 & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x900 }
49f58d10
JB		 36724 },
36725/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36726 {
36727 { 0, 0, 0, 0 },
36728 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 36729 & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0xa00 }
49f58d10
JB		 36730 },
36731/* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36732 {
36733 { 0, 0, 0, 0 },
36734 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
5348b81e 36735 & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0xb0000 }
49f58d10
JB		 36736 },
36737/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
36738 {
36739 { 0, 0, 0, 0 },
36740 { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
5348b81e 36741 & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x100 }
49f58d10
JB		 36742 },
36743/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
36744 {
36745 { 0, 0, 0, 0 },
36746 { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
5348b81e 36747 & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x200 }
49f58d10
JB		 36748 },
36749/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
36750 {
36751 { 0, 0, 0, 0 },
36752 { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U16), 0 } },
5348b81e 36753 & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x30000 }
49f58d10
JB		 36754 },
36755/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36756 {
36757 { 0, 0, 0, 0 },
36758 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36759 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990300 }
36760 },
36761/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
36762 {
36763 { 0, 0, 0, 0 },
36764 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36765 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992300 }
36766 },
36767/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
36768 {
36769 { 0, 0, 0, 0 },
36770 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36771 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993300 }
36772 },
36773/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36774 {
36775 { 0, 0, 0, 0 },
36776 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36777 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918300 }
36778 },
36779/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
36780 {
36781 { 0, 0, 0, 0 },
36782 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36783 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a300 }
36784 },
36785/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
36786 {
36787 { 0, 0, 0, 0 },
36788 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36789 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b300 }
36790 },
36791/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36792 {
36793 { 0, 0, 0, 0 },
36794 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36795 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910300 }
36796 },
36797/* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36798 {
36799 { 0, 0, 0, 0 },
36800 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36801 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912300 }
36802 },
36803/* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36804 {
36805 { 0, 0, 0, 0 },
36806 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36807 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913300 }
36808 },
36809/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36810 {
36811 { 0, 0, 0, 0 },
36812 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36813 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93030000 }
36814 },
36815/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36816 {
36817 { 0, 0, 0, 0 },
36818 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36819 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93230000 }
36820 },
36821/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36822 {
36823 { 0, 0, 0, 0 },
36824 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36825 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93330000 }
36826 },
36827/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36828 {
36829 { 0, 0, 0, 0 },
36830 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36831 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95030000 }
36832 },
36833/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36834 {
36835 { 0, 0, 0, 0 },
36836 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36837 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95230000 }
36838 },
36839/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36840 {
36841 { 0, 0, 0, 0 },
36842 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36843 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95330000 }
36844 },
36845/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36846 {
36847 { 0, 0, 0, 0 },
36848 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36849 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97030000 }
36850 },
36851/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36852 {
36853 { 0, 0, 0, 0 },
36854 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36855 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97230000 }
36856 },
36857/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36858 {
36859 { 0, 0, 0, 0 },
36860 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36861 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97330000 }
36862 },
36863/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36864 {
36865 { 0, 0, 0, 0 },
36866 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36867 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93830000 }
36868 },
36869/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36870 {
36871 { 0, 0, 0, 0 },
36872 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36873 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a30000 }
36874 },
36875/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36876 {
36877 { 0, 0, 0, 0 },
36878 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36879 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b30000 }
36880 },
36881/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36882 {
36883 { 0, 0, 0, 0 },
36884 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36885 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95830000 }
36886 },
36887/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36888 {
36889 { 0, 0, 0, 0 },
36890 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36891 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a30000 }
36892 },
36893/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36894 {
36895 { 0, 0, 0, 0 },
36896 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36897 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b30000 }
36898 },
36899/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36900 {
36901 { 0, 0, 0, 0 },
36902 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36903 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c30000 }
36904 },
36905/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36906 {
36907 { 0, 0, 0, 0 },
36908 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36909 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e30000 }
36910 },
36911/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36912 {
36913 { 0, 0, 0, 0 },
36914 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36915 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f30000 }
36916 },
36917/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36918 {
36919 { 0, 0, 0, 0 },
36920 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36921 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c30000 }
36922 },
36923/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36924 {
36925 { 0, 0, 0, 0 },
36926 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36927 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e30000 }
36928 },
36929/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36930 {
36931 { 0, 0, 0, 0 },
36932 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36933 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f30000 }
36934 },
36935/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36936 {
36937 { 0, 0, 0, 0 },
36938 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
36939 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c30000 }
36940 },
36941/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36942 {
36943 { 0, 0, 0, 0 },
36944 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
36945 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e30000 }
36946 },
36947/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36948 {
36949 { 0, 0, 0, 0 },
36950 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
36951 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f30000 }
36952 },
36953/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36954 {
36955 { 0, 0, 0, 0 },
36956 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
36957 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97830000 }
36958 },
36959/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36960 {
36961 { 0, 0, 0, 0 },
36962 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
36963 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a30000 }
36964 },
36965/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36966 {
36967 { 0, 0, 0, 0 },
36968 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
36969 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b30000 }
36970 },
36971/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36972 {
36973 { 0, 0, 0, 0 },
36974 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36975 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9030000 }
36976 },
36977/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
36978 {
36979 { 0, 0, 0, 0 },
36980 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36981 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9230000 }
36982 },
36983/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
36984 {
36985 { 0, 0, 0, 0 },
36986 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36987 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9330000 }
36988 },
36989/* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
36990 {
36991 { 0, 0, 0, 0 },
36992 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36993 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9330000 }
36994 },
36995/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36996 {
36997 { 0, 0, 0, 0 },
36998 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36999 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1830000 }
37000 },
37001/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
37002 {
37003 { 0, 0, 0, 0 },
37004 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37005 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a30000 }
37006 },
37007/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
37008 {
37009 { 0, 0, 0, 0 },
37010 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37011 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b30000 }
37012 },
37013/* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
37014 {
37015 { 0, 0, 0, 0 },
37016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37017 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b30000 }
37018 },
37019/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37020 {
37021 { 0, 0, 0, 0 },
37022 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37023 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1030000 }
37024 },
37025/* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37026 {
37027 { 0, 0, 0, 0 },
37028 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37029 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1230000 }
37030 },
37031/* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37032 {
37033 { 0, 0, 0, 0 },
37034 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37035 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1330000 }
37036 },
37037/* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37038 {
37039 { 0, 0, 0, 0 },
37040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37041 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1330000 }
37042 },
37043/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37044 {
37045 { 0, 0, 0, 0 },
37046 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37047 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3030000 }
37048 },
37049/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37050 {
37051 { 0, 0, 0, 0 },
37052 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37053 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3230000 }
37054 },
37055/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37056 {
37057 { 0, 0, 0, 0 },
37058 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37059 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3330000 }
37060 },
37061/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37062 {
37063 { 0, 0, 0, 0 },
37064 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37065 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3330000 }
37066 },
37067/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37068 {
37069 { 0, 0, 0, 0 },
37070 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37071 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5030000 }
37072 },
37073/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37074 {
37075 { 0, 0, 0, 0 },
37076 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37077 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5230000 }
37078 },
37079/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37080 {
37081 { 0, 0, 0, 0 },
37082 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37083 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5330000 }
37084 },
37085/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37086 {
37087 { 0, 0, 0, 0 },
37088 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37089 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5330000 }
37090 },
37091/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37092 {
37093 { 0, 0, 0, 0 },
37094 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37095 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7030000 }
37096 },
37097/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37098 {
37099 { 0, 0, 0, 0 },
37100 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37101 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7230000 }
37102 },
37103/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37104 {
37105 { 0, 0, 0, 0 },
37106 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37107 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7330000 }
37108 },
37109/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37110 {
37111 { 0, 0, 0, 0 },
37112 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37113 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7330000 }
37114 },
37115/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37116 {
37117 { 0, 0, 0, 0 },
37118 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37119 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3830000 }
37120 },
37121/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37122 {
37123 { 0, 0, 0, 0 },
37124 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37125 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a30000 }
37126 },
37127/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37128 {
37129 { 0, 0, 0, 0 },
37130 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37131 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b30000 }
37132 },
37133/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37134 {
37135 { 0, 0, 0, 0 },
37136 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37137 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b30000 }
37138 },
37139/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37140 {
37141 { 0, 0, 0, 0 },
37142 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37143 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5830000 }
37144 },
37145/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37146 {
37147 { 0, 0, 0, 0 },
37148 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37149 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a30000 }
37150 },
37151/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37152 {
37153 { 0, 0, 0, 0 },
37154 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37155 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b30000 }
37156 },
37157/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37158 {
37159 { 0, 0, 0, 0 },
37160 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37161 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b30000 }
37162 },
37163/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37164 {
37165 { 0, 0, 0, 0 },
37166 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37167 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c30000 }
37168 },
37169/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37170 {
37171 { 0, 0, 0, 0 },
37172 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37173 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e30000 }
37174 },
37175/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37176 {
37177 { 0, 0, 0, 0 },
37178 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37179 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f30000 }
37180 },
37181/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37182 {
37183 { 0, 0, 0, 0 },
37184 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37185 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f30000 }
37186 },
37187/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37188 {
37189 { 0, 0, 0, 0 },
37190 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37191 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c30000 }
37192 },
37193/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37194 {
37195 { 0, 0, 0, 0 },
37196 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37197 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e30000 }
37198 },
37199/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37200 {
37201 { 0, 0, 0, 0 },
37202 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37203 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f30000 }
37204 },
37205/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37206 {
37207 { 0, 0, 0, 0 },
37208 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37209 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f30000 }
37210 },
37211/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37212 {
37213 { 0, 0, 0, 0 },
37214 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
37215 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c30000 }
37216 },
37217/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37218 {
37219 { 0, 0, 0, 0 },
37220 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
37221 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e30000 }
37222 },
37223/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37224 {
37225 { 0, 0, 0, 0 },
37226 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
37227 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f30000 }
37228 },
37229/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
37230 {
37231 { 0, 0, 0, 0 },
37232 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
37233 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f30000 }
37234 },
37235/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37236 {
37237 { 0, 0, 0, 0 },
37238 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
37239 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7830000 }
37240 },
37241/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37242 {
37243 { 0, 0, 0, 0 },
37244 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
37245 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a30000 }
37246 },
37247/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37248 {
37249 { 0, 0, 0, 0 },
37250 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
37251 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b30000 }
37252 },
37253/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
37254 {
37255 { 0, 0, 0, 0 },
37256 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
37257 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b30000 }
37258 },
37259/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
37260 {
37261 { 0, 0, 0, 0 },
37262 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37263 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9030000 }
37264 },
37265/* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
37266 {
37267 { 0, 0, 0, 0 },
37268 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37269 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9230000 }
37270 },
37271/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
37272 {
37273 { 0, 0, 0, 0 },
37274 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37275 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1830000 }
37276 },
37277/* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
37278 {
37279 { 0, 0, 0, 0 },
37280 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37281 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a30000 }
37282 },
37283/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37284 {
37285 { 0, 0, 0, 0 },
37286 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37287 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1030000 }
37288 },
37289/* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37290 {
37291 { 0, 0, 0, 0 },
37292 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37293 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1230000 }
37294 },
37295/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37296 {
37297 { 0, 0, 0, 0 },
37298 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37299 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3030000 }
37300 },
37301/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37302 {
37303 { 0, 0, 0, 0 },
37304 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37305 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3230000 }
37306 },
37307/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37308 {
37309 { 0, 0, 0, 0 },
37310 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37311 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5030000 }
37312 },
37313/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37314 {
37315 { 0, 0, 0, 0 },
37316 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37317 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5230000 }
37318 },
37319/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37320 {
37321 { 0, 0, 0, 0 },
37322 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37323 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7030000 }
37324 },
37325/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37326 {
37327 { 0, 0, 0, 0 },
37328 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37329 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7230000 }
37330 },
37331/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37332 {
37333 { 0, 0, 0, 0 },
37334 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
37335 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3830000 }
37336 },
37337/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37338 {
37339 { 0, 0, 0, 0 },
37340 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
37341 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a30000 }
37342 },
37343/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37344 {
37345 { 0, 0, 0, 0 },
37346 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
37347 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5830000 }
37348 },
37349/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37350 {
37351 { 0, 0, 0, 0 },
37352 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
37353 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a30000 }
37354 },
37355/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37356 {
37357 { 0, 0, 0, 0 },
37358 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
37359 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c30000 }
37360 },
37361/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37362 {
37363 { 0, 0, 0, 0 },
37364 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
37365 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e30000 }
37366 },
37367/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37368 {
37369 { 0, 0, 0, 0 },
37370 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
37371 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c30000 }
37372 },
37373/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37374 {
37375 { 0, 0, 0, 0 },
37376 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
37377 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e30000 }
37378 },
37379/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37380 {
37381 { 0, 0, 0, 0 },
37382 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
37383 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c30000 }
37384 },
37385/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
37386 {
37387 { 0, 0, 0, 0 },
37388 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
37389 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e30000 }
37390 },
37391/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37392 {
37393 { 0, 0, 0, 0 },
37394 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
37395 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7830000 }
37396 },
37397/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
37398 {
37399 { 0, 0, 0, 0 },
37400 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
37401 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a30000 }
37402 },
37403/* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
37404 {
37405 { 0, 0, 0, 0 },
37406 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37407 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc903 }
37408 },
37409/* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
37410 {
37411 { 0, 0, 0, 0 },
37412 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37413 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8923 }
37414 },
37415/* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
37416 {
37417 { 0, 0, 0, 0 },
37418 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37419 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8903 }
37420 },
37421/* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
37422 {
37423 { 0, 0, 0, 0 },
37424 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37425 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc183 }
37426 },
37427/* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
37428 {
37429 { 0, 0, 0, 0 },
37430 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37431 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a3 }
37432 },
37433/* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
37434 {
37435 { 0, 0, 0, 0 },
37436 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37437 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8183 }
37438 },
37439/* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
37440 {
37441 { 0, 0, 0, 0 },
37442 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37443 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc103 }
37444 },
37445/* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
37446 {
37447 { 0, 0, 0, 0 },
37448 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37449 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8123 }
37450 },
37451/* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37452 {
37453 { 0, 0, 0, 0 },
37454 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37455 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8103 }
37456 },
37457/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37458 {
37459 { 0, 0, 0, 0 },
37460 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37461 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30300 }
37462 },
37463/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37464 {
37465 { 0, 0, 0, 0 },
37466 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37467 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832300 }
37468 },
37469/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37470 {
37471 { 0, 0, 0, 0 },
37472 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37473 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830300 }
37474 },
37475/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37476 {
37477 { 0, 0, 0, 0 },
37478 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37479 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5030000 }
37480 },
37481/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37482 {
37483 { 0, 0, 0, 0 },
37484 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37485 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85230000 }
37486 },
37487/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37488 {
37489 { 0, 0, 0, 0 },
37490 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37491 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85030000 }
37492 },
37493/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37494 {
37495 { 0, 0, 0, 0 },
37496 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37497 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7030000 }
37498 },
37499/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37500 {
37501 { 0, 0, 0, 0 },
37502 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37503 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87230000 }
37504 },
37505/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37506 {
37507 { 0, 0, 0, 0 },
37508 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37509 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87030000 }
37510 },
37511/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
37512 {
37513 { 0, 0, 0, 0 },
37514 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37515 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38300 }
37516 },
37517/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
37518 {
37519 { 0, 0, 0, 0 },
37520 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37521 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a300 }
37522 },
37523/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37524 {
37525 { 0, 0, 0, 0 },
37526 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37527 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838300 }
37528 },
37529/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
37530 {
37531 { 0, 0, 0, 0 },
37532 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37533 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5830000 }
37534 },
37535/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
37536 {
37537 { 0, 0, 0, 0 },
37538 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37539 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a30000 }
37540 },
37541/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37542 {
37543 { 0, 0, 0, 0 },
37544 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37545 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85830000 }
37546 },
37547/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
37548 {
37549 { 0, 0, 0, 0 },
37550 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37551 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c300 }
37552 },
37553/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
37554 {
37555 { 0, 0, 0, 0 },
37556 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37557 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e300 }
37558 },
37559/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37560 {
37561 { 0, 0, 0, 0 },
37562 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37563 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c300 }
37564 },
37565/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
37566 {
37567 { 0, 0, 0, 0 },
37568 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37569 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c30000 }
37570 },
37571/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
37572 {
37573 { 0, 0, 0, 0 },
37574 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37575 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e30000 }
37576 },
37577/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37578 {
37579 { 0, 0, 0, 0 },
37580 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37581 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c30000 }
37582 },
37583/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
37584 {
37585 { 0, 0, 0, 0 },
37586 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
37587 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c30000 }
37588 },
37589/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
37590 {
37591 { 0, 0, 0, 0 },
37592 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
37593 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e30000 }
37594 },
37595/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37596 {
37597 { 0, 0, 0, 0 },
37598 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
37599 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c30000 }
37600 },
37601/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
37602 {
37603 { 0, 0, 0, 0 },
37604 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
37605 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7830000 }
37606 },
37607/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
37608 {
37609 { 0, 0, 0, 0 },
37610 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
37611 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a30000 }
37612 },
37613/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37614 {
37615 { 0, 0, 0, 0 },
37616 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
37617 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87830000 }
37618 },
37619/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
37620 {
37621 { 0, 0, 0, 0 },
37622 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI_S), 0 } },
37623 & ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI, { 0x3100 }
37624 },
37625/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
37626 {
37627 { 0, 0, 0, 0 },
37628 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI_S), 0 } },
37629 & ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI, { 0x3200 }
37630 },
37631/* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
37632 {
37633 { 0, 0, 0, 0 },
37634 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16ANQI_S), 0 } },
37635 & ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI, { 0x330000 }
37636 },
37637/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37638 {
37639 { 0, 0, 0, 0 },
37640 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37641 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990b00 }
37642 },
37643/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
37644 {
37645 { 0, 0, 0, 0 },
37646 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37647 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992b00 }
37648 },
37649/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
37650 {
37651 { 0, 0, 0, 0 },
37652 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37653 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993b00 }
37654 },
37655/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37656 {
37657 { 0, 0, 0, 0 },
37658 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37659 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918b00 }
37660 },
37661/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
37662 {
37663 { 0, 0, 0, 0 },
37664 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37665 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ab00 }
37666 },
37667/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
37668 {
37669 { 0, 0, 0, 0 },
37670 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37671 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bb00 }
37672 },
37673/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37674 {
37675 { 0, 0, 0, 0 },
37676 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37677 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910b00 }
37678 },
37679/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37680 {
37681 { 0, 0, 0, 0 },
37682 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37683 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912b00 }
37684 },
37685/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37686 {
37687 { 0, 0, 0, 0 },
37688 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37689 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913b00 }
37690 },
37691/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37692 {
37693 { 0, 0, 0, 0 },
37694 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37695 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930b0000 }
37696 },
37697/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37698 {
37699 { 0, 0, 0, 0 },
37700 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37701 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932b0000 }
37702 },
37703/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37704 {
37705 { 0, 0, 0, 0 },
37706 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37707 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933b0000 }
37708 },
37709/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37710 {
37711 { 0, 0, 0, 0 },
37712 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37713 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950b0000 }
37714 },
37715/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37716 {
37717 { 0, 0, 0, 0 },
37718 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37719 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952b0000 }
37720 },
37721/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37722 {
37723 { 0, 0, 0, 0 },
37724 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37725 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953b0000 }
37726 },
37727/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37728 {
37729 { 0, 0, 0, 0 },
37730 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37731 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970b0000 }
37732 },
37733/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37734 {
37735 { 0, 0, 0, 0 },
37736 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37737 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972b0000 }
37738 },
37739/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37740 {
37741 { 0, 0, 0, 0 },
37742 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37743 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973b0000 }
37744 },
37745/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37746 {
37747 { 0, 0, 0, 0 },
37748 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37749 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938b0000 }
37750 },
37751/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37752 {
37753 { 0, 0, 0, 0 },
37754 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37755 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ab0000 }
37756 },
37757/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37758 {
37759 { 0, 0, 0, 0 },
37760 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37761 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bb0000 }
37762 },
37763/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37764 {
37765 { 0, 0, 0, 0 },
37766 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37767 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958b0000 }
37768 },
37769/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37770 {
37771 { 0, 0, 0, 0 },
37772 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37773 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ab0000 }
37774 },
37775/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37776 {
37777 { 0, 0, 0, 0 },
37778 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37779 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bb0000 }
37780 },
37781/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37782 {
37783 { 0, 0, 0, 0 },
37784 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37785 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cb0000 }
37786 },
37787/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37788 {
37789 { 0, 0, 0, 0 },
37790 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37791 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93eb0000 }
37792 },
37793/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37794 {
37795 { 0, 0, 0, 0 },
37796 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37797 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fb0000 }
37798 },
37799/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37800 {
37801 { 0, 0, 0, 0 },
37802 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37803 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cb0000 }
37804 },
37805/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37806 {
37807 { 0, 0, 0, 0 },
37808 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37809 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95eb0000 }
37810 },
37811/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37812 {
37813 { 0, 0, 0, 0 },
37814 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37815 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fb0000 }
37816 },
37817/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37818 {
37819 { 0, 0, 0, 0 },
37820 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
37821 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cb0000 }
37822 },
37823/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37824 {
37825 { 0, 0, 0, 0 },
37826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
37827 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97eb0000 }
37828 },
37829/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37830 {
37831 { 0, 0, 0, 0 },
37832 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
37833 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fb0000 }
37834 },
37835/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37836 {
37837 { 0, 0, 0, 0 },
37838 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
37839 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978b0000 }
37840 },
37841/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37842 {
37843 { 0, 0, 0, 0 },
37844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
37845 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ab0000 }
37846 },
37847/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37848 {
37849 { 0, 0, 0, 0 },
37850 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
37851 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bb0000 }
37852 },
37853/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37854 {
37855 { 0, 0, 0, 0 },
37856 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37857 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90b0000 }
37858 },
37859/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
37860 {
37861 { 0, 0, 0, 0 },
37862 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37863 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92b0000 }
37864 },
37865/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
37866 {
37867 { 0, 0, 0, 0 },
37868 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37869 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93b0000 }
37870 },
37871/* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
37872 {
37873 { 0, 0, 0, 0 },
37874 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37875 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93b0000 }
37876 },
37877/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37878 {
37879 { 0, 0, 0, 0 },
37880 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37881 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18b0000 }
37882 },
37883/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
37884 {
37885 { 0, 0, 0, 0 },
37886 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37887 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ab0000 }
37888 },
37889/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
37890 {
37891 { 0, 0, 0, 0 },
37892 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37893 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bb0000 }
37894 },
37895/* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
37896 {
37897 { 0, 0, 0, 0 },
37898 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37899 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bb0000 }
37900 },
37901/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37902 {
37903 { 0, 0, 0, 0 },
37904 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37905 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10b0000 }
37906 },
37907/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37908 {
37909 { 0, 0, 0, 0 },
37910 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37911 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12b0000 }
37912 },
37913/* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37914 {
37915 { 0, 0, 0, 0 },
37916 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37917 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13b0000 }
37918 },
37919/* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37920 {
37921 { 0, 0, 0, 0 },
37922 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37923 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13b0000 }
37924 },
37925/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37926 {
37927 { 0, 0, 0, 0 },
37928 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37929 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30b0000 }
37930 },
37931/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37932 {
37933 { 0, 0, 0, 0 },
37934 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37935 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32b0000 }
37936 },
37937/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37938 {
37939 { 0, 0, 0, 0 },
37940 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37941 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33b0000 }
37942 },
37943/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37944 {
37945 { 0, 0, 0, 0 },
37946 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37947 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33b0000 }
37948 },
37949/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37950 {
37951 { 0, 0, 0, 0 },
37952 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37953 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50b0000 }
37954 },
37955/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37956 {
37957 { 0, 0, 0, 0 },
37958 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37959 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52b0000 }
37960 },
37961/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37962 {
37963 { 0, 0, 0, 0 },
37964 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37965 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53b0000 }
37966 },
37967/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37968 {
37969 { 0, 0, 0, 0 },
37970 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37971 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53b0000 }
37972 },
37973/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37974 {
37975 { 0, 0, 0, 0 },
37976 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37977 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70b0000 }
37978 },
37979/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37980 {
37981 { 0, 0, 0, 0 },
37982 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37983 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72b0000 }
37984 },
37985/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37986 {
37987 { 0, 0, 0, 0 },
37988 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37989 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73b0000 }
37990 },
37991/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37992 {
37993 { 0, 0, 0, 0 },
37994 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37995 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73b0000 }
37996 },
37997/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37998 {
37999 { 0, 0, 0, 0 },
38000 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38001 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38b0000 }
38002 },
38003/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38004 {
38005 { 0, 0, 0, 0 },
38006 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38007 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ab0000 }
38008 },
38009/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
38010 {
38011 { 0, 0, 0, 0 },
38012 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38013 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bb0000 }
38014 },
38015/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38016 {
38017 { 0, 0, 0, 0 },
38018 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38019 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bb0000 }
38020 },
38021/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
38022 {
38023 { 0, 0, 0, 0 },
38024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38025 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58b0000 }
38026 },
38027/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38028 {
38029 { 0, 0, 0, 0 },
38030 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38031 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ab0000 }
38032 },
38033/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
38034 {
38035 { 0, 0, 0, 0 },
38036 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38037 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bb0000 }
38038 },
38039/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38040 {
38041 { 0, 0, 0, 0 },
38042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38043 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bb0000 }
38044 },
38045/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
38046 {
38047 { 0, 0, 0, 0 },
38048 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38049 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cb0000 }
38050 },
38051/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38052 {
38053 { 0, 0, 0, 0 },
38054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38055 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3eb0000 }
38056 },
38057/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
38058 {
38059 { 0, 0, 0, 0 },
38060 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38061 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fb0000 }
38062 },
38063/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38064 {
38065 { 0, 0, 0, 0 },
38066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38067 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fb0000 }
38068 },
38069/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
38070 {
38071 { 0, 0, 0, 0 },
38072 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38073 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cb0000 }
38074 },
38075/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
38076 {
38077 { 0, 0, 0, 0 },
38078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38079 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5eb0000 }
38080 },
38081/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
38082 {
38083 { 0, 0, 0, 0 },
38084 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38085 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fb0000 }
38086 },
38087/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
38088 {
38089 { 0, 0, 0, 0 },
38090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38091 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fb0000 }
38092 },
38093/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
38094 {
38095 { 0, 0, 0, 0 },
38096 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
38097 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cb0000 }
38098 },
38099/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38100 {
38101 { 0, 0, 0, 0 },
38102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38103 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7eb0000 }
38104 },
38105/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
38106 {
38107 { 0, 0, 0, 0 },
38108 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38109 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fb0000 }
38110 },
38111/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
38112 {
38113 { 0, 0, 0, 0 },
38114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
38115 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fb0000 }
38116 },
38117/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
38118 {
38119 { 0, 0, 0, 0 },
38120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
38121 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78b0000 }
38122 },
38123/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
38124 {
38125 { 0, 0, 0, 0 },
38126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38127 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ab0000 }
38128 },
38129/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
38130 {
38131 { 0, 0, 0, 0 },
38132 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38133 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bb0000 }
38134 },
38135/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
38136 {
38137 { 0, 0, 0, 0 },
38138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
38139 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bb0000 }
38140 },
38141/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
38142 {
38143 { 0, 0, 0, 0 },
38144 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38145 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90b0000 }
38146 },
38147/* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
38148 {
38149 { 0, 0, 0, 0 },
38150 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38151 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92b0000 }
38152 },
38153/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
38154 {
38155 { 0, 0, 0, 0 },
38156 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38157 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18b0000 }
38158 },
38159/* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
38160 {
38161 { 0, 0, 0, 0 },
38162 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38163 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ab0000 }
38164 },
38165/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38166 {
38167 { 0, 0, 0, 0 },
38168 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38169 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10b0000 }
38170 },
38171/* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
38172 {
38173 { 0, 0, 0, 0 },
38174 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38175 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12b0000 }
38176 },
38177/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
38178 {
38179 { 0, 0, 0, 0 },
38180 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38181 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30b0000 }
38182 },
38183/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
38184 {
38185 { 0, 0, 0, 0 },
38186 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38187 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32b0000 }
38188 },
38189/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
38190 {
38191 { 0, 0, 0, 0 },
38192 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38193 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50b0000 }
38194 },
38195/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
38196 {
38197 { 0, 0, 0, 0 },
38198 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38199 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52b0000 }
38200 },
38201/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
38202 {
38203 { 0, 0, 0, 0 },
38204 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38205 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70b0000 }
38206 },
38207/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
38208 {
38209 { 0, 0, 0, 0 },
38210 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38211 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72b0000 }
38212 },
38213/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
38214 {
38215 { 0, 0, 0, 0 },
38216 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
38217 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38b0000 }
38218 },
38219/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
38220 {
38221 { 0, 0, 0, 0 },
38222 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
38223 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ab0000 }
38224 },
38225/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
38226 {
38227 { 0, 0, 0, 0 },
38228 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
38229 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58b0000 }
38230 },
38231/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
38232 {
38233 { 0, 0, 0, 0 },
38234 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
38235 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ab0000 }
38236 },
38237/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
38238 {
38239 { 0, 0, 0, 0 },
38240 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
38241 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cb0000 }
38242 },
38243/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
38244 {
38245 { 0, 0, 0, 0 },
38246 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
38247 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3eb0000 }
38248 },
38249/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
38250 {
38251 { 0, 0, 0, 0 },
38252 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
38253 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cb0000 }
38254 },
38255/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
38256 {
38257 { 0, 0, 0, 0 },
38258 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
38259 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5eb0000 }
38260 },
38261/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
38262 {
38263 { 0, 0, 0, 0 },
38264 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
38265 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cb0000 }
38266 },
38267/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
38268 {
38269 { 0, 0, 0, 0 },
38270 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
38271 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7eb0000 }
38272 },
38273/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
38274 {
38275 { 0, 0, 0, 0 },
38276 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
38277 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78b0000 }
38278 },
38279/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
38280 {
38281 { 0, 0, 0, 0 },
38282 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
38283 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ab0000 }
38284 },
38285/* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
38286 {
38287 { 0, 0, 0, 0 },
38288 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38289 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90b }
38290 },
38291/* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
38292 {
38293 { 0, 0, 0, 0 },
38294 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38295 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892b }
38296 },
38297/* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
38298 {
38299 { 0, 0, 0, 0 },
38300 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38301 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890b }
38302 },
38303/* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
38304 {
38305 { 0, 0, 0, 0 },
38306 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38307 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18b }
38308 },
38309/* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
38310 {
38311 { 0, 0, 0, 0 },
38312 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38313 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ab }
38314 },
38315/* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
38316 {
38317 { 0, 0, 0, 0 },
38318 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38319 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818b }
38320 },
38321/* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
38322 {
38323 { 0, 0, 0, 0 },
38324 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38325 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10b }
38326 },
38327/* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
38328 {
38329 { 0, 0, 0, 0 },
38330 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38331 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812b }
38332 },
38333/* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38334 {
38335 { 0, 0, 0, 0 },
38336 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38337 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810b }
38338 },
38339/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38340 {
38341 { 0, 0, 0, 0 },
38342 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38343 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30b00 }
38344 },
38345/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38346 {
38347 { 0, 0, 0, 0 },
38348 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38349 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832b00 }
38350 },
38351/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
38352 {
38353 { 0, 0, 0, 0 },
38354 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38355 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830b00 }
38356 },
38357/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38358 {
38359 { 0, 0, 0, 0 },
38360 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38361 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50b0000 }
38362 },
38363/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38364 {
38365 { 0, 0, 0, 0 },
38366 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38367 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852b0000 }
38368 },
38369/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
38370 {
38371 { 0, 0, 0, 0 },
38372 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38373 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850b0000 }
38374 },
38375/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38376 {
38377 { 0, 0, 0, 0 },
38378 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38379 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70b0000 }
38380 },
38381/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38382 {
38383 { 0, 0, 0, 0 },
38384 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38385 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872b0000 }
38386 },
38387/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38388 {
38389 { 0, 0, 0, 0 },
38390 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38391 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870b0000 }
38392 },
38393/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
38394 {
38395 { 0, 0, 0, 0 },
38396 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38397 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38b00 }
38398 },
38399/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
38400 {
38401 { 0, 0, 0, 0 },
38402 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38403 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ab00 }
38404 },
38405/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38406 {
38407 { 0, 0, 0, 0 },
38408 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38409 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838b00 }
38410 },
38411/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
38412 {
38413 { 0, 0, 0, 0 },
38414 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38415 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58b0000 }
38416 },
38417/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
38418 {
38419 { 0, 0, 0, 0 },
38420 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38421 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ab0000 }
38422 },
38423/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38424 {
38425 { 0, 0, 0, 0 },
38426 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38427 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858b0000 }
38428 },
38429/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
38430 {
38431 { 0, 0, 0, 0 },
38432 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38433 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cb00 }
38434 },
38435/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
38436 {
38437 { 0, 0, 0, 0 },
38438 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38439 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83eb00 }
38440 },
38441/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38442 {
38443 { 0, 0, 0, 0 },
38444 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38445 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cb00 }
38446 },
38447/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
38448 {
38449 { 0, 0, 0, 0 },
38450 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38451 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cb0000 }
38452 },
38453/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
38454 {
38455 { 0, 0, 0, 0 },
38456 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38457 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85eb0000 }
38458 },
38459/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38460 {
38461 { 0, 0, 0, 0 },
38462 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38463 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cb0000 }
38464 },
38465/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
38466 {
38467 { 0, 0, 0, 0 },
38468 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
38469 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cb0000 }
38470 },
38471/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
38472 {
38473 { 0, 0, 0, 0 },
38474 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
38475 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87eb0000 }
38476 },
38477/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38478 {
38479 { 0, 0, 0, 0 },
38480 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
38481 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cb0000 }
38482 },
38483/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
38484 {
38485 { 0, 0, 0, 0 },
38486 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
38487 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78b0000 }
38488 },
38489/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
38490 {
38491 { 0, 0, 0, 0 },
38492 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
38493 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ab0000 }
38494 },
38495/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38496 {
38497 { 0, 0, 0, 0 },
38498 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
38499 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878b0000 }
38500 },
38501/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38502 {
38503 { 0, 0, 0, 0 },
38504 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38505 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980b00 }
38506 },
38507/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
38508 {
38509 { 0, 0, 0, 0 },
38510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38511 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982b00 }
38512 },
38513/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
38514 {
38515 { 0, 0, 0, 0 },
38516 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38517 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983b00 }
38518 },
38519/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38520 {
38521 { 0, 0, 0, 0 },
38522 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38523 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908b00 }
38524 },
38525/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
38526 {
38527 { 0, 0, 0, 0 },
38528 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38529 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ab00 }
38530 },
38531/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
38532 {
38533 { 0, 0, 0, 0 },
38534 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38535 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bb00 }
38536 },
38537/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38538 {
38539 { 0, 0, 0, 0 },
38540 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38541 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900b00 }
38542 },
38543/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
38544 {
38545 { 0, 0, 0, 0 },
38546 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38547 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902b00 }
38548 },
38549/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
38550 {
38551 { 0, 0, 0, 0 },
38552 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38553 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903b00 }
38554 },
38555/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38556 {
38557 { 0, 0, 0, 0 },
38558 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38559 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920b0000 }
38560 },
38561/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38562 {
38563 { 0, 0, 0, 0 },
38564 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38565 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922b0000 }
38566 },
38567/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38568 {
38569 { 0, 0, 0, 0 },
38570 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38571 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923b0000 }
38572 },
38573/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38574 {
38575 { 0, 0, 0, 0 },
38576 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38577 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940b0000 }
38578 },
38579/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38580 {
38581 { 0, 0, 0, 0 },
38582 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38583 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942b0000 }
38584 },
38585/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38586 {
38587 { 0, 0, 0, 0 },
38588 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38589 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943b0000 }
38590 },
38591/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38592 {
38593 { 0, 0, 0, 0 },
38594 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38595 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960b0000 }
38596 },
38597/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38598 {
38599 { 0, 0, 0, 0 },
38600 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38601 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962b0000 }
38602 },
38603/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38604 {
38605 { 0, 0, 0, 0 },
38606 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38607 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963b0000 }
38608 },
38609/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
38610 {
38611 { 0, 0, 0, 0 },
38612 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38613 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928b0000 }
38614 },
38615/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38616 {
38617 { 0, 0, 0, 0 },
38618 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38619 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ab0000 }
38620 },
38621/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38622 {
38623 { 0, 0, 0, 0 },
38624 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38625 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bb0000 }
38626 },
38627/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
38628 {
38629 { 0, 0, 0, 0 },
38630 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38631 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948b0000 }
38632 },
38633/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38634 {
38635 { 0, 0, 0, 0 },
38636 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38637 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ab0000 }
38638 },
38639/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38640 {
38641 { 0, 0, 0, 0 },
38642 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38643 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bb0000 }
38644 },
38645/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
38646 {
38647 { 0, 0, 0, 0 },
38648 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38649 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cb0000 }
38650 },
38651/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38652 {
38653 { 0, 0, 0, 0 },
38654 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38655 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92eb0000 }
38656 },
38657/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38658 {
38659 { 0, 0, 0, 0 },
38660 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38661 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fb0000 }
38662 },
38663/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
38664 {
38665 { 0, 0, 0, 0 },
38666 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38667 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cb0000 }
38668 },
38669/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
38670 {
38671 { 0, 0, 0, 0 },
38672 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38673 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94eb0000 }
38674 },
38675/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
38676 {
38677 { 0, 0, 0, 0 },
38678 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38679 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fb0000 }
38680 },
38681/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
38682 {
38683 { 0, 0, 0, 0 },
38684 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
38685 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cb0000 }
38686 },
38687/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38688 {
38689 { 0, 0, 0, 0 },
38690 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
38691 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96eb0000 }
38692 },
38693/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38694 {
38695 { 0, 0, 0, 0 },
38696 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
38697 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fb0000 }
38698 },
38699/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
38700 {
38701 { 0, 0, 0, 0 },
38702 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
38703 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968b0000 }
38704 },
38705/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
38706 {
38707 { 0, 0, 0, 0 },
38708 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
38709 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ab0000 }
38710 },
38711/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
38712 {
38713 { 0, 0, 0, 0 },
38714 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
38715 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bb0000 }
38716 },
38717/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38718 {
38719 { 0, 0, 0, 0 },
38720 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38721 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80b0000 }
38722 },
38723/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
38724 {
38725 { 0, 0, 0, 0 },
38726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38727 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82b0000 }
38728 },
38729/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
38730 {
38731 { 0, 0, 0, 0 },
38732 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38733 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83b0000 }
38734 },
38735/* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
38736 {
38737 { 0, 0, 0, 0 },
38738 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38739 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83b0000 }
38740 },
38741/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38742 {
38743 { 0, 0, 0, 0 },
38744 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38745 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08b0000 }
38746 },
38747/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
38748 {
38749 { 0, 0, 0, 0 },
38750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38751 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ab0000 }
38752 },
38753/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
38754 {
38755 { 0, 0, 0, 0 },
38756 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38757 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bb0000 }
38758 },
38759/* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
38760 {
38761 { 0, 0, 0, 0 },
38762 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38763 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bb0000 }
38764 },
38765/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38766 {
38767 { 0, 0, 0, 0 },
38768 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38769 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00b0000 }
38770 },
38771/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
38772 {
38773 { 0, 0, 0, 0 },
38774 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38775 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02b0000 }
38776 },
38777/* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
38778 {
38779 { 0, 0, 0, 0 },
38780 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38781 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03b0000 }
38782 },
38783/* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
38784 {
38785 { 0, 0, 0, 0 },
38786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38787 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03b0000 }
38788 },
38789/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38790 {
38791 { 0, 0, 0, 0 },
38792 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38793 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20b0000 }
38794 },
38795/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38796 {
38797 { 0, 0, 0, 0 },
38798 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38799 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22b0000 }
38800 },
38801/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38802 {
38803 { 0, 0, 0, 0 },
38804 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38805 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23b0000 }
38806 },
38807/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
38808 {
38809 { 0, 0, 0, 0 },
38810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38811 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23b0000 }
38812 },
38813/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38814 {
38815 { 0, 0, 0, 0 },
38816 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38817 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40b0000 }
38818 },
38819/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38820 {
38821 { 0, 0, 0, 0 },
38822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38823 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42b0000 }
38824 },
38825/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38826 {
38827 { 0, 0, 0, 0 },
38828 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38829 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43b0000 }
38830 },
38831/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
38832 {
38833 { 0, 0, 0, 0 },
38834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38835 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43b0000 }
38836 },
38837/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38838 {
38839 { 0, 0, 0, 0 },
38840 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38841 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60b0000 }
38842 },
38843/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38844 {
38845 { 0, 0, 0, 0 },
38846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38847 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62b0000 }
38848 },
38849/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38850 {
38851 { 0, 0, 0, 0 },
38852 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38853 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63b0000 }
38854 },
38855/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
38856 {
38857 { 0, 0, 0, 0 },
38858 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38859 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63b0000 }
38860 },
38861/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
38862 {
38863 { 0, 0, 0, 0 },
38864 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38865 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28b0000 }
38866 },
38867/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38868 {
38869 { 0, 0, 0, 0 },
38870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38871 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ab0000 }
38872 },
38873/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
38874 {
38875 { 0, 0, 0, 0 },
38876 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38877 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bb0000 }
38878 },
38879/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38880 {
38881 { 0, 0, 0, 0 },
38882 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38883 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bb0000 }
38884 },
38885/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
38886 {
38887 { 0, 0, 0, 0 },
38888 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38889 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48b0000 }
38890 },
38891/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38892 {
38893 { 0, 0, 0, 0 },
38894 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38895 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ab0000 }
38896 },
38897/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
38898 {
38899 { 0, 0, 0, 0 },
38900 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38901 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bb0000 }
38902 },
38903/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38904 {
38905 { 0, 0, 0, 0 },
38906 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38907 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bb0000 }
38908 },
38909/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
38910 {
38911 { 0, 0, 0, 0 },
38912 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38913 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cb0000 }
38914 },
38915/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38916 {
38917 { 0, 0, 0, 0 },
38918 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38919 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2eb0000 }
38920 },
38921/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
38922 {
38923 { 0, 0, 0, 0 },
38924 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38925 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fb0000 }
38926 },
38927/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38928 {
38929 { 0, 0, 0, 0 },
38930 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38931 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fb0000 }
38932 },
38933/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
38934 {
38935 { 0, 0, 0, 0 },
38936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38937 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cb0000 }
38938 },
38939/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
38940 {
38941 { 0, 0, 0, 0 },
38942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38943 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4eb0000 }
38944 },
38945/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
38946 {
38947 { 0, 0, 0, 0 },
38948 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38949 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fb0000 }
38950 },
38951/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
38952 {
38953 { 0, 0, 0, 0 },
38954 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38955 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fb0000 }
38956 },
38957/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
38958 {
38959 { 0, 0, 0, 0 },
38960 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
38961 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cb0000 }
38962 },
38963/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38964 {
38965 { 0, 0, 0, 0 },
38966 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38967 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6eb0000 }
38968 },
38969/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
38970 {
38971 { 0, 0, 0, 0 },
38972 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38973 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fb0000 }
38974 },
38975/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38976 {
38977 { 0, 0, 0, 0 },
38978 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
38979 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fb0000 }
38980 },
38981/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
38982 {
38983 { 0, 0, 0, 0 },
38984 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
38985 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68b0000 }
38986 },
38987/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
38988 {
38989 { 0, 0, 0, 0 },
38990 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38991 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ab0000 }
38992 },
38993/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
38994 {
38995 { 0, 0, 0, 0 },
38996 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38997 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bb0000 }
38998 },
38999/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
39000 {
39001 { 0, 0, 0, 0 },
39002 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
39003 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bb0000 }
39004 },
39005/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
39006 {
39007 { 0, 0, 0, 0 },
39008 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39009 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80b0000 }
39010 },
39011/* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
39012 {
39013 { 0, 0, 0, 0 },
39014 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39015 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82b0000 }
39016 },
39017/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
39018 {
39019 { 0, 0, 0, 0 },
39020 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39021 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08b0000 }
39022 },
39023/* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
39024 {
39025 { 0, 0, 0, 0 },
39026 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39027 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ab0000 }
39028 },
39029/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
39030 {
39031 { 0, 0, 0, 0 },
39032 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39033 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00b0000 }
39034 },
39035/* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
39036 {
39037 { 0, 0, 0, 0 },
39038 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39039 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02b0000 }
39040 },
39041/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
39042 {
39043 { 0, 0, 0, 0 },
39044 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39045 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20b0000 }
39046 },
39047/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
39048 {
39049 { 0, 0, 0, 0 },
39050 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39051 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22b0000 }
39052 },
39053/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
39054 {
39055 { 0, 0, 0, 0 },
39056 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39057 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40b0000 }
39058 },
39059/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
39060 {
39061 { 0, 0, 0, 0 },
39062 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39063 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42b0000 }
39064 },
39065/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
39066 {
39067 { 0, 0, 0, 0 },
39068 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39069 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60b0000 }
39070 },
39071/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
39072 {
39073 { 0, 0, 0, 0 },
39074 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39075 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62b0000 }
39076 },
39077/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
39078 {
39079 { 0, 0, 0, 0 },
39080 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
39081 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28b0000 }
39082 },
39083/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
39084 {
39085 { 0, 0, 0, 0 },
39086 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
39087 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ab0000 }
39088 },
39089/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
39090 {
39091 { 0, 0, 0, 0 },
39092 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
39093 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48b0000 }
39094 },
39095/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
39096 {
39097 { 0, 0, 0, 0 },
39098 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
39099 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ab0000 }
39100 },
39101/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
39102 {
39103 { 0, 0, 0, 0 },
39104 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
39105 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cb0000 }
39106 },
39107/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
39108 {
39109 { 0, 0, 0, 0 },
39110 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
39111 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2eb0000 }
39112 },
39113/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
39114 {
39115 { 0, 0, 0, 0 },
39116 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
39117 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cb0000 }
39118 },
39119/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
39120 {
39121 { 0, 0, 0, 0 },
39122 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
39123 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4eb0000 }
39124 },
39125/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
39126 {
39127 { 0, 0, 0, 0 },
39128 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
39129 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cb0000 }
39130 },
39131/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
39132 {
39133 { 0, 0, 0, 0 },
39134 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
39135 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6eb0000 }
39136 },
39137/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
39138 {
39139 { 0, 0, 0, 0 },
39140 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
39141 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68b0000 }
39142 },
39143/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
39144 {
39145 { 0, 0, 0, 0 },
39146 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
39147 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ab0000 }
39148 },
39149/* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
39150 {
39151 { 0, 0, 0, 0 },
39152 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39153 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80b }
39154 },
39155/* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
39156 {
39157 { 0, 0, 0, 0 },
39158 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39159 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882b }
39160 },
39161/* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
39162 {
39163 { 0, 0, 0, 0 },
39164 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39165 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880b }
39166 },
39167/* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
39168 {
39169 { 0, 0, 0, 0 },
39170 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39171 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08b }
39172 },
39173/* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
39174 {
39175 { 0, 0, 0, 0 },
39176 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39177 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ab }
39178 },
39179/* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
39180 {
39181 { 0, 0, 0, 0 },
39182 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39183 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808b }
39184 },
39185/* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
39186 {
39187 { 0, 0, 0, 0 },
39188 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39189 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00b }
39190 },
39191/* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
39192 {
39193 { 0, 0, 0, 0 },
39194 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39195 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802b }
39196 },
39197/* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
39198 {
39199 { 0, 0, 0, 0 },
39200 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39201 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800b }
39202 },
39203/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
39204 {
39205 { 0, 0, 0, 0 },
39206 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39207 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20b00 }
39208 },
39209/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
39210 {
39211 { 0, 0, 0, 0 },
39212 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39213 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822b00 }
39214 },
39215/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
39216 {
39217 { 0, 0, 0, 0 },
39218 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39219 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820b00 }
39220 },
39221/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
39222 {
39223 { 0, 0, 0, 0 },
39224 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39225 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40b0000 }
39226 },
39227/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
39228 {
39229 { 0, 0, 0, 0 },
39230 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39231 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842b0000 }
39232 },
39233/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
39234 {
39235 { 0, 0, 0, 0 },
39236 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39237 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840b0000 }
39238 },
39239/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
39240 {
39241 { 0, 0, 0, 0 },
39242 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39243 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60b0000 }
39244 },
39245/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
39246 {
39247 { 0, 0, 0, 0 },
39248 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39249 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862b0000 }
39250 },
39251/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
39252 {
39253 { 0, 0, 0, 0 },
39254 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39255 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860b0000 }
39256 },
39257/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
39258 {
39259 { 0, 0, 0, 0 },
39260 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39261 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28b00 }
39262 },
39263/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
39264 {
39265 { 0, 0, 0, 0 },
39266 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39267 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ab00 }
39268 },
39269/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
39270 {
39271 { 0, 0, 0, 0 },
39272 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39273 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828b00 }
39274 },
39275/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
39276 {
39277 { 0, 0, 0, 0 },
39278 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39279 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48b0000 }
39280 },
39281/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
39282 {
39283 { 0, 0, 0, 0 },
39284 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39285 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ab0000 }
39286 },
39287/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
39288 {
39289 { 0, 0, 0, 0 },
39290 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39291 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848b0000 }
39292 },
39293/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
39294 {
39295 { 0, 0, 0, 0 },
39296 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39297 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cb00 }
39298 },
39299/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
39300 {
39301 { 0, 0, 0, 0 },
39302 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39303 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82eb00 }
39304 },
39305/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
39306 {
39307 { 0, 0, 0, 0 },
39308 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39309 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cb00 }
39310 },
39311/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
39312 {
39313 { 0, 0, 0, 0 },
39314 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
39315 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cb0000 }
39316 },
39317/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
39318 {
39319 { 0, 0, 0, 0 },
39320 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
39321 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84eb0000 }
39322 },
39323/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
39324 {
39325 { 0, 0, 0, 0 },
39326 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
39327 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cb0000 }
39328 },
39329/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
39330 {
39331 { 0, 0, 0, 0 },
39332 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
39333 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cb0000 }
39334 },
39335/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
39336 {
39337 { 0, 0, 0, 0 },
39338 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
39339 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86eb0000 }
39340 },
39341/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
39342 {
39343 { 0, 0, 0, 0 },
39344 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
39345 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cb0000 }
39346 },
39347/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
39348 {
39349 { 0, 0, 0, 0 },
39350 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
39351 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68b0000 }
39352 },
39353/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
39354 {
39355 { 0, 0, 0, 0 },
39356 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
39357 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ab0000 }
39358 },
39359/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
39360 {
39361 { 0, 0, 0, 0 },
39362 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
39363 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868b0000 }
39364 },
39365/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
39366 {
39367 { 0, 0, 0, 0 },
39368 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39369 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x738000 }
39370 },
39371/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
39372 {
39373 { 0, 0, 0, 0 },
39374 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
39375 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x73a000 }
39376 },
39377/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
39378 {
39379 { 0, 0, 0, 0 },
39380 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
39381 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x73b000 }
39382 },
39383/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
39384 {
39385 { 0, 0, 0, 0 },
39386 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39387 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x738400 }
39388 },
39389/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
39390 {
39391 { 0, 0, 0, 0 },
39392 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
39393 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x73a400 }
39394 },
39395/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
39396 {
39397 { 0, 0, 0, 0 },
39398 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
39399 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x73b400 }
39400 },
39401/* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
39402 {
39403 { 0, 0, 0, 0 },
39404 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39405 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x738600 }
39406 },
39407/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
39408 {
39409 { 0, 0, 0, 0 },
39410 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39411 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x73a600 }
39412 },
39413/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
39414 {
39415 { 0, 0, 0, 0 },
39416 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39417 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x73b600 }
39418 },
39419/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
39420 {
39421 { 0, 0, 0, 0 },
39422 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39423 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x73880000 }
39424 },
39425/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
39426 {
39427 { 0, 0, 0, 0 },
39428 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39429 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x73a80000 }
39430 },
39431/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
39432 {
39433 { 0, 0, 0, 0 },
39434 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39435 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x73b80000 }
39436 },
39437/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
39438 {
39439 { 0, 0, 0, 0 },
39440 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39441 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x738c0000 }
39442 },
39443/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
39444 {
39445 { 0, 0, 0, 0 },
39446 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39447 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x73ac0000 }
39448 },
39449/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
39450 {
39451 { 0, 0, 0, 0 },
39452 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39453 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x73bc0000 }
39454 },
39455/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
39456 {
39457 { 0, 0, 0, 0 },
39458 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39459 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x738a0000 }
39460 },
39461/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
39462 {
39463 { 0, 0, 0, 0 },
39464 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39465 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73aa0000 }
39466 },
39467/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
39468 {
39469 { 0, 0, 0, 0 },
39470 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39471 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73ba0000 }
39472 },
39473/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
39474 {
39475 { 0, 0, 0, 0 },
39476 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39477 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x738e0000 }
39478 },
39479/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
39480 {
39481 { 0, 0, 0, 0 },
39482 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39483 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73ae0000 }
39484 },
39485/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
39486 {
39487 { 0, 0, 0, 0 },
39488 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39489 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73be0000 }
39490 },
39491/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
39492 {
39493 { 0, 0, 0, 0 },
39494 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39495 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x738b0000 }
39496 },
39497/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
39498 {
39499 { 0, 0, 0, 0 },
39500 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39501 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73ab0000 }
39502 },
39503/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
39504 {
39505 { 0, 0, 0, 0 },
39506 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39507 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73bb0000 }
39508 },
39509/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
39510 {
39511 { 0, 0, 0, 0 },
39512 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
39513 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x738f0000 }
39514 },
39515/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
39516 {
39517 { 0, 0, 0, 0 },
39518 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39519 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x73af0000 }
39520 },
39521/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
39522 {
39523 { 0, 0, 0, 0 },
39524 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39525 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x73bf0000 }
39526 },
39527/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
39528 {
39529 { 0, 0, 0, 0 },
39530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39531 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x73c00000 }
39532 },
39533/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
39534 {
39535 { 0, 0, 0, 0 },
39536 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
39537 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x73e00000 }
39538 },
39539/* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
39540 {
39541 { 0, 0, 0, 0 },
39542 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
39543 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x73f00000 }
39544 },
39545/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
39546 {
39547 { 0, 0, 0, 0 },
39548 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39549 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x73c40000 }
39550 },
39551/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
39552 {
39553 { 0, 0, 0, 0 },
39554 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
39555 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x73e40000 }
39556 },
39557/* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
39558 {
39559 { 0, 0, 0, 0 },
39560 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
39561 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x73f40000 }
39562 },
39563/* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
39564 {
39565 { 0, 0, 0, 0 },
39566 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39567 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x73c60000 }
39568 },
39569/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
39570 {
39571 { 0, 0, 0, 0 },
39572 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39573 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x73e60000 }
39574 },
39575/* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
39576 {
39577 { 0, 0, 0, 0 },
39578 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
39579 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x73f60000 }
39580 },
39581/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
39582 {
39583 { 0, 0, 0, 0 },
39584 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39585 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x73c80000 }
39586 },
39587/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
39588 {
39589 { 0, 0, 0, 0 },
39590 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39591 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x73e80000 }
39592 },
39593/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
39594 {
39595 { 0, 0, 0, 0 },
39596 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39597 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x73f80000 }
39598 },
39599/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
39600 {
39601 { 0, 0, 0, 0 },
39602 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39603 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x73cc0000 }
39604 },
39605/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
39606 {
39607 { 0, 0, 0, 0 },
39608 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39609 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x73ec0000 }
39610 },
39611/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
39612 {
39613 { 0, 0, 0, 0 },
39614 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39615 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x73fc0000 }
39616 },
39617/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
39618 {
39619 { 0, 0, 0, 0 },
39620 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39621 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ca0000 }
39622 },
39623/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
39624 {
39625 { 0, 0, 0, 0 },
39626 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39627 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ea0000 }
39628 },
39629/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
39630 {
39631 { 0, 0, 0, 0 },
39632 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39633 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x73fa0000 }
39634 },
39635/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
39636 {
39637 { 0, 0, 0, 0 },
39638 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39639 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ce0000 }
39640 },
39641/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
39642 {
39643 { 0, 0, 0, 0 },
39644 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39645 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ee0000 }
39646 },
39647/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
39648 {
39649 { 0, 0, 0, 0 },
39650 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39651 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x73fe0000 }
39652 },
39653/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
39654 {
39655 { 0, 0, 0, 0 },
39656 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39657 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x73cb0000 }
39658 },
39659/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
39660 {
39661 { 0, 0, 0, 0 },
39662 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39663 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x73eb0000 }
39664 },
39665/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
39666 {
39667 { 0, 0, 0, 0 },
39668 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39669 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x73fb0000 }
39670 },
39671/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
39672 {
39673 { 0, 0, 0, 0 },
39674 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
39675 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x73cf0000 }
39676 },
39677/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
39678 {
39679 { 0, 0, 0, 0 },
39680 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
39681 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x73ef0000 }
39682 },
39683/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
39684 {
39685 { 0, 0, 0, 0 },
39686 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
39687 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x73ff0000 }
39688 },
39689/* mov.w${G} $Src16RnHI,$Dst16RnHI */
39690 {
39691 { 0, 0, 0, 0 },
39692 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
39693 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7300 }
39694 },
39695/* mov.w${G} $Src16AnHI,$Dst16RnHI */
39696 {
39697 { 0, 0, 0, 0 },
39698 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
39699 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7340 }
39700 },
39701/* mov.w${G} [$Src16An],$Dst16RnHI */
39702 {
39703 { 0, 0, 0, 0 },
39704 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39705 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7360 }
39706 },
39707/* mov.w${G} $Src16RnHI,$Dst16AnHI */
39708 {
39709 { 0, 0, 0, 0 },
39710 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
39711 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7304 }
39712 },
39713/* mov.w${G} $Src16AnHI,$Dst16AnHI */
39714 {
39715 { 0, 0, 0, 0 },
39716 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
39717 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7344 }
39718 },
39719/* mov.w${G} [$Src16An],$Dst16AnHI */
39720 {
39721 { 0, 0, 0, 0 },
39722 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39723 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7364 }
39724 },
39725/* mov.w${G} $Src16RnHI,[$Dst16An] */
39726 {
39727 { 0, 0, 0, 0 },
39728 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
39729 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7306 }
39730 },
39731/* mov.w${G} $Src16AnHI,[$Dst16An] */
39732 {
39733 { 0, 0, 0, 0 },
39734 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
39735 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7346 }
39736 },
39737/* mov.w${G} [$Src16An],[$Dst16An] */
39738 {
39739 { 0, 0, 0, 0 },
39740 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39741 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7366 }
39742 },
39743/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
39744 {
39745 { 0, 0, 0, 0 },
39746 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39747 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x730800 }
39748 },
39749/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
39750 {
39751 { 0, 0, 0, 0 },
39752 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39753 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x734800 }
39754 },
39755/* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
39756 {
39757 { 0, 0, 0, 0 },
39758 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39759 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x736800 }
39760 },
39761/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
39762 {
39763 { 0, 0, 0, 0 },
39764 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39765 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x730c0000 }
39766 },
39767/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
39768 {
39769 { 0, 0, 0, 0 },
39770 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39771 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x734c0000 }
39772 },
39773/* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
39774 {
39775 { 0, 0, 0, 0 },
39776 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39777 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x736c0000 }
39778 },
39779/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
39780 {
39781 { 0, 0, 0, 0 },
39782 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39783 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x730a00 }
39784 },
39785/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
39786 {
39787 { 0, 0, 0, 0 },
39788 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39789 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x734a00 }
39790 },
39791/* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
39792 {
39793 { 0, 0, 0, 0 },
39794 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39795 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x736a00 }
39796 },
39797/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
39798 {
39799 { 0, 0, 0, 0 },
39800 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39801 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x730e0000 }
39802 },
39803/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
39804 {
39805 { 0, 0, 0, 0 },
39806 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39807 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x734e0000 }
39808 },
39809/* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
39810 {
39811 { 0, 0, 0, 0 },
39812 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39813 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x736e0000 }
39814 },
39815/* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
39816 {
39817 { 0, 0, 0, 0 },
39818 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39819 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x730b00 }
39820 },
39821/* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
39822 {
39823 { 0, 0, 0, 0 },
39824 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39825 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x734b00 }
39826 },
39827/* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
39828 {
39829 { 0, 0, 0, 0 },
39830 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39831 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x736b00 }
39832 },
39833/* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
39834 {
39835 { 0, 0, 0, 0 },
39836 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
39837 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x730f0000 }
39838 },
39839/* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
39840 {
39841 { 0, 0, 0, 0 },
39842 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
39843 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x734f0000 }
39844 },
39845/* mov.w${G} [$Src16An],${Dsp-16-u16} */
39846 {
39847 { 0, 0, 0, 0 },
39848 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
39849 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x736f0000 }
39850 },
39851/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
39852 {
39853 { 0, 0, 0, 0 },
39854 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
39855 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x728000 }
39856 },
39857/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
39858 {
39859 { 0, 0, 0, 0 },
39860 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
39861 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x72a000 }
39862 },
39863/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
39864 {
39865 { 0, 0, 0, 0 },
39866 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
39867 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x72b000 }
39868 },
39869/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
39870 {
39871 { 0, 0, 0, 0 },
39872 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
39873 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x728400 }
39874 },
39875/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
39876 {
39877 { 0, 0, 0, 0 },
39878 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
39879 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x72a400 }
39880 },
39881/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
39882 {
39883 { 0, 0, 0, 0 },
39884 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
39885 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x72b400 }
39886 },
39887/* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
39888 {
39889 { 0, 0, 0, 0 },
39890 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39891 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x728600 }
39892 },
39893/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
39894 {
39895 { 0, 0, 0, 0 },
39896 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39897 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x72a600 }
39898 },
39899/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
39900 {
39901 { 0, 0, 0, 0 },
39902 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39903 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x72b600 }
39904 },
39905/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
39906 {
39907 { 0, 0, 0, 0 },
39908 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39909 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x72880000 }
39910 },
39911/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
39912 {
39913 { 0, 0, 0, 0 },
39914 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39915 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x72a80000 }
39916 },
39917/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
39918 {
39919 { 0, 0, 0, 0 },
39920 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39921 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x72b80000 }
39922 },
39923/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
39924 {
39925 { 0, 0, 0, 0 },
39926 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39927 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x728c0000 }
39928 },
39929/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
39930 {
39931 { 0, 0, 0, 0 },
39932 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39933 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x72ac0000 }
39934 },
39935/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
39936 {
39937 { 0, 0, 0, 0 },
39938 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39939 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x72bc0000 }
39940 },
39941/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
39942 {
39943 { 0, 0, 0, 0 },
39944 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39945 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x728a0000 }
39946 },
39947/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
39948 {
39949 { 0, 0, 0, 0 },
39950 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39951 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72aa0000 }
39952 },
39953/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
39954 {
39955 { 0, 0, 0, 0 },
39956 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39957 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72ba0000 }
39958 },
39959/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
39960 {
39961 { 0, 0, 0, 0 },
39962 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39963 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x728e0000 }
39964 },
39965/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
39966 {
39967 { 0, 0, 0, 0 },
39968 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39969 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72ae0000 }
39970 },
39971/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
39972 {
39973 { 0, 0, 0, 0 },
39974 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39975 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72be0000 }
39976 },
39977/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
39978 {
39979 { 0, 0, 0, 0 },
39980 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39981 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x728b0000 }
39982 },
39983/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
39984 {
39985 { 0, 0, 0, 0 },
39986 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39987 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72ab0000 }
39988 },
39989/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
39990 {
39991 { 0, 0, 0, 0 },
39992 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39993 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72bb0000 }
39994 },
39995/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
39996 {
39997 { 0, 0, 0, 0 },
39998 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
39999 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x728f0000 }
40000 },
40001/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
40002 {
40003 { 0, 0, 0, 0 },
40004 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
40005 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x72af0000 }
40006 },
40007/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
40008 {
40009 { 0, 0, 0, 0 },
40010 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
40011 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x72bf0000 }
40012 },
40013/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
40014 {
40015 { 0, 0, 0, 0 },
40016 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
40017 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x72c00000 }
40018 },
40019/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
40020 {
40021 { 0, 0, 0, 0 },
40022 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
40023 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x72e00000 }
40024 },
40025/* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
40026 {
40027 { 0, 0, 0, 0 },
40028 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
40029 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x72f00000 }
40030 },
40031/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
40032 {
40033 { 0, 0, 0, 0 },
40034 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
40035 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x72c40000 }
40036 },
40037/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
40038 {
40039 { 0, 0, 0, 0 },
40040 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
40041 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x72e40000 }
40042 },
40043/* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
40044 {
40045 { 0, 0, 0, 0 },
40046 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
40047 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x72f40000 }
40048 },
40049/* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
40050 {
40051 { 0, 0, 0, 0 },
40052 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
40053 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x72c60000 }
40054 },
40055/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
40056 {
40057 { 0, 0, 0, 0 },
40058 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
40059 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x72e60000 }
40060 },
40061/* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
40062 {
40063 { 0, 0, 0, 0 },
40064 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
40065 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x72f60000 }
40066 },
40067/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
40068 {
40069 { 0, 0, 0, 0 },
40070 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
40071 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x72c80000 }
40072 },
40073/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
40074 {
40075 { 0, 0, 0, 0 },
40076 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
40077 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x72e80000 }
40078 },
40079/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
40080 {
40081 { 0, 0, 0, 0 },
40082 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
40083 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x72f80000 }
40084 },
40085/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
40086 {
40087 { 0, 0, 0, 0 },
40088 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
40089 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x72cc0000 }
40090 },
40091/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
40092 {
40093 { 0, 0, 0, 0 },
40094 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
40095 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x72ec0000 }
40096 },
40097/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
40098 {
40099 { 0, 0, 0, 0 },
40100 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
40101 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x72fc0000 }
40102 },
40103/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
40104 {
40105 { 0, 0, 0, 0 },
40106 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40107 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ca0000 }
40108 },
40109/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
40110 {
40111 { 0, 0, 0, 0 },
40112 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40113 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ea0000 }
40114 },
40115/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
40116 {
40117 { 0, 0, 0, 0 },
40118 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40119 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x72fa0000 }
40120 },
40121/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
40122 {
40123 { 0, 0, 0, 0 },
40124 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40125 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ce0000 }
40126 },
40127/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
40128 {
40129 { 0, 0, 0, 0 },
40130 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40131 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ee0000 }
40132 },
40133/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
40134 {
40135 { 0, 0, 0, 0 },
40136 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40137 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x72fe0000 }
40138 },
40139/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
40140 {
40141 { 0, 0, 0, 0 },
40142 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40143 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x72cb0000 }
40144 },
40145/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
40146 {
40147 { 0, 0, 0, 0 },
40148 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40149 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x72eb0000 }
40150 },
40151/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
40152 {
40153 { 0, 0, 0, 0 },
40154 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40155 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x72fb0000 }
40156 },
40157/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
40158 {
40159 { 0, 0, 0, 0 },
40160 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
40161 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x72cf0000 }
40162 },
40163/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
40164 {
40165 { 0, 0, 0, 0 },
40166 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
40167 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x72ef0000 }
40168 },
40169/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
40170 {
40171 { 0, 0, 0, 0 },
40172 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
40173 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x72ff0000 }
40174 },
40175/* mov.b${G} $Src16RnQI,$Dst16RnQI */
40176 {
40177 { 0, 0, 0, 0 },
40178 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
40179 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7200 }
40180 },
40181/* mov.b${G} $Src16AnQI,$Dst16RnQI */
40182 {
40183 { 0, 0, 0, 0 },
40184 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
40185 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7240 }
40186 },
40187/* mov.b${G} [$Src16An],$Dst16RnQI */
40188 {
40189 { 0, 0, 0, 0 },
40190 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
40191 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7260 }
40192 },
40193/* mov.b${G} $Src16RnQI,$Dst16AnQI */
40194 {
40195 { 0, 0, 0, 0 },
40196 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
40197 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7204 }
40198 },
40199/* mov.b${G} $Src16AnQI,$Dst16AnQI */
40200 {
40201 { 0, 0, 0, 0 },
40202 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
40203 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7244 }
40204 },
40205/* mov.b${G} [$Src16An],$Dst16AnQI */
40206 {
40207 { 0, 0, 0, 0 },
40208 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
40209 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7264 }
40210 },
40211/* mov.b${G} $Src16RnQI,[$Dst16An] */
40212 {
40213 { 0, 0, 0, 0 },
40214 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
40215 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7206 }
40216 },
40217/* mov.b${G} $Src16AnQI,[$Dst16An] */
40218 {
40219 { 0, 0, 0, 0 },
40220 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
40221 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7246 }
40222 },
40223/* mov.b${G} [$Src16An],[$Dst16An] */
40224 {
40225 { 0, 0, 0, 0 },
40226 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
40227 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7266 }
40228 },
40229/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
40230 {
40231 { 0, 0, 0, 0 },
40232 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40233 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x720800 }
40234 },
40235/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
40236 {
40237 { 0, 0, 0, 0 },
40238 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40239 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x724800 }
40240 },
40241/* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
40242 {
40243 { 0, 0, 0, 0 },
40244 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40245 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x726800 }
40246 },
40247/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
40248 {
40249 { 0, 0, 0, 0 },
40250 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40251 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x720c0000 }
40252 },
40253/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
40254 {
40255 { 0, 0, 0, 0 },
40256 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40257 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x724c0000 }
40258 },
40259/* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
40260 {
40261 { 0, 0, 0, 0 },
40262 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40263 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x726c0000 }
40264 },
40265/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
40266 {
40267 { 0, 0, 0, 0 },
40268 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40269 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x720a00 }
40270 },
40271/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
40272 {
40273 { 0, 0, 0, 0 },
40274 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40275 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x724a00 }
40276 },
40277/* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
40278 {
40279 { 0, 0, 0, 0 },
40280 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40281 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x726a00 }
40282 },
40283/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
40284 {
40285 { 0, 0, 0, 0 },
40286 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40287 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x720e0000 }
40288 },
40289/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
40290 {
40291 { 0, 0, 0, 0 },
40292 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40293 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x724e0000 }
40294 },
40295/* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
40296 {
40297 { 0, 0, 0, 0 },
40298 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40299 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x726e0000 }
40300 },
40301/* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
40302 {
40303 { 0, 0, 0, 0 },
40304 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40305 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x720b00 }
40306 },
40307/* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
40308 {
40309 { 0, 0, 0, 0 },
40310 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40311 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x724b00 }
40312 },
40313/* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
40314 {
40315 { 0, 0, 0, 0 },
40316 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40317 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x726b00 }
40318 },
40319/* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
40320 {
40321 { 0, 0, 0, 0 },
40322 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
40323 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x720f0000 }
40324 },
40325/* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
40326 {
40327 { 0, 0, 0, 0 },
40328 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
40329 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x724f0000 }
40330 },
40331/* mov.b${G} [$Src16An],${Dsp-16-u16} */
40332 {
40333 { 0, 0, 0, 0 },
40334 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
40335 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x726f0000 }
40336 },
40337/* mov.w${Z} #0,${Dsp-8-u8}[sb] */
40338 {
40339 { 0, 0, 0, 0 },
40340 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40341 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2300 }
40342 },
40343/* mov.w${Z} #0,${Dsp-8-s8}[fb] */
40344 {
40345 { 0, 0, 0, 0 },
40346 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40347 & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3300 }
40348 },
40349/* mov.w${Z} #0,${Dsp-8-u16} */
40350 {
40351 { 0, 0, 0, 0 },
40352 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
40353 & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x130000 }
40354 },
40355/* mov.w${Z} #0,r0 */
40356 {
40357 { 0, 0, 0, 0 },
40358 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 0 } },
f75eb1c0 40359 & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x3 }
49f58d10
JB		 40360 },
40361/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
40362 {
40363 { 0, 0, 0, 0 },
40364 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40365 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2200 }
40366 },
40367/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
40368 {
40369 { 0, 0, 0, 0 },
40370 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40371 & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3200 }
40372 },
40373/* mov.b${Z} #0,${Dsp-8-u16} */
40374 {
40375 { 0, 0, 0, 0 },
40376 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
40377 & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x120000 }
40378 },
40379/* mov.b${Z} #0,r0l */
40380 {
40381 { 0, 0, 0, 0 },
40382 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } },
40383 & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x2 }
40384 },
40385/* mov.b${Z} #0,r0l */
40386 {
40387 { 0, 0, 0, 0 },
40388 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } },
c6552317 40389 & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xb4 }
49f58d10
JB		 40390 },
40391/* mov.b${Z} #0,r0h */
40392 {
40393 { 0, 0, 0, 0 },
40394 { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'h', 0 } },
c6552317 40395 & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xb3 }
49f58d10
JB		 40396 },
40397/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
40398 {
40399 { 0, 0, 0, 0 },
40400 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
c6552317 40401 & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xb500 }
49f58d10
JB		 40402 },
40403/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
40404 {
40405 { 0, 0, 0, 0 },
40406 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
c6552317 40407 & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xb600 }
49f58d10
JB		 40408 },
40409/* mov.b${Z} #0,${Dsp-8-u16} */
40410 {
40411 { 0, 0, 0, 0 },
40412 { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
c6552317 40413 & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xb70000 }
49f58d10 40414 },
49f58d10
JB		 40415/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
40416 {
40417 { 0, 0, 0, 0 },
40418 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
40419 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf920 }
40420 },
40421/* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
40422 {
40423 { 0, 0, 0, 0 },
40424 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
40425 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf1a0 }
40426 },
40427/* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
40428 {
40429 { 0, 0, 0, 0 },
40430 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40431 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf120 }
40432 },
40433/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40434 {
40435 { 0, 0, 0, 0 },
40436 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40437 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf32000 }
40438 },
40439/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40440 {
40441 { 0, 0, 0, 0 },
40442 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40443 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5200000 }
40444 },
40445/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40446 {
40447 { 0, 0, 0, 0 },
40448 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40449 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7200000 }
40450 },
40451/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
40452 {
40453 { 0, 0, 0, 0 },
40454 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40455 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3a000 }
40456 },
40457/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
40458 {
40459 { 0, 0, 0, 0 },
40460 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40461 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5a00000 }
40462 },
40463/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
40464 {
40465 { 0, 0, 0, 0 },
40466 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40467 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3e000 }
40468 },
40469/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
40470 {
40471 { 0, 0, 0, 0 },
40472 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40473 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5e00000 }
40474 },
40475/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
40476 {
40477 { 0, 0, 0, 0 },
40478 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
40479 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7e00000 }
40480 },
40481/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
40482 {
40483 { 0, 0, 0, 0 },
40484 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
40485 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7a00000 }
40486 },
40487/* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
40488 {
40489 { 0, 0, 0, 0 },
40490 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
40491 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf820 }
40492 },
40493/* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
40494 {
40495 { 0, 0, 0, 0 },
40496 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
40497 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf0a0 }
40498 },
40499/* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
40500 {
40501 { 0, 0, 0, 0 },
40502 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40503 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf020 }
40504 },
40505/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40506 {
40507 { 0, 0, 0, 0 },
40508 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40509 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf22000 }
40510 },
40511/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40512 {
40513 { 0, 0, 0, 0 },
40514 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40515 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4200000 }
40516 },
40517/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40518 {
40519 { 0, 0, 0, 0 },
40520 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40521 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6200000 }
40522 },
40523/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
40524 {
40525 { 0, 0, 0, 0 },
40526 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40527 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2a000 }
40528 },
40529/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
40530 {
40531 { 0, 0, 0, 0 },
40532 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40533 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4a00000 }
40534 },
40535/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
40536 {
40537 { 0, 0, 0, 0 },
40538 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40539 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2e000 }
40540 },
40541/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
40542 {
40543 { 0, 0, 0, 0 },
40544 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40545 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4e00000 }
40546 },
40547/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
40548 {
40549 { 0, 0, 0, 0 },
40550 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
40551 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6e00000 }
40552 },
40553/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
40554 {
40555 { 0, 0, 0, 0 },
40556 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
40557 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6a00000 }
40558 },
db313fa6 40559/* mov.w${Q} #${Imm-8-s4},$Dst16RnHI */
49f58d10
JB		 40560 {
40561 { 0, 0, 0, 0 },
db313fa6
DD		 40562 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
40563 & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd900 }
49f58d10 40564 },
db313fa6 40565/* mov.w${Q} #${Imm-8-s4},$Dst16AnHI */
49f58d10
JB		 40566 {
40567 { 0, 0, 0, 0 },
db313fa6
DD		 40568 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
40569 & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd904 }
49f58d10
JB		 40570 },
40571/* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
40572 {
40573 { 0, 0, 0, 0 },
40574 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
db313fa6 40575 & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd906 }
49f58d10
JB		 40576 },
40577/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
40578 {
40579 { 0, 0, 0, 0 },
40580 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
db313fa6 40581 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd90800 }
49f58d10
JB		 40582 },
40583/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
40584 {
40585 { 0, 0, 0, 0 },
40586 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
db313fa6 40587 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd90c0000 }
49f58d10
JB		 40588 },
40589/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
40590 {
40591 { 0, 0, 0, 0 },
40592 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
db313fa6 40593 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd90a00 }
49f58d10
JB		 40594 },
40595/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
40596 {
40597 { 0, 0, 0, 0 },
40598 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
db313fa6 40599 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd90e0000 }
49f58d10
JB		 40600 },
40601/* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
40602 {
40603 { 0, 0, 0, 0 },
40604 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
db313fa6 40605 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd90b00 }
49f58d10
JB		 40606 },
40607/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
40608 {
40609 { 0, 0, 0, 0 },
40610 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
db313fa6 40611 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd90f0000 }
49f58d10
JB		 40612 },
40613/* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
40614 {
40615 { 0, 0, 0, 0 },
40616 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
db313fa6 40617 & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xd800 }
49f58d10
JB		 40618 },
40619/* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
40620 {
40621 { 0, 0, 0, 0 },
40622 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
db313fa6 40623 & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xd804 }
49f58d10
JB		 40624 },
40625/* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
40626 {
40627 { 0, 0, 0, 0 },
40628 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
db313fa6 40629 & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xd806 }
49f58d10
JB		 40630 },
40631/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
40632 {
40633 { 0, 0, 0, 0 },
40634 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
db313fa6 40635 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd80800 }
49f58d10
JB		 40636 },
40637/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
40638 {
40639 { 0, 0, 0, 0 },
40640 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
db313fa6 40641 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd80c0000 }
49f58d10
JB		 40642 },
40643/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
40644 {
40645 { 0, 0, 0, 0 },
40646 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
db313fa6 40647 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd80a00 }
49f58d10
JB		 40648 },
40649/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
40650 {
40651 { 0, 0, 0, 0 },
40652 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
db313fa6 40653 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd80e0000 }
49f58d10
JB		 40654 },
40655/* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
40656 {
40657 { 0, 0, 0, 0 },
40658 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
db313fa6 40659 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd80b00 }
49f58d10
JB		 40660 },
40661/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
40662 {
40663 { 0, 0, 0, 0 },
40664 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
db313fa6 40665 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd80f0000 }
49f58d10 40666 },
e729279b
NC		 40667/* mov.b${S} #${Imm-8-QI},r0l */
40668 {
40669 { 0, 0, 0, 0 },
40670 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
40671 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 }
40672 },
40673/* mov.b${S} #${Imm-8-QI},r0h */
40674 {
40675 { 0, 0, 0, 0 },
40676 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
40677 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 }
40678 },
40679/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
40680 {
40681 { 0, 0, 0, 0 },
40682 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40683 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 }
40684 },
40685/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
40686 {
40687 { 0, 0, 0, 0 },
40688 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40689 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 }
40690 },
40691/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
40692 {
40693 { 0, 0, 0, 0 },
40694 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
40695 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 }
40696 },
40697/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
40698 {
40699 { 0, 0, 0, 0 },
40700 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40701 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 }
40702 },
40703/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
40704 {
40705 { 0, 0, 0, 0 },
40706 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40707 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 }
40708 },
40709/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
40710 {
40711 { 0, 0, 0, 0 },
40712 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
40713 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 }
40714 },
40715/* mov.w${S} #${Imm-8-HI},r0 */
40716 {
40717 { 0, 0, 0, 0 },
40718 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
40719 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 }
40720 },
40721/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
40722 {
40723 { 0, 0, 0, 0 },
40724 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40725 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 }
40726 },
40727/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
40728 {
40729 { 0, 0, 0, 0 },
40730 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40731 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 }
40732 },
40733/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
40734 {
40735 { 0, 0, 0, 0 },
40736 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
40737 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 }
40738 },
40739/* mov.b${S} #${Imm-8-QI},r0l */
40740 {
40741 { 0, 0, 0, 0 },
40742 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
40743 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 }
40744 },
49f58d10
JB		 40745/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
40746 {
40747 { 0, 0, 0, 0 },
40748 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
40749 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb8310000 }
40750 },
40751/* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
40752 {
40753 { 0, 0, 0, 0 },
40754 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
40755 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb0b10000 }
40756 },
40757/* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
40758 {
40759 { 0, 0, 0, 0 },
40760 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40761 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb0310000 }
40762 },
40763/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40764 {
40765 { 0, 0, 0, 0 },
40766 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40767 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2310000 }
40768 },
40769/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
40770 {
40771 { 0, 0, 0, 0 },
40772 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40773 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2b10000 }
40774 },
40775/* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
40776 {
40777 { 0, 0, 0, 0 },
40778 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40779 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2f10000 }
40780 },
40781/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40782 {
40783 { 0, 0, 0, 0 },
40784 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40785 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4310000 }
40786 },
40787/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
40788 {
40789 { 0, 0, 0, 0 },
40790 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40791 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4b10000 }
40792 },
40793/* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
40794 {
40795 { 0, 0, 0, 0 },
40796 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40797 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4f10000 }
40798 },
40799/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
40800 {
40801 { 0, 0, 0, 0 },
40802 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
40803 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6f10000 }
40804 },
40805/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40806 {
40807 { 0, 0, 0, 0 },
40808 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40809 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6310000 }
40810 },
40811/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
40812 {
40813 { 0, 0, 0, 0 },
40814 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
40815 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6b10000 }
40816 },
40817/* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
40818 {
40819 { 0, 0, 0, 0 },
40820 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
40821 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992f0000 }
40822 },
40823/* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
40824 {
40825 { 0, 0, 0, 0 },
40826 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
40827 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91af0000 }
40828 },
40829/* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
40830 {
40831 { 0, 0, 0, 0 },
40832 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40833 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912f0000 }
40834 },
40835/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40836 {
40837 { 0, 0, 0, 0 },
40838 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40839 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932f0000 }
40840 },
40841/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
40842 {
40843 { 0, 0, 0, 0 },
40844 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40845 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93af0000 }
40846 },
40847/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
40848 {
40849 { 0, 0, 0, 0 },
40850 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40851 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ef0000 }
40852 },
40853/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40854 {
40855 { 0, 0, 0, 0 },
40856 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40857 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952f0000 }
40858 },
40859/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
40860 {
40861 { 0, 0, 0, 0 },
40862 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40863 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95af0000 }
40864 },
40865/* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
40866 {
40867 { 0, 0, 0, 0 },
40868 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40869 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ef0000 }
40870 },
40871/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
40872 {
40873 { 0, 0, 0, 0 },
40874 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
40875 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ef0000 }
40876 },
40877/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40878 {
40879 { 0, 0, 0, 0 },
40880 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40881 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972f0000 }
40882 },
40883/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
40884 {
40885 { 0, 0, 0, 0 },
40886 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
40887 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97af0000 }
40888 },
40889/* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
40890 {
40891 { 0, 0, 0, 0 },
40892 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
40893 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982f00 }
40894 },
40895/* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
40896 {
40897 { 0, 0, 0, 0 },
40898 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
40899 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90af00 }
40900 },
40901/* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
40902 {
40903 { 0, 0, 0, 0 },
40904 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40905 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902f00 }
40906 },
40907/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40908 {
40909 { 0, 0, 0, 0 },
40910 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40911 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922f0000 }
40912 },
40913/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
40914 {
40915 { 0, 0, 0, 0 },
40916 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40917 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92af0000 }
40918 },
40919/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
40920 {
40921 { 0, 0, 0, 0 },
40922 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40923 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ef0000 }
40924 },
40925/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40926 {
40927 { 0, 0, 0, 0 },
40928 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40929 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942f0000 }
40930 },
40931/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
40932 {
40933 { 0, 0, 0, 0 },
40934 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40935 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94af0000 }
40936 },
40937/* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
40938 {
40939 { 0, 0, 0, 0 },
40940 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40941 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ef0000 }
40942 },
40943/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
40944 {
40945 { 0, 0, 0, 0 },
40946 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
40947 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ef0000 }
40948 },
40949/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40950 {
40951 { 0, 0, 0, 0 },
40952 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40953 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962f0000 }
40954 },
40955/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
40956 {
40957 { 0, 0, 0, 0 },
40958 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
40959 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96af0000 }
40960 },
40961/* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
40962 {
40963 { 0, 0, 0, 0 },
40964 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
40965 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x75c00000 }
40966 },
40967/* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
40968 {
40969 { 0, 0, 0, 0 },
40970 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
40971 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x75c40000 }
40972 },
40973/* mov.w${G} #${Imm-16-HI},[$Dst16An] */
40974 {
40975 { 0, 0, 0, 0 },
40976 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
40977 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x75c60000 }
40978 },
40979/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
40980 {
40981 { 0, 0, 0, 0 },
40982 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40983 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x75c80000 }
40984 },
40985/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
40986 {
40987 { 0, 0, 0, 0 },
40988 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40989 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x75ca0000 }
40990 },
40991/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
40992 {
40993 { 0, 0, 0, 0 },
40994 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40995 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x75cb0000 }
40996 },
40997/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
40998 {
40999 { 0, 0, 0, 0 },
41000 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
41001 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x75cc0000 }
41002 },
41003/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
41004 {
41005 { 0, 0, 0, 0 },
41006 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
41007 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x75ce0000 }
41008 },
41009/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
41010 {
41011 { 0, 0, 0, 0 },
41012 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
41013 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x75cf0000 }
41014 },
41015/* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
41016 {
41017 { 0, 0, 0, 0 },
41018 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
41019 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x74c000 }
41020 },
41021/* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
41022 {
41023 { 0, 0, 0, 0 },
41024 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
41025 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x74c400 }
41026 },
41027/* mov.b${G} #${Imm-16-QI},[$Dst16An] */
41028 {
41029 { 0, 0, 0, 0 },
41030 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
41031 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x74c600 }
41032 },
41033/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
41034 {
41035 { 0, 0, 0, 0 },
41036 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
41037 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x74c80000 }
41038 },
41039/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
41040 {
41041 { 0, 0, 0, 0 },
41042 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
41043 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x74ca0000 }
41044 },
41045/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
41046 {
41047 { 0, 0, 0, 0 },
41048 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
41049 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x74cb0000 }
41050 },
41051/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
41052 {
41053 { 0, 0, 0, 0 },
41054 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
41055 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x74cc0000 }
41056 },
41057/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
41058 {
41059 { 0, 0, 0, 0 },
41060 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
41061 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x74ce0000 }
41062 },
41063/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
41064 {
41065 { 0, 0, 0, 0 },
41066 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
41067 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x74cf0000 }
41068 },
41069/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41070 {
41071 { 0, 0, 0, 0 },
41072 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41073 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990c00 }
41074 },
41075/* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
41076 {
41077 { 0, 0, 0, 0 },
41078 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41079 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992c00 }
41080 },
41081/* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
41082 {
41083 { 0, 0, 0, 0 },
41084 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41085 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993c00 }
41086 },
41087/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41088 {
41089 { 0, 0, 0, 0 },
41090 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41091 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918c00 }
41092 },
41093/* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
41094 {
41095 { 0, 0, 0, 0 },
41096 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41097 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ac00 }
41098 },
41099/* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
41100 {
41101 { 0, 0, 0, 0 },
41102 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41103 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bc00 }
41104 },
41105/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41106 {
41107 { 0, 0, 0, 0 },
41108 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41109 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910c00 }
41110 },
41111/* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41112 {
41113 { 0, 0, 0, 0 },
41114 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41115 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912c00 }
41116 },
41117/* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41118 {
41119 { 0, 0, 0, 0 },
41120 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41121 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913c00 }
41122 },
41123/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41124 {
41125 { 0, 0, 0, 0 },
41126 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41127 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930c00 }
41128 },
41129/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41130 {
41131 { 0, 0, 0, 0 },
41132 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41133 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932c00 }
41134 },
41135/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41136 {
41137 { 0, 0, 0, 0 },
41138 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41139 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933c00 }
41140 },
41141/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41142 {
41143 { 0, 0, 0, 0 },
41144 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41145 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950c00 }
41146 },
41147/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41148 {
41149 { 0, 0, 0, 0 },
41150 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41151 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952c00 }
41152 },
41153/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41154 {
41155 { 0, 0, 0, 0 },
41156 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41157 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953c00 }
41158 },
41159/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41160 {
41161 { 0, 0, 0, 0 },
41162 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41163 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970c00 }
41164 },
41165/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41166 {
41167 { 0, 0, 0, 0 },
41168 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41169 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972c00 }
41170 },
41171/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41172 {
41173 { 0, 0, 0, 0 },
41174 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41175 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973c00 }
41176 },
41177/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41178 {
41179 { 0, 0, 0, 0 },
41180 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41181 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938c00 }
41182 },
41183/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41184 {
41185 { 0, 0, 0, 0 },
41186 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41187 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ac00 }
41188 },
41189/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41190 {
41191 { 0, 0, 0, 0 },
41192 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41193 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bc00 }
41194 },
41195/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41196 {
41197 { 0, 0, 0, 0 },
41198 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41199 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958c00 }
41200 },
41201/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41202 {
41203 { 0, 0, 0, 0 },
41204 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41205 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ac00 }
41206 },
41207/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41208 {
41209 { 0, 0, 0, 0 },
41210 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41211 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bc00 }
41212 },
41213/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41214 {
41215 { 0, 0, 0, 0 },
41216 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41217 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cc00 }
41218 },
41219/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41220 {
41221 { 0, 0, 0, 0 },
41222 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41223 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ec00 }
41224 },
41225/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41226 {
41227 { 0, 0, 0, 0 },
41228 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41229 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fc00 }
41230 },
41231/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41232 {
41233 { 0, 0, 0, 0 },
41234 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41235 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cc00 }
41236 },
41237/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41238 {
41239 { 0, 0, 0, 0 },
41240 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41241 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ec00 }
41242 },
41243/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41244 {
41245 { 0, 0, 0, 0 },
41246 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41247 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fc00 }
41248 },
41249/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41250 {
41251 { 0, 0, 0, 0 },
41252 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
41253 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cc00 }
41254 },
41255/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41256 {
41257 { 0, 0, 0, 0 },
41258 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
41259 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ec00 }
41260 },
41261/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41262 {
41263 { 0, 0, 0, 0 },
41264 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
41265 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fc00 }
41266 },
41267/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41268 {
41269 { 0, 0, 0, 0 },
41270 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
41271 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978c00 }
41272 },
41273/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41274 {
41275 { 0, 0, 0, 0 },
41276 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
41277 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ac00 }
41278 },
41279/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41280 {
41281 { 0, 0, 0, 0 },
41282 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
41283 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bc00 }
41284 },
41285/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41286 {
41287 { 0, 0, 0, 0 },
41288 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41289 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90c00 }
41290 },
41291/* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
41292 {
41293 { 0, 0, 0, 0 },
41294 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41295 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92c00 }
41296 },
41297/* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
41298 {
41299 { 0, 0, 0, 0 },
41300 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41301 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93c00 }
41302 },
41303/* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
41304 {
41305 { 0, 0, 0, 0 },
41306 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
41307 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93c00 }
41308 },
41309/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41310 {
41311 { 0, 0, 0, 0 },
41312 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41313 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18c00 }
41314 },
41315/* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
41316 {
41317 { 0, 0, 0, 0 },
41318 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41319 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ac00 }
41320 },
41321/* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
41322 {
41323 { 0, 0, 0, 0 },
41324 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41325 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bc00 }
41326 },
41327/* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
41328 {
41329 { 0, 0, 0, 0 },
41330 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
41331 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bc00 }
41332 },
41333/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41334 {
41335 { 0, 0, 0, 0 },
41336 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41337 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10c00 }
41338 },
41339/* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41340 {
41341 { 0, 0, 0, 0 },
41342 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41343 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12c00 }
41344 },
41345/* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41346 {
41347 { 0, 0, 0, 0 },
41348 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41349 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13c00 }
41350 },
41351/* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41352 {
41353 { 0, 0, 0, 0 },
41354 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41355 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13c00 }
41356 },
41357/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41358 {
41359 { 0, 0, 0, 0 },
41360 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41361 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30c00 }
41362 },
41363/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41364 {
41365 { 0, 0, 0, 0 },
41366 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41367 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32c00 }
41368 },
41369/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41370 {
41371 { 0, 0, 0, 0 },
41372 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41373 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33c00 }
41374 },
41375/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41376 {
41377 { 0, 0, 0, 0 },
41378 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41379 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33c00 }
41380 },
41381/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41382 {
41383 { 0, 0, 0, 0 },
41384 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41385 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50c00 }
41386 },
41387/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41388 {
41389 { 0, 0, 0, 0 },
41390 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41391 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52c00 }
41392 },
41393/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41394 {
41395 { 0, 0, 0, 0 },
41396 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41397 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53c00 }
41398 },
41399/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41400 {
41401 { 0, 0, 0, 0 },
41402 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41403 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53c00 }
41404 },
41405/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41406 {
41407 { 0, 0, 0, 0 },
41408 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41409 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70c00 }
41410 },
41411/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41412 {
41413 { 0, 0, 0, 0 },
41414 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41415 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72c00 }
41416 },
41417/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41418 {
41419 { 0, 0, 0, 0 },
41420 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41421 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73c00 }
41422 },
41423/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41424 {
41425 { 0, 0, 0, 0 },
41426 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41427 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73c00 }
41428 },
41429/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41430 {
41431 { 0, 0, 0, 0 },
41432 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41433 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38c00 }
41434 },
41435/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41436 {
41437 { 0, 0, 0, 0 },
41438 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41439 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ac00 }
41440 },
41441/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41442 {
41443 { 0, 0, 0, 0 },
41444 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41445 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bc00 }
41446 },
41447/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41448 {
41449 { 0, 0, 0, 0 },
41450 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41451 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bc00 }
41452 },
41453/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41454 {
41455 { 0, 0, 0, 0 },
41456 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41457 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58c00 }
41458 },
41459/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41460 {
41461 { 0, 0, 0, 0 },
41462 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41463 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ac00 }
41464 },
41465/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41466 {
41467 { 0, 0, 0, 0 },
41468 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41469 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bc00 }
41470 },
41471/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41472 {
41473 { 0, 0, 0, 0 },
41474 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41475 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bc00 }
41476 },
41477/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41478 {
41479 { 0, 0, 0, 0 },
41480 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41481 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cc00 }
41482 },
41483/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41484 {
41485 { 0, 0, 0, 0 },
41486 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41487 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ec00 }
41488 },
41489/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41490 {
41491 { 0, 0, 0, 0 },
41492 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41493 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fc00 }
41494 },
41495/* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41496 {
41497 { 0, 0, 0, 0 },
41498 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41499 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fc00 }
41500 },
41501/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41502 {
41503 { 0, 0, 0, 0 },
41504 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41505 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cc00 }
41506 },
41507/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41508 {
41509 { 0, 0, 0, 0 },
41510 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41511 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ec00 }
41512 },
41513/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41514 {
41515 { 0, 0, 0, 0 },
41516 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41517 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fc00 }
41518 },
41519/* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41520 {
41521 { 0, 0, 0, 0 },
41522 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41523 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fc00 }
41524 },
41525/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41526 {
41527 { 0, 0, 0, 0 },
41528 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
41529 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cc00 }
41530 },
41531/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41532 {
41533 { 0, 0, 0, 0 },
41534 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
41535 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ec00 }
41536 },
41537/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41538 {
41539 { 0, 0, 0, 0 },
41540 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
41541 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fc00 }
41542 },
41543/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
41544 {
41545 { 0, 0, 0, 0 },
41546 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
41547 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fc00 }
41548 },
41549/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41550 {
41551 { 0, 0, 0, 0 },
41552 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
41553 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78c00 }
41554 },
41555/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41556 {
41557 { 0, 0, 0, 0 },
41558 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
41559 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ac00 }
41560 },
41561/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41562 {
41563 { 0, 0, 0, 0 },
41564 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
41565 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bc00 }
41566 },
41567/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
41568 {
41569 { 0, 0, 0, 0 },
41570 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
41571 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bc00 }
41572 },
41573/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41574 {
41575 { 0, 0, 0, 0 },
41576 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41577 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90c00 }
41578 },
41579/* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
41580 {
41581 { 0, 0, 0, 0 },
41582 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
41583 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92c00 }
41584 },
41585/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41586 {
41587 { 0, 0, 0, 0 },
41588 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41589 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18c00 }
41590 },
41591/* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
41592 {
41593 { 0, 0, 0, 0 },
41594 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
41595 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ac00 }
41596 },
41597/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41598 {
41599 { 0, 0, 0, 0 },
41600 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41601 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10c00 }
41602 },
41603/* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41604 {
41605 { 0, 0, 0, 0 },
41606 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41607 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12c00 }
41608 },
41609/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41610 {
41611 { 0, 0, 0, 0 },
41612 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41613 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30c00 }
41614 },
41615/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41616 {
41617 { 0, 0, 0, 0 },
41618 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41619 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32c00 }
41620 },
41621/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41622 {
41623 { 0, 0, 0, 0 },
41624 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41625 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50c00 }
41626 },
41627/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41628 {
41629 { 0, 0, 0, 0 },
41630 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41631 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52c00 }
41632 },
41633/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41634 {
41635 { 0, 0, 0, 0 },
41636 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41637 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70c00 }
41638 },
41639/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41640 {
41641 { 0, 0, 0, 0 },
41642 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41643 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72c00 }
41644 },
41645/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41646 {
41647 { 0, 0, 0, 0 },
41648 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
41649 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38c00 }
41650 },
41651/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41652 {
41653 { 0, 0, 0, 0 },
41654 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
41655 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ac00 }
41656 },
41657/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41658 {
41659 { 0, 0, 0, 0 },
41660 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
41661 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58c00 }
41662 },
41663/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41664 {
41665 { 0, 0, 0, 0 },
41666 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
41667 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ac00 }
41668 },
41669/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41670 {
41671 { 0, 0, 0, 0 },
41672 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
41673 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cc00 }
41674 },
41675/* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41676 {
41677 { 0, 0, 0, 0 },
41678 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
41679 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ec00 }
41680 },
41681/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41682 {
41683 { 0, 0, 0, 0 },
41684 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
41685 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cc00 }
41686 },
41687/* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41688 {
41689 { 0, 0, 0, 0 },
41690 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
41691 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ec00 }
41692 },
41693/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41694 {
41695 { 0, 0, 0, 0 },
41696 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
41697 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cc00 }
41698 },
41699/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
41700 {
41701 { 0, 0, 0, 0 },
41702 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
41703 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ec00 }
41704 },
41705/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41706 {
41707 { 0, 0, 0, 0 },
41708 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
41709 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78c00 }
41710 },
41711/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
41712 {
41713 { 0, 0, 0, 0 },
41714 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
41715 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ac00 }
41716 },
41717/* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
41718 {
41719 { 0, 0, 0, 0 },
41720 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
41721 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90c }
41722 },
41723/* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41724 {
41725 { 0, 0, 0, 0 },
41726 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
41727 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892c }
41728 },
41729/* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41730 {
41731 { 0, 0, 0, 0 },
41732 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41733 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890c }
41734 },
41735/* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41736 {
41737 { 0, 0, 0, 0 },
41738 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
41739 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18c }
41740 },
41741/* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41742 {
41743 { 0, 0, 0, 0 },
41744 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
41745 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ac }
41746 },
41747/* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41748 {
41749 { 0, 0, 0, 0 },
41750 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41751 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818c }
41752 },
41753/* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41754 {
41755 { 0, 0, 0, 0 },
41756 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41757 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10c }
41758 },
41759/* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41760 {
41761 { 0, 0, 0, 0 },
41762 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41763 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812c }
41764 },
41765/* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41766 {
41767 { 0, 0, 0, 0 },
41768 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41769 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810c }
41770 },
41771/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41772 {
41773 { 0, 0, 0, 0 },
41774 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41775 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30c00 }
41776 },
41777/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41778 {
41779 { 0, 0, 0, 0 },
41780 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41781 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832c00 }
41782 },
41783/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41784 {
41785 { 0, 0, 0, 0 },
41786 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41787 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830c00 }
41788 },
41789/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41790 {
41791 { 0, 0, 0, 0 },
41792 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41793 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50c00 }
41794 },
41795/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41796 {
41797 { 0, 0, 0, 0 },
41798 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41799 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852c00 }
41800 },
41801/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41802 {
41803 { 0, 0, 0, 0 },
41804 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41805 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850c00 }
41806 },
41807/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41808 {
41809 { 0, 0, 0, 0 },
41810 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41811 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70c00 }
41812 },
41813/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41814 {
41815 { 0, 0, 0, 0 },
41816 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41817 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872c00 }
41818 },
41819/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41820 {
41821 { 0, 0, 0, 0 },
41822 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41823 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870c00 }
41824 },
41825/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41826 {
41827 { 0, 0, 0, 0 },
41828 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41829 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38c00 }
41830 },
41831/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41832 {
41833 { 0, 0, 0, 0 },
41834 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41835 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ac00 }
41836 },
41837/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41838 {
41839 { 0, 0, 0, 0 },
41840 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41841 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838c00 }
41842 },
41843/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41844 {
41845 { 0, 0, 0, 0 },
41846 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41847 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58c00 }
41848 },
41849/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41850 {
41851 { 0, 0, 0, 0 },
41852 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41853 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ac00 }
41854 },
41855/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41856 {
41857 { 0, 0, 0, 0 },
41858 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41859 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858c00 }
41860 },
41861/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41862 {
41863 { 0, 0, 0, 0 },
41864 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41865 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cc00 }
41866 },
41867/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41868 {
41869 { 0, 0, 0, 0 },
41870 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41871 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ec00 }
41872 },
41873/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41874 {
41875 { 0, 0, 0, 0 },
41876 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41877 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cc00 }
41878 },
41879/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41880 {
41881 { 0, 0, 0, 0 },
41882 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41883 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cc00 }
41884 },
41885/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41886 {
41887 { 0, 0, 0, 0 },
41888 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41889 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ec00 }
41890 },
41891/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41892 {
41893 { 0, 0, 0, 0 },
41894 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41895 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cc00 }
41896 },
41897/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41898 {
41899 { 0, 0, 0, 0 },
41900 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
41901 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cc00 }
41902 },
41903/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41904 {
41905 { 0, 0, 0, 0 },
41906 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
41907 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ec00 }
41908 },
41909/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41910 {
41911 { 0, 0, 0, 0 },
41912 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
41913 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cc00 }
41914 },
41915/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41916 {
41917 { 0, 0, 0, 0 },
41918 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
41919 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78c00 }
41920 },
41921/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41922 {
41923 { 0, 0, 0, 0 },
41924 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
41925 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ac00 }
41926 },
41927/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41928 {
41929 { 0, 0, 0, 0 },
41930 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
41931 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878c00 }
41932 },
41933/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41934 {
41935 { 0, 0, 0, 0 },
41936 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41937 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980c00 }
41938 },
41939/* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41940 {
41941 { 0, 0, 0, 0 },
41942 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41943 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982c00 }
41944 },
41945/* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41946 {
41947 { 0, 0, 0, 0 },
41948 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41949 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983c00 }
41950 },
41951/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41952 {
41953 { 0, 0, 0, 0 },
41954 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41955 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908c00 }
41956 },
41957/* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41958 {
41959 { 0, 0, 0, 0 },
41960 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41961 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ac00 }
41962 },
41963/* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41964 {
41965 { 0, 0, 0, 0 },
41966 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41967 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bc00 }
41968 },
41969/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41970 {
41971 { 0, 0, 0, 0 },
41972 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41973 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900c00 }
41974 },
41975/* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41976 {
41977 { 0, 0, 0, 0 },
41978 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41979 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902c00 }
41980 },
41981/* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41982 {
41983 { 0, 0, 0, 0 },
41984 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41985 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903c00 }
41986 },
41987/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41988 {
41989 { 0, 0, 0, 0 },
41990 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41991 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920c00 }
41992 },
41993/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41994 {
41995 { 0, 0, 0, 0 },
41996 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41997 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922c00 }
41998 },
41999/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
42000 {
42001 { 0, 0, 0, 0 },
42002 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42003 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923c00 }
42004 },
42005/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
42006 {
42007 { 0, 0, 0, 0 },
42008 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42009 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940c00 }
42010 },
42011/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
42012 {
42013 { 0, 0, 0, 0 },
42014 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42015 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942c00 }
42016 },
42017/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
42018 {
42019 { 0, 0, 0, 0 },
42020 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42021 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943c00 }
42022 },
42023/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
42024 {
42025 { 0, 0, 0, 0 },
42026 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42027 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960c00 }
42028 },
42029/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
42030 {
42031 { 0, 0, 0, 0 },
42032 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42033 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962c00 }
42034 },
42035/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
42036 {
42037 { 0, 0, 0, 0 },
42038 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42039 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963c00 }
42040 },
42041/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
42042 {
42043 { 0, 0, 0, 0 },
42044 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42045 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928c00 }
42046 },
42047/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
42048 {
42049 { 0, 0, 0, 0 },
42050 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42051 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ac00 }
42052 },
42053/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
42054 {
42055 { 0, 0, 0, 0 },
42056 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42057 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bc00 }
42058 },
42059/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
42060 {
42061 { 0, 0, 0, 0 },
42062 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42063 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948c00 }
42064 },
42065/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
42066 {
42067 { 0, 0, 0, 0 },
42068 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42069 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ac00 }
42070 },
42071/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
42072 {
42073 { 0, 0, 0, 0 },
42074 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42075 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bc00 }
42076 },
42077/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
42078 {
42079 { 0, 0, 0, 0 },
42080 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42081 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cc00 }
42082 },
42083/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
42084 {
42085 { 0, 0, 0, 0 },
42086 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42087 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ec00 }
42088 },
42089/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
42090 {
42091 { 0, 0, 0, 0 },
42092 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42093 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fc00 }
42094 },
42095/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
42096 {
42097 { 0, 0, 0, 0 },
42098 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42099 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cc00 }
42100 },
42101/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
42102 {
42103 { 0, 0, 0, 0 },
42104 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42105 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ec00 }
42106 },
42107/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
42108 {
42109 { 0, 0, 0, 0 },
42110 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42111 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fc00 }
42112 },
42113/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
42114 {
42115 { 0, 0, 0, 0 },
42116 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
42117 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cc00 }
42118 },
42119/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
42120 {
42121 { 0, 0, 0, 0 },
42122 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
42123 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ec00 }
42124 },
42125/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
42126 {
42127 { 0, 0, 0, 0 },
42128 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
42129 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fc00 }
42130 },
42131/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
42132 {
42133 { 0, 0, 0, 0 },
42134 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
42135 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968c00 }
42136 },
42137/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
42138 {
42139 { 0, 0, 0, 0 },
42140 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
42141 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ac00 }
42142 },
42143/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
42144 {
42145 { 0, 0, 0, 0 },
42146 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
42147 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bc00 }
42148 },
42149/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
42150 {
42151 { 0, 0, 0, 0 },
42152 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42153 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80c00 }
42154 },
42155/* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
42156 {
42157 { 0, 0, 0, 0 },
42158 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42159 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82c00 }
42160 },
42161/* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
42162 {
42163 { 0, 0, 0, 0 },
42164 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42165 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83c00 }
42166 },
42167/* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
42168 {
42169 { 0, 0, 0, 0 },
42170 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
42171 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83c00 }
42172 },
42173/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
42174 {
42175 { 0, 0, 0, 0 },
42176 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42177 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08c00 }
42178 },
42179/* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
42180 {
42181 { 0, 0, 0, 0 },
42182 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42183 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ac00 }
42184 },
42185/* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
42186 {
42187 { 0, 0, 0, 0 },
42188 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42189 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bc00 }
42190 },
42191/* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
42192 {
42193 { 0, 0, 0, 0 },
42194 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
42195 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bc00 }
42196 },
42197/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42198 {
42199 { 0, 0, 0, 0 },
42200 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42201 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00c00 }
42202 },
42203/* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
42204 {
42205 { 0, 0, 0, 0 },
42206 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42207 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02c00 }
42208 },
42209/* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
42210 {
42211 { 0, 0, 0, 0 },
42212 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42213 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03c00 }
42214 },
42215/* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
42216 {
42217 { 0, 0, 0, 0 },
42218 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42219 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03c00 }
42220 },
42221/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
42222 {
42223 { 0, 0, 0, 0 },
42224 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42225 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20c00 }
42226 },
42227/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
42228 {
42229 { 0, 0, 0, 0 },
42230 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42231 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22c00 }
42232 },
42233/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
42234 {
42235 { 0, 0, 0, 0 },
42236 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42237 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23c00 }
42238 },
42239/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
42240 {
42241 { 0, 0, 0, 0 },
42242 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42243 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23c00 }
42244 },
42245/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
42246 {
42247 { 0, 0, 0, 0 },
42248 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42249 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40c00 }
42250 },
42251/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
42252 {
42253 { 0, 0, 0, 0 },
42254 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42255 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42c00 }
42256 },
42257/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
42258 {
42259 { 0, 0, 0, 0 },
42260 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42261 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43c00 }
42262 },
42263/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
42264 {
42265 { 0, 0, 0, 0 },
42266 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42267 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43c00 }
42268 },
42269/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
42270 {
42271 { 0, 0, 0, 0 },
42272 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42273 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60c00 }
42274 },
42275/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
42276 {
42277 { 0, 0, 0, 0 },
42278 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42279 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62c00 }
42280 },
42281/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
42282 {
42283 { 0, 0, 0, 0 },
42284 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42285 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63c00 }
42286 },
42287/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
42288 {
42289 { 0, 0, 0, 0 },
42290 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42291 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63c00 }
42292 },
42293/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
42294 {
42295 { 0, 0, 0, 0 },
42296 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42297 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28c00 }
42298 },
42299/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
42300 {
42301 { 0, 0, 0, 0 },
42302 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42303 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ac00 }
42304 },
42305/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
42306 {
42307 { 0, 0, 0, 0 },
42308 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42309 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bc00 }
42310 },
42311/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
42312 {
42313 { 0, 0, 0, 0 },
42314 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42315 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bc00 }
42316 },
42317/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
42318 {
42319 { 0, 0, 0, 0 },
42320 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42321 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48c00 }
42322 },
42323/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
42324 {
42325 { 0, 0, 0, 0 },
42326 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42327 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ac00 }
42328 },
42329/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
42330 {
42331 { 0, 0, 0, 0 },
42332 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42333 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bc00 }
42334 },
42335/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
42336 {
42337 { 0, 0, 0, 0 },
42338 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42339 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bc00 }
42340 },
42341/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
42342 {
42343 { 0, 0, 0, 0 },
42344 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42345 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cc00 }
42346 },
42347/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
42348 {
42349 { 0, 0, 0, 0 },
42350 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42351 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ec00 }
42352 },
42353/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
42354 {
42355 { 0, 0, 0, 0 },
42356 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42357 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fc00 }
42358 },
42359/* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
42360 {
42361 { 0, 0, 0, 0 },
42362 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42363 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fc00 }
42364 },
42365/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
42366 {
42367 { 0, 0, 0, 0 },
42368 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42369 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cc00 }
42370 },
42371/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
42372 {
42373 { 0, 0, 0, 0 },
42374 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42375 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ec00 }
42376 },
42377/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
42378 {
42379 { 0, 0, 0, 0 },
42380 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42381 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fc00 }
42382 },
42383/* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
42384 {
42385 { 0, 0, 0, 0 },
42386 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42387 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fc00 }
42388 },
42389/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
42390 {
42391 { 0, 0, 0, 0 },
42392 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
42393 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cc00 }
42394 },
42395/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
42396 {
42397 { 0, 0, 0, 0 },
42398 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
42399 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ec00 }
42400 },
42401/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
42402 {
42403 { 0, 0, 0, 0 },
42404 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
42405 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fc00 }
42406 },
42407/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
42408 {
42409 { 0, 0, 0, 0 },
42410 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
42411 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fc00 }
42412 },
42413/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
42414 {
42415 { 0, 0, 0, 0 },
42416 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
42417 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68c00 }
42418 },
42419/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
42420 {
42421 { 0, 0, 0, 0 },
42422 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
42423 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ac00 }
42424 },
42425/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
42426 {
42427 { 0, 0, 0, 0 },
42428 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
42429 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bc00 }
42430 },
42431/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
42432 {
42433 { 0, 0, 0, 0 },
42434 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
42435 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bc00 }
42436 },
42437/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
42438 {
42439 { 0, 0, 0, 0 },
42440 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42441 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80c00 }
42442 },
42443/* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
42444 {
42445 { 0, 0, 0, 0 },
42446 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
42447 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82c00 }
42448 },
42449/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
42450 {
42451 { 0, 0, 0, 0 },
42452 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42453 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08c00 }
42454 },
42455/* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
42456 {
42457 { 0, 0, 0, 0 },
42458 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
42459 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ac00 }
42460 },
42461/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42462 {
42463 { 0, 0, 0, 0 },
42464 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42465 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00c00 }
42466 },
42467/* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
42468 {
42469 { 0, 0, 0, 0 },
42470 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42471 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02c00 }
42472 },
42473/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
42474 {
42475 { 0, 0, 0, 0 },
42476 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42477 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20c00 }
42478 },
42479/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
42480 {
42481 { 0, 0, 0, 0 },
42482 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42483 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22c00 }
42484 },
42485/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
42486 {
42487 { 0, 0, 0, 0 },
42488 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42489 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40c00 }
42490 },
42491/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
42492 {
42493 { 0, 0, 0, 0 },
42494 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42495 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42c00 }
42496 },
42497/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
42498 {
42499 { 0, 0, 0, 0 },
42500 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42501 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60c00 }
42502 },
42503/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
42504 {
42505 { 0, 0, 0, 0 },
42506 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42507 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62c00 }
42508 },
42509/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
42510 {
42511 { 0, 0, 0, 0 },
42512 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
42513 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28c00 }
42514 },
42515/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
42516 {
42517 { 0, 0, 0, 0 },
42518 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
42519 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ac00 }
42520 },
42521/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
42522 {
42523 { 0, 0, 0, 0 },
42524 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
42525 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48c00 }
42526 },
42527/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
42528 {
42529 { 0, 0, 0, 0 },
42530 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
42531 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ac00 }
42532 },
42533/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
42534 {
42535 { 0, 0, 0, 0 },
42536 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
42537 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cc00 }
42538 },
42539/* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
42540 {
42541 { 0, 0, 0, 0 },
42542 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
42543 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ec00 }
42544 },
42545/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
42546 {
42547 { 0, 0, 0, 0 },
42548 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
42549 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cc00 }
42550 },
42551/* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
42552 {
42553 { 0, 0, 0, 0 },
42554 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
42555 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ec00 }
42556 },
42557/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
42558 {
42559 { 0, 0, 0, 0 },
42560 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
42561 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cc00 }
42562 },
42563/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
42564 {
42565 { 0, 0, 0, 0 },
42566 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
42567 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ec00 }
42568 },
42569/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
42570 {
42571 { 0, 0, 0, 0 },
42572 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
42573 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68c00 }
42574 },
42575/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
42576 {
42577 { 0, 0, 0, 0 },
42578 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
42579 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ac00 }
42580 },
42581/* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
42582 {
42583 { 0, 0, 0, 0 },
42584 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42585 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80c }
42586 },
42587/* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
42588 {
42589 { 0, 0, 0, 0 },
42590 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42591 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882c }
42592 },
42593/* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
42594 {
42595 { 0, 0, 0, 0 },
42596 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42597 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880c }
42598 },
42599/* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
42600 {
42601 { 0, 0, 0, 0 },
42602 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42603 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08c }
42604 },
42605/* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
42606 {
42607 { 0, 0, 0, 0 },
42608 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42609 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ac }
42610 },
42611/* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
42612 {
42613 { 0, 0, 0, 0 },
42614 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42615 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808c }
42616 },
42617/* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
42618 {
42619 { 0, 0, 0, 0 },
42620 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42621 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00c }
42622 },
42623/* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
42624 {
42625 { 0, 0, 0, 0 },
42626 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42627 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802c }
42628 },
42629/* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
42630 {
42631 { 0, 0, 0, 0 },
42632 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42633 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800c }
42634 },
42635/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42636 {
42637 { 0, 0, 0, 0 },
42638 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42639 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20c00 }
42640 },
42641/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42642 {
42643 { 0, 0, 0, 0 },
42644 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42645 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822c00 }
42646 },
42647/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
42648 {
42649 { 0, 0, 0, 0 },
42650 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42651 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820c00 }
42652 },
42653/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42654 {
42655 { 0, 0, 0, 0 },
42656 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42657 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40c00 }
42658 },
42659/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42660 {
42661 { 0, 0, 0, 0 },
42662 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42663 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842c00 }
42664 },
42665/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
42666 {
42667 { 0, 0, 0, 0 },
42668 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42669 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840c00 }
42670 },
42671/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42672 {
42673 { 0, 0, 0, 0 },
42674 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42675 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60c00 }
42676 },
42677/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42678 {
42679 { 0, 0, 0, 0 },
42680 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42681 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862c00 }
42682 },
42683/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
42684 {
42685 { 0, 0, 0, 0 },
42686 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42687 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860c00 }
42688 },
42689/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
42690 {
42691 { 0, 0, 0, 0 },
42692 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42693 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28c00 }
42694 },
42695/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
42696 {
42697 { 0, 0, 0, 0 },
42698 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42699 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ac00 }
42700 },
42701/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
42702 {
42703 { 0, 0, 0, 0 },
42704 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42705 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828c00 }
42706 },
42707/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
42708 {
42709 { 0, 0, 0, 0 },
42710 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42711 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48c00 }
42712 },
42713/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
42714 {
42715 { 0, 0, 0, 0 },
42716 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42717 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ac00 }
42718 },
42719/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
42720 {
42721 { 0, 0, 0, 0 },
42722 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42723 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848c00 }
42724 },
42725/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
42726 {
42727 { 0, 0, 0, 0 },
42728 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42729 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cc00 }
42730 },
42731/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
42732 {
42733 { 0, 0, 0, 0 },
42734 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42735 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ec00 }
42736 },
42737/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
42738 {
42739 { 0, 0, 0, 0 },
42740 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42741 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cc00 }
42742 },
42743/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
42744 {
42745 { 0, 0, 0, 0 },
42746 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42747 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cc00 }
42748 },
42749/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
42750 {
42751 { 0, 0, 0, 0 },
42752 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42753 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ec00 }
42754 },
42755/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
42756 {
42757 { 0, 0, 0, 0 },
42758 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42759 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cc00 }
42760 },
42761/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
42762 {
42763 { 0, 0, 0, 0 },
42764 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
42765 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cc00 }
42766 },
42767/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
42768 {
42769 { 0, 0, 0, 0 },
42770 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
42771 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ec00 }
42772 },
42773/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
42774 {
42775 { 0, 0, 0, 0 },
42776 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
42777 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cc00 }
42778 },
42779/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
42780 {
42781 { 0, 0, 0, 0 },
42782 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
42783 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68c00 }
42784 },
42785/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
42786 {
42787 { 0, 0, 0, 0 },
42788 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
42789 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ac00 }
42790 },
42791/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
42792 {
42793 { 0, 0, 0, 0 },
42794 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
42795 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868c00 }
42796 },
42797/* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
42798 {
42799 { 0, 0, 0, 0 },
42800 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
42801 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892f00 }
42802 },
42803/* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
42804 {
42805 { 0, 0, 0, 0 },
42806 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
42807 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181af00 }
42808 },
42809/* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
42810 {
42811 { 0, 0, 0, 0 },
42812 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42813 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812f00 }
42814 },
42815/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42816 {
42817 { 0, 0, 0, 0 },
42818 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42819 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832f00 }
42820 },
42821/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
42822 {
42823 { 0, 0, 0, 0 },
42824 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42825 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183af00 }
42826 },
42827/* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
42828 {
42829 { 0, 0, 0, 0 },
42830 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42831 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ef00 }
42832 },
42833/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42834 {
42835 { 0, 0, 0, 0 },
42836 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42837 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852f00 }
42838 },
42839/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
42840 {
42841 { 0, 0, 0, 0 },
42842 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42843 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185af00 }
42844 },
42845/* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
42846 {
42847 { 0, 0, 0, 0 },
42848 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42849 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ef00 }
42850 },
42851/* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
42852 {
42853 { 0, 0, 0, 0 },
42854 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
42855 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ef00 }
42856 },
42857/* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42858 {
42859 { 0, 0, 0, 0 },
42860 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42861 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872f00 }
42862 },
42863/* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
42864 {
42865 { 0, 0, 0, 0 },
42866 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
42867 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187af00 }
42868 },
42869/* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
42870 {
42871 { 0, 0, 0, 0 },
42872 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42873 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882f00 }
42874 },
42875/* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
42876 {
42877 { 0, 0, 0, 0 },
42878 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42879 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180af00 }
42880 },
42881/* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
42882 {
42883 { 0, 0, 0, 0 },
42884 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42885 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802f00 }
42886 },
42887/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42888 {
42889 { 0, 0, 0, 0 },
42890 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42891 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822f00 }
42892 },
42893/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
42894 {
42895 { 0, 0, 0, 0 },
42896 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42897 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182af00 }
42898 },
42899/* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
42900 {
42901 { 0, 0, 0, 0 },
42902 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42903 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ef00 }
42904 },
42905/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42906 {
42907 { 0, 0, 0, 0 },
42908 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42909 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842f00 }
42910 },
42911/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
42912 {
42913 { 0, 0, 0, 0 },
42914 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42915 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184af00 }
42916 },
42917/* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
42918 {
42919 { 0, 0, 0, 0 },
42920 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42921 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ef00 }
42922 },
42923/* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42924 {
42925 { 0, 0, 0, 0 },
42926 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
42927 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ef00 }
42928 },
42929/* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42930 {
42931 { 0, 0, 0, 0 },
42932 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42933 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862f00 }
42934 },
42935/* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42936 {
42937 { 0, 0, 0, 0 },
42938 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
42939 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186af00 }
42940 },
42941/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
42942 {
42943 { 0, 0, 0, 0 },
42944 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42945 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990d00 }
42946 },
42947/* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
42948 {
42949 { 0, 0, 0, 0 },
42950 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42951 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992d00 }
42952 },
42953/* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
42954 {
42955 { 0, 0, 0, 0 },
42956 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42957 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993d00 }
42958 },
42959/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
42960 {
42961 { 0, 0, 0, 0 },
42962 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42963 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918d00 }
42964 },
42965/* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
42966 {
42967 { 0, 0, 0, 0 },
42968 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42969 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ad00 }
42970 },
42971/* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
42972 {
42973 { 0, 0, 0, 0 },
42974 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42975 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bd00 }
42976 },
42977/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42978 {
42979 { 0, 0, 0, 0 },
42980 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42981 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910d00 }
42982 },
42983/* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
42984 {
42985 { 0, 0, 0, 0 },
42986 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42987 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912d00 }
42988 },
42989/* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
42990 {
42991 { 0, 0, 0, 0 },
42992 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42993 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913d00 }
42994 },
42995/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
42996 {
42997 { 0, 0, 0, 0 },
42998 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42999 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930d00 }
43000 },
43001/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43002 {
43003 { 0, 0, 0, 0 },
43004 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43005 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932d00 }
43006 },
43007/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43008 {
43009 { 0, 0, 0, 0 },
43010 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43011 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933d00 }
43012 },
43013/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
43014 {
43015 { 0, 0, 0, 0 },
43016 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43017 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950d00 }
43018 },
43019/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43020 {
43021 { 0, 0, 0, 0 },
43022 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43023 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952d00 }
43024 },
43025/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43026 {
43027 { 0, 0, 0, 0 },
43028 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43029 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953d00 }
43030 },
43031/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
43032 {
43033 { 0, 0, 0, 0 },
43034 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43035 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970d00 }
43036 },
43037/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43038 {
43039 { 0, 0, 0, 0 },
43040 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43041 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972d00 }
43042 },
43043/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43044 {
43045 { 0, 0, 0, 0 },
43046 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43047 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973d00 }
43048 },
43049/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
43050 {
43051 { 0, 0, 0, 0 },
43052 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43053 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938d00 }
43054 },
43055/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
43056 {
43057 { 0, 0, 0, 0 },
43058 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43059 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ad00 }
43060 },
43061/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
43062 {
43063 { 0, 0, 0, 0 },
43064 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43065 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bd00 }
43066 },
43067/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
43068 {
43069 { 0, 0, 0, 0 },
43070 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43071 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958d00 }
43072 },
43073/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
43074 {
43075 { 0, 0, 0, 0 },
43076 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43077 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ad00 }
43078 },
43079/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
43080 {
43081 { 0, 0, 0, 0 },
43082 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43083 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bd00 }
43084 },
43085/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
43086 {
43087 { 0, 0, 0, 0 },
43088 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43089 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cd00 }
43090 },
43091/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
43092 {
43093 { 0, 0, 0, 0 },
43094 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43095 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ed00 }
43096 },
43097/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
43098 {
43099 { 0, 0, 0, 0 },
43100 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43101 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fd00 }
43102 },
43103/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
43104 {
43105 { 0, 0, 0, 0 },
43106 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43107 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cd00 }
43108 },
43109/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
43110 {
43111 { 0, 0, 0, 0 },
43112 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43113 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ed00 }
43114 },
43115/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
43116 {
43117 { 0, 0, 0, 0 },
43118 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43119 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fd00 }
43120 },
43121/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
43122 {
43123 { 0, 0, 0, 0 },
43124 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
43125 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cd00 }
43126 },
43127/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
43128 {
43129 { 0, 0, 0, 0 },
43130 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43131 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ed00 }
43132 },
43133/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
43134 {
43135 { 0, 0, 0, 0 },
43136 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43137 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fd00 }
43138 },
43139/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
43140 {
43141 { 0, 0, 0, 0 },
43142 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
43143 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978d00 }
43144 },
43145/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
43146 {
43147 { 0, 0, 0, 0 },
43148 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
43149 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ad00 }
43150 },
43151/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
43152 {
43153 { 0, 0, 0, 0 },
43154 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
43155 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bd00 }
43156 },
43157/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
43158 {
43159 { 0, 0, 0, 0 },
43160 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43161 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90d00 }
43162 },
43163/* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
43164 {
43165 { 0, 0, 0, 0 },
43166 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43167 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92d00 }
43168 },
43169/* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
43170 {
43171 { 0, 0, 0, 0 },
43172 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43173 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93d00 }
43174 },
43175/* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
43176 {
43177 { 0, 0, 0, 0 },
43178 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
43179 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93d00 }
43180 },
43181/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
43182 {
43183 { 0, 0, 0, 0 },
43184 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43185 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18d00 }
43186 },
43187/* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
43188 {
43189 { 0, 0, 0, 0 },
43190 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43191 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ad00 }
43192 },
43193/* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
43194 {
43195 { 0, 0, 0, 0 },
43196 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43197 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bd00 }
43198 },
43199/* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
43200 {
43201 { 0, 0, 0, 0 },
43202 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
43203 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bd00 }
43204 },
43205/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43206 {
43207 { 0, 0, 0, 0 },
43208 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43209 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10d00 }
43210 },
43211/* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
43212 {
43213 { 0, 0, 0, 0 },
43214 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43215 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12d00 }
43216 },
43217/* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
43218 {
43219 { 0, 0, 0, 0 },
43220 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43221 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13d00 }
43222 },
43223/* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
43224 {
43225 { 0, 0, 0, 0 },
43226 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43227 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13d00 }
43228 },
43229/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
43230 {
43231 { 0, 0, 0, 0 },
43232 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43233 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30d00 }
43234 },
43235/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
43236 {
43237 { 0, 0, 0, 0 },
43238 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43239 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32d00 }
43240 },
43241/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
43242 {
43243 { 0, 0, 0, 0 },
43244 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43245 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33d00 }
43246 },
43247/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
43248 {
43249 { 0, 0, 0, 0 },
43250 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43251 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33d00 }
43252 },
43253/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
43254 {
43255 { 0, 0, 0, 0 },
43256 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43257 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50d00 }
43258 },
43259/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
43260 {
43261 { 0, 0, 0, 0 },
43262 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43263 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52d00 }
43264 },
43265/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
43266 {
43267 { 0, 0, 0, 0 },
43268 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43269 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53d00 }
43270 },
43271/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
43272 {
43273 { 0, 0, 0, 0 },
43274 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43275 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53d00 }
43276 },
43277/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
43278 {
43279 { 0, 0, 0, 0 },
43280 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43281 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70d00 }
43282 },
43283/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
43284 {
43285 { 0, 0, 0, 0 },
43286 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43287 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72d00 }
43288 },
43289/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
43290 {
43291 { 0, 0, 0, 0 },
43292 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43293 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73d00 }
43294 },
43295/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
43296 {
43297 { 0, 0, 0, 0 },
43298 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43299 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73d00 }
43300 },
43301/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
43302 {
43303 { 0, 0, 0, 0 },
43304 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43305 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38d00 }
43306 },
43307/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
43308 {
43309 { 0, 0, 0, 0 },
43310 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43311 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ad00 }
43312 },
43313/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
43314 {
43315 { 0, 0, 0, 0 },
43316 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43317 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bd00 }
43318 },
43319/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
43320 {
43321 { 0, 0, 0, 0 },
43322 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43323 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bd00 }
43324 },
43325/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
43326 {
43327 { 0, 0, 0, 0 },
43328 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43329 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58d00 }
43330 },
43331/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
43332 {
43333 { 0, 0, 0, 0 },
43334 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43335 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ad00 }
43336 },
43337/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
43338 {
43339 { 0, 0, 0, 0 },
43340 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43341 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bd00 }
43342 },
43343/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
43344 {
43345 { 0, 0, 0, 0 },
43346 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43347 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bd00 }
43348 },
43349/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
43350 {
43351 { 0, 0, 0, 0 },
43352 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43353 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cd00 }
43354 },
43355/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
43356 {
43357 { 0, 0, 0, 0 },
43358 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43359 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ed00 }
43360 },
43361/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
43362 {
43363 { 0, 0, 0, 0 },
43364 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43365 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fd00 }
43366 },
43367/* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
43368 {
43369 { 0, 0, 0, 0 },
43370 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43371 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fd00 }
43372 },
43373/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
43374 {
43375 { 0, 0, 0, 0 },
43376 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43377 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cd00 }
43378 },
43379/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
43380 {
43381 { 0, 0, 0, 0 },
43382 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43383 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ed00 }
43384 },
43385/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
43386 {
43387 { 0, 0, 0, 0 },
43388 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43389 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fd00 }
43390 },
43391/* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
43392 {
43393 { 0, 0, 0, 0 },
43394 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43395 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fd00 }
43396 },
43397/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
43398 {
43399 { 0, 0, 0, 0 },
43400 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
43401 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cd00 }
43402 },
43403/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
43404 {
43405 { 0, 0, 0, 0 },
43406 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43407 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ed00 }
43408 },
43409/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
43410 {
43411 { 0, 0, 0, 0 },
43412 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43413 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fd00 }
43414 },
43415/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
43416 {
43417 { 0, 0, 0, 0 },
43418 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
43419 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fd00 }
43420 },
43421/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
43422 {
43423 { 0, 0, 0, 0 },
43424 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
43425 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78d00 }
43426 },
43427/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
43428 {
43429 { 0, 0, 0, 0 },
43430 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43431 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ad00 }
43432 },
43433/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
43434 {
43435 { 0, 0, 0, 0 },
43436 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43437 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bd00 }
43438 },
43439/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
43440 {
43441 { 0, 0, 0, 0 },
43442 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
43443 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bd00 }
43444 },
43445/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
43446 {
43447 { 0, 0, 0, 0 },
43448 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43449 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90d00 }
43450 },
43451/* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
43452 {
43453 { 0, 0, 0, 0 },
43454 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
43455 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92d00 }
43456 },
43457/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
43458 {
43459 { 0, 0, 0, 0 },
43460 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43461 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18d00 }
43462 },
43463/* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
43464 {
43465 { 0, 0, 0, 0 },
43466 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
43467 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ad00 }
43468 },
43469/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43470 {
43471 { 0, 0, 0, 0 },
43472 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43473 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10d00 }
43474 },
43475/* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
43476 {
43477 { 0, 0, 0, 0 },
43478 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43479 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12d00 }
43480 },
43481/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
43482 {
43483 { 0, 0, 0, 0 },
43484 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43485 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30d00 }
43486 },
43487/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
43488 {
43489 { 0, 0, 0, 0 },
43490 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43491 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32d00 }
43492 },
43493/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
43494 {
43495 { 0, 0, 0, 0 },
43496 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43497 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50d00 }
43498 },
43499/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
43500 {
43501 { 0, 0, 0, 0 },
43502 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43503 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52d00 }
43504 },
43505/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
43506 {
43507 { 0, 0, 0, 0 },
43508 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43509 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70d00 }
43510 },
43511/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
43512 {
43513 { 0, 0, 0, 0 },
43514 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43515 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72d00 }
43516 },
43517/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
43518 {
43519 { 0, 0, 0, 0 },
43520 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
43521 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38d00 }
43522 },
43523/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
43524 {
43525 { 0, 0, 0, 0 },
43526 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
43527 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ad00 }
43528 },
43529/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
43530 {
43531 { 0, 0, 0, 0 },
43532 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
43533 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58d00 }
43534 },
43535/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
43536 {
43537 { 0, 0, 0, 0 },
43538 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
43539 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ad00 }
43540 },
43541/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
43542 {
43543 { 0, 0, 0, 0 },
43544 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
43545 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cd00 }
43546 },
43547/* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
43548 {
43549 { 0, 0, 0, 0 },
43550 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
43551 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ed00 }
43552 },
43553/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
43554 {
43555 { 0, 0, 0, 0 },
43556 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
43557 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cd00 }
43558 },
43559/* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
43560 {
43561 { 0, 0, 0, 0 },
43562 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
43563 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ed00 }
43564 },
43565/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
43566 {
43567 { 0, 0, 0, 0 },
43568 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
43569 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cd00 }
43570 },
43571/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
43572 {
43573 { 0, 0, 0, 0 },
43574 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
43575 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ed00 }
43576 },
43577/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
43578 {
43579 { 0, 0, 0, 0 },
43580 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
43581 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78d00 }
43582 },
43583/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
43584 {
43585 { 0, 0, 0, 0 },
43586 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
43587 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ad00 }
43588 },
43589/* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
43590 {
43591 { 0, 0, 0, 0 },
43592 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
43593 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90d }
43594 },
43595/* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
43596 {
43597 { 0, 0, 0, 0 },
43598 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
43599 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892d }
43600 },
43601/* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
43602 {
43603 { 0, 0, 0, 0 },
43604 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43605 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890d }
43606 },
43607/* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
43608 {
43609 { 0, 0, 0, 0 },
43610 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
43611 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18d }
43612 },
43613/* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
43614 {
43615 { 0, 0, 0, 0 },
43616 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
43617 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ad }
43618 },
43619/* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
43620 {
43621 { 0, 0, 0, 0 },
43622 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43623 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818d }
43624 },
43625/* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
43626 {
43627 { 0, 0, 0, 0 },
43628 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43629 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10d }
43630 },
43631/* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
43632 {
43633 { 0, 0, 0, 0 },
43634 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43635 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812d }
43636 },
43637/* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
43638 {
43639 { 0, 0, 0, 0 },
43640 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43641 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810d }
43642 },
43643/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
43644 {
43645 { 0, 0, 0, 0 },
43646 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43647 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30d00 }
43648 },
43649/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
43650 {
43651 { 0, 0, 0, 0 },
43652 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43653 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832d00 }
43654 },
43655/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
43656 {
43657 { 0, 0, 0, 0 },
43658 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43659 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830d00 }
43660 },
43661/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
43662 {
43663 { 0, 0, 0, 0 },
43664 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43665 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50d00 }
43666 },
43667/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
43668 {
43669 { 0, 0, 0, 0 },
43670 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43671 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852d00 }
43672 },
43673/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
43674 {
43675 { 0, 0, 0, 0 },
43676 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43677 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850d00 }
43678 },
43679/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
43680 {
43681 { 0, 0, 0, 0 },
43682 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43683 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70d00 }
43684 },
43685/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
43686 {
43687 { 0, 0, 0, 0 },
43688 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43689 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872d00 }
43690 },
43691/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
43692 {
43693 { 0, 0, 0, 0 },
43694 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43695 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870d00 }
43696 },
43697/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
43698 {
43699 { 0, 0, 0, 0 },
43700 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43701 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38d00 }
43702 },
43703/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
43704 {
43705 { 0, 0, 0, 0 },
43706 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43707 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ad00 }
43708 },
43709/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
43710 {
43711 { 0, 0, 0, 0 },
43712 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43713 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838d00 }
43714 },
43715/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
43716 {
43717 { 0, 0, 0, 0 },
43718 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43719 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58d00 }
43720 },
43721/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
43722 {
43723 { 0, 0, 0, 0 },
43724 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43725 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ad00 }
43726 },
43727/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
43728 {
43729 { 0, 0, 0, 0 },
43730 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43731 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858d00 }
43732 },
43733/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
43734 {
43735 { 0, 0, 0, 0 },
43736 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43737 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cd00 }
43738 },
43739/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
43740 {
43741 { 0, 0, 0, 0 },
43742 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43743 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ed00 }
43744 },
43745/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
43746 {
43747 { 0, 0, 0, 0 },
43748 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43749 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cd00 }
43750 },
43751/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
43752 {
43753 { 0, 0, 0, 0 },
43754 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43755 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cd00 }
43756 },
43757/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
43758 {
43759 { 0, 0, 0, 0 },
43760 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43761 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ed00 }
43762 },
43763/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
43764 {
43765 { 0, 0, 0, 0 },
43766 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43767 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cd00 }
43768 },
43769/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
43770 {
43771 { 0, 0, 0, 0 },
43772 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
43773 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cd00 }
43774 },
43775/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
43776 {
43777 { 0, 0, 0, 0 },
43778 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
43779 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ed00 }
43780 },
43781/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
43782 {
43783 { 0, 0, 0, 0 },
43784 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
43785 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cd00 }
43786 },
43787/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
43788 {
43789 { 0, 0, 0, 0 },
43790 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
43791 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78d00 }
43792 },
43793/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
43794 {
43795 { 0, 0, 0, 0 },
43796 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
43797 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ad00 }
43798 },
43799/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
43800 {
43801 { 0, 0, 0, 0 },
43802 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
43803 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878d00 }
43804 },
43805/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
43806 {
43807 { 0, 0, 0, 0 },
43808 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43809 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980d00 }
43810 },
43811/* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
43812 {
43813 { 0, 0, 0, 0 },
43814 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43815 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982d00 }
43816 },
43817/* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
43818 {
43819 { 0, 0, 0, 0 },
43820 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43821 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983d00 }
43822 },
43823/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
43824 {
43825 { 0, 0, 0, 0 },
43826 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43827 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908d00 }
43828 },
43829/* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
43830 {
43831 { 0, 0, 0, 0 },
43832 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43833 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ad00 }
43834 },
43835/* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
43836 {
43837 { 0, 0, 0, 0 },
43838 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43839 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bd00 }
43840 },
43841/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43842 {
43843 { 0, 0, 0, 0 },
43844 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43845 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900d00 }
43846 },
43847/* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
43848 {
43849 { 0, 0, 0, 0 },
43850 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43851 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902d00 }
43852 },
43853/* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
43854 {
43855 { 0, 0, 0, 0 },
43856 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43857 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903d00 }
43858 },
43859/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
43860 {
43861 { 0, 0, 0, 0 },
43862 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43863 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920d00 }
43864 },
43865/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43866 {
43867 { 0, 0, 0, 0 },
43868 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43869 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922d00 }
43870 },
43871/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43872 {
43873 { 0, 0, 0, 0 },
43874 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43875 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923d00 }
43876 },
43877/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
43878 {
43879 { 0, 0, 0, 0 },
43880 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43881 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940d00 }
43882 },
43883/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43884 {
43885 { 0, 0, 0, 0 },
43886 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43887 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942d00 }
43888 },
43889/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43890 {
43891 { 0, 0, 0, 0 },
43892 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43893 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943d00 }
43894 },
43895/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
43896 {
43897 { 0, 0, 0, 0 },
43898 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43899 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960d00 }
43900 },
43901/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43902 {
43903 { 0, 0, 0, 0 },
43904 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43905 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962d00 }
43906 },
43907/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43908 {
43909 { 0, 0, 0, 0 },
43910 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43911 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963d00 }
43912 },
43913/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
43914 {
43915 { 0, 0, 0, 0 },
43916 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43917 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928d00 }
43918 },
43919/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
43920 {
43921 { 0, 0, 0, 0 },
43922 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43923 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ad00 }
43924 },
43925/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
43926 {
43927 { 0, 0, 0, 0 },
43928 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43929 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bd00 }
43930 },
43931/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
43932 {
43933 { 0, 0, 0, 0 },
43934 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43935 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948d00 }
43936 },
43937/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
43938 {
43939 { 0, 0, 0, 0 },
43940 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43941 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ad00 }
43942 },
43943/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
43944 {
43945 { 0, 0, 0, 0 },
43946 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43947 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bd00 }
43948 },
43949/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
43950 {
43951 { 0, 0, 0, 0 },
43952 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43953 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cd00 }
43954 },
43955/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
43956 {
43957 { 0, 0, 0, 0 },
43958 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43959 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ed00 }
43960 },
43961/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
43962 {
43963 { 0, 0, 0, 0 },
43964 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43965 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fd00 }
43966 },
43967/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
43968 {
43969 { 0, 0, 0, 0 },
43970 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43971 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cd00 }
43972 },
43973/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
43974 {
43975 { 0, 0, 0, 0 },
43976 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43977 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ed00 }
43978 },
43979/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
43980 {
43981 { 0, 0, 0, 0 },
43982 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43983 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fd00 }
43984 },
43985/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
43986 {
43987 { 0, 0, 0, 0 },
43988 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
43989 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cd00 }
43990 },
43991/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
43992 {
43993 { 0, 0, 0, 0 },
43994 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43995 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ed00 }
43996 },
43997/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
43998 {
43999 { 0, 0, 0, 0 },
44000 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
44001 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fd00 }
44002 },
44003/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
44004 {
44005 { 0, 0, 0, 0 },
44006 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
44007 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968d00 }
44008 },
44009/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
44010 {
44011 { 0, 0, 0, 0 },
44012 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
44013 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ad00 }
44014 },
44015/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
44016 {
44017 { 0, 0, 0, 0 },
44018 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
44019 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bd00 }
44020 },
44021/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
44022 {
44023 { 0, 0, 0, 0 },
44024 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44025 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80d00 }
44026 },
44027/* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
44028 {
44029 { 0, 0, 0, 0 },
44030 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44031 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82d00 }
44032 },
44033/* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
44034 {
44035 { 0, 0, 0, 0 },
44036 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44037 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83d00 }
44038 },
44039/* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
44040 {
44041 { 0, 0, 0, 0 },
44042 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
44043 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83d00 }
44044 },
44045/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
44046 {
44047 { 0, 0, 0, 0 },
44048 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44049 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08d00 }
44050 },
44051/* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
44052 {
44053 { 0, 0, 0, 0 },
44054 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44055 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ad00 }
44056 },
44057/* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
44058 {
44059 { 0, 0, 0, 0 },
44060 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44061 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bd00 }
44062 },
44063/* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
44064 {
44065 { 0, 0, 0, 0 },
44066 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
44067 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bd00 }
44068 },
44069/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
44070 {
44071 { 0, 0, 0, 0 },
44072 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44073 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00d00 }
44074 },
44075/* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
44076 {
44077 { 0, 0, 0, 0 },
44078 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44079 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02d00 }
44080 },
44081/* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
44082 {
44083 { 0, 0, 0, 0 },
44084 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44085 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03d00 }
44086 },
44087/* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
44088 {
44089 { 0, 0, 0, 0 },
44090 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44091 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03d00 }
44092 },
44093/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
44094 {
44095 { 0, 0, 0, 0 },
44096 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44097 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20d00 }
44098 },
44099/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
44100 {
44101 { 0, 0, 0, 0 },
44102 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44103 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22d00 }
44104 },
44105/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
44106 {
44107 { 0, 0, 0, 0 },
44108 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44109 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23d00 }
44110 },
44111/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
44112 {
44113 { 0, 0, 0, 0 },
44114 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44115 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23d00 }
44116 },
44117/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
44118 {
44119 { 0, 0, 0, 0 },
44120 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44121 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40d00 }
44122 },
44123/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
44124 {
44125 { 0, 0, 0, 0 },
44126 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44127 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42d00 }
44128 },
44129/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
44130 {
44131 { 0, 0, 0, 0 },
44132 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44133 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43d00 }
44134 },
44135/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
44136 {
44137 { 0, 0, 0, 0 },
44138 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44139 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43d00 }
44140 },
44141/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
44142 {
44143 { 0, 0, 0, 0 },
44144 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44145 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60d00 }
44146 },
44147/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
44148 {
44149 { 0, 0, 0, 0 },
44150 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44151 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62d00 }
44152 },
44153/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
44154 {
44155 { 0, 0, 0, 0 },
44156 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44157 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63d00 }
44158 },
44159/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
44160 {
44161 { 0, 0, 0, 0 },
44162 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44163 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63d00 }
44164 },
44165/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
44166 {
44167 { 0, 0, 0, 0 },
44168 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44169 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28d00 }
44170 },
44171/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
44172 {
44173 { 0, 0, 0, 0 },
44174 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44175 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ad00 }
44176 },
44177/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
44178 {
44179 { 0, 0, 0, 0 },
44180 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44181 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bd00 }
44182 },
44183/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
44184 {
44185 { 0, 0, 0, 0 },
44186 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44187 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bd00 }
44188 },
44189/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
44190 {
44191 { 0, 0, 0, 0 },
44192 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44193 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48d00 }
44194 },
44195/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
44196 {
44197 { 0, 0, 0, 0 },
44198 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44199 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ad00 }
44200 },
44201/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
44202 {
44203 { 0, 0, 0, 0 },
44204 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44205 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bd00 }
44206 },
44207/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
44208 {
44209 { 0, 0, 0, 0 },
44210 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44211 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bd00 }
44212 },
44213/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
44214 {
44215 { 0, 0, 0, 0 },
44216 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44217 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cd00 }
44218 },
44219/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
44220 {
44221 { 0, 0, 0, 0 },
44222 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44223 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ed00 }
44224 },
44225/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
44226 {
44227 { 0, 0, 0, 0 },
44228 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44229 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fd00 }
44230 },
44231/* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
44232 {
44233 { 0, 0, 0, 0 },
44234 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44235 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fd00 }
44236 },
44237/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
44238 {
44239 { 0, 0, 0, 0 },
44240 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44241 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cd00 }
44242 },
44243/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
44244 {
44245 { 0, 0, 0, 0 },
44246 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44247 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ed00 }
44248 },
44249/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
44250 {
44251 { 0, 0, 0, 0 },
44252 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44253 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fd00 }
44254 },
44255/* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
44256 {
44257 { 0, 0, 0, 0 },
44258 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44259 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fd00 }
44260 },
44261/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
44262 {
44263 { 0, 0, 0, 0 },
44264 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
44265 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cd00 }
44266 },
44267/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
44268 {
44269 { 0, 0, 0, 0 },
44270 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
44271 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ed00 }
44272 },
44273/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
44274 {
44275 { 0, 0, 0, 0 },
44276 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
44277 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fd00 }
44278 },
44279/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
44280 {
44281 { 0, 0, 0, 0 },
44282 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
44283 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fd00 }
44284 },
44285/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
44286 {
44287 { 0, 0, 0, 0 },
44288 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
44289 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68d00 }
44290 },
44291/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
44292 {
44293 { 0, 0, 0, 0 },
44294 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
44295 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ad00 }
44296 },
44297/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
44298 {
44299 { 0, 0, 0, 0 },
44300 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
44301 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bd00 }
44302 },
44303/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
44304 {
44305 { 0, 0, 0, 0 },
44306 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
44307 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bd00 }
44308 },
44309/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
44310 {
44311 { 0, 0, 0, 0 },
44312 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44313 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80d00 }
44314 },
44315/* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
44316 {
44317 { 0, 0, 0, 0 },
44318 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
44319 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82d00 }
44320 },
44321/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
44322 {
44323 { 0, 0, 0, 0 },
44324 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44325 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08d00 }
44326 },
44327/* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
44328 {
44329 { 0, 0, 0, 0 },
44330 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
44331 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ad00 }
44332 },
44333/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
44334 {
44335 { 0, 0, 0, 0 },
44336 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44337 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00d00 }
44338 },
44339/* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
44340 {
44341 { 0, 0, 0, 0 },
44342 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44343 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02d00 }
44344 },
44345/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
44346 {
44347 { 0, 0, 0, 0 },
44348 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44349 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20d00 }
44350 },
44351/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
44352 {
44353 { 0, 0, 0, 0 },
44354 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44355 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22d00 }
44356 },
44357/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
44358 {
44359 { 0, 0, 0, 0 },
44360 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44361 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40d00 }
44362 },
44363/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
44364 {
44365 { 0, 0, 0, 0 },
44366 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44367 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42d00 }
44368 },
44369/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
44370 {
44371 { 0, 0, 0, 0 },
44372 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44373 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60d00 }
44374 },
44375/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
44376 {
44377 { 0, 0, 0, 0 },
44378 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44379 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62d00 }
44380 },
44381/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
44382 {
44383 { 0, 0, 0, 0 },
44384 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
44385 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28d00 }
44386 },
44387/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
44388 {
44389 { 0, 0, 0, 0 },
44390 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
44391 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ad00 }
44392 },
44393/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
44394 {
44395 { 0, 0, 0, 0 },
44396 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
44397 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48d00 }
44398 },
44399/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
44400 {
44401 { 0, 0, 0, 0 },
44402 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
44403 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ad00 }
44404 },
44405/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
44406 {
44407 { 0, 0, 0, 0 },
44408 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
44409 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cd00 }
44410 },
44411/* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
44412 {
44413 { 0, 0, 0, 0 },
44414 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
44415 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ed00 }
44416 },
44417/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
44418 {
44419 { 0, 0, 0, 0 },
44420 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
44421 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cd00 }
44422 },
44423/* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
44424 {
44425 { 0, 0, 0, 0 },
44426 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
44427 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ed00 }
44428 },
44429/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
44430 {
44431 { 0, 0, 0, 0 },
44432 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
44433 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cd00 }
44434 },
44435/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
44436 {
44437 { 0, 0, 0, 0 },
44438 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
44439 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ed00 }
44440 },
44441/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
44442 {
44443 { 0, 0, 0, 0 },
44444 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
44445 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68d00 }
44446 },
44447/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
44448 {
44449 { 0, 0, 0, 0 },
44450 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
44451 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ad00 }
44452 },
44453/* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
44454 {
44455 { 0, 0, 0, 0 },
44456 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44457 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80d }
44458 },
44459/* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
44460 {
44461 { 0, 0, 0, 0 },
44462 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44463 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882d }
44464 },
44465/* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
44466 {
44467 { 0, 0, 0, 0 },
44468 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44469 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880d }
44470 },
44471/* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
44472 {
44473 { 0, 0, 0, 0 },
44474 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44475 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08d }
44476 },
44477/* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
44478 {
44479 { 0, 0, 0, 0 },
44480 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44481 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ad }
44482 },
44483/* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
44484 {
44485 { 0, 0, 0, 0 },
44486 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44487 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808d }
44488 },
44489/* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
44490 {
44491 { 0, 0, 0, 0 },
44492 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44493 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00d }
44494 },
44495/* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
44496 {
44497 { 0, 0, 0, 0 },
44498 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44499 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802d }
44500 },
44501/* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
44502 {
44503 { 0, 0, 0, 0 },
44504 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44505 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800d }
44506 },
44507/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
44508 {
44509 { 0, 0, 0, 0 },
44510 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44511 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20d00 }
44512 },
44513/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
44514 {
44515 { 0, 0, 0, 0 },
44516 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44517 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822d00 }
44518 },
44519/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
44520 {
44521 { 0, 0, 0, 0 },
44522 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44523 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820d00 }
44524 },
44525/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
44526 {
44527 { 0, 0, 0, 0 },
44528 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44529 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40d00 }
44530 },
44531/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
44532 {
44533 { 0, 0, 0, 0 },
44534 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44535 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842d00 }
44536 },
44537/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
44538 {
44539 { 0, 0, 0, 0 },
44540 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44541 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840d00 }
44542 },
44543/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
44544 {
44545 { 0, 0, 0, 0 },
44546 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44547 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60d00 }
44548 },
44549/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
44550 {
44551 { 0, 0, 0, 0 },
44552 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44553 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862d00 }
44554 },
44555/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
44556 {
44557 { 0, 0, 0, 0 },
44558 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44559 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860d00 }
44560 },
44561/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
44562 {
44563 { 0, 0, 0, 0 },
44564 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44565 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28d00 }
44566 },
44567/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
44568 {
44569 { 0, 0, 0, 0 },
44570 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44571 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ad00 }
44572 },
44573/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
44574 {
44575 { 0, 0, 0, 0 },
44576 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44577 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828d00 }
44578 },
44579/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
44580 {
44581 { 0, 0, 0, 0 },
44582 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44583 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48d00 }
44584 },
44585/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
44586 {
44587 { 0, 0, 0, 0 },
44588 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44589 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ad00 }
44590 },
44591/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
44592 {
44593 { 0, 0, 0, 0 },
44594 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44595 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848d00 }
44596 },
44597/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
44598 {
44599 { 0, 0, 0, 0 },
44600 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44601 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cd00 }
44602 },
44603/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
44604 {
44605 { 0, 0, 0, 0 },
44606 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44607 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ed00 }
44608 },
44609/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
44610 {
44611 { 0, 0, 0, 0 },
44612 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44613 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cd00 }
44614 },
44615/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
44616 {
44617 { 0, 0, 0, 0 },
44618 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44619 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cd00 }
44620 },
44621/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
44622 {
44623 { 0, 0, 0, 0 },
44624 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44625 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ed00 }
44626 },
44627/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
44628 {
44629 { 0, 0, 0, 0 },
44630 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44631 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cd00 }
44632 },
44633/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
44634 {
44635 { 0, 0, 0, 0 },
44636 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
44637 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cd00 }
44638 },
44639/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
44640 {
44641 { 0, 0, 0, 0 },
44642 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
44643 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ed00 }
44644 },
44645/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
44646 {
44647 { 0, 0, 0, 0 },
44648 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
44649 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cd00 }
44650 },
44651/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
44652 {
44653 { 0, 0, 0, 0 },
44654 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
44655 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68d00 }
44656 },
44657/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
44658 {
44659 { 0, 0, 0, 0 },
44660 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
44661 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ad00 }
44662 },
44663/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
44664 {
44665 { 0, 0, 0, 0 },
44666 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
44667 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868d00 }
44668 },
44669/* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
44670 {
44671 { 0, 0, 0, 0 },
44672 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
44673 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893f00 }
44674 },
44675/* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
44676 {
44677 { 0, 0, 0, 0 },
44678 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
44679 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181bf00 }
44680 },
44681/* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
44682 {
44683 { 0, 0, 0, 0 },
44684 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44685 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813f00 }
44686 },
44687/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
44688 {
44689 { 0, 0, 0, 0 },
44690 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44691 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833f00 }
44692 },
44693/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
44694 {
44695 { 0, 0, 0, 0 },
44696 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44697 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183bf00 }
44698 },
44699/* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
44700 {
44701 { 0, 0, 0, 0 },
44702 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44703 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ff00 }
44704 },
44705/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
44706 {
44707 { 0, 0, 0, 0 },
44708 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44709 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853f00 }
44710 },
44711/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
44712 {
44713 { 0, 0, 0, 0 },
44714 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44715 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185bf00 }
44716 },
44717/* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
44718 {
44719 { 0, 0, 0, 0 },
44720 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44721 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ff00 }
44722 },
44723/* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
44724 {
44725 { 0, 0, 0, 0 },
44726 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
44727 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ff00 }
44728 },
44729/* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
44730 {
44731 { 0, 0, 0, 0 },
44732 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44733 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873f00 }
44734 },
44735/* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
44736 {
44737 { 0, 0, 0, 0 },
44738 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
44739 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187bf00 }
44740 },
44741/* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
44742 {
44743 { 0, 0, 0, 0 },
44744 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44745 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883f00 }
44746 },
44747/* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
44748 {
44749 { 0, 0, 0, 0 },
44750 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44751 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180bf00 }
44752 },
44753/* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
44754 {
44755 { 0, 0, 0, 0 },
44756 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44757 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803f00 }
44758 },
44759/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
44760 {
44761 { 0, 0, 0, 0 },
44762 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44763 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823f00 }
44764 },
44765/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
44766 {
44767 { 0, 0, 0, 0 },
44768 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44769 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182bf00 }
44770 },
44771/* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
44772 {
44773 { 0, 0, 0, 0 },
44774 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44775 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ff00 }
44776 },
44777/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
44778 {
44779 { 0, 0, 0, 0 },
44780 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44781 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843f00 }
44782 },
44783/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
44784 {
44785 { 0, 0, 0, 0 },
44786 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44787 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184bf00 }
44788 },
44789/* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
44790 {
44791 { 0, 0, 0, 0 },
44792 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44793 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ff00 }
44794 },
44795/* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
44796 {
44797 { 0, 0, 0, 0 },
44798 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
44799 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ff00 }
44800 },
44801/* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
44802 {
44803 { 0, 0, 0, 0 },
44804 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44805 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863f00 }
44806 },
44807/* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
44808 {
44809 { 0, 0, 0, 0 },
44810 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
44811 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186bf00 }
44812 },
a1a280bb 44813/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
49f58d10
JB		 44814 {
44815 { 0, 0, 0, 0 },
a1a280bb
DD		 44816 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44817 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x752c0000 }
49f58d10 44818 },
a1a280bb 44819/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
49f58d10
JB		 44820 {
44821 { 0, 0, 0, 0 },
a1a280bb
DD		 44822 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44823 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x752e0000 }
49f58d10 44824 },
a1a280bb 44825/* ste.w ${Dsp-16-u16},[a1a0] */
49f58d10
JB		 44826 {
44827 { 0, 0, 0, 0 },
a1a280bb
DD		 44828 { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44829 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x752f0000 }
44830 },
44831/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
44832 {
44833 { 0, 0, 0, 0 },
44834 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44835 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x751c0000 }
44836 },
44837/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
44838 {
44839 { 0, 0, 0, 0 },
44840 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44841 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x751e0000 }
44842 },
44843/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
44844 {
44845 { 0, 0, 0, 0 },
44846 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44847 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x751f0000 }
49f58d10
JB		 44848 },
44849/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
44850 {
44851 { 0, 0, 0, 0 },
44852 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 44853 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x750c0000 }
49f58d10
JB		 44854 },
44855/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
44856 {
44857 { 0, 0, 0, 0 },
44858 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 44859 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x750e0000 }
49f58d10
JB		 44860 },
44861/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
44862 {
44863 { 0, 0, 0, 0 },
44864 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
a1a280bb
DD		 44865 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x750f0000 }
44866 },
44867/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
44868 {
44869 { 0, 0, 0, 0 },
44870 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44871 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x752800 }
44872 },
44873/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
44874 {
44875 { 0, 0, 0, 0 },
44876 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44877 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x752a00 }
44878 },
44879/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
44880 {
44881 { 0, 0, 0, 0 },
44882 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44883 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x752b00 }
44884 },
44885/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
44886 {
44887 { 0, 0, 0, 0 },
44888 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44889 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75180000 }
44890 },
44891/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
44892 {
44893 { 0, 0, 0, 0 },
44894 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44895 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x751a0000 }
44896 },
44897/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
44898 {
44899 { 0, 0, 0, 0 },
44900 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44901 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x751b0000 }
44902 },
44903/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
44904 {
44905 { 0, 0, 0, 0 },
44906 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
44907 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75080000 }
44908 },
44909/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
44910 {
44911 { 0, 0, 0, 0 },
44912 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44913 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x750a0000 }
44914 },
44915/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
44916 {
44917 { 0, 0, 0, 0 },
44918 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44919 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x750b0000 }
44920 },
44921/* ste.w $Dst16RnHI,[a1a0] */
44922 {
44923 { 0, 0, 0, 0 },
44924 { { MNEM, ' ', OP (DST16RNHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44925 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7520 }
44926 },
44927/* ste.w $Dst16AnHI,[a1a0] */
44928 {
44929 { 0, 0, 0, 0 },
44930 { { MNEM, ' ', OP (DST16ANHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44931 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7524 }
44932 },
44933/* ste.w [$Dst16An],[a1a0] */
44934 {
44935 { 0, 0, 0, 0 },
44936 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44937 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7526 }
44938 },
44939/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
44940 {
44941 { 0, 0, 0, 0 },
44942 { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44943 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75100000 }
44944 },
44945/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
44946 {
44947 { 0, 0, 0, 0 },
44948 { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44949 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75140000 }
44950 },
44951/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
44952 {
44953 { 0, 0, 0, 0 },
44954 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44955 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75160000 }
49f58d10
JB		 44956 },
44957/* ste.w $Dst16RnHI,${Dsp-16-u20} */
44958 {
44959 { 0, 0, 0, 0 },
44960 { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 44961 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75000000 }
49f58d10
JB		 44962 },
44963/* ste.w $Dst16AnHI,${Dsp-16-u20} */
44964 {
44965 { 0, 0, 0, 0 },
44966 { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 44967 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75040000 }
49f58d10
JB		 44968 },
44969/* ste.w [$Dst16An],${Dsp-16-u20} */
44970 {
44971 { 0, 0, 0, 0 },
44972 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
a1a280bb 44973 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75060000 }
49f58d10 44974 },
a1a280bb 44975/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
49f58d10
JB		 44976 {
44977 { 0, 0, 0, 0 },
a1a280bb
DD		 44978 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44979 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x742c0000 }
49f58d10 44980 },
a1a280bb 44981/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
49f58d10
JB		 44982 {
44983 { 0, 0, 0, 0 },
a1a280bb
DD		 44984 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44985 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x742e0000 }
49f58d10 44986 },
a1a280bb 44987/* ste.b ${Dsp-16-u16},[a1a0] */
49f58d10
JB		 44988 {
44989 { 0, 0, 0, 0 },
a1a280bb
DD		 44990 { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44991 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x742f0000 }
44992 },
44993/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
44994 {
44995 { 0, 0, 0, 0 },
44996 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44997 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x741c0000 }
44998 },
44999/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
45000 {
45001 { 0, 0, 0, 0 },
45002 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
45003 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x741e0000 }
45004 },
45005/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
45006 {
45007 { 0, 0, 0, 0 },
45008 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
45009 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x741f0000 }
49f58d10
JB		 45010 },
45011/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
45012 {
45013 { 0, 0, 0, 0 },
45014 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 45015 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x740c0000 }
49f58d10
JB		 45016 },
45017/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
45018 {
45019 { 0, 0, 0, 0 },
45020 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
a1a280bb 45021 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x740e0000 }
49f58d10
JB		 45022 },
45023/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
45024 {
45025 { 0, 0, 0, 0 },
45026 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
a1a280bb
DD		 45027 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x740f0000 }
45028 },
45029/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
45030 {
45031 { 0, 0, 0, 0 },
45032 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45033 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x742800 }
45034 },
45035/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
45036 {
45037 { 0, 0, 0, 0 },
45038 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45039 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x742a00 }
45040 },
45041/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
45042 {
45043 { 0, 0, 0, 0 },
45044 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45045 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x742b00 }
45046 },
45047/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
45048 {
45049 { 0, 0, 0, 0 },
45050 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
45051 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74180000 }
45052 },
45053/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
45054 {
45055 { 0, 0, 0, 0 },
45056 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
45057 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x741a0000 }
45058 },
45059/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
45060 {
45061 { 0, 0, 0, 0 },
45062 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
45063 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x741b0000 }
45064 },
45065/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
45066 {
45067 { 0, 0, 0, 0 },
45068 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
45069 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74080000 }
45070 },
45071/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
45072 {
45073 { 0, 0, 0, 0 },
45074 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
45075 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x740a0000 }
45076 },
45077/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
45078 {
45079 { 0, 0, 0, 0 },
45080 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
45081 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x740b0000 }
45082 },
45083/* ste.b $Dst16RnQI,[a1a0] */
45084 {
45085 { 0, 0, 0, 0 },
45086 { { MNEM, ' ', OP (DST16RNQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45087 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7420 }
45088 },
45089/* ste.b $Dst16AnQI,[a1a0] */
45090 {
45091 { 0, 0, 0, 0 },
45092 { { MNEM, ' ', OP (DST16ANQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45093 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7424 }
45094 },
45095/* ste.b [$Dst16An],[a1a0] */
45096 {
45097 { 0, 0, 0, 0 },
45098 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45099 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7426 }
45100 },
45101/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
45102 {
45103 { 0, 0, 0, 0 },
45104 { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
45105 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74100000 }
45106 },
45107/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
45108 {
45109 { 0, 0, 0, 0 },
45110 { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
45111 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74140000 }
45112 },
45113/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
45114 {
45115 { 0, 0, 0, 0 },
45116 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
45117 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74160000 }
49f58d10
JB		 45118 },
45119/* ste.b $Dst16RnQI,${Dsp-16-u20} */
45120 {
45121 { 0, 0, 0, 0 },
45122 { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 45123 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74000000 }
49f58d10
JB		 45124 },
45125/* ste.b $Dst16AnQI,${Dsp-16-u20} */
45126 {
45127 { 0, 0, 0, 0 },
45128 { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), 0 } },
a1a280bb 45129 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74040000 }
49f58d10
JB		 45130 },
45131/* ste.b [$Dst16An],${Dsp-16-u20} */
45132 {
45133 { 0, 0, 0, 0 },
45134 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
a1a280bb 45135 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74060000 }
49f58d10 45136 },
a1a280bb 45137/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 45138 {
45139 { 0, 0, 0, 0 },
a1a280bb
DD		 45140 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45141 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75ac0000 }
49f58d10 45142 },
a1a280bb 45143/* lde.w [a1a0],${Dsp-16-u16}[sb] */
49f58d10
JB		 45144 {
45145 { 0, 0, 0, 0 },
a1a280bb
DD		 45146 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45147 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75ae0000 }
49f58d10 45148 },
a1a280bb 45149/* lde.w [a1a0],${Dsp-16-u16} */
49f58d10
JB		 45150 {
45151 { 0, 0, 0, 0 },
a1a280bb
DD		 45152 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45153 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75af0000 }
45154 },
45155/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
45156 {
45157 { 0, 0, 0, 0 },
45158 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45159 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x759c0000 }
45160 },
45161/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
45162 {
45163 { 0, 0, 0, 0 },
45164 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45165 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x759e0000 }
45166 },
45167/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
45168 {
45169 { 0, 0, 0, 0 },
45170 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45171 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x759f0000 }
49f58d10
JB		 45172 },
45173/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
45174 {
45175 { 0, 0, 0, 0 },
45176 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 45177 & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x758c0000 }
49f58d10
JB		 45178 },
45179/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
45180 {
45181 { 0, 0, 0, 0 },
45182 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 45183 & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x758e0000 }
49f58d10
JB		 45184 },
45185/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
45186 {
45187 { 0, 0, 0, 0 },
45188 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
a1a280bb
DD		 45189 & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x758f0000 }
45190 },
45191/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
45192 {
45193 { 0, 0, 0, 0 },
45194 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45195 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75a800 }
45196 },
45197/* lde.w [a1a0],${Dsp-16-u8}[sb] */
45198 {
45199 { 0, 0, 0, 0 },
45200 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45201 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75aa00 }
45202 },
45203/* lde.w [a1a0],${Dsp-16-s8}[fb] */
45204 {
45205 { 0, 0, 0, 0 },
45206 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45207 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75ab00 }
45208 },
45209/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
45210 {
45211 { 0, 0, 0, 0 },
45212 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45213 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75980000 }
45214 },
45215/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
45216 {
45217 { 0, 0, 0, 0 },
45218 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45219 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x759a0000 }
45220 },
45221/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
45222 {
45223 { 0, 0, 0, 0 },
45224 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45225 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x759b0000 }
45226 },
45227/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
45228 {
45229 { 0, 0, 0, 0 },
45230 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45231 & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75880000 }
45232 },
45233/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
45234 {
45235 { 0, 0, 0, 0 },
45236 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45237 & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x758a0000 }
45238 },
45239/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
45240 {
45241 { 0, 0, 0, 0 },
45242 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45243 & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x758b0000 }
45244 },
45245/* lde.w [a1a0],$Dst16RnHI */
45246 {
45247 { 0, 0, 0, 0 },
45248 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
45249 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75a0 }
45250 },
45251/* lde.w [a1a0],$Dst16AnHI */
45252 {
45253 { 0, 0, 0, 0 },
45254 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
45255 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75a4 }
45256 },
45257/* lde.w [a1a0],[$Dst16An] */
45258 {
45259 { 0, 0, 0, 0 },
45260 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45261 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75a6 }
45262 },
45263/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
45264 {
45265 { 0, 0, 0, 0 },
45266 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
45267 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75900000 }
45268 },
45269/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
45270 {
45271 { 0, 0, 0, 0 },
45272 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
45273 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75940000 }
45274 },
45275/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
45276 {
45277 { 0, 0, 0, 0 },
45278 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45279 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75960000 }
49f58d10
JB		 45280 },
45281/* lde.w ${Dsp-16-u20},$Dst16RnHI */
45282 {
45283 { 0, 0, 0, 0 },
45284 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNHI), 0 } },
a1a280bb 45285 & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75800000 }
49f58d10
JB		 45286 },
45287/* lde.w ${Dsp-16-u20},$Dst16AnHI */
45288 {
45289 { 0, 0, 0, 0 },
45290 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANHI), 0 } },
a1a280bb 45291 & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75840000 }
49f58d10
JB		 45292 },
45293/* lde.w ${Dsp-16-u20},[$Dst16An] */
45294 {
45295 { 0, 0, 0, 0 },
45296 { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 45297 & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75860000 }
49f58d10 45298 },
a1a280bb 45299/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 45300 {
45301 { 0, 0, 0, 0 },
a1a280bb
DD		 45302 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45303 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74ac0000 }
49f58d10 45304 },
a1a280bb 45305/* lde.b [a1a0],${Dsp-16-u16}[sb] */
49f58d10
JB		 45306 {
45307 { 0, 0, 0, 0 },
a1a280bb
DD		 45308 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45309 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74ae0000 }
49f58d10 45310 },
a1a280bb 45311/* lde.b [a1a0],${Dsp-16-u16} */
49f58d10
JB		 45312 {
45313 { 0, 0, 0, 0 },
a1a280bb
DD		 45314 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45315 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74af0000 }
45316 },
45317/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
45318 {
45319 { 0, 0, 0, 0 },
45320 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45321 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x749c0000 }
45322 },
45323/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
45324 {
45325 { 0, 0, 0, 0 },
45326 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45327 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x749e0000 }
45328 },
45329/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
45330 {
45331 { 0, 0, 0, 0 },
45332 { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45333 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x749f0000 }
49f58d10
JB		 45334 },
45335/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
45336 {
45337 { 0, 0, 0, 0 },
45338 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
a1a280bb 45339 & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x748c0000 }
49f58d10
JB		 45340 },
45341/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
45342 {
45343 { 0, 0, 0, 0 },
45344 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
a1a280bb 45345 & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x748e0000 }
49f58d10
JB		 45346 },
45347/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
45348 {
45349 { 0, 0, 0, 0 },
45350 { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
a1a280bb
DD		 45351 & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x748f0000 }
45352 },
45353/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
45354 {
45355 { 0, 0, 0, 0 },
45356 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45357 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74a800 }
45358 },
45359/* lde.b [a1a0],${Dsp-16-u8}[sb] */
45360 {
45361 { 0, 0, 0, 0 },
45362 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45363 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74aa00 }
45364 },
45365/* lde.b [a1a0],${Dsp-16-s8}[fb] */
45366 {
45367 { 0, 0, 0, 0 },
45368 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45369 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74ab00 }
45370 },
45371/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
45372 {
45373 { 0, 0, 0, 0 },
45374 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45375 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74980000 }
45376 },
45377/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
45378 {
45379 { 0, 0, 0, 0 },
45380 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45381 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x749a0000 }
45382 },
45383/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
45384 {
45385 { 0, 0, 0, 0 },
45386 { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45387 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x749b0000 }
45388 },
45389/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
45390 {
45391 { 0, 0, 0, 0 },
45392 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45393 & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74880000 }
45394 },
45395/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
45396 {
45397 { 0, 0, 0, 0 },
45398 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45399 & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x748a0000 }
45400 },
45401/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
45402 {
45403 { 0, 0, 0, 0 },
45404 { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45405 & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x748b0000 }
45406 },
45407/* lde.b [a1a0],$Dst16RnQI */
45408 {
45409 { 0, 0, 0, 0 },
45410 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
45411 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74a0 }
45412 },
45413/* lde.b [a1a0],$Dst16AnQI */
45414 {
45415 { 0, 0, 0, 0 },
45416 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
45417 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74a4 }
45418 },
45419/* lde.b [a1a0],[$Dst16An] */
45420 {
45421 { 0, 0, 0, 0 },
45422 { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45423 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74a6 }
45424 },
45425/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
45426 {
45427 { 0, 0, 0, 0 },
45428 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
45429 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74900000 }
45430 },
45431/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
45432 {
45433 { 0, 0, 0, 0 },
45434 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
45435 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74940000 }
45436 },
45437/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
45438 {
45439 { 0, 0, 0, 0 },
45440 { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45441 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74960000 }
49f58d10
JB		 45442 },
45443/* lde.b ${Dsp-16-u20},$Dst16RnQI */
45444 {
45445 { 0, 0, 0, 0 },
45446 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNQI), 0 } },
a1a280bb 45447 & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74800000 }
49f58d10
JB		 45448 },
45449/* lde.b ${Dsp-16-u20},$Dst16AnQI */
45450 {
45451 { 0, 0, 0, 0 },
45452 { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANQI), 0 } },
a1a280bb 45453 & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74840000 }
49f58d10
JB		 45454 },
45455/* lde.b ${Dsp-16-u20},[$Dst16An] */
45456 {
45457 { 0, 0, 0, 0 },
45458 { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
a1a280bb 45459 & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74860000 }
49f58d10
JB		 45460 },
45461/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
45462 {
45463 { 0, 0, 0, 0 },
45464 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32RNPREFIXEDSI), 0 } },
45465 & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d910 }
45466 },
45467/* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
45468 {
45469 { 0, 0, 0, 0 },
45470 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32ANPREFIXEDSI), 0 } },
45471 & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d190 }
45472 },
45473/* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
45474 {
45475 { 0, 0, 0, 0 },
45476 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
45477 & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d110 }
45478 },
45479/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
45480 {
45481 { 0, 0, 0, 0 },
45482 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
45483 & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d31000 }
45484 },
45485/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
45486 {
45487 { 0, 0, 0, 0 },
45488 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
45489 & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d51000 }
45490 },
45491/* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
45492 {
45493 { 0, 0, 0, 0 },
45494 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
45495 & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d71000 }
45496 },
45497/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
45498 {
45499 { 0, 0, 0, 0 },
45500 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
45501 & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d39000 }
45502 },
45503/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
45504 {
45505 { 0, 0, 0, 0 },
45506 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
45507 & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d59000 }
45508 },
45509/* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
45510 {
45511 { 0, 0, 0, 0 },
45512 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
45513 & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3d000 }
45514 },
45515/* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
45516 {
45517 { 0, 0, 0, 0 },
45518 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
45519 & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5d000 }
45520 },
45521/* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
45522 {
45523 { 0, 0, 0, 0 },
45524 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), 0 } },
45525 & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7d000 }
45526 },
45527/* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
45528 {
45529 { 0, 0, 0, 0 },
45530 { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), 0 } },
45531 & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d79000 }
45532 },
45533/* stc ${cr2-32},$Dst32RnUnprefixedSI */
45534 {
45535 { 0, 0, 0, 0 },
45536 { { MNEM, ' ', OP (CR2_32), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
45537 & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd910 }
45538 },
45539/* stc ${cr2-32},$Dst32AnUnprefixedSI */
45540 {
45541 { 0, 0, 0, 0 },
45542 { { MNEM, ' ', OP (CR2_32), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
45543 & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd190 }
45544 },
45545/* stc ${cr2-32},[$Dst32AnUnprefixed] */
45546 {
45547 { 0, 0, 0, 0 },
45548 { { MNEM, ' ', OP (CR2_32), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45549 & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd110 }
45550 },
45551/* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
45552 {
45553 { 0, 0, 0, 0 },
45554 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45555 & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd31000 }
45556 },
45557/* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
45558 {
45559 { 0, 0, 0, 0 },
45560 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45561 & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5100000 }
45562 },
45563/* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
45564 {
45565 { 0, 0, 0, 0 },
45566 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45567 & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7100000 }
45568 },
45569/* stc ${cr2-32},${Dsp-16-u8}[sb] */
45570 {
45571 { 0, 0, 0, 0 },
45572 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45573 & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd39000 }
45574 },
45575/* stc ${cr2-32},${Dsp-16-u16}[sb] */
45576 {
45577 { 0, 0, 0, 0 },
45578 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45579 & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5900000 }
45580 },
45581/* stc ${cr2-32},${Dsp-16-s8}[fb] */
45582 {
45583 { 0, 0, 0, 0 },
45584 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45585 & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3d000 }
45586 },
45587/* stc ${cr2-32},${Dsp-16-s16}[fb] */
45588 {
45589 { 0, 0, 0, 0 },
45590 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
45591 & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5d00000 }
45592 },
45593/* stc ${cr2-32},${Dsp-16-u16} */
45594 {
45595 { 0, 0, 0, 0 },
45596 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), 0 } },
45597 & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7d00000 }
45598 },
45599/* stc ${cr2-32},${Dsp-16-u24} */
45600 {
45601 { 0, 0, 0, 0 },
45602 { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), 0 } },
45603 & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7900000 }
45604 },
45605/* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
45606 {
45607 { 0, 0, 0, 0 },
45608 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32RNPREFIXEDHI), 0 } },
45609 & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d918 }
45610 },
45611/* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
45612 {
45613 { 0, 0, 0, 0 },
45614 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32ANPREFIXEDHI), 0 } },
45615 & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d198 }
45616 },
45617/* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
45618 {
45619 { 0, 0, 0, 0 },
45620 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
45621 & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d118 }
45622 },
45623/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
45624 {
45625 { 0, 0, 0, 0 },
45626 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
45627 & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d31800 }
45628 },
45629/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
45630 {
45631 { 0, 0, 0, 0 },
45632 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
45633 & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d51800 }
45634 },
45635/* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
45636 {
45637 { 0, 0, 0, 0 },
45638 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
45639 & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d71800 }
45640 },
45641/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
45642 {
45643 { 0, 0, 0, 0 },
45644 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
45645 & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d39800 }
45646 },
45647/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
45648 {
45649 { 0, 0, 0, 0 },
45650 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
45651 & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d59800 }
45652 },
45653/* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
45654 {
45655 { 0, 0, 0, 0 },
45656 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
45657 & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3d800 }
45658 },
45659/* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
45660 {
45661 { 0, 0, 0, 0 },
45662 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
45663 & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5d800 }
45664 },
45665/* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
45666 {
45667 { 0, 0, 0, 0 },
45668 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), 0 } },
45669 & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7d800 }
45670 },
45671/* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
45672 {
45673 { 0, 0, 0, 0 },
45674 { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), 0 } },
45675 & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d79800 }
45676 },
45677/* stc pc,$Dst16RnHI */
45678 {
45679 { 0, 0, 0, 0 },
45680 { { MNEM, ' ', 'p', 'c', ',', OP (DST16RNHI), 0 } },
45681 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7cc0 }
45682 },
45683/* stc pc,$Dst16AnHI */
45684 {
45685 { 0, 0, 0, 0 },
45686 { { MNEM, ' ', 'p', 'c', ',', OP (DST16ANHI), 0 } },
45687 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7cc4 }
45688 },
45689/* stc pc,[$Dst16An] */
45690 {
45691 { 0, 0, 0, 0 },
45692 { { MNEM, ' ', 'p', 'c', ',', '[', OP (DST16AN), ']', 0 } },
45693 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7cc6 }
45694 },
45695/* stc pc,${Dsp-16-u8}[$Dst16An] */
45696 {
45697 { 0, 0, 0, 0 },
45698 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45699 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7cc800 }
45700 },
45701/* stc pc,${Dsp-16-u16}[$Dst16An] */
45702 {
45703 { 0, 0, 0, 0 },
45704 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45705 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7ccc0000 }
45706 },
45707/* stc pc,${Dsp-16-u8}[sb] */
45708 {
45709 { 0, 0, 0, 0 },
45710 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45711 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7cca00 }
45712 },
45713/* stc pc,${Dsp-16-u16}[sb] */
45714 {
45715 { 0, 0, 0, 0 },
45716 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45717 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7cce0000 }
45718 },
45719/* stc pc,${Dsp-16-s8}[fb] */
45720 {
45721 { 0, 0, 0, 0 },
45722 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45723 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7ccb00 }
45724 },
45725/* stc pc,${Dsp-16-u16} */
45726 {
45727 { 0, 0, 0, 0 },
45728 { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), 0 } },
45729 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7ccf0000 }
45730 },
45731/* stc ${cr16},$Dst16RnHI */
45732 {
45733 { 0, 0, 0, 0 },
45734 { { MNEM, ' ', OP (CR16), ',', OP (DST16RNHI), 0 } },
45735 & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7b80 }
45736 },
45737/* stc ${cr16},$Dst16AnHI */
45738 {
45739 { 0, 0, 0, 0 },
45740 { { MNEM, ' ', OP (CR16), ',', OP (DST16ANHI), 0 } },
45741 & ifmt_stc16_src_dst16_An_direct_HI, { 0x7b84 }
45742 },
45743/* stc ${cr16},[$Dst16An] */
45744 {
45745 { 0, 0, 0, 0 },
45746 { { MNEM, ' ', OP (CR16), ',', '[', OP (DST16AN), ']', 0 } },
45747 & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7b86 }
45748 },
45749/* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
45750 {
45751 { 0, 0, 0, 0 },
45752 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45753 & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7b8800 }
45754 },
45755/* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
45756 {
45757 { 0, 0, 0, 0 },
45758 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45759 & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7b8c0000 }
45760 },
45761/* stc ${cr16},${Dsp-16-u8}[sb] */
45762 {
45763 { 0, 0, 0, 0 },
45764 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45765 & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7b8a00 }
45766 },
45767/* stc ${cr16},${Dsp-16-u16}[sb] */
45768 {
45769 { 0, 0, 0, 0 },
45770 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45771 & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7b8e0000 }
45772 },
45773/* stc ${cr16},${Dsp-16-s8}[fb] */
45774 {
45775 { 0, 0, 0, 0 },
45776 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45777 & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7b8b00 }
45778 },
45779/* stc ${cr16},${Dsp-16-u16} */
45780 {
45781 { 0, 0, 0, 0 },
45782 { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), 0 } },
45783 & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7b8f0000 }
45784 },
45785/* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
45786 {
45787 { 0, 0, 0, 0 },
45788 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } },
45789 & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d900 }
45790 },
45791/* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
45792 {
45793 { 0, 0, 0, 0 },
45794 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } },
45795 & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d180 }
45796 },
45797/* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
45798 {
45799 { 0, 0, 0, 0 },
45800 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45801 & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d100 }
45802 },
45803/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45804 {
45805 { 0, 0, 0, 0 },
45806 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45807 & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d30000 }
45808 },
45809/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45810 {
45811 { 0, 0, 0, 0 },
45812 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45813 & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d50000 }
45814 },
45815/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45816 {
45817 { 0, 0, 0, 0 },
45818 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45819 & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d70000 }
45820 },
45821/* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
45822 {
45823 { 0, 0, 0, 0 },
45824 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45825 & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d38000 }
45826 },
45827/* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
45828 {
45829 { 0, 0, 0, 0 },
45830 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45831 & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d58000 }
45832 },
45833/* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
45834 {
45835 { 0, 0, 0, 0 },
45836 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45837 & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3c000 }
45838 },
45839/* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
45840 {
45841 { 0, 0, 0, 0 },
45842 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45843 & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5c000 }
45844 },
45845/* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
45846 {
45847 { 0, 0, 0, 0 },
45848 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR3_PREFIXED_32), 0 } },
45849 & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7c000 }
45850 },
45851/* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
45852 {
45853 { 0, 0, 0, 0 },
45854 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR3_PREFIXED_32), 0 } },
45855 & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d78000 }
45856 },
45857/* ldc $Dst32RnUnprefixedSI,${cr2-32} */
45858 {
45859 { 0, 0, 0, 0 },
45860 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), ',', OP (CR2_32), 0 } },
45861 & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd900 }
45862 },
45863/* ldc $Dst32AnUnprefixedSI,${cr2-32} */
45864 {
45865 { 0, 0, 0, 0 },
45866 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), ',', OP (CR2_32), 0 } },
45867 & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd180 }
45868 },
45869/* ldc [$Dst32AnUnprefixed],${cr2-32} */
45870 {
45871 { 0, 0, 0, 0 },
45872 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45873 & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd100 }
45874 },
45875/* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
45876 {
45877 { 0, 0, 0, 0 },
45878 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45879 & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd30000 }
45880 },
45881/* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
45882 {
45883 { 0, 0, 0, 0 },
45884 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45885 & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5000000 }
45886 },
45887/* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
45888 {
45889 { 0, 0, 0, 0 },
45890 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45891 & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7000000 }
45892 },
45893/* ldc ${Dsp-16-u8}[sb],${cr2-32} */
45894 {
45895 { 0, 0, 0, 0 },
45896 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } },
45897 & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd38000 }
45898 },
45899/* ldc ${Dsp-16-u16}[sb],${cr2-32} */
45900 {
45901 { 0, 0, 0, 0 },
45902 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } },
45903 & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5800000 }
45904 },
45905/* ldc ${Dsp-16-s8}[fb],${cr2-32} */
45906 {
45907 { 0, 0, 0, 0 },
45908 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } },
45909 & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3c000 }
45910 },
45911/* ldc ${Dsp-16-s16}[fb],${cr2-32} */
45912 {
45913 { 0, 0, 0, 0 },
45914 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } },
45915 & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5c00000 }
45916 },
45917/* ldc ${Dsp-16-u16},${cr2-32} */
45918 {
45919 { 0, 0, 0, 0 },
45920 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR2_32), 0 } },
45921 & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7c00000 }
45922 },
45923/* ldc ${Dsp-16-u24},${cr2-32} */
45924 {
45925 { 0, 0, 0, 0 },
45926 { { MNEM, ' ', OP (DSP_16_U24), ',', OP (CR2_32), 0 } },
45927 & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7800000 }
45928 },
45929/* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
45930 {
45931 { 0, 0, 0, 0 },
45932 { { MNEM, ' ', OP (DST32RNPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } },
45933 & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d908 }
45934 },
45935/* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
45936 {
45937 { 0, 0, 0, 0 },
45938 { { MNEM, ' ', OP (DST32ANPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } },
45939 & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d188 }
45940 },
45941/* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
45942 {
45943 { 0, 0, 0, 0 },
45944 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45945 & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d108 }
45946 },
45947/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45948 {
45949 { 0, 0, 0, 0 },
45950 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45951 & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d30800 }
45952 },
45953/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45954 {
45955 { 0, 0, 0, 0 },
45956 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45957 & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d50800 }
45958 },
45959/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45960 {
45961 { 0, 0, 0, 0 },
45962 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45963 & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d70800 }
45964 },
45965/* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
45966 {
45967 { 0, 0, 0, 0 },
45968 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45969 & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d38800 }
45970 },
45971/* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
45972 {
45973 { 0, 0, 0, 0 },
45974 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45975 & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d58800 }
45976 },
45977/* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
45978 {
45979 { 0, 0, 0, 0 },
45980 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45981 & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3c800 }
45982 },
45983/* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
45984 {
45985 { 0, 0, 0, 0 },
45986 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45987 & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5c800 }
45988 },
45989/* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
45990 {
45991 { 0, 0, 0, 0 },
45992 { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR1_PREFIXED_32), 0 } },
45993 & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7c800 }
45994 },
45995/* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
45996 {
45997 { 0, 0, 0, 0 },
45998 { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR1_PREFIXED_32), 0 } },
45999 & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d78800 }
46000 },
46001/* ldc $Dst16RnHI,${cr16} */
46002 {
46003 { 0, 0, 0, 0 },
46004 { { MNEM, ' ', OP (DST16RNHI), ',', OP (CR16), 0 } },
46005 & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7a80 }
46006 },
46007/* ldc $Dst16AnHI,${cr16} */
46008 {
46009 { 0, 0, 0, 0 },
46010 { { MNEM, ' ', OP (DST16ANHI), ',', OP (CR16), 0 } },
46011 & ifmt_stc16_src_dst16_An_direct_HI, { 0x7a84 }
46012 },
46013/* ldc [$Dst16An],${cr16} */
46014 {
46015 { 0, 0, 0, 0 },
46016 { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
46017 & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7a86 }
46018 },
46019/* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
46020 {
46021 { 0, 0, 0, 0 },
46022 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
46023 & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7a8800 }
46024 },
46025/* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
46026 {
46027 { 0, 0, 0, 0 },
46028 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
46029 & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7a8c0000 }
46030 },
46031/* ldc ${Dsp-16-u8}[sb],${cr16} */
46032 {
46033 { 0, 0, 0, 0 },
46034 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR16), 0 } },
46035 & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7a8a00 }
46036 },
46037/* ldc ${Dsp-16-u16}[sb],${cr16} */
46038 {
46039 { 0, 0, 0, 0 },
46040 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR16), 0 } },
46041 & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7a8e0000 }
46042 },
46043/* ldc ${Dsp-16-s8}[fb],${cr16} */
46044 {
46045 { 0, 0, 0, 0 },
46046 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR16), 0 } },
46047 & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7a8b00 }
46048 },
46049/* ldc ${Dsp-16-u16},${cr16} */
46050 {
46051 { 0, 0, 0, 0 },
46052 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR16), 0 } },
46053 & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7a8f0000 }
46054 },
75b06e7b 46055/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 46056 {
46057 { 0, 0, 0, 0 },
46058 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46059 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 }
46060 },
75b06e7b 46061/* jsri.a ${Dsp-16-u24} */
49f58d10
JB		 46062 {
46063 { 0, 0, 0, 0 },
46064 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46065 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 }
46066 },
eda87aba
DD		 46067/* jsri.a $Dst32RnUnprefixedSI */
46068 {
46069 { 0, 0, 0, 0 },
46070 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
46071 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x9801 }
46072 },
46073/* jsri.a $Dst32AnUnprefixedSI */
46074 {
46075 { 0, 0, 0, 0 },
46076 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
46077 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x9081 }
46078 },
46079/* jsri.a [$Dst32AnUnprefixed] */
46080 {
46081 { 0, 0, 0, 0 },
46082 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46083 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x9001 }
46084 },
46085/* jsri.a $Dst16RnSI */
46086 {
46087 { 0, 0, 0, 0 },
46088 { { MNEM, ' ', OP (DST16RNSI), 0 } },
46089 & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d10 }
46090 },
46091/* jsri.a $Dst16AnSI */
46092 {
46093 { 0, 0, 0, 0 },
46094 { { MNEM, ' ', OP (DST16ANSI), 0 } },
46095 & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d14 }
46096 },
46097/* jsri.a [$Dst16An] */
46098 {
46099 { 0, 0, 0, 0 },
46100 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46101 & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 }
46102 },
49f58d10
JB		 46103/* jsri.a ${Dsp-16-u16}[sb] */
46104 {
46105 { 0, 0, 0, 0 },
46106 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46107 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94810000 }
46108 },
46109/* jsri.a ${Dsp-16-s16}[fb] */
46110 {
46111 { 0, 0, 0, 0 },
46112 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46113 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94c10000 }
46114 },
46115/* jsri.a ${Dsp-16-u16} */
46116 {
46117 { 0, 0, 0, 0 },
46118 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46119 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x96c10000 }
46120 },
49f58d10
JB		 46121/* jsri.a ${Dsp-16-u16}[sb] */
46122 {
46123 { 0, 0, 0, 0 },
46124 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75b06e7b 46125 & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d1e0000 }
49f58d10
JB		 46126 },
46127/* jsri.a ${Dsp-16-u16} */
46128 {
46129 { 0, 0, 0, 0 },
46130 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
75b06e7b 46131 & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d1f0000 }
49f58d10
JB		 46132 },
46133/* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46134 {
46135 { 0, 0, 0, 0 },
46136 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46137 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x920100 }
46138 },
46139/* jsri.a ${Dsp-16-u8}[sb] */
46140 {
46141 { 0, 0, 0, 0 },
46142 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46143 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x928100 }
46144 },
46145/* jsri.a ${Dsp-16-s8}[fb] */
46146 {
46147 { 0, 0, 0, 0 },
46148 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46149 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92c100 }
46150 },
46151/* jsri.a ${Dsp-16-u8}[$Dst16An] */
46152 {
46153 { 0, 0, 0, 0 },
46154 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46155 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d1800 }
46156 },
46157/* jsri.a ${Dsp-16-u8}[sb] */
46158 {
46159 { 0, 0, 0, 0 },
46160 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46161 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d1a00 }
46162 },
46163/* jsri.a ${Dsp-16-s8}[fb] */
46164 {
46165 { 0, 0, 0, 0 },
46166 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46167 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d1b00 }
46168 },
75b06e7b 46169/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 46170 {
46171 { 0, 0, 0, 0 },
eda87aba 46172 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75b06e7b 46173 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 }
49f58d10 46174 },
75b06e7b 46175/* jsri.a ${Dsp-16-u24} */
49f58d10
JB		 46176 {
46177 { 0, 0, 0, 0 },
eda87aba 46178 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
75b06e7b
DD		 46179 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 }
46180 },
46181/* jsri.a ${Dsp-16-u20}[$Dst16An] */
46182 {
46183 { 0, 0, 0, 0 },
46184 { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } },
46185 & ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI, { 0x7d1c0000 }
49f58d10 46186 },
eda87aba 46187/* jsri.w $Dst32RnUnprefixedHI */
49f58d10
JB		 46188 {
46189 { 0, 0, 0, 0 },
eda87aba
DD		 46190 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46191 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc91f }
49f58d10 46192 },
eda87aba 46193/* jsri.w $Dst32AnUnprefixedHI */
49f58d10
JB		 46194 {
46195 { 0, 0, 0, 0 },
eda87aba
DD		 46196 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46197 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc19f }
49f58d10 46198 },
eda87aba 46199/* jsri.w [$Dst32AnUnprefixed] */
49f58d10
JB		 46200 {
46201 { 0, 0, 0, 0 },
eda87aba
DD		 46202 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46203 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc11f }
49f58d10 46204 },
eda87aba 46205/* jsri.w $Dst16RnHI */
49f58d10
JB		 46206 {
46207 { 0, 0, 0, 0 },
eda87aba
DD		 46208 { { MNEM, ' ', OP (DST16RNHI), 0 } },
46209 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d30 }
49f58d10 46210 },
eda87aba 46211/* jsri.w $Dst16AnHI */
49f58d10
JB		 46212 {
46213 { 0, 0, 0, 0 },
eda87aba
DD		 46214 { { MNEM, ' ', OP (DST16ANHI), 0 } },
46215 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d34 }
49f58d10 46216 },
eda87aba 46217/* jsri.w [$Dst16An] */
49f58d10
JB		 46218 {
46219 { 0, 0, 0, 0 },
eda87aba
DD		 46220 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46221 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 }
49f58d10 46222 },
75b06e7b 46223/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 46224 {
46225 { 0, 0, 0, 0 },
75b06e7b
DD		 46226 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46227 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31f00 }
46228 },
46229/* jsri.w ${Dsp-16-u8}[sb] */
46230 {
46231 { 0, 0, 0, 0 },
46232 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46233 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39f00 }
46234 },
46235/* jsri.w ${Dsp-16-s8}[fb] */
46236 {
46237 { 0, 0, 0, 0 },
46238 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46239 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3df00 }
46240 },
46241/* jsri.w ${Dsp-16-u8}[$Dst16An] */
46242 {
46243 { 0, 0, 0, 0 },
46244 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46245 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d3800 }
46246 },
46247/* jsri.w ${Dsp-16-u8}[sb] */
46248 {
46249 { 0, 0, 0, 0 },
46250 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46251 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d3a00 }
46252 },
46253/* jsri.w ${Dsp-16-s8}[fb] */
46254 {
46255 { 0, 0, 0, 0 },
46256 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46257 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 }
49f58d10
JB		 46258 },
46259/* jsri.w ${Dsp-16-u16}[sb] */
46260 {
46261 { 0, 0, 0, 0 },
46262 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46263 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc59f0000 }
46264 },
46265/* jsri.w ${Dsp-16-s16}[fb] */
46266 {
46267 { 0, 0, 0, 0 },
46268 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46269 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5df0000 }
46270 },
46271/* jsri.w ${Dsp-16-u16} */
46272 {
46273 { 0, 0, 0, 0 },
46274 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46275 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7df0000 }
46276 },
49f58d10
JB		 46277/* jsri.w ${Dsp-16-u16}[sb] */
46278 {
46279 { 0, 0, 0, 0 },
46280 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46281 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d3e0000 }
46282 },
46283/* jsri.w ${Dsp-16-u16} */
46284 {
46285 { 0, 0, 0, 0 },
46286 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46287 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d3f0000 }
46288 },
75b06e7b 46289/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 46290 {
46291 { 0, 0, 0, 0 },
75b06e7b
DD		 46292 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46293 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 }
49f58d10 46294 },
75b06e7b 46295/* jsri.w ${Dsp-16-u24} */
49f58d10
JB		 46296 {
46297 { 0, 0, 0, 0 },
75b06e7b
DD		 46298 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46299 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 }
49f58d10 46300 },
75b06e7b 46301/* jsri.w ${Dsp-16-u20}[$Dst16An] */
49f58d10
JB		 46302 {
46303 { 0, 0, 0, 0 },
75b06e7b
DD		 46304 { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } },
46305 & ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI, { 0x7d3c0000 }
49f58d10 46306 },
49f58d10
JB		 46307/* jmpi.a $Dst32RnUnprefixedSI */
46308 {
46309 { 0, 0, 0, 0 },
46310 { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
46311 & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x8801 }
46312 },
46313/* jmpi.a $Dst32AnUnprefixedSI */
46314 {
46315 { 0, 0, 0, 0 },
46316 { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
46317 & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x8081 }
46318 },
46319/* jmpi.a [$Dst32AnUnprefixed] */
46320 {
46321 { 0, 0, 0, 0 },
46322 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46323 & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x8001 }
46324 },
46325/* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46326 {
46327 { 0, 0, 0, 0 },
46328 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46329 & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x820100 }
46330 },
46331/* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46332 {
46333 { 0, 0, 0, 0 },
46334 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46335 & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x84010000 }
46336 },
46337/* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46338 {
46339 { 0, 0, 0, 0 },
46340 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46341 & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x86010000 }
46342 },
46343/* jmpi.a ${Dsp-16-u8}[sb] */
46344 {
46345 { 0, 0, 0, 0 },
46346 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46347 & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828100 }
46348 },
46349/* jmpi.a ${Dsp-16-u16}[sb] */
46350 {
46351 { 0, 0, 0, 0 },
46352 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46353 & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84810000 }
46354 },
46355/* jmpi.a ${Dsp-16-s8}[fb] */
46356 {
46357 { 0, 0, 0, 0 },
46358 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46359 & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c100 }
46360 },
46361/* jmpi.a ${Dsp-16-s16}[fb] */
46362 {
46363 { 0, 0, 0, 0 },
46364 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46365 & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c10000 }
46366 },
46367/* jmpi.a ${Dsp-16-u16} */
46368 {
46369 { 0, 0, 0, 0 },
46370 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46371 & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x86c10000 }
46372 },
46373/* jmpi.a ${Dsp-16-u24} */
46374 {
46375 { 0, 0, 0, 0 },
46376 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46377 & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x86810000 }
46378 },
46379/* jmpi.a $Dst16RnSI */
46380 {
46381 { 0, 0, 0, 0 },
46382 { { MNEM, ' ', OP (DST16RNSI), 0 } },
46383 & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d00 }
46384 },
46385/* jmpi.a $Dst16AnSI */
46386 {
46387 { 0, 0, 0, 0 },
46388 { { MNEM, ' ', OP (DST16ANSI), 0 } },
46389 & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d04 }
46390 },
46391/* jmpi.a [$Dst16An] */
46392 {
46393 { 0, 0, 0, 0 },
46394 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46395 & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d06 }
46396 },
46397/* jmpi.a ${Dsp-16-u8}[$Dst16An] */
46398 {
46399 { 0, 0, 0, 0 },
46400 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46401 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d0800 }
46402 },
46403/* jmpi.a ${Dsp-16-u16}[$Dst16An] */
46404 {
46405 { 0, 0, 0, 0 },
46406 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
75b06e7b 46407 & ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI, { 0x7d0c0000 }
49f58d10
JB		 46408 },
46409/* jmpi.a ${Dsp-16-u8}[sb] */
46410 {
46411 { 0, 0, 0, 0 },
46412 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46413 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d0a00 }
46414 },
46415/* jmpi.a ${Dsp-16-u16}[sb] */
46416 {
46417 { 0, 0, 0, 0 },
46418 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75b06e7b 46419 & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d0e0000 }
49f58d10
JB		 46420 },
46421/* jmpi.a ${Dsp-16-s8}[fb] */
46422 {
46423 { 0, 0, 0, 0 },
46424 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46425 & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d0b00 }
46426 },
46427/* jmpi.a ${Dsp-16-u16} */
46428 {
46429 { 0, 0, 0, 0 },
46430 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
75b06e7b 46431 & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d0f0000 }
49f58d10
JB		 46432 },
46433/* jmpi.w $Dst32RnUnprefixedHI */
46434 {
46435 { 0, 0, 0, 0 },
46436 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46437 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90f }
46438 },
46439/* jmpi.w $Dst32AnUnprefixedHI */
46440 {
46441 { 0, 0, 0, 0 },
46442 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46443 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18f }
46444 },
46445/* jmpi.w [$Dst32AnUnprefixed] */
46446 {
46447 { 0, 0, 0, 0 },
46448 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46449 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10f }
46450 },
46451/* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46452 {
46453 { 0, 0, 0, 0 },
46454 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46455 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30f00 }
46456 },
46457/* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46458 {
46459 { 0, 0, 0, 0 },
46460 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46461 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50f0000 }
46462 },
46463/* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46464 {
46465 { 0, 0, 0, 0 },
46466 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46467 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70f0000 }
46468 },
46469/* jmpi.w ${Dsp-16-u8}[sb] */
46470 {
46471 { 0, 0, 0, 0 },
46472 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46473 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38f00 }
46474 },
46475/* jmpi.w ${Dsp-16-u16}[sb] */
46476 {
46477 { 0, 0, 0, 0 },
46478 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46479 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58f0000 }
46480 },
46481/* jmpi.w ${Dsp-16-s8}[fb] */
46482 {
46483 { 0, 0, 0, 0 },
46484 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46485 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cf00 }
46486 },
46487/* jmpi.w ${Dsp-16-s16}[fb] */
46488 {
46489 { 0, 0, 0, 0 },
46490 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46491 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cf0000 }
46492 },
46493/* jmpi.w ${Dsp-16-u16} */
46494 {
46495 { 0, 0, 0, 0 },
46496 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46497 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cf0000 }
46498 },
46499/* jmpi.w ${Dsp-16-u24} */
46500 {
46501 { 0, 0, 0, 0 },
46502 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46503 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78f0000 }
46504 },
46505/* jmpi.w $Dst16RnHI */
46506 {
46507 { 0, 0, 0, 0 },
46508 { { MNEM, ' ', OP (DST16RNHI), 0 } },
46509 & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d20 }
46510 },
46511/* jmpi.w $Dst16AnHI */
46512 {
46513 { 0, 0, 0, 0 },
46514 { { MNEM, ' ', OP (DST16ANHI), 0 } },
46515 & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d24 }
46516 },
46517/* jmpi.w [$Dst16An] */
46518 {
46519 { 0, 0, 0, 0 },
46520 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46521 & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d26 }
46522 },
46523/* jmpi.w ${Dsp-16-u8}[$Dst16An] */
46524 {
46525 { 0, 0, 0, 0 },
46526 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46527 & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d2800 }
46528 },
46529/* jmpi.w ${Dsp-16-u16}[$Dst16An] */
46530 {
46531 { 0, 0, 0, 0 },
46532 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
46533 & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d2c0000 }
46534 },
46535/* jmpi.w ${Dsp-16-u8}[sb] */
46536 {
46537 { 0, 0, 0, 0 },
46538 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46539 & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d2a00 }
46540 },
46541/* jmpi.w ${Dsp-16-u16}[sb] */
46542 {
46543 { 0, 0, 0, 0 },
46544 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46545 & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d2e0000 }
46546 },
46547/* jmpi.w ${Dsp-16-s8}[fb] */
46548 {
46549 { 0, 0, 0, 0 },
46550 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46551 & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d2b00 }
46552 },
46553/* jmpi.w ${Dsp-16-u16} */
46554 {
46555 { 0, 0, 0, 0 },
46556 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46557 & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d2f0000 }
46558 },
46559/* indexws.w $Dst32RnUnprefixedHI */
46560 {
46561 { 0, 0, 0, 0 },
46562 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 46563 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc833 }
49f58d10
JB		 46564 },
46565/* indexws.w $Dst32AnUnprefixedHI */
46566 {
46567 { 0, 0, 0, 0 },
46568 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 46569 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc0b3 }
49f58d10
JB		 46570 },
46571/* indexws.w [$Dst32AnUnprefixed] */
46572 {
46573 { 0, 0, 0, 0 },
46574 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46575 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc033 }
49f58d10
JB		 46576 },
46577/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46578 {
46579 { 0, 0, 0, 0 },
46580 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46581 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc23300 }
49f58d10
JB		 46582 },
46583/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46584 {
46585 { 0, 0, 0, 0 },
46586 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46587 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4330000 }
49f58d10
JB		 46588 },
46589/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46590 {
46591 { 0, 0, 0, 0 },
46592 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46593 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6330000 }
49f58d10
JB		 46594 },
46595/* indexws.w ${Dsp-16-u8}[sb] */
46596 {
46597 { 0, 0, 0, 0 },
46598 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 46599 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc2b300 }
49f58d10
JB		 46600 },
46601/* indexws.w ${Dsp-16-u16}[sb] */
46602 {
46603 { 0, 0, 0, 0 },
46604 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 46605 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4b30000 }
49f58d10
JB		 46606 },
46607/* indexws.w ${Dsp-16-s8}[fb] */
46608 {
46609 { 0, 0, 0, 0 },
46610 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 46611 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2f300 }
49f58d10
JB		 46612 },
46613/* indexws.w ${Dsp-16-s16}[fb] */
46614 {
46615 { 0, 0, 0, 0 },
46616 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 46617 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4f30000 }
49f58d10
JB		 46618 },
46619/* indexws.w ${Dsp-16-u16} */
46620 {
46621 { 0, 0, 0, 0 },
46622 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 46623 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6f30000 }
49f58d10
JB		 46624 },
46625/* indexws.w ${Dsp-16-u24} */
46626 {
46627 { 0, 0, 0, 0 },
46628 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 46629 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6b30000 }
49f58d10
JB		 46630 },
46631/* indexws.b $Dst32RnUnprefixedQI */
46632 {
46633 { 0, 0, 0, 0 },
46634 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46635 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc823 }
46636 },
46637/* indexws.b $Dst32AnUnprefixedQI */
46638 {
46639 { 0, 0, 0, 0 },
46640 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46641 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0a3 }
46642 },
46643/* indexws.b [$Dst32AnUnprefixed] */
46644 {
46645 { 0, 0, 0, 0 },
46646 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46647 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc023 }
46648 },
46649/* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46650 {
46651 { 0, 0, 0, 0 },
46652 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46653 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22300 }
46654 },
46655/* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46656 {
46657 { 0, 0, 0, 0 },
46658 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46659 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4230000 }
46660 },
46661/* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46662 {
46663 { 0, 0, 0, 0 },
46664 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46665 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6230000 }
46666 },
46667/* indexws.b ${Dsp-16-u8}[sb] */
46668 {
46669 { 0, 0, 0, 0 },
46670 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46671 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2a300 }
46672 },
46673/* indexws.b ${Dsp-16-u16}[sb] */
46674 {
46675 { 0, 0, 0, 0 },
46676 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46677 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4a30000 }
46678 },
46679/* indexws.b ${Dsp-16-s8}[fb] */
46680 {
46681 { 0, 0, 0, 0 },
46682 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46683 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2e300 }
46684 },
46685/* indexws.b ${Dsp-16-s16}[fb] */
46686 {
46687 { 0, 0, 0, 0 },
46688 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46689 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4e30000 }
46690 },
46691/* indexws.b ${Dsp-16-u16} */
46692 {
46693 { 0, 0, 0, 0 },
46694 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46695 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6e30000 }
46696 },
46697/* indexws.b ${Dsp-16-u24} */
46698 {
46699 { 0, 0, 0, 0 },
46700 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46701 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6a30000 }
46702 },
46703/* indexwd.w $Dst32RnUnprefixedHI */
46704 {
46705 { 0, 0, 0, 0 },
46706 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 46707 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa833 }
49f58d10
JB		 46708 },
46709/* indexwd.w $Dst32AnUnprefixedHI */
46710 {
46711 { 0, 0, 0, 0 },
46712 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 46713 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa0b3 }
49f58d10
JB		 46714 },
46715/* indexwd.w [$Dst32AnUnprefixed] */
46716 {
46717 { 0, 0, 0, 0 },
46718 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46719 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa033 }
49f58d10
JB		 46720 },
46721/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46722 {
46723 { 0, 0, 0, 0 },
46724 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46725 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa23300 }
49f58d10
JB		 46726 },
46727/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46728 {
46729 { 0, 0, 0, 0 },
46730 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46731 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4330000 }
49f58d10
JB		 46732 },
46733/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46734 {
46735 { 0, 0, 0, 0 },
46736 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46737 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6330000 }
49f58d10
JB		 46738 },
46739/* indexwd.w ${Dsp-16-u8}[sb] */
46740 {
46741 { 0, 0, 0, 0 },
46742 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 46743 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa2b300 }
49f58d10
JB		 46744 },
46745/* indexwd.w ${Dsp-16-u16}[sb] */
46746 {
46747 { 0, 0, 0, 0 },
46748 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 46749 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4b30000 }
49f58d10
JB		 46750 },
46751/* indexwd.w ${Dsp-16-s8}[fb] */
46752 {
46753 { 0, 0, 0, 0 },
46754 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 46755 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2f300 }
49f58d10
JB		 46756 },
46757/* indexwd.w ${Dsp-16-s16}[fb] */
46758 {
46759 { 0, 0, 0, 0 },
46760 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 46761 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4f30000 }
49f58d10
JB		 46762 },
46763/* indexwd.w ${Dsp-16-u16} */
46764 {
46765 { 0, 0, 0, 0 },
46766 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 46767 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6f30000 }
49f58d10
JB		 46768 },
46769/* indexwd.w ${Dsp-16-u24} */
46770 {
46771 { 0, 0, 0, 0 },
46772 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 46773 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6b30000 }
49f58d10
JB		 46774 },
46775/* indexwd.b $Dst32RnUnprefixedQI */
46776 {
46777 { 0, 0, 0, 0 },
46778 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46779 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa823 }
46780 },
46781/* indexwd.b $Dst32AnUnprefixedQI */
46782 {
46783 { 0, 0, 0, 0 },
46784 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46785 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0a3 }
46786 },
46787/* indexwd.b [$Dst32AnUnprefixed] */
46788 {
46789 { 0, 0, 0, 0 },
46790 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46791 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa023 }
46792 },
46793/* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46794 {
46795 { 0, 0, 0, 0 },
46796 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46797 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22300 }
46798 },
46799/* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46800 {
46801 { 0, 0, 0, 0 },
46802 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46803 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4230000 }
46804 },
46805/* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46806 {
46807 { 0, 0, 0, 0 },
46808 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46809 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6230000 }
46810 },
46811/* indexwd.b ${Dsp-16-u8}[sb] */
46812 {
46813 { 0, 0, 0, 0 },
46814 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46815 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2a300 }
46816 },
46817/* indexwd.b ${Dsp-16-u16}[sb] */
46818 {
46819 { 0, 0, 0, 0 },
46820 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46821 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4a30000 }
46822 },
46823/* indexwd.b ${Dsp-16-s8}[fb] */
46824 {
46825 { 0, 0, 0, 0 },
46826 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46827 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2e300 }
46828 },
46829/* indexwd.b ${Dsp-16-s16}[fb] */
46830 {
46831 { 0, 0, 0, 0 },
46832 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46833 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4e30000 }
46834 },
46835/* indexwd.b ${Dsp-16-u16} */
46836 {
46837 { 0, 0, 0, 0 },
46838 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46839 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6e30000 }
46840 },
46841/* indexwd.b ${Dsp-16-u24} */
46842 {
46843 { 0, 0, 0, 0 },
46844 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46845 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6a30000 }
46846 },
46847/* indexw.w $Dst32RnUnprefixedHI */
46848 {
46849 { 0, 0, 0, 0 },
46850 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 46851 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8833 }
49f58d10
JB		 46852 },
46853/* indexw.w $Dst32AnUnprefixedHI */
46854 {
46855 { 0, 0, 0, 0 },
46856 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 46857 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x80b3 }
49f58d10
JB		 46858 },
46859/* indexw.w [$Dst32AnUnprefixed] */
46860 {
46861 { 0, 0, 0, 0 },
46862 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46863 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8033 }
49f58d10
JB		 46864 },
46865/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46866 {
46867 { 0, 0, 0, 0 },
46868 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46869 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x823300 }
49f58d10
JB		 46870 },
46871/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46872 {
46873 { 0, 0, 0, 0 },
46874 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46875 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84330000 }
49f58d10
JB		 46876 },
46877/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46878 {
46879 { 0, 0, 0, 0 },
46880 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 46881 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86330000 }
49f58d10
JB		 46882 },
46883/* indexw.w ${Dsp-16-u8}[sb] */
46884 {
46885 { 0, 0, 0, 0 },
46886 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 46887 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x82b300 }
49f58d10
JB		 46888 },
46889/* indexw.w ${Dsp-16-u16}[sb] */
46890 {
46891 { 0, 0, 0, 0 },
46892 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 46893 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84b30000 }
49f58d10
JB		 46894 },
46895/* indexw.w ${Dsp-16-s8}[fb] */
46896 {
46897 { 0, 0, 0, 0 },
46898 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 46899 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82f300 }
49f58d10
JB		 46900 },
46901/* indexw.w ${Dsp-16-s16}[fb] */
46902 {
46903 { 0, 0, 0, 0 },
46904 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 46905 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84f30000 }
49f58d10
JB		 46906 },
46907/* indexw.w ${Dsp-16-u16} */
46908 {
46909 { 0, 0, 0, 0 },
46910 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 46911 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86f30000 }
49f58d10
JB		 46912 },
46913/* indexw.w ${Dsp-16-u24} */
46914 {
46915 { 0, 0, 0, 0 },
46916 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 46917 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86b30000 }
49f58d10
JB		 46918 },
46919/* indexw.b $Dst32RnUnprefixedQI */
46920 {
46921 { 0, 0, 0, 0 },
46922 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46923 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8823 }
46924 },
46925/* indexw.b $Dst32AnUnprefixedQI */
46926 {
46927 { 0, 0, 0, 0 },
46928 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46929 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x80a3 }
46930 },
46931/* indexw.b [$Dst32AnUnprefixed] */
46932 {
46933 { 0, 0, 0, 0 },
46934 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46935 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8023 }
46936 },
46937/* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46938 {
46939 { 0, 0, 0, 0 },
46940 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46941 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x822300 }
46942 },
46943/* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46944 {
46945 { 0, 0, 0, 0 },
46946 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46947 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84230000 }
46948 },
46949/* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46950 {
46951 { 0, 0, 0, 0 },
46952 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46953 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86230000 }
46954 },
46955/* indexw.b ${Dsp-16-u8}[sb] */
46956 {
46957 { 0, 0, 0, 0 },
46958 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46959 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a300 }
46960 },
46961/* indexw.b ${Dsp-16-u16}[sb] */
46962 {
46963 { 0, 0, 0, 0 },
46964 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46965 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a30000 }
46966 },
46967/* indexw.b ${Dsp-16-s8}[fb] */
46968 {
46969 { 0, 0, 0, 0 },
46970 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46971 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e300 }
46972 },
46973/* indexw.b ${Dsp-16-s16}[fb] */
46974 {
46975 { 0, 0, 0, 0 },
46976 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46977 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e30000 }
46978 },
46979/* indexw.b ${Dsp-16-u16} */
46980 {
46981 { 0, 0, 0, 0 },
46982 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46983 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86e30000 }
46984 },
46985/* indexw.b ${Dsp-16-u24} */
46986 {
46987 { 0, 0, 0, 0 },
46988 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46989 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86a30000 }
46990 },
46991/* indexls.w $Dst32RnUnprefixedHI */
46992 {
46993 { 0, 0, 0, 0 },
46994 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 46995 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9813 }
49f58d10
JB		 46996 },
46997/* indexls.w $Dst32AnUnprefixedHI */
46998 {
46999 { 0, 0, 0, 0 },
47000 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 47001 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9093 }
49f58d10
JB		 47002 },
47003/* indexls.w [$Dst32AnUnprefixed] */
47004 {
47005 { 0, 0, 0, 0 },
47006 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47007 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9013 }
49f58d10
JB		 47008 },
47009/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47010 {
47011 { 0, 0, 0, 0 },
47012 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47013 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x921300 }
49f58d10
JB		 47014 },
47015/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47016 {
47017 { 0, 0, 0, 0 },
47018 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47019 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94130000 }
49f58d10
JB		 47020 },
47021/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47022 {
47023 { 0, 0, 0, 0 },
47024 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47025 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96130000 }
49f58d10
JB		 47026 },
47027/* indexls.w ${Dsp-16-u8}[sb] */
47028 {
47029 { 0, 0, 0, 0 },
47030 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 47031 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x929300 }
49f58d10
JB		 47032 },
47033/* indexls.w ${Dsp-16-u16}[sb] */
47034 {
47035 { 0, 0, 0, 0 },
47036 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 47037 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94930000 }
49f58d10
JB		 47038 },
47039/* indexls.w ${Dsp-16-s8}[fb] */
47040 {
47041 { 0, 0, 0, 0 },
47042 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 47043 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92d300 }
49f58d10
JB		 47044 },
47045/* indexls.w ${Dsp-16-s16}[fb] */
47046 {
47047 { 0, 0, 0, 0 },
47048 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 47049 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94d30000 }
49f58d10
JB		 47050 },
47051/* indexls.w ${Dsp-16-u16} */
47052 {
47053 { 0, 0, 0, 0 },
47054 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 47055 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96d30000 }
49f58d10
JB		 47056 },
47057/* indexls.w ${Dsp-16-u24} */
47058 {
47059 { 0, 0, 0, 0 },
47060 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 47061 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96930000 }
49f58d10
JB		 47062 },
47063/* indexls.b $Dst32RnUnprefixedQI */
47064 {
47065 { 0, 0, 0, 0 },
47066 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47067 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9803 }
47068 },
47069/* indexls.b $Dst32AnUnprefixedQI */
47070 {
47071 { 0, 0, 0, 0 },
47072 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47073 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x9083 }
47074 },
47075/* indexls.b [$Dst32AnUnprefixed] */
47076 {
47077 { 0, 0, 0, 0 },
47078 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47079 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9003 }
47080 },
47081/* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47082 {
47083 { 0, 0, 0, 0 },
47084 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47085 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x920300 }
47086 },
47087/* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47088 {
47089 { 0, 0, 0, 0 },
47090 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47091 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94030000 }
47092 },
47093/* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47094 {
47095 { 0, 0, 0, 0 },
47096 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47097 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96030000 }
47098 },
47099/* indexls.b ${Dsp-16-u8}[sb] */
47100 {
47101 { 0, 0, 0, 0 },
47102 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47103 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928300 }
47104 },
47105/* indexls.b ${Dsp-16-u16}[sb] */
47106 {
47107 { 0, 0, 0, 0 },
47108 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47109 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94830000 }
47110 },
47111/* indexls.b ${Dsp-16-s8}[fb] */
47112 {
47113 { 0, 0, 0, 0 },
47114 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47115 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92c300 }
47116 },
47117/* indexls.b ${Dsp-16-s16}[fb] */
47118 {
47119 { 0, 0, 0, 0 },
47120 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47121 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94c30000 }
47122 },
47123/* indexls.b ${Dsp-16-u16} */
47124 {
47125 { 0, 0, 0, 0 },
47126 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47127 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96c30000 }
47128 },
47129/* indexls.b ${Dsp-16-u24} */
47130 {
47131 { 0, 0, 0, 0 },
47132 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47133 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96830000 }
47134 },
47135/* indexld.w $Dst32RnUnprefixedHI */
47136 {
47137 { 0, 0, 0, 0 },
47138 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 47139 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb833 }
49f58d10
JB		 47140 },
47141/* indexld.w $Dst32AnUnprefixedHI */
47142 {
47143 { 0, 0, 0, 0 },
47144 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 47145 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb0b3 }
49f58d10
JB		 47146 },
47147/* indexld.w [$Dst32AnUnprefixed] */
47148 {
47149 { 0, 0, 0, 0 },
47150 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47151 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb033 }
49f58d10
JB		 47152 },
47153/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47154 {
47155 { 0, 0, 0, 0 },
47156 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47157 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb23300 }
49f58d10
JB		 47158 },
47159/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47160 {
47161 { 0, 0, 0, 0 },
47162 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47163 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb4330000 }
49f58d10
JB		 47164 },
47165/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47166 {
47167 { 0, 0, 0, 0 },
47168 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47169 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb6330000 }
49f58d10
JB		 47170 },
47171/* indexld.w ${Dsp-16-u8}[sb] */
47172 {
47173 { 0, 0, 0, 0 },
47174 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 47175 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb2b300 }
49f58d10
JB		 47176 },
47177/* indexld.w ${Dsp-16-u16}[sb] */
47178 {
47179 { 0, 0, 0, 0 },
47180 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 47181 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb4b30000 }
49f58d10
JB		 47182 },
47183/* indexld.w ${Dsp-16-s8}[fb] */
47184 {
47185 { 0, 0, 0, 0 },
47186 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 47187 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb2f300 }
49f58d10
JB		 47188 },
47189/* indexld.w ${Dsp-16-s16}[fb] */
47190 {
47191 { 0, 0, 0, 0 },
47192 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 47193 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb4f30000 }
49f58d10
JB		 47194 },
47195/* indexld.w ${Dsp-16-u16} */
47196 {
47197 { 0, 0, 0, 0 },
47198 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 47199 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb6f30000 }
49f58d10
JB		 47200 },
47201/* indexld.w ${Dsp-16-u24} */
47202 {
47203 { 0, 0, 0, 0 },
47204 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 47205 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb6b30000 }
49f58d10
JB		 47206 },
47207/* indexld.b $Dst32RnUnprefixedQI */
47208 {
47209 { 0, 0, 0, 0 },
47210 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47211 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb823 }
47212 },
47213/* indexld.b $Dst32AnUnprefixedQI */
47214 {
47215 { 0, 0, 0, 0 },
47216 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47217 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0a3 }
47218 },
47219/* indexld.b [$Dst32AnUnprefixed] */
47220 {
47221 { 0, 0, 0, 0 },
47222 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47223 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb023 }
47224 },
47225/* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47226 {
47227 { 0, 0, 0, 0 },
47228 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47229 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22300 }
47230 },
47231/* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47232 {
47233 { 0, 0, 0, 0 },
47234 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47235 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb4230000 }
47236 },
47237/* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47238 {
47239 { 0, 0, 0, 0 },
47240 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47241 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb6230000 }
47242 },
47243/* indexld.b ${Dsp-16-u8}[sb] */
47244 {
47245 { 0, 0, 0, 0 },
47246 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47247 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2a300 }
47248 },
47249/* indexld.b ${Dsp-16-u16}[sb] */
47250 {
47251 { 0, 0, 0, 0 },
47252 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47253 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4a30000 }
47254 },
47255/* indexld.b ${Dsp-16-s8}[fb] */
47256 {
47257 { 0, 0, 0, 0 },
47258 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47259 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2e300 }
47260 },
47261/* indexld.b ${Dsp-16-s16}[fb] */
47262 {
47263 { 0, 0, 0, 0 },
47264 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47265 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4e30000 }
47266 },
47267/* indexld.b ${Dsp-16-u16} */
47268 {
47269 { 0, 0, 0, 0 },
47270 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47271 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6e30000 }
47272 },
47273/* indexld.b ${Dsp-16-u24} */
47274 {
47275 { 0, 0, 0, 0 },
47276 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47277 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6a30000 }
47278 },
47279/* indexl.w $Dst32RnUnprefixedHI */
47280 {
47281 { 0, 0, 0, 0 },
47282 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 47283 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9833 }
49f58d10
JB		 47284 },
47285/* indexl.w $Dst32AnUnprefixedHI */
47286 {
47287 { 0, 0, 0, 0 },
47288 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 47289 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x90b3 }
49f58d10
JB		 47290 },
47291/* indexl.w [$Dst32AnUnprefixed] */
47292 {
47293 { 0, 0, 0, 0 },
47294 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47295 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9033 }
49f58d10
JB		 47296 },
47297/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47298 {
47299 { 0, 0, 0, 0 },
47300 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47301 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x923300 }
49f58d10
JB		 47302 },
47303/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47304 {
47305 { 0, 0, 0, 0 },
47306 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47307 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94330000 }
49f58d10
JB		 47308 },
47309/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47310 {
47311 { 0, 0, 0, 0 },
47312 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47313 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96330000 }
49f58d10
JB		 47314 },
47315/* indexl.w ${Dsp-16-u8}[sb] */
47316 {
47317 { 0, 0, 0, 0 },
47318 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 47319 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x92b300 }
49f58d10
JB		 47320 },
47321/* indexl.w ${Dsp-16-u16}[sb] */
47322 {
47323 { 0, 0, 0, 0 },
47324 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 47325 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94b30000 }
49f58d10
JB		 47326 },
47327/* indexl.w ${Dsp-16-s8}[fb] */
47328 {
47329 { 0, 0, 0, 0 },
47330 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 47331 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92f300 }
49f58d10
JB		 47332 },
47333/* indexl.w ${Dsp-16-s16}[fb] */
47334 {
47335 { 0, 0, 0, 0 },
47336 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 47337 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94f30000 }
49f58d10
JB		 47338 },
47339/* indexl.w ${Dsp-16-u16} */
47340 {
47341 { 0, 0, 0, 0 },
47342 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 47343 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96f30000 }
49f58d10
JB		 47344 },
47345/* indexl.w ${Dsp-16-u24} */
47346 {
47347 { 0, 0, 0, 0 },
47348 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 47349 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96b30000 }
49f58d10
JB		 47350 },
47351/* indexl.b $Dst32RnUnprefixedQI */
47352 {
47353 { 0, 0, 0, 0 },
47354 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47355 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9823 }
47356 },
47357/* indexl.b $Dst32AnUnprefixedQI */
47358 {
47359 { 0, 0, 0, 0 },
47360 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47361 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x90a3 }
47362 },
47363/* indexl.b [$Dst32AnUnprefixed] */
47364 {
47365 { 0, 0, 0, 0 },
47366 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47367 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9023 }
47368 },
47369/* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47370 {
47371 { 0, 0, 0, 0 },
47372 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47373 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x922300 }
47374 },
47375/* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47376 {
47377 { 0, 0, 0, 0 },
47378 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47379 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94230000 }
47380 },
47381/* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47382 {
47383 { 0, 0, 0, 0 },
47384 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47385 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96230000 }
47386 },
47387/* indexl.b ${Dsp-16-u8}[sb] */
47388 {
47389 { 0, 0, 0, 0 },
47390 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47391 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92a300 }
47392 },
47393/* indexl.b ${Dsp-16-u16}[sb] */
47394 {
47395 { 0, 0, 0, 0 },
47396 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47397 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94a30000 }
47398 },
47399/* indexl.b ${Dsp-16-s8}[fb] */
47400 {
47401 { 0, 0, 0, 0 },
47402 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47403 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92e300 }
47404 },
47405/* indexl.b ${Dsp-16-s16}[fb] */
47406 {
47407 { 0, 0, 0, 0 },
47408 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47409 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94e30000 }
47410 },
47411/* indexl.b ${Dsp-16-u16} */
47412 {
47413 { 0, 0, 0, 0 },
47414 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47415 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96e30000 }
47416 },
47417/* indexl.b ${Dsp-16-u24} */
47418 {
47419 { 0, 0, 0, 0 },
47420 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47421 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96a30000 }
47422 },
47423/* indexbs.w $Dst32RnUnprefixedHI */
47424 {
47425 { 0, 0, 0, 0 },
47426 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 47427 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc813 }
49f58d10
JB		 47428 },
47429/* indexbs.w $Dst32AnUnprefixedHI */
47430 {
47431 { 0, 0, 0, 0 },
47432 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 47433 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc093 }
49f58d10
JB		 47434 },
47435/* indexbs.w [$Dst32AnUnprefixed] */
47436 {
47437 { 0, 0, 0, 0 },
47438 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47439 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc013 }
49f58d10
JB		 47440 },
47441/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47442 {
47443 { 0, 0, 0, 0 },
47444 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47445 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc21300 }
49f58d10
JB		 47446 },
47447/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47448 {
47449 { 0, 0, 0, 0 },
47450 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47451 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4130000 }
49f58d10
JB		 47452 },
47453/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47454 {
47455 { 0, 0, 0, 0 },
47456 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47457 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6130000 }
49f58d10
JB		 47458 },
47459/* indexbs.w ${Dsp-16-u8}[sb] */
47460 {
47461 { 0, 0, 0, 0 },
47462 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 47463 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc29300 }
49f58d10
JB		 47464 },
47465/* indexbs.w ${Dsp-16-u16}[sb] */
47466 {
47467 { 0, 0, 0, 0 },
47468 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 47469 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4930000 }
49f58d10
JB		 47470 },
47471/* indexbs.w ${Dsp-16-s8}[fb] */
47472 {
47473 { 0, 0, 0, 0 },
47474 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 47475 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2d300 }
49f58d10
JB		 47476 },
47477/* indexbs.w ${Dsp-16-s16}[fb] */
47478 {
47479 { 0, 0, 0, 0 },
47480 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 47481 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4d30000 }
49f58d10
JB		 47482 },
47483/* indexbs.w ${Dsp-16-u16} */
47484 {
47485 { 0, 0, 0, 0 },
47486 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 47487 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6d30000 }
49f58d10
JB		 47488 },
47489/* indexbs.w ${Dsp-16-u24} */
47490 {
47491 { 0, 0, 0, 0 },
47492 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 47493 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6930000 }
49f58d10
JB		 47494 },
47495/* indexbs.b $Dst32RnUnprefixedQI */
47496 {
47497 { 0, 0, 0, 0 },
47498 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47499 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc803 }
47500 },
47501/* indexbs.b $Dst32AnUnprefixedQI */
47502 {
47503 { 0, 0, 0, 0 },
47504 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47505 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc083 }
47506 },
47507/* indexbs.b [$Dst32AnUnprefixed] */
47508 {
47509 { 0, 0, 0, 0 },
47510 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47511 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc003 }
47512 },
47513/* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47514 {
47515 { 0, 0, 0, 0 },
47516 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47517 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20300 }
47518 },
47519/* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47520 {
47521 { 0, 0, 0, 0 },
47522 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47523 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4030000 }
47524 },
47525/* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47526 {
47527 { 0, 0, 0, 0 },
47528 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47529 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6030000 }
47530 },
47531/* indexbs.b ${Dsp-16-u8}[sb] */
47532 {
47533 { 0, 0, 0, 0 },
47534 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47535 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28300 }
47536 },
47537/* indexbs.b ${Dsp-16-u16}[sb] */
47538 {
47539 { 0, 0, 0, 0 },
47540 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47541 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4830000 }
47542 },
47543/* indexbs.b ${Dsp-16-s8}[fb] */
47544 {
47545 { 0, 0, 0, 0 },
47546 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47547 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c300 }
47548 },
47549/* indexbs.b ${Dsp-16-s16}[fb] */
47550 {
47551 { 0, 0, 0, 0 },
47552 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47553 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c30000 }
47554 },
47555/* indexbs.b ${Dsp-16-u16} */
47556 {
47557 { 0, 0, 0, 0 },
47558 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47559 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c30000 }
47560 },
47561/* indexbs.b ${Dsp-16-u24} */
47562 {
47563 { 0, 0, 0, 0 },
47564 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47565 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6830000 }
47566 },
47567/* indexbd.w $Dst32RnUnprefixedHI */
47568 {
47569 { 0, 0, 0, 0 },
47570 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 47571 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa813 }
49f58d10
JB		 47572 },
47573/* indexbd.w $Dst32AnUnprefixedHI */
47574 {
47575 { 0, 0, 0, 0 },
47576 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 47577 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa093 }
49f58d10
JB		 47578 },
47579/* indexbd.w [$Dst32AnUnprefixed] */
47580 {
47581 { 0, 0, 0, 0 },
47582 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47583 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa013 }
49f58d10
JB		 47584 },
47585/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47586 {
47587 { 0, 0, 0, 0 },
47588 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47589 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa21300 }
49f58d10
JB		 47590 },
47591/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47592 {
47593 { 0, 0, 0, 0 },
47594 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47595 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4130000 }
49f58d10
JB		 47596 },
47597/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47598 {
47599 { 0, 0, 0, 0 },
47600 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47601 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6130000 }
49f58d10
JB		 47602 },
47603/* indexbd.w ${Dsp-16-u8}[sb] */
47604 {
47605 { 0, 0, 0, 0 },
47606 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 47607 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa29300 }
49f58d10
JB		 47608 },
47609/* indexbd.w ${Dsp-16-u16}[sb] */
47610 {
47611 { 0, 0, 0, 0 },
47612 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 47613 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4930000 }
49f58d10
JB		 47614 },
47615/* indexbd.w ${Dsp-16-s8}[fb] */
47616 {
47617 { 0, 0, 0, 0 },
47618 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 47619 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2d300 }
49f58d10
JB		 47620 },
47621/* indexbd.w ${Dsp-16-s16}[fb] */
47622 {
47623 { 0, 0, 0, 0 },
47624 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 47625 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4d30000 }
49f58d10
JB		 47626 },
47627/* indexbd.w ${Dsp-16-u16} */
47628 {
47629 { 0, 0, 0, 0 },
47630 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 47631 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6d30000 }
49f58d10
JB		 47632 },
47633/* indexbd.w ${Dsp-16-u24} */
47634 {
47635 { 0, 0, 0, 0 },
47636 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 47637 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6930000 }
49f58d10
JB		 47638 },
47639/* indexbd.b $Dst32RnUnprefixedQI */
47640 {
47641 { 0, 0, 0, 0 },
47642 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47643 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa803 }
47644 },
47645/* indexbd.b $Dst32AnUnprefixedQI */
47646 {
47647 { 0, 0, 0, 0 },
47648 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47649 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa083 }
47650 },
47651/* indexbd.b [$Dst32AnUnprefixed] */
47652 {
47653 { 0, 0, 0, 0 },
47654 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47655 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa003 }
47656 },
47657/* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47658 {
47659 { 0, 0, 0, 0 },
47660 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47661 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20300 }
47662 },
47663/* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47664 {
47665 { 0, 0, 0, 0 },
47666 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47667 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4030000 }
47668 },
47669/* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47670 {
47671 { 0, 0, 0, 0 },
47672 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47673 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6030000 }
47674 },
47675/* indexbd.b ${Dsp-16-u8}[sb] */
47676 {
47677 { 0, 0, 0, 0 },
47678 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47679 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28300 }
47680 },
47681/* indexbd.b ${Dsp-16-u16}[sb] */
47682 {
47683 { 0, 0, 0, 0 },
47684 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47685 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4830000 }
47686 },
47687/* indexbd.b ${Dsp-16-s8}[fb] */
47688 {
47689 { 0, 0, 0, 0 },
47690 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47691 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2c300 }
47692 },
47693/* indexbd.b ${Dsp-16-s16}[fb] */
47694 {
47695 { 0, 0, 0, 0 },
47696 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47697 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4c30000 }
47698 },
47699/* indexbd.b ${Dsp-16-u16} */
47700 {
47701 { 0, 0, 0, 0 },
47702 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47703 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6c30000 }
47704 },
47705/* indexbd.b ${Dsp-16-u24} */
47706 {
47707 { 0, 0, 0, 0 },
47708 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47709 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6830000 }
47710 },
47711/* indexb.w $Dst32RnUnprefixedHI */
47712 {
47713 { 0, 0, 0, 0 },
47714 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
eda87aba 47715 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8813 }
49f58d10
JB		 47716 },
47717/* indexb.w $Dst32AnUnprefixedHI */
47718 {
47719 { 0, 0, 0, 0 },
47720 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
eda87aba 47721 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8093 }
49f58d10
JB		 47722 },
47723/* indexb.w [$Dst32AnUnprefixed] */
47724 {
47725 { 0, 0, 0, 0 },
47726 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47727 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8013 }
49f58d10
JB		 47728 },
47729/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47730 {
47731 { 0, 0, 0, 0 },
47732 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47733 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x821300 }
49f58d10
JB		 47734 },
47735/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47736 {
47737 { 0, 0, 0, 0 },
47738 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47739 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84130000 }
49f58d10
JB		 47740 },
47741/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47742 {
47743 { 0, 0, 0, 0 },
47744 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
eda87aba 47745 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86130000 }
49f58d10
JB		 47746 },
47747/* indexb.w ${Dsp-16-u8}[sb] */
47748 {
47749 { 0, 0, 0, 0 },
47750 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
eda87aba 47751 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x829300 }
49f58d10
JB		 47752 },
47753/* indexb.w ${Dsp-16-u16}[sb] */
47754 {
47755 { 0, 0, 0, 0 },
47756 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
eda87aba 47757 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84930000 }
49f58d10
JB		 47758 },
47759/* indexb.w ${Dsp-16-s8}[fb] */
47760 {
47761 { 0, 0, 0, 0 },
47762 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
eda87aba 47763 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82d300 }
49f58d10
JB		 47764 },
47765/* indexb.w ${Dsp-16-s16}[fb] */
47766 {
47767 { 0, 0, 0, 0 },
47768 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
eda87aba 47769 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84d30000 }
49f58d10
JB		 47770 },
47771/* indexb.w ${Dsp-16-u16} */
47772 {
47773 { 0, 0, 0, 0 },
47774 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
eda87aba 47775 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86d30000 }
49f58d10
JB		 47776 },
47777/* indexb.w ${Dsp-16-u24} */
47778 {
47779 { 0, 0, 0, 0 },
47780 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
eda87aba 47781 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86930000 }
49f58d10
JB		 47782 },
47783/* indexb.b $Dst32RnUnprefixedQI */
47784 {
47785 { 0, 0, 0, 0 },
47786 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47787 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8803 }
47788 },
47789/* indexb.b $Dst32AnUnprefixedQI */
47790 {
47791 { 0, 0, 0, 0 },
47792 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47793 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x8083 }
47794 },
47795/* indexb.b [$Dst32AnUnprefixed] */
47796 {
47797 { 0, 0, 0, 0 },
47798 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47799 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8003 }
47800 },
47801/* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47802 {
47803 { 0, 0, 0, 0 },
47804 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47805 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820300 }
47806 },
47807/* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47808 {
47809 { 0, 0, 0, 0 },
47810 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47811 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84030000 }
47812 },
47813/* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47814 {
47815 { 0, 0, 0, 0 },
47816 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47817 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86030000 }
47818 },
47819/* indexb.b ${Dsp-16-u8}[sb] */
47820 {
47821 { 0, 0, 0, 0 },
47822 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47823 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828300 }
47824 },
47825/* indexb.b ${Dsp-16-u16}[sb] */
47826 {
47827 { 0, 0, 0, 0 },
47828 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47829 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84830000 }
47830 },
47831/* indexb.b ${Dsp-16-s8}[fb] */
47832 {
47833 { 0, 0, 0, 0 },
47834 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47835 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c300 }
47836 },
47837/* indexb.b ${Dsp-16-s16}[fb] */
47838 {
47839 { 0, 0, 0, 0 },
47840 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47841 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c30000 }
47842 },
47843/* indexb.b ${Dsp-16-u16} */
47844 {
47845 { 0, 0, 0, 0 },
47846 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47847 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86c30000 }
47848 },
47849/* indexb.b ${Dsp-16-u24} */
47850 {
47851 { 0, 0, 0, 0 },
47852 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47853 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86830000 }
47854 },
47855/* inc.w $Dst32RnUnprefixedHI */
47856 {
47857 { 0, 0, 0, 0 },
47858 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47859 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa90e }
47860 },
47861/* inc.w $Dst32AnUnprefixedHI */
47862 {
47863 { 0, 0, 0, 0 },
47864 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47865 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18e }
47866 },
47867/* inc.w [$Dst32AnUnprefixed] */
47868 {
47869 { 0, 0, 0, 0 },
47870 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47871 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa10e }
47872 },
47873/* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47874 {
47875 { 0, 0, 0, 0 },
47876 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47877 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30e00 }
47878 },
47879/* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47880 {
47881 { 0, 0, 0, 0 },
47882 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47883 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50e0000 }
47884 },
47885/* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47886 {
47887 { 0, 0, 0, 0 },
47888 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47889 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70e0000 }
47890 },
47891/* inc.w ${Dsp-16-u8}[sb] */
47892 {
47893 { 0, 0, 0, 0 },
47894 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47895 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38e00 }
47896 },
47897/* inc.w ${Dsp-16-u16}[sb] */
47898 {
47899 { 0, 0, 0, 0 },
47900 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47901 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58e0000 }
47902 },
47903/* inc.w ${Dsp-16-s8}[fb] */
47904 {
47905 { 0, 0, 0, 0 },
47906 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47907 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ce00 }
47908 },
47909/* inc.w ${Dsp-16-s16}[fb] */
47910 {
47911 { 0, 0, 0, 0 },
47912 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47913 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ce0000 }
47914 },
47915/* inc.w ${Dsp-16-u16} */
47916 {
47917 { 0, 0, 0, 0 },
47918 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47919 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ce0000 }
47920 },
47921/* inc.w ${Dsp-16-u24} */
47922 {
47923 { 0, 0, 0, 0 },
47924 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47925 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa78e0000 }
47926 },
47927/* inc.b $Dst32RnUnprefixedQI */
47928 {
47929 { 0, 0, 0, 0 },
47930 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47931 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa80e }
47932 },
47933/* inc.b $Dst32AnUnprefixedQI */
47934 {
47935 { 0, 0, 0, 0 },
47936 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47937 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa08e }
47938 },
47939/* inc.b [$Dst32AnUnprefixed] */
47940 {
47941 { 0, 0, 0, 0 },
47942 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47943 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa00e }
47944 },
47945/* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47946 {
47947 { 0, 0, 0, 0 },
47948 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47949 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20e00 }
47950 },
47951/* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47952 {
47953 { 0, 0, 0, 0 },
47954 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47955 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40e0000 }
47956 },
47957/* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47958 {
47959 { 0, 0, 0, 0 },
47960 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47961 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60e0000 }
47962 },
47963/* inc.b ${Dsp-16-u8}[sb] */
47964 {
47965 { 0, 0, 0, 0 },
47966 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47967 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28e00 }
47968 },
47969/* inc.b ${Dsp-16-u16}[sb] */
47970 {
47971 { 0, 0, 0, 0 },
47972 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47973 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48e0000 }
47974 },
47975/* inc.b ${Dsp-16-s8}[fb] */
47976 {
47977 { 0, 0, 0, 0 },
47978 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47979 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ce00 }
47980 },
47981/* inc.b ${Dsp-16-s16}[fb] */
47982 {
47983 { 0, 0, 0, 0 },
47984 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47985 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ce0000 }
47986 },
47987/* inc.b ${Dsp-16-u16} */
47988 {
47989 { 0, 0, 0, 0 },
47990 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47991 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ce0000 }
47992 },
47993/* inc.b ${Dsp-16-u24} */
47994 {
47995 { 0, 0, 0, 0 },
47996 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47997 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa68e0000 }
47998 },
47999/* inc.b r0l */
48000 {
48001 { 0, 0, 0, 0 },
48002 { { MNEM, ' ', 'r', '0', 'l', 0 } },
c6552317 48003 & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xa4 }
49f58d10
JB		 48004 },
48005/* inc.b r0h */
48006 {
48007 { 0, 0, 0, 0 },
48008 { { MNEM, ' ', 'r', '0', 'h', 0 } },
c6552317 48009 & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xa3 }
49f58d10
JB		 48010 },
48011/* inc.b ${Dsp-8-u8}[sb] */
48012 {
48013 { 0, 0, 0, 0 },
48014 { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
c6552317 48015 & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xa500 }
49f58d10
JB		 48016 },
48017/* inc.b ${Dsp-8-s8}[fb] */
48018 {
48019 { 0, 0, 0, 0 },
48020 { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
c6552317 48021 & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xa600 }
49f58d10
JB		 48022 },
48023/* inc.b ${Dsp-8-u16} */
48024 {
48025 { 0, 0, 0, 0 },
48026 { { MNEM, ' ', OP (DSP_8_U16), 0 } },
c6552317 48027 & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xa70000 }
49f58d10
JB		 48028 },
48029/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48030 {
48031 { 0, 0, 0, 0 },
48032 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48033 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990000 }
48034 },
48035/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
48036 {
48037 { 0, 0, 0, 0 },
48038 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48039 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992000 }
48040 },
48041/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
48042 {
48043 { 0, 0, 0, 0 },
48044 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48045 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993000 }
48046 },
48047/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48048 {
48049 { 0, 0, 0, 0 },
48050 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48051 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918000 }
48052 },
48053/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
48054 {
48055 { 0, 0, 0, 0 },
48056 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48057 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a000 }
48058 },
48059/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
48060 {
48061 { 0, 0, 0, 0 },
48062 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48063 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b000 }
48064 },
48065/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48066 {
48067 { 0, 0, 0, 0 },
48068 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48069 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910000 }
48070 },
48071/* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48072 {
48073 { 0, 0, 0, 0 },
48074 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48075 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912000 }
48076 },
48077/* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48078 {
48079 { 0, 0, 0, 0 },
48080 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48081 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913000 }
48082 },
48083/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48084 {
48085 { 0, 0, 0, 0 },
48086 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48087 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93000000 }
48088 },
48089/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48090 {
48091 { 0, 0, 0, 0 },
48092 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48093 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93200000 }
48094 },
48095/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48096 {
48097 { 0, 0, 0, 0 },
48098 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48099 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93300000 }
48100 },
48101/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48102 {
48103 { 0, 0, 0, 0 },
48104 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48105 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95000000 }
48106 },
48107/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48108 {
48109 { 0, 0, 0, 0 },
48110 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48111 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95200000 }
48112 },
48113/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48114 {
48115 { 0, 0, 0, 0 },
48116 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48117 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95300000 }
48118 },
48119/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48120 {
48121 { 0, 0, 0, 0 },
48122 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48123 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97000000 }
48124 },
48125/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48126 {
48127 { 0, 0, 0, 0 },
48128 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48129 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97200000 }
48130 },
48131/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48132 {
48133 { 0, 0, 0, 0 },
48134 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48135 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97300000 }
48136 },
48137/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48138 {
48139 { 0, 0, 0, 0 },
48140 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48141 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93800000 }
48142 },
48143/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48144 {
48145 { 0, 0, 0, 0 },
48146 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48147 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a00000 }
48148 },
48149/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48150 {
48151 { 0, 0, 0, 0 },
48152 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48153 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b00000 }
48154 },
48155/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48156 {
48157 { 0, 0, 0, 0 },
48158 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48159 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95800000 }
48160 },
48161/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48162 {
48163 { 0, 0, 0, 0 },
48164 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48165 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a00000 }
48166 },
48167/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48168 {
48169 { 0, 0, 0, 0 },
48170 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48171 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b00000 }
48172 },
48173/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48174 {
48175 { 0, 0, 0, 0 },
48176 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48177 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c00000 }
48178 },
48179/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48180 {
48181 { 0, 0, 0, 0 },
48182 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48183 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e00000 }
48184 },
48185/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48186 {
48187 { 0, 0, 0, 0 },
48188 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48189 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f00000 }
48190 },
48191/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48192 {
48193 { 0, 0, 0, 0 },
48194 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48195 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c00000 }
48196 },
48197/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48198 {
48199 { 0, 0, 0, 0 },
48200 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48201 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e00000 }
48202 },
48203/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48204 {
48205 { 0, 0, 0, 0 },
48206 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48207 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f00000 }
48208 },
48209/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48210 {
48211 { 0, 0, 0, 0 },
48212 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
48213 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c00000 }
48214 },
48215/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48216 {
48217 { 0, 0, 0, 0 },
48218 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
48219 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e00000 }
48220 },
48221/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48222 {
48223 { 0, 0, 0, 0 },
48224 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
48225 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f00000 }
48226 },
48227/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48228 {
48229 { 0, 0, 0, 0 },
48230 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
48231 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97800000 }
48232 },
48233/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48234 {
48235 { 0, 0, 0, 0 },
48236 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
48237 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a00000 }
48238 },
48239/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48240 {
48241 { 0, 0, 0, 0 },
48242 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
48243 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b00000 }
48244 },
48245/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48246 {
48247 { 0, 0, 0, 0 },
48248 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48249 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9000000 }
48250 },
48251/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
48252 {
48253 { 0, 0, 0, 0 },
48254 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48255 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9200000 }
48256 },
48257/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
48258 {
48259 { 0, 0, 0, 0 },
48260 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48261 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9300000 }
48262 },
48263/* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
48264 {
48265 { 0, 0, 0, 0 },
48266 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48267 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9300000 }
48268 },
48269/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48270 {
48271 { 0, 0, 0, 0 },
48272 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48273 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1800000 }
48274 },
48275/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
48276 {
48277 { 0, 0, 0, 0 },
48278 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48279 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a00000 }
48280 },
48281/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
48282 {
48283 { 0, 0, 0, 0 },
48284 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48285 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b00000 }
48286 },
48287/* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
48288 {
48289 { 0, 0, 0, 0 },
48290 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48291 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b00000 }
48292 },
48293/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48294 {
48295 { 0, 0, 0, 0 },
48296 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48297 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1000000 }
48298 },
48299/* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
48300 {
48301 { 0, 0, 0, 0 },
48302 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48303 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1200000 }
48304 },
48305/* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
48306 {
48307 { 0, 0, 0, 0 },
48308 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48309 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1300000 }
48310 },
48311/* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
48312 {
48313 { 0, 0, 0, 0 },
48314 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48315 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1300000 }
48316 },
48317/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48318 {
48319 { 0, 0, 0, 0 },
48320 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48321 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3000000 }
48322 },
48323/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48324 {
48325 { 0, 0, 0, 0 },
48326 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48327 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3200000 }
48328 },
48329/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48330 {
48331 { 0, 0, 0, 0 },
48332 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48333 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3300000 }
48334 },
48335/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
48336 {
48337 { 0, 0, 0, 0 },
48338 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48339 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3300000 }
48340 },
48341/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48342 {
48343 { 0, 0, 0, 0 },
48344 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48345 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5000000 }
48346 },
48347/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48348 {
48349 { 0, 0, 0, 0 },
48350 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48351 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5200000 }
48352 },
48353/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48354 {
48355 { 0, 0, 0, 0 },
48356 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48357 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5300000 }
48358 },
48359/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
48360 {
48361 { 0, 0, 0, 0 },
48362 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48363 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5300000 }
48364 },
48365/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48366 {
48367 { 0, 0, 0, 0 },
48368 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48369 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7000000 }
48370 },
48371/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48372 {
48373 { 0, 0, 0, 0 },
48374 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48375 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7200000 }
48376 },
48377/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48378 {
48379 { 0, 0, 0, 0 },
48380 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48381 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7300000 }
48382 },
48383/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
48384 {
48385 { 0, 0, 0, 0 },
48386 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48387 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7300000 }
48388 },
48389/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
48390 {
48391 { 0, 0, 0, 0 },
48392 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48393 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3800000 }
48394 },
48395/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
48396 {
48397 { 0, 0, 0, 0 },
48398 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48399 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a00000 }
48400 },
48401/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
48402 {
48403 { 0, 0, 0, 0 },
48404 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48405 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b00000 }
48406 },
48407/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
48408 {
48409 { 0, 0, 0, 0 },
48410 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48411 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b00000 }
48412 },
48413/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
48414 {
48415 { 0, 0, 0, 0 },
48416 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48417 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5800000 }
48418 },
48419/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
48420 {
48421 { 0, 0, 0, 0 },
48422 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48423 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a00000 }
48424 },
48425/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
48426 {
48427 { 0, 0, 0, 0 },
48428 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48429 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b00000 }
48430 },
48431/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
48432 {
48433 { 0, 0, 0, 0 },
48434 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48435 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b00000 }
48436 },
48437/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
48438 {
48439 { 0, 0, 0, 0 },
48440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48441 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c00000 }
48442 },
48443/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
48444 {
48445 { 0, 0, 0, 0 },
48446 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48447 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e00000 }
48448 },
48449/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
48450 {
48451 { 0, 0, 0, 0 },
48452 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48453 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f00000 }
48454 },
48455/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
48456 {
48457 { 0, 0, 0, 0 },
48458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48459 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f00000 }
48460 },
48461/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
48462 {
48463 { 0, 0, 0, 0 },
48464 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48465 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c00000 }
48466 },
48467/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
48468 {
48469 { 0, 0, 0, 0 },
48470 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48471 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e00000 }
48472 },
48473/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
48474 {
48475 { 0, 0, 0, 0 },
48476 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48477 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f00000 }
48478 },
48479/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
48480 {
48481 { 0, 0, 0, 0 },
48482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48483 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f00000 }
48484 },
48485/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
48486 {
48487 { 0, 0, 0, 0 },
48488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
48489 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c00000 }
48490 },
48491/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
48492 {
48493 { 0, 0, 0, 0 },
48494 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
48495 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e00000 }
48496 },
48497/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
48498 {
48499 { 0, 0, 0, 0 },
48500 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
48501 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f00000 }
48502 },
48503/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
48504 {
48505 { 0, 0, 0, 0 },
48506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
48507 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f00000 }
48508 },
48509/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
48510 {
48511 { 0, 0, 0, 0 },
48512 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
48513 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7800000 }
48514 },
48515/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
48516 {
48517 { 0, 0, 0, 0 },
48518 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
48519 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a00000 }
48520 },
48521/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
48522 {
48523 { 0, 0, 0, 0 },
48524 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
48525 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b00000 }
48526 },
48527/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
48528 {
48529 { 0, 0, 0, 0 },
48530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
48531 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b00000 }
48532 },
48533/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48534 {
48535 { 0, 0, 0, 0 },
48536 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48537 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9000000 }
48538 },
48539/* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
48540 {
48541 { 0, 0, 0, 0 },
48542 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48543 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9200000 }
48544 },
48545/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48546 {
48547 { 0, 0, 0, 0 },
48548 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48549 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1800000 }
48550 },
48551/* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
48552 {
48553 { 0, 0, 0, 0 },
48554 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48555 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a00000 }
48556 },
48557/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48558 {
48559 { 0, 0, 0, 0 },
48560 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48561 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1000000 }
48562 },
48563/* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
48564 {
48565 { 0, 0, 0, 0 },
48566 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48567 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1200000 }
48568 },
48569/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
48570 {
48571 { 0, 0, 0, 0 },
48572 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48573 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3000000 }
48574 },
48575/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
48576 {
48577 { 0, 0, 0, 0 },
48578 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48579 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3200000 }
48580 },
48581/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
48582 {
48583 { 0, 0, 0, 0 },
48584 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48585 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5000000 }
48586 },
48587/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
48588 {
48589 { 0, 0, 0, 0 },
48590 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48591 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5200000 }
48592 },
48593/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
48594 {
48595 { 0, 0, 0, 0 },
48596 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48597 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7000000 }
48598 },
48599/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
48600 {
48601 { 0, 0, 0, 0 },
48602 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48603 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7200000 }
48604 },
48605/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
48606 {
48607 { 0, 0, 0, 0 },
48608 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
48609 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3800000 }
48610 },
48611/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
48612 {
48613 { 0, 0, 0, 0 },
48614 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
48615 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a00000 }
48616 },
48617/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
48618 {
48619 { 0, 0, 0, 0 },
48620 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
48621 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5800000 }
48622 },
48623/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
48624 {
48625 { 0, 0, 0, 0 },
48626 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
48627 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a00000 }
48628 },
48629/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
48630 {
48631 { 0, 0, 0, 0 },
48632 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
48633 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c00000 }
48634 },
48635/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
48636 {
48637 { 0, 0, 0, 0 },
48638 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
48639 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e00000 }
48640 },
48641/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
48642 {
48643 { 0, 0, 0, 0 },
48644 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
48645 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c00000 }
48646 },
48647/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
48648 {
48649 { 0, 0, 0, 0 },
48650 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
48651 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e00000 }
48652 },
48653/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
48654 {
48655 { 0, 0, 0, 0 },
48656 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
48657 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c00000 }
48658 },
48659/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
48660 {
48661 { 0, 0, 0, 0 },
48662 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
48663 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e00000 }
48664 },
48665/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
48666 {
48667 { 0, 0, 0, 0 },
48668 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
48669 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7800000 }
48670 },
48671/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
48672 {
48673 { 0, 0, 0, 0 },
48674 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
48675 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a00000 }
48676 },
48677/* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
48678 {
48679 { 0, 0, 0, 0 },
48680 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48681 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc900 }
48682 },
48683/* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
48684 {
48685 { 0, 0, 0, 0 },
48686 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48687 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8920 }
48688 },
48689/* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48690 {
48691 { 0, 0, 0, 0 },
48692 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48693 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8900 }
48694 },
48695/* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
48696 {
48697 { 0, 0, 0, 0 },
48698 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48699 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc180 }
48700 },
48701/* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
48702 {
48703 { 0, 0, 0, 0 },
48704 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48705 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a0 }
48706 },
48707/* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48708 {
48709 { 0, 0, 0, 0 },
48710 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48711 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8180 }
48712 },
48713/* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
48714 {
48715 { 0, 0, 0, 0 },
48716 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48717 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc100 }
48718 },
48719/* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
48720 {
48721 { 0, 0, 0, 0 },
48722 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48723 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8120 }
48724 },
48725/* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48726 {
48727 { 0, 0, 0, 0 },
48728 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48729 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8100 }
48730 },
48731/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48732 {
48733 { 0, 0, 0, 0 },
48734 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48735 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30000 }
48736 },
48737/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48738 {
48739 { 0, 0, 0, 0 },
48740 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48741 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832000 }
48742 },
48743/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
48744 {
48745 { 0, 0, 0, 0 },
48746 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48747 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830000 }
48748 },
48749/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48750 {
48751 { 0, 0, 0, 0 },
48752 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48753 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5000000 }
48754 },
48755/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48756 {
48757 { 0, 0, 0, 0 },
48758 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48759 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85200000 }
48760 },
48761/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
48762 {
48763 { 0, 0, 0, 0 },
48764 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48765 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85000000 }
48766 },
48767/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
48768 {
48769 { 0, 0, 0, 0 },
48770 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48771 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7000000 }
48772 },
48773/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
48774 {
48775 { 0, 0, 0, 0 },
48776 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48777 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87200000 }
48778 },
48779/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
48780 {
48781 { 0, 0, 0, 0 },
48782 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48783 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87000000 }
48784 },
48785/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
48786 {
48787 { 0, 0, 0, 0 },
48788 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48789 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38000 }
48790 },
48791/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
48792 {
48793 { 0, 0, 0, 0 },
48794 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48795 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a000 }
48796 },
48797/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
48798 {
48799 { 0, 0, 0, 0 },
48800 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48801 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838000 }
48802 },
48803/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
48804 {
48805 { 0, 0, 0, 0 },
48806 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48807 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5800000 }
48808 },
48809/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
48810 {
48811 { 0, 0, 0, 0 },
48812 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48813 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a00000 }
48814 },
48815/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
48816 {
48817 { 0, 0, 0, 0 },
48818 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48819 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85800000 }
48820 },
48821/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
48822 {
48823 { 0, 0, 0, 0 },
48824 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48825 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c000 }
48826 },
48827/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
48828 {
48829 { 0, 0, 0, 0 },
48830 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48831 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e000 }
48832 },
48833/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
48834 {
48835 { 0, 0, 0, 0 },
48836 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48837 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c000 }
48838 },
48839/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
48840 {
48841 { 0, 0, 0, 0 },
48842 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48843 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c00000 }
48844 },
48845/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
48846 {
48847 { 0, 0, 0, 0 },
48848 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48849 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e00000 }
48850 },
48851/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
48852 {
48853 { 0, 0, 0, 0 },
48854 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48855 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c00000 }
48856 },
48857/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
48858 {
48859 { 0, 0, 0, 0 },
48860 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
48861 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c00000 }
48862 },
48863/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
48864 {
48865 { 0, 0, 0, 0 },
48866 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
48867 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e00000 }
48868 },
48869/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
48870 {
48871 { 0, 0, 0, 0 },
48872 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
48873 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c00000 }
48874 },
48875/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
48876 {
48877 { 0, 0, 0, 0 },
48878 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
48879 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7800000 }
48880 },
48881/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
48882 {
48883 { 0, 0, 0, 0 },
48884 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
48885 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a00000 }
48886 },
48887/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
48888 {
48889 { 0, 0, 0, 0 },
48890 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
48891 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87800000 }
48892 },
48893/* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48894 {
48895 { 0, 0, 0, 0 },
48896 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
48897 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2f000000 }
48898 },
48899/* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48900 {
48901 { 0, 0, 0, 0 },
48902 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
48903 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3f000000 }
48904 },
48905/* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48906 {
48907 { 0, 0, 0, 0 },
48908 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
48909 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1f000000 }
48910 },
48911/* sub.w${S} #${Imm-8-HI},r0 */
48912 {
48913 { 0, 0, 0, 0 },
48914 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
48915 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xf0000 }
48916 },
48917/* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48918 {
48919 { 0, 0, 0, 0 },
48920 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
48921 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2e0000 }
48922 },
48923/* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48924 {
48925 { 0, 0, 0, 0 },
48926 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
48927 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3e0000 }
48928 },
48929/* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48930 {
48931 { 0, 0, 0, 0 },
48932 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
48933 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1e000000 }
48934 },
48935/* sub.b${S} #${Imm-8-QI},r0l */
48936 {
48937 { 0, 0, 0, 0 },
48938 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
48939 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xe00 }
48940 },
48941/* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
48942 {
48943 { 0, 0, 0, 0 },
48944 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48945 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x98310000 }
48946 },
48947/* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
48948 {
48949 { 0, 0, 0, 0 },
48950 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48951 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90b10000 }
48952 },
48953/* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
48954 {
48955 { 0, 0, 0, 0 },
48956 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48957 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x90310000 }
48958 },
48959/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
48960 {
48961 { 0, 0, 0, 0 },
48962 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48963 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92310000 }
48964 },
48965/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
48966 {
48967 { 0, 0, 0, 0 },
48968 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48969 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92b10000 }
48970 },
48971/* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
48972 {
48973 { 0, 0, 0, 0 },
48974 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48975 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92f10000 }
48976 },
48977/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
48978 {
48979 { 0, 0, 0, 0 },
48980 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48981 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94310000 }
48982 },
48983/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
48984 {
48985 { 0, 0, 0, 0 },
48986 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48987 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94b10000 }
48988 },
48989/* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
48990 {
48991 { 0, 0, 0, 0 },
48992 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48993 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94f10000 }
48994 },
48995/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
48996 {
48997 { 0, 0, 0, 0 },
48998 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
48999 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96f10000 }
49000 },
49001/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
49002 {
49003 { 0, 0, 0, 0 },
49004 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49005 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96310000 }
49006 },
49007/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
49008 {
49009 { 0, 0, 0, 0 },
49010 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
49011 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96b10000 }
49012 },
49013/* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
49014 {
49015 { 0, 0, 0, 0 },
49016 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
5348b81e 49017 & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x28 }
49f58d10
JB		 49018 },
49019/* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
49020 {
49021 { 0, 0, 0, 0 },
49022 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 49023 & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2900 }
49f58d10
JB		 49024 },
49025/* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
49026 {
49027 { 0, 0, 0, 0 },
49028 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 49029 & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2a00 }
49f58d10
JB		 49030 },
49031/* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
49032 {
49033 { 0, 0, 0, 0 },
49034 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
5348b81e 49035 & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x2b0000 }
49f58d10
JB		 49036 },
49037/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49038 {
49039 { 0, 0, 0, 0 },
49040 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49041 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990a00 }
49042 },
49043/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
49044 {
49045 { 0, 0, 0, 0 },
49046 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49047 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992a00 }
49048 },
49049/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
49050 {
49051 { 0, 0, 0, 0 },
49052 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49053 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993a00 }
49054 },
49055/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49056 {
49057 { 0, 0, 0, 0 },
49058 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49059 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918a00 }
49060 },
49061/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
49062 {
49063 { 0, 0, 0, 0 },
49064 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49065 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91aa00 }
49066 },
49067/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
49068 {
49069 { 0, 0, 0, 0 },
49070 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49071 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ba00 }
49072 },
49073/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49074 {
49075 { 0, 0, 0, 0 },
49076 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49077 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910a00 }
49078 },
49079/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49080 {
49081 { 0, 0, 0, 0 },
49082 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49083 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912a00 }
49084 },
49085/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49086 {
49087 { 0, 0, 0, 0 },
49088 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49089 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913a00 }
49090 },
49091/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49092 {
49093 { 0, 0, 0, 0 },
49094 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49095 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930a0000 }
49096 },
49097/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49098 {
49099 { 0, 0, 0, 0 },
49100 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49101 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932a0000 }
49102 },
49103/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49104 {
49105 { 0, 0, 0, 0 },
49106 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49107 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933a0000 }
49108 },
49109/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49110 {
49111 { 0, 0, 0, 0 },
49112 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49113 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950a0000 }
49114 },
49115/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49116 {
49117 { 0, 0, 0, 0 },
49118 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49119 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952a0000 }
49120 },
49121/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49122 {
49123 { 0, 0, 0, 0 },
49124 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49125 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953a0000 }
49126 },
49127/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49128 {
49129 { 0, 0, 0, 0 },
49130 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49131 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970a0000 }
49132 },
49133/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49134 {
49135 { 0, 0, 0, 0 },
49136 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49137 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972a0000 }
49138 },
49139/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49140 {
49141 { 0, 0, 0, 0 },
49142 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49143 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973a0000 }
49144 },
49145/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49146 {
49147 { 0, 0, 0, 0 },
49148 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49149 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938a0000 }
49150 },
49151/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49152 {
49153 { 0, 0, 0, 0 },
49154 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49155 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93aa0000 }
49156 },
49157/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49158 {
49159 { 0, 0, 0, 0 },
49160 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49161 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ba0000 }
49162 },
49163/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49164 {
49165 { 0, 0, 0, 0 },
49166 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49167 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958a0000 }
49168 },
49169/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49170 {
49171 { 0, 0, 0, 0 },
49172 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49173 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95aa0000 }
49174 },
49175/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49176 {
49177 { 0, 0, 0, 0 },
49178 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49179 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ba0000 }
49180 },
49181/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49182 {
49183 { 0, 0, 0, 0 },
49184 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49185 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ca0000 }
49186 },
49187/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49188 {
49189 { 0, 0, 0, 0 },
49190 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49191 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ea0000 }
49192 },
49193/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49194 {
49195 { 0, 0, 0, 0 },
49196 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49197 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fa0000 }
49198 },
49199/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49200 {
49201 { 0, 0, 0, 0 },
49202 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49203 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ca0000 }
49204 },
49205/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49206 {
49207 { 0, 0, 0, 0 },
49208 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49209 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ea0000 }
49210 },
49211/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49212 {
49213 { 0, 0, 0, 0 },
49214 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49215 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fa0000 }
49216 },
49217/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49218 {
49219 { 0, 0, 0, 0 },
49220 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
49221 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ca0000 }
49222 },
49223/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49224 {
49225 { 0, 0, 0, 0 },
49226 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
49227 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ea0000 }
49228 },
49229/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49230 {
49231 { 0, 0, 0, 0 },
49232 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
49233 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fa0000 }
49234 },
49235/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49236 {
49237 { 0, 0, 0, 0 },
49238 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
49239 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978a0000 }
49240 },
49241/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49242 {
49243 { 0, 0, 0, 0 },
49244 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
49245 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97aa0000 }
49246 },
49247/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49248 {
49249 { 0, 0, 0, 0 },
49250 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
49251 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ba0000 }
49252 },
49253/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49254 {
49255 { 0, 0, 0, 0 },
49256 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49257 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90a0000 }
49258 },
49259/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
49260 {
49261 { 0, 0, 0, 0 },
49262 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49263 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92a0000 }
49264 },
49265/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
49266 {
49267 { 0, 0, 0, 0 },
49268 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49269 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93a0000 }
49270 },
49271/* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
49272 {
49273 { 0, 0, 0, 0 },
49274 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49275 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93a0000 }
49276 },
49277/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49278 {
49279 { 0, 0, 0, 0 },
49280 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49281 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18a0000 }
49282 },
49283/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
49284 {
49285 { 0, 0, 0, 0 },
49286 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49287 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1aa0000 }
49288 },
49289/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
49290 {
49291 { 0, 0, 0, 0 },
49292 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49293 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ba0000 }
49294 },
49295/* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
49296 {
49297 { 0, 0, 0, 0 },
49298 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49299 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ba0000 }
49300 },
49301/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49302 {
49303 { 0, 0, 0, 0 },
49304 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49305 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10a0000 }
49306 },
49307/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49308 {
49309 { 0, 0, 0, 0 },
49310 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49311 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12a0000 }
49312 },
49313/* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49314 {
49315 { 0, 0, 0, 0 },
49316 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49317 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13a0000 }
49318 },
49319/* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49320 {
49321 { 0, 0, 0, 0 },
49322 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49323 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13a0000 }
49324 },
49325/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49326 {
49327 { 0, 0, 0, 0 },
49328 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49329 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30a0000 }
49330 },
49331/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49332 {
49333 { 0, 0, 0, 0 },
49334 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49335 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32a0000 }
49336 },
49337/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49338 {
49339 { 0, 0, 0, 0 },
49340 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49341 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33a0000 }
49342 },
49343/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49344 {
49345 { 0, 0, 0, 0 },
49346 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49347 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33a0000 }
49348 },
49349/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49350 {
49351 { 0, 0, 0, 0 },
49352 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49353 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50a0000 }
49354 },
49355/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49356 {
49357 { 0, 0, 0, 0 },
49358 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49359 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52a0000 }
49360 },
49361/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49362 {
49363 { 0, 0, 0, 0 },
49364 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49365 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53a0000 }
49366 },
49367/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49368 {
49369 { 0, 0, 0, 0 },
49370 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49371 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53a0000 }
49372 },
49373/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49374 {
49375 { 0, 0, 0, 0 },
49376 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49377 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70a0000 }
49378 },
49379/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49380 {
49381 { 0, 0, 0, 0 },
49382 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49383 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72a0000 }
49384 },
49385/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49386 {
49387 { 0, 0, 0, 0 },
49388 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49389 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73a0000 }
49390 },
49391/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49392 {
49393 { 0, 0, 0, 0 },
49394 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49395 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73a0000 }
49396 },
49397/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49398 {
49399 { 0, 0, 0, 0 },
49400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49401 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38a0000 }
49402 },
49403/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49404 {
49405 { 0, 0, 0, 0 },
49406 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49407 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3aa0000 }
49408 },
49409/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49410 {
49411 { 0, 0, 0, 0 },
49412 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49413 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ba0000 }
49414 },
49415/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49416 {
49417 { 0, 0, 0, 0 },
49418 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49419 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3ba0000 }
49420 },
49421/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49422 {
49423 { 0, 0, 0, 0 },
49424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49425 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58a0000 }
49426 },
49427/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49428 {
49429 { 0, 0, 0, 0 },
49430 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49431 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5aa0000 }
49432 },
49433/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49434 {
49435 { 0, 0, 0, 0 },
49436 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49437 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ba0000 }
49438 },
49439/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49440 {
49441 { 0, 0, 0, 0 },
49442 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49443 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5ba0000 }
49444 },
49445/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49446 {
49447 { 0, 0, 0, 0 },
49448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49449 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ca0000 }
49450 },
49451/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49452 {
49453 { 0, 0, 0, 0 },
49454 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49455 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ea0000 }
49456 },
49457/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49458 {
49459 { 0, 0, 0, 0 },
49460 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49461 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fa0000 }
49462 },
49463/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49464 {
49465 { 0, 0, 0, 0 },
49466 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49467 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fa0000 }
49468 },
49469/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49470 {
49471 { 0, 0, 0, 0 },
49472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49473 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ca0000 }
49474 },
49475/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49476 {
49477 { 0, 0, 0, 0 },
49478 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49479 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ea0000 }
49480 },
49481/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49482 {
49483 { 0, 0, 0, 0 },
49484 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49485 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fa0000 }
49486 },
49487/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49488 {
49489 { 0, 0, 0, 0 },
49490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49491 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fa0000 }
49492 },
49493/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49494 {
49495 { 0, 0, 0, 0 },
49496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49497 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ca0000 }
49498 },
49499/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49500 {
49501 { 0, 0, 0, 0 },
49502 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49503 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ea0000 }
49504 },
49505/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49506 {
49507 { 0, 0, 0, 0 },
49508 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49509 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fa0000 }
49510 },
49511/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
49512 {
49513 { 0, 0, 0, 0 },
49514 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
49515 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fa0000 }
49516 },
49517/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49518 {
49519 { 0, 0, 0, 0 },
49520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49521 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78a0000 }
49522 },
49523/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49524 {
49525 { 0, 0, 0, 0 },
49526 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49527 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7aa0000 }
49528 },
49529/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49530 {
49531 { 0, 0, 0, 0 },
49532 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49533 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ba0000 }
49534 },
49535/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
49536 {
49537 { 0, 0, 0, 0 },
49538 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
49539 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7ba0000 }
49540 },
49541/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49542 {
49543 { 0, 0, 0, 0 },
49544 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49545 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90a0000 }
49546 },
49547/* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
49548 {
49549 { 0, 0, 0, 0 },
49550 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49551 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92a0000 }
49552 },
49553/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49554 {
49555 { 0, 0, 0, 0 },
49556 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49557 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18a0000 }
49558 },
49559/* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
49560 {
49561 { 0, 0, 0, 0 },
49562 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49563 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1aa0000 }
49564 },
49565/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49566 {
49567 { 0, 0, 0, 0 },
49568 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49569 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10a0000 }
49570 },
49571/* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49572 {
49573 { 0, 0, 0, 0 },
49574 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49575 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12a0000 }
49576 },
49577/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49578 {
49579 { 0, 0, 0, 0 },
49580 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49581 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30a0000 }
49582 },
49583/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49584 {
49585 { 0, 0, 0, 0 },
49586 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49587 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32a0000 }
49588 },
49589/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49590 {
49591 { 0, 0, 0, 0 },
49592 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49593 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50a0000 }
49594 },
49595/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49596 {
49597 { 0, 0, 0, 0 },
49598 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49599 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52a0000 }
49600 },
49601/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49602 {
49603 { 0, 0, 0, 0 },
49604 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49605 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70a0000 }
49606 },
49607/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49608 {
49609 { 0, 0, 0, 0 },
49610 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49611 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72a0000 }
49612 },
49613/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49614 {
49615 { 0, 0, 0, 0 },
49616 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49617 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38a0000 }
49618 },
49619/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49620 {
49621 { 0, 0, 0, 0 },
49622 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49623 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3aa0000 }
49624 },
49625/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49626 {
49627 { 0, 0, 0, 0 },
49628 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49629 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58a0000 }
49630 },
49631/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49632 {
49633 { 0, 0, 0, 0 },
49634 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49635 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5aa0000 }
49636 },
49637/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49638 {
49639 { 0, 0, 0, 0 },
49640 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49641 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ca0000 }
49642 },
49643/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49644 {
49645 { 0, 0, 0, 0 },
49646 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49647 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ea0000 }
49648 },
49649/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49650 {
49651 { 0, 0, 0, 0 },
49652 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49653 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ca0000 }
49654 },
49655/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49656 {
49657 { 0, 0, 0, 0 },
49658 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49659 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ea0000 }
49660 },
49661/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49662 {
49663 { 0, 0, 0, 0 },
49664 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
49665 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ca0000 }
49666 },
49667/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
49668 {
49669 { 0, 0, 0, 0 },
49670 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
49671 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ea0000 }
49672 },
49673/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49674 {
49675 { 0, 0, 0, 0 },
49676 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
49677 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78a0000 }
49678 },
49679/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
49680 {
49681 { 0, 0, 0, 0 },
49682 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
49683 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7aa0000 }
49684 },
49685/* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
49686 {
49687 { 0, 0, 0, 0 },
49688 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49689 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90a }
49690 },
49691/* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
49692 {
49693 { 0, 0, 0, 0 },
49694 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49695 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892a }
49696 },
49697/* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49698 {
49699 { 0, 0, 0, 0 },
49700 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49701 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890a }
49702 },
49703/* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
49704 {
49705 { 0, 0, 0, 0 },
49706 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49707 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18a }
49708 },
49709/* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
49710 {
49711 { 0, 0, 0, 0 },
49712 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49713 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81aa }
49714 },
49715/* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49716 {
49717 { 0, 0, 0, 0 },
49718 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49719 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818a }
49720 },
49721/* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
49722 {
49723 { 0, 0, 0, 0 },
49724 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49725 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10a }
49726 },
49727/* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
49728 {
49729 { 0, 0, 0, 0 },
49730 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49731 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812a }
49732 },
49733/* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49734 {
49735 { 0, 0, 0, 0 },
49736 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49737 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810a }
49738 },
49739/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49740 {
49741 { 0, 0, 0, 0 },
49742 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49743 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30a00 }
49744 },
49745/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49746 {
49747 { 0, 0, 0, 0 },
49748 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49749 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832a00 }
49750 },
49751/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49752 {
49753 { 0, 0, 0, 0 },
49754 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49755 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830a00 }
49756 },
49757/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49758 {
49759 { 0, 0, 0, 0 },
49760 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49761 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50a0000 }
49762 },
49763/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49764 {
49765 { 0, 0, 0, 0 },
49766 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49767 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852a0000 }
49768 },
49769/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49770 {
49771 { 0, 0, 0, 0 },
49772 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49773 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850a0000 }
49774 },
49775/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49776 {
49777 { 0, 0, 0, 0 },
49778 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49779 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70a0000 }
49780 },
49781/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49782 {
49783 { 0, 0, 0, 0 },
49784 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49785 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872a0000 }
49786 },
49787/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49788 {
49789 { 0, 0, 0, 0 },
49790 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49791 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870a0000 }
49792 },
49793/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49794 {
49795 { 0, 0, 0, 0 },
49796 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49797 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38a00 }
49798 },
49799/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49800 {
49801 { 0, 0, 0, 0 },
49802 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49803 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83aa00 }
49804 },
49805/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49806 {
49807 { 0, 0, 0, 0 },
49808 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49809 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838a00 }
49810 },
49811/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49812 {
49813 { 0, 0, 0, 0 },
49814 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49815 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58a0000 }
49816 },
49817/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49818 {
49819 { 0, 0, 0, 0 },
49820 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49821 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85aa0000 }
49822 },
49823/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49824 {
49825 { 0, 0, 0, 0 },
49826 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49827 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858a0000 }
49828 },
49829/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49830 {
49831 { 0, 0, 0, 0 },
49832 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49833 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ca00 }
49834 },
49835/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49836 {
49837 { 0, 0, 0, 0 },
49838 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49839 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ea00 }
49840 },
49841/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49842 {
49843 { 0, 0, 0, 0 },
49844 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49845 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ca00 }
49846 },
49847/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49848 {
49849 { 0, 0, 0, 0 },
49850 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49851 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ca0000 }
49852 },
49853/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49854 {
49855 { 0, 0, 0, 0 },
49856 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49857 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ea0000 }
49858 },
49859/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49860 {
49861 { 0, 0, 0, 0 },
49862 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49863 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ca0000 }
49864 },
49865/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49866 {
49867 { 0, 0, 0, 0 },
49868 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
49869 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ca0000 }
49870 },
49871/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49872 {
49873 { 0, 0, 0, 0 },
49874 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
49875 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ea0000 }
49876 },
49877/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49878 {
49879 { 0, 0, 0, 0 },
49880 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
49881 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ca0000 }
49882 },
49883/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49884 {
49885 { 0, 0, 0, 0 },
49886 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
49887 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78a0000 }
49888 },
49889/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49890 {
49891 { 0, 0, 0, 0 },
49892 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
49893 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87aa0000 }
49894 },
49895/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49896 {
49897 { 0, 0, 0, 0 },
49898 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
49899 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878a0000 }
49900 },
49901/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49902 {
49903 { 0, 0, 0, 0 },
49904 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49905 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980a00 }
49906 },
49907/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49908 {
49909 { 0, 0, 0, 0 },
49910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49911 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982a00 }
49912 },
49913/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49914 {
49915 { 0, 0, 0, 0 },
49916 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49917 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983a00 }
49918 },
49919/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49920 {
49921 { 0, 0, 0, 0 },
49922 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49923 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908a00 }
49924 },
49925/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49926 {
49927 { 0, 0, 0, 0 },
49928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49929 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90aa00 }
49930 },
49931/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49932 {
49933 { 0, 0, 0, 0 },
49934 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49935 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ba00 }
49936 },
49937/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49938 {
49939 { 0, 0, 0, 0 },
49940 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49941 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900a00 }
49942 },
49943/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49944 {
49945 { 0, 0, 0, 0 },
49946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49947 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902a00 }
49948 },
49949/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49950 {
49951 { 0, 0, 0, 0 },
49952 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49953 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903a00 }
49954 },
49955/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49956 {
49957 { 0, 0, 0, 0 },
49958 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49959 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920a0000 }
49960 },
49961/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49962 {
49963 { 0, 0, 0, 0 },
49964 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49965 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922a0000 }
49966 },
49967/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49968 {
49969 { 0, 0, 0, 0 },
49970 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49971 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923a0000 }
49972 },
49973/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49974 {
49975 { 0, 0, 0, 0 },
49976 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49977 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940a0000 }
49978 },
49979/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49980 {
49981 { 0, 0, 0, 0 },
49982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49983 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942a0000 }
49984 },
49985/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49986 {
49987 { 0, 0, 0, 0 },
49988 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49989 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943a0000 }
49990 },
49991/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49992 {
49993 { 0, 0, 0, 0 },
49994 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49995 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960a0000 }
49996 },
49997/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49998 {
49999 { 0, 0, 0, 0 },
50000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50001 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962a0000 }
50002 },
50003/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
50004 {
50005 { 0, 0, 0, 0 },
50006 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50007 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963a0000 }
50008 },
50009/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
50010 {
50011 { 0, 0, 0, 0 },
50012 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50013 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928a0000 }
50014 },
50015/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50016 {
50017 { 0, 0, 0, 0 },
50018 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50019 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92aa0000 }
50020 },
50021/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50022 {
50023 { 0, 0, 0, 0 },
50024 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50025 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ba0000 }
50026 },
50027/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
50028 {
50029 { 0, 0, 0, 0 },
50030 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50031 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948a0000 }
50032 },
50033/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50034 {
50035 { 0, 0, 0, 0 },
50036 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50037 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94aa0000 }
50038 },
50039/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50040 {
50041 { 0, 0, 0, 0 },
50042 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50043 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ba0000 }
50044 },
50045/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
50046 {
50047 { 0, 0, 0, 0 },
50048 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50049 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ca0000 }
50050 },
50051/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50052 {
50053 { 0, 0, 0, 0 },
50054 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50055 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ea0000 }
50056 },
50057/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50058 {
50059 { 0, 0, 0, 0 },
50060 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50061 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fa0000 }
50062 },
50063/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
50064 {
50065 { 0, 0, 0, 0 },
50066 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
50067 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ca0000 }
50068 },
50069/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
50070 {
50071 { 0, 0, 0, 0 },
50072 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
50073 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ea0000 }
50074 },
50075/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
50076 {
50077 { 0, 0, 0, 0 },
50078 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
50079 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fa0000 }
50080 },
50081/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
50082 {
50083 { 0, 0, 0, 0 },
50084 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
50085 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ca0000 }
50086 },
50087/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50088 {
50089 { 0, 0, 0, 0 },
50090 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50091 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ea0000 }
50092 },
50093/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50094 {
50095 { 0, 0, 0, 0 },
50096 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50097 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fa0000 }
50098 },
50099/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
50100 {
50101 { 0, 0, 0, 0 },
50102 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
50103 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968a0000 }
50104 },
50105/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
50106 {
50107 { 0, 0, 0, 0 },
50108 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
50109 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96aa0000 }
50110 },
50111/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
50112 {
50113 { 0, 0, 0, 0 },
50114 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
50115 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ba0000 }
50116 },
50117/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50118 {
50119 { 0, 0, 0, 0 },
50120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50121 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80a0000 }
50122 },
50123/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
50124 {
50125 { 0, 0, 0, 0 },
50126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50127 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82a0000 }
50128 },
50129/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
50130 {
50131 { 0, 0, 0, 0 },
50132 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50133 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83a0000 }
50134 },
50135/* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
50136 {
50137 { 0, 0, 0, 0 },
50138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50139 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83a0000 }
50140 },
50141/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50142 {
50143 { 0, 0, 0, 0 },
50144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50145 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08a0000 }
50146 },
50147/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
50148 {
50149 { 0, 0, 0, 0 },
50150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50151 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0aa0000 }
50152 },
50153/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
50154 {
50155 { 0, 0, 0, 0 },
50156 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50157 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ba0000 }
50158 },
50159/* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
50160 {
50161 { 0, 0, 0, 0 },
50162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50163 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ba0000 }
50164 },
50165/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50166 {
50167 { 0, 0, 0, 0 },
50168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50169 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00a0000 }
50170 },
50171/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
50172 {
50173 { 0, 0, 0, 0 },
50174 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50175 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02a0000 }
50176 },
50177/* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
50178 {
50179 { 0, 0, 0, 0 },
50180 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50181 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03a0000 }
50182 },
50183/* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
50184 {
50185 { 0, 0, 0, 0 },
50186 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50187 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03a0000 }
50188 },
50189/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
50190 {
50191 { 0, 0, 0, 0 },
50192 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50193 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20a0000 }
50194 },
50195/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
50196 {
50197 { 0, 0, 0, 0 },
50198 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50199 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22a0000 }
50200 },
50201/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
50202 {
50203 { 0, 0, 0, 0 },
50204 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50205 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23a0000 }
50206 },
50207/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
50208 {
50209 { 0, 0, 0, 0 },
50210 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50211 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23a0000 }
50212 },
50213/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
50214 {
50215 { 0, 0, 0, 0 },
50216 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50217 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40a0000 }
50218 },
50219/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
50220 {
50221 { 0, 0, 0, 0 },
50222 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50223 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42a0000 }
50224 },
50225/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
50226 {
50227 { 0, 0, 0, 0 },
50228 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50229 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43a0000 }
50230 },
50231/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
50232 {
50233 { 0, 0, 0, 0 },
50234 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50235 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43a0000 }
50236 },
50237/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
50238 {
50239 { 0, 0, 0, 0 },
50240 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50241 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60a0000 }
50242 },
50243/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
50244 {
50245 { 0, 0, 0, 0 },
50246 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50247 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62a0000 }
50248 },
50249/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
50250 {
50251 { 0, 0, 0, 0 },
50252 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50253 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63a0000 }
50254 },
50255/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
50256 {
50257 { 0, 0, 0, 0 },
50258 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50259 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63a0000 }
50260 },
50261/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
50262 {
50263 { 0, 0, 0, 0 },
50264 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50265 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28a0000 }
50266 },
50267/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50268 {
50269 { 0, 0, 0, 0 },
50270 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50271 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2aa0000 }
50272 },
50273/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
50274 {
50275 { 0, 0, 0, 0 },
50276 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50277 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ba0000 }
50278 },
50279/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50280 {
50281 { 0, 0, 0, 0 },
50282 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50283 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2ba0000 }
50284 },
50285/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
50286 {
50287 { 0, 0, 0, 0 },
50288 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50289 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48a0000 }
50290 },
50291/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50292 {
50293 { 0, 0, 0, 0 },
50294 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50295 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4aa0000 }
50296 },
50297/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
50298 {
50299 { 0, 0, 0, 0 },
50300 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50301 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ba0000 }
50302 },
50303/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50304 {
50305 { 0, 0, 0, 0 },
50306 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50307 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4ba0000 }
50308 },
50309/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
50310 {
50311 { 0, 0, 0, 0 },
50312 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50313 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ca0000 }
50314 },
50315/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50316 {
50317 { 0, 0, 0, 0 },
50318 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50319 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ea0000 }
50320 },
50321/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
50322 {
50323 { 0, 0, 0, 0 },
50324 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50325 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fa0000 }
50326 },
50327/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50328 {
50329 { 0, 0, 0, 0 },
50330 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50331 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fa0000 }
50332 },
50333/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
50334 {
50335 { 0, 0, 0, 0 },
50336 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50337 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ca0000 }
50338 },
50339/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
50340 {
50341 { 0, 0, 0, 0 },
50342 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50343 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ea0000 }
50344 },
50345/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
50346 {
50347 { 0, 0, 0, 0 },
50348 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50349 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fa0000 }
50350 },
50351/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
50352 {
50353 { 0, 0, 0, 0 },
50354 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50355 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fa0000 }
50356 },
50357/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
50358 {
50359 { 0, 0, 0, 0 },
50360 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
50361 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ca0000 }
50362 },
50363/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50364 {
50365 { 0, 0, 0, 0 },
50366 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
50367 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ea0000 }
50368 },
50369/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
50370 {
50371 { 0, 0, 0, 0 },
50372 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
50373 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fa0000 }
50374 },
50375/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
50376 {
50377 { 0, 0, 0, 0 },
50378 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
50379 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fa0000 }
50380 },
50381/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
50382 {
50383 { 0, 0, 0, 0 },
50384 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
50385 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68a0000 }
50386 },
50387/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
50388 {
50389 { 0, 0, 0, 0 },
50390 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
50391 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6aa0000 }
50392 },
50393/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
50394 {
50395 { 0, 0, 0, 0 },
50396 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
50397 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ba0000 }
50398 },
50399/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
50400 {
50401 { 0, 0, 0, 0 },
50402 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
50403 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6ba0000 }
50404 },
50405/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50406 {
50407 { 0, 0, 0, 0 },
50408 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50409 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80a0000 }
50410 },
50411/* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
50412 {
50413 { 0, 0, 0, 0 },
50414 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50415 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82a0000 }
50416 },
50417/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50418 {
50419 { 0, 0, 0, 0 },
50420 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50421 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08a0000 }
50422 },
50423/* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
50424 {
50425 { 0, 0, 0, 0 },
50426 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50427 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0aa0000 }
50428 },
50429/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50430 {
50431 { 0, 0, 0, 0 },
50432 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50433 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00a0000 }
50434 },
50435/* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
50436 {
50437 { 0, 0, 0, 0 },
50438 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50439 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02a0000 }
50440 },
50441/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
50442 {
50443 { 0, 0, 0, 0 },
50444 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50445 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20a0000 }
50446 },
50447/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
50448 {
50449 { 0, 0, 0, 0 },
50450 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50451 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22a0000 }
50452 },
50453/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
50454 {
50455 { 0, 0, 0, 0 },
50456 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50457 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40a0000 }
50458 },
50459/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
50460 {
50461 { 0, 0, 0, 0 },
50462 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50463 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42a0000 }
50464 },
50465/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
50466 {
50467 { 0, 0, 0, 0 },
50468 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50469 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60a0000 }
50470 },
50471/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
50472 {
50473 { 0, 0, 0, 0 },
50474 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50475 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62a0000 }
50476 },
50477/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
50478 {
50479 { 0, 0, 0, 0 },
50480 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
50481 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28a0000 }
50482 },
50483/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
50484 {
50485 { 0, 0, 0, 0 },
50486 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
50487 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2aa0000 }
50488 },
50489/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
50490 {
50491 { 0, 0, 0, 0 },
50492 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
50493 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48a0000 }
50494 },
50495/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
50496 {
50497 { 0, 0, 0, 0 },
50498 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
50499 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4aa0000 }
50500 },
50501/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
50502 {
50503 { 0, 0, 0, 0 },
50504 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
50505 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ca0000 }
50506 },
50507/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
50508 {
50509 { 0, 0, 0, 0 },
50510 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
50511 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ea0000 }
50512 },
50513/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
50514 {
50515 { 0, 0, 0, 0 },
50516 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
50517 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ca0000 }
50518 },
50519/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
50520 {
50521 { 0, 0, 0, 0 },
50522 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
50523 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ea0000 }
50524 },
50525/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
50526 {
50527 { 0, 0, 0, 0 },
50528 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
50529 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ca0000 }
50530 },
50531/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
50532 {
50533 { 0, 0, 0, 0 },
50534 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
50535 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ea0000 }
50536 },
50537/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
50538 {
50539 { 0, 0, 0, 0 },
50540 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
50541 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68a0000 }
50542 },
50543/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
50544 {
50545 { 0, 0, 0, 0 },
50546 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
50547 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6aa0000 }
50548 },
50549/* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
50550 {
50551 { 0, 0, 0, 0 },
50552 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50553 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80a }
50554 },
50555/* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
50556 {
50557 { 0, 0, 0, 0 },
50558 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50559 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882a }
50560 },
50561/* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50562 {
50563 { 0, 0, 0, 0 },
50564 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50565 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880a }
50566 },
50567/* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
50568 {
50569 { 0, 0, 0, 0 },
50570 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50571 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08a }
50572 },
50573/* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
50574 {
50575 { 0, 0, 0, 0 },
50576 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50577 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80aa }
50578 },
50579/* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50580 {
50581 { 0, 0, 0, 0 },
50582 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50583 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808a }
50584 },
50585/* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
50586 {
50587 { 0, 0, 0, 0 },
50588 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50589 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00a }
50590 },
50591/* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
50592 {
50593 { 0, 0, 0, 0 },
50594 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50595 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802a }
50596 },
50597/* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50598 {
50599 { 0, 0, 0, 0 },
50600 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50601 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800a }
50602 },
50603/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50604 {
50605 { 0, 0, 0, 0 },
50606 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50607 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20a00 }
50608 },
50609/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50610 {
50611 { 0, 0, 0, 0 },
50612 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50613 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822a00 }
50614 },
50615/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
50616 {
50617 { 0, 0, 0, 0 },
50618 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50619 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820a00 }
50620 },
50621/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50622 {
50623 { 0, 0, 0, 0 },
50624 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50625 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40a0000 }
50626 },
50627/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50628 {
50629 { 0, 0, 0, 0 },
50630 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50631 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842a0000 }
50632 },
50633/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
50634 {
50635 { 0, 0, 0, 0 },
50636 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50637 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840a0000 }
50638 },
50639/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50640 {
50641 { 0, 0, 0, 0 },
50642 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50643 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60a0000 }
50644 },
50645/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50646 {
50647 { 0, 0, 0, 0 },
50648 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50649 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862a0000 }
50650 },
50651/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
50652 {
50653 { 0, 0, 0, 0 },
50654 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50655 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860a0000 }
50656 },
50657/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
50658 {
50659 { 0, 0, 0, 0 },
50660 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50661 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28a00 }
50662 },
50663/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
50664 {
50665 { 0, 0, 0, 0 },
50666 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50667 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82aa00 }
50668 },
50669/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
50670 {
50671 { 0, 0, 0, 0 },
50672 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50673 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828a00 }
50674 },
50675/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
50676 {
50677 { 0, 0, 0, 0 },
50678 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50679 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48a0000 }
50680 },
50681/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
50682 {
50683 { 0, 0, 0, 0 },
50684 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50685 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84aa0000 }
50686 },
50687/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
50688 {
50689 { 0, 0, 0, 0 },
50690 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50691 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848a0000 }
50692 },
50693/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
50694 {
50695 { 0, 0, 0, 0 },
50696 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50697 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ca00 }
50698 },
50699/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
50700 {
50701 { 0, 0, 0, 0 },
50702 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50703 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ea00 }
50704 },
50705/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
50706 {
50707 { 0, 0, 0, 0 },
50708 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50709 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ca00 }
50710 },
50711/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
50712 {
50713 { 0, 0, 0, 0 },
50714 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50715 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ca0000 }
50716 },
50717/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
50718 {
50719 { 0, 0, 0, 0 },
50720 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50721 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ea0000 }
50722 },
50723/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
50724 {
50725 { 0, 0, 0, 0 },
50726 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50727 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ca0000 }
50728 },
50729/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
50730 {
50731 { 0, 0, 0, 0 },
50732 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
50733 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ca0000 }
50734 },
50735/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
50736 {
50737 { 0, 0, 0, 0 },
50738 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
50739 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ea0000 }
50740 },
50741/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
50742 {
50743 { 0, 0, 0, 0 },
50744 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
50745 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ca0000 }
50746 },
50747/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
50748 {
50749 { 0, 0, 0, 0 },
50750 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
50751 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68a0000 }
50752 },
50753/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
50754 {
50755 { 0, 0, 0, 0 },
50756 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
50757 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86aa0000 }
50758 },
50759/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
50760 {
50761 { 0, 0, 0, 0 },
50762 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
50763 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868a0000 }
50764 },
50765/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
50766 {
50767 { 0, 0, 0, 0 },
50768 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
50769 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa98000 }
50770 },
50771/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
50772 {
50773 { 0, 0, 0, 0 },
50774 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
50775 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9a000 }
50776 },
50777/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
50778 {
50779 { 0, 0, 0, 0 },
50780 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
50781 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa9b000 }
50782 },
50783/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
50784 {
50785 { 0, 0, 0, 0 },
50786 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
50787 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa98400 }
50788 },
50789/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
50790 {
50791 { 0, 0, 0, 0 },
50792 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
50793 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa9a400 }
50794 },
50795/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
50796 {
50797 { 0, 0, 0, 0 },
50798 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
50799 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa9b400 }
50800 },
50801/* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50802 {
50803 { 0, 0, 0, 0 },
50804 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50805 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa98600 }
50806 },
50807/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50808 {
50809 { 0, 0, 0, 0 },
50810 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50811 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa9a600 }
50812 },
50813/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50814 {
50815 { 0, 0, 0, 0 },
50816 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50817 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa9b600 }
50818 },
50819/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50820 {
50821 { 0, 0, 0, 0 },
50822 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50823 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa9880000 }
50824 },
50825/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50826 {
50827 { 0, 0, 0, 0 },
50828 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50829 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9a80000 }
50830 },
50831/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50832 {
50833 { 0, 0, 0, 0 },
50834 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50835 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9b80000 }
50836 },
50837/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50838 {
50839 { 0, 0, 0, 0 },
50840 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50841 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa98c0000 }
50842 },
50843/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50844 {
50845 { 0, 0, 0, 0 },
50846 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50847 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9ac0000 }
50848 },
50849/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50850 {
50851 { 0, 0, 0, 0 },
50852 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50853 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9bc0000 }
50854 },
50855/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50856 {
50857 { 0, 0, 0, 0 },
50858 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50859 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa98a0000 }
50860 },
50861/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50862 {
50863 { 0, 0, 0, 0 },
50864 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50865 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9aa0000 }
50866 },
50867/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50868 {
50869 { 0, 0, 0, 0 },
50870 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50871 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9ba0000 }
50872 },
50873/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50874 {
50875 { 0, 0, 0, 0 },
50876 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50877 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa98e0000 }
50878 },
50879/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50880 {
50881 { 0, 0, 0, 0 },
50882 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50883 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9ae0000 }
50884 },
50885/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50886 {
50887 { 0, 0, 0, 0 },
50888 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50889 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9be0000 }
50890 },
50891/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50892 {
50893 { 0, 0, 0, 0 },
50894 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50895 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa98b0000 }
50896 },
50897/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50898 {
50899 { 0, 0, 0, 0 },
50900 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50901 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9ab0000 }
50902 },
50903/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50904 {
50905 { 0, 0, 0, 0 },
50906 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50907 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9bb0000 }
50908 },
50909/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50910 {
50911 { 0, 0, 0, 0 },
50912 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
50913 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa98f0000 }
50914 },
50915/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50916 {
50917 { 0, 0, 0, 0 },
50918 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50919 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa9af0000 }
50920 },
50921/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50922 {
50923 { 0, 0, 0, 0 },
50924 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50925 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa9bf0000 }
50926 },
50927/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
50928 {
50929 { 0, 0, 0, 0 },
50930 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
50931 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa9c00000 }
50932 },
50933/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
50934 {
50935 { 0, 0, 0, 0 },
50936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
50937 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9e00000 }
50938 },
50939/* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
50940 {
50941 { 0, 0, 0, 0 },
50942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
50943 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa9f00000 }
50944 },
50945/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
50946 {
50947 { 0, 0, 0, 0 },
50948 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
50949 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa9c40000 }
50950 },
50951/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
50952 {
50953 { 0, 0, 0, 0 },
50954 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
50955 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa9e40000 }
50956 },
50957/* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
50958 {
50959 { 0, 0, 0, 0 },
50960 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
50961 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa9f40000 }
50962 },
50963/* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50964 {
50965 { 0, 0, 0, 0 },
50966 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50967 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa9c60000 }
50968 },
50969/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50970 {
50971 { 0, 0, 0, 0 },
50972 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50973 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa9e60000 }
50974 },
50975/* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
50976 {
50977 { 0, 0, 0, 0 },
50978 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
50979 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa9f60000 }
50980 },
50981/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50982 {
50983 { 0, 0, 0, 0 },
50984 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50985 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa9c80000 }
50986 },
50987/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50988 {
50989 { 0, 0, 0, 0 },
50990 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50991 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa9e80000 }
50992 },
50993/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50994 {
50995 { 0, 0, 0, 0 },
50996 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50997 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa9f80000 }
50998 },
50999/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
51000 {
51001 { 0, 0, 0, 0 },
51002 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51003 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa9cc0000 }
51004 },
51005/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
51006 {
51007 { 0, 0, 0, 0 },
51008 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51009 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa9ec0000 }
51010 },
51011/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
51012 {
51013 { 0, 0, 0, 0 },
51014 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51015 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa9fc0000 }
51016 },
51017/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
51018 {
51019 { 0, 0, 0, 0 },
51020 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51021 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ca0000 }
51022 },
51023/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51024 {
51025 { 0, 0, 0, 0 },
51026 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51027 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ea0000 }
51028 },
51029/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51030 {
51031 { 0, 0, 0, 0 },
51032 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51033 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa9fa0000 }
51034 },
51035/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
51036 {
51037 { 0, 0, 0, 0 },
51038 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51039 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ce0000 }
51040 },
51041/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51042 {
51043 { 0, 0, 0, 0 },
51044 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51045 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ee0000 }
51046 },
51047/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51048 {
51049 { 0, 0, 0, 0 },
51050 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51051 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa9fe0000 }
51052 },
51053/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
51054 {
51055 { 0, 0, 0, 0 },
51056 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51057 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9cb0000 }
51058 },
51059/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51060 {
51061 { 0, 0, 0, 0 },
51062 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51063 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9eb0000 }
51064 },
51065/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51066 {
51067 { 0, 0, 0, 0 },
51068 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51069 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa9fb0000 }
51070 },
51071/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
51072 {
51073 { 0, 0, 0, 0 },
51074 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
51075 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa9cf0000 }
51076 },
51077/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51078 {
51079 { 0, 0, 0, 0 },
51080 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
51081 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa9ef0000 }
51082 },
51083/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
51084 {
51085 { 0, 0, 0, 0 },
51086 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
51087 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa9ff0000 }
51088 },
51089/* sub.w${G} $Src16RnHI,$Dst16RnHI */
51090 {
51091 { 0, 0, 0, 0 },
51092 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
51093 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa900 }
51094 },
51095/* sub.w${G} $Src16AnHI,$Dst16RnHI */
51096 {
51097 { 0, 0, 0, 0 },
51098 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
51099 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa940 }
51100 },
51101/* sub.w${G} [$Src16An],$Dst16RnHI */
51102 {
51103 { 0, 0, 0, 0 },
51104 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
51105 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa960 }
51106 },
51107/* sub.w${G} $Src16RnHI,$Dst16AnHI */
51108 {
51109 { 0, 0, 0, 0 },
51110 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
51111 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa904 }
51112 },
51113/* sub.w${G} $Src16AnHI,$Dst16AnHI */
51114 {
51115 { 0, 0, 0, 0 },
51116 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
51117 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa944 }
51118 },
51119/* sub.w${G} [$Src16An],$Dst16AnHI */
51120 {
51121 { 0, 0, 0, 0 },
51122 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
51123 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa964 }
51124 },
51125/* sub.w${G} $Src16RnHI,[$Dst16An] */
51126 {
51127 { 0, 0, 0, 0 },
51128 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
51129 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa906 }
51130 },
51131/* sub.w${G} $Src16AnHI,[$Dst16An] */
51132 {
51133 { 0, 0, 0, 0 },
51134 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
51135 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa946 }
51136 },
51137/* sub.w${G} [$Src16An],[$Dst16An] */
51138 {
51139 { 0, 0, 0, 0 },
51140 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51141 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa966 }
51142 },
51143/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
51144 {
51145 { 0, 0, 0, 0 },
51146 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51147 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa90800 }
51148 },
51149/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
51150 {
51151 { 0, 0, 0, 0 },
51152 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51153 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa94800 }
51154 },
51155/* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
51156 {
51157 { 0, 0, 0, 0 },
51158 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51159 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa96800 }
51160 },
51161/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
51162 {
51163 { 0, 0, 0, 0 },
51164 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51165 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa90c0000 }
51166 },
51167/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
51168 {
51169 { 0, 0, 0, 0 },
51170 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51171 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa94c0000 }
51172 },
51173/* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
51174 {
51175 { 0, 0, 0, 0 },
51176 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51177 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa96c0000 }
51178 },
51179/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
51180 {
51181 { 0, 0, 0, 0 },
51182 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51183 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa90a00 }
51184 },
51185/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
51186 {
51187 { 0, 0, 0, 0 },
51188 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51189 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa94a00 }
51190 },
51191/* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
51192 {
51193 { 0, 0, 0, 0 },
51194 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51195 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa96a00 }
51196 },
51197/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
51198 {
51199 { 0, 0, 0, 0 },
51200 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51201 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa90e0000 }
51202 },
51203/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
51204 {
51205 { 0, 0, 0, 0 },
51206 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51207 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa94e0000 }
51208 },
51209/* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
51210 {
51211 { 0, 0, 0, 0 },
51212 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51213 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa96e0000 }
51214 },
51215/* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
51216 {
51217 { 0, 0, 0, 0 },
51218 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51219 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa90b00 }
51220 },
51221/* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
51222 {
51223 { 0, 0, 0, 0 },
51224 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51225 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa94b00 }
51226 },
51227/* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
51228 {
51229 { 0, 0, 0, 0 },
51230 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51231 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa96b00 }
51232 },
51233/* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
51234 {
51235 { 0, 0, 0, 0 },
51236 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
51237 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa90f0000 }
51238 },
51239/* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
51240 {
51241 { 0, 0, 0, 0 },
51242 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
51243 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa94f0000 }
51244 },
51245/* sub.w${G} [$Src16An],${Dsp-16-u16} */
51246 {
51247 { 0, 0, 0, 0 },
51248 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
51249 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa96f0000 }
51250 },
51251/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
51252 {
51253 { 0, 0, 0, 0 },
51254 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51255 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa88000 }
51256 },
51257/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
51258 {
51259 { 0, 0, 0, 0 },
51260 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
51261 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8a000 }
51262 },
51263/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
51264 {
51265 { 0, 0, 0, 0 },
51266 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
51267 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa8b000 }
51268 },
51269/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
51270 {
51271 { 0, 0, 0, 0 },
51272 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51273 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa88400 }
51274 },
51275/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
51276 {
51277 { 0, 0, 0, 0 },
51278 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
51279 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa8a400 }
51280 },
51281/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
51282 {
51283 { 0, 0, 0, 0 },
51284 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
51285 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa8b400 }
51286 },
51287/* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
51288 {
51289 { 0, 0, 0, 0 },
51290 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51291 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa88600 }
51292 },
51293/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
51294 {
51295 { 0, 0, 0, 0 },
51296 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
51297 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa8a600 }
51298 },
51299/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
51300 {
51301 { 0, 0, 0, 0 },
51302 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
51303 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa8b600 }
51304 },
51305/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
51306 {
51307 { 0, 0, 0, 0 },
51308 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
51309 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa8880000 }
51310 },
51311/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
51312 {
51313 { 0, 0, 0, 0 },
51314 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
51315 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8a80000 }
51316 },
51317/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
51318 {
51319 { 0, 0, 0, 0 },
51320 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
51321 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8b80000 }
51322 },
51323/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
51324 {
51325 { 0, 0, 0, 0 },
51326 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
51327 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa88c0000 }
51328 },
51329/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
51330 {
51331 { 0, 0, 0, 0 },
51332 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
51333 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8ac0000 }
51334 },
51335/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
51336 {
51337 { 0, 0, 0, 0 },
51338 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
51339 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8bc0000 }
51340 },
51341/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
51342 {
51343 { 0, 0, 0, 0 },
51344 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
51345 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa88a0000 }
51346 },
51347/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
51348 {
51349 { 0, 0, 0, 0 },
51350 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
51351 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8aa0000 }
51352 },
51353/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
51354 {
51355 { 0, 0, 0, 0 },
51356 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
51357 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8ba0000 }
51358 },
51359/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
51360 {
51361 { 0, 0, 0, 0 },
51362 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
51363 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa88e0000 }
51364 },
51365/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
51366 {
51367 { 0, 0, 0, 0 },
51368 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
51369 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8ae0000 }
51370 },
51371/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
51372 {
51373 { 0, 0, 0, 0 },
51374 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
51375 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8be0000 }
51376 },
51377/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
51378 {
51379 { 0, 0, 0, 0 },
51380 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51381 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa88b0000 }
51382 },
51383/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
51384 {
51385 { 0, 0, 0, 0 },
51386 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51387 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8ab0000 }
51388 },
51389/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51390 {
51391 { 0, 0, 0, 0 },
51392 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51393 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8bb0000 }
51394 },
51395/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
51396 {
51397 { 0, 0, 0, 0 },
51398 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
51399 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa88f0000 }
51400 },
51401/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51402 {
51403 { 0, 0, 0, 0 },
51404 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
51405 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa8af0000 }
51406 },
51407/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51408 {
51409 { 0, 0, 0, 0 },
51410 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
51411 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa8bf0000 }
51412 },
51413/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
51414 {
51415 { 0, 0, 0, 0 },
51416 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51417 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa8c00000 }
51418 },
51419/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
51420 {
51421 { 0, 0, 0, 0 },
51422 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
51423 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8e00000 }
51424 },
51425/* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
51426 {
51427 { 0, 0, 0, 0 },
51428 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
51429 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa8f00000 }
51430 },
51431/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
51432 {
51433 { 0, 0, 0, 0 },
51434 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51435 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa8c40000 }
51436 },
51437/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
51438 {
51439 { 0, 0, 0, 0 },
51440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
51441 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa8e40000 }
51442 },
51443/* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
51444 {
51445 { 0, 0, 0, 0 },
51446 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
51447 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa8f40000 }
51448 },
51449/* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
51450 {
51451 { 0, 0, 0, 0 },
51452 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51453 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa8c60000 }
51454 },
51455/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
51456 {
51457 { 0, 0, 0, 0 },
51458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
51459 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa8e60000 }
51460 },
51461/* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
51462 {
51463 { 0, 0, 0, 0 },
51464 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
51465 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa8f60000 }
51466 },
51467/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
51468 {
51469 { 0, 0, 0, 0 },
51470 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51471 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa8c80000 }
51472 },
51473/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
51474 {
51475 { 0, 0, 0, 0 },
51476 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51477 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa8e80000 }
51478 },
51479/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
51480 {
51481 { 0, 0, 0, 0 },
51482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51483 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa8f80000 }
51484 },
51485/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
51486 {
51487 { 0, 0, 0, 0 },
51488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51489 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa8cc0000 }
51490 },
51491/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
51492 {
51493 { 0, 0, 0, 0 },
51494 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51495 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa8ec0000 }
51496 },
51497/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
51498 {
51499 { 0, 0, 0, 0 },
51500 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51501 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa8fc0000 }
51502 },
51503/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
51504 {
51505 { 0, 0, 0, 0 },
51506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51507 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ca0000 }
51508 },
51509/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51510 {
51511 { 0, 0, 0, 0 },
51512 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51513 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ea0000 }
51514 },
51515/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51516 {
51517 { 0, 0, 0, 0 },
51518 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51519 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa8fa0000 }
51520 },
51521/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
51522 {
51523 { 0, 0, 0, 0 },
51524 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51525 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ce0000 }
51526 },
51527/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51528 {
51529 { 0, 0, 0, 0 },
51530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51531 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ee0000 }
51532 },
51533/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51534 {
51535 { 0, 0, 0, 0 },
51536 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51537 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa8fe0000 }
51538 },
51539/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
51540 {
51541 { 0, 0, 0, 0 },
51542 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51543 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8cb0000 }
51544 },
51545/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51546 {
51547 { 0, 0, 0, 0 },
51548 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51549 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8eb0000 }
51550 },
51551/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51552 {
51553 { 0, 0, 0, 0 },
51554 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51555 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa8fb0000 }
51556 },
51557/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
51558 {
51559 { 0, 0, 0, 0 },
51560 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
51561 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa8cf0000 }
51562 },
51563/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51564 {
51565 { 0, 0, 0, 0 },
51566 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
51567 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa8ef0000 }
51568 },
51569/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
51570 {
51571 { 0, 0, 0, 0 },
51572 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
51573 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa8ff0000 }
51574 },
51575/* sub.b${G} $Src16RnQI,$Dst16RnQI */
51576 {
51577 { 0, 0, 0, 0 },
51578 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
51579 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa800 }
51580 },
51581/* sub.b${G} $Src16AnQI,$Dst16RnQI */
51582 {
51583 { 0, 0, 0, 0 },
51584 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
51585 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa840 }
51586 },
51587/* sub.b${G} [$Src16An],$Dst16RnQI */
51588 {
51589 { 0, 0, 0, 0 },
51590 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51591 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa860 }
51592 },
51593/* sub.b${G} $Src16RnQI,$Dst16AnQI */
51594 {
51595 { 0, 0, 0, 0 },
51596 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
51597 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa804 }
51598 },
51599/* sub.b${G} $Src16AnQI,$Dst16AnQI */
51600 {
51601 { 0, 0, 0, 0 },
51602 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
51603 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa844 }
51604 },
51605/* sub.b${G} [$Src16An],$Dst16AnQI */
51606 {
51607 { 0, 0, 0, 0 },
51608 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51609 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa864 }
51610 },
51611/* sub.b${G} $Src16RnQI,[$Dst16An] */
51612 {
51613 { 0, 0, 0, 0 },
51614 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
51615 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa806 }
51616 },
51617/* sub.b${G} $Src16AnQI,[$Dst16An] */
51618 {
51619 { 0, 0, 0, 0 },
51620 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
51621 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa846 }
51622 },
51623/* sub.b${G} [$Src16An],[$Dst16An] */
51624 {
51625 { 0, 0, 0, 0 },
51626 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51627 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa866 }
51628 },
51629/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
51630 {
51631 { 0, 0, 0, 0 },
51632 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51633 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa80800 }
51634 },
51635/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
51636 {
51637 { 0, 0, 0, 0 },
51638 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51639 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa84800 }
51640 },
51641/* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
51642 {
51643 { 0, 0, 0, 0 },
51644 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51645 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa86800 }
51646 },
51647/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
51648 {
51649 { 0, 0, 0, 0 },
51650 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51651 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa80c0000 }
51652 },
51653/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
51654 {
51655 { 0, 0, 0, 0 },
51656 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51657 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa84c0000 }
51658 },
51659/* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
51660 {
51661 { 0, 0, 0, 0 },
51662 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51663 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa86c0000 }
51664 },
51665/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
51666 {
51667 { 0, 0, 0, 0 },
51668 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51669 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa80a00 }
51670 },
51671/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
51672 {
51673 { 0, 0, 0, 0 },
51674 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51675 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa84a00 }
51676 },
51677/* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
51678 {
51679 { 0, 0, 0, 0 },
51680 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51681 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa86a00 }
51682 },
51683/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
51684 {
51685 { 0, 0, 0, 0 },
51686 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51687 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa80e0000 }
51688 },
51689/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
51690 {
51691 { 0, 0, 0, 0 },
51692 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51693 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa84e0000 }
51694 },
51695/* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
51696 {
51697 { 0, 0, 0, 0 },
51698 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51699 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa86e0000 }
51700 },
51701/* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
51702 {
51703 { 0, 0, 0, 0 },
51704 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51705 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa80b00 }
51706 },
51707/* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
51708 {
51709 { 0, 0, 0, 0 },
51710 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51711 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa84b00 }
51712 },
51713/* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
51714 {
51715 { 0, 0, 0, 0 },
51716 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51717 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa86b00 }
51718 },
51719/* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
51720 {
51721 { 0, 0, 0, 0 },
51722 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
51723 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa80f0000 }
51724 },
51725/* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
51726 {
51727 { 0, 0, 0, 0 },
51728 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
51729 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa84f0000 }
51730 },
51731/* sub.b${G} [$Src16An],${Dsp-16-u16} */
51732 {
51733 { 0, 0, 0, 0 },
51734 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
51735 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa86f0000 }
51736 },
51737/* sub.b${S} #${Imm-8-QI},r0l */
51738 {
51739 { 0, 0, 0, 0 },
51740 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
51741 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8c00 }
51742 },
51743/* sub.b${S} #${Imm-8-QI},r0h */
51744 {
51745 { 0, 0, 0, 0 },
51746 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
51747 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8b00 }
51748 },
51749/* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
51750 {
51751 { 0, 0, 0, 0 },
51752 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51753 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x8d0000 }
51754 },
51755/* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
51756 {
51757 { 0, 0, 0, 0 },
51758 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51759 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x8e0000 }
51760 },
51761/* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
51762 {
51763 { 0, 0, 0, 0 },
51764 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
51765 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x8f000000 }
51766 },
51767/* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
51768 {
51769 { 0, 0, 0, 0 },
51770 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
51771 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893e0000 }
51772 },
51773/* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
51774 {
51775 { 0, 0, 0, 0 },
51776 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
51777 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81be0000 }
51778 },
51779/* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
51780 {
51781 { 0, 0, 0, 0 },
51782 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51783 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813e0000 }
51784 },
51785/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51786 {
51787 { 0, 0, 0, 0 },
51788 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51789 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833e0000 }
51790 },
51791/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51792 {
51793 { 0, 0, 0, 0 },
51794 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51795 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83be0000 }
51796 },
51797/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51798 {
51799 { 0, 0, 0, 0 },
51800 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51801 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83fe0000 }
51802 },
51803/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51804 {
51805 { 0, 0, 0, 0 },
51806 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51807 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853e0000 }
51808 },
51809/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51810 {
51811 { 0, 0, 0, 0 },
51812 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51813 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85be0000 }
51814 },
51815/* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
51816 {
51817 { 0, 0, 0, 0 },
51818 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
51819 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85fe0000 }
51820 },
51821/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51822 {
51823 { 0, 0, 0, 0 },
51824 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
51825 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87fe0000 }
51826 },
51827/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51828 {
51829 { 0, 0, 0, 0 },
51830 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51831 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873e0000 }
51832 },
51833/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
51834 {
51835 { 0, 0, 0, 0 },
51836 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
51837 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87be0000 }
51838 },
51839/* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
51840 {
51841 { 0, 0, 0, 0 },
51842 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
51843 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883e00 }
51844 },
51845/* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
51846 {
51847 { 0, 0, 0, 0 },
51848 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
51849 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80be00 }
51850 },
51851/* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51852 {
51853 { 0, 0, 0, 0 },
51854 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51855 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803e00 }
51856 },
51857/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51858 {
51859 { 0, 0, 0, 0 },
51860 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51861 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823e0000 }
51862 },
51863/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51864 {
51865 { 0, 0, 0, 0 },
51866 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51867 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82be0000 }
51868 },
51869/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51870 {
51871 { 0, 0, 0, 0 },
51872 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51873 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82fe0000 }
51874 },
51875/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51876 {
51877 { 0, 0, 0, 0 },
51878 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51879 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843e0000 }
51880 },
51881/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51882 {
51883 { 0, 0, 0, 0 },
51884 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51885 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84be0000 }
51886 },
51887/* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51888 {
51889 { 0, 0, 0, 0 },
51890 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
51891 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84fe0000 }
51892 },
51893/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51894 {
51895 { 0, 0, 0, 0 },
51896 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
51897 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86fe0000 }
51898 },
51899/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51900 {
51901 { 0, 0, 0, 0 },
51902 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51903 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863e0000 }
51904 },
51905/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
51906 {
51907 { 0, 0, 0, 0 },
51908 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
51909 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86be0000 }
51910 },
51911/* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
51912 {
51913 { 0, 0, 0, 0 },
51914 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
51915 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77500000 }
51916 },
51917/* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
51918 {
51919 { 0, 0, 0, 0 },
51920 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
51921 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77540000 }
51922 },
51923/* sub.w${G} #${Imm-16-HI},[$Dst16An] */
51924 {
51925 { 0, 0, 0, 0 },
51926 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
51927 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77560000 }
51928 },
51929/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
51930 {
51931 { 0, 0, 0, 0 },
51932 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51933 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77580000 }
51934 },
51935/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51936 {
51937 { 0, 0, 0, 0 },
51938 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51939 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x775a0000 }
51940 },
51941/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51942 {
51943 { 0, 0, 0, 0 },
51944 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51945 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x775b0000 }
51946 },
51947/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
51948 {
51949 { 0, 0, 0, 0 },
51950 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51951 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x775c0000 }
51952 },
51953/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51954 {
51955 { 0, 0, 0, 0 },
51956 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51957 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x775e0000 }
51958 },
51959/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51960 {
51961 { 0, 0, 0, 0 },
51962 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
51963 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x775f0000 }
51964 },
51965/* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
51966 {
51967 { 0, 0, 0, 0 },
51968 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
51969 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x765000 }
51970 },
51971/* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
51972 {
51973 { 0, 0, 0, 0 },
51974 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
51975 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x765400 }
51976 },
51977/* sub.b${G} #${Imm-16-QI},[$Dst16An] */
51978 {
51979 { 0, 0, 0, 0 },
51980 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
51981 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x765600 }
51982 },
51983/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
51984 {
51985 { 0, 0, 0, 0 },
51986 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51987 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76580000 }
51988 },
51989/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51990 {
51991 { 0, 0, 0, 0 },
51992 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51993 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x765a0000 }
51994 },
51995/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51996 {
51997 { 0, 0, 0, 0 },
51998 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51999 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x765b0000 }
52000 },
52001/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
52002 {
52003 { 0, 0, 0, 0 },
52004 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
52005 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x765c0000 }
52006 },
52007/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
52008 {
52009 { 0, 0, 0, 0 },
52010 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
52011 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x765e0000 }
52012 },
52013/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
52014 {
52015 { 0, 0, 0, 0 },
52016 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
52017 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x765f0000 }
52018 },
52019/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52020 {
52021 { 0, 0, 0, 0 },
52022 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52023 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990200 }
52024 },
52025/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
52026 {
52027 { 0, 0, 0, 0 },
52028 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52029 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992200 }
52030 },
52031/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
52032 {
52033 { 0, 0, 0, 0 },
52034 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52035 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993200 }
52036 },
52037/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52038 {
52039 { 0, 0, 0, 0 },
52040 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52041 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918200 }
52042 },
52043/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
52044 {
52045 { 0, 0, 0, 0 },
52046 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52047 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a200 }
52048 },
52049/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
52050 {
52051 { 0, 0, 0, 0 },
52052 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52053 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b200 }
52054 },
52055/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52056 {
52057 { 0, 0, 0, 0 },
52058 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52059 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910200 }
52060 },
52061/* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52062 {
52063 { 0, 0, 0, 0 },
52064 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52065 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912200 }
52066 },
52067/* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52068 {
52069 { 0, 0, 0, 0 },
52070 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52071 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913200 }
52072 },
52073/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52074 {
52075 { 0, 0, 0, 0 },
52076 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52077 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930200 }
52078 },
52079/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52080 {
52081 { 0, 0, 0, 0 },
52082 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52083 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932200 }
52084 },
52085/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52086 {
52087 { 0, 0, 0, 0 },
52088 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52089 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933200 }
52090 },
52091/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52092 {
52093 { 0, 0, 0, 0 },
52094 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52095 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950200 }
52096 },
52097/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52098 {
52099 { 0, 0, 0, 0 },
52100 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52101 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952200 }
52102 },
52103/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52104 {
52105 { 0, 0, 0, 0 },
52106 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52107 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953200 }
52108 },
52109/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52110 {
52111 { 0, 0, 0, 0 },
52112 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52113 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970200 }
52114 },
52115/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52116 {
52117 { 0, 0, 0, 0 },
52118 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52119 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972200 }
52120 },
52121/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52122 {
52123 { 0, 0, 0, 0 },
52124 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52125 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973200 }
52126 },
52127/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52128 {
52129 { 0, 0, 0, 0 },
52130 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52131 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938200 }
52132 },
52133/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52134 {
52135 { 0, 0, 0, 0 },
52136 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52137 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a200 }
52138 },
52139/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52140 {
52141 { 0, 0, 0, 0 },
52142 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52143 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b200 }
52144 },
52145/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52146 {
52147 { 0, 0, 0, 0 },
52148 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52149 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958200 }
52150 },
52151/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52152 {
52153 { 0, 0, 0, 0 },
52154 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52155 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a200 }
52156 },
52157/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52158 {
52159 { 0, 0, 0, 0 },
52160 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52161 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b200 }
52162 },
52163/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52164 {
52165 { 0, 0, 0, 0 },
52166 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52167 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c200 }
52168 },
52169/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52170 {
52171 { 0, 0, 0, 0 },
52172 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52173 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e200 }
52174 },
52175/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52176 {
52177 { 0, 0, 0, 0 },
52178 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52179 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f200 }
52180 },
52181/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52182 {
52183 { 0, 0, 0, 0 },
52184 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52185 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c200 }
52186 },
52187/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52188 {
52189 { 0, 0, 0, 0 },
52190 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52191 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e200 }
52192 },
52193/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52194 {
52195 { 0, 0, 0, 0 },
52196 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52197 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f200 }
52198 },
52199/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52200 {
52201 { 0, 0, 0, 0 },
52202 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
52203 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c200 }
52204 },
52205/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52206 {
52207 { 0, 0, 0, 0 },
52208 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
52209 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e200 }
52210 },
52211/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52212 {
52213 { 0, 0, 0, 0 },
52214 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
52215 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f200 }
52216 },
52217/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52218 {
52219 { 0, 0, 0, 0 },
52220 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
52221 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978200 }
52222 },
52223/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52224 {
52225 { 0, 0, 0, 0 },
52226 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
52227 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a200 }
52228 },
52229/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52230 {
52231 { 0, 0, 0, 0 },
52232 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
52233 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b200 }
52234 },
52235/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52236 {
52237 { 0, 0, 0, 0 },
52238 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52239 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90200 }
52240 },
52241/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
52242 {
52243 { 0, 0, 0, 0 },
52244 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52245 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92200 }
52246 },
52247/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
52248 {
52249 { 0, 0, 0, 0 },
52250 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52251 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93200 }
52252 },
52253/* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
52254 {
52255 { 0, 0, 0, 0 },
52256 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
52257 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93200 }
52258 },
52259/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52260 {
52261 { 0, 0, 0, 0 },
52262 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52263 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18200 }
52264 },
52265/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
52266 {
52267 { 0, 0, 0, 0 },
52268 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52269 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a200 }
52270 },
52271/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
52272 {
52273 { 0, 0, 0, 0 },
52274 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52275 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b200 }
52276 },
52277/* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
52278 {
52279 { 0, 0, 0, 0 },
52280 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
52281 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b200 }
52282 },
52283/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52284 {
52285 { 0, 0, 0, 0 },
52286 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52287 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10200 }
52288 },
52289/* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52290 {
52291 { 0, 0, 0, 0 },
52292 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52293 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12200 }
52294 },
52295/* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52296 {
52297 { 0, 0, 0, 0 },
52298 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52299 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13200 }
52300 },
52301/* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52302 {
52303 { 0, 0, 0, 0 },
52304 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52305 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13200 }
52306 },
52307/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52308 {
52309 { 0, 0, 0, 0 },
52310 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52311 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30200 }
52312 },
52313/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52314 {
52315 { 0, 0, 0, 0 },
52316 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52317 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32200 }
52318 },
52319/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52320 {
52321 { 0, 0, 0, 0 },
52322 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52323 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33200 }
52324 },
52325/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52326 {
52327 { 0, 0, 0, 0 },
52328 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52329 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33200 }
52330 },
52331/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52332 {
52333 { 0, 0, 0, 0 },
52334 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52335 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50200 }
52336 },
52337/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52338 {
52339 { 0, 0, 0, 0 },
52340 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52341 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52200 }
52342 },
52343/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52344 {
52345 { 0, 0, 0, 0 },
52346 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52347 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53200 }
52348 },
52349/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52350 {
52351 { 0, 0, 0, 0 },
52352 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52353 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53200 }
52354 },
52355/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52356 {
52357 { 0, 0, 0, 0 },
52358 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52359 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70200 }
52360 },
52361/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52362 {
52363 { 0, 0, 0, 0 },
52364 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52365 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72200 }
52366 },
52367/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52368 {
52369 { 0, 0, 0, 0 },
52370 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52371 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73200 }
52372 },
52373/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52374 {
52375 { 0, 0, 0, 0 },
52376 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52377 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73200 }
52378 },
52379/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52380 {
52381 { 0, 0, 0, 0 },
52382 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52383 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38200 }
52384 },
52385/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52386 {
52387 { 0, 0, 0, 0 },
52388 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52389 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a200 }
52390 },
52391/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52392 {
52393 { 0, 0, 0, 0 },
52394 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52395 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b200 }
52396 },
52397/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52398 {
52399 { 0, 0, 0, 0 },
52400 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52401 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b200 }
52402 },
52403/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52404 {
52405 { 0, 0, 0, 0 },
52406 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52407 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58200 }
52408 },
52409/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52410 {
52411 { 0, 0, 0, 0 },
52412 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52413 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a200 }
52414 },
52415/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52416 {
52417 { 0, 0, 0, 0 },
52418 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52419 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b200 }
52420 },
52421/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52422 {
52423 { 0, 0, 0, 0 },
52424 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52425 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b200 }
52426 },
52427/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52428 {
52429 { 0, 0, 0, 0 },
52430 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52431 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c200 }
52432 },
52433/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52434 {
52435 { 0, 0, 0, 0 },
52436 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52437 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e200 }
52438 },
52439/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52440 {
52441 { 0, 0, 0, 0 },
52442 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52443 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f200 }
52444 },
52445/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52446 {
52447 { 0, 0, 0, 0 },
52448 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52449 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f200 }
52450 },
52451/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52452 {
52453 { 0, 0, 0, 0 },
52454 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52455 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c200 }
52456 },
52457/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52458 {
52459 { 0, 0, 0, 0 },
52460 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52461 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e200 }
52462 },
52463/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52464 {
52465 { 0, 0, 0, 0 },
52466 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52467 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f200 }
52468 },
52469/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52470 {
52471 { 0, 0, 0, 0 },
52472 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52473 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f200 }
52474 },
52475/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52476 {
52477 { 0, 0, 0, 0 },
52478 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
52479 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c200 }
52480 },
52481/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52482 {
52483 { 0, 0, 0, 0 },
52484 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52485 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e200 }
52486 },
52487/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52488 {
52489 { 0, 0, 0, 0 },
52490 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52491 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f200 }
52492 },
52493/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52494 {
52495 { 0, 0, 0, 0 },
52496 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
52497 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f200 }
52498 },
52499/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52500 {
52501 { 0, 0, 0, 0 },
52502 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
52503 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78200 }
52504 },
52505/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52506 {
52507 { 0, 0, 0, 0 },
52508 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52509 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a200 }
52510 },
52511/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52512 {
52513 { 0, 0, 0, 0 },
52514 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52515 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b200 }
52516 },
52517/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52518 {
52519 { 0, 0, 0, 0 },
52520 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
52521 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b200 }
52522 },
52523/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52524 {
52525 { 0, 0, 0, 0 },
52526 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52527 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90200 }
52528 },
52529/* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52530 {
52531 { 0, 0, 0, 0 },
52532 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
52533 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92200 }
52534 },
52535/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52536 {
52537 { 0, 0, 0, 0 },
52538 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52539 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18200 }
52540 },
52541/* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52542 {
52543 { 0, 0, 0, 0 },
52544 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
52545 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a200 }
52546 },
52547/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52548 {
52549 { 0, 0, 0, 0 },
52550 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52551 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10200 }
52552 },
52553/* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52554 {
52555 { 0, 0, 0, 0 },
52556 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52557 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12200 }
52558 },
52559/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52560 {
52561 { 0, 0, 0, 0 },
52562 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52563 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30200 }
52564 },
52565/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52566 {
52567 { 0, 0, 0, 0 },
52568 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52569 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32200 }
52570 },
52571/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52572 {
52573 { 0, 0, 0, 0 },
52574 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52575 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50200 }
52576 },
52577/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52578 {
52579 { 0, 0, 0, 0 },
52580 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52581 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52200 }
52582 },
52583/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52584 {
52585 { 0, 0, 0, 0 },
52586 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52587 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70200 }
52588 },
52589/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52590 {
52591 { 0, 0, 0, 0 },
52592 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52593 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72200 }
52594 },
52595/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52596 {
52597 { 0, 0, 0, 0 },
52598 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
52599 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38200 }
52600 },
52601/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52602 {
52603 { 0, 0, 0, 0 },
52604 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
52605 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a200 }
52606 },
52607/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52608 {
52609 { 0, 0, 0, 0 },
52610 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
52611 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58200 }
52612 },
52613/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52614 {
52615 { 0, 0, 0, 0 },
52616 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
52617 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a200 }
52618 },
52619/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52620 {
52621 { 0, 0, 0, 0 },
52622 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
52623 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c200 }
52624 },
52625/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52626 {
52627 { 0, 0, 0, 0 },
52628 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
52629 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e200 }
52630 },
52631/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52632 {
52633 { 0, 0, 0, 0 },
52634 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
52635 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c200 }
52636 },
52637/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52638 {
52639 { 0, 0, 0, 0 },
52640 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
52641 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e200 }
52642 },
52643/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52644 {
52645 { 0, 0, 0, 0 },
52646 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
52647 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c200 }
52648 },
52649/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52650 {
52651 { 0, 0, 0, 0 },
52652 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
52653 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e200 }
52654 },
52655/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52656 {
52657 { 0, 0, 0, 0 },
52658 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
52659 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78200 }
52660 },
52661/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52662 {
52663 { 0, 0, 0, 0 },
52664 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
52665 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a200 }
52666 },
52667/* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52668 {
52669 { 0, 0, 0, 0 },
52670 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
52671 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c902 }
52672 },
52673/* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52674 {
52675 { 0, 0, 0, 0 },
52676 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
52677 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18922 }
52678 },
52679/* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52680 {
52681 { 0, 0, 0, 0 },
52682 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52683 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18902 }
52684 },
52685/* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52686 {
52687 { 0, 0, 0, 0 },
52688 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
52689 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c182 }
52690 },
52691/* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52692 {
52693 { 0, 0, 0, 0 },
52694 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
52695 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a2 }
52696 },
52697/* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52698 {
52699 { 0, 0, 0, 0 },
52700 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52701 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18182 }
52702 },
52703/* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52704 {
52705 { 0, 0, 0, 0 },
52706 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52707 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c102 }
52708 },
52709/* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52710 {
52711 { 0, 0, 0, 0 },
52712 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52713 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18122 }
52714 },
52715/* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52716 {
52717 { 0, 0, 0, 0 },
52718 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52719 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18102 }
52720 },
52721/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52722 {
52723 { 0, 0, 0, 0 },
52724 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52725 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30200 }
52726 },
52727/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52728 {
52729 { 0, 0, 0, 0 },
52730 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52731 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832200 }
52732 },
52733/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52734 {
52735 { 0, 0, 0, 0 },
52736 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52737 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830200 }
52738 },
52739/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52740 {
52741 { 0, 0, 0, 0 },
52742 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52743 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50200 }
52744 },
52745/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52746 {
52747 { 0, 0, 0, 0 },
52748 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52749 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852200 }
52750 },
52751/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52752 {
52753 { 0, 0, 0, 0 },
52754 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52755 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850200 }
52756 },
52757/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52758 {
52759 { 0, 0, 0, 0 },
52760 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52761 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70200 }
52762 },
52763/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52764 {
52765 { 0, 0, 0, 0 },
52766 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52767 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872200 }
52768 },
52769/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52770 {
52771 { 0, 0, 0, 0 },
52772 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52773 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870200 }
52774 },
52775/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52776 {
52777 { 0, 0, 0, 0 },
52778 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52779 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38200 }
52780 },
52781/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52782 {
52783 { 0, 0, 0, 0 },
52784 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52785 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a200 }
52786 },
52787/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52788 {
52789 { 0, 0, 0, 0 },
52790 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52791 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838200 }
52792 },
52793/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52794 {
52795 { 0, 0, 0, 0 },
52796 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52797 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58200 }
52798 },
52799/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52800 {
52801 { 0, 0, 0, 0 },
52802 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52803 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a200 }
52804 },
52805/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52806 {
52807 { 0, 0, 0, 0 },
52808 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52809 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858200 }
52810 },
52811/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52812 {
52813 { 0, 0, 0, 0 },
52814 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52815 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c200 }
52816 },
52817/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52818 {
52819 { 0, 0, 0, 0 },
52820 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52821 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e200 }
52822 },
52823/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52824 {
52825 { 0, 0, 0, 0 },
52826 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52827 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c200 }
52828 },
52829/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52830 {
52831 { 0, 0, 0, 0 },
52832 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52833 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c200 }
52834 },
52835/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52836 {
52837 { 0, 0, 0, 0 },
52838 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52839 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e200 }
52840 },
52841/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52842 {
52843 { 0, 0, 0, 0 },
52844 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52845 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c200 }
52846 },
52847/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52848 {
52849 { 0, 0, 0, 0 },
52850 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
52851 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c200 }
52852 },
52853/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52854 {
52855 { 0, 0, 0, 0 },
52856 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
52857 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e200 }
52858 },
52859/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52860 {
52861 { 0, 0, 0, 0 },
52862 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
52863 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c200 }
52864 },
52865/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52866 {
52867 { 0, 0, 0, 0 },
52868 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
52869 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78200 }
52870 },
52871/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52872 {
52873 { 0, 0, 0, 0 },
52874 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
52875 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a200 }
52876 },
52877/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52878 {
52879 { 0, 0, 0, 0 },
52880 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
52881 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878200 }
52882 },
52883/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52884 {
52885 { 0, 0, 0, 0 },
52886 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52887 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980200 }
52888 },
52889/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
52890 {
52891 { 0, 0, 0, 0 },
52892 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52893 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982200 }
52894 },
52895/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
52896 {
52897 { 0, 0, 0, 0 },
52898 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52899 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983200 }
52900 },
52901/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52902 {
52903 { 0, 0, 0, 0 },
52904 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52905 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908200 }
52906 },
52907/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
52908 {
52909 { 0, 0, 0, 0 },
52910 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52911 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a200 }
52912 },
52913/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
52914 {
52915 { 0, 0, 0, 0 },
52916 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52917 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b200 }
52918 },
52919/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52920 {
52921 { 0, 0, 0, 0 },
52922 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52923 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900200 }
52924 },
52925/* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52926 {
52927 { 0, 0, 0, 0 },
52928 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52929 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902200 }
52930 },
52931/* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52932 {
52933 { 0, 0, 0, 0 },
52934 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52935 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903200 }
52936 },
52937/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52938 {
52939 { 0, 0, 0, 0 },
52940 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52941 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920200 }
52942 },
52943/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52944 {
52945 { 0, 0, 0, 0 },
52946 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52947 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922200 }
52948 },
52949/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52950 {
52951 { 0, 0, 0, 0 },
52952 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52953 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923200 }
52954 },
52955/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52956 {
52957 { 0, 0, 0, 0 },
52958 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52959 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940200 }
52960 },
52961/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52962 {
52963 { 0, 0, 0, 0 },
52964 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52965 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942200 }
52966 },
52967/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52968 {
52969 { 0, 0, 0, 0 },
52970 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52971 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943200 }
52972 },
52973/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52974 {
52975 { 0, 0, 0, 0 },
52976 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52977 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960200 }
52978 },
52979/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52980 {
52981 { 0, 0, 0, 0 },
52982 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52983 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962200 }
52984 },
52985/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52986 {
52987 { 0, 0, 0, 0 },
52988 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52989 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963200 }
52990 },
52991/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52992 {
52993 { 0, 0, 0, 0 },
52994 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52995 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928200 }
52996 },
52997/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52998 {
52999 { 0, 0, 0, 0 },
53000 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
53001 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a200 }
53002 },
53003/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53004 {
53005 { 0, 0, 0, 0 },
53006 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
53007 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b200 }
53008 },
53009/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53010 {
53011 { 0, 0, 0, 0 },
53012 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53013 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948200 }
53014 },
53015/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53016 {
53017 { 0, 0, 0, 0 },
53018 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53019 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a200 }
53020 },
53021/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53022 {
53023 { 0, 0, 0, 0 },
53024 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53025 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b200 }
53026 },
53027/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53028 {
53029 { 0, 0, 0, 0 },
53030 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53031 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c200 }
53032 },
53033/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53034 {
53035 { 0, 0, 0, 0 },
53036 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53037 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e200 }
53038 },
53039/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53040 {
53041 { 0, 0, 0, 0 },
53042 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53043 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f200 }
53044 },
53045/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53046 {
53047 { 0, 0, 0, 0 },
53048 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53049 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c200 }
53050 },
53051/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53052 {
53053 { 0, 0, 0, 0 },
53054 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53055 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e200 }
53056 },
53057/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53058 {
53059 { 0, 0, 0, 0 },
53060 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53061 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f200 }
53062 },
53063/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53064 {
53065 { 0, 0, 0, 0 },
53066 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
53067 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c200 }
53068 },
53069/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53070 {
53071 { 0, 0, 0, 0 },
53072 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
53073 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e200 }
53074 },
53075/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53076 {
53077 { 0, 0, 0, 0 },
53078 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
53079 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f200 }
53080 },
53081/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53082 {
53083 { 0, 0, 0, 0 },
53084 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
53085 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968200 }
53086 },
53087/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53088 {
53089 { 0, 0, 0, 0 },
53090 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
53091 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a200 }
53092 },
53093/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53094 {
53095 { 0, 0, 0, 0 },
53096 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
53097 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b200 }
53098 },
53099/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53100 {
53101 { 0, 0, 0, 0 },
53102 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53103 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80200 }
53104 },
53105/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
53106 {
53107 { 0, 0, 0, 0 },
53108 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53109 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82200 }
53110 },
53111/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
53112 {
53113 { 0, 0, 0, 0 },
53114 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53115 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83200 }
53116 },
53117/* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
53118 {
53119 { 0, 0, 0, 0 },
53120 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
53121 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83200 }
53122 },
53123/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53124 {
53125 { 0, 0, 0, 0 },
53126 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53127 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08200 }
53128 },
53129/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
53130 {
53131 { 0, 0, 0, 0 },
53132 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53133 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a200 }
53134 },
53135/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
53136 {
53137 { 0, 0, 0, 0 },
53138 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53139 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b200 }
53140 },
53141/* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
53142 {
53143 { 0, 0, 0, 0 },
53144 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
53145 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b200 }
53146 },
53147/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53148 {
53149 { 0, 0, 0, 0 },
53150 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53151 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00200 }
53152 },
53153/* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53154 {
53155 { 0, 0, 0, 0 },
53156 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53157 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02200 }
53158 },
53159/* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53160 {
53161 { 0, 0, 0, 0 },
53162 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53163 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03200 }
53164 },
53165/* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53166 {
53167 { 0, 0, 0, 0 },
53168 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53169 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03200 }
53170 },
53171/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53172 {
53173 { 0, 0, 0, 0 },
53174 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53175 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20200 }
53176 },
53177/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53178 {
53179 { 0, 0, 0, 0 },
53180 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53181 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22200 }
53182 },
53183/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53184 {
53185 { 0, 0, 0, 0 },
53186 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53187 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23200 }
53188 },
53189/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53190 {
53191 { 0, 0, 0, 0 },
53192 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53193 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23200 }
53194 },
53195/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53196 {
53197 { 0, 0, 0, 0 },
53198 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53199 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40200 }
53200 },
53201/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53202 {
53203 { 0, 0, 0, 0 },
53204 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53205 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42200 }
53206 },
53207/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53208 {
53209 { 0, 0, 0, 0 },
53210 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53211 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43200 }
53212 },
53213/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53214 {
53215 { 0, 0, 0, 0 },
53216 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53217 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43200 }
53218 },
53219/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53220 {
53221 { 0, 0, 0, 0 },
53222 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53223 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60200 }
53224 },
53225/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53226 {
53227 { 0, 0, 0, 0 },
53228 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53229 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62200 }
53230 },
53231/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53232 {
53233 { 0, 0, 0, 0 },
53234 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53235 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63200 }
53236 },
53237/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53238 {
53239 { 0, 0, 0, 0 },
53240 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53241 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63200 }
53242 },
53243/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53244 {
53245 { 0, 0, 0, 0 },
53246 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53247 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28200 }
53248 },
53249/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53250 {
53251 { 0, 0, 0, 0 },
53252 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53253 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a200 }
53254 },
53255/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53256 {
53257 { 0, 0, 0, 0 },
53258 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53259 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b200 }
53260 },
53261/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53262 {
53263 { 0, 0, 0, 0 },
53264 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53265 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b200 }
53266 },
53267/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53268 {
53269 { 0, 0, 0, 0 },
53270 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53271 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48200 }
53272 },
53273/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53274 {
53275 { 0, 0, 0, 0 },
53276 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53277 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a200 }
53278 },
53279/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53280 {
53281 { 0, 0, 0, 0 },
53282 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53283 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b200 }
53284 },
53285/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53286 {
53287 { 0, 0, 0, 0 },
53288 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53289 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b200 }
53290 },
53291/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53292 {
53293 { 0, 0, 0, 0 },
53294 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53295 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c200 }
53296 },
53297/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53298 {
53299 { 0, 0, 0, 0 },
53300 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53301 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e200 }
53302 },
53303/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53304 {
53305 { 0, 0, 0, 0 },
53306 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53307 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f200 }
53308 },
53309/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53310 {
53311 { 0, 0, 0, 0 },
53312 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53313 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f200 }
53314 },
53315/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53316 {
53317 { 0, 0, 0, 0 },
53318 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53319 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c200 }
53320 },
53321/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53322 {
53323 { 0, 0, 0, 0 },
53324 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53325 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e200 }
53326 },
53327/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53328 {
53329 { 0, 0, 0, 0 },
53330 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53331 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f200 }
53332 },
53333/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53334 {
53335 { 0, 0, 0, 0 },
53336 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53337 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f200 }
53338 },
53339/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53340 {
53341 { 0, 0, 0, 0 },
53342 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
53343 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c200 }
53344 },
53345/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53346 {
53347 { 0, 0, 0, 0 },
53348 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
53349 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e200 }
53350 },
53351/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53352 {
53353 { 0, 0, 0, 0 },
53354 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
53355 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f200 }
53356 },
53357/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
53358 {
53359 { 0, 0, 0, 0 },
53360 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
53361 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f200 }
53362 },
53363/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53364 {
53365 { 0, 0, 0, 0 },
53366 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
53367 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68200 }
53368 },
53369/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53370 {
53371 { 0, 0, 0, 0 },
53372 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
53373 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a200 }
53374 },
53375/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53376 {
53377 { 0, 0, 0, 0 },
53378 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
53379 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b200 }
53380 },
53381/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
53382 {
53383 { 0, 0, 0, 0 },
53384 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
53385 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b200 }
53386 },
53387/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53388 {
53389 { 0, 0, 0, 0 },
53390 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53391 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80200 }
53392 },
53393/* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53394 {
53395 { 0, 0, 0, 0 },
53396 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
53397 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82200 }
53398 },
53399/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53400 {
53401 { 0, 0, 0, 0 },
53402 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53403 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08200 }
53404 },
53405/* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53406 {
53407 { 0, 0, 0, 0 },
53408 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
53409 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a200 }
53410 },
53411/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53412 {
53413 { 0, 0, 0, 0 },
53414 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53415 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00200 }
53416 },
53417/* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53418 {
53419 { 0, 0, 0, 0 },
53420 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53421 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02200 }
53422 },
53423/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53424 {
53425 { 0, 0, 0, 0 },
53426 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53427 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20200 }
53428 },
53429/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53430 {
53431 { 0, 0, 0, 0 },
53432 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53433 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22200 }
53434 },
53435/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53436 {
53437 { 0, 0, 0, 0 },
53438 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53439 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40200 }
53440 },
53441/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53442 {
53443 { 0, 0, 0, 0 },
53444 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53445 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42200 }
53446 },
53447/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53448 {
53449 { 0, 0, 0, 0 },
53450 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53451 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60200 }
53452 },
53453/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53454 {
53455 { 0, 0, 0, 0 },
53456 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53457 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62200 }
53458 },
53459/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53460 {
53461 { 0, 0, 0, 0 },
53462 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
53463 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28200 }
53464 },
53465/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53466 {
53467 { 0, 0, 0, 0 },
53468 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
53469 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a200 }
53470 },
53471/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53472 {
53473 { 0, 0, 0, 0 },
53474 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
53475 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48200 }
53476 },
53477/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53478 {
53479 { 0, 0, 0, 0 },
53480 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
53481 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a200 }
53482 },
53483/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53484 {
53485 { 0, 0, 0, 0 },
53486 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
53487 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c200 }
53488 },
53489/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53490 {
53491 { 0, 0, 0, 0 },
53492 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
53493 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e200 }
53494 },
53495/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53496 {
53497 { 0, 0, 0, 0 },
53498 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
53499 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c200 }
53500 },
53501/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53502 {
53503 { 0, 0, 0, 0 },
53504 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
53505 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e200 }
53506 },
53507/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53508 {
53509 { 0, 0, 0, 0 },
53510 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
53511 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c200 }
53512 },
53513/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53514 {
53515 { 0, 0, 0, 0 },
53516 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
53517 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e200 }
53518 },
53519/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53520 {
53521 { 0, 0, 0, 0 },
53522 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
53523 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68200 }
53524 },
53525/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53526 {
53527 { 0, 0, 0, 0 },
53528 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
53529 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a200 }
53530 },
53531/* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53532 {
53533 { 0, 0, 0, 0 },
53534 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53535 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c802 }
53536 },
53537/* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53538 {
53539 { 0, 0, 0, 0 },
53540 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53541 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18822 }
53542 },
53543/* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53544 {
53545 { 0, 0, 0, 0 },
53546 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53547 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18802 }
53548 },
53549/* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53550 {
53551 { 0, 0, 0, 0 },
53552 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53553 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c082 }
53554 },
53555/* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53556 {
53557 { 0, 0, 0, 0 },
53558 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53559 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a2 }
53560 },
53561/* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53562 {
53563 { 0, 0, 0, 0 },
53564 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53565 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18082 }
53566 },
53567/* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53568 {
53569 { 0, 0, 0, 0 },
53570 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53571 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c002 }
53572 },
53573/* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53574 {
53575 { 0, 0, 0, 0 },
53576 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53577 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18022 }
53578 },
53579/* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53580 {
53581 { 0, 0, 0, 0 },
53582 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53583 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18002 }
53584 },
53585/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53586 {
53587 { 0, 0, 0, 0 },
53588 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53589 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20200 }
53590 },
53591/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53592 {
53593 { 0, 0, 0, 0 },
53594 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53595 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822200 }
53596 },
53597/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53598 {
53599 { 0, 0, 0, 0 },
53600 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53601 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820200 }
53602 },
53603/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53604 {
53605 { 0, 0, 0, 0 },
53606 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53607 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40200 }
53608 },
53609/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53610 {
53611 { 0, 0, 0, 0 },
53612 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53613 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842200 }
53614 },
53615/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53616 {
53617 { 0, 0, 0, 0 },
53618 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53619 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840200 }
53620 },
53621/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53622 {
53623 { 0, 0, 0, 0 },
53624 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53625 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60200 }
53626 },
53627/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53628 {
53629 { 0, 0, 0, 0 },
53630 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53631 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862200 }
53632 },
53633/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53634 {
53635 { 0, 0, 0, 0 },
53636 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53637 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860200 }
53638 },
53639/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53640 {
53641 { 0, 0, 0, 0 },
53642 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53643 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28200 }
53644 },
53645/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53646 {
53647 { 0, 0, 0, 0 },
53648 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53649 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a200 }
53650 },
53651/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53652 {
53653 { 0, 0, 0, 0 },
53654 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53655 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828200 }
53656 },
53657/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53658 {
53659 { 0, 0, 0, 0 },
53660 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53661 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48200 }
53662 },
53663/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53664 {
53665 { 0, 0, 0, 0 },
53666 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53667 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a200 }
53668 },
53669/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53670 {
53671 { 0, 0, 0, 0 },
53672 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53673 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848200 }
53674 },
53675/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53676 {
53677 { 0, 0, 0, 0 },
53678 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53679 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c200 }
53680 },
53681/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53682 {
53683 { 0, 0, 0, 0 },
53684 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53685 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e200 }
53686 },
53687/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53688 {
53689 { 0, 0, 0, 0 },
53690 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53691 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c200 }
53692 },
53693/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53694 {
53695 { 0, 0, 0, 0 },
53696 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53697 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c200 }
53698 },
53699/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53700 {
53701 { 0, 0, 0, 0 },
53702 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53703 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e200 }
53704 },
53705/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53706 {
53707 { 0, 0, 0, 0 },
53708 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53709 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c200 }
53710 },
53711/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53712 {
53713 { 0, 0, 0, 0 },
53714 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
53715 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c200 }
53716 },
53717/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53718 {
53719 { 0, 0, 0, 0 },
53720 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
53721 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e200 }
53722 },
53723/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53724 {
53725 { 0, 0, 0, 0 },
53726 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
53727 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c200 }
53728 },
53729/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53730 {
53731 { 0, 0, 0, 0 },
53732 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
53733 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68200 }
53734 },
53735/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53736 {
53737 { 0, 0, 0, 0 },
53738 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
53739 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a200 }
53740 },
53741/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53742 {
53743 { 0, 0, 0, 0 },
53744 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
53745 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868200 }
53746 },
53747/* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53748 {
53749 { 0, 0, 0, 0 },
53750 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
53751 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1991e00 }
53752 },
53753/* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53754 {
53755 { 0, 0, 0, 0 },
53756 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
53757 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1919e00 }
53758 },
53759/* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53760 {
53761 { 0, 0, 0, 0 },
53762 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53763 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1911e00 }
53764 },
53765/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53766 {
53767 { 0, 0, 0, 0 },
53768 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53769 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1931e00 }
53770 },
53771/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53772 {
53773 { 0, 0, 0, 0 },
53774 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53775 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1939e00 }
53776 },
53777/* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53778 {
53779 { 0, 0, 0, 0 },
53780 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53781 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193de00 }
53782 },
53783/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53784 {
53785 { 0, 0, 0, 0 },
53786 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53787 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1951e00 }
53788 },
53789/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53790 {
53791 { 0, 0, 0, 0 },
53792 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53793 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1959e00 }
53794 },
53795/* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53796 {
53797 { 0, 0, 0, 0 },
53798 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53799 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195de00 }
53800 },
53801/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53802 {
53803 { 0, 0, 0, 0 },
53804 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
53805 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197de00 }
53806 },
53807/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53808 {
53809 { 0, 0, 0, 0 },
53810 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53811 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1971e00 }
53812 },
53813/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53814 {
53815 { 0, 0, 0, 0 },
53816 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
53817 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1979e00 }
53818 },
53819/* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53820 {
53821 { 0, 0, 0, 0 },
53822 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53823 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1981e00 }
53824 },
53825/* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53826 {
53827 { 0, 0, 0, 0 },
53828 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53829 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1909e00 }
53830 },
53831/* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53832 {
53833 { 0, 0, 0, 0 },
53834 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53835 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1901e00 }
53836 },
53837/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53838 {
53839 { 0, 0, 0, 0 },
53840 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53841 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1921e00 }
53842 },
53843/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53844 {
53845 { 0, 0, 0, 0 },
53846 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53847 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1929e00 }
53848 },
53849/* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53850 {
53851 { 0, 0, 0, 0 },
53852 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53853 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192de00 }
53854 },
53855/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53856 {
53857 { 0, 0, 0, 0 },
53858 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53859 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1941e00 }
53860 },
53861/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53862 {
53863 { 0, 0, 0, 0 },
53864 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53865 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1949e00 }
53866 },
53867/* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53868 {
53869 { 0, 0, 0, 0 },
53870 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53871 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194de00 }
53872 },
53873/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53874 {
53875 { 0, 0, 0, 0 },
53876 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
53877 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196de00 }
53878 },
53879/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53880 {
53881 { 0, 0, 0, 0 },
53882 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53883 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1961e00 }
53884 },
53885/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53886 {
53887 { 0, 0, 0, 0 },
53888 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
53889 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1969e00 }
53890 },
53891/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53892 {
53893 { 0, 0, 0, 0 },
53894 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53895 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990a00 }
53896 },
53897/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53898 {
53899 { 0, 0, 0, 0 },
53900 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53901 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992a00 }
53902 },
53903/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53904 {
53905 { 0, 0, 0, 0 },
53906 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53907 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993a00 }
53908 },
53909/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53910 {
53911 { 0, 0, 0, 0 },
53912 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53913 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918a00 }
53914 },
53915/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53916 {
53917 { 0, 0, 0, 0 },
53918 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53919 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191aa00 }
53920 },
53921/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53922 {
53923 { 0, 0, 0, 0 },
53924 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53925 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ba00 }
53926 },
53927/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53928 {
53929 { 0, 0, 0, 0 },
53930 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53931 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910a00 }
53932 },
53933/* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53934 {
53935 { 0, 0, 0, 0 },
53936 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53937 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912a00 }
53938 },
53939/* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53940 {
53941 { 0, 0, 0, 0 },
53942 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53943 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913a00 }
53944 },
53945/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53946 {
53947 { 0, 0, 0, 0 },
53948 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53949 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930a00 }
53950 },
53951/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53952 {
53953 { 0, 0, 0, 0 },
53954 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53955 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932a00 }
53956 },
53957/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53958 {
53959 { 0, 0, 0, 0 },
53960 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53961 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933a00 }
53962 },
53963/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53964 {
53965 { 0, 0, 0, 0 },
53966 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53967 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950a00 }
53968 },
53969/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53970 {
53971 { 0, 0, 0, 0 },
53972 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53973 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952a00 }
53974 },
53975/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53976 {
53977 { 0, 0, 0, 0 },
53978 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53979 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953a00 }
53980 },
53981/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53982 {
53983 { 0, 0, 0, 0 },
53984 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53985 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970a00 }
53986 },
53987/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53988 {
53989 { 0, 0, 0, 0 },
53990 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53991 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972a00 }
53992 },
53993/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53994 {
53995 { 0, 0, 0, 0 },
53996 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53997 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973a00 }
53998 },
53999/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54000 {
54001 { 0, 0, 0, 0 },
54002 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54003 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938a00 }
54004 },
54005/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54006 {
54007 { 0, 0, 0, 0 },
54008 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54009 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193aa00 }
54010 },
54011/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54012 {
54013 { 0, 0, 0, 0 },
54014 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54015 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ba00 }
54016 },
54017/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54018 {
54019 { 0, 0, 0, 0 },
54020 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54021 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958a00 }
54022 },
54023/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54024 {
54025 { 0, 0, 0, 0 },
54026 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54027 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195aa00 }
54028 },
54029/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54030 {
54031 { 0, 0, 0, 0 },
54032 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54033 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ba00 }
54034 },
54035/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54036 {
54037 { 0, 0, 0, 0 },
54038 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54039 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ca00 }
54040 },
54041/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54042 {
54043 { 0, 0, 0, 0 },
54044 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54045 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ea00 }
54046 },
54047/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54048 {
54049 { 0, 0, 0, 0 },
54050 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54051 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fa00 }
54052 },
54053/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54054 {
54055 { 0, 0, 0, 0 },
54056 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54057 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ca00 }
54058 },
54059/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54060 {
54061 { 0, 0, 0, 0 },
54062 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54063 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ea00 }
54064 },
54065/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54066 {
54067 { 0, 0, 0, 0 },
54068 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54069 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fa00 }
54070 },
54071/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54072 {
54073 { 0, 0, 0, 0 },
54074 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
54075 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ca00 }
54076 },
54077/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54078 {
54079 { 0, 0, 0, 0 },
54080 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54081 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ea00 }
54082 },
54083/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54084 {
54085 { 0, 0, 0, 0 },
54086 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54087 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fa00 }
54088 },
54089/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54090 {
54091 { 0, 0, 0, 0 },
54092 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
54093 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978a00 }
54094 },
54095/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54096 {
54097 { 0, 0, 0, 0 },
54098 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54099 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197aa00 }
54100 },
54101/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54102 {
54103 { 0, 0, 0, 0 },
54104 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54105 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ba00 }
54106 },
54107/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54108 {
54109 { 0, 0, 0, 0 },
54110 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54111 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90a00 }
54112 },
54113/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
54114 {
54115 { 0, 0, 0, 0 },
54116 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54117 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92a00 }
54118 },
54119/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
54120 {
54121 { 0, 0, 0, 0 },
54122 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54123 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93a00 }
54124 },
54125/* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
54126 {
54127 { 0, 0, 0, 0 },
54128 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
54129 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93a00 }
54130 },
54131/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54132 {
54133 { 0, 0, 0, 0 },
54134 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54135 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18a00 }
54136 },
54137/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
54138 {
54139 { 0, 0, 0, 0 },
54140 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54141 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1aa00 }
54142 },
54143/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
54144 {
54145 { 0, 0, 0, 0 },
54146 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54147 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ba00 }
54148 },
54149/* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
54150 {
54151 { 0, 0, 0, 0 },
54152 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
54153 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ba00 }
54154 },
54155/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54156 {
54157 { 0, 0, 0, 0 },
54158 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54159 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10a00 }
54160 },
54161/* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54162 {
54163 { 0, 0, 0, 0 },
54164 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54165 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12a00 }
54166 },
54167/* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54168 {
54169 { 0, 0, 0, 0 },
54170 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54171 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13a00 }
54172 },
54173/* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54174 {
54175 { 0, 0, 0, 0 },
54176 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54177 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13a00 }
54178 },
54179/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54180 {
54181 { 0, 0, 0, 0 },
54182 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54183 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30a00 }
54184 },
54185/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54186 {
54187 { 0, 0, 0, 0 },
54188 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54189 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32a00 }
54190 },
54191/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54192 {
54193 { 0, 0, 0, 0 },
54194 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54195 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33a00 }
54196 },
54197/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54198 {
54199 { 0, 0, 0, 0 },
54200 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54201 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33a00 }
54202 },
54203/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54204 {
54205 { 0, 0, 0, 0 },
54206 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54207 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50a00 }
54208 },
54209/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54210 {
54211 { 0, 0, 0, 0 },
54212 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54213 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52a00 }
54214 },
54215/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54216 {
54217 { 0, 0, 0, 0 },
54218 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54219 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53a00 }
54220 },
54221/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54222 {
54223 { 0, 0, 0, 0 },
54224 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54225 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53a00 }
54226 },
54227/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54228 {
54229 { 0, 0, 0, 0 },
54230 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54231 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70a00 }
54232 },
54233/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54234 {
54235 { 0, 0, 0, 0 },
54236 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54237 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72a00 }
54238 },
54239/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54240 {
54241 { 0, 0, 0, 0 },
54242 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54243 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73a00 }
54244 },
54245/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54246 {
54247 { 0, 0, 0, 0 },
54248 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54249 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73a00 }
54250 },
54251/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54252 {
54253 { 0, 0, 0, 0 },
54254 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54255 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38a00 }
54256 },
54257/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54258 {
54259 { 0, 0, 0, 0 },
54260 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54261 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3aa00 }
54262 },
54263/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54264 {
54265 { 0, 0, 0, 0 },
54266 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54267 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ba00 }
54268 },
54269/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54270 {
54271 { 0, 0, 0, 0 },
54272 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54273 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3ba00 }
54274 },
54275/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54276 {
54277 { 0, 0, 0, 0 },
54278 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54279 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58a00 }
54280 },
54281/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54282 {
54283 { 0, 0, 0, 0 },
54284 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54285 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5aa00 }
54286 },
54287/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54288 {
54289 { 0, 0, 0, 0 },
54290 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54291 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ba00 }
54292 },
54293/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54294 {
54295 { 0, 0, 0, 0 },
54296 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54297 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5ba00 }
54298 },
54299/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54300 {
54301 { 0, 0, 0, 0 },
54302 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54303 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ca00 }
54304 },
54305/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54306 {
54307 { 0, 0, 0, 0 },
54308 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54309 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ea00 }
54310 },
54311/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54312 {
54313 { 0, 0, 0, 0 },
54314 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54315 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fa00 }
54316 },
54317/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54318 {
54319 { 0, 0, 0, 0 },
54320 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54321 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fa00 }
54322 },
54323/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54324 {
54325 { 0, 0, 0, 0 },
54326 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54327 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ca00 }
54328 },
54329/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54330 {
54331 { 0, 0, 0, 0 },
54332 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54333 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ea00 }
54334 },
54335/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54336 {
54337 { 0, 0, 0, 0 },
54338 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54339 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fa00 }
54340 },
54341/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54342 {
54343 { 0, 0, 0, 0 },
54344 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54345 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fa00 }
54346 },
54347/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54348 {
54349 { 0, 0, 0, 0 },
54350 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
54351 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ca00 }
54352 },
54353/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54354 {
54355 { 0, 0, 0, 0 },
54356 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
54357 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ea00 }
54358 },
54359/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54360 {
54361 { 0, 0, 0, 0 },
54362 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
54363 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fa00 }
54364 },
54365/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
54366 {
54367 { 0, 0, 0, 0 },
54368 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
54369 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fa00 }
54370 },
54371/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54372 {
54373 { 0, 0, 0, 0 },
54374 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
54375 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78a00 }
54376 },
54377/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54378 {
54379 { 0, 0, 0, 0 },
54380 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
54381 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7aa00 }
54382 },
54383/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54384 {
54385 { 0, 0, 0, 0 },
54386 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
54387 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ba00 }
54388 },
54389/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
54390 {
54391 { 0, 0, 0, 0 },
54392 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
54393 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7ba00 }
54394 },
54395/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54396 {
54397 { 0, 0, 0, 0 },
54398 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54399 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90a00 }
54400 },
54401/* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
54402 {
54403 { 0, 0, 0, 0 },
54404 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
54405 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92a00 }
54406 },
54407/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54408 {
54409 { 0, 0, 0, 0 },
54410 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54411 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18a00 }
54412 },
54413/* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
54414 {
54415 { 0, 0, 0, 0 },
54416 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
54417 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1aa00 }
54418 },
54419/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54420 {
54421 { 0, 0, 0, 0 },
54422 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54423 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10a00 }
54424 },
54425/* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54426 {
54427 { 0, 0, 0, 0 },
54428 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54429 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12a00 }
54430 },
54431/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54432 {
54433 { 0, 0, 0, 0 },
54434 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54435 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30a00 }
54436 },
54437/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54438 {
54439 { 0, 0, 0, 0 },
54440 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54441 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32a00 }
54442 },
54443/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54444 {
54445 { 0, 0, 0, 0 },
54446 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54447 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50a00 }
54448 },
54449/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54450 {
54451 { 0, 0, 0, 0 },
54452 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54453 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52a00 }
54454 },
54455/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54456 {
54457 { 0, 0, 0, 0 },
54458 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54459 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70a00 }
54460 },
54461/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54462 {
54463 { 0, 0, 0, 0 },
54464 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54465 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72a00 }
54466 },
54467/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54468 {
54469 { 0, 0, 0, 0 },
54470 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54471 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38a00 }
54472 },
54473/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54474 {
54475 { 0, 0, 0, 0 },
54476 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54477 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3aa00 }
54478 },
54479/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54480 {
54481 { 0, 0, 0, 0 },
54482 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54483 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58a00 }
54484 },
54485/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54486 {
54487 { 0, 0, 0, 0 },
54488 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54489 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5aa00 }
54490 },
54491/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54492 {
54493 { 0, 0, 0, 0 },
54494 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54495 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ca00 }
54496 },
54497/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54498 {
54499 { 0, 0, 0, 0 },
54500 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54501 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ea00 }
54502 },
54503/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54504 {
54505 { 0, 0, 0, 0 },
54506 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54507 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ca00 }
54508 },
54509/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54510 {
54511 { 0, 0, 0, 0 },
54512 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54513 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ea00 }
54514 },
54515/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54516 {
54517 { 0, 0, 0, 0 },
54518 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
54519 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ca00 }
54520 },
54521/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
54522 {
54523 { 0, 0, 0, 0 },
54524 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
54525 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ea00 }
54526 },
54527/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54528 {
54529 { 0, 0, 0, 0 },
54530 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
54531 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78a00 }
54532 },
54533/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
54534 {
54535 { 0, 0, 0, 0 },
54536 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
54537 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7aa00 }
54538 },
54539/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
54540 {
54541 { 0, 0, 0, 0 },
54542 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
54543 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90a }
54544 },
54545/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
54546 {
54547 { 0, 0, 0, 0 },
54548 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
54549 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892a }
54550 },
54551/* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
54552 {
54553 { 0, 0, 0, 0 },
54554 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54555 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890a }
54556 },
54557/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
54558 {
54559 { 0, 0, 0, 0 },
54560 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
54561 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18a }
54562 },
54563/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
54564 {
54565 { 0, 0, 0, 0 },
54566 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
54567 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181aa }
54568 },
54569/* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
54570 {
54571 { 0, 0, 0, 0 },
54572 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54573 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818a }
54574 },
54575/* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
54576 {
54577 { 0, 0, 0, 0 },
54578 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54579 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10a }
54580 },
54581/* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
54582 {
54583 { 0, 0, 0, 0 },
54584 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54585 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812a }
54586 },
54587/* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54588 {
54589 { 0, 0, 0, 0 },
54590 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54591 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810a }
54592 },
54593/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54594 {
54595 { 0, 0, 0, 0 },
54596 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54597 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30a00 }
54598 },
54599/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54600 {
54601 { 0, 0, 0, 0 },
54602 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54603 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832a00 }
54604 },
54605/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54606 {
54607 { 0, 0, 0, 0 },
54608 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54609 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830a00 }
54610 },
54611/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54612 {
54613 { 0, 0, 0, 0 },
54614 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54615 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50a00 }
54616 },
54617/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54618 {
54619 { 0, 0, 0, 0 },
54620 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54621 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852a00 }
54622 },
54623/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54624 {
54625 { 0, 0, 0, 0 },
54626 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54627 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850a00 }
54628 },
54629/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54630 {
54631 { 0, 0, 0, 0 },
54632 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54633 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70a00 }
54634 },
54635/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54636 {
54637 { 0, 0, 0, 0 },
54638 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54639 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872a00 }
54640 },
54641/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54642 {
54643 { 0, 0, 0, 0 },
54644 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54645 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870a00 }
54646 },
54647/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54648 {
54649 { 0, 0, 0, 0 },
54650 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54651 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38a00 }
54652 },
54653/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54654 {
54655 { 0, 0, 0, 0 },
54656 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54657 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183aa00 }
54658 },
54659/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54660 {
54661 { 0, 0, 0, 0 },
54662 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54663 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838a00 }
54664 },
54665/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54666 {
54667 { 0, 0, 0, 0 },
54668 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54669 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58a00 }
54670 },
54671/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54672 {
54673 { 0, 0, 0, 0 },
54674 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54675 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185aa00 }
54676 },
54677/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54678 {
54679 { 0, 0, 0, 0 },
54680 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54681 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858a00 }
54682 },
54683/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54684 {
54685 { 0, 0, 0, 0 },
54686 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54687 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3ca00 }
54688 },
54689/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54690 {
54691 { 0, 0, 0, 0 },
54692 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54693 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ea00 }
54694 },
54695/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54696 {
54697 { 0, 0, 0, 0 },
54698 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54699 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ca00 }
54700 },
54701/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54702 {
54703 { 0, 0, 0, 0 },
54704 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54705 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5ca00 }
54706 },
54707/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54708 {
54709 { 0, 0, 0, 0 },
54710 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54711 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ea00 }
54712 },
54713/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54714 {
54715 { 0, 0, 0, 0 },
54716 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54717 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ca00 }
54718 },
54719/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54720 {
54721 { 0, 0, 0, 0 },
54722 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
54723 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7ca00 }
54724 },
54725/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54726 {
54727 { 0, 0, 0, 0 },
54728 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
54729 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ea00 }
54730 },
54731/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54732 {
54733 { 0, 0, 0, 0 },
54734 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
54735 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ca00 }
54736 },
54737/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54738 {
54739 { 0, 0, 0, 0 },
54740 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
54741 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78a00 }
54742 },
54743/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54744 {
54745 { 0, 0, 0, 0 },
54746 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
54747 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187aa00 }
54748 },
54749/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54750 {
54751 { 0, 0, 0, 0 },
54752 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
54753 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878a00 }
54754 },
54755/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54756 {
54757 { 0, 0, 0, 0 },
54758 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54759 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980a00 }
54760 },
54761/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54762 {
54763 { 0, 0, 0, 0 },
54764 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54765 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982a00 }
54766 },
54767/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54768 {
54769 { 0, 0, 0, 0 },
54770 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54771 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983a00 }
54772 },
54773/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54774 {
54775 { 0, 0, 0, 0 },
54776 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54777 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908a00 }
54778 },
54779/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54780 {
54781 { 0, 0, 0, 0 },
54782 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54783 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190aa00 }
54784 },
54785/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54786 {
54787 { 0, 0, 0, 0 },
54788 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54789 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ba00 }
54790 },
54791/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54792 {
54793 { 0, 0, 0, 0 },
54794 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54795 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900a00 }
54796 },
54797/* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54798 {
54799 { 0, 0, 0, 0 },
54800 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54801 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902a00 }
54802 },
54803/* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54804 {
54805 { 0, 0, 0, 0 },
54806 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54807 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903a00 }
54808 },
54809/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54810 {
54811 { 0, 0, 0, 0 },
54812 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54813 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920a00 }
54814 },
54815/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54816 {
54817 { 0, 0, 0, 0 },
54818 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54819 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922a00 }
54820 },
54821/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54822 {
54823 { 0, 0, 0, 0 },
54824 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54825 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923a00 }
54826 },
54827/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54828 {
54829 { 0, 0, 0, 0 },
54830 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54831 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940a00 }
54832 },
54833/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54834 {
54835 { 0, 0, 0, 0 },
54836 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54837 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942a00 }
54838 },
54839/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54840 {
54841 { 0, 0, 0, 0 },
54842 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54843 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943a00 }
54844 },
54845/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54846 {
54847 { 0, 0, 0, 0 },
54848 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54849 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960a00 }
54850 },
54851/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54852 {
54853 { 0, 0, 0, 0 },
54854 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54855 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962a00 }
54856 },
54857/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54858 {
54859 { 0, 0, 0, 0 },
54860 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54861 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963a00 }
54862 },
54863/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54864 {
54865 { 0, 0, 0, 0 },
54866 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54867 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928a00 }
54868 },
54869/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54870 {
54871 { 0, 0, 0, 0 },
54872 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54873 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192aa00 }
54874 },
54875/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54876 {
54877 { 0, 0, 0, 0 },
54878 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54879 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ba00 }
54880 },
54881/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54882 {
54883 { 0, 0, 0, 0 },
54884 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54885 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948a00 }
54886 },
54887/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54888 {
54889 { 0, 0, 0, 0 },
54890 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54891 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194aa00 }
54892 },
54893/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54894 {
54895 { 0, 0, 0, 0 },
54896 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54897 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ba00 }
54898 },
54899/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54900 {
54901 { 0, 0, 0, 0 },
54902 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54903 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ca00 }
54904 },
54905/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54906 {
54907 { 0, 0, 0, 0 },
54908 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54909 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ea00 }
54910 },
54911/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54912 {
54913 { 0, 0, 0, 0 },
54914 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54915 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fa00 }
54916 },
54917/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54918 {
54919 { 0, 0, 0, 0 },
54920 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54921 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ca00 }
54922 },
54923/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54924 {
54925 { 0, 0, 0, 0 },
54926 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54927 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ea00 }
54928 },
54929/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54930 {
54931 { 0, 0, 0, 0 },
54932 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54933 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fa00 }
54934 },
54935/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54936 {
54937 { 0, 0, 0, 0 },
54938 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
54939 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ca00 }
54940 },
54941/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54942 {
54943 { 0, 0, 0, 0 },
54944 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54945 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ea00 }
54946 },
54947/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54948 {
54949 { 0, 0, 0, 0 },
54950 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54951 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fa00 }
54952 },
54953/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54954 {
54955 { 0, 0, 0, 0 },
54956 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
54957 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968a00 }
54958 },
54959/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54960 {
54961 { 0, 0, 0, 0 },
54962 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54963 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196aa00 }
54964 },
54965/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54966 {
54967 { 0, 0, 0, 0 },
54968 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54969 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ba00 }
54970 },
54971/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54972 {
54973 { 0, 0, 0, 0 },
54974 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54975 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80a00 }
54976 },
54977/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54978 {
54979 { 0, 0, 0, 0 },
54980 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54981 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82a00 }
54982 },
54983/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54984 {
54985 { 0, 0, 0, 0 },
54986 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54987 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83a00 }
54988 },
54989/* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54990 {
54991 { 0, 0, 0, 0 },
54992 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
54993 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83a00 }
54994 },
54995/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54996 {
54997 { 0, 0, 0, 0 },
54998 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54999 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08a00 }
55000 },
55001/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
55002 {
55003 { 0, 0, 0, 0 },
55004 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55005 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0aa00 }
55006 },
55007/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
55008 {
55009 { 0, 0, 0, 0 },
55010 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55011 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ba00 }
55012 },
55013/* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
55014 {
55015 { 0, 0, 0, 0 },
55016 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
55017 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ba00 }
55018 },
55019/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55020 {
55021 { 0, 0, 0, 0 },
55022 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55023 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00a00 }
55024 },
55025/* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55026 {
55027 { 0, 0, 0, 0 },
55028 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55029 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02a00 }
55030 },
55031/* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55032 {
55033 { 0, 0, 0, 0 },
55034 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55035 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03a00 }
55036 },
55037/* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55038 {
55039 { 0, 0, 0, 0 },
55040 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55041 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03a00 }
55042 },
55043/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55044 {
55045 { 0, 0, 0, 0 },
55046 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55047 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20a00 }
55048 },
55049/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55050 {
55051 { 0, 0, 0, 0 },
55052 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55053 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22a00 }
55054 },
55055/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55056 {
55057 { 0, 0, 0, 0 },
55058 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55059 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23a00 }
55060 },
55061/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55062 {
55063 { 0, 0, 0, 0 },
55064 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55065 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23a00 }
55066 },
55067/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55068 {
55069 { 0, 0, 0, 0 },
55070 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55071 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40a00 }
55072 },
55073/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55074 {
55075 { 0, 0, 0, 0 },
55076 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55077 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42a00 }
55078 },
55079/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55080 {
55081 { 0, 0, 0, 0 },
55082 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55083 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43a00 }
55084 },
55085/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55086 {
55087 { 0, 0, 0, 0 },
55088 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55089 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43a00 }
55090 },
55091/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55092 {
55093 { 0, 0, 0, 0 },
55094 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55095 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60a00 }
55096 },
55097/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55098 {
55099 { 0, 0, 0, 0 },
55100 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55101 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62a00 }
55102 },
55103/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55104 {
55105 { 0, 0, 0, 0 },
55106 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55107 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63a00 }
55108 },
55109/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55110 {
55111 { 0, 0, 0, 0 },
55112 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55113 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63a00 }
55114 },
55115/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
55116 {
55117 { 0, 0, 0, 0 },
55118 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55119 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28a00 }
55120 },
55121/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
55122 {
55123 { 0, 0, 0, 0 },
55124 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55125 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2aa00 }
55126 },
55127/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
55128 {
55129 { 0, 0, 0, 0 },
55130 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55131 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ba00 }
55132 },
55133/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
55134 {
55135 { 0, 0, 0, 0 },
55136 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55137 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2ba00 }
55138 },
55139/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
55140 {
55141 { 0, 0, 0, 0 },
55142 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55143 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48a00 }
55144 },
55145/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
55146 {
55147 { 0, 0, 0, 0 },
55148 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55149 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4aa00 }
55150 },
55151/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
55152 {
55153 { 0, 0, 0, 0 },
55154 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55155 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ba00 }
55156 },
55157/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
55158 {
55159 { 0, 0, 0, 0 },
55160 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55161 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4ba00 }
55162 },
55163/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
55164 {
55165 { 0, 0, 0, 0 },
55166 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55167 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ca00 }
55168 },
55169/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
55170 {
55171 { 0, 0, 0, 0 },
55172 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55173 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ea00 }
55174 },
55175/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
55176 {
55177 { 0, 0, 0, 0 },
55178 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55179 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fa00 }
55180 },
55181/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
55182 {
55183 { 0, 0, 0, 0 },
55184 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55185 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fa00 }
55186 },
55187/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
55188 {
55189 { 0, 0, 0, 0 },
55190 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55191 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ca00 }
55192 },
55193/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
55194 {
55195 { 0, 0, 0, 0 },
55196 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55197 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ea00 }
55198 },
55199/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
55200 {
55201 { 0, 0, 0, 0 },
55202 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55203 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fa00 }
55204 },
55205/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
55206 {
55207 { 0, 0, 0, 0 },
55208 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55209 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fa00 }
55210 },
55211/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
55212 {
55213 { 0, 0, 0, 0 },
55214 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
55215 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ca00 }
55216 },
55217/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
55218 {
55219 { 0, 0, 0, 0 },
55220 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
55221 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ea00 }
55222 },
55223/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
55224 {
55225 { 0, 0, 0, 0 },
55226 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
55227 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fa00 }
55228 },
55229/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
55230 {
55231 { 0, 0, 0, 0 },
55232 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
55233 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fa00 }
55234 },
55235/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
55236 {
55237 { 0, 0, 0, 0 },
55238 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
55239 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68a00 }
55240 },
55241/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
55242 {
55243 { 0, 0, 0, 0 },
55244 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
55245 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6aa00 }
55246 },
55247/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
55248 {
55249 { 0, 0, 0, 0 },
55250 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
55251 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ba00 }
55252 },
55253/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
55254 {
55255 { 0, 0, 0, 0 },
55256 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
55257 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6ba00 }
55258 },
55259/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
55260 {
55261 { 0, 0, 0, 0 },
55262 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
55263 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80a00 }
55264 },
55265/* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
55266 {
55267 { 0, 0, 0, 0 },
55268 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
55269 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82a00 }
55270 },
55271/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
55272 {
55273 { 0, 0, 0, 0 },
55274 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55275 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08a00 }
55276 },
55277/* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
55278 {
55279 { 0, 0, 0, 0 },
55280 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
55281 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0aa00 }
55282 },
55283/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55284 {
55285 { 0, 0, 0, 0 },
55286 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55287 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00a00 }
55288 },
55289/* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55290 {
55291 { 0, 0, 0, 0 },
55292 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55293 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02a00 }
55294 },
55295/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55296 {
55297 { 0, 0, 0, 0 },
55298 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55299 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20a00 }
55300 },
55301/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55302 {
55303 { 0, 0, 0, 0 },
55304 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55305 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22a00 }
55306 },
55307/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55308 {
55309 { 0, 0, 0, 0 },
55310 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55311 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40a00 }
55312 },
55313/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55314 {
55315 { 0, 0, 0, 0 },
55316 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55317 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42a00 }
55318 },
55319/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55320 {
55321 { 0, 0, 0, 0 },
55322 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55323 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60a00 }
55324 },
55325/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55326 {
55327 { 0, 0, 0, 0 },
55328 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55329 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62a00 }
55330 },
55331/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55332 {
55333 { 0, 0, 0, 0 },
55334 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
55335 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28a00 }
55336 },
55337/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55338 {
55339 { 0, 0, 0, 0 },
55340 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
55341 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2aa00 }
55342 },
55343/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55344 {
55345 { 0, 0, 0, 0 },
55346 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
55347 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48a00 }
55348 },
55349/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55350 {
55351 { 0, 0, 0, 0 },
55352 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
55353 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4aa00 }
55354 },
55355/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55356 {
55357 { 0, 0, 0, 0 },
55358 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
55359 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ca00 }
55360 },
55361/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55362 {
55363 { 0, 0, 0, 0 },
55364 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
55365 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ea00 }
55366 },
55367/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55368 {
55369 { 0, 0, 0, 0 },
55370 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
55371 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ca00 }
55372 },
55373/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55374 {
55375 { 0, 0, 0, 0 },
55376 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
55377 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ea00 }
55378 },
55379/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55380 {
55381 { 0, 0, 0, 0 },
55382 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
55383 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ca00 }
55384 },
55385/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
55386 {
55387 { 0, 0, 0, 0 },
55388 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
55389 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ea00 }
55390 },
55391/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55392 {
55393 { 0, 0, 0, 0 },
55394 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
55395 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68a00 }
55396 },
55397/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
55398 {
55399 { 0, 0, 0, 0 },
55400 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
55401 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6aa00 }
55402 },
55403/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
55404 {
55405 { 0, 0, 0, 0 },
55406 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55407 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80a }
55408 },
55409/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
55410 {
55411 { 0, 0, 0, 0 },
55412 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55413 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882a }
55414 },
55415/* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
55416 {
55417 { 0, 0, 0, 0 },
55418 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
55419 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880a }
55420 },
55421/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
55422 {
55423 { 0, 0, 0, 0 },
55424 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55425 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08a }
55426 },
55427/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
55428 {
55429 { 0, 0, 0, 0 },
55430 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55431 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180aa }
55432 },
55433/* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
55434 {
55435 { 0, 0, 0, 0 },
55436 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55437 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808a }
55438 },
55439/* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
55440 {
55441 { 0, 0, 0, 0 },
55442 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55443 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00a }
55444 },
55445/* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
55446 {
55447 { 0, 0, 0, 0 },
55448 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55449 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802a }
55450 },
55451/* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55452 {
55453 { 0, 0, 0, 0 },
55454 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55455 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800a }
55456 },
55457/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55458 {
55459 { 0, 0, 0, 0 },
55460 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55461 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20a00 }
55462 },
55463/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55464 {
55465 { 0, 0, 0, 0 },
55466 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55467 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822a00 }
55468 },
55469/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55470 {
55471 { 0, 0, 0, 0 },
55472 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55473 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820a00 }
55474 },
55475/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55476 {
55477 { 0, 0, 0, 0 },
55478 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55479 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40a00 }
55480 },
55481/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55482 {
55483 { 0, 0, 0, 0 },
55484 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55485 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842a00 }
55486 },
55487/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55488 {
55489 { 0, 0, 0, 0 },
55490 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55491 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840a00 }
55492 },
55493/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55494 {
55495 { 0, 0, 0, 0 },
55496 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55497 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60a00 }
55498 },
55499/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55500 {
55501 { 0, 0, 0, 0 },
55502 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55503 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862a00 }
55504 },
55505/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55506 {
55507 { 0, 0, 0, 0 },
55508 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55509 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860a00 }
55510 },
55511/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
55512 {
55513 { 0, 0, 0, 0 },
55514 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55515 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28a00 }
55516 },
55517/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
55518 {
55519 { 0, 0, 0, 0 },
55520 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55521 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182aa00 }
55522 },
55523/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55524 {
55525 { 0, 0, 0, 0 },
55526 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55527 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828a00 }
55528 },
55529/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
55530 {
55531 { 0, 0, 0, 0 },
55532 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55533 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48a00 }
55534 },
55535/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
55536 {
55537 { 0, 0, 0, 0 },
55538 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55539 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184aa00 }
55540 },
55541/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55542 {
55543 { 0, 0, 0, 0 },
55544 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55545 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848a00 }
55546 },
55547/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
55548 {
55549 { 0, 0, 0, 0 },
55550 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55551 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2ca00 }
55552 },
55553/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
55554 {
55555 { 0, 0, 0, 0 },
55556 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55557 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ea00 }
55558 },
55559/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55560 {
55561 { 0, 0, 0, 0 },
55562 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55563 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ca00 }
55564 },
55565/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
55566 {
55567 { 0, 0, 0, 0 },
55568 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55569 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4ca00 }
55570 },
55571/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
55572 {
55573 { 0, 0, 0, 0 },
55574 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55575 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ea00 }
55576 },
55577/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55578 {
55579 { 0, 0, 0, 0 },
55580 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55581 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ca00 }
55582 },
55583/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
55584 {
55585 { 0, 0, 0, 0 },
55586 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
55587 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6ca00 }
55588 },
55589/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
55590 {
55591 { 0, 0, 0, 0 },
55592 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
55593 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ea00 }
55594 },
55595/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55596 {
55597 { 0, 0, 0, 0 },
55598 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
55599 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ca00 }
55600 },
55601/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
55602 {
55603 { 0, 0, 0, 0 },
55604 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
55605 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68a00 }
55606 },
55607/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
55608 {
55609 { 0, 0, 0, 0 },
55610 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
55611 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186aa00 }
55612 },
55613/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55614 {
55615 { 0, 0, 0, 0 },
55616 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
55617 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868a00 }
55618 },
55619/* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
55620 {
55621 { 0, 0, 0, 0 },
55622 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
55623 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1990e00 }
55624 },
55625/* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
55626 {
55627 { 0, 0, 0, 0 },
55628 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
55629 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1918e00 }
55630 },
55631/* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
55632 {
55633 { 0, 0, 0, 0 },
55634 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55635 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1910e00 }
55636 },
55637/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55638 {
55639 { 0, 0, 0, 0 },
55640 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55641 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1930e00 }
55642 },
55643/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
55644 {
55645 { 0, 0, 0, 0 },
55646 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55647 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1938e00 }
55648 },
55649/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
55650 {
55651 { 0, 0, 0, 0 },
55652 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55653 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ce00 }
55654 },
55655/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55656 {
55657 { 0, 0, 0, 0 },
55658 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55659 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1950e00 }
55660 },
55661/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
55662 {
55663 { 0, 0, 0, 0 },
55664 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55665 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1958e00 }
55666 },
55667/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
55668 {
55669 { 0, 0, 0, 0 },
55670 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55671 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ce00 }
55672 },
55673/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
55674 {
55675 { 0, 0, 0, 0 },
55676 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
55677 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ce00 }
55678 },
55679/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55680 {
55681 { 0, 0, 0, 0 },
55682 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55683 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1970e00 }
55684 },
55685/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
55686 {
55687 { 0, 0, 0, 0 },
55688 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
55689 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1978e00 }
55690 },
55691/* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
55692 {
55693 { 0, 0, 0, 0 },
55694 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55695 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1980e00 }
55696 },
55697/* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
55698 {
55699 { 0, 0, 0, 0 },
55700 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55701 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1908e00 }
55702 },
55703/* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
55704 {
55705 { 0, 0, 0, 0 },
55706 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55707 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1900e00 }
55708 },
55709/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55710 {
55711 { 0, 0, 0, 0 },
55712 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55713 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1920e00 }
55714 },
55715/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
55716 {
55717 { 0, 0, 0, 0 },
55718 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55719 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1928e00 }
55720 },
55721/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
55722 {
55723 { 0, 0, 0, 0 },
55724 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55725 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ce00 }
55726 },
55727/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55728 {
55729 { 0, 0, 0, 0 },
55730 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55731 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1940e00 }
55732 },
55733/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
55734 {
55735 { 0, 0, 0, 0 },
55736 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55737 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1948e00 }
55738 },
55739/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
55740 {
55741 { 0, 0, 0, 0 },
55742 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55743 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ce00 }
55744 },
55745/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
55746 {
55747 { 0, 0, 0, 0 },
55748 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
55749 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ce00 }
55750 },
55751/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55752 {
55753 { 0, 0, 0, 0 },
55754 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55755 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1960e00 }
55756 },
55757/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
55758 {
55759 { 0, 0, 0, 0 },
55760 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
55761 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1968e00 }
55762 },
55763/* divx.l $Dst32RnPrefixedSI */
55764 {
55765 { 0, 0, 0, 0 },
55766 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
253d272c 55767 & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a92f }
49f58d10
JB		 55768 },
55769/* divx.l $Dst32AnPrefixedSI */
55770 {
55771 { 0, 0, 0, 0 },
55772 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
253d272c 55773 & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a1af }
49f58d10
JB		 55774 },
55775/* divx.l [$Dst32AnPrefixed] */
55776 {
55777 { 0, 0, 0, 0 },
55778 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55779 & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a12f }
49f58d10
JB		 55780 },
55781/* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55782 {
55783 { 0, 0, 0, 0 },
55784 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55785 & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a32f00 }
49f58d10
JB		 55786 },
55787/* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55788 {
55789 { 0, 0, 0, 0 },
55790 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55791 & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a52f00 }
49f58d10
JB		 55792 },
55793/* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55794 {
55795 { 0, 0, 0, 0 },
55796 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55797 & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a72f00 }
49f58d10
JB		 55798 },
55799/* divx.l ${Dsp-24-u8}[sb] */
55800 {
55801 { 0, 0, 0, 0 },
55802 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
253d272c 55803 & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a3af00 }
49f58d10
JB		 55804 },
55805/* divx.l ${Dsp-24-u16}[sb] */
55806 {
55807 { 0, 0, 0, 0 },
55808 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
253d272c 55809 & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a5af00 }
49f58d10
JB		 55810 },
55811/* divx.l ${Dsp-24-s8}[fb] */
55812 {
55813 { 0, 0, 0, 0 },
55814 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
253d272c 55815 & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3ef00 }
49f58d10
JB		 55816 },
55817/* divx.l ${Dsp-24-s16}[fb] */
55818 {
55819 { 0, 0, 0, 0 },
55820 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
253d272c 55821 & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5ef00 }
49f58d10
JB		 55822 },
55823/* divx.l ${Dsp-24-u16} */
55824 {
55825 { 0, 0, 0, 0 },
55826 { { MNEM, ' ', OP (DSP_24_U16), 0 } },
253d272c 55827 & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7ef00 }
49f58d10
JB		 55828 },
55829/* divx.l ${Dsp-24-u24} */
55830 {
55831 { 0, 0, 0, 0 },
55832 { { MNEM, ' ', OP (DSP_24_U24), 0 } },
253d272c 55833 & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a7af00 }
49f58d10
JB		 55834 },
55835/* divu.l $Dst32RnPrefixedSI */
55836 {
55837 { 0, 0, 0, 0 },
55838 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
253d272c 55839 & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a90f }
49f58d10
JB		 55840 },
55841/* divu.l $Dst32AnPrefixedSI */
55842 {
55843 { 0, 0, 0, 0 },
55844 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
253d272c 55845 & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a18f }
49f58d10
JB		 55846 },
55847/* divu.l [$Dst32AnPrefixed] */
55848 {
55849 { 0, 0, 0, 0 },
55850 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55851 & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a10f }
49f58d10
JB		 55852 },
55853/* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55854 {
55855 { 0, 0, 0, 0 },
55856 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55857 & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a30f00 }
49f58d10
JB		 55858 },
55859/* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55860 {
55861 { 0, 0, 0, 0 },
55862 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55863 & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a50f00 }
49f58d10
JB		 55864 },
55865/* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55866 {
55867 { 0, 0, 0, 0 },
55868 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55869 & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a70f00 }
49f58d10
JB		 55870 },
55871/* divu.l ${Dsp-24-u8}[sb] */
55872 {
55873 { 0, 0, 0, 0 },
55874 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
253d272c 55875 & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a38f00 }
49f58d10
JB		 55876 },
55877/* divu.l ${Dsp-24-u16}[sb] */
55878 {
55879 { 0, 0, 0, 0 },
55880 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
253d272c 55881 & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a58f00 }
49f58d10
JB		 55882 },
55883/* divu.l ${Dsp-24-s8}[fb] */
55884 {
55885 { 0, 0, 0, 0 },
55886 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
253d272c 55887 & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3cf00 }
49f58d10
JB		 55888 },
55889/* divu.l ${Dsp-24-s16}[fb] */
55890 {
55891 { 0, 0, 0, 0 },
55892 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
253d272c 55893 & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5cf00 }
49f58d10
JB		 55894 },
55895/* divu.l ${Dsp-24-u16} */
55896 {
55897 { 0, 0, 0, 0 },
55898 { { MNEM, ' ', OP (DSP_24_U16), 0 } },
253d272c 55899 & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7cf00 }
49f58d10
JB		 55900 },
55901/* divu.l ${Dsp-24-u24} */
55902 {
55903 { 0, 0, 0, 0 },
55904 { { MNEM, ' ', OP (DSP_24_U24), 0 } },
253d272c 55905 & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a78f00 }
49f58d10
JB		 55906 },
55907/* div.l $Dst32RnPrefixedSI */
55908 {
55909 { 0, 0, 0, 0 },
55910 { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
253d272c 55911 & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a91f }
49f58d10
JB		 55912 },
55913/* div.l $Dst32AnPrefixedSI */
55914 {
55915 { 0, 0, 0, 0 },
55916 { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
253d272c 55917 & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a19f }
49f58d10
JB		 55918 },
55919/* div.l [$Dst32AnPrefixed] */
55920 {
55921 { 0, 0, 0, 0 },
55922 { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55923 & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a11f }
49f58d10
JB		 55924 },
55925/* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55926 {
55927 { 0, 0, 0, 0 },
55928 { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55929 & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a31f00 }
49f58d10
JB		 55930 },
55931/* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55932 {
55933 { 0, 0, 0, 0 },
55934 { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55935 & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a51f00 }
49f58d10
JB		 55936 },
55937/* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55938 {
55939 { 0, 0, 0, 0 },
55940 { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
253d272c 55941 & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a71f00 }
49f58d10
JB		 55942 },
55943/* div.l ${Dsp-24-u8}[sb] */
55944 {
55945 { 0, 0, 0, 0 },
55946 { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
253d272c 55947 & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a39f00 }
49f58d10
JB		 55948 },
55949/* div.l ${Dsp-24-u16}[sb] */
55950 {
55951 { 0, 0, 0, 0 },
55952 { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
253d272c 55953 & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a59f00 }
49f58d10
JB		 55954 },
55955/* div.l ${Dsp-24-s8}[fb] */
55956 {
55957 { 0, 0, 0, 0 },
55958 { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
253d272c 55959 & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3df00 }
49f58d10
JB		 55960 },
55961/* div.l ${Dsp-24-s16}[fb] */
55962 {
55963 { 0, 0, 0, 0 },
55964 { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
253d272c 55965 & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5df00 }
49f58d10
JB		 55966 },
55967/* div.l ${Dsp-24-u16} */
55968 {
55969 { 0, 0, 0, 0 },
55970 { { MNEM, ' ', OP (DSP_24_U16), 0 } },
253d272c 55971 & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7df00 }
49f58d10
JB		 55972 },
55973/* div.l ${Dsp-24-u24} */
55974 {
55975 { 0, 0, 0, 0 },
55976 { { MNEM, ' ', OP (DSP_24_U24), 0 } },
253d272c 55977 & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a79f00 }
49f58d10
JB		 55978 },
55979/* divx.w $Dst32RnUnprefixedHI */
55980 {
55981 { 0, 0, 0, 0 },
55982 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
55983 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x991e }
55984 },
55985/* divx.w $Dst32AnUnprefixedHI */
55986 {
55987 { 0, 0, 0, 0 },
55988 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
55989 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x919e }
55990 },
55991/* divx.w [$Dst32AnUnprefixed] */
55992 {
55993 { 0, 0, 0, 0 },
55994 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55995 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x911e }
55996 },
55997/* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
55998 {
55999 { 0, 0, 0, 0 },
56000 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56001 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931e00 }
56002 },
56003/* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56004 {
56005 { 0, 0, 0, 0 },
56006 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56007 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x951e0000 }
56008 },
56009/* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56010 {
56011 { 0, 0, 0, 0 },
56012 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56013 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x971e0000 }
56014 },
56015/* divx.w ${Dsp-16-u8}[sb] */
56016 {
56017 { 0, 0, 0, 0 },
56018 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56019 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939e00 }
56020 },
56021/* divx.w ${Dsp-16-u16}[sb] */
56022 {
56023 { 0, 0, 0, 0 },
56024 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56025 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959e0000 }
56026 },
56027/* divx.w ${Dsp-16-s8}[fb] */
56028 {
56029 { 0, 0, 0, 0 },
56030 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56031 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93de00 }
56032 },
56033/* divx.w ${Dsp-16-s16}[fb] */
56034 {
56035 { 0, 0, 0, 0 },
56036 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56037 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95de0000 }
56038 },
56039/* divx.w ${Dsp-16-u16} */
56040 {
56041 { 0, 0, 0, 0 },
56042 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56043 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97de0000 }
56044 },
56045/* divx.w ${Dsp-16-u24} */
56046 {
56047 { 0, 0, 0, 0 },
56048 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56049 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x979e0000 }
56050 },
56051/* divx.b $Dst32RnUnprefixedQI */
56052 {
56053 { 0, 0, 0, 0 },
56054 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56055 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x981e }
56056 },
56057/* divx.b $Dst32AnUnprefixedQI */
56058 {
56059 { 0, 0, 0, 0 },
56060 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56061 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x909e }
56062 },
56063/* divx.b [$Dst32AnUnprefixed] */
56064 {
56065 { 0, 0, 0, 0 },
56066 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56067 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x901e }
56068 },
56069/* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56070 {
56071 { 0, 0, 0, 0 },
56072 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56073 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x921e00 }
56074 },
56075/* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56076 {
56077 { 0, 0, 0, 0 },
56078 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56079 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x941e0000 }
56080 },
56081/* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56082 {
56083 { 0, 0, 0, 0 },
56084 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56085 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x961e0000 }
56086 },
56087/* divx.b ${Dsp-16-u8}[sb] */
56088 {
56089 { 0, 0, 0, 0 },
56090 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56091 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929e00 }
56092 },
56093/* divx.b ${Dsp-16-u16}[sb] */
56094 {
56095 { 0, 0, 0, 0 },
56096 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56097 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949e0000 }
56098 },
56099/* divx.b ${Dsp-16-s8}[fb] */
56100 {
56101 { 0, 0, 0, 0 },
56102 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56103 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92de00 }
56104 },
56105/* divx.b ${Dsp-16-s16}[fb] */
56106 {
56107 { 0, 0, 0, 0 },
56108 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56109 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94de0000 }
56110 },
56111/* divx.b ${Dsp-16-u16} */
56112 {
56113 { 0, 0, 0, 0 },
56114 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56115 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96de0000 }
56116 },
56117/* divx.b ${Dsp-16-u24} */
56118 {
56119 { 0, 0, 0, 0 },
56120 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56121 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x969e0000 }
56122 },
56123/* divx.w $Dst16RnHI */
56124 {
56125 { 0, 0, 0, 0 },
56126 { { MNEM, ' ', OP (DST16RNHI), 0 } },
56127 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7790 }
56128 },
56129/* divx.w $Dst16AnHI */
56130 {
56131 { 0, 0, 0, 0 },
56132 { { MNEM, ' ', OP (DST16ANHI), 0 } },
56133 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7794 }
56134 },
56135/* divx.w [$Dst16An] */
56136 {
56137 { 0, 0, 0, 0 },
56138 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56139 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7796 }
56140 },
56141/* divx.w ${Dsp-16-u8}[$Dst16An] */
56142 {
56143 { 0, 0, 0, 0 },
56144 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56145 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x779800 }
56146 },
56147/* divx.w ${Dsp-16-u16}[$Dst16An] */
56148 {
56149 { 0, 0, 0, 0 },
56150 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56151 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x779c0000 }
56152 },
56153/* divx.w ${Dsp-16-u8}[sb] */
56154 {
56155 { 0, 0, 0, 0 },
56156 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56157 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x779a00 }
56158 },
56159/* divx.w ${Dsp-16-u16}[sb] */
56160 {
56161 { 0, 0, 0, 0 },
56162 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56163 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x779e0000 }
56164 },
56165/* divx.w ${Dsp-16-s8}[fb] */
56166 {
56167 { 0, 0, 0, 0 },
56168 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56169 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x779b00 }
56170 },
56171/* divx.w ${Dsp-16-u16} */
56172 {
56173 { 0, 0, 0, 0 },
56174 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56175 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x779f0000 }
56176 },
56177/* divx.b $Dst16RnQI */
56178 {
56179 { 0, 0, 0, 0 },
56180 { { MNEM, ' ', OP (DST16RNQI), 0 } },
56181 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7690 }
56182 },
56183/* divx.b $Dst16AnQI */
56184 {
56185 { 0, 0, 0, 0 },
56186 { { MNEM, ' ', OP (DST16ANQI), 0 } },
56187 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7694 }
56188 },
56189/* divx.b [$Dst16An] */
56190 {
56191 { 0, 0, 0, 0 },
56192 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56193 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7696 }
56194 },
56195/* divx.b ${Dsp-16-u8}[$Dst16An] */
56196 {
56197 { 0, 0, 0, 0 },
56198 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56199 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x769800 }
56200 },
56201/* divx.b ${Dsp-16-u16}[$Dst16An] */
56202 {
56203 { 0, 0, 0, 0 },
56204 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56205 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x769c0000 }
56206 },
56207/* divx.b ${Dsp-16-u8}[sb] */
56208 {
56209 { 0, 0, 0, 0 },
56210 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56211 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x769a00 }
56212 },
56213/* divx.b ${Dsp-16-u16}[sb] */
56214 {
56215 { 0, 0, 0, 0 },
56216 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56217 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x769e0000 }
56218 },
56219/* divx.b ${Dsp-16-s8}[fb] */
56220 {
56221 { 0, 0, 0, 0 },
56222 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56223 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x769b00 }
56224 },
56225/* divx.b ${Dsp-16-u16} */
56226 {
56227 { 0, 0, 0, 0 },
56228 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56229 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x769f0000 }
56230 },
56231/* divu.w $Dst32RnUnprefixedHI */
56232 {
56233 { 0, 0, 0, 0 },
56234 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56235 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x890e }
56236 },
56237/* divu.w $Dst32AnUnprefixedHI */
56238 {
56239 { 0, 0, 0, 0 },
56240 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56241 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x818e }
56242 },
56243/* divu.w [$Dst32AnUnprefixed] */
56244 {
56245 { 0, 0, 0, 0 },
56246 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56247 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x810e }
56248 },
56249/* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56250 {
56251 { 0, 0, 0, 0 },
56252 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56253 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x830e00 }
56254 },
56255/* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56256 {
56257 { 0, 0, 0, 0 },
56258 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56259 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x850e0000 }
56260 },
56261/* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56262 {
56263 { 0, 0, 0, 0 },
56264 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56265 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x870e0000 }
56266 },
56267/* divu.w ${Dsp-16-u8}[sb] */
56268 {
56269 { 0, 0, 0, 0 },
56270 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56271 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838e00 }
56272 },
56273/* divu.w ${Dsp-16-u16}[sb] */
56274 {
56275 { 0, 0, 0, 0 },
56276 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56277 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858e0000 }
56278 },
56279/* divu.w ${Dsp-16-s8}[fb] */
56280 {
56281 { 0, 0, 0, 0 },
56282 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56283 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ce00 }
56284 },
56285/* divu.w ${Dsp-16-s16}[fb] */
56286 {
56287 { 0, 0, 0, 0 },
56288 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56289 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ce0000 }
56290 },
56291/* divu.w ${Dsp-16-u16} */
56292 {
56293 { 0, 0, 0, 0 },
56294 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56295 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87ce0000 }
56296 },
56297/* divu.w ${Dsp-16-u24} */
56298 {
56299 { 0, 0, 0, 0 },
56300 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56301 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x878e0000 }
56302 },
56303/* divu.b $Dst32RnUnprefixedQI */
56304 {
56305 { 0, 0, 0, 0 },
56306 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56307 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x880e }
56308 },
56309/* divu.b $Dst32AnUnprefixedQI */
56310 {
56311 { 0, 0, 0, 0 },
56312 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56313 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x808e }
56314 },
56315/* divu.b [$Dst32AnUnprefixed] */
56316 {
56317 { 0, 0, 0, 0 },
56318 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56319 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x800e }
56320 },
56321/* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56322 {
56323 { 0, 0, 0, 0 },
56324 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56325 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820e00 }
56326 },
56327/* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56328 {
56329 { 0, 0, 0, 0 },
56330 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56331 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x840e0000 }
56332 },
56333/* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56334 {
56335 { 0, 0, 0, 0 },
56336 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56337 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x860e0000 }
56338 },
56339/* divu.b ${Dsp-16-u8}[sb] */
56340 {
56341 { 0, 0, 0, 0 },
56342 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56343 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828e00 }
56344 },
56345/* divu.b ${Dsp-16-u16}[sb] */
56346 {
56347 { 0, 0, 0, 0 },
56348 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56349 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848e0000 }
56350 },
56351/* divu.b ${Dsp-16-s8}[fb] */
56352 {
56353 { 0, 0, 0, 0 },
56354 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56355 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ce00 }
56356 },
56357/* divu.b ${Dsp-16-s16}[fb] */
56358 {
56359 { 0, 0, 0, 0 },
56360 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56361 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ce0000 }
56362 },
56363/* divu.b ${Dsp-16-u16} */
56364 {
56365 { 0, 0, 0, 0 },
56366 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56367 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86ce0000 }
56368 },
56369/* divu.b ${Dsp-16-u24} */
56370 {
56371 { 0, 0, 0, 0 },
56372 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56373 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x868e0000 }
56374 },
56375/* divu.w $Dst16RnHI */
56376 {
56377 { 0, 0, 0, 0 },
56378 { { MNEM, ' ', OP (DST16RNHI), 0 } },
56379 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77c0 }
56380 },
56381/* divu.w $Dst16AnHI */
56382 {
56383 { 0, 0, 0, 0 },
56384 { { MNEM, ' ', OP (DST16ANHI), 0 } },
56385 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77c4 }
56386 },
56387/* divu.w [$Dst16An] */
56388 {
56389 { 0, 0, 0, 0 },
56390 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56391 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77c6 }
56392 },
56393/* divu.w ${Dsp-16-u8}[$Dst16An] */
56394 {
56395 { 0, 0, 0, 0 },
56396 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56397 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77c800 }
56398 },
56399/* divu.w ${Dsp-16-u16}[$Dst16An] */
56400 {
56401 { 0, 0, 0, 0 },
56402 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56403 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77cc0000 }
56404 },
56405/* divu.w ${Dsp-16-u8}[sb] */
56406 {
56407 { 0, 0, 0, 0 },
56408 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56409 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ca00 }
56410 },
56411/* divu.w ${Dsp-16-u16}[sb] */
56412 {
56413 { 0, 0, 0, 0 },
56414 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56415 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ce0000 }
56416 },
56417/* divu.w ${Dsp-16-s8}[fb] */
56418 {
56419 { 0, 0, 0, 0 },
56420 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56421 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77cb00 }
56422 },
56423/* divu.w ${Dsp-16-u16} */
56424 {
56425 { 0, 0, 0, 0 },
56426 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56427 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77cf0000 }
56428 },
56429/* divu.b $Dst16RnQI */
56430 {
56431 { 0, 0, 0, 0 },
56432 { { MNEM, ' ', OP (DST16RNQI), 0 } },
56433 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76c0 }
56434 },
56435/* divu.b $Dst16AnQI */
56436 {
56437 { 0, 0, 0, 0 },
56438 { { MNEM, ' ', OP (DST16ANQI), 0 } },
56439 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76c4 }
56440 },
56441/* divu.b [$Dst16An] */
56442 {
56443 { 0, 0, 0, 0 },
56444 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56445 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76c6 }
56446 },
56447/* divu.b ${Dsp-16-u8}[$Dst16An] */
56448 {
56449 { 0, 0, 0, 0 },
56450 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56451 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76c800 }
56452 },
56453/* divu.b ${Dsp-16-u16}[$Dst16An] */
56454 {
56455 { 0, 0, 0, 0 },
56456 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56457 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76cc0000 }
56458 },
56459/* divu.b ${Dsp-16-u8}[sb] */
56460 {
56461 { 0, 0, 0, 0 },
56462 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56463 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ca00 }
56464 },
56465/* divu.b ${Dsp-16-u16}[sb] */
56466 {
56467 { 0, 0, 0, 0 },
56468 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56469 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ce0000 }
56470 },
56471/* divu.b ${Dsp-16-s8}[fb] */
56472 {
56473 { 0, 0, 0, 0 },
56474 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56475 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76cb00 }
56476 },
56477/* divu.b ${Dsp-16-u16} */
56478 {
56479 { 0, 0, 0, 0 },
56480 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56481 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76cf0000 }
56482 },
56483/* div.w $Dst32RnUnprefixedHI */
56484 {
56485 { 0, 0, 0, 0 },
56486 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56487 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x891e }
56488 },
56489/* div.w $Dst32AnUnprefixedHI */
56490 {
56491 { 0, 0, 0, 0 },
56492 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56493 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x819e }
56494 },
56495/* div.w [$Dst32AnUnprefixed] */
56496 {
56497 { 0, 0, 0, 0 },
56498 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56499 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x811e }
56500 },
56501/* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56502 {
56503 { 0, 0, 0, 0 },
56504 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56505 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831e00 }
56506 },
56507/* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56508 {
56509 { 0, 0, 0, 0 },
56510 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56511 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x851e0000 }
56512 },
56513/* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56514 {
56515 { 0, 0, 0, 0 },
56516 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56517 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x871e0000 }
56518 },
56519/* div.w ${Dsp-16-u8}[sb] */
56520 {
56521 { 0, 0, 0, 0 },
56522 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56523 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839e00 }
56524 },
56525/* div.w ${Dsp-16-u16}[sb] */
56526 {
56527 { 0, 0, 0, 0 },
56528 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56529 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859e0000 }
56530 },
56531/* div.w ${Dsp-16-s8}[fb] */
56532 {
56533 { 0, 0, 0, 0 },
56534 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56535 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83de00 }
56536 },
56537/* div.w ${Dsp-16-s16}[fb] */
56538 {
56539 { 0, 0, 0, 0 },
56540 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56541 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85de0000 }
56542 },
56543/* div.w ${Dsp-16-u16} */
56544 {
56545 { 0, 0, 0, 0 },
56546 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56547 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87de0000 }
56548 },
56549/* div.w ${Dsp-16-u24} */
56550 {
56551 { 0, 0, 0, 0 },
56552 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56553 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x879e0000 }
56554 },
56555/* div.b $Dst32RnUnprefixedQI */
56556 {
56557 { 0, 0, 0, 0 },
56558 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56559 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x881e }
56560 },
56561/* div.b $Dst32AnUnprefixedQI */
56562 {
56563 { 0, 0, 0, 0 },
56564 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56565 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x809e }
56566 },
56567/* div.b [$Dst32AnUnprefixed] */
56568 {
56569 { 0, 0, 0, 0 },
56570 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56571 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x801e }
56572 },
56573/* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56574 {
56575 { 0, 0, 0, 0 },
56576 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56577 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x821e00 }
56578 },
56579/* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56580 {
56581 { 0, 0, 0, 0 },
56582 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56583 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x841e0000 }
56584 },
56585/* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56586 {
56587 { 0, 0, 0, 0 },
56588 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56589 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x861e0000 }
56590 },
56591/* div.b ${Dsp-16-u8}[sb] */
56592 {
56593 { 0, 0, 0, 0 },
56594 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56595 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829e00 }
56596 },
56597/* div.b ${Dsp-16-u16}[sb] */
56598 {
56599 { 0, 0, 0, 0 },
56600 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56601 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849e0000 }
56602 },
56603/* div.b ${Dsp-16-s8}[fb] */
56604 {
56605 { 0, 0, 0, 0 },
56606 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56607 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82de00 }
56608 },
56609/* div.b ${Dsp-16-s16}[fb] */
56610 {
56611 { 0, 0, 0, 0 },
56612 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56613 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84de0000 }
56614 },
56615/* div.b ${Dsp-16-u16} */
56616 {
56617 { 0, 0, 0, 0 },
56618 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56619 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86de0000 }
56620 },
56621/* div.b ${Dsp-16-u24} */
56622 {
56623 { 0, 0, 0, 0 },
56624 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56625 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x869e0000 }
56626 },
56627/* div.w $Dst16RnHI */
56628 {
56629 { 0, 0, 0, 0 },
56630 { { MNEM, ' ', OP (DST16RNHI), 0 } },
56631 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77d0 }
56632 },
56633/* div.w $Dst16AnHI */
56634 {
56635 { 0, 0, 0, 0 },
56636 { { MNEM, ' ', OP (DST16ANHI), 0 } },
56637 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77d4 }
56638 },
56639/* div.w [$Dst16An] */
56640 {
56641 { 0, 0, 0, 0 },
56642 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56643 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77d6 }
56644 },
56645/* div.w ${Dsp-16-u8}[$Dst16An] */
56646 {
56647 { 0, 0, 0, 0 },
56648 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56649 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77d800 }
56650 },
56651/* div.w ${Dsp-16-u16}[$Dst16An] */
56652 {
56653 { 0, 0, 0, 0 },
56654 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56655 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77dc0000 }
56656 },
56657/* div.w ${Dsp-16-u8}[sb] */
56658 {
56659 { 0, 0, 0, 0 },
56660 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56661 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77da00 }
56662 },
56663/* div.w ${Dsp-16-u16}[sb] */
56664 {
56665 { 0, 0, 0, 0 },
56666 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56667 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77de0000 }
56668 },
56669/* div.w ${Dsp-16-s8}[fb] */
56670 {
56671 { 0, 0, 0, 0 },
56672 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56673 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77db00 }
56674 },
56675/* div.w ${Dsp-16-u16} */
56676 {
56677 { 0, 0, 0, 0 },
56678 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56679 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77df0000 }
56680 },
56681/* div.b $Dst16RnQI */
56682 {
56683 { 0, 0, 0, 0 },
56684 { { MNEM, ' ', OP (DST16RNQI), 0 } },
56685 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76d0 }
56686 },
56687/* div.b $Dst16AnQI */
56688 {
56689 { 0, 0, 0, 0 },
56690 { { MNEM, ' ', OP (DST16ANQI), 0 } },
56691 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76d4 }
56692 },
56693/* div.b [$Dst16An] */
56694 {
56695 { 0, 0, 0, 0 },
56696 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56697 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76d6 }
56698 },
56699/* div.b ${Dsp-16-u8}[$Dst16An] */
56700 {
56701 { 0, 0, 0, 0 },
56702 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56703 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76d800 }
56704 },
56705/* div.b ${Dsp-16-u16}[$Dst16An] */
56706 {
56707 { 0, 0, 0, 0 },
56708 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56709 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76dc0000 }
56710 },
56711/* div.b ${Dsp-16-u8}[sb] */
56712 {
56713 { 0, 0, 0, 0 },
56714 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56715 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76da00 }
56716 },
56717/* div.b ${Dsp-16-u16}[sb] */
56718 {
56719 { 0, 0, 0, 0 },
56720 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56721 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76de0000 }
56722 },
56723/* div.b ${Dsp-16-s8}[fb] */
56724 {
56725 { 0, 0, 0, 0 },
56726 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56727 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76db00 }
56728 },
56729/* div.b ${Dsp-16-u16} */
56730 {
56731 { 0, 0, 0, 0 },
56732 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56733 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76df0000 }
56734 },
56735/* dec.w $Dst32RnUnprefixedHI */
56736 {
56737 { 0, 0, 0, 0 },
56738 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56739 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb90e }
56740 },
56741/* dec.w $Dst32AnUnprefixedHI */
56742 {
56743 { 0, 0, 0, 0 },
56744 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56745 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18e }
56746 },
56747/* dec.w [$Dst32AnUnprefixed] */
56748 {
56749 { 0, 0, 0, 0 },
56750 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56751 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb10e }
56752 },
56753/* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56754 {
56755 { 0, 0, 0, 0 },
56756 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56757 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30e00 }
56758 },
56759/* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56760 {
56761 { 0, 0, 0, 0 },
56762 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56763 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50e0000 }
56764 },
56765/* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56766 {
56767 { 0, 0, 0, 0 },
56768 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56769 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70e0000 }
56770 },
56771/* dec.w ${Dsp-16-u8}[sb] */
56772 {
56773 { 0, 0, 0, 0 },
56774 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56775 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38e00 }
56776 },
56777/* dec.w ${Dsp-16-u16}[sb] */
56778 {
56779 { 0, 0, 0, 0 },
56780 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56781 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58e0000 }
56782 },
56783/* dec.w ${Dsp-16-s8}[fb] */
56784 {
56785 { 0, 0, 0, 0 },
56786 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56787 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ce00 }
56788 },
56789/* dec.w ${Dsp-16-s16}[fb] */
56790 {
56791 { 0, 0, 0, 0 },
56792 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56793 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ce0000 }
56794 },
56795/* dec.w ${Dsp-16-u16} */
56796 {
56797 { 0, 0, 0, 0 },
56798 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56799 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ce0000 }
56800 },
56801/* dec.w ${Dsp-16-u24} */
56802 {
56803 { 0, 0, 0, 0 },
56804 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56805 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb78e0000 }
56806 },
56807/* dec.b $Dst32RnUnprefixedQI */
56808 {
56809 { 0, 0, 0, 0 },
56810 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56811 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb80e }
56812 },
56813/* dec.b $Dst32AnUnprefixedQI */
56814 {
56815 { 0, 0, 0, 0 },
56816 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56817 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb08e }
56818 },
56819/* dec.b [$Dst32AnUnprefixed] */
56820 {
56821 { 0, 0, 0, 0 },
56822 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56823 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb00e }
56824 },
56825/* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56826 {
56827 { 0, 0, 0, 0 },
56828 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56829 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20e00 }
56830 },
56831/* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56832 {
56833 { 0, 0, 0, 0 },
56834 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56835 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40e0000 }
56836 },
56837/* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56838 {
56839 { 0, 0, 0, 0 },
56840 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56841 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60e0000 }
56842 },
56843/* dec.b ${Dsp-16-u8}[sb] */
56844 {
56845 { 0, 0, 0, 0 },
56846 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56847 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28e00 }
56848 },
56849/* dec.b ${Dsp-16-u16}[sb] */
56850 {
56851 { 0, 0, 0, 0 },
56852 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56853 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48e0000 }
56854 },
56855/* dec.b ${Dsp-16-s8}[fb] */
56856 {
56857 { 0, 0, 0, 0 },
56858 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56859 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ce00 }
56860 },
56861/* dec.b ${Dsp-16-s16}[fb] */
56862 {
56863 { 0, 0, 0, 0 },
56864 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56865 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ce0000 }
56866 },
56867/* dec.b ${Dsp-16-u16} */
56868 {
56869 { 0, 0, 0, 0 },
56870 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56871 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ce0000 }
56872 },
56873/* dec.b ${Dsp-16-u24} */
56874 {
56875 { 0, 0, 0, 0 },
56876 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56877 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb68e0000 }
56878 },
56879/* dec.b r0l */
56880 {
56881 { 0, 0, 0, 0 },
56882 { { MNEM, ' ', 'r', '0', 'l', 0 } },
c6552317 56883 & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xac }
49f58d10
JB		 56884 },
56885/* dec.b r0h */
56886 {
56887 { 0, 0, 0, 0 },
56888 { { MNEM, ' ', 'r', '0', 'h', 0 } },
c6552317 56889 & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xab }
49f58d10
JB		 56890 },
56891/* dec.b ${Dsp-8-u8}[sb] */
56892 {
56893 { 0, 0, 0, 0 },
56894 { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
c6552317 56895 & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xad00 }
49f58d10
JB		 56896 },
56897/* dec.b ${Dsp-8-s8}[fb] */
56898 {
56899 { 0, 0, 0, 0 },
56900 { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
c6552317 56901 & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xae00 }
49f58d10
JB		 56902 },
56903/* dec.b ${Dsp-8-u16} */
56904 {
56905 { 0, 0, 0, 0 },
56906 { { MNEM, ' ', OP (DSP_8_U16), 0 } },
c6552317 56907 & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xaf0000 }
49f58d10
JB		 56908 },
56909/* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
56910 {
56911 { 0, 0, 0, 0 },
56912 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56913 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa81100 }
56914 },
56915/* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
56916 {
56917 { 0, 0, 0, 0 },
56918 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56919 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa09100 }
56920 },
56921/* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
56922 {
56923 { 0, 0, 0, 0 },
56924 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56925 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa01100 }
56926 },
56927/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
56928 {
56929 { 0, 0, 0, 0 },
56930 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56931 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2110000 }
56932 },
56933/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
56934 {
56935 { 0, 0, 0, 0 },
56936 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56937 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2910000 }
56938 },
56939/* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
56940 {
56941 { 0, 0, 0, 0 },
56942 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56943 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2d10000 }
56944 },
56945/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
56946 {
56947 { 0, 0, 0, 0 },
56948 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56949 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4110000 }
56950 },
56951/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
56952 {
56953 { 0, 0, 0, 0 },
56954 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56955 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4910000 }
56956 },
56957/* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
56958 {
56959 { 0, 0, 0, 0 },
56960 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56961 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4d10000 }
56962 },
56963/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
56964 {
56965 { 0, 0, 0, 0 },
56966 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
56967 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6d10000 }
56968 },
56969/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
56970 {
56971 { 0, 0, 0, 0 },
56972 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56973 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6110000 }
56974 },
56975/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
56976 {
56977 { 0, 0, 0, 0 },
56978 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
56979 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6910000 }
56980 },
56981/* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
56982 {
56983 { 0, 0, 0, 0 },
56984 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0HI_S), 0 } },
56985 & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI, { 0x6100 }
56986 },
56987/* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
56988 {
56989 { 0, 0, 0, 0 },
56990 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0HI_S), 0 } },
56991 & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI, { 0x7100 }
56992 },
56993/* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
56994 {
56995 { 0, 0, 0, 0 },
56996 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0HI_S), 0 } },
56997 & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI, { 0x510000 }
56998 },
56999/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
57000 {
57001 { 0, 0, 0, 0 },
57002 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0QI_S), 0 } },
57003 & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI, { 0x6000 }
57004 },
57005/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
57006 {
57007 { 0, 0, 0, 0 },
57008 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0QI_S), 0 } },
57009 & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI, { 0x7000 }
57010 },
57011/* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
57012 {
57013 { 0, 0, 0, 0 },
57014 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0QI_S), 0 } },
57015 & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI, { 0x500000 }
57016 },
57017/* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
57018 {
57019 { 0, 0, 0, 0 },
57020 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
57021 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x67000000 }
57022 },
57023/* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
57024 {
57025 { 0, 0, 0, 0 },
57026 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
57027 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x77000000 }
57028 },
57029/* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
57030 {
57031 { 0, 0, 0, 0 },
57032 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
57033 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x57000000 }
57034 },
57035/* cmp.w${S} #${Imm-8-HI},r0 */
57036 {
57037 { 0, 0, 0, 0 },
57038 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
57039 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x470000 }
57040 },
57041/* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
57042 {
57043 { 0, 0, 0, 0 },
57044 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
57045 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x660000 }
57046 },
57047/* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
57048 {
57049 { 0, 0, 0, 0 },
57050 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
57051 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x760000 }
57052 },
57053/* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
57054 {
57055 { 0, 0, 0, 0 },
57056 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
57057 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x56000000 }
57058 },
57059/* cmp.b${S} #${Imm-8-QI},r0l */
57060 {
57061 { 0, 0, 0, 0 },
57062 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
57063 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4600 }
57064 },
57065/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57066 {
57067 { 0, 0, 0, 0 },
57068 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57069 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990100 }
57070 },
57071/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
57072 {
57073 { 0, 0, 0, 0 },
57074 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57075 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992100 }
57076 },
57077/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
57078 {
57079 { 0, 0, 0, 0 },
57080 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57081 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993100 }
57082 },
57083/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57084 {
57085 { 0, 0, 0, 0 },
57086 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57087 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918100 }
57088 },
57089/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
57090 {
57091 { 0, 0, 0, 0 },
57092 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57093 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a100 }
57094 },
57095/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
57096 {
57097 { 0, 0, 0, 0 },
57098 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57099 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b100 }
57100 },
57101/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57102 {
57103 { 0, 0, 0, 0 },
57104 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57105 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910100 }
57106 },
57107/* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57108 {
57109 { 0, 0, 0, 0 },
57110 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57111 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912100 }
57112 },
57113/* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57114 {
57115 { 0, 0, 0, 0 },
57116 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57117 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913100 }
57118 },
57119/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57120 {
57121 { 0, 0, 0, 0 },
57122 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57123 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93010000 }
57124 },
57125/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57126 {
57127 { 0, 0, 0, 0 },
57128 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57129 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93210000 }
57130 },
57131/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57132 {
57133 { 0, 0, 0, 0 },
57134 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57135 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93310000 }
57136 },
57137/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57138 {
57139 { 0, 0, 0, 0 },
57140 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57141 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95010000 }
57142 },
57143/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57144 {
57145 { 0, 0, 0, 0 },
57146 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57147 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95210000 }
57148 },
57149/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57150 {
57151 { 0, 0, 0, 0 },
57152 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57153 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95310000 }
57154 },
57155/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57156 {
57157 { 0, 0, 0, 0 },
57158 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57159 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97010000 }
57160 },
57161/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57162 {
57163 { 0, 0, 0, 0 },
57164 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57165 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97210000 }
57166 },
57167/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57168 {
57169 { 0, 0, 0, 0 },
57170 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57171 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97310000 }
57172 },
57173/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
57174 {
57175 { 0, 0, 0, 0 },
57176 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57177 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93810000 }
57178 },
57179/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57180 {
57181 { 0, 0, 0, 0 },
57182 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57183 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a10000 }
57184 },
57185/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57186 {
57187 { 0, 0, 0, 0 },
57188 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57189 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b10000 }
57190 },
57191/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
57192 {
57193 { 0, 0, 0, 0 },
57194 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57195 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95810000 }
57196 },
57197/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57198 {
57199 { 0, 0, 0, 0 },
57200 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57201 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a10000 }
57202 },
57203/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57204 {
57205 { 0, 0, 0, 0 },
57206 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57207 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b10000 }
57208 },
57209/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
57210 {
57211 { 0, 0, 0, 0 },
57212 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57213 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c10000 }
57214 },
57215/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57216 {
57217 { 0, 0, 0, 0 },
57218 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57219 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e10000 }
57220 },
57221/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57222 {
57223 { 0, 0, 0, 0 },
57224 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57225 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f10000 }
57226 },
57227/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
57228 {
57229 { 0, 0, 0, 0 },
57230 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57231 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c10000 }
57232 },
57233/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
57234 {
57235 { 0, 0, 0, 0 },
57236 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57237 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e10000 }
57238 },
57239/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
57240 {
57241 { 0, 0, 0, 0 },
57242 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57243 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f10000 }
57244 },
57245/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
57246 {
57247 { 0, 0, 0, 0 },
57248 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
57249 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c10000 }
57250 },
57251/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57252 {
57253 { 0, 0, 0, 0 },
57254 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
57255 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e10000 }
57256 },
57257/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57258 {
57259 { 0, 0, 0, 0 },
57260 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
57261 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f10000 }
57262 },
57263/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
57264 {
57265 { 0, 0, 0, 0 },
57266 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
57267 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97810000 }
57268 },
57269/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
57270 {
57271 { 0, 0, 0, 0 },
57272 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
57273 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a10000 }
57274 },
57275/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
57276 {
57277 { 0, 0, 0, 0 },
57278 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
57279 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b10000 }
57280 },
57281/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57282 {
57283 { 0, 0, 0, 0 },
57284 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57285 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9010000 }
57286 },
57287/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
57288 {
57289 { 0, 0, 0, 0 },
57290 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57291 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9210000 }
57292 },
57293/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
57294 {
57295 { 0, 0, 0, 0 },
57296 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57297 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9310000 }
57298 },
57299/* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
57300 {
57301 { 0, 0, 0, 0 },
57302 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57303 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9310000 }
57304 },
57305/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57306 {
57307 { 0, 0, 0, 0 },
57308 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57309 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1810000 }
57310 },
57311/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
57312 {
57313 { 0, 0, 0, 0 },
57314 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57315 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a10000 }
57316 },
57317/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
57318 {
57319 { 0, 0, 0, 0 },
57320 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57321 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b10000 }
57322 },
57323/* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
57324 {
57325 { 0, 0, 0, 0 },
57326 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57327 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b10000 }
57328 },
57329/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57330 {
57331 { 0, 0, 0, 0 },
57332 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57333 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1010000 }
57334 },
57335/* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
57336 {
57337 { 0, 0, 0, 0 },
57338 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57339 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1210000 }
57340 },
57341/* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
57342 {
57343 { 0, 0, 0, 0 },
57344 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57345 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1310000 }
57346 },
57347/* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
57348 {
57349 { 0, 0, 0, 0 },
57350 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57351 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1310000 }
57352 },
57353/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57354 {
57355 { 0, 0, 0, 0 },
57356 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57357 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3010000 }
57358 },
57359/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57360 {
57361 { 0, 0, 0, 0 },
57362 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57363 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3210000 }
57364 },
57365/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57366 {
57367 { 0, 0, 0, 0 },
57368 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57369 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3310000 }
57370 },
57371/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
57372 {
57373 { 0, 0, 0, 0 },
57374 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57375 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3310000 }
57376 },
57377/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57378 {
57379 { 0, 0, 0, 0 },
57380 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57381 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5010000 }
57382 },
57383/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57384 {
57385 { 0, 0, 0, 0 },
57386 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57387 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5210000 }
57388 },
57389/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57390 {
57391 { 0, 0, 0, 0 },
57392 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57393 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5310000 }
57394 },
57395/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
57396 {
57397 { 0, 0, 0, 0 },
57398 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57399 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5310000 }
57400 },
57401/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57402 {
57403 { 0, 0, 0, 0 },
57404 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57405 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7010000 }
57406 },
57407/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57408 {
57409 { 0, 0, 0, 0 },
57410 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57411 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7210000 }
57412 },
57413/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57414 {
57415 { 0, 0, 0, 0 },
57416 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57417 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7310000 }
57418 },
57419/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
57420 {
57421 { 0, 0, 0, 0 },
57422 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57423 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7310000 }
57424 },
57425/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
57426 {
57427 { 0, 0, 0, 0 },
57428 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57429 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3810000 }
57430 },
57431/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57432 {
57433 { 0, 0, 0, 0 },
57434 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57435 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a10000 }
57436 },
57437/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
57438 {
57439 { 0, 0, 0, 0 },
57440 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57441 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b10000 }
57442 },
57443/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57444 {
57445 { 0, 0, 0, 0 },
57446 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57447 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b10000 }
57448 },
57449/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
57450 {
57451 { 0, 0, 0, 0 },
57452 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57453 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5810000 }
57454 },
57455/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57456 {
57457 { 0, 0, 0, 0 },
57458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57459 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a10000 }
57460 },
57461/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
57462 {
57463 { 0, 0, 0, 0 },
57464 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57465 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b10000 }
57466 },
57467/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57468 {
57469 { 0, 0, 0, 0 },
57470 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57471 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b10000 }
57472 },
57473/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
57474 {
57475 { 0, 0, 0, 0 },
57476 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57477 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c10000 }
57478 },
57479/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57480 {
57481 { 0, 0, 0, 0 },
57482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57483 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e10000 }
57484 },
57485/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
57486 {
57487 { 0, 0, 0, 0 },
57488 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57489 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f10000 }
57490 },
57491/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57492 {
57493 { 0, 0, 0, 0 },
57494 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57495 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f10000 }
57496 },
57497/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
57498 {
57499 { 0, 0, 0, 0 },
57500 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57501 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c10000 }
57502 },
57503/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
57504 {
57505 { 0, 0, 0, 0 },
57506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57507 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e10000 }
57508 },
57509/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
57510 {
57511 { 0, 0, 0, 0 },
57512 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57513 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f10000 }
57514 },
57515/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
57516 {
57517 { 0, 0, 0, 0 },
57518 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57519 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f10000 }
57520 },
57521/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
57522 {
57523 { 0, 0, 0, 0 },
57524 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
57525 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c10000 }
57526 },
57527/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57528 {
57529 { 0, 0, 0, 0 },
57530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
57531 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e10000 }
57532 },
57533/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
57534 {
57535 { 0, 0, 0, 0 },
57536 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
57537 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f10000 }
57538 },
57539/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
57540 {
57541 { 0, 0, 0, 0 },
57542 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
57543 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f10000 }
57544 },
57545/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
57546 {
57547 { 0, 0, 0, 0 },
57548 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
57549 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7810000 }
57550 },
57551/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
57552 {
57553 { 0, 0, 0, 0 },
57554 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
57555 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a10000 }
57556 },
57557/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
57558 {
57559 { 0, 0, 0, 0 },
57560 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
57561 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b10000 }
57562 },
57563/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
57564 {
57565 { 0, 0, 0, 0 },
57566 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
57567 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b10000 }
57568 },
57569/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57570 {
57571 { 0, 0, 0, 0 },
57572 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57573 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9010000 }
57574 },
57575/* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
57576 {
57577 { 0, 0, 0, 0 },
57578 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57579 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9210000 }
57580 },
57581/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57582 {
57583 { 0, 0, 0, 0 },
57584 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57585 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1810000 }
57586 },
57587/* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
57588 {
57589 { 0, 0, 0, 0 },
57590 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57591 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a10000 }
57592 },
57593/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57594 {
57595 { 0, 0, 0, 0 },
57596 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57597 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1010000 }
57598 },
57599/* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
57600 {
57601 { 0, 0, 0, 0 },
57602 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57603 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1210000 }
57604 },
57605/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
57606 {
57607 { 0, 0, 0, 0 },
57608 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57609 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3010000 }
57610 },
57611/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
57612 {
57613 { 0, 0, 0, 0 },
57614 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57615 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3210000 }
57616 },
57617/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
57618 {
57619 { 0, 0, 0, 0 },
57620 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57621 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5010000 }
57622 },
57623/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
57624 {
57625 { 0, 0, 0, 0 },
57626 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57627 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5210000 }
57628 },
57629/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
57630 {
57631 { 0, 0, 0, 0 },
57632 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57633 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7010000 }
57634 },
57635/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
57636 {
57637 { 0, 0, 0, 0 },
57638 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57639 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7210000 }
57640 },
57641/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
57642 {
57643 { 0, 0, 0, 0 },
57644 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
57645 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3810000 }
57646 },
57647/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
57648 {
57649 { 0, 0, 0, 0 },
57650 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
57651 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a10000 }
57652 },
57653/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
57654 {
57655 { 0, 0, 0, 0 },
57656 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
57657 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5810000 }
57658 },
57659/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
57660 {
57661 { 0, 0, 0, 0 },
57662 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
57663 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a10000 }
57664 },
57665/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
57666 {
57667 { 0, 0, 0, 0 },
57668 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
57669 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c10000 }
57670 },
57671/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
57672 {
57673 { 0, 0, 0, 0 },
57674 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
57675 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e10000 }
57676 },
57677/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
57678 {
57679 { 0, 0, 0, 0 },
57680 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
57681 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c10000 }
57682 },
57683/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
57684 {
57685 { 0, 0, 0, 0 },
57686 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
57687 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e10000 }
57688 },
57689/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
57690 {
57691 { 0, 0, 0, 0 },
57692 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
57693 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c10000 }
57694 },
57695/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
57696 {
57697 { 0, 0, 0, 0 },
57698 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
57699 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e10000 }
57700 },
57701/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
57702 {
57703 { 0, 0, 0, 0 },
57704 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
57705 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7810000 }
57706 },
57707/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
57708 {
57709 { 0, 0, 0, 0 },
57710 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
57711 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a10000 }
57712 },
57713/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
57714 {
57715 { 0, 0, 0, 0 },
57716 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57717 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc901 }
57718 },
57719/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
57720 {
57721 { 0, 0, 0, 0 },
57722 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57723 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8921 }
57724 },
57725/* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57726 {
57727 { 0, 0, 0, 0 },
57728 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57729 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8901 }
57730 },
57731/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
57732 {
57733 { 0, 0, 0, 0 },
57734 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57735 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc181 }
57736 },
57737/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
57738 {
57739 { 0, 0, 0, 0 },
57740 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57741 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a1 }
57742 },
57743/* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57744 {
57745 { 0, 0, 0, 0 },
57746 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57747 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8181 }
57748 },
57749/* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
57750 {
57751 { 0, 0, 0, 0 },
57752 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57753 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc101 }
57754 },
57755/* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
57756 {
57757 { 0, 0, 0, 0 },
57758 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57759 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8121 }
57760 },
57761/* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57762 {
57763 { 0, 0, 0, 0 },
57764 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57765 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8101 }
57766 },
57767/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
57768 {
57769 { 0, 0, 0, 0 },
57770 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57771 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30100 }
57772 },
57773/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
57774 {
57775 { 0, 0, 0, 0 },
57776 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57777 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832100 }
57778 },
57779/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
57780 {
57781 { 0, 0, 0, 0 },
57782 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57783 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830100 }
57784 },
57785/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
57786 {
57787 { 0, 0, 0, 0 },
57788 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57789 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5010000 }
57790 },
57791/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
57792 {
57793 { 0, 0, 0, 0 },
57794 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57795 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85210000 }
57796 },
57797/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
57798 {
57799 { 0, 0, 0, 0 },
57800 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57801 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85010000 }
57802 },
57803/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
57804 {
57805 { 0, 0, 0, 0 },
57806 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57807 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7010000 }
57808 },
57809/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
57810 {
57811 { 0, 0, 0, 0 },
57812 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57813 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87210000 }
57814 },
57815/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
57816 {
57817 { 0, 0, 0, 0 },
57818 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57819 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87010000 }
57820 },
57821/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
57822 {
57823 { 0, 0, 0, 0 },
57824 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57825 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38100 }
57826 },
57827/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
57828 {
57829 { 0, 0, 0, 0 },
57830 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57831 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a100 }
57832 },
57833/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
57834 {
57835 { 0, 0, 0, 0 },
57836 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57837 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838100 }
57838 },
57839/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
57840 {
57841 { 0, 0, 0, 0 },
57842 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57843 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5810000 }
57844 },
57845/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
57846 {
57847 { 0, 0, 0, 0 },
57848 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57849 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a10000 }
57850 },
57851/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
57852 {
57853 { 0, 0, 0, 0 },
57854 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57855 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85810000 }
57856 },
57857/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
57858 {
57859 { 0, 0, 0, 0 },
57860 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57861 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c100 }
57862 },
57863/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
57864 {
57865 { 0, 0, 0, 0 },
57866 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57867 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e100 }
57868 },
57869/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
57870 {
57871 { 0, 0, 0, 0 },
57872 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57873 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c100 }
57874 },
57875/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
57876 {
57877 { 0, 0, 0, 0 },
57878 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57879 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c10000 }
57880 },
57881/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
57882 {
57883 { 0, 0, 0, 0 },
57884 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57885 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e10000 }
57886 },
57887/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
57888 {
57889 { 0, 0, 0, 0 },
57890 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57891 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c10000 }
57892 },
57893/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
57894 {
57895 { 0, 0, 0, 0 },
57896 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
57897 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c10000 }
57898 },
57899/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
57900 {
57901 { 0, 0, 0, 0 },
57902 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
57903 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e10000 }
57904 },
57905/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
57906 {
57907 { 0, 0, 0, 0 },
57908 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
57909 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c10000 }
57910 },
57911/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
57912 {
57913 { 0, 0, 0, 0 },
57914 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
57915 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7810000 }
57916 },
57917/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
57918 {
57919 { 0, 0, 0, 0 },
57920 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
57921 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a10000 }
57922 },
57923/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
57924 {
57925 { 0, 0, 0, 0 },
57926 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
57927 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87810000 }
57928 },
57929/* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
57930 {
57931 { 0, 0, 0, 0 },
57932 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
5348b81e 57933 & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x38 }
49f58d10
JB		 57934 },
57935/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
57936 {
57937 { 0, 0, 0, 0 },
57938 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 57939 & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x3900 }
49f58d10
JB		 57940 },
57941/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
57942 {
57943 { 0, 0, 0, 0 },
57944 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 57945 & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x3a00 }
49f58d10
JB		 57946 },
57947/* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
57948 {
57949 { 0, 0, 0, 0 },
57950 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
5348b81e 57951 & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x3b0000 }
49f58d10
JB		 57952 },
57953/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
57954 {
57955 { 0, 0, 0, 0 },
57956 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57957 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990600 }
57958 },
57959/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
57960 {
57961 { 0, 0, 0, 0 },
57962 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57963 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992600 }
57964 },
57965/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
57966 {
57967 { 0, 0, 0, 0 },
57968 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57969 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993600 }
57970 },
57971/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
57972 {
57973 { 0, 0, 0, 0 },
57974 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57975 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918600 }
57976 },
57977/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
57978 {
57979 { 0, 0, 0, 0 },
57980 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57981 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a600 }
57982 },
57983/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
57984 {
57985 { 0, 0, 0, 0 },
57986 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57987 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b600 }
57988 },
57989/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57990 {
57991 { 0, 0, 0, 0 },
57992 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57993 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910600 }
57994 },
57995/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57996 {
57997 { 0, 0, 0, 0 },
57998 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57999 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912600 }
58000 },
58001/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58002 {
58003 { 0, 0, 0, 0 },
58004 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58005 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913600 }
58006 },
58007/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58008 {
58009 { 0, 0, 0, 0 },
58010 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58011 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93060000 }
58012 },
58013/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58014 {
58015 { 0, 0, 0, 0 },
58016 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58017 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93260000 }
58018 },
58019/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58020 {
58021 { 0, 0, 0, 0 },
58022 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58023 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93360000 }
58024 },
58025/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58026 {
58027 { 0, 0, 0, 0 },
58028 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58029 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95060000 }
58030 },
58031/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58032 {
58033 { 0, 0, 0, 0 },
58034 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58035 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95260000 }
58036 },
58037/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58038 {
58039 { 0, 0, 0, 0 },
58040 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58041 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95360000 }
58042 },
58043/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58044 {
58045 { 0, 0, 0, 0 },
58046 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58047 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97060000 }
58048 },
58049/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58050 {
58051 { 0, 0, 0, 0 },
58052 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58053 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97260000 }
58054 },
58055/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58056 {
58057 { 0, 0, 0, 0 },
58058 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58059 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97360000 }
58060 },
58061/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58062 {
58063 { 0, 0, 0, 0 },
58064 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58065 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93860000 }
58066 },
58067/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58068 {
58069 { 0, 0, 0, 0 },
58070 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58071 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a60000 }
58072 },
58073/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58074 {
58075 { 0, 0, 0, 0 },
58076 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58077 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b60000 }
58078 },
58079/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58080 {
58081 { 0, 0, 0, 0 },
58082 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58083 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95860000 }
58084 },
58085/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58086 {
58087 { 0, 0, 0, 0 },
58088 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58089 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a60000 }
58090 },
58091/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58092 {
58093 { 0, 0, 0, 0 },
58094 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58095 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b60000 }
58096 },
58097/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58098 {
58099 { 0, 0, 0, 0 },
58100 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58101 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c60000 }
58102 },
58103/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58104 {
58105 { 0, 0, 0, 0 },
58106 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58107 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e60000 }
58108 },
58109/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58110 {
58111 { 0, 0, 0, 0 },
58112 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58113 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f60000 }
58114 },
58115/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58116 {
58117 { 0, 0, 0, 0 },
58118 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58119 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c60000 }
58120 },
58121/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58122 {
58123 { 0, 0, 0, 0 },
58124 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58125 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e60000 }
58126 },
58127/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58128 {
58129 { 0, 0, 0, 0 },
58130 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58131 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f60000 }
58132 },
58133/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58134 {
58135 { 0, 0, 0, 0 },
58136 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
58137 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c60000 }
58138 },
58139/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58140 {
58141 { 0, 0, 0, 0 },
58142 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
58143 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e60000 }
58144 },
58145/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58146 {
58147 { 0, 0, 0, 0 },
58148 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
58149 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f60000 }
58150 },
58151/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58152 {
58153 { 0, 0, 0, 0 },
58154 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
58155 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97860000 }
58156 },
58157/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58158 {
58159 { 0, 0, 0, 0 },
58160 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
58161 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a60000 }
58162 },
58163/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58164 {
58165 { 0, 0, 0, 0 },
58166 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
58167 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b60000 }
58168 },
58169/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58170 {
58171 { 0, 0, 0, 0 },
58172 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58173 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9060000 }
58174 },
58175/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
58176 {
58177 { 0, 0, 0, 0 },
58178 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58179 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9260000 }
58180 },
58181/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
58182 {
58183 { 0, 0, 0, 0 },
58184 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58185 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9360000 }
58186 },
58187/* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
58188 {
58189 { 0, 0, 0, 0 },
58190 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58191 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9360000 }
58192 },
58193/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58194 {
58195 { 0, 0, 0, 0 },
58196 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58197 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1860000 }
58198 },
58199/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
58200 {
58201 { 0, 0, 0, 0 },
58202 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58203 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a60000 }
58204 },
58205/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
58206 {
58207 { 0, 0, 0, 0 },
58208 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58209 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b60000 }
58210 },
58211/* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
58212 {
58213 { 0, 0, 0, 0 },
58214 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58215 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b60000 }
58216 },
58217/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58218 {
58219 { 0, 0, 0, 0 },
58220 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58221 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1060000 }
58222 },
58223/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58224 {
58225 { 0, 0, 0, 0 },
58226 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58227 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1260000 }
58228 },
58229/* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58230 {
58231 { 0, 0, 0, 0 },
58232 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58233 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1360000 }
58234 },
58235/* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58236 {
58237 { 0, 0, 0, 0 },
58238 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58239 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1360000 }
58240 },
58241/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58242 {
58243 { 0, 0, 0, 0 },
58244 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58245 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3060000 }
58246 },
58247/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58248 {
58249 { 0, 0, 0, 0 },
58250 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58251 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3260000 }
58252 },
58253/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58254 {
58255 { 0, 0, 0, 0 },
58256 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58257 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3360000 }
58258 },
58259/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58260 {
58261 { 0, 0, 0, 0 },
58262 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58263 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3360000 }
58264 },
58265/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58266 {
58267 { 0, 0, 0, 0 },
58268 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58269 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5060000 }
58270 },
58271/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58272 {
58273 { 0, 0, 0, 0 },
58274 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58275 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5260000 }
58276 },
58277/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58278 {
58279 { 0, 0, 0, 0 },
58280 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58281 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5360000 }
58282 },
58283/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58284 {
58285 { 0, 0, 0, 0 },
58286 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58287 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5360000 }
58288 },
58289/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58290 {
58291 { 0, 0, 0, 0 },
58292 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58293 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7060000 }
58294 },
58295/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58296 {
58297 { 0, 0, 0, 0 },
58298 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58299 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7260000 }
58300 },
58301/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58302 {
58303 { 0, 0, 0, 0 },
58304 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58305 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7360000 }
58306 },
58307/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58308 {
58309 { 0, 0, 0, 0 },
58310 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58311 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7360000 }
58312 },
58313/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58314 {
58315 { 0, 0, 0, 0 },
58316 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58317 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3860000 }
58318 },
58319/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58320 {
58321 { 0, 0, 0, 0 },
58322 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58323 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a60000 }
58324 },
58325/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58326 {
58327 { 0, 0, 0, 0 },
58328 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58329 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b60000 }
58330 },
58331/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58332 {
58333 { 0, 0, 0, 0 },
58334 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58335 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b60000 }
58336 },
58337/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58338 {
58339 { 0, 0, 0, 0 },
58340 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58341 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5860000 }
58342 },
58343/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58344 {
58345 { 0, 0, 0, 0 },
58346 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58347 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a60000 }
58348 },
58349/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58350 {
58351 { 0, 0, 0, 0 },
58352 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58353 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b60000 }
58354 },
58355/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58356 {
58357 { 0, 0, 0, 0 },
58358 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58359 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b60000 }
58360 },
58361/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58362 {
58363 { 0, 0, 0, 0 },
58364 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58365 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c60000 }
58366 },
58367/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58368 {
58369 { 0, 0, 0, 0 },
58370 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58371 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e60000 }
58372 },
58373/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58374 {
58375 { 0, 0, 0, 0 },
58376 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58377 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f60000 }
58378 },
58379/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58380 {
58381 { 0, 0, 0, 0 },
58382 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58383 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f60000 }
58384 },
58385/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58386 {
58387 { 0, 0, 0, 0 },
58388 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58389 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c60000 }
58390 },
58391/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58392 {
58393 { 0, 0, 0, 0 },
58394 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58395 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e60000 }
58396 },
58397/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58398 {
58399 { 0, 0, 0, 0 },
58400 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58401 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f60000 }
58402 },
58403/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58404 {
58405 { 0, 0, 0, 0 },
58406 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58407 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f60000 }
58408 },
58409/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58410 {
58411 { 0, 0, 0, 0 },
58412 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
58413 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c60000 }
58414 },
58415/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58416 {
58417 { 0, 0, 0, 0 },
58418 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58419 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e60000 }
58420 },
58421/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58422 {
58423 { 0, 0, 0, 0 },
58424 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58425 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f60000 }
58426 },
58427/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
58428 {
58429 { 0, 0, 0, 0 },
58430 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
58431 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f60000 }
58432 },
58433/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58434 {
58435 { 0, 0, 0, 0 },
58436 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
58437 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7860000 }
58438 },
58439/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58440 {
58441 { 0, 0, 0, 0 },
58442 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58443 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a60000 }
58444 },
58445/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58446 {
58447 { 0, 0, 0, 0 },
58448 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58449 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b60000 }
58450 },
58451/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
58452 {
58453 { 0, 0, 0, 0 },
58454 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
58455 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b60000 }
58456 },
58457/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58458 {
58459 { 0, 0, 0, 0 },
58460 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58461 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9060000 }
58462 },
58463/* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
58464 {
58465 { 0, 0, 0, 0 },
58466 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58467 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9260000 }
58468 },
58469/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58470 {
58471 { 0, 0, 0, 0 },
58472 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58473 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1860000 }
58474 },
58475/* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
58476 {
58477 { 0, 0, 0, 0 },
58478 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58479 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a60000 }
58480 },
58481/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58482 {
58483 { 0, 0, 0, 0 },
58484 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58485 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1060000 }
58486 },
58487/* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58488 {
58489 { 0, 0, 0, 0 },
58490 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58491 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1260000 }
58492 },
58493/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58494 {
58495 { 0, 0, 0, 0 },
58496 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58497 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3060000 }
58498 },
58499/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58500 {
58501 { 0, 0, 0, 0 },
58502 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58503 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3260000 }
58504 },
58505/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58506 {
58507 { 0, 0, 0, 0 },
58508 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58509 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5060000 }
58510 },
58511/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58512 {
58513 { 0, 0, 0, 0 },
58514 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58515 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5260000 }
58516 },
58517/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58518 {
58519 { 0, 0, 0, 0 },
58520 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58521 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7060000 }
58522 },
58523/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58524 {
58525 { 0, 0, 0, 0 },
58526 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58527 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7260000 }
58528 },
58529/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58530 {
58531 { 0, 0, 0, 0 },
58532 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
58533 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3860000 }
58534 },
58535/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58536 {
58537 { 0, 0, 0, 0 },
58538 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
58539 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a60000 }
58540 },
58541/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58542 {
58543 { 0, 0, 0, 0 },
58544 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
58545 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5860000 }
58546 },
58547/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58548 {
58549 { 0, 0, 0, 0 },
58550 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
58551 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a60000 }
58552 },
58553/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58554 {
58555 { 0, 0, 0, 0 },
58556 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
58557 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c60000 }
58558 },
58559/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58560 {
58561 { 0, 0, 0, 0 },
58562 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
58563 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e60000 }
58564 },
58565/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58566 {
58567 { 0, 0, 0, 0 },
58568 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
58569 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c60000 }
58570 },
58571/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58572 {
58573 { 0, 0, 0, 0 },
58574 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
58575 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e60000 }
58576 },
58577/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58578 {
58579 { 0, 0, 0, 0 },
58580 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
58581 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c60000 }
58582 },
58583/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
58584 {
58585 { 0, 0, 0, 0 },
58586 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
58587 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e60000 }
58588 },
58589/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58590 {
58591 { 0, 0, 0, 0 },
58592 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
58593 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7860000 }
58594 },
58595/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
58596 {
58597 { 0, 0, 0, 0 },
58598 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
58599 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a60000 }
58600 },
58601/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
58602 {
58603 { 0, 0, 0, 0 },
58604 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58605 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc906 }
58606 },
58607/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
58608 {
58609 { 0, 0, 0, 0 },
58610 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58611 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8926 }
58612 },
58613/* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58614 {
58615 { 0, 0, 0, 0 },
58616 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58617 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8906 }
58618 },
58619/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
58620 {
58621 { 0, 0, 0, 0 },
58622 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58623 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc186 }
58624 },
58625/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
58626 {
58627 { 0, 0, 0, 0 },
58628 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58629 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a6 }
58630 },
58631/* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58632 {
58633 { 0, 0, 0, 0 },
58634 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58635 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8186 }
58636 },
58637/* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
58638 {
58639 { 0, 0, 0, 0 },
58640 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58641 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc106 }
58642 },
58643/* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
58644 {
58645 { 0, 0, 0, 0 },
58646 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58647 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8126 }
58648 },
58649/* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58650 {
58651 { 0, 0, 0, 0 },
58652 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58653 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8106 }
58654 },
58655/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58656 {
58657 { 0, 0, 0, 0 },
58658 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58659 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30600 }
58660 },
58661/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58662 {
58663 { 0, 0, 0, 0 },
58664 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58665 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832600 }
58666 },
58667/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58668 {
58669 { 0, 0, 0, 0 },
58670 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58671 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830600 }
58672 },
58673/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58674 {
58675 { 0, 0, 0, 0 },
58676 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58677 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5060000 }
58678 },
58679/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58680 {
58681 { 0, 0, 0, 0 },
58682 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58683 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85260000 }
58684 },
58685/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58686 {
58687 { 0, 0, 0, 0 },
58688 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58689 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85060000 }
58690 },
58691/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58692 {
58693 { 0, 0, 0, 0 },
58694 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58695 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7060000 }
58696 },
58697/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58698 {
58699 { 0, 0, 0, 0 },
58700 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58701 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87260000 }
58702 },
58703/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58704 {
58705 { 0, 0, 0, 0 },
58706 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58707 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87060000 }
58708 },
58709/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
58710 {
58711 { 0, 0, 0, 0 },
58712 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58713 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38600 }
58714 },
58715/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
58716 {
58717 { 0, 0, 0, 0 },
58718 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58719 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a600 }
58720 },
58721/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58722 {
58723 { 0, 0, 0, 0 },
58724 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58725 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838600 }
58726 },
58727/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
58728 {
58729 { 0, 0, 0, 0 },
58730 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58731 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5860000 }
58732 },
58733/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
58734 {
58735 { 0, 0, 0, 0 },
58736 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58737 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a60000 }
58738 },
58739/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58740 {
58741 { 0, 0, 0, 0 },
58742 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58743 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85860000 }
58744 },
58745/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
58746 {
58747 { 0, 0, 0, 0 },
58748 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58749 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c600 }
58750 },
58751/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
58752 {
58753 { 0, 0, 0, 0 },
58754 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58755 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e600 }
58756 },
58757/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58758 {
58759 { 0, 0, 0, 0 },
58760 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58761 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c600 }
58762 },
58763/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
58764 {
58765 { 0, 0, 0, 0 },
58766 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58767 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c60000 }
58768 },
58769/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
58770 {
58771 { 0, 0, 0, 0 },
58772 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58773 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e60000 }
58774 },
58775/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58776 {
58777 { 0, 0, 0, 0 },
58778 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58779 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c60000 }
58780 },
58781/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
58782 {
58783 { 0, 0, 0, 0 },
58784 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
58785 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c60000 }
58786 },
58787/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
58788 {
58789 { 0, 0, 0, 0 },
58790 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
58791 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e60000 }
58792 },
58793/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58794 {
58795 { 0, 0, 0, 0 },
58796 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
58797 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c60000 }
58798 },
58799/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
58800 {
58801 { 0, 0, 0, 0 },
58802 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
58803 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7860000 }
58804 },
58805/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
58806 {
58807 { 0, 0, 0, 0 },
58808 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
58809 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a60000 }
58810 },
58811/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58812 {
58813 { 0, 0, 0, 0 },
58814 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
58815 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87860000 }
58816 },
58817/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
58818 {
58819 { 0, 0, 0, 0 },
58820 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58821 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980600 }
58822 },
58823/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
58824 {
58825 { 0, 0, 0, 0 },
58826 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58827 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982600 }
58828 },
58829/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
58830 {
58831 { 0, 0, 0, 0 },
58832 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58833 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983600 }
58834 },
58835/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
58836 {
58837 { 0, 0, 0, 0 },
58838 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58839 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908600 }
58840 },
58841/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
58842 {
58843 { 0, 0, 0, 0 },
58844 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58845 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a600 }
58846 },
58847/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
58848 {
58849 { 0, 0, 0, 0 },
58850 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58851 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b600 }
58852 },
58853/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58854 {
58855 { 0, 0, 0, 0 },
58856 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58857 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900600 }
58858 },
58859/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58860 {
58861 { 0, 0, 0, 0 },
58862 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58863 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902600 }
58864 },
58865/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58866 {
58867 { 0, 0, 0, 0 },
58868 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58869 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903600 }
58870 },
58871/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58872 {
58873 { 0, 0, 0, 0 },
58874 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58875 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92060000 }
58876 },
58877/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58878 {
58879 { 0, 0, 0, 0 },
58880 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58881 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92260000 }
58882 },
58883/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58884 {
58885 { 0, 0, 0, 0 },
58886 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58887 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92360000 }
58888 },
58889/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58890 {
58891 { 0, 0, 0, 0 },
58892 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58893 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94060000 }
58894 },
58895/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58896 {
58897 { 0, 0, 0, 0 },
58898 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58899 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94260000 }
58900 },
58901/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58902 {
58903 { 0, 0, 0, 0 },
58904 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58905 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94360000 }
58906 },
58907/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58908 {
58909 { 0, 0, 0, 0 },
58910 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58911 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96060000 }
58912 },
58913/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58914 {
58915 { 0, 0, 0, 0 },
58916 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58917 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96260000 }
58918 },
58919/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58920 {
58921 { 0, 0, 0, 0 },
58922 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58923 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96360000 }
58924 },
58925/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58926 {
58927 { 0, 0, 0, 0 },
58928 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58929 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92860000 }
58930 },
58931/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58932 {
58933 { 0, 0, 0, 0 },
58934 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58935 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a60000 }
58936 },
58937/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58938 {
58939 { 0, 0, 0, 0 },
58940 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58941 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b60000 }
58942 },
58943/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58944 {
58945 { 0, 0, 0, 0 },
58946 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58947 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94860000 }
58948 },
58949/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58950 {
58951 { 0, 0, 0, 0 },
58952 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58953 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a60000 }
58954 },
58955/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58956 {
58957 { 0, 0, 0, 0 },
58958 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58959 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b60000 }
58960 },
58961/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58962 {
58963 { 0, 0, 0, 0 },
58964 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58965 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c60000 }
58966 },
58967/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58968 {
58969 { 0, 0, 0, 0 },
58970 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58971 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e60000 }
58972 },
58973/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58974 {
58975 { 0, 0, 0, 0 },
58976 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58977 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f60000 }
58978 },
58979/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58980 {
58981 { 0, 0, 0, 0 },
58982 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58983 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c60000 }
58984 },
58985/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58986 {
58987 { 0, 0, 0, 0 },
58988 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58989 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e60000 }
58990 },
58991/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58992 {
58993 { 0, 0, 0, 0 },
58994 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58995 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f60000 }
58996 },
58997/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58998 {
58999 { 0, 0, 0, 0 },
59000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
59001 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c60000 }
59002 },
59003/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59004 {
59005 { 0, 0, 0, 0 },
59006 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59007 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e60000 }
59008 },
59009/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59010 {
59011 { 0, 0, 0, 0 },
59012 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59013 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f60000 }
59014 },
59015/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
59016 {
59017 { 0, 0, 0, 0 },
59018 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
59019 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96860000 }
59020 },
59021/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
59022 {
59023 { 0, 0, 0, 0 },
59024 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
59025 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a60000 }
59026 },
59027/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
59028 {
59029 { 0, 0, 0, 0 },
59030 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
59031 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b60000 }
59032 },
59033/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59034 {
59035 { 0, 0, 0, 0 },
59036 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59037 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8060000 }
59038 },
59039/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
59040 {
59041 { 0, 0, 0, 0 },
59042 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59043 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8260000 }
59044 },
59045/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
59046 {
59047 { 0, 0, 0, 0 },
59048 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59049 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8360000 }
59050 },
59051/* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
59052 {
59053 { 0, 0, 0, 0 },
59054 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59055 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8360000 }
59056 },
59057/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59058 {
59059 { 0, 0, 0, 0 },
59060 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59061 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0860000 }
59062 },
59063/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
59064 {
59065 { 0, 0, 0, 0 },
59066 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59067 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a60000 }
59068 },
59069/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
59070 {
59071 { 0, 0, 0, 0 },
59072 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59073 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b60000 }
59074 },
59075/* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
59076 {
59077 { 0, 0, 0, 0 },
59078 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59079 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b60000 }
59080 },
59081/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59082 {
59083 { 0, 0, 0, 0 },
59084 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59085 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0060000 }
59086 },
59087/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
59088 {
59089 { 0, 0, 0, 0 },
59090 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59091 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0260000 }
59092 },
59093/* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
59094 {
59095 { 0, 0, 0, 0 },
59096 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59097 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0360000 }
59098 },
59099/* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
59100 {
59101 { 0, 0, 0, 0 },
59102 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59103 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0360000 }
59104 },
59105/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59106 {
59107 { 0, 0, 0, 0 },
59108 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59109 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2060000 }
59110 },
59111/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59112 {
59113 { 0, 0, 0, 0 },
59114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59115 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2260000 }
59116 },
59117/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59118 {
59119 { 0, 0, 0, 0 },
59120 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59121 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2360000 }
59122 },
59123/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
59124 {
59125 { 0, 0, 0, 0 },
59126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59127 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2360000 }
59128 },
59129/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59130 {
59131 { 0, 0, 0, 0 },
59132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59133 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4060000 }
59134 },
59135/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59136 {
59137 { 0, 0, 0, 0 },
59138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59139 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4260000 }
59140 },
59141/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59142 {
59143 { 0, 0, 0, 0 },
59144 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59145 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4360000 }
59146 },
59147/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
59148 {
59149 { 0, 0, 0, 0 },
59150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59151 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4360000 }
59152 },
59153/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59154 {
59155 { 0, 0, 0, 0 },
59156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59157 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6060000 }
59158 },
59159/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59160 {
59161 { 0, 0, 0, 0 },
59162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59163 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6260000 }
59164 },
59165/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59166 {
59167 { 0, 0, 0, 0 },
59168 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59169 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6360000 }
59170 },
59171/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
59172 {
59173 { 0, 0, 0, 0 },
59174 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59175 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6360000 }
59176 },
59177/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
59178 {
59179 { 0, 0, 0, 0 },
59180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59181 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2860000 }
59182 },
59183/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59184 {
59185 { 0, 0, 0, 0 },
59186 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59187 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a60000 }
59188 },
59189/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
59190 {
59191 { 0, 0, 0, 0 },
59192 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59193 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b60000 }
59194 },
59195/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59196 {
59197 { 0, 0, 0, 0 },
59198 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59199 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b60000 }
59200 },
59201/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
59202 {
59203 { 0, 0, 0, 0 },
59204 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59205 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4860000 }
59206 },
59207/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59208 {
59209 { 0, 0, 0, 0 },
59210 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59211 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a60000 }
59212 },
59213/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
59214 {
59215 { 0, 0, 0, 0 },
59216 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59217 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b60000 }
59218 },
59219/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59220 {
59221 { 0, 0, 0, 0 },
59222 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59223 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b60000 }
59224 },
59225/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
59226 {
59227 { 0, 0, 0, 0 },
59228 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59229 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c60000 }
59230 },
59231/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59232 {
59233 { 0, 0, 0, 0 },
59234 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59235 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e60000 }
59236 },
59237/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59238 {
59239 { 0, 0, 0, 0 },
59240 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59241 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f60000 }
59242 },
59243/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59244 {
59245 { 0, 0, 0, 0 },
59246 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59247 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f60000 }
59248 },
59249/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59250 {
59251 { 0, 0, 0, 0 },
59252 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59253 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c60000 }
59254 },
59255/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59256 {
59257 { 0, 0, 0, 0 },
59258 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59259 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e60000 }
59260 },
59261/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59262 {
59263 { 0, 0, 0, 0 },
59264 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59265 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f60000 }
59266 },
59267/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59268 {
59269 { 0, 0, 0, 0 },
59270 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59271 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f60000 }
59272 },
59273/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59274 {
59275 { 0, 0, 0, 0 },
59276 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
59277 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c60000 }
59278 },
59279/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59280 {
59281 { 0, 0, 0, 0 },
59282 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
59283 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e60000 }
59284 },
59285/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59286 {
59287 { 0, 0, 0, 0 },
59288 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
59289 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f60000 }
59290 },
59291/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
59292 {
59293 { 0, 0, 0, 0 },
59294 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
59295 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f60000 }
59296 },
59297/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59298 {
59299 { 0, 0, 0, 0 },
59300 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
59301 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6860000 }
59302 },
59303/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59304 {
59305 { 0, 0, 0, 0 },
59306 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
59307 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a60000 }
59308 },
59309/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59310 {
59311 { 0, 0, 0, 0 },
59312 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
59313 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b60000 }
59314 },
59315/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
59316 {
59317 { 0, 0, 0, 0 },
59318 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
59319 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b60000 }
59320 },
59321/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59322 {
59323 { 0, 0, 0, 0 },
59324 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59325 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8060000 }
59326 },
59327/* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
59328 {
59329 { 0, 0, 0, 0 },
59330 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59331 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8260000 }
59332 },
59333/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59334 {
59335 { 0, 0, 0, 0 },
59336 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59337 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0860000 }
59338 },
59339/* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
59340 {
59341 { 0, 0, 0, 0 },
59342 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59343 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a60000 }
59344 },
59345/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59346 {
59347 { 0, 0, 0, 0 },
59348 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59349 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0060000 }
59350 },
59351/* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59352 {
59353 { 0, 0, 0, 0 },
59354 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59355 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0260000 }
59356 },
59357/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59358 {
59359 { 0, 0, 0, 0 },
59360 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59361 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2060000 }
59362 },
59363/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59364 {
59365 { 0, 0, 0, 0 },
59366 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59367 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2260000 }
59368 },
59369/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59370 {
59371 { 0, 0, 0, 0 },
59372 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59373 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4060000 }
59374 },
59375/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59376 {
59377 { 0, 0, 0, 0 },
59378 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59379 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4260000 }
59380 },
59381/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59382 {
59383 { 0, 0, 0, 0 },
59384 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59385 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6060000 }
59386 },
59387/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59388 {
59389 { 0, 0, 0, 0 },
59390 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59391 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6260000 }
59392 },
59393/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59394 {
59395 { 0, 0, 0, 0 },
59396 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
59397 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2860000 }
59398 },
59399/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59400 {
59401 { 0, 0, 0, 0 },
59402 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
59403 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a60000 }
59404 },
59405/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59406 {
59407 { 0, 0, 0, 0 },
59408 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
59409 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4860000 }
59410 },
59411/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59412 {
59413 { 0, 0, 0, 0 },
59414 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
59415 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a60000 }
59416 },
59417/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59418 {
59419 { 0, 0, 0, 0 },
59420 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
59421 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c60000 }
59422 },
59423/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59424 {
59425 { 0, 0, 0, 0 },
59426 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
59427 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e60000 }
59428 },
59429/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59430 {
59431 { 0, 0, 0, 0 },
59432 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
59433 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c60000 }
59434 },
59435/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59436 {
59437 { 0, 0, 0, 0 },
59438 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
59439 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e60000 }
59440 },
59441/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59442 {
59443 { 0, 0, 0, 0 },
59444 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
59445 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c60000 }
59446 },
59447/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59448 {
59449 { 0, 0, 0, 0 },
59450 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
59451 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e60000 }
59452 },
59453/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59454 {
59455 { 0, 0, 0, 0 },
59456 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
59457 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6860000 }
59458 },
59459/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59460 {
59461 { 0, 0, 0, 0 },
59462 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
59463 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a60000 }
59464 },
59465/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59466 {
59467 { 0, 0, 0, 0 },
59468 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59469 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc806 }
59470 },
59471/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59472 {
59473 { 0, 0, 0, 0 },
59474 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59475 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8826 }
59476 },
59477/* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59478 {
59479 { 0, 0, 0, 0 },
59480 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59481 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8806 }
59482 },
59483/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59484 {
59485 { 0, 0, 0, 0 },
59486 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59487 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc086 }
59488 },
59489/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59490 {
59491 { 0, 0, 0, 0 },
59492 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59493 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a6 }
59494 },
59495/* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59496 {
59497 { 0, 0, 0, 0 },
59498 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59499 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8086 }
59500 },
59501/* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59502 {
59503 { 0, 0, 0, 0 },
59504 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59505 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc006 }
59506 },
59507/* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59508 {
59509 { 0, 0, 0, 0 },
59510 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59511 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8026 }
59512 },
59513/* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59514 {
59515 { 0, 0, 0, 0 },
59516 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59517 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8006 }
59518 },
59519/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59520 {
59521 { 0, 0, 0, 0 },
59522 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59523 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20600 }
59524 },
59525/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59526 {
59527 { 0, 0, 0, 0 },
59528 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59529 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822600 }
59530 },
59531/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59532 {
59533 { 0, 0, 0, 0 },
59534 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59535 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820600 }
59536 },
59537/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59538 {
59539 { 0, 0, 0, 0 },
59540 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59541 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4060000 }
59542 },
59543/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59544 {
59545 { 0, 0, 0, 0 },
59546 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59547 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84260000 }
59548 },
59549/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59550 {
59551 { 0, 0, 0, 0 },
59552 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59553 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84060000 }
59554 },
59555/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59556 {
59557 { 0, 0, 0, 0 },
59558 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59559 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6060000 }
59560 },
59561/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59562 {
59563 { 0, 0, 0, 0 },
59564 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59565 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86260000 }
59566 },
59567/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59568 {
59569 { 0, 0, 0, 0 },
59570 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59571 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86060000 }
59572 },
59573/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
59574 {
59575 { 0, 0, 0, 0 },
59576 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59577 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28600 }
59578 },
59579/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
59580 {
59581 { 0, 0, 0, 0 },
59582 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59583 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a600 }
59584 },
59585/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59586 {
59587 { 0, 0, 0, 0 },
59588 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59589 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828600 }
59590 },
59591/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
59592 {
59593 { 0, 0, 0, 0 },
59594 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59595 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4860000 }
59596 },
59597/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
59598 {
59599 { 0, 0, 0, 0 },
59600 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59601 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a60000 }
59602 },
59603/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59604 {
59605 { 0, 0, 0, 0 },
59606 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59607 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84860000 }
59608 },
59609/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
59610 {
59611 { 0, 0, 0, 0 },
59612 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59613 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c600 }
59614 },
59615/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
59616 {
59617 { 0, 0, 0, 0 },
59618 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59619 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e600 }
59620 },
59621/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59622 {
59623 { 0, 0, 0, 0 },
59624 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59625 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c600 }
59626 },
59627/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
59628 {
59629 { 0, 0, 0, 0 },
59630 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59631 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c60000 }
59632 },
59633/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
59634 {
59635 { 0, 0, 0, 0 },
59636 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59637 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e60000 }
59638 },
59639/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59640 {
59641 { 0, 0, 0, 0 },
59642 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59643 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c60000 }
59644 },
59645/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
59646 {
59647 { 0, 0, 0, 0 },
59648 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
59649 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c60000 }
59650 },
59651/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
59652 {
59653 { 0, 0, 0, 0 },
59654 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
59655 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e60000 }
59656 },
59657/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59658 {
59659 { 0, 0, 0, 0 },
59660 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
59661 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c60000 }
59662 },
59663/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
59664 {
59665 { 0, 0, 0, 0 },
59666 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
59667 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6860000 }
59668 },
59669/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
59670 {
59671 { 0, 0, 0, 0 },
59672 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
59673 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a60000 }
59674 },
59675/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59676 {
59677 { 0, 0, 0, 0 },
59678 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
59679 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86860000 }
59680 },
59681/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
59682 {
59683 { 0, 0, 0, 0 },
59684 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
59685 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xc18000 }
59686 },
59687/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
59688 {
59689 { 0, 0, 0, 0 },
59690 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
59691 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1a000 }
59692 },
59693/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
59694 {
59695 { 0, 0, 0, 0 },
59696 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
59697 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xc1b000 }
59698 },
59699/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
59700 {
59701 { 0, 0, 0, 0 },
59702 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
59703 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xc18400 }
59704 },
59705/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
59706 {
59707 { 0, 0, 0, 0 },
59708 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
59709 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xc1a400 }
59710 },
59711/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
59712 {
59713 { 0, 0, 0, 0 },
59714 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
59715 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xc1b400 }
59716 },
59717/* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
59718 {
59719 { 0, 0, 0, 0 },
59720 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59721 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xc18600 }
59722 },
59723/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
59724 {
59725 { 0, 0, 0, 0 },
59726 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59727 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xc1a600 }
59728 },
59729/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
59730 {
59731 { 0, 0, 0, 0 },
59732 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59733 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xc1b600 }
59734 },
59735/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
59736 {
59737 { 0, 0, 0, 0 },
59738 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59739 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xc1880000 }
59740 },
59741/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
59742 {
59743 { 0, 0, 0, 0 },
59744 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59745 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1a80000 }
59746 },
59747/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
59748 {
59749 { 0, 0, 0, 0 },
59750 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59751 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1b80000 }
59752 },
59753/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
59754 {
59755 { 0, 0, 0, 0 },
59756 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59757 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xc18c0000 }
59758 },
59759/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
59760 {
59761 { 0, 0, 0, 0 },
59762 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59763 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1ac0000 }
59764 },
59765/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
59766 {
59767 { 0, 0, 0, 0 },
59768 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59769 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1bc0000 }
59770 },
59771/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
59772 {
59773 { 0, 0, 0, 0 },
59774 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59775 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xc18a0000 }
59776 },
59777/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59778 {
59779 { 0, 0, 0, 0 },
59780 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59781 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1aa0000 }
59782 },
59783/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59784 {
59785 { 0, 0, 0, 0 },
59786 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59787 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1ba0000 }
59788 },
59789/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
59790 {
59791 { 0, 0, 0, 0 },
59792 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59793 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xc18e0000 }
59794 },
59795/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59796 {
59797 { 0, 0, 0, 0 },
59798 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59799 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1ae0000 }
59800 },
59801/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59802 {
59803 { 0, 0, 0, 0 },
59804 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59805 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1be0000 }
59806 },
59807/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
59808 {
59809 { 0, 0, 0, 0 },
59810 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59811 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xc18b0000 }
59812 },
59813/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59814 {
59815 { 0, 0, 0, 0 },
59816 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59817 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1ab0000 }
59818 },
59819/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59820 {
59821 { 0, 0, 0, 0 },
59822 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59823 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1bb0000 }
59824 },
59825/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
59826 {
59827 { 0, 0, 0, 0 },
59828 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
59829 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xc18f0000 }
59830 },
59831/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59832 {
59833 { 0, 0, 0, 0 },
59834 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59835 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xc1af0000 }
59836 },
59837/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59838 {
59839 { 0, 0, 0, 0 },
59840 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59841 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xc1bf0000 }
59842 },
59843/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
59844 {
59845 { 0, 0, 0, 0 },
59846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
59847 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xc1c00000 }
59848 },
59849/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
59850 {
59851 { 0, 0, 0, 0 },
59852 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
59853 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1e00000 }
59854 },
59855/* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
59856 {
59857 { 0, 0, 0, 0 },
59858 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
59859 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xc1f00000 }
59860 },
59861/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
59862 {
59863 { 0, 0, 0, 0 },
59864 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
59865 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xc1c40000 }
59866 },
59867/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
59868 {
59869 { 0, 0, 0, 0 },
59870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
59871 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xc1e40000 }
59872 },
59873/* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
59874 {
59875 { 0, 0, 0, 0 },
59876 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
59877 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xc1f40000 }
59878 },
59879/* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
59880 {
59881 { 0, 0, 0, 0 },
59882 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59883 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xc1c60000 }
59884 },
59885/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
59886 {
59887 { 0, 0, 0, 0 },
59888 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59889 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xc1e60000 }
59890 },
59891/* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
59892 {
59893 { 0, 0, 0, 0 },
59894 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
59895 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xc1f60000 }
59896 },
59897/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
59898 {
59899 { 0, 0, 0, 0 },
59900 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59901 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xc1c80000 }
59902 },
59903/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
59904 {
59905 { 0, 0, 0, 0 },
59906 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59907 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xc1e80000 }
59908 },
59909/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
59910 {
59911 { 0, 0, 0, 0 },
59912 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59913 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xc1f80000 }
59914 },
59915/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
59916 {
59917 { 0, 0, 0, 0 },
59918 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59919 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xc1cc0000 }
59920 },
59921/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
59922 {
59923 { 0, 0, 0, 0 },
59924 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59925 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xc1ec0000 }
59926 },
59927/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
59928 {
59929 { 0, 0, 0, 0 },
59930 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59931 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xc1fc0000 }
59932 },
59933/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
59934 {
59935 { 0, 0, 0, 0 },
59936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59937 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ca0000 }
59938 },
59939/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59940 {
59941 { 0, 0, 0, 0 },
59942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59943 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ea0000 }
59944 },
59945/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59946 {
59947 { 0, 0, 0, 0 },
59948 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59949 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xc1fa0000 }
59950 },
59951/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
59952 {
59953 { 0, 0, 0, 0 },
59954 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59955 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ce0000 }
59956 },
59957/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59958 {
59959 { 0, 0, 0, 0 },
59960 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59961 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ee0000 }
59962 },
59963/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59964 {
59965 { 0, 0, 0, 0 },
59966 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59967 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xc1fe0000 }
59968 },
59969/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
59970 {
59971 { 0, 0, 0, 0 },
59972 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59973 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1cb0000 }
59974 },
59975/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59976 {
59977 { 0, 0, 0, 0 },
59978 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59979 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1eb0000 }
59980 },
59981/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59982 {
59983 { 0, 0, 0, 0 },
59984 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59985 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xc1fb0000 }
59986 },
59987/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
59988 {
59989 { 0, 0, 0, 0 },
59990 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
59991 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xc1cf0000 }
59992 },
59993/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59994 {
59995 { 0, 0, 0, 0 },
59996 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
59997 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xc1ef0000 }
59998 },
59999/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
60000 {
60001 { 0, 0, 0, 0 },
60002 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
60003 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xc1ff0000 }
60004 },
60005/* cmp.w${G} $Src16RnHI,$Dst16RnHI */
60006 {
60007 { 0, 0, 0, 0 },
60008 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
60009 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xc100 }
60010 },
60011/* cmp.w${G} $Src16AnHI,$Dst16RnHI */
60012 {
60013 { 0, 0, 0, 0 },
60014 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
60015 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xc140 }
60016 },
60017/* cmp.w${G} [$Src16An],$Dst16RnHI */
60018 {
60019 { 0, 0, 0, 0 },
60020 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
60021 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xc160 }
60022 },
60023/* cmp.w${G} $Src16RnHI,$Dst16AnHI */
60024 {
60025 { 0, 0, 0, 0 },
60026 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
60027 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xc104 }
60028 },
60029/* cmp.w${G} $Src16AnHI,$Dst16AnHI */
60030 {
60031 { 0, 0, 0, 0 },
60032 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
60033 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xc144 }
60034 },
60035/* cmp.w${G} [$Src16An],$Dst16AnHI */
60036 {
60037 { 0, 0, 0, 0 },
60038 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
60039 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xc164 }
60040 },
60041/* cmp.w${G} $Src16RnHI,[$Dst16An] */
60042 {
60043 { 0, 0, 0, 0 },
60044 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
60045 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xc106 }
60046 },
60047/* cmp.w${G} $Src16AnHI,[$Dst16An] */
60048 {
60049 { 0, 0, 0, 0 },
60050 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
60051 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xc146 }
60052 },
60053/* cmp.w${G} [$Src16An],[$Dst16An] */
60054 {
60055 { 0, 0, 0, 0 },
60056 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60057 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xc166 }
60058 },
60059/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
60060 {
60061 { 0, 0, 0, 0 },
60062 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60063 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xc10800 }
60064 },
60065/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
60066 {
60067 { 0, 0, 0, 0 },
60068 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60069 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xc14800 }
60070 },
60071/* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60072 {
60073 { 0, 0, 0, 0 },
60074 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60075 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xc16800 }
60076 },
60077/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
60078 {
60079 { 0, 0, 0, 0 },
60080 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60081 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xc10c0000 }
60082 },
60083/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
60084 {
60085 { 0, 0, 0, 0 },
60086 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60087 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xc14c0000 }
60088 },
60089/* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60090 {
60091 { 0, 0, 0, 0 },
60092 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60093 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xc16c0000 }
60094 },
60095/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
60096 {
60097 { 0, 0, 0, 0 },
60098 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60099 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xc10a00 }
60100 },
60101/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
60102 {
60103 { 0, 0, 0, 0 },
60104 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60105 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xc14a00 }
60106 },
60107/* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
60108 {
60109 { 0, 0, 0, 0 },
60110 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60111 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xc16a00 }
60112 },
60113/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
60114 {
60115 { 0, 0, 0, 0 },
60116 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60117 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xc10e0000 }
60118 },
60119/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
60120 {
60121 { 0, 0, 0, 0 },
60122 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60123 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xc14e0000 }
60124 },
60125/* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
60126 {
60127 { 0, 0, 0, 0 },
60128 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60129 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xc16e0000 }
60130 },
60131/* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
60132 {
60133 { 0, 0, 0, 0 },
60134 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60135 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xc10b00 }
60136 },
60137/* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
60138 {
60139 { 0, 0, 0, 0 },
60140 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60141 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xc14b00 }
60142 },
60143/* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
60144 {
60145 { 0, 0, 0, 0 },
60146 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60147 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xc16b00 }
60148 },
60149/* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
60150 {
60151 { 0, 0, 0, 0 },
60152 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
60153 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xc10f0000 }
60154 },
60155/* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
60156 {
60157 { 0, 0, 0, 0 },
60158 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
60159 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xc14f0000 }
60160 },
60161/* cmp.w${G} [$Src16An],${Dsp-16-u16} */
60162 {
60163 { 0, 0, 0, 0 },
60164 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
60165 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xc16f0000 }
60166 },
60167/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
60168 {
60169 { 0, 0, 0, 0 },
60170 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
60171 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xc08000 }
60172 },
60173/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
60174 {
60175 { 0, 0, 0, 0 },
60176 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
60177 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0a000 }
60178 },
60179/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
60180 {
60181 { 0, 0, 0, 0 },
60182 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
60183 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xc0b000 }
60184 },
60185/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
60186 {
60187 { 0, 0, 0, 0 },
60188 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
60189 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xc08400 }
60190 },
60191/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
60192 {
60193 { 0, 0, 0, 0 },
60194 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
60195 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xc0a400 }
60196 },
60197/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
60198 {
60199 { 0, 0, 0, 0 },
60200 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
60201 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xc0b400 }
60202 },
60203/* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60204 {
60205 { 0, 0, 0, 0 },
60206 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60207 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xc08600 }
60208 },
60209/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60210 {
60211 { 0, 0, 0, 0 },
60212 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
60213 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xc0a600 }
60214 },
60215/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60216 {
60217 { 0, 0, 0, 0 },
60218 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
60219 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xc0b600 }
60220 },
60221/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60222 {
60223 { 0, 0, 0, 0 },
60224 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
60225 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xc0880000 }
60226 },
60227/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60228 {
60229 { 0, 0, 0, 0 },
60230 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
60231 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0a80000 }
60232 },
60233/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60234 {
60235 { 0, 0, 0, 0 },
60236 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
60237 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0b80000 }
60238 },
60239/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60240 {
60241 { 0, 0, 0, 0 },
60242 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
60243 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xc08c0000 }
60244 },
60245/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60246 {
60247 { 0, 0, 0, 0 },
60248 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
60249 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0ac0000 }
60250 },
60251/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60252 {
60253 { 0, 0, 0, 0 },
60254 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
60255 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0bc0000 }
60256 },
60257/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60258 {
60259 { 0, 0, 0, 0 },
60260 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60261 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xc08a0000 }
60262 },
60263/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60264 {
60265 { 0, 0, 0, 0 },
60266 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60267 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0aa0000 }
60268 },
60269/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60270 {
60271 { 0, 0, 0, 0 },
60272 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60273 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0ba0000 }
60274 },
60275/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60276 {
60277 { 0, 0, 0, 0 },
60278 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60279 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xc08e0000 }
60280 },
60281/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60282 {
60283 { 0, 0, 0, 0 },
60284 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60285 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0ae0000 }
60286 },
60287/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60288 {
60289 { 0, 0, 0, 0 },
60290 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60291 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0be0000 }
60292 },
60293/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60294 {
60295 { 0, 0, 0, 0 },
60296 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60297 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xc08b0000 }
60298 },
60299/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60300 {
60301 { 0, 0, 0, 0 },
60302 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60303 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0ab0000 }
60304 },
60305/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60306 {
60307 { 0, 0, 0, 0 },
60308 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60309 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0bb0000 }
60310 },
60311/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60312 {
60313 { 0, 0, 0, 0 },
60314 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
60315 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xc08f0000 }
60316 },
60317/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60318 {
60319 { 0, 0, 0, 0 },
60320 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
60321 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xc0af0000 }
60322 },
60323/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60324 {
60325 { 0, 0, 0, 0 },
60326 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
60327 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xc0bf0000 }
60328 },
60329/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
60330 {
60331 { 0, 0, 0, 0 },
60332 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
60333 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xc0c00000 }
60334 },
60335/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
60336 {
60337 { 0, 0, 0, 0 },
60338 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
60339 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0e00000 }
60340 },
60341/* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
60342 {
60343 { 0, 0, 0, 0 },
60344 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
60345 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xc0f00000 }
60346 },
60347/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
60348 {
60349 { 0, 0, 0, 0 },
60350 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
60351 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xc0c40000 }
60352 },
60353/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
60354 {
60355 { 0, 0, 0, 0 },
60356 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
60357 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xc0e40000 }
60358 },
60359/* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
60360 {
60361 { 0, 0, 0, 0 },
60362 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
60363 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xc0f40000 }
60364 },
60365/* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60366 {
60367 { 0, 0, 0, 0 },
60368 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60369 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xc0c60000 }
60370 },
60371/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60372 {
60373 { 0, 0, 0, 0 },
60374 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
60375 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xc0e60000 }
60376 },
60377/* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
60378 {
60379 { 0, 0, 0, 0 },
60380 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
60381 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xc0f60000 }
60382 },
60383/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60384 {
60385 { 0, 0, 0, 0 },
60386 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60387 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xc0c80000 }
60388 },
60389/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60390 {
60391 { 0, 0, 0, 0 },
60392 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60393 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xc0e80000 }
60394 },
60395/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60396 {
60397 { 0, 0, 0, 0 },
60398 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60399 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xc0f80000 }
60400 },
60401/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60402 {
60403 { 0, 0, 0, 0 },
60404 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60405 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xc0cc0000 }
60406 },
60407/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60408 {
60409 { 0, 0, 0, 0 },
60410 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60411 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xc0ec0000 }
60412 },
60413/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60414 {
60415 { 0, 0, 0, 0 },
60416 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60417 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xc0fc0000 }
60418 },
60419/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60420 {
60421 { 0, 0, 0, 0 },
60422 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60423 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ca0000 }
60424 },
60425/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60426 {
60427 { 0, 0, 0, 0 },
60428 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60429 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ea0000 }
60430 },
60431/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60432 {
60433 { 0, 0, 0, 0 },
60434 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60435 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xc0fa0000 }
60436 },
60437/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60438 {
60439 { 0, 0, 0, 0 },
60440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60441 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ce0000 }
60442 },
60443/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60444 {
60445 { 0, 0, 0, 0 },
60446 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60447 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ee0000 }
60448 },
60449/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60450 {
60451 { 0, 0, 0, 0 },
60452 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60453 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xc0fe0000 }
60454 },
60455/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60456 {
60457 { 0, 0, 0, 0 },
60458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60459 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0cb0000 }
60460 },
60461/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60462 {
60463 { 0, 0, 0, 0 },
60464 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60465 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0eb0000 }
60466 },
60467/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60468 {
60469 { 0, 0, 0, 0 },
60470 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60471 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xc0fb0000 }
60472 },
60473/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60474 {
60475 { 0, 0, 0, 0 },
60476 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
60477 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xc0cf0000 }
60478 },
60479/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60480 {
60481 { 0, 0, 0, 0 },
60482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
60483 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xc0ef0000 }
60484 },
60485/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60486 {
60487 { 0, 0, 0, 0 },
60488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
60489 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xc0ff0000 }
60490 },
60491/* cmp.b${G} $Src16RnQI,$Dst16RnQI */
60492 {
60493 { 0, 0, 0, 0 },
60494 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
60495 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xc000 }
60496 },
60497/* cmp.b${G} $Src16AnQI,$Dst16RnQI */
60498 {
60499 { 0, 0, 0, 0 },
60500 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
60501 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xc040 }
60502 },
60503/* cmp.b${G} [$Src16An],$Dst16RnQI */
60504 {
60505 { 0, 0, 0, 0 },
60506 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
60507 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xc060 }
60508 },
60509/* cmp.b${G} $Src16RnQI,$Dst16AnQI */
60510 {
60511 { 0, 0, 0, 0 },
60512 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
60513 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xc004 }
60514 },
60515/* cmp.b${G} $Src16AnQI,$Dst16AnQI */
60516 {
60517 { 0, 0, 0, 0 },
60518 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
60519 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xc044 }
60520 },
60521/* cmp.b${G} [$Src16An],$Dst16AnQI */
60522 {
60523 { 0, 0, 0, 0 },
60524 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
60525 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xc064 }
60526 },
60527/* cmp.b${G} $Src16RnQI,[$Dst16An] */
60528 {
60529 { 0, 0, 0, 0 },
60530 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
60531 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xc006 }
60532 },
60533/* cmp.b${G} $Src16AnQI,[$Dst16An] */
60534 {
60535 { 0, 0, 0, 0 },
60536 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
60537 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xc046 }
60538 },
60539/* cmp.b${G} [$Src16An],[$Dst16An] */
60540 {
60541 { 0, 0, 0, 0 },
60542 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60543 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xc066 }
60544 },
60545/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60546 {
60547 { 0, 0, 0, 0 },
60548 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60549 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xc00800 }
60550 },
60551/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60552 {
60553 { 0, 0, 0, 0 },
60554 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60555 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xc04800 }
60556 },
60557/* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60558 {
60559 { 0, 0, 0, 0 },
60560 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60561 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xc06800 }
60562 },
60563/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60564 {
60565 { 0, 0, 0, 0 },
60566 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60567 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xc00c0000 }
60568 },
60569/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60570 {
60571 { 0, 0, 0, 0 },
60572 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60573 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xc04c0000 }
60574 },
60575/* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60576 {
60577 { 0, 0, 0, 0 },
60578 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60579 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xc06c0000 }
60580 },
60581/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60582 {
60583 { 0, 0, 0, 0 },
60584 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60585 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xc00a00 }
60586 },
60587/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60588 {
60589 { 0, 0, 0, 0 },
60590 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60591 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xc04a00 }
60592 },
60593/* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60594 {
60595 { 0, 0, 0, 0 },
60596 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60597 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xc06a00 }
60598 },
60599/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60600 {
60601 { 0, 0, 0, 0 },
60602 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60603 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xc00e0000 }
60604 },
60605/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60606 {
60607 { 0, 0, 0, 0 },
60608 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60609 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xc04e0000 }
60610 },
60611/* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60612 {
60613 { 0, 0, 0, 0 },
60614 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60615 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xc06e0000 }
60616 },
60617/* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60618 {
60619 { 0, 0, 0, 0 },
60620 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60621 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xc00b00 }
60622 },
60623/* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60624 {
60625 { 0, 0, 0, 0 },
60626 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60627 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xc04b00 }
60628 },
60629/* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60630 {
60631 { 0, 0, 0, 0 },
60632 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60633 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xc06b00 }
60634 },
60635/* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
60636 {
60637 { 0, 0, 0, 0 },
60638 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
60639 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xc00f0000 }
60640 },
60641/* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
60642 {
60643 { 0, 0, 0, 0 },
60644 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
60645 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xc04f0000 }
60646 },
60647/* cmp.b${G} [$Src16An],${Dsp-16-u16} */
60648 {
60649 { 0, 0, 0, 0 },
60650 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
60651 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xc06f0000 }
60652 },
60653/* cmp.b${S} #${Imm-8-QI},r0l */
60654 {
60655 { 0, 0, 0, 0 },
60656 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
60657 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xe400 }
60658 },
60659/* cmp.b${S} #${Imm-8-QI},r0h */
60660 {
60661 { 0, 0, 0, 0 },
60662 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
60663 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xe300 }
60664 },
60665/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60666 {
60667 { 0, 0, 0, 0 },
60668 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60669 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xe50000 }
60670 },
60671/* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60672 {
60673 { 0, 0, 0, 0 },
60674 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60675 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xe60000 }
60676 },
60677/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60678 {
60679 { 0, 0, 0, 0 },
60680 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
60681 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xe7000000 }
60682 },
60683/* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60684 {
60685 { 0, 0, 0, 0 },
60686 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
60687 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe910 }
60688 },
60689/* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60690 {
60691 { 0, 0, 0, 0 },
60692 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
60693 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe190 }
60694 },
60695/* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60696 {
60697 { 0, 0, 0, 0 },
60698 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60699 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe110 }
60700 },
60701/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60702 {
60703 { 0, 0, 0, 0 },
60704 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60705 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe31000 }
60706 },
60707/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60708 {
60709 { 0, 0, 0, 0 },
60710 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60711 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5100000 }
60712 },
60713/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60714 {
60715 { 0, 0, 0, 0 },
60716 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60717 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7100000 }
60718 },
60719/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60720 {
60721 { 0, 0, 0, 0 },
60722 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60723 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe39000 }
60724 },
60725/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60726 {
60727 { 0, 0, 0, 0 },
60728 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60729 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5900000 }
60730 },
60731/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60732 {
60733 { 0, 0, 0, 0 },
60734 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60735 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3d000 }
60736 },
60737/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60738 {
60739 { 0, 0, 0, 0 },
60740 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60741 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5d00000 }
60742 },
60743/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
60744 {
60745 { 0, 0, 0, 0 },
60746 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
60747 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7d00000 }
60748 },
60749/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
60750 {
60751 { 0, 0, 0, 0 },
60752 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
60753 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7900000 }
60754 },
60755/* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
60756 {
60757 { 0, 0, 0, 0 },
60758 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
60759 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe810 }
60760 },
60761/* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
60762 {
60763 { 0, 0, 0, 0 },
60764 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
60765 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe090 }
60766 },
60767/* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60768 {
60769 { 0, 0, 0, 0 },
60770 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60771 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe010 }
60772 },
60773/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60774 {
60775 { 0, 0, 0, 0 },
60776 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60777 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe21000 }
60778 },
60779/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60780 {
60781 { 0, 0, 0, 0 },
60782 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60783 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4100000 }
60784 },
60785/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60786 {
60787 { 0, 0, 0, 0 },
60788 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60789 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6100000 }
60790 },
60791/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60792 {
60793 { 0, 0, 0, 0 },
60794 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60795 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe29000 }
60796 },
60797/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60798 {
60799 { 0, 0, 0, 0 },
60800 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60801 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4900000 }
60802 },
60803/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60804 {
60805 { 0, 0, 0, 0 },
60806 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60807 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2d000 }
60808 },
60809/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60810 {
60811 { 0, 0, 0, 0 },
60812 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60813 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4d00000 }
60814 },
60815/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
60816 {
60817 { 0, 0, 0, 0 },
60818 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
60819 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6d00000 }
60820 },
60821/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
60822 {
60823 { 0, 0, 0, 0 },
60824 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
60825 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6900000 }
60826 },
60827/* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
60828 {
60829 { 0, 0, 0, 0 },
60830 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
db313fa6 60831 & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd100 }
49f58d10
JB		 60832 },
60833/* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
60834 {
60835 { 0, 0, 0, 0 },
60836 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
db313fa6 60837 & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd104 }
49f58d10
JB		 60838 },
60839/* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
60840 {
60841 { 0, 0, 0, 0 },
60842 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
db313fa6 60843 & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd106 }
49f58d10
JB		 60844 },
60845/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60846 {
60847 { 0, 0, 0, 0 },
60848 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
db313fa6 60849 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd10800 }
49f58d10
JB		 60850 },
60851/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60852 {
60853 { 0, 0, 0, 0 },
60854 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
db313fa6 60855 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd10c0000 }
49f58d10
JB		 60856 },
60857/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60858 {
60859 { 0, 0, 0, 0 },
60860 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
db313fa6 60861 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd10a00 }
49f58d10
JB		 60862 },
60863/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60864 {
60865 { 0, 0, 0, 0 },
60866 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
db313fa6 60867 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd10e0000 }
49f58d10
JB		 60868 },
60869/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60870 {
60871 { 0, 0, 0, 0 },
60872 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
db313fa6 60873 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd10b00 }
49f58d10
JB		 60874 },
60875/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
60876 {
60877 { 0, 0, 0, 0 },
60878 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
db313fa6 60879 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd10f0000 }
49f58d10
JB		 60880 },
60881/* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
60882 {
60883 { 0, 0, 0, 0 },
60884 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
db313fa6 60885 & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xd000 }
49f58d10
JB		 60886 },
60887/* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
60888 {
60889 { 0, 0, 0, 0 },
60890 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
db313fa6 60891 & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xd004 }
49f58d10
JB		 60892 },
60893/* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
60894 {
60895 { 0, 0, 0, 0 },
60896 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
db313fa6 60897 & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xd006 }
49f58d10
JB		 60898 },
60899/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60900 {
60901 { 0, 0, 0, 0 },
60902 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
db313fa6 60903 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd00800 }
49f58d10
JB		 60904 },
60905/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60906 {
60907 { 0, 0, 0, 0 },
60908 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
db313fa6 60909 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd00c0000 }
49f58d10
JB		 60910 },
60911/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60912 {
60913 { 0, 0, 0, 0 },
60914 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
db313fa6 60915 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd00a00 }
49f58d10
JB		 60916 },
60917/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60918 {
60919 { 0, 0, 0, 0 },
60920 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
db313fa6 60921 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd00e0000 }
49f58d10
JB		 60922 },
60923/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60924 {
60925 { 0, 0, 0, 0 },
60926 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
db313fa6 60927 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd00b00 }
49f58d10
JB		 60928 },
60929/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
60930 {
60931 { 0, 0, 0, 0 },
60932 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
db313fa6 60933 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd00f0000 }
49f58d10
JB		 60934 },
60935/* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
60936 {
60937 { 0, 0, 0, 0 },
60938 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
60939 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992e0000 }
60940 },
60941/* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
60942 {
60943 { 0, 0, 0, 0 },
60944 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
60945 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91ae0000 }
60946 },
60947/* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
60948 {
60949 { 0, 0, 0, 0 },
60950 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60951 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912e0000 }
60952 },
60953/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60954 {
60955 { 0, 0, 0, 0 },
60956 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60957 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932e0000 }
60958 },
60959/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
60960 {
60961 { 0, 0, 0, 0 },
60962 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60963 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93ae0000 }
60964 },
60965/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
60966 {
60967 { 0, 0, 0, 0 },
60968 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60969 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ee0000 }
60970 },
60971/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60972 {
60973 { 0, 0, 0, 0 },
60974 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60975 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952e0000 }
60976 },
60977/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
60978 {
60979 { 0, 0, 0, 0 },
60980 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60981 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95ae0000 }
60982 },
60983/* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
60984 {
60985 { 0, 0, 0, 0 },
60986 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60987 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ee0000 }
60988 },
60989/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
60990 {
60991 { 0, 0, 0, 0 },
60992 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
60993 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ee0000 }
60994 },
60995/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60996 {
60997 { 0, 0, 0, 0 },
60998 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60999 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972e0000 }
61000 },
61001/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
61002 {
61003 { 0, 0, 0, 0 },
61004 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
61005 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97ae0000 }
61006 },
61007/* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
61008 {
61009 { 0, 0, 0, 0 },
61010 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
61011 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982e00 }
61012 },
61013/* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
61014 {
61015 { 0, 0, 0, 0 },
61016 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
61017 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90ae00 }
61018 },
61019/* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
61020 {
61021 { 0, 0, 0, 0 },
61022 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61023 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902e00 }
61024 },
61025/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61026 {
61027 { 0, 0, 0, 0 },
61028 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61029 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922e0000 }
61030 },
61031/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61032 {
61033 { 0, 0, 0, 0 },
61034 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61035 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92ae0000 }
61036 },
61037/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61038 {
61039 { 0, 0, 0, 0 },
61040 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61041 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ee0000 }
61042 },
61043/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61044 {
61045 { 0, 0, 0, 0 },
61046 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61047 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942e0000 }
61048 },
61049/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61050 {
61051 { 0, 0, 0, 0 },
61052 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61053 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94ae0000 }
61054 },
61055/* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
61056 {
61057 { 0, 0, 0, 0 },
61058 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
61059 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ee0000 }
61060 },
61061/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61062 {
61063 { 0, 0, 0, 0 },
61064 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
61065 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ee0000 }
61066 },
61067/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61068 {
61069 { 0, 0, 0, 0 },
61070 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61071 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962e0000 }
61072 },
61073/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
61074 {
61075 { 0, 0, 0, 0 },
61076 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
61077 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96ae0000 }
61078 },
61079/* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
61080 {
61081 { 0, 0, 0, 0 },
61082 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
61083 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77800000 }
61084 },
61085/* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
61086 {
61087 { 0, 0, 0, 0 },
61088 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
61089 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77840000 }
61090 },
61091/* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
61092 {
61093 { 0, 0, 0, 0 },
61094 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
61095 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77860000 }
61096 },
61097/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
61098 {
61099 { 0, 0, 0, 0 },
61100 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
61101 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77880000 }
61102 },
61103/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61104 {
61105 { 0, 0, 0, 0 },
61106 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61107 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x778a0000 }
61108 },
61109/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61110 {
61111 { 0, 0, 0, 0 },
61112 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61113 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x778b0000 }
61114 },
61115/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
61116 {
61117 { 0, 0, 0, 0 },
61118 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
61119 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x778c0000 }
61120 },
61121/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61122 {
61123 { 0, 0, 0, 0 },
61124 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61125 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x778e0000 }
61126 },
61127/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61128 {
61129 { 0, 0, 0, 0 },
61130 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
61131 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x778f0000 }
61132 },
61133/* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
61134 {
61135 { 0, 0, 0, 0 },
61136 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
61137 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x768000 }
61138 },
61139/* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
61140 {
61141 { 0, 0, 0, 0 },
61142 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
61143 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x768400 }
61144 },
61145/* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
61146 {
61147 { 0, 0, 0, 0 },
61148 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
61149 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x768600 }
61150 },
61151/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
61152 {
61153 { 0, 0, 0, 0 },
61154 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
61155 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76880000 }
61156 },
61157/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61158 {
61159 { 0, 0, 0, 0 },
61160 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61161 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x768a0000 }
61162 },
61163/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61164 {
61165 { 0, 0, 0, 0 },
61166 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61167 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x768b0000 }
61168 },
61169/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
61170 {
61171 { 0, 0, 0, 0 },
61172 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
61173 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x768c0000 }
61174 },
61175/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61176 {
61177 { 0, 0, 0, 0 },
61178 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61179 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x768e0000 }
61180 },
61181/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61182 {
61183 { 0, 0, 0, 0 },
61184 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
61185 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x768f0000 }
61186 },
61187/* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
61188 {
61189 { 0, 0, 0, 0 },
61190 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
61191 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa8310000 }
61192 },
61193/* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
61194 {
61195 { 0, 0, 0, 0 },
61196 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
61197 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0b10000 }
61198 },
61199/* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
61200 {
61201 { 0, 0, 0, 0 },
61202 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61203 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa0310000 }
61204 },
61205/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61206 {
61207 { 0, 0, 0, 0 },
61208 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61209 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2310000 }
61210 },
61211/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
61212 {
61213 { 0, 0, 0, 0 },
61214 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61215 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2b10000 }
61216 },
61217/* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
61218 {
61219 { 0, 0, 0, 0 },
61220 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61221 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2f10000 }
61222 },
61223/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61224 {
61225 { 0, 0, 0, 0 },
61226 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61227 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4310000 }
61228 },
61229/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
61230 {
61231 { 0, 0, 0, 0 },
61232 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61233 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4b10000 }
61234 },
61235/* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
61236 {
61237 { 0, 0, 0, 0 },
61238 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
61239 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4f10000 }
61240 },
61241/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
61242 {
61243 { 0, 0, 0, 0 },
61244 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
61245 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6f10000 }
61246 },
61247/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61248 {
61249 { 0, 0, 0, 0 },
61250 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61251 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6310000 }
61252 },
61253/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
61254 {
61255 { 0, 0, 0, 0 },
61256 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
61257 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6b10000 }
61258 },
61259/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
61260 {
61261 { 0, 0, 0, 0 },
61262 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
61263 & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893e00 }
61264 },
61265/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
61266 {
61267 { 0, 0, 0, 0 },
61268 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
61269 & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181be00 }
61270 },
61271/* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
61272 {
61273 { 0, 0, 0, 0 },
61274 { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
61275 & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813e00 }
61276 },
61277/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
61278 {
61279 { 0, 0, 0, 0 },
61280 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
61281 & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833e00 }
61282 },
61283/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
61284 {
61285 { 0, 0, 0, 0 },
61286 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
61287 & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183be00 }
61288 },
61289/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
61290 {
61291 { 0, 0, 0, 0 },
61292 { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
61293 & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183fe00 }
61294 },
61295/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
61296 {
61297 { 0, 0, 0, 0 },
61298 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
61299 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853e00 }
61300 },
61301/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
61302 {
61303 { 0, 0, 0, 0 },
61304 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
61305 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185be00 }
61306 },
61307/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
61308 {
61309 { 0, 0, 0, 0 },
61310 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
61311 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185fe00 }
61312 },
61313/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
61314 {
61315 { 0, 0, 0, 0 },
61316 { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), 0 } },
61317 & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187fe00 }
61318 },
61319/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
61320 {
61321 { 0, 0, 0, 0 },
61322 { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
61323 & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873e00 }
61324 },
61325/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
61326 {
61327 { 0, 0, 0, 0 },
61328 { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), 0 } },
61329 & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187be00 }
61330 },
61331/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
61332 {
61333 { 0, 0, 0, 0 },
61334 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
61335 & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883e00 }
61336 },
61337/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
61338 {
61339 { 0, 0, 0, 0 },
61340 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
61341 & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180be00 }
61342 },
61343/* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
61344 {
61345 { 0, 0, 0, 0 },
61346 { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
61347 & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803e00 }
61348 },
61349/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
61350 {
61351 { 0, 0, 0, 0 },
61352 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
61353 & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823e00 }
61354 },
61355/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
61356 {
61357 { 0, 0, 0, 0 },
61358 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
61359 & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182be00 }
61360 },
61361/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
61362 {
61363 { 0, 0, 0, 0 },
61364 { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
61365 & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182fe00 }
61366 },
61367/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
61368 {
61369 { 0, 0, 0, 0 },
61370 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
61371 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843e00 }
61372 },
61373/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
61374 {
61375 { 0, 0, 0, 0 },
61376 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
61377 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184be00 }
61378 },
61379/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
61380 {
61381 { 0, 0, 0, 0 },
61382 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
61383 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184fe00 }
61384 },
61385/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
61386 {
61387 { 0, 0, 0, 0 },
61388 { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), 0 } },
61389 & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186fe00 }
61390 },
61391/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
61392 {
61393 { 0, 0, 0, 0 },
61394 { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
61395 & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863e00 }
61396 },
61397/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
61398 {
61399 { 0, 0, 0, 0 },
61400 { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), 0 } },
61401 & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186be00 }
61402 },
61403/* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
61404 {
61405 { 0, 0, 0, 0 },
61406 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
61407 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d828 }
61408 },
61409/* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
61410 {
61411 { 0, 0, 0, 0 },
61412 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
61413 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a8 }
61414 },
61415/* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
61416 {
61417 { 0, 0, 0, 0 },
61418 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
61419 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d028 }
61420 },
61421/* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
61422 {
61423 { 0, 0, 0, 0 },
61424 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61425 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22800 }
61426 },
61427/* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
61428 {
61429 { 0, 0, 0, 0 },
61430 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61431 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42800 }
61432 },
61433/* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
61434 {
61435 { 0, 0, 0, 0 },
61436 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61437 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62800 }
61438 },
61439/* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
61440 {
61441 { 0, 0, 0, 0 },
61442 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
61443 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a800 }
61444 },
61445/* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
61446 {
61447 { 0, 0, 0, 0 },
61448 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
61449 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a800 }
61450 },
61451/* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
61452 {
61453 { 0, 0, 0, 0 },
61454 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
61455 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e800 }
61456 },
61457/* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
61458 {
61459 { 0, 0, 0, 0 },
61460 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
61461 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e800 }
61462 },
61463/* bxor${X} ${BitBase32-24-u19-Prefixed} */
61464 {
61465 { 0, 0, 0, 0 },
61466 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
61467 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e800 }
61468 },
61469/* bxor${X} ${BitBase32-24-u27-Prefixed} */
61470 {
61471 { 0, 0, 0, 0 },
61472 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
61473 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a800 }
61474 },
61475/* bxor${X} $Bitno16R,$Bit16Rn */
61476 {
61477 { 0, 0, 0, 0 },
61478 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61479 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ec000 }
61480 },
61481/* bxor${X} $Bitno16R,$Bit16An */
61482 {
61483 { 0, 0, 0, 0 },
61484 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61485 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ec400 }
61486 },
61487/* bxor${X} [$Bit16An] */
61488 {
61489 { 0, 0, 0, 0 },
61490 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61491 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ec6 }
61492 },
61493/* bxor${X} ${Dsp-16-u8}[$Bit16An] */
61494 {
61495 { 0, 0, 0, 0 },
61496 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61497 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ec800 }
61498 },
61499/* bxor${X} ${Dsp-16-u16}[$Bit16An] */
61500 {
61501 { 0, 0, 0, 0 },
61502 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61503 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ecc0000 }
61504 },
61505/* bxor${X} ${BitBase16-16-u8}[sb] */
61506 {
61507 { 0, 0, 0, 0 },
61508 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61509 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eca00 }
61510 },
61511/* bxor${X} ${BitBase16-16-u16}[sb] */
61512 {
61513 { 0, 0, 0, 0 },
61514 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61515 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ece0000 }
61516 },
61517/* bxor${X} ${BitBase16-16-s8}[fb] */
61518 {
61519 { 0, 0, 0, 0 },
61520 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61521 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ecb00 }
61522 },
61523/* bxor${X} ${BitBase16-16-u16} */
61524 {
61525 { 0, 0, 0, 0 },
61526 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61527 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ecf0000 }
61528 },
61529/* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61530 {
61531 { 0, 0, 0, 0 },
61532 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61533 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd828 }
61534 },
61535/* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61536 {
61537 { 0, 0, 0, 0 },
61538 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61539 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a8 }
61540 },
61541/* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61542 {
61543 { 0, 0, 0, 0 },
61544 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61545 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd028 }
61546 },
61547/* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61548 {
61549 { 0, 0, 0, 0 },
61550 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61551 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22800 }
61552 },
61553/* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61554 {
61555 { 0, 0, 0, 0 },
61556 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61557 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4280000 }
61558 },
61559/* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61560 {
61561 { 0, 0, 0, 0 },
61562 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61563 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6280000 }
61564 },
61565/* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61566 {
61567 { 0, 0, 0, 0 },
61568 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61569 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a800 }
61570 },
61571/* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61572 {
61573 { 0, 0, 0, 0 },
61574 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61575 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a80000 }
61576 },
61577/* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61578 {
61579 { 0, 0, 0, 0 },
61580 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61581 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e800 }
61582 },
61583/* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61584 {
61585 { 0, 0, 0, 0 },
61586 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61587 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e80000 }
61588 },
61589/* btsts${X} ${BitBase32-16-u19-Unprefixed} */
61590 {
61591 { 0, 0, 0, 0 },
61592 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61593 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e80000 }
61594 },
61595/* btsts${X} ${BitBase32-16-u27-Unprefixed} */
61596 {
61597 { 0, 0, 0, 0 },
61598 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61599 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a80000 }
61600 },
61601/* btsts${X} $Bitno16R,$Bit16Rn */
61602 {
61603 { 0, 0, 0, 0 },
61604 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61605 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e1000 }
61606 },
61607/* btsts${X} $Bitno16R,$Bit16An */
61608 {
61609 { 0, 0, 0, 0 },
61610 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61611 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e1400 }
61612 },
61613/* btsts${X} [$Bit16An] */
61614 {
61615 { 0, 0, 0, 0 },
61616 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61617 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e16 }
61618 },
61619/* btsts${X} ${Dsp-16-u8}[$Bit16An] */
61620 {
61621 { 0, 0, 0, 0 },
61622 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61623 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e1800 }
61624 },
61625/* btsts${X} ${Dsp-16-u16}[$Bit16An] */
61626 {
61627 { 0, 0, 0, 0 },
61628 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61629 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e1c0000 }
61630 },
61631/* btsts${X} ${BitBase16-16-u8}[sb] */
61632 {
61633 { 0, 0, 0, 0 },
61634 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61635 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e1a00 }
61636 },
61637/* btsts${X} ${BitBase16-16-u16}[sb] */
61638 {
61639 { 0, 0, 0, 0 },
61640 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61641 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e1e0000 }
61642 },
61643/* btsts${X} ${BitBase16-16-s8}[fb] */
61644 {
61645 { 0, 0, 0, 0 },
61646 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61647 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e1b00 }
61648 },
61649/* btsts${X} ${BitBase16-16-u16} */
61650 {
61651 { 0, 0, 0, 0 },
61652 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61653 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e1f0000 }
61654 },
61655/* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61656 {
61657 { 0, 0, 0, 0 },
61658 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61659 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd820 }
61660 },
61661/* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61662 {
61663 { 0, 0, 0, 0 },
61664 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61665 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a0 }
61666 },
61667/* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61668 {
61669 { 0, 0, 0, 0 },
61670 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61671 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd020 }
61672 },
61673/* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61674 {
61675 { 0, 0, 0, 0 },
61676 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61677 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22000 }
61678 },
61679/* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61680 {
61681 { 0, 0, 0, 0 },
61682 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61683 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4200000 }
61684 },
61685/* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61686 {
61687 { 0, 0, 0, 0 },
61688 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61689 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6200000 }
61690 },
61691/* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61692 {
61693 { 0, 0, 0, 0 },
61694 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61695 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a000 }
61696 },
61697/* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61698 {
61699 { 0, 0, 0, 0 },
61700 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61701 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a00000 }
61702 },
61703/* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61704 {
61705 { 0, 0, 0, 0 },
61706 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61707 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e000 }
61708 },
61709/* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61710 {
61711 { 0, 0, 0, 0 },
61712 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61713 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e00000 }
61714 },
61715/* btstc${X} ${BitBase32-16-u19-Unprefixed} */
61716 {
61717 { 0, 0, 0, 0 },
61718 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61719 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e00000 }
61720 },
61721/* btstc${X} ${BitBase32-16-u27-Unprefixed} */
61722 {
61723 { 0, 0, 0, 0 },
61724 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61725 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a00000 }
61726 },
61727/* btstc${X} $Bitno16R,$Bit16Rn */
61728 {
61729 { 0, 0, 0, 0 },
61730 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61731 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e0000 }
61732 },
61733/* btstc${X} $Bitno16R,$Bit16An */
61734 {
61735 { 0, 0, 0, 0 },
61736 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61737 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e0400 }
61738 },
61739/* btstc${X} [$Bit16An] */
61740 {
61741 { 0, 0, 0, 0 },
61742 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61743 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e06 }
61744 },
61745/* btstc${X} ${Dsp-16-u8}[$Bit16An] */
61746 {
61747 { 0, 0, 0, 0 },
61748 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61749 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e0800 }
61750 },
61751/* btstc${X} ${Dsp-16-u16}[$Bit16An] */
61752 {
61753 { 0, 0, 0, 0 },
61754 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61755 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e0c0000 }
61756 },
61757/* btstc${X} ${BitBase16-16-u8}[sb] */
61758 {
61759 { 0, 0, 0, 0 },
61760 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61761 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e0a00 }
61762 },
61763/* btstc${X} ${BitBase16-16-u16}[sb] */
61764 {
61765 { 0, 0, 0, 0 },
61766 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61767 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e0e0000 }
61768 },
61769/* btstc${X} ${BitBase16-16-s8}[fb] */
61770 {
61771 { 0, 0, 0, 0 },
61772 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61773 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e0b00 }
61774 },
61775/* btstc${X} ${BitBase16-16-u16} */
61776 {
61777 { 0, 0, 0, 0 },
61778 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61779 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e0f0000 }
61780 },
5348b81e 61781/* btst${G} $Bitno32Unprefixed,$Bit32RnUnprefixed */
49f58d10
JB		 61782 {
61783 { 0, 0, 0, 0 },
5348b81e 61784 { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
49f58d10
JB		 61785 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd800 }
61786 },
5348b81e 61787/* btst${G} $Bitno32Unprefixed,$Bit32AnUnprefixed */
49f58d10
JB		 61788 {
61789 { 0, 0, 0, 0 },
5348b81e 61790 { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
49f58d10
JB		 61791 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd080 }
61792 },
5348b81e 61793/* btst${G} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
49f58d10
JB		 61794 {
61795 { 0, 0, 0, 0 },
5348b81e 61796 { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 61797 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd000 }
61798 },
5348b81e 61799/* btst${G} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
49f58d10
JB		 61800 {
61801 { 0, 0, 0, 0 },
5348b81e 61802 { { MNEM, OP (G), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 61803 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd20000 }
61804 },
5348b81e 61805/* btst${G} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
49f58d10
JB		 61806 {
61807 { 0, 0, 0, 0 },
5348b81e 61808 { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 61809 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4000000 }
61810 },
5348b81e 61811/* btst${G} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
49f58d10
JB		 61812 {
61813 { 0, 0, 0, 0 },
5348b81e 61814 { { MNEM, OP (G), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
49f58d10
JB		 61815 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6000000 }
61816 },
5348b81e 61817/* btst${G} ${BitBase32-16-u11-Unprefixed}[sb] */
49f58d10
JB		 61818 {
61819 { 0, 0, 0, 0 },
5348b81e 61820 { { MNEM, OP (G), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 61821 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd28000 }
61822 },
5348b81e 61823/* btst${G} ${BitBase32-16-u19-Unprefixed}[sb] */
49f58d10
JB		 61824 {
61825 { 0, 0, 0, 0 },
5348b81e 61826 { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 61827 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4800000 }
61828 },
5348b81e 61829/* btst${G} ${BitBase32-16-s11-Unprefixed}[fb] */
49f58d10
JB		 61830 {
61831 { 0, 0, 0, 0 },
5348b81e 61832 { { MNEM, OP (G), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 61833 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2c000 }
61834 },
5348b81e 61835/* btst${G} ${BitBase32-16-s19-Unprefixed}[fb] */
49f58d10
JB		 61836 {
61837 { 0, 0, 0, 0 },
5348b81e 61838 { { MNEM, OP (G), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
49f58d10
JB		 61839 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4c00000 }
61840 },
5348b81e 61841/* btst${G} ${BitBase32-16-u19-Unprefixed} */
49f58d10
JB		 61842 {
61843 { 0, 0, 0, 0 },
5348b81e 61844 { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
49f58d10
JB		 61845 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6c00000 }
61846 },
5348b81e 61847/* btst${G} ${BitBase32-16-u27-Unprefixed} */
49f58d10
JB		 61848 {
61849 { 0, 0, 0, 0 },
5348b81e 61850 { { MNEM, OP (G), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
49f58d10
JB		 61851 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6800000 }
61852 },
61853/* btst${G} $Bitno16R,$Bit16Rn */
61854 {
61855 { 0, 0, 0, 0 },
61856 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61857 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7eb000 }
61858 },
61859/* btst${G} $Bitno16R,$Bit16An */
61860 {
61861 { 0, 0, 0, 0 },
61862 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61863 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7eb400 }
61864 },
61865/* btst${G} ${Dsp-16-u8}[$Bit16An] */
61866 {
61867 { 0, 0, 0, 0 },
61868 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61869 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7eb800 }
61870 },
61871/* btst${G} ${BitBase16-16-u8}[sb] */
61872 {
61873 { 0, 0, 0, 0 },
61874 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61875 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eba00 }
61876 },
61877/* btst${G} ${BitBase16-16-s8}[fb] */
61878 {
61879 { 0, 0, 0, 0 },
61880 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61881 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ebb00 }
61882 },
61883/* btst${S} ${BitBase16-8-u11-S}[sb] */
61884 {
61885 { 0, 0, 0, 0 },
61886 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
61887 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5800 }
61888 },
61889/* btst${G} ${Dsp-16-u16}[$Bit16An] */
61890 {
61891 { 0, 0, 0, 0 },
61892 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61893 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ebc0000 }
61894 },
61895/* btst${G} ${BitBase16-16-u16}[sb] */
61896 {
61897 { 0, 0, 0, 0 },
61898 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61899 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ebe0000 }
61900 },
61901/* btst${G} ${BitBase16-16-u16} */
61902 {
61903 { 0, 0, 0, 0 },
61904 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
61905 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ebf0000 }
61906 },
61907/* btst${G} [$Bit16An] */
61908 {
61909 { 0, 0, 0, 0 },
61910 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
61911 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7eb6 }
61912 },
61913/* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61914 {
61915 { 0, 0, 0, 0 },
61916 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61917 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd838 }
61918 },
61919/* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61920 {
61921 { 0, 0, 0, 0 },
61922 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61923 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b8 }
61924 },
61925/* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61926 {
61927 { 0, 0, 0, 0 },
61928 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61929 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd038 }
61930 },
61931/* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61932 {
61933 { 0, 0, 0, 0 },
61934 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61935 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23800 }
61936 },
61937/* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61938 {
61939 { 0, 0, 0, 0 },
61940 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61941 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4380000 }
61942 },
61943/* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61944 {
61945 { 0, 0, 0, 0 },
61946 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61947 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6380000 }
61948 },
61949/* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61950 {
61951 { 0, 0, 0, 0 },
61952 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61953 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b800 }
61954 },
61955/* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61956 {
61957 { 0, 0, 0, 0 },
61958 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61959 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b80000 }
61960 },
61961/* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61962 {
61963 { 0, 0, 0, 0 },
61964 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61965 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f800 }
61966 },
61967/* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61968 {
61969 { 0, 0, 0, 0 },
61970 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61971 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f80000 }
61972 },
61973/* bset${X} ${BitBase32-16-u19-Unprefixed} */
61974 {
61975 { 0, 0, 0, 0 },
61976 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61977 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f80000 }
61978 },
61979/* bset${X} ${BitBase32-16-u27-Unprefixed} */
61980 {
61981 { 0, 0, 0, 0 },
61982 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61983 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b80000 }
61984 },
61985/* bset${G} $Bitno16R,$Bit16Rn */
61986 {
61987 { 0, 0, 0, 0 },
61988 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61989 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e9000 }
61990 },
61991/* bset${G} $Bitno16R,$Bit16An */
61992 {
61993 { 0, 0, 0, 0 },
61994 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61995 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e9400 }
61996 },
61997/* bset${G} ${Dsp-16-u8}[$Bit16An] */
61998 {
61999 { 0, 0, 0, 0 },
62000 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62001 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e9800 }
62002 },
62003/* bset${G} ${BitBase16-16-u8}[sb] */
62004 {
62005 { 0, 0, 0, 0 },
62006 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62007 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e9a00 }
62008 },
62009/* bset${G} ${BitBase16-16-s8}[fb] */
62010 {
62011 { 0, 0, 0, 0 },
62012 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62013 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e9b00 }
62014 },
62015/* bset${S} ${BitBase16-8-u11-S}[sb] */
62016 {
62017 { 0, 0, 0, 0 },
62018 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
62019 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4800 }
62020 },
62021/* bset${G} ${Dsp-16-u16}[$Bit16An] */
62022 {
62023 { 0, 0, 0, 0 },
62024 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62025 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e9c0000 }
62026 },
62027/* bset${G} ${BitBase16-16-u16}[sb] */
62028 {
62029 { 0, 0, 0, 0 },
62030 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62031 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e9e0000 }
62032 },
62033/* bset${G} ${BitBase16-16-u16} */
62034 {
62035 { 0, 0, 0, 0 },
62036 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
62037 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e9f0000 }
62038 },
62039/* bset${G} [$Bit16An] */
62040 {
62041 { 0, 0, 0, 0 },
62042 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
62043 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e96 }
62044 },
62045/* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62046 {
62047 { 0, 0, 0, 0 },
62048 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62049 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d820 }
62050 },
62051/* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62052 {
62053 { 0, 0, 0, 0 },
62054 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62055 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a0 }
62056 },
62057/* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62058 {
62059 { 0, 0, 0, 0 },
62060 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62061 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d020 }
62062 },
62063/* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62064 {
62065 { 0, 0, 0, 0 },
62066 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62067 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22000 }
62068 },
62069/* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62070 {
62071 { 0, 0, 0, 0 },
62072 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62073 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42000 }
62074 },
62075/* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62076 {
62077 { 0, 0, 0, 0 },
62078 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62079 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62000 }
62080 },
62081/* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
62082 {
62083 { 0, 0, 0, 0 },
62084 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62085 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a000 }
62086 },
62087/* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
62088 {
62089 { 0, 0, 0, 0 },
62090 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62091 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a000 }
62092 },
62093/* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
62094 {
62095 { 0, 0, 0, 0 },
62096 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62097 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e000 }
62098 },
62099/* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
62100 {
62101 { 0, 0, 0, 0 },
62102 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62103 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e000 }
62104 },
62105/* bor${X} ${BitBase32-24-u19-Prefixed} */
62106 {
62107 { 0, 0, 0, 0 },
62108 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62109 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e000 }
62110 },
62111/* bor${X} ${BitBase32-24-u27-Prefixed} */
62112 {
62113 { 0, 0, 0, 0 },
62114 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62115 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a000 }
62116 },
62117/* bor${X} $Bitno16R,$Bit16Rn */
62118 {
62119 { 0, 0, 0, 0 },
62120 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62121 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e6000 }
62122 },
62123/* bor${X} $Bitno16R,$Bit16An */
62124 {
62125 { 0, 0, 0, 0 },
62126 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62127 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e6400 }
62128 },
62129/* bor${X} [$Bit16An] */
62130 {
62131 { 0, 0, 0, 0 },
62132 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62133 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e66 }
62134 },
62135/* bor${X} ${Dsp-16-u8}[$Bit16An] */
62136 {
62137 { 0, 0, 0, 0 },
62138 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62139 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e6800 }
62140 },
62141/* bor${X} ${Dsp-16-u16}[$Bit16An] */
62142 {
62143 { 0, 0, 0, 0 },
62144 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62145 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e6c0000 }
62146 },
62147/* bor${X} ${BitBase16-16-u8}[sb] */
62148 {
62149 { 0, 0, 0, 0 },
62150 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62151 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e6a00 }
62152 },
62153/* bor${X} ${BitBase16-16-u16}[sb] */
62154 {
62155 { 0, 0, 0, 0 },
62156 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62157 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e6e0000 }
62158 },
62159/* bor${X} ${BitBase16-16-s8}[fb] */
62160 {
62161 { 0, 0, 0, 0 },
62162 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62163 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e6b00 }
62164 },
62165/* bor${X} ${BitBase16-16-u16} */
62166 {
62167 { 0, 0, 0, 0 },
62168 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62169 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e6f0000 }
62170 },
62171/* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62172 {
62173 { 0, 0, 0, 0 },
62174 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62175 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d838 }
62176 },
62177/* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62178 {
62179 { 0, 0, 0, 0 },
62180 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62181 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b8 }
62182 },
62183/* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62184 {
62185 { 0, 0, 0, 0 },
62186 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62187 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d038 }
62188 },
62189/* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62190 {
62191 { 0, 0, 0, 0 },
62192 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62193 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23800 }
62194 },
62195/* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62196 {
62197 { 0, 0, 0, 0 },
62198 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62199 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43800 }
62200 },
62201/* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62202 {
62203 { 0, 0, 0, 0 },
62204 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62205 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63800 }
62206 },
62207/* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
62208 {
62209 { 0, 0, 0, 0 },
62210 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62211 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b800 }
62212 },
62213/* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
62214 {
62215 { 0, 0, 0, 0 },
62216 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62217 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b800 }
62218 },
62219/* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
62220 {
62221 { 0, 0, 0, 0 },
62222 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62223 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f800 }
62224 },
62225/* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
62226 {
62227 { 0, 0, 0, 0 },
62228 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62229 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f800 }
62230 },
62231/* bnxor${X} ${BitBase32-24-u19-Prefixed} */
62232 {
62233 { 0, 0, 0, 0 },
62234 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62235 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f800 }
62236 },
62237/* bnxor${X} ${BitBase32-24-u27-Prefixed} */
62238 {
62239 { 0, 0, 0, 0 },
62240 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62241 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b800 }
62242 },
62243/* bnxor${X} $Bitno16R,$Bit16Rn */
62244 {
62245 { 0, 0, 0, 0 },
62246 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62247 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ed000 }
62248 },
62249/* bnxor${X} $Bitno16R,$Bit16An */
62250 {
62251 { 0, 0, 0, 0 },
62252 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62253 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ed400 }
62254 },
62255/* bnxor${X} [$Bit16An] */
62256 {
62257 { 0, 0, 0, 0 },
62258 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62259 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ed6 }
62260 },
62261/* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
62262 {
62263 { 0, 0, 0, 0 },
62264 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62265 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ed800 }
62266 },
62267/* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
62268 {
62269 { 0, 0, 0, 0 },
62270 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62271 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7edc0000 }
62272 },
62273/* bnxor${X} ${BitBase16-16-u8}[sb] */
62274 {
62275 { 0, 0, 0, 0 },
62276 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62277 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eda00 }
62278 },
62279/* bnxor${X} ${BitBase16-16-u16}[sb] */
62280 {
62281 { 0, 0, 0, 0 },
62282 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62283 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ede0000 }
62284 },
62285/* bnxor${X} ${BitBase16-16-s8}[fb] */
62286 {
62287 { 0, 0, 0, 0 },
62288 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62289 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7edb00 }
62290 },
62291/* bnxor${X} ${BitBase16-16-u16} */
62292 {
62293 { 0, 0, 0, 0 },
62294 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62295 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7edf0000 }
62296 },
62297/* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62298 {
62299 { 0, 0, 0, 0 },
62300 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62301 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d800 }
62302 },
62303/* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62304 {
62305 { 0, 0, 0, 0 },
62306 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62307 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d080 }
62308 },
62309/* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62310 {
62311 { 0, 0, 0, 0 },
62312 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62313 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d000 }
62314 },
62315/* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62316 {
62317 { 0, 0, 0, 0 },
62318 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62319 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20000 }
62320 },
62321/* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62322 {
62323 { 0, 0, 0, 0 },
62324 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62325 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40000 }
62326 },
62327/* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62328 {
62329 { 0, 0, 0, 0 },
62330 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62331 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60000 }
62332 },
62333/* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
62334 {
62335 { 0, 0, 0, 0 },
62336 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62337 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28000 }
62338 },
62339/* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
62340 {
62341 { 0, 0, 0, 0 },
62342 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62343 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48000 }
62344 },
62345/* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
62346 {
62347 { 0, 0, 0, 0 },
62348 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62349 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c000 }
62350 },
62351/* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
62352 {
62353 { 0, 0, 0, 0 },
62354 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62355 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c000 }
62356 },
62357/* bntst${X} ${BitBase32-24-u19-Prefixed} */
62358 {
62359 { 0, 0, 0, 0 },
62360 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62361 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c000 }
62362 },
62363/* bntst${X} ${BitBase32-24-u27-Prefixed} */
62364 {
62365 { 0, 0, 0, 0 },
62366 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62367 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68000 }
62368 },
62369/* bntst${X} $Bitno16R,$Bit16Rn */
62370 {
62371 { 0, 0, 0, 0 },
62372 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62373 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e3000 }
62374 },
62375/* bntst${X} $Bitno16R,$Bit16An */
62376 {
62377 { 0, 0, 0, 0 },
62378 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62379 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e3400 }
62380 },
62381/* bntst${X} [$Bit16An] */
62382 {
62383 { 0, 0, 0, 0 },
62384 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62385 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e36 }
62386 },
62387/* bntst${X} ${Dsp-16-u8}[$Bit16An] */
62388 {
62389 { 0, 0, 0, 0 },
62390 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62391 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e3800 }
62392 },
62393/* bntst${X} ${Dsp-16-u16}[$Bit16An] */
62394 {
62395 { 0, 0, 0, 0 },
62396 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62397 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e3c0000 }
62398 },
62399/* bntst${X} ${BitBase16-16-u8}[sb] */
62400 {
62401 { 0, 0, 0, 0 },
62402 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62403 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e3a00 }
62404 },
62405/* bntst${X} ${BitBase16-16-u16}[sb] */
62406 {
62407 { 0, 0, 0, 0 },
62408 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62409 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e3e0000 }
62410 },
62411/* bntst${X} ${BitBase16-16-s8}[fb] */
62412 {
62413 { 0, 0, 0, 0 },
62414 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62415 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e3b00 }
62416 },
62417/* bntst${X} ${BitBase16-16-u16} */
62418 {
62419 { 0, 0, 0, 0 },
62420 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62421 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e3f0000 }
62422 },
62423/* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
62424 {
62425 { 0, 0, 0, 0 },
62426 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
62427 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd818 }
62428 },
62429/* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
62430 {
62431 { 0, 0, 0, 0 },
62432 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
62433 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd098 }
62434 },
62435/* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
62436 {
62437 { 0, 0, 0, 0 },
62438 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62439 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd018 }
62440 },
62441/* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
62442 {
62443 { 0, 0, 0, 0 },
62444 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62445 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd21800 }
62446 },
62447/* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
62448 {
62449 { 0, 0, 0, 0 },
62450 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62451 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4180000 }
62452 },
62453/* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
62454 {
62455 { 0, 0, 0, 0 },
62456 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62457 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6180000 }
62458 },
62459/* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
62460 {
62461 { 0, 0, 0, 0 },
62462 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62463 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd29800 }
62464 },
62465/* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
62466 {
62467 { 0, 0, 0, 0 },
62468 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62469 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4980000 }
62470 },
62471/* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
62472 {
62473 { 0, 0, 0, 0 },
62474 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62475 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2d800 }
62476 },
62477/* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
62478 {
62479 { 0, 0, 0, 0 },
62480 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62481 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4d80000 }
62482 },
62483/* bnot${X} ${BitBase32-16-u19-Unprefixed} */
62484 {
62485 { 0, 0, 0, 0 },
62486 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
62487 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6d80000 }
62488 },
62489/* bnot${X} ${BitBase32-16-u27-Unprefixed} */
62490 {
62491 { 0, 0, 0, 0 },
62492 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
62493 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6980000 }
62494 },
62495/* bnot${G} $Bitno16R,$Bit16Rn */
62496 {
62497 { 0, 0, 0, 0 },
62498 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62499 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ea000 }
62500 },
62501/* bnot${G} $Bitno16R,$Bit16An */
62502 {
62503 { 0, 0, 0, 0 },
62504 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62505 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ea400 }
62506 },
62507/* bnot${G} ${Dsp-16-u8}[$Bit16An] */
62508 {
62509 { 0, 0, 0, 0 },
62510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62511 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ea800 }
62512 },
62513/* bnot${G} ${BitBase16-16-u8}[sb] */
62514 {
62515 { 0, 0, 0, 0 },
62516 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62517 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eaa00 }
62518 },
62519/* bnot${G} ${BitBase16-16-s8}[fb] */
62520 {
62521 { 0, 0, 0, 0 },
62522 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62523 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7eab00 }
62524 },
62525/* bnot${S} ${BitBase16-8-u11-S}[sb] */
62526 {
62527 { 0, 0, 0, 0 },
62528 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
62529 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5000 }
62530 },
62531/* bnot${G} ${Dsp-16-u16}[$Bit16An] */
62532 {
62533 { 0, 0, 0, 0 },
62534 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62535 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7eac0000 }
62536 },
62537/* bnot${G} ${BitBase16-16-u16}[sb] */
62538 {
62539 { 0, 0, 0, 0 },
62540 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62541 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7eae0000 }
62542 },
62543/* bnot${G} ${BitBase16-16-u16} */
62544 {
62545 { 0, 0, 0, 0 },
62546 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
62547 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7eaf0000 }
62548 },
62549/* bnot${G} [$Bit16An] */
62550 {
62551 { 0, 0, 0, 0 },
62552 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
62553 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ea6 }
62554 },
62555/* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62556 {
62557 { 0, 0, 0, 0 },
62558 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62559 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d830 }
62560 },
62561/* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62562 {
62563 { 0, 0, 0, 0 },
62564 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62565 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b0 }
62566 },
62567/* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62568 {
62569 { 0, 0, 0, 0 },
62570 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62571 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d030 }
62572 },
62573/* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62574 {
62575 { 0, 0, 0, 0 },
62576 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62577 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23000 }
62578 },
62579/* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62580 {
62581 { 0, 0, 0, 0 },
62582 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62583 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43000 }
62584 },
62585/* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62586 {
62587 { 0, 0, 0, 0 },
62588 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62589 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63000 }
62590 },
62591/* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
62592 {
62593 { 0, 0, 0, 0 },
62594 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62595 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b000 }
62596 },
62597/* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
62598 {
62599 { 0, 0, 0, 0 },
62600 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62601 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b000 }
62602 },
62603/* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
62604 {
62605 { 0, 0, 0, 0 },
62606 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62607 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f000 }
62608 },
62609/* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
62610 {
62611 { 0, 0, 0, 0 },
62612 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62613 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f000 }
62614 },
62615/* bnor${X} ${BitBase32-24-u19-Prefixed} */
62616 {
62617 { 0, 0, 0, 0 },
62618 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62619 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f000 }
62620 },
62621/* bnor${X} ${BitBase32-24-u27-Prefixed} */
62622 {
62623 { 0, 0, 0, 0 },
62624 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62625 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b000 }
62626 },
62627/* bnor${X} $Bitno16R,$Bit16Rn */
62628 {
62629 { 0, 0, 0, 0 },
62630 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62631 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e7000 }
62632 },
62633/* bnor${X} $Bitno16R,$Bit16An */
62634 {
62635 { 0, 0, 0, 0 },
62636 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62637 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e7400 }
62638 },
62639/* bnor${X} [$Bit16An] */
62640 {
62641 { 0, 0, 0, 0 },
62642 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62643 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e76 }
62644 },
62645/* bnor${X} ${Dsp-16-u8}[$Bit16An] */
62646 {
62647 { 0, 0, 0, 0 },
62648 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62649 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e7800 }
62650 },
62651/* bnor${X} ${Dsp-16-u16}[$Bit16An] */
62652 {
62653 { 0, 0, 0, 0 },
62654 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62655 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e7c0000 }
62656 },
62657/* bnor${X} ${BitBase16-16-u8}[sb] */
62658 {
62659 { 0, 0, 0, 0 },
62660 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62661 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e7a00 }
62662 },
62663/* bnor${X} ${BitBase16-16-u16}[sb] */
62664 {
62665 { 0, 0, 0, 0 },
62666 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62667 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e7e0000 }
62668 },
62669/* bnor${X} ${BitBase16-16-s8}[fb] */
62670 {
62671 { 0, 0, 0, 0 },
62672 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62673 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e7b00 }
62674 },
62675/* bnor${X} ${BitBase16-16-u16} */
62676 {
62677 { 0, 0, 0, 0 },
62678 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62679 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e7f0000 }
62680 },
62681/* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62682 {
62683 { 0, 0, 0, 0 },
62684 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62685 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d818 }
62686 },
62687/* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62688 {
62689 { 0, 0, 0, 0 },
62690 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62691 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d098 }
62692 },
62693/* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62694 {
62695 { 0, 0, 0, 0 },
62696 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62697 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d018 }
62698 },
62699/* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62700 {
62701 { 0, 0, 0, 0 },
62702 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62703 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d21800 }
62704 },
62705/* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62706 {
62707 { 0, 0, 0, 0 },
62708 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62709 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d41800 }
62710 },
62711/* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62712 {
62713 { 0, 0, 0, 0 },
62714 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62715 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d61800 }
62716 },
62717/* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
62718 {
62719 { 0, 0, 0, 0 },
62720 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62721 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d29800 }
62722 },
62723/* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
62724 {
62725 { 0, 0, 0, 0 },
62726 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62727 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d49800 }
62728 },
62729/* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
62730 {
62731 { 0, 0, 0, 0 },
62732 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62733 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2d800 }
62734 },
62735/* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
62736 {
62737 { 0, 0, 0, 0 },
62738 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62739 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4d800 }
62740 },
62741/* bnand${X} ${BitBase32-24-u19-Prefixed} */
62742 {
62743 { 0, 0, 0, 0 },
62744 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62745 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6d800 }
62746 },
62747/* bnand${X} ${BitBase32-24-u27-Prefixed} */
62748 {
62749 { 0, 0, 0, 0 },
62750 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62751 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d69800 }
62752 },
62753/* bnand${X} $Bitno16R,$Bit16Rn */
62754 {
62755 { 0, 0, 0, 0 },
62756 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62757 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e5000 }
62758 },
62759/* bnand${X} $Bitno16R,$Bit16An */
62760 {
62761 { 0, 0, 0, 0 },
62762 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62763 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e5400 }
62764 },
62765/* bnand${X} [$Bit16An] */
62766 {
62767 { 0, 0, 0, 0 },
62768 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62769 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e56 }
62770 },
62771/* bnand${X} ${Dsp-16-u8}[$Bit16An] */
62772 {
62773 { 0, 0, 0, 0 },
62774 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62775 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e5800 }
62776 },
62777/* bnand${X} ${Dsp-16-u16}[$Bit16An] */
62778 {
62779 { 0, 0, 0, 0 },
62780 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62781 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e5c0000 }
62782 },
62783/* bnand${X} ${BitBase16-16-u8}[sb] */
62784 {
62785 { 0, 0, 0, 0 },
62786 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62787 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e5a00 }
62788 },
62789/* bnand${X} ${BitBase16-16-u16}[sb] */
62790 {
62791 { 0, 0, 0, 0 },
62792 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62793 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e5e0000 }
62794 },
62795/* bnand${X} ${BitBase16-16-s8}[fb] */
62796 {
62797 { 0, 0, 0, 0 },
62798 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62799 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e5b00 }
62800 },
62801/* bnand${X} ${BitBase16-16-u16} */
62802 {
62803 { 0, 0, 0, 0 },
62804 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62805 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e5f0000 }
62806 },
62807/* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
62808 {
62809 { 0, 0, 0, 0 },
62810 { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
62811 & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed, { 0xd81000 }
62812 },
62813/* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
62814 {
62815 { 0, 0, 0, 0 },
62816 { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
62817 & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed, { 0xd09000 }
62818 },
62819/* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
62820 {
62821 { 0, 0, 0, 0 },
62822 { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62823 & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed, { 0xd01000 }
62824 },
62825/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
62826 {
62827 { 0, 0, 0, 0 },
62828 { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62829 & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed, { 0xd2100000 }
62830 },
62831/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
62832 {
62833 { 0, 0, 0, 0 },
62834 { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62835 & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed, { 0xd2900000 }
62836 },
62837/* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
62838 {
62839 { 0, 0, 0, 0 },
62840 { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62841 & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed, { 0xd2d00000 }
62842 },
62843/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
62844 {
62845 { 0, 0, 0, 0 },
62846 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62847 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed, { 0xd4100000 }
62848 },
62849/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
62850 {
62851 { 0, 0, 0, 0 },
62852 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62853 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed, { 0xd4900000 }
62854 },
62855/* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
62856 {
62857 { 0, 0, 0, 0 },
62858 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62859 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed, { 0xd4d00000 }
62860 },
62861/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
62862 {
62863 { 0, 0, 0, 0 },
62864 { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
62865 & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed, { 0xd6d00000 }
62866 },
62867/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
62868 {
62869 { 0, 0, 0, 0 },
62870 { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62871 & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed, { 0xd6100000 }
62872 },
62873/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
62874 {
62875 { 0, 0, 0, 0 },
62876 { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
62877 & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed, { 0xd6900000 }
62878 },
62879/* bm${cond16-24} $Bitno16R,$Bit16Rn */
62880 {
62881 { 0, 0, 0, 0 },
62882 { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62883 & ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct, { 0x7e200000 }
62884 },
62885/* bm${cond16-24} $Bitno16R,$Bit16An */
62886 {
62887 { 0, 0, 0, 0 },
62888 { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62889 & ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct, { 0x7e240000 }
62890 },
62891/* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
62892 {
62893 { 0, 0, 0, 0 },
62894 { { MNEM, OP (COND16_24), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62895 & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative, { 0x7e280000 }
62896 },
62897/* bm${cond16-24} ${BitBase16-16-u8}[sb] */
62898 {
62899 { 0, 0, 0, 0 },
62900 { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62901 & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative, { 0x7e2a0000 }
62902 },
62903/* bm${cond16-24} ${BitBase16-16-s8}[fb] */
62904 {
62905 { 0, 0, 0, 0 },
62906 { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62907 & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative, { 0x7e2b0000 }
62908 },
62909/* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
62910 {
62911 { 0, 0, 0, 0 },
62912 { { MNEM, OP (COND16_32), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62913 & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative, { 0x7e2c0000 }
62914 },
62915/* bm${cond16-32} ${BitBase16-16-u16}[sb] */
62916 {
62917 { 0, 0, 0, 0 },
62918 { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62919 & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative, { 0x7e2e0000 }
62920 },
62921/* bm${cond16-32} ${BitBase16-16-u16} */
62922 {
62923 { 0, 0, 0, 0 },
62924 { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), 0 } },
62925 & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute, { 0x7e2f0000 }
62926 },
62927/* bm${cond16-16} [$Bit16An] */
62928 {
62929 { 0, 0, 0, 0 },
62930 { { MNEM, OP (COND16_16), ' ', '[', OP (BIT16AN), ']', 0 } },
62931 & ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect, { 0x7e2600 }
62932 },
62933/* bitindex.w $Dst32RnUnprefixedHI */
62934 {
62935 { 0, 0, 0, 0 },
62936 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
62937 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc92e }
62938 },
62939/* bitindex.w $Dst32AnUnprefixedHI */
62940 {
62941 { 0, 0, 0, 0 },
62942 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
62943 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1ae }
62944 },
62945/* bitindex.w [$Dst32AnUnprefixed] */
62946 {
62947 { 0, 0, 0, 0 },
62948 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62949 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc12e }
62950 },
62951/* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
62952 {
62953 { 0, 0, 0, 0 },
62954 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62955 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc32e00 }
62956 },
62957/* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
62958 {
62959 { 0, 0, 0, 0 },
62960 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62961 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc52e0000 }
62962 },
62963/* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
62964 {
62965 { 0, 0, 0, 0 },
62966 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62967 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc72e0000 }
62968 },
62969/* bitindex.w ${Dsp-16-u8}[sb] */
62970 {
62971 { 0, 0, 0, 0 },
62972 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
62973 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3ae00 }
62974 },
62975/* bitindex.w ${Dsp-16-u16}[sb] */
62976 {
62977 { 0, 0, 0, 0 },
62978 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
62979 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5ae0000 }
62980 },
62981/* bitindex.w ${Dsp-16-s8}[fb] */
62982 {
62983 { 0, 0, 0, 0 },
62984 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
62985 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ee00 }
62986 },
62987/* bitindex.w ${Dsp-16-s16}[fb] */
62988 {
62989 { 0, 0, 0, 0 },
62990 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
62991 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ee0000 }
62992 },
62993/* bitindex.w ${Dsp-16-u16} */
62994 {
62995 { 0, 0, 0, 0 },
62996 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
62997 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ee0000 }
62998 },
62999/* bitindex.w ${Dsp-16-u24} */
63000 {
63001 { 0, 0, 0, 0 },
63002 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
63003 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7ae0000 }
63004 },
63005/* bitindex.b $Dst32RnUnprefixedQI */
63006 {
63007 { 0, 0, 0, 0 },
63008 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
63009 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc82e }
63010 },
63011/* bitindex.b $Dst32AnUnprefixedQI */
63012 {
63013 { 0, 0, 0, 0 },
63014 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
63015 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0ae }
63016 },
63017/* bitindex.b [$Dst32AnUnprefixed] */
63018 {
63019 { 0, 0, 0, 0 },
63020 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63021 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc02e }
63022 },
63023/* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
63024 {
63025 { 0, 0, 0, 0 },
63026 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63027 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22e00 }
63028 },
63029/* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
63030 {
63031 { 0, 0, 0, 0 },
63032 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63033 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc42e0000 }
63034 },
63035/* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
63036 {
63037 { 0, 0, 0, 0 },
63038 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63039 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc62e0000 }
63040 },
63041/* bitindex.b ${Dsp-16-u8}[sb] */
63042 {
63043 { 0, 0, 0, 0 },
63044 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
63045 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2ae00 }
63046 },
63047/* bitindex.b ${Dsp-16-u16}[sb] */
63048 {
63049 { 0, 0, 0, 0 },
63050 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
63051 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4ae0000 }
63052 },
63053/* bitindex.b ${Dsp-16-s8}[fb] */
63054 {
63055 { 0, 0, 0, 0 },
63056 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
63057 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ee00 }
63058 },
63059/* bitindex.b ${Dsp-16-s16}[fb] */
63060 {
63061 { 0, 0, 0, 0 },
63062 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
63063 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ee0000 }
63064 },
63065/* bitindex.b ${Dsp-16-u16} */
63066 {
63067 { 0, 0, 0, 0 },
63068 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
63069 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ee0000 }
63070 },
63071/* bitindex.b ${Dsp-16-u24} */
63072 {
63073 { 0, 0, 0, 0 },
63074 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
63075 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6ae0000 }
63076 },
63077/* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
63078 {
63079 { 0, 0, 0, 0 },
63080 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
63081 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd830 }
63082 },
63083/* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
63084 {
63085 { 0, 0, 0, 0 },
63086 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
63087 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b0 }
63088 },
63089/* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
63090 {
63091 { 0, 0, 0, 0 },
63092 { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63093 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd030 }
63094 },
63095/* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
63096 {
63097 { 0, 0, 0, 0 },
63098 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63099 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23000 }
63100 },
63101/* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
63102 {
63103 { 0, 0, 0, 0 },
63104 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63105 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4300000 }
63106 },
63107/* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
63108 {
63109 { 0, 0, 0, 0 },
63110 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63111 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6300000 }
63112 },
63113/* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
63114 {
63115 { 0, 0, 0, 0 },
63116 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
63117 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b000 }
63118 },
63119/* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
63120 {
63121 { 0, 0, 0, 0 },
63122 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
63123 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b00000 }
63124 },
63125/* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
63126 {
63127 { 0, 0, 0, 0 },
63128 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
63129 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f000 }
63130 },
63131/* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
63132 {
63133 { 0, 0, 0, 0 },
63134 { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
63135 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f00000 }
63136 },
63137/* bclr${X} ${BitBase32-16-u19-Unprefixed} */
63138 {
63139 { 0, 0, 0, 0 },
63140 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
63141 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f00000 }
63142 },
63143/* bclr${X} ${BitBase32-16-u27-Unprefixed} */
63144 {
63145 { 0, 0, 0, 0 },
63146 { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
63147 & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b00000 }
63148 },
63149/* bclr${G} $Bitno16R,$Bit16Rn */
63150 {
63151 { 0, 0, 0, 0 },
63152 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
63153 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e8000 }
63154 },
63155/* bclr${G} $Bitno16R,$Bit16An */
63156 {
63157 { 0, 0, 0, 0 },
63158 { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
63159 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e8400 }
63160 },
63161/* bclr${G} ${Dsp-16-u8}[$Bit16An] */
63162 {
63163 { 0, 0, 0, 0 },
63164 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
63165 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e8800 }
63166 },
63167/* bclr${G} ${BitBase16-16-u8}[sb] */
63168 {
63169 { 0, 0, 0, 0 },
63170 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
63171 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e8a00 }
63172 },
63173/* bclr${G} ${BitBase16-16-s8}[fb] */
63174 {
63175 { 0, 0, 0, 0 },
63176 { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
63177 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e8b00 }
63178 },
63179/* bclr${S} ${BitBase16-8-u11-S}[sb] */
63180 {
63181 { 0, 0, 0, 0 },
63182 { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
63183 & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4000 }
63184 },
63185/* bclr${G} ${Dsp-16-u16}[$Bit16An] */
63186 {
63187 { 0, 0, 0, 0 },
63188 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
63189 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e8c0000 }
63190 },
63191/* bclr${G} ${BitBase16-16-u16}[sb] */
63192 {
63193 { 0, 0, 0, 0 },
63194 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
63195 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e8e0000 }
63196 },
63197/* bclr${G} ${BitBase16-16-u16} */
63198 {
63199 { 0, 0, 0, 0 },
63200 { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
63201 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e8f0000 }
63202 },
63203/* bclr${G} [$Bit16An] */
63204 {
63205 { 0, 0, 0, 0 },
63206 { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
63207 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e86 }
63208 },
63209/* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
63210 {
63211 { 0, 0, 0, 0 },
63212 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
63213 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d808 }
63214 },
63215/* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
63216 {
63217 { 0, 0, 0, 0 },
63218 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
63219 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d088 }
63220 },
63221/* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
63222 {
63223 { 0, 0, 0, 0 },
63224 { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
63225 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d008 }
63226 },
63227/* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
63228 {
63229 { 0, 0, 0, 0 },
63230 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
63231 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20800 }
63232 },
63233/* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
63234 {
63235 { 0, 0, 0, 0 },
63236 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
63237 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40800 }
63238 },
63239/* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
63240 {
63241 { 0, 0, 0, 0 },
63242 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
63243 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60800 }
63244 },
63245/* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
63246 {
63247 { 0, 0, 0, 0 },
63248 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
63249 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28800 }
63250 },
63251/* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
63252 {
63253 { 0, 0, 0, 0 },
63254 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
63255 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48800 }
63256 },
63257/* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
63258 {
63259 { 0, 0, 0, 0 },
63260 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
63261 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c800 }
63262 },
63263/* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
63264 {
63265 { 0, 0, 0, 0 },
63266 { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
63267 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c800 }
63268 },
63269/* band${X} ${BitBase32-24-u19-Prefixed} */
63270 {
63271 { 0, 0, 0, 0 },
63272 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
63273 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c800 }
63274 },
63275/* band${X} ${BitBase32-24-u27-Prefixed} */
63276 {
63277 { 0, 0, 0, 0 },
63278 { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
63279 & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68800 }
63280 },
63281/* band${X} $Bitno16R,$Bit16Rn */
63282 {
63283 { 0, 0, 0, 0 },
63284 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
63285 & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e4000 }
63286 },
63287/* band${X} $Bitno16R,$Bit16An */
63288 {
63289 { 0, 0, 0, 0 },
63290 { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
63291 & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e4400 }
63292 },
63293/* band${X} [$Bit16An] */
63294 {
63295 { 0, 0, 0, 0 },
63296 { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
63297 & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e46 }
63298 },
63299/* band${X} ${Dsp-16-u8}[$Bit16An] */
63300 {
63301 { 0, 0, 0, 0 },
63302 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
63303 & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e4800 }
63304 },
63305/* band${X} ${Dsp-16-u16}[$Bit16An] */
63306 {
63307 { 0, 0, 0, 0 },
63308 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
63309 & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e4c0000 }
63310 },
63311/* band${X} ${BitBase16-16-u8}[sb] */
63312 {
63313 { 0, 0, 0, 0 },
63314 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
63315 & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e4a00 }
63316 },
63317/* band${X} ${BitBase16-16-u16}[sb] */
63318 {
63319 { 0, 0, 0, 0 },
63320 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
63321 & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e4e0000 }
63322 },
63323/* band${X} ${BitBase16-16-s8}[fb] */
63324 {
63325 { 0, 0, 0, 0 },
63326 { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
63327 & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e4b00 }
63328 },
63329/* band${X} ${BitBase16-16-u16} */
63330 {
63331 { 0, 0, 0, 0 },
63332 { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
63333 & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e4f0000 }
63334 },
63335/* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
63336 {
63337 { 0, 0, 0, 0 },
63338 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
63339 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6d000000 }
63340 },
63341/* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
63342 {
63343 { 0, 0, 0, 0 },
63344 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
63345 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7d000000 }
63346 },
63347/* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
63348 {
63349 { 0, 0, 0, 0 },
63350 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
63351 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x5d000000 }
63352 },
63353/* and.w${S} #${Imm-8-HI},r0 */
63354 {
63355 { 0, 0, 0, 0 },
63356 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
63357 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x4d0000 }
63358 },
63359/* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
63360 {
63361 { 0, 0, 0, 0 },
63362 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
63363 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6c0000 }
63364 },
63365/* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
63366 {
63367 { 0, 0, 0, 0 },
63368 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
63369 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7c0000 }
63370 },
63371/* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
63372 {
63373 { 0, 0, 0, 0 },
63374 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
63375 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x5c000000 }
63376 },
63377/* and.b${S} #${Imm-8-QI},r0l */
63378 {
63379 { 0, 0, 0, 0 },
63380 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
63381 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4c00 }
63382 },
63383/* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
63384 {
63385 { 0, 0, 0, 0 },
63386 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
5348b81e 63387 & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x10 }
49f58d10
JB		 63388 },
63389/* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
63390 {
63391 { 0, 0, 0, 0 },
63392 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 63393 & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1100 }
49f58d10
JB		 63394 },
63395/* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
63396 {
63397 { 0, 0, 0, 0 },
63398 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 63399 & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1200 }
49f58d10
JB		 63400 },
63401/* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
63402 {
63403 { 0, 0, 0, 0 },
63404 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
5348b81e 63405 & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x130000 }
49f58d10
JB		 63406 },
63407/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63408 {
63409 { 0, 0, 0, 0 },
63410 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63411 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990d00 }
63412 },
63413/* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
63414 {
63415 { 0, 0, 0, 0 },
63416 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63417 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992d00 }
63418 },
63419/* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
63420 {
63421 { 0, 0, 0, 0 },
63422 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63423 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993d00 }
63424 },
63425/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63426 {
63427 { 0, 0, 0, 0 },
63428 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63429 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918d00 }
63430 },
63431/* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
63432 {
63433 { 0, 0, 0, 0 },
63434 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63435 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ad00 }
63436 },
63437/* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
63438 {
63439 { 0, 0, 0, 0 },
63440 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63441 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bd00 }
63442 },
63443/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63444 {
63445 { 0, 0, 0, 0 },
63446 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63447 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910d00 }
63448 },
63449/* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
63450 {
63451 { 0, 0, 0, 0 },
63452 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63453 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912d00 }
63454 },
63455/* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
63456 {
63457 { 0, 0, 0, 0 },
63458 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63459 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913d00 }
63460 },
63461/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63462 {
63463 { 0, 0, 0, 0 },
63464 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63465 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930d0000 }
63466 },
63467/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63468 {
63469 { 0, 0, 0, 0 },
63470 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63471 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932d0000 }
63472 },
63473/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63474 {
63475 { 0, 0, 0, 0 },
63476 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63477 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933d0000 }
63478 },
63479/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63480 {
63481 { 0, 0, 0, 0 },
63482 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63483 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950d0000 }
63484 },
63485/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63486 {
63487 { 0, 0, 0, 0 },
63488 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63489 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952d0000 }
63490 },
63491/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63492 {
63493 { 0, 0, 0, 0 },
63494 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63495 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953d0000 }
63496 },
63497/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63498 {
63499 { 0, 0, 0, 0 },
63500 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63501 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970d0000 }
63502 },
63503/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63504 {
63505 { 0, 0, 0, 0 },
63506 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63507 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972d0000 }
63508 },
63509/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63510 {
63511 { 0, 0, 0, 0 },
63512 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63513 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973d0000 }
63514 },
63515/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
63516 {
63517 { 0, 0, 0, 0 },
63518 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63519 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938d0000 }
63520 },
63521/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
63522 {
63523 { 0, 0, 0, 0 },
63524 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63525 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ad0000 }
63526 },
63527/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
63528 {
63529 { 0, 0, 0, 0 },
63530 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63531 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bd0000 }
63532 },
63533/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
63534 {
63535 { 0, 0, 0, 0 },
63536 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63537 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958d0000 }
63538 },
63539/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
63540 {
63541 { 0, 0, 0, 0 },
63542 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63543 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ad0000 }
63544 },
63545/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
63546 {
63547 { 0, 0, 0, 0 },
63548 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63549 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bd0000 }
63550 },
63551/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
63552 {
63553 { 0, 0, 0, 0 },
63554 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63555 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cd0000 }
63556 },
63557/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
63558 {
63559 { 0, 0, 0, 0 },
63560 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63561 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ed0000 }
63562 },
63563/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
63564 {
63565 { 0, 0, 0, 0 },
63566 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63567 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fd0000 }
63568 },
63569/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
63570 {
63571 { 0, 0, 0, 0 },
63572 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63573 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cd0000 }
63574 },
63575/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
63576 {
63577 { 0, 0, 0, 0 },
63578 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63579 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ed0000 }
63580 },
63581/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
63582 {
63583 { 0, 0, 0, 0 },
63584 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63585 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fd0000 }
63586 },
63587/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
63588 {
63589 { 0, 0, 0, 0 },
63590 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
63591 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cd0000 }
63592 },
63593/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
63594 {
63595 { 0, 0, 0, 0 },
63596 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
63597 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ed0000 }
63598 },
63599/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
63600 {
63601 { 0, 0, 0, 0 },
63602 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
63603 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fd0000 }
63604 },
63605/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
63606 {
63607 { 0, 0, 0, 0 },
63608 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
63609 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978d0000 }
63610 },
63611/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
63612 {
63613 { 0, 0, 0, 0 },
63614 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
63615 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ad0000 }
63616 },
63617/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
63618 {
63619 { 0, 0, 0, 0 },
63620 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
63621 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bd0000 }
63622 },
63623/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63624 {
63625 { 0, 0, 0, 0 },
63626 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63627 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90d0000 }
63628 },
63629/* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
63630 {
63631 { 0, 0, 0, 0 },
63632 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63633 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92d0000 }
63634 },
63635/* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
63636 {
63637 { 0, 0, 0, 0 },
63638 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63639 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93d0000 }
63640 },
63641/* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
63642 {
63643 { 0, 0, 0, 0 },
63644 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63645 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93d0000 }
63646 },
63647/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63648 {
63649 { 0, 0, 0, 0 },
63650 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63651 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18d0000 }
63652 },
63653/* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
63654 {
63655 { 0, 0, 0, 0 },
63656 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63657 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ad0000 }
63658 },
63659/* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
63660 {
63661 { 0, 0, 0, 0 },
63662 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63663 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bd0000 }
63664 },
63665/* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
63666 {
63667 { 0, 0, 0, 0 },
63668 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63669 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bd0000 }
63670 },
63671/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63672 {
63673 { 0, 0, 0, 0 },
63674 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63675 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10d0000 }
63676 },
63677/* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
63678 {
63679 { 0, 0, 0, 0 },
63680 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63681 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12d0000 }
63682 },
63683/* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
63684 {
63685 { 0, 0, 0, 0 },
63686 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63687 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13d0000 }
63688 },
63689/* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
63690 {
63691 { 0, 0, 0, 0 },
63692 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63693 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13d0000 }
63694 },
63695/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63696 {
63697 { 0, 0, 0, 0 },
63698 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63699 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30d0000 }
63700 },
63701/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63702 {
63703 { 0, 0, 0, 0 },
63704 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63705 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32d0000 }
63706 },
63707/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63708 {
63709 { 0, 0, 0, 0 },
63710 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63711 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33d0000 }
63712 },
63713/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
63714 {
63715 { 0, 0, 0, 0 },
63716 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63717 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33d0000 }
63718 },
63719/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63720 {
63721 { 0, 0, 0, 0 },
63722 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63723 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50d0000 }
63724 },
63725/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63726 {
63727 { 0, 0, 0, 0 },
63728 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63729 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52d0000 }
63730 },
63731/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63732 {
63733 { 0, 0, 0, 0 },
63734 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63735 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53d0000 }
63736 },
63737/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
63738 {
63739 { 0, 0, 0, 0 },
63740 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63741 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53d0000 }
63742 },
63743/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63744 {
63745 { 0, 0, 0, 0 },
63746 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63747 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70d0000 }
63748 },
63749/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63750 {
63751 { 0, 0, 0, 0 },
63752 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63753 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72d0000 }
63754 },
63755/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63756 {
63757 { 0, 0, 0, 0 },
63758 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63759 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73d0000 }
63760 },
63761/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
63762 {
63763 { 0, 0, 0, 0 },
63764 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63765 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73d0000 }
63766 },
63767/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
63768 {
63769 { 0, 0, 0, 0 },
63770 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63771 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38d0000 }
63772 },
63773/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
63774 {
63775 { 0, 0, 0, 0 },
63776 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63777 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ad0000 }
63778 },
63779/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
63780 {
63781 { 0, 0, 0, 0 },
63782 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63783 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bd0000 }
63784 },
63785/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
63786 {
63787 { 0, 0, 0, 0 },
63788 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63789 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bd0000 }
63790 },
63791/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
63792 {
63793 { 0, 0, 0, 0 },
63794 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63795 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58d0000 }
63796 },
63797/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
63798 {
63799 { 0, 0, 0, 0 },
63800 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63801 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ad0000 }
63802 },
63803/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
63804 {
63805 { 0, 0, 0, 0 },
63806 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63807 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bd0000 }
63808 },
63809/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
63810 {
63811 { 0, 0, 0, 0 },
63812 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63813 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bd0000 }
63814 },
63815/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
63816 {
63817 { 0, 0, 0, 0 },
63818 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63819 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cd0000 }
63820 },
63821/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
63822 {
63823 { 0, 0, 0, 0 },
63824 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63825 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ed0000 }
63826 },
63827/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
63828 {
63829 { 0, 0, 0, 0 },
63830 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63831 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fd0000 }
63832 },
63833/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
63834 {
63835 { 0, 0, 0, 0 },
63836 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63837 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fd0000 }
63838 },
63839/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
63840 {
63841 { 0, 0, 0, 0 },
63842 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63843 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cd0000 }
63844 },
63845/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
63846 {
63847 { 0, 0, 0, 0 },
63848 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63849 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ed0000 }
63850 },
63851/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
63852 {
63853 { 0, 0, 0, 0 },
63854 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63855 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fd0000 }
63856 },
63857/* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
63858 {
63859 { 0, 0, 0, 0 },
63860 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63861 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fd0000 }
63862 },
63863/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
63864 {
63865 { 0, 0, 0, 0 },
63866 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
63867 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cd0000 }
63868 },
63869/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
63870 {
63871 { 0, 0, 0, 0 },
63872 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
63873 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ed0000 }
63874 },
63875/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
63876 {
63877 { 0, 0, 0, 0 },
63878 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
63879 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fd0000 }
63880 },
63881/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
63882 {
63883 { 0, 0, 0, 0 },
63884 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
63885 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fd0000 }
63886 },
63887/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
63888 {
63889 { 0, 0, 0, 0 },
63890 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
63891 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78d0000 }
63892 },
63893/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
63894 {
63895 { 0, 0, 0, 0 },
63896 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
63897 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ad0000 }
63898 },
63899/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
63900 {
63901 { 0, 0, 0, 0 },
63902 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
63903 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bd0000 }
63904 },
63905/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
63906 {
63907 { 0, 0, 0, 0 },
63908 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
63909 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bd0000 }
63910 },
63911/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63912 {
63913 { 0, 0, 0, 0 },
63914 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63915 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90d0000 }
63916 },
63917/* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
63918 {
63919 { 0, 0, 0, 0 },
63920 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63921 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92d0000 }
63922 },
63923/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63924 {
63925 { 0, 0, 0, 0 },
63926 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63927 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18d0000 }
63928 },
63929/* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
63930 {
63931 { 0, 0, 0, 0 },
63932 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63933 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ad0000 }
63934 },
63935/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63936 {
63937 { 0, 0, 0, 0 },
63938 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63939 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10d0000 }
63940 },
63941/* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
63942 {
63943 { 0, 0, 0, 0 },
63944 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63945 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12d0000 }
63946 },
63947/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
63948 {
63949 { 0, 0, 0, 0 },
63950 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63951 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30d0000 }
63952 },
63953/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
63954 {
63955 { 0, 0, 0, 0 },
63956 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63957 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32d0000 }
63958 },
63959/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
63960 {
63961 { 0, 0, 0, 0 },
63962 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63963 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50d0000 }
63964 },
63965/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
63966 {
63967 { 0, 0, 0, 0 },
63968 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63969 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52d0000 }
63970 },
63971/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
63972 {
63973 { 0, 0, 0, 0 },
63974 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63975 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70d0000 }
63976 },
63977/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
63978 {
63979 { 0, 0, 0, 0 },
63980 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63981 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72d0000 }
63982 },
63983/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
63984 {
63985 { 0, 0, 0, 0 },
63986 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
63987 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38d0000 }
63988 },
63989/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
63990 {
63991 { 0, 0, 0, 0 },
63992 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
63993 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ad0000 }
63994 },
63995/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
63996 {
63997 { 0, 0, 0, 0 },
63998 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
63999 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58d0000 }
64000 },
64001/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
64002 {
64003 { 0, 0, 0, 0 },
64004 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
64005 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ad0000 }
64006 },
64007/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
64008 {
64009 { 0, 0, 0, 0 },
64010 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64011 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cd0000 }
64012 },
64013/* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
64014 {
64015 { 0, 0, 0, 0 },
64016 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64017 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ed0000 }
64018 },
64019/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
64020 {
64021 { 0, 0, 0, 0 },
64022 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64023 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cd0000 }
64024 },
64025/* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
64026 {
64027 { 0, 0, 0, 0 },
64028 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64029 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ed0000 }
64030 },
64031/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
64032 {
64033 { 0, 0, 0, 0 },
64034 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
64035 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cd0000 }
64036 },
64037/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
64038 {
64039 { 0, 0, 0, 0 },
64040 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
64041 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ed0000 }
64042 },
64043/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
64044 {
64045 { 0, 0, 0, 0 },
64046 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
64047 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78d0000 }
64048 },
64049/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
64050 {
64051 { 0, 0, 0, 0 },
64052 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
64053 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ad0000 }
64054 },
64055/* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
64056 {
64057 { 0, 0, 0, 0 },
64058 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
64059 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90d }
64060 },
64061/* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
64062 {
64063 { 0, 0, 0, 0 },
64064 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
64065 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892d }
64066 },
64067/* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
64068 {
64069 { 0, 0, 0, 0 },
64070 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
64071 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890d }
64072 },
64073/* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
64074 {
64075 { 0, 0, 0, 0 },
64076 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
64077 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18d }
64078 },
64079/* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
64080 {
64081 { 0, 0, 0, 0 },
64082 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
64083 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ad }
64084 },
64085/* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
64086 {
64087 { 0, 0, 0, 0 },
64088 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
64089 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818d }
64090 },
64091/* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
64092 {
64093 { 0, 0, 0, 0 },
64094 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64095 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10d }
64096 },
64097/* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
64098 {
64099 { 0, 0, 0, 0 },
64100 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64101 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812d }
64102 },
64103/* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64104 {
64105 { 0, 0, 0, 0 },
64106 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64107 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810d }
64108 },
64109/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64110 {
64111 { 0, 0, 0, 0 },
64112 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64113 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30d00 }
64114 },
64115/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64116 {
64117 { 0, 0, 0, 0 },
64118 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64119 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832d00 }
64120 },
64121/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
64122 {
64123 { 0, 0, 0, 0 },
64124 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64125 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830d00 }
64126 },
64127/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64128 {
64129 { 0, 0, 0, 0 },
64130 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64131 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50d0000 }
64132 },
64133/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64134 {
64135 { 0, 0, 0, 0 },
64136 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64137 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852d0000 }
64138 },
64139/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
64140 {
64141 { 0, 0, 0, 0 },
64142 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64143 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850d0000 }
64144 },
64145/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
64146 {
64147 { 0, 0, 0, 0 },
64148 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64149 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70d0000 }
64150 },
64151/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
64152 {
64153 { 0, 0, 0, 0 },
64154 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64155 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872d0000 }
64156 },
64157/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
64158 {
64159 { 0, 0, 0, 0 },
64160 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64161 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870d0000 }
64162 },
64163/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
64164 {
64165 { 0, 0, 0, 0 },
64166 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64167 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38d00 }
64168 },
64169/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
64170 {
64171 { 0, 0, 0, 0 },
64172 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64173 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ad00 }
64174 },
64175/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
64176 {
64177 { 0, 0, 0, 0 },
64178 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64179 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838d00 }
64180 },
64181/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
64182 {
64183 { 0, 0, 0, 0 },
64184 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64185 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58d0000 }
64186 },
64187/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
64188 {
64189 { 0, 0, 0, 0 },
64190 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64191 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ad0000 }
64192 },
64193/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
64194 {
64195 { 0, 0, 0, 0 },
64196 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64197 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858d0000 }
64198 },
64199/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
64200 {
64201 { 0, 0, 0, 0 },
64202 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64203 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cd00 }
64204 },
64205/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
64206 {
64207 { 0, 0, 0, 0 },
64208 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64209 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ed00 }
64210 },
64211/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
64212 {
64213 { 0, 0, 0, 0 },
64214 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64215 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cd00 }
64216 },
64217/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
64218 {
64219 { 0, 0, 0, 0 },
64220 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64221 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cd0000 }
64222 },
64223/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
64224 {
64225 { 0, 0, 0, 0 },
64226 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64227 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ed0000 }
64228 },
64229/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
64230 {
64231 { 0, 0, 0, 0 },
64232 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64233 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cd0000 }
64234 },
64235/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
64236 {
64237 { 0, 0, 0, 0 },
64238 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
64239 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cd0000 }
64240 },
64241/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
64242 {
64243 { 0, 0, 0, 0 },
64244 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
64245 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ed0000 }
64246 },
64247/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
64248 {
64249 { 0, 0, 0, 0 },
64250 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
64251 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cd0000 }
64252 },
64253/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
64254 {
64255 { 0, 0, 0, 0 },
64256 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
64257 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78d0000 }
64258 },
64259/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
64260 {
64261 { 0, 0, 0, 0 },
64262 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
64263 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ad0000 }
64264 },
64265/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
64266 {
64267 { 0, 0, 0, 0 },
64268 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
64269 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878d0000 }
64270 },
64271/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64272 {
64273 { 0, 0, 0, 0 },
64274 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64275 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980d00 }
64276 },
64277/* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
64278 {
64279 { 0, 0, 0, 0 },
64280 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64281 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982d00 }
64282 },
64283/* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
64284 {
64285 { 0, 0, 0, 0 },
64286 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64287 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983d00 }
64288 },
64289/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64290 {
64291 { 0, 0, 0, 0 },
64292 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64293 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908d00 }
64294 },
64295/* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
64296 {
64297 { 0, 0, 0, 0 },
64298 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64299 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ad00 }
64300 },
64301/* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
64302 {
64303 { 0, 0, 0, 0 },
64304 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64305 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bd00 }
64306 },
64307/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64308 {
64309 { 0, 0, 0, 0 },
64310 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64311 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900d00 }
64312 },
64313/* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
64314 {
64315 { 0, 0, 0, 0 },
64316 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64317 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902d00 }
64318 },
64319/* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
64320 {
64321 { 0, 0, 0, 0 },
64322 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64323 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903d00 }
64324 },
64325/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
64326 {
64327 { 0, 0, 0, 0 },
64328 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64329 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920d0000 }
64330 },
64331/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
64332 {
64333 { 0, 0, 0, 0 },
64334 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64335 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922d0000 }
64336 },
64337/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
64338 {
64339 { 0, 0, 0, 0 },
64340 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64341 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923d0000 }
64342 },
64343/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
64344 {
64345 { 0, 0, 0, 0 },
64346 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64347 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940d0000 }
64348 },
64349/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
64350 {
64351 { 0, 0, 0, 0 },
64352 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64353 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942d0000 }
64354 },
64355/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
64356 {
64357 { 0, 0, 0, 0 },
64358 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64359 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943d0000 }
64360 },
64361/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
64362 {
64363 { 0, 0, 0, 0 },
64364 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64365 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960d0000 }
64366 },
64367/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
64368 {
64369 { 0, 0, 0, 0 },
64370 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64371 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962d0000 }
64372 },
64373/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
64374 {
64375 { 0, 0, 0, 0 },
64376 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64377 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963d0000 }
64378 },
64379/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
64380 {
64381 { 0, 0, 0, 0 },
64382 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64383 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928d0000 }
64384 },
64385/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
64386 {
64387 { 0, 0, 0, 0 },
64388 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64389 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ad0000 }
64390 },
64391/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
64392 {
64393 { 0, 0, 0, 0 },
64394 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64395 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bd0000 }
64396 },
64397/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
64398 {
64399 { 0, 0, 0, 0 },
64400 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64401 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948d0000 }
64402 },
64403/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
64404 {
64405 { 0, 0, 0, 0 },
64406 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64407 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ad0000 }
64408 },
64409/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
64410 {
64411 { 0, 0, 0, 0 },
64412 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64413 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bd0000 }
64414 },
64415/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
64416 {
64417 { 0, 0, 0, 0 },
64418 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64419 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cd0000 }
64420 },
64421/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
64422 {
64423 { 0, 0, 0, 0 },
64424 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64425 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ed0000 }
64426 },
64427/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
64428 {
64429 { 0, 0, 0, 0 },
64430 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64431 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fd0000 }
64432 },
64433/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
64434 {
64435 { 0, 0, 0, 0 },
64436 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64437 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cd0000 }
64438 },
64439/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
64440 {
64441 { 0, 0, 0, 0 },
64442 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64443 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ed0000 }
64444 },
64445/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
64446 {
64447 { 0, 0, 0, 0 },
64448 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64449 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fd0000 }
64450 },
64451/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
64452 {
64453 { 0, 0, 0, 0 },
64454 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
64455 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cd0000 }
64456 },
64457/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
64458 {
64459 { 0, 0, 0, 0 },
64460 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64461 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ed0000 }
64462 },
64463/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
64464 {
64465 { 0, 0, 0, 0 },
64466 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64467 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fd0000 }
64468 },
64469/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
64470 {
64471 { 0, 0, 0, 0 },
64472 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
64473 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968d0000 }
64474 },
64475/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
64476 {
64477 { 0, 0, 0, 0 },
64478 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
64479 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ad0000 }
64480 },
64481/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
64482 {
64483 { 0, 0, 0, 0 },
64484 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
64485 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bd0000 }
64486 },
64487/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64488 {
64489 { 0, 0, 0, 0 },
64490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64491 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80d0000 }
64492 },
64493/* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
64494 {
64495 { 0, 0, 0, 0 },
64496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64497 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82d0000 }
64498 },
64499/* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
64500 {
64501 { 0, 0, 0, 0 },
64502 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64503 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83d0000 }
64504 },
64505/* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
64506 {
64507 { 0, 0, 0, 0 },
64508 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64509 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83d0000 }
64510 },
64511/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64512 {
64513 { 0, 0, 0, 0 },
64514 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64515 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08d0000 }
64516 },
64517/* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
64518 {
64519 { 0, 0, 0, 0 },
64520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64521 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ad0000 }
64522 },
64523/* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
64524 {
64525 { 0, 0, 0, 0 },
64526 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64527 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bd0000 }
64528 },
64529/* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
64530 {
64531 { 0, 0, 0, 0 },
64532 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64533 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bd0000 }
64534 },
64535/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64536 {
64537 { 0, 0, 0, 0 },
64538 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64539 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00d0000 }
64540 },
64541/* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
64542 {
64543 { 0, 0, 0, 0 },
64544 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64545 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02d0000 }
64546 },
64547/* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
64548 {
64549 { 0, 0, 0, 0 },
64550 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64551 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03d0000 }
64552 },
64553/* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
64554 {
64555 { 0, 0, 0, 0 },
64556 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64557 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03d0000 }
64558 },
64559/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64560 {
64561 { 0, 0, 0, 0 },
64562 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64563 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20d0000 }
64564 },
64565/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64566 {
64567 { 0, 0, 0, 0 },
64568 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64569 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22d0000 }
64570 },
64571/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64572 {
64573 { 0, 0, 0, 0 },
64574 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64575 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23d0000 }
64576 },
64577/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
64578 {
64579 { 0, 0, 0, 0 },
64580 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64581 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23d0000 }
64582 },
64583/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64584 {
64585 { 0, 0, 0, 0 },
64586 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64587 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40d0000 }
64588 },
64589/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64590 {
64591 { 0, 0, 0, 0 },
64592 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64593 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42d0000 }
64594 },
64595/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64596 {
64597 { 0, 0, 0, 0 },
64598 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64599 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43d0000 }
64600 },
64601/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
64602 {
64603 { 0, 0, 0, 0 },
64604 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64605 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43d0000 }
64606 },
64607/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64608 {
64609 { 0, 0, 0, 0 },
64610 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64611 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60d0000 }
64612 },
64613/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64614 {
64615 { 0, 0, 0, 0 },
64616 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64617 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62d0000 }
64618 },
64619/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64620 {
64621 { 0, 0, 0, 0 },
64622 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64623 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63d0000 }
64624 },
64625/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
64626 {
64627 { 0, 0, 0, 0 },
64628 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64629 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63d0000 }
64630 },
64631/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
64632 {
64633 { 0, 0, 0, 0 },
64634 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64635 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28d0000 }
64636 },
64637/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
64638 {
64639 { 0, 0, 0, 0 },
64640 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64641 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ad0000 }
64642 },
64643/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
64644 {
64645 { 0, 0, 0, 0 },
64646 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64647 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bd0000 }
64648 },
64649/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
64650 {
64651 { 0, 0, 0, 0 },
64652 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64653 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bd0000 }
64654 },
64655/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
64656 {
64657 { 0, 0, 0, 0 },
64658 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64659 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48d0000 }
64660 },
64661/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
64662 {
64663 { 0, 0, 0, 0 },
64664 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64665 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ad0000 }
64666 },
64667/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
64668 {
64669 { 0, 0, 0, 0 },
64670 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64671 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bd0000 }
64672 },
64673/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
64674 {
64675 { 0, 0, 0, 0 },
64676 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64677 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bd0000 }
64678 },
64679/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
64680 {
64681 { 0, 0, 0, 0 },
64682 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64683 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cd0000 }
64684 },
64685/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
64686 {
64687 { 0, 0, 0, 0 },
64688 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64689 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ed0000 }
64690 },
64691/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
64692 {
64693 { 0, 0, 0, 0 },
64694 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64695 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fd0000 }
64696 },
64697/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
64698 {
64699 { 0, 0, 0, 0 },
64700 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64701 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fd0000 }
64702 },
64703/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
64704 {
64705 { 0, 0, 0, 0 },
64706 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64707 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cd0000 }
64708 },
64709/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
64710 {
64711 { 0, 0, 0, 0 },
64712 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64713 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ed0000 }
64714 },
64715/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
64716 {
64717 { 0, 0, 0, 0 },
64718 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64719 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fd0000 }
64720 },
64721/* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
64722 {
64723 { 0, 0, 0, 0 },
64724 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64725 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fd0000 }
64726 },
64727/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
64728 {
64729 { 0, 0, 0, 0 },
64730 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
64731 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cd0000 }
64732 },
64733/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
64734 {
64735 { 0, 0, 0, 0 },
64736 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
64737 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ed0000 }
64738 },
64739/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
64740 {
64741 { 0, 0, 0, 0 },
64742 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
64743 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fd0000 }
64744 },
64745/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
64746 {
64747 { 0, 0, 0, 0 },
64748 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
64749 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fd0000 }
64750 },
64751/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
64752 {
64753 { 0, 0, 0, 0 },
64754 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
64755 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68d0000 }
64756 },
64757/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
64758 {
64759 { 0, 0, 0, 0 },
64760 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
64761 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ad0000 }
64762 },
64763/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
64764 {
64765 { 0, 0, 0, 0 },
64766 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
64767 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bd0000 }
64768 },
64769/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
64770 {
64771 { 0, 0, 0, 0 },
64772 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
64773 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bd0000 }
64774 },
64775/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64776 {
64777 { 0, 0, 0, 0 },
64778 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64779 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80d0000 }
64780 },
64781/* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
64782 {
64783 { 0, 0, 0, 0 },
64784 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64785 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82d0000 }
64786 },
64787/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64788 {
64789 { 0, 0, 0, 0 },
64790 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64791 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08d0000 }
64792 },
64793/* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
64794 {
64795 { 0, 0, 0, 0 },
64796 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64797 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ad0000 }
64798 },
64799/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64800 {
64801 { 0, 0, 0, 0 },
64802 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64803 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00d0000 }
64804 },
64805/* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
64806 {
64807 { 0, 0, 0, 0 },
64808 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64809 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02d0000 }
64810 },
64811/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
64812 {
64813 { 0, 0, 0, 0 },
64814 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64815 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20d0000 }
64816 },
64817/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
64818 {
64819 { 0, 0, 0, 0 },
64820 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64821 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22d0000 }
64822 },
64823/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
64824 {
64825 { 0, 0, 0, 0 },
64826 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64827 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40d0000 }
64828 },
64829/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
64830 {
64831 { 0, 0, 0, 0 },
64832 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64833 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42d0000 }
64834 },
64835/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
64836 {
64837 { 0, 0, 0, 0 },
64838 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64839 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60d0000 }
64840 },
64841/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
64842 {
64843 { 0, 0, 0, 0 },
64844 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64845 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62d0000 }
64846 },
64847/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
64848 {
64849 { 0, 0, 0, 0 },
64850 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
64851 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28d0000 }
64852 },
64853/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
64854 {
64855 { 0, 0, 0, 0 },
64856 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
64857 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ad0000 }
64858 },
64859/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
64860 {
64861 { 0, 0, 0, 0 },
64862 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
64863 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48d0000 }
64864 },
64865/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
64866 {
64867 { 0, 0, 0, 0 },
64868 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
64869 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ad0000 }
64870 },
64871/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
64872 {
64873 { 0, 0, 0, 0 },
64874 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64875 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cd0000 }
64876 },
64877/* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
64878 {
64879 { 0, 0, 0, 0 },
64880 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64881 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ed0000 }
64882 },
64883/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
64884 {
64885 { 0, 0, 0, 0 },
64886 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64887 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cd0000 }
64888 },
64889/* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
64890 {
64891 { 0, 0, 0, 0 },
64892 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64893 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ed0000 }
64894 },
64895/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
64896 {
64897 { 0, 0, 0, 0 },
64898 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
64899 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cd0000 }
64900 },
64901/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
64902 {
64903 { 0, 0, 0, 0 },
64904 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
64905 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ed0000 }
64906 },
64907/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
64908 {
64909 { 0, 0, 0, 0 },
64910 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
64911 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68d0000 }
64912 },
64913/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
64914 {
64915 { 0, 0, 0, 0 },
64916 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
64917 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ad0000 }
64918 },
64919/* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
64920 {
64921 { 0, 0, 0, 0 },
64922 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64923 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80d }
64924 },
64925/* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
64926 {
64927 { 0, 0, 0, 0 },
64928 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64929 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882d }
64930 },
64931/* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64932 {
64933 { 0, 0, 0, 0 },
64934 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64935 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880d }
64936 },
64937/* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
64938 {
64939 { 0, 0, 0, 0 },
64940 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64941 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08d }
64942 },
64943/* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
64944 {
64945 { 0, 0, 0, 0 },
64946 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64947 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ad }
64948 },
64949/* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64950 {
64951 { 0, 0, 0, 0 },
64952 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64953 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808d }
64954 },
64955/* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
64956 {
64957 { 0, 0, 0, 0 },
64958 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64959 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00d }
64960 },
64961/* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
64962 {
64963 { 0, 0, 0, 0 },
64964 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64965 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802d }
64966 },
64967/* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64968 {
64969 { 0, 0, 0, 0 },
64970 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64971 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800d }
64972 },
64973/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64974 {
64975 { 0, 0, 0, 0 },
64976 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64977 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20d00 }
64978 },
64979/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64980 {
64981 { 0, 0, 0, 0 },
64982 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64983 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822d00 }
64984 },
64985/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
64986 {
64987 { 0, 0, 0, 0 },
64988 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64989 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820d00 }
64990 },
64991/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64992 {
64993 { 0, 0, 0, 0 },
64994 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64995 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40d0000 }
64996 },
64997/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64998 {
64999 { 0, 0, 0, 0 },
65000 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65001 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842d0000 }
65002 },
65003/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
65004 {
65005 { 0, 0, 0, 0 },
65006 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65007 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840d0000 }
65008 },
65009/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
65010 {
65011 { 0, 0, 0, 0 },
65012 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65013 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60d0000 }
65014 },
65015/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
65016 {
65017 { 0, 0, 0, 0 },
65018 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65019 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862d0000 }
65020 },
65021/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
65022 {
65023 { 0, 0, 0, 0 },
65024 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65025 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860d0000 }
65026 },
65027/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
65028 {
65029 { 0, 0, 0, 0 },
65030 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65031 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28d00 }
65032 },
65033/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
65034 {
65035 { 0, 0, 0, 0 },
65036 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65037 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ad00 }
65038 },
65039/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
65040 {
65041 { 0, 0, 0, 0 },
65042 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65043 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828d00 }
65044 },
65045/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
65046 {
65047 { 0, 0, 0, 0 },
65048 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65049 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48d0000 }
65050 },
65051/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
65052 {
65053 { 0, 0, 0, 0 },
65054 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65055 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ad0000 }
65056 },
65057/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
65058 {
65059 { 0, 0, 0, 0 },
65060 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65061 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848d0000 }
65062 },
65063/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
65064 {
65065 { 0, 0, 0, 0 },
65066 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65067 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cd00 }
65068 },
65069/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
65070 {
65071 { 0, 0, 0, 0 },
65072 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65073 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ed00 }
65074 },
65075/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
65076 {
65077 { 0, 0, 0, 0 },
65078 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65079 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cd00 }
65080 },
65081/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
65082 {
65083 { 0, 0, 0, 0 },
65084 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65085 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cd0000 }
65086 },
65087/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
65088 {
65089 { 0, 0, 0, 0 },
65090 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65091 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ed0000 }
65092 },
65093/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
65094 {
65095 { 0, 0, 0, 0 },
65096 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65097 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cd0000 }
65098 },
65099/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
65100 {
65101 { 0, 0, 0, 0 },
65102 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
65103 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cd0000 }
65104 },
65105/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
65106 {
65107 { 0, 0, 0, 0 },
65108 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
65109 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ed0000 }
65110 },
65111/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
65112 {
65113 { 0, 0, 0, 0 },
65114 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
65115 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cd0000 }
65116 },
65117/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
65118 {
65119 { 0, 0, 0, 0 },
65120 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
65121 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68d0000 }
65122 },
65123/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
65124 {
65125 { 0, 0, 0, 0 },
65126 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
65127 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ad0000 }
65128 },
65129/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
65130 {
65131 { 0, 0, 0, 0 },
65132 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
65133 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868d0000 }
65134 },
65135/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
65136 {
65137 { 0, 0, 0, 0 },
65138 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
65139 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x918000 }
65140 },
65141/* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
65142 {
65143 { 0, 0, 0, 0 },
65144 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
65145 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x91a000 }
65146 },
65147/* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
65148 {
65149 { 0, 0, 0, 0 },
65150 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
65151 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x91b000 }
65152 },
65153/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
65154 {
65155 { 0, 0, 0, 0 },
65156 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
65157 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x918400 }
65158 },
65159/* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
65160 {
65161 { 0, 0, 0, 0 },
65162 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
65163 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x91a400 }
65164 },
65165/* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
65166 {
65167 { 0, 0, 0, 0 },
65168 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
65169 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x91b400 }
65170 },
65171/* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
65172 {
65173 { 0, 0, 0, 0 },
65174 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65175 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x918600 }
65176 },
65177/* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
65178 {
65179 { 0, 0, 0, 0 },
65180 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65181 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x91a600 }
65182 },
65183/* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
65184 {
65185 { 0, 0, 0, 0 },
65186 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65187 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x91b600 }
65188 },
65189/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
65190 {
65191 { 0, 0, 0, 0 },
65192 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65193 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x91880000 }
65194 },
65195/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
65196 {
65197 { 0, 0, 0, 0 },
65198 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65199 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x91a80000 }
65200 },
65201/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
65202 {
65203 { 0, 0, 0, 0 },
65204 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65205 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x91b80000 }
65206 },
65207/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
65208 {
65209 { 0, 0, 0, 0 },
65210 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65211 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x918c0000 }
65212 },
65213/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
65214 {
65215 { 0, 0, 0, 0 },
65216 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65217 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x91ac0000 }
65218 },
65219/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
65220 {
65221 { 0, 0, 0, 0 },
65222 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65223 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x91bc0000 }
65224 },
65225/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
65226 {
65227 { 0, 0, 0, 0 },
65228 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65229 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x918a0000 }
65230 },
65231/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
65232 {
65233 { 0, 0, 0, 0 },
65234 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65235 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91aa0000 }
65236 },
65237/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
65238 {
65239 { 0, 0, 0, 0 },
65240 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65241 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91ba0000 }
65242 },
65243/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
65244 {
65245 { 0, 0, 0, 0 },
65246 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65247 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x918e0000 }
65248 },
65249/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
65250 {
65251 { 0, 0, 0, 0 },
65252 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65253 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91ae0000 }
65254 },
65255/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
65256 {
65257 { 0, 0, 0, 0 },
65258 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65259 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91be0000 }
65260 },
65261/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
65262 {
65263 { 0, 0, 0, 0 },
65264 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65265 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x918b0000 }
65266 },
65267/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
65268 {
65269 { 0, 0, 0, 0 },
65270 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65271 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91ab0000 }
65272 },
65273/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
65274 {
65275 { 0, 0, 0, 0 },
65276 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65277 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91bb0000 }
65278 },
65279/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
65280 {
65281 { 0, 0, 0, 0 },
65282 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
65283 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x918f0000 }
65284 },
65285/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
65286 {
65287 { 0, 0, 0, 0 },
65288 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65289 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x91af0000 }
65290 },
65291/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
65292 {
65293 { 0, 0, 0, 0 },
65294 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65295 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x91bf0000 }
65296 },
65297/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
65298 {
65299 { 0, 0, 0, 0 },
65300 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
65301 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x91c00000 }
65302 },
65303/* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
65304 {
65305 { 0, 0, 0, 0 },
65306 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
65307 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x91e00000 }
65308 },
65309/* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
65310 {
65311 { 0, 0, 0, 0 },
65312 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
65313 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x91f00000 }
65314 },
65315/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
65316 {
65317 { 0, 0, 0, 0 },
65318 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
65319 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x91c40000 }
65320 },
65321/* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
65322 {
65323 { 0, 0, 0, 0 },
65324 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
65325 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x91e40000 }
65326 },
65327/* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
65328 {
65329 { 0, 0, 0, 0 },
65330 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
65331 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x91f40000 }
65332 },
65333/* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
65334 {
65335 { 0, 0, 0, 0 },
65336 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65337 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x91c60000 }
65338 },
65339/* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
65340 {
65341 { 0, 0, 0, 0 },
65342 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65343 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x91e60000 }
65344 },
65345/* and.w${G} ${Dsp-16-u16},[$Dst16An] */
65346 {
65347 { 0, 0, 0, 0 },
65348 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
65349 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x91f60000 }
65350 },
65351/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
65352 {
65353 { 0, 0, 0, 0 },
65354 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65355 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x91c80000 }
65356 },
65357/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
65358 {
65359 { 0, 0, 0, 0 },
65360 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65361 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x91e80000 }
65362 },
65363/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
65364 {
65365 { 0, 0, 0, 0 },
65366 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65367 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x91f80000 }
65368 },
65369/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
65370 {
65371 { 0, 0, 0, 0 },
65372 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65373 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x91cc0000 }
65374 },
65375/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
65376 {
65377 { 0, 0, 0, 0 },
65378 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65379 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x91ec0000 }
65380 },
65381/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
65382 {
65383 { 0, 0, 0, 0 },
65384 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65385 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x91fc0000 }
65386 },
65387/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
65388 {
65389 { 0, 0, 0, 0 },
65390 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65391 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ca0000 }
65392 },
65393/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
65394 {
65395 { 0, 0, 0, 0 },
65396 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65397 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ea0000 }
65398 },
65399/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
65400 {
65401 { 0, 0, 0, 0 },
65402 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65403 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x91fa0000 }
65404 },
65405/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
65406 {
65407 { 0, 0, 0, 0 },
65408 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65409 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ce0000 }
65410 },
65411/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
65412 {
65413 { 0, 0, 0, 0 },
65414 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65415 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ee0000 }
65416 },
65417/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
65418 {
65419 { 0, 0, 0, 0 },
65420 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65421 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x91fe0000 }
65422 },
65423/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
65424 {
65425 { 0, 0, 0, 0 },
65426 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65427 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x91cb0000 }
65428 },
65429/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
65430 {
65431 { 0, 0, 0, 0 },
65432 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65433 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x91eb0000 }
65434 },
65435/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
65436 {
65437 { 0, 0, 0, 0 },
65438 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65439 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x91fb0000 }
65440 },
65441/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
65442 {
65443 { 0, 0, 0, 0 },
65444 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
65445 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x91cf0000 }
65446 },
65447/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
65448 {
65449 { 0, 0, 0, 0 },
65450 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
65451 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x91ef0000 }
65452 },
65453/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
65454 {
65455 { 0, 0, 0, 0 },
65456 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
65457 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x91ff0000 }
65458 },
65459/* and.w${G} $Src16RnHI,$Dst16RnHI */
65460 {
65461 { 0, 0, 0, 0 },
65462 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
65463 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9100 }
65464 },
65465/* and.w${G} $Src16AnHI,$Dst16RnHI */
65466 {
65467 { 0, 0, 0, 0 },
65468 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
65469 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9140 }
65470 },
65471/* and.w${G} [$Src16An],$Dst16RnHI */
65472 {
65473 { 0, 0, 0, 0 },
65474 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
65475 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9160 }
65476 },
65477/* and.w${G} $Src16RnHI,$Dst16AnHI */
65478 {
65479 { 0, 0, 0, 0 },
65480 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
65481 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9104 }
65482 },
65483/* and.w${G} $Src16AnHI,$Dst16AnHI */
65484 {
65485 { 0, 0, 0, 0 },
65486 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
65487 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9144 }
65488 },
65489/* and.w${G} [$Src16An],$Dst16AnHI */
65490 {
65491 { 0, 0, 0, 0 },
65492 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
65493 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9164 }
65494 },
65495/* and.w${G} $Src16RnHI,[$Dst16An] */
65496 {
65497 { 0, 0, 0, 0 },
65498 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
65499 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9106 }
65500 },
65501/* and.w${G} $Src16AnHI,[$Dst16An] */
65502 {
65503 { 0, 0, 0, 0 },
65504 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
65505 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9146 }
65506 },
65507/* and.w${G} [$Src16An],[$Dst16An] */
65508 {
65509 { 0, 0, 0, 0 },
65510 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65511 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9166 }
65512 },
65513/* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
65514 {
65515 { 0, 0, 0, 0 },
65516 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65517 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x910800 }
65518 },
65519/* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
65520 {
65521 { 0, 0, 0, 0 },
65522 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65523 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x914800 }
65524 },
65525/* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
65526 {
65527 { 0, 0, 0, 0 },
65528 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65529 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x916800 }
65530 },
65531/* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
65532 {
65533 { 0, 0, 0, 0 },
65534 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65535 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x910c0000 }
65536 },
65537/* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
65538 {
65539 { 0, 0, 0, 0 },
65540 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65541 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x914c0000 }
65542 },
65543/* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
65544 {
65545 { 0, 0, 0, 0 },
65546 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65547 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x916c0000 }
65548 },
65549/* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
65550 {
65551 { 0, 0, 0, 0 },
65552 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65553 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x910a00 }
65554 },
65555/* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
65556 {
65557 { 0, 0, 0, 0 },
65558 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65559 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x914a00 }
65560 },
65561/* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
65562 {
65563 { 0, 0, 0, 0 },
65564 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65565 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x916a00 }
65566 },
65567/* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
65568 {
65569 { 0, 0, 0, 0 },
65570 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65571 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x910e0000 }
65572 },
65573/* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
65574 {
65575 { 0, 0, 0, 0 },
65576 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65577 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x914e0000 }
65578 },
65579/* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
65580 {
65581 { 0, 0, 0, 0 },
65582 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65583 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x916e0000 }
65584 },
65585/* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
65586 {
65587 { 0, 0, 0, 0 },
65588 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65589 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x910b00 }
65590 },
65591/* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
65592 {
65593 { 0, 0, 0, 0 },
65594 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65595 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x914b00 }
65596 },
65597/* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
65598 {
65599 { 0, 0, 0, 0 },
65600 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65601 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x916b00 }
65602 },
65603/* and.w${G} $Src16RnHI,${Dsp-16-u16} */
65604 {
65605 { 0, 0, 0, 0 },
65606 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
65607 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x910f0000 }
65608 },
65609/* and.w${G} $Src16AnHI,${Dsp-16-u16} */
65610 {
65611 { 0, 0, 0, 0 },
65612 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
65613 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x914f0000 }
65614 },
65615/* and.w${G} [$Src16An],${Dsp-16-u16} */
65616 {
65617 { 0, 0, 0, 0 },
65618 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
65619 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x916f0000 }
65620 },
65621/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
65622 {
65623 { 0, 0, 0, 0 },
65624 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65625 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x908000 }
65626 },
65627/* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
65628 {
65629 { 0, 0, 0, 0 },
65630 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
65631 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x90a000 }
65632 },
65633/* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
65634 {
65635 { 0, 0, 0, 0 },
65636 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
65637 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x90b000 }
65638 },
65639/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
65640 {
65641 { 0, 0, 0, 0 },
65642 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65643 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x908400 }
65644 },
65645/* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
65646 {
65647 { 0, 0, 0, 0 },
65648 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
65649 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x90a400 }
65650 },
65651/* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
65652 {
65653 { 0, 0, 0, 0 },
65654 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
65655 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x90b400 }
65656 },
65657/* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
65658 {
65659 { 0, 0, 0, 0 },
65660 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65661 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x908600 }
65662 },
65663/* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
65664 {
65665 { 0, 0, 0, 0 },
65666 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65667 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x90a600 }
65668 },
65669/* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
65670 {
65671 { 0, 0, 0, 0 },
65672 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65673 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x90b600 }
65674 },
65675/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
65676 {
65677 { 0, 0, 0, 0 },
65678 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65679 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x90880000 }
65680 },
65681/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
65682 {
65683 { 0, 0, 0, 0 },
65684 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65685 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x90a80000 }
65686 },
65687/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
65688 {
65689 { 0, 0, 0, 0 },
65690 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65691 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x90b80000 }
65692 },
65693/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
65694 {
65695 { 0, 0, 0, 0 },
65696 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65697 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x908c0000 }
65698 },
65699/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
65700 {
65701 { 0, 0, 0, 0 },
65702 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65703 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x90ac0000 }
65704 },
65705/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
65706 {
65707 { 0, 0, 0, 0 },
65708 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65709 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x90bc0000 }
65710 },
65711/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
65712 {
65713 { 0, 0, 0, 0 },
65714 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65715 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x908a0000 }
65716 },
65717/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
65718 {
65719 { 0, 0, 0, 0 },
65720 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65721 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90aa0000 }
65722 },
65723/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
65724 {
65725 { 0, 0, 0, 0 },
65726 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65727 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90ba0000 }
65728 },
65729/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
65730 {
65731 { 0, 0, 0, 0 },
65732 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65733 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x908e0000 }
65734 },
65735/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
65736 {
65737 { 0, 0, 0, 0 },
65738 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65739 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90ae0000 }
65740 },
65741/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
65742 {
65743 { 0, 0, 0, 0 },
65744 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65745 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90be0000 }
65746 },
65747/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
65748 {
65749 { 0, 0, 0, 0 },
65750 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65751 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x908b0000 }
65752 },
65753/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
65754 {
65755 { 0, 0, 0, 0 },
65756 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65757 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90ab0000 }
65758 },
65759/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
65760 {
65761 { 0, 0, 0, 0 },
65762 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65763 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90bb0000 }
65764 },
65765/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
65766 {
65767 { 0, 0, 0, 0 },
65768 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
65769 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x908f0000 }
65770 },
65771/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
65772 {
65773 { 0, 0, 0, 0 },
65774 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65775 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x90af0000 }
65776 },
65777/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
65778 {
65779 { 0, 0, 0, 0 },
65780 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65781 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x90bf0000 }
65782 },
65783/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
65784 {
65785 { 0, 0, 0, 0 },
65786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65787 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x90c00000 }
65788 },
65789/* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
65790 {
65791 { 0, 0, 0, 0 },
65792 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
65793 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x90e00000 }
65794 },
65795/* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
65796 {
65797 { 0, 0, 0, 0 },
65798 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
65799 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x90f00000 }
65800 },
65801/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
65802 {
65803 { 0, 0, 0, 0 },
65804 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65805 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x90c40000 }
65806 },
65807/* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
65808 {
65809 { 0, 0, 0, 0 },
65810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
65811 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x90e40000 }
65812 },
65813/* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
65814 {
65815 { 0, 0, 0, 0 },
65816 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
65817 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x90f40000 }
65818 },
65819/* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
65820 {
65821 { 0, 0, 0, 0 },
65822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65823 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x90c60000 }
65824 },
65825/* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
65826 {
65827 { 0, 0, 0, 0 },
65828 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65829 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x90e60000 }
65830 },
65831/* and.b${G} ${Dsp-16-u16},[$Dst16An] */
65832 {
65833 { 0, 0, 0, 0 },
65834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
65835 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x90f60000 }
65836 },
65837/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
65838 {
65839 { 0, 0, 0, 0 },
65840 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65841 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x90c80000 }
65842 },
65843/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
65844 {
65845 { 0, 0, 0, 0 },
65846 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65847 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x90e80000 }
65848 },
65849/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
65850 {
65851 { 0, 0, 0, 0 },
65852 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65853 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x90f80000 }
65854 },
65855/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
65856 {
65857 { 0, 0, 0, 0 },
65858 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65859 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x90cc0000 }
65860 },
65861/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
65862 {
65863 { 0, 0, 0, 0 },
65864 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65865 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x90ec0000 }
65866 },
65867/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
65868 {
65869 { 0, 0, 0, 0 },
65870 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65871 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x90fc0000 }
65872 },
65873/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
65874 {
65875 { 0, 0, 0, 0 },
65876 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65877 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ca0000 }
65878 },
65879/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
65880 {
65881 { 0, 0, 0, 0 },
65882 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65883 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ea0000 }
65884 },
65885/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
65886 {
65887 { 0, 0, 0, 0 },
65888 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65889 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x90fa0000 }
65890 },
65891/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
65892 {
65893 { 0, 0, 0, 0 },
65894 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65895 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ce0000 }
65896 },
65897/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
65898 {
65899 { 0, 0, 0, 0 },
65900 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65901 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ee0000 }
65902 },
65903/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
65904 {
65905 { 0, 0, 0, 0 },
65906 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65907 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x90fe0000 }
65908 },
65909/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
65910 {
65911 { 0, 0, 0, 0 },
65912 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65913 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x90cb0000 }
65914 },
65915/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
65916 {
65917 { 0, 0, 0, 0 },
65918 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65919 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x90eb0000 }
65920 },
65921/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
65922 {
65923 { 0, 0, 0, 0 },
65924 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65925 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x90fb0000 }
65926 },
65927/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
65928 {
65929 { 0, 0, 0, 0 },
65930 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
65931 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x90cf0000 }
65932 },
65933/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
65934 {
65935 { 0, 0, 0, 0 },
65936 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
65937 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x90ef0000 }
65938 },
65939/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
65940 {
65941 { 0, 0, 0, 0 },
65942 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
65943 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x90ff0000 }
65944 },
65945/* and.b${G} $Src16RnQI,$Dst16RnQI */
65946 {
65947 { 0, 0, 0, 0 },
65948 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
65949 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9000 }
65950 },
65951/* and.b${G} $Src16AnQI,$Dst16RnQI */
65952 {
65953 { 0, 0, 0, 0 },
65954 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
65955 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9040 }
65956 },
65957/* and.b${G} [$Src16An],$Dst16RnQI */
65958 {
65959 { 0, 0, 0, 0 },
65960 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65961 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9060 }
65962 },
65963/* and.b${G} $Src16RnQI,$Dst16AnQI */
65964 {
65965 { 0, 0, 0, 0 },
65966 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
65967 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9004 }
65968 },
65969/* and.b${G} $Src16AnQI,$Dst16AnQI */
65970 {
65971 { 0, 0, 0, 0 },
65972 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
65973 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9044 }
65974 },
65975/* and.b${G} [$Src16An],$Dst16AnQI */
65976 {
65977 { 0, 0, 0, 0 },
65978 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65979 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9064 }
65980 },
65981/* and.b${G} $Src16RnQI,[$Dst16An] */
65982 {
65983 { 0, 0, 0, 0 },
65984 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
65985 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9006 }
65986 },
65987/* and.b${G} $Src16AnQI,[$Dst16An] */
65988 {
65989 { 0, 0, 0, 0 },
65990 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
65991 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9046 }
65992 },
65993/* and.b${G} [$Src16An],[$Dst16An] */
65994 {
65995 { 0, 0, 0, 0 },
65996 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65997 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9066 }
65998 },
65999/* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
66000 {
66001 { 0, 0, 0, 0 },
66002 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66003 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x900800 }
66004 },
66005/* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
66006 {
66007 { 0, 0, 0, 0 },
66008 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66009 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x904800 }
66010 },
66011/* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
66012 {
66013 { 0, 0, 0, 0 },
66014 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66015 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x906800 }
66016 },
66017/* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
66018 {
66019 { 0, 0, 0, 0 },
66020 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66021 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x900c0000 }
66022 },
66023/* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
66024 {
66025 { 0, 0, 0, 0 },
66026 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66027 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x904c0000 }
66028 },
66029/* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
66030 {
66031 { 0, 0, 0, 0 },
66032 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66033 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x906c0000 }
66034 },
66035/* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
66036 {
66037 { 0, 0, 0, 0 },
66038 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66039 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x900a00 }
66040 },
66041/* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
66042 {
66043 { 0, 0, 0, 0 },
66044 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66045 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x904a00 }
66046 },
66047/* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
66048 {
66049 { 0, 0, 0, 0 },
66050 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66051 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x906a00 }
66052 },
66053/* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
66054 {
66055 { 0, 0, 0, 0 },
66056 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66057 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x900e0000 }
66058 },
66059/* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
66060 {
66061 { 0, 0, 0, 0 },
66062 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66063 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x904e0000 }
66064 },
66065/* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
66066 {
66067 { 0, 0, 0, 0 },
66068 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66069 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x906e0000 }
66070 },
66071/* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
66072 {
66073 { 0, 0, 0, 0 },
66074 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66075 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x900b00 }
66076 },
66077/* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
66078 {
66079 { 0, 0, 0, 0 },
66080 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66081 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x904b00 }
66082 },
66083/* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
66084 {
66085 { 0, 0, 0, 0 },
66086 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66087 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x906b00 }
66088 },
66089/* and.b${G} $Src16RnQI,${Dsp-16-u16} */
66090 {
66091 { 0, 0, 0, 0 },
66092 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
66093 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x900f0000 }
66094 },
66095/* and.b${G} $Src16AnQI,${Dsp-16-u16} */
66096 {
66097 { 0, 0, 0, 0 },
66098 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
66099 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x904f0000 }
66100 },
66101/* and.b${G} [$Src16An],${Dsp-16-u16} */
66102 {
66103 { 0, 0, 0, 0 },
66104 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
66105 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x906f0000 }
66106 },
66107/* and.b${S} #${Imm-8-QI},r0l */
66108 {
66109 { 0, 0, 0, 0 },
66110 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
66111 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9400 }
66112 },
66113/* and.b${S} #${Imm-8-QI},r0h */
66114 {
66115 { 0, 0, 0, 0 },
66116 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
66117 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9300 }
66118 },
66119/* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
66120 {
66121 { 0, 0, 0, 0 },
66122 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66123 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x950000 }
66124 },
66125/* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
66126 {
66127 { 0, 0, 0, 0 },
66128 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66129 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x960000 }
66130 },
66131/* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
66132 {
66133 { 0, 0, 0, 0 },
66134 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
66135 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x97000000 }
66136 },
66137/* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
66138 {
66139 { 0, 0, 0, 0 },
66140 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
66141 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893f0000 }
66142 },
66143/* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
66144 {
66145 { 0, 0, 0, 0 },
66146 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
66147 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81bf0000 }
66148 },
66149/* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
66150 {
66151 { 0, 0, 0, 0 },
66152 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66153 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813f0000 }
66154 },
66155/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
66156 {
66157 { 0, 0, 0, 0 },
66158 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66159 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833f0000 }
66160 },
66161/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
66162 {
66163 { 0, 0, 0, 0 },
66164 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66165 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83bf0000 }
66166 },
66167/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
66168 {
66169 { 0, 0, 0, 0 },
66170 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66171 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ff0000 }
66172 },
66173/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
66174 {
66175 { 0, 0, 0, 0 },
66176 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66177 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853f0000 }
66178 },
66179/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
66180 {
66181 { 0, 0, 0, 0 },
66182 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66183 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85bf0000 }
66184 },
66185/* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
66186 {
66187 { 0, 0, 0, 0 },
66188 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
66189 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ff0000 }
66190 },
66191/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
66192 {
66193 { 0, 0, 0, 0 },
66194 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
66195 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ff0000 }
66196 },
66197/* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
66198 {
66199 { 0, 0, 0, 0 },
66200 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66201 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873f0000 }
66202 },
66203/* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
66204 {
66205 { 0, 0, 0, 0 },
66206 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
66207 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87bf0000 }
66208 },
66209/* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
66210 {
66211 { 0, 0, 0, 0 },
66212 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
66213 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883f00 }
66214 },
66215/* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
66216 {
66217 { 0, 0, 0, 0 },
66218 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
66219 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80bf00 }
66220 },
66221/* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
66222 {
66223 { 0, 0, 0, 0 },
66224 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66225 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803f00 }
66226 },
66227/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
66228 {
66229 { 0, 0, 0, 0 },
66230 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66231 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823f0000 }
66232 },
66233/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
66234 {
66235 { 0, 0, 0, 0 },
66236 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66237 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82bf0000 }
66238 },
66239/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
66240 {
66241 { 0, 0, 0, 0 },
66242 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66243 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ff0000 }
66244 },
66245/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
66246 {
66247 { 0, 0, 0, 0 },
66248 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66249 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843f0000 }
66250 },
66251/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
66252 {
66253 { 0, 0, 0, 0 },
66254 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66255 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84bf0000 }
66256 },
66257/* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
66258 {
66259 { 0, 0, 0, 0 },
66260 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
66261 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ff0000 }
66262 },
66263/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
66264 {
66265 { 0, 0, 0, 0 },
66266 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
66267 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ff0000 }
66268 },
66269/* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
66270 {
66271 { 0, 0, 0, 0 },
66272 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66273 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863f0000 }
66274 },
66275/* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
66276 {
66277 { 0, 0, 0, 0 },
66278 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
66279 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86bf0000 }
66280 },
66281/* and.w${G} #${Imm-16-HI},$Dst16RnHI */
66282 {
66283 { 0, 0, 0, 0 },
66284 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
66285 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77200000 }
66286 },
66287/* and.w${G} #${Imm-16-HI},$Dst16AnHI */
66288 {
66289 { 0, 0, 0, 0 },
66290 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
66291 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77240000 }
66292 },
66293/* and.w${G} #${Imm-16-HI},[$Dst16An] */
66294 {
66295 { 0, 0, 0, 0 },
66296 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
66297 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77260000 }
66298 },
66299/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
66300 {
66301 { 0, 0, 0, 0 },
66302 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66303 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77280000 }
66304 },
66305/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
66306 {
66307 { 0, 0, 0, 0 },
66308 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66309 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x772a0000 }
66310 },
66311/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
66312 {
66313 { 0, 0, 0, 0 },
66314 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66315 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x772b0000 }
66316 },
66317/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
66318 {
66319 { 0, 0, 0, 0 },
66320 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66321 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x772c0000 }
66322 },
66323/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
66324 {
66325 { 0, 0, 0, 0 },
66326 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66327 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x772e0000 }
66328 },
66329/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
66330 {
66331 { 0, 0, 0, 0 },
66332 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
66333 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x772f0000 }
66334 },
66335/* and.b${G} #${Imm-16-QI},$Dst16RnQI */
66336 {
66337 { 0, 0, 0, 0 },
66338 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
66339 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x762000 }
66340 },
66341/* and.b${G} #${Imm-16-QI},$Dst16AnQI */
66342 {
66343 { 0, 0, 0, 0 },
66344 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
66345 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x762400 }
66346 },
66347/* and.b${G} #${Imm-16-QI},[$Dst16An] */
66348 {
66349 { 0, 0, 0, 0 },
66350 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
66351 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x762600 }
66352 },
66353/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
66354 {
66355 { 0, 0, 0, 0 },
66356 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66357 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76280000 }
66358 },
66359/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
66360 {
66361 { 0, 0, 0, 0 },
66362 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66363 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x762a0000 }
66364 },
66365/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
66366 {
66367 { 0, 0, 0, 0 },
66368 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66369 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x762b0000 }
66370 },
66371/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
66372 {
66373 { 0, 0, 0, 0 },
66374 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66375 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x762c0000 }
66376 },
66377/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
66378 {
66379 { 0, 0, 0, 0 },
66380 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66381 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x762e0000 }
66382 },
66383/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
66384 {
66385 { 0, 0, 0, 0 },
66386 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
66387 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x762f0000 }
66388 },
66389/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
66390 {
66391 { 0, 0, 0, 0 },
66392 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
c6552317 66393 & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
49f58d10
JB		 66394 },
66395/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66396 {
66397 { 0, 0, 0, 0 },
66398 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66399 & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
49f58d10
JB		 66400 },
66401/* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66402 {
66403 { 0, 0, 0, 0 },
66404 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66405 & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
49f58d10
JB		 66406 },
66407/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
66408 {
66409 { 0, 0, 0, 0 },
66410 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
c6552317 66411 & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
49f58d10
JB		 66412 },
66413/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66414 {
66415 { 0, 0, 0, 0 },
66416 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
c6552317 66417 & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
49f58d10
JB		 66418 },
66419/* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
66420 {
66421 { 0, 0, 0, 0 },
66422 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
c6552317 66423 & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
49f58d10
JB		 66424 },
66425/* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
66426 {
66427 { 0, 0, 0, 0 },
66428 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
c6552317 66429 & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
49f58d10
JB		 66430 },
66431/* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
66432 {
66433 { 0, 0, 0, 0 },
66434 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
c6552317 66435 & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
49f58d10
JB		 66436 },
66437/* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
66438 {
66439 { 0, 0, 0, 0 },
66440 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
c6552317 66441 & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
49f58d10
JB		 66442 },
66443/* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
66444 {
66445 { 0, 0, 0, 0 },
66446 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
c6552317 66447 & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
49f58d10
JB		 66448 },
66449/* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
66450 {
66451 { 0, 0, 0, 0 },
66452 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
c6552317 66453 & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
49f58d10
JB		 66454 },
66455/* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
66456 {
66457 { 0, 0, 0, 0 },
66458 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
c6552317 66459 & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
49f58d10
JB		 66460 },
66461/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
66462 {
66463 { 0, 0, 0, 0 },
66464 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
c6552317 66465 & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
49f58d10
JB		 66466 },
66467/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66468 {
66469 { 0, 0, 0, 0 },
66470 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66471 & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
49f58d10
JB		 66472 },
66473/* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66474 {
66475 { 0, 0, 0, 0 },
66476 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66477 & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
49f58d10
JB		 66478 },
66479/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
66480 {
66481 { 0, 0, 0, 0 },
66482 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
c6552317 66483 & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
49f58d10
JB		 66484 },
66485/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66486 {
66487 { 0, 0, 0, 0 },
66488 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
c6552317 66489 & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
49f58d10
JB		 66490 },
66491/* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
66492 {
66493 { 0, 0, 0, 0 },
66494 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
c6552317 66495 & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
49f58d10
JB		 66496 },
66497/* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
66498 {
66499 { 0, 0, 0, 0 },
66500 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
c6552317 66501 & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
49f58d10
JB		 66502 },
66503/* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
66504 {
66505 { 0, 0, 0, 0 },
66506 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
c6552317 66507 & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
49f58d10
JB		 66508 },
66509/* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
66510 {
66511 { 0, 0, 0, 0 },
66512 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
c6552317 66513 & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
49f58d10
JB		 66514 },
66515/* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
66516 {
66517 { 0, 0, 0, 0 },
66518 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
c6552317 66519 & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
49f58d10
JB		 66520 },
66521/* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
66522 {
66523 { 0, 0, 0, 0 },
66524 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
c6552317 66525 & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
49f58d10
JB		 66526 },
66527/* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
66528 {
66529 { 0, 0, 0, 0 },
66530 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
c6552317 66531 & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
49f58d10
JB		 66532 },
66533/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
66534 {
66535 { 0, 0, 0, 0 },
66536 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
c6552317 66537 & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
49f58d10
JB		 66538 },
66539/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66540 {
66541 { 0, 0, 0, 0 },
66542 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66543 & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
49f58d10
JB		 66544 },
66545/* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66546 {
66547 { 0, 0, 0, 0 },
66548 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66549 & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
49f58d10
JB		 66550 },
66551/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
66552 {
66553 { 0, 0, 0, 0 },
66554 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
c6552317 66555 & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
49f58d10
JB		 66556 },
66557/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66558 {
66559 { 0, 0, 0, 0 },
66560 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
c6552317 66561 & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
49f58d10
JB		 66562 },
66563/* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
66564 {
66565 { 0, 0, 0, 0 },
66566 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
c6552317 66567 & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
49f58d10
JB		 66568 },
66569/* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
66570 {
66571 { 0, 0, 0, 0 },
66572 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
c6552317 66573 & ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
49f58d10
JB		 66574 },
66575/* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
66576 {
66577 { 0, 0, 0, 0 },
66578 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
c6552317 66579 & ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
49f58d10
JB		 66580 },
66581/* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
66582 {
66583 { 0, 0, 0, 0 },
66584 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
c6552317 66585 & ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
49f58d10
JB		 66586 },
66587/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
66588 {
66589 { 0, 0, 0, 0 },
66590 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
c6552317 66591 & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
49f58d10
JB		 66592 },
66593/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66594 {
66595 { 0, 0, 0, 0 },
66596 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66597 & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
49f58d10
JB		 66598 },
66599/* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66600 {
66601 { 0, 0, 0, 0 },
66602 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
c6552317 66603 & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
49f58d10
JB		 66604 },
66605/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
66606 {
66607 { 0, 0, 0, 0 },
66608 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
c6552317 66609 & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
49f58d10
JB		 66610 },
66611/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66612 {
66613 { 0, 0, 0, 0 },
66614 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
c6552317 66615 & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
49f58d10
JB		 66616 },
66617/* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
66618 {
66619 { 0, 0, 0, 0 },
66620 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
c6552317 66621 & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
49f58d10
JB		 66622 },
66623/* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
66624 {
66625 { 0, 0, 0, 0 },
66626 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
c6552317 66627 & ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
49f58d10
JB		 66628 },
66629/* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
66630 {
66631 { 0, 0, 0, 0 },
66632 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
c6552317 66633 & ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
49f58d10
JB		 66634 },
66635/* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
66636 {
66637 { 0, 0, 0, 0 },
66638 { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
c6552317 66639 & ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
49f58d10
JB		 66640 },
66641/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66642 {
66643 { 0, 0, 0, 0 },
66644 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66645 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980200 }
66646 },
66647/* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
66648 {
66649 { 0, 0, 0, 0 },
66650 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66651 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982200 }
66652 },
66653/* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
66654 {
66655 { 0, 0, 0, 0 },
66656 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66657 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983200 }
66658 },
66659/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66660 {
66661 { 0, 0, 0, 0 },
66662 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66663 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908200 }
66664 },
66665/* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
66666 {
66667 { 0, 0, 0, 0 },
66668 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66669 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a200 }
66670 },
66671/* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
66672 {
66673 { 0, 0, 0, 0 },
66674 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66675 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b200 }
66676 },
66677/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66678 {
66679 { 0, 0, 0, 0 },
66680 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66681 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900200 }
66682 },
66683/* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
66684 {
66685 { 0, 0, 0, 0 },
66686 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66687 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902200 }
66688 },
66689/* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
66690 {
66691 { 0, 0, 0, 0 },
66692 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66693 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903200 }
66694 },
66695/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66696 {
66697 { 0, 0, 0, 0 },
66698 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66699 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92020000 }
66700 },
66701/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66702 {
66703 { 0, 0, 0, 0 },
66704 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66705 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92220000 }
66706 },
66707/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66708 {
66709 { 0, 0, 0, 0 },
66710 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66711 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92320000 }
66712 },
66713/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66714 {
66715 { 0, 0, 0, 0 },
66716 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66717 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94020000 }
66718 },
66719/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66720 {
66721 { 0, 0, 0, 0 },
66722 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66723 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94220000 }
66724 },
66725/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66726 {
66727 { 0, 0, 0, 0 },
66728 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66729 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94320000 }
66730 },
66731/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66732 {
66733 { 0, 0, 0, 0 },
66734 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66735 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96020000 }
66736 },
66737/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66738 {
66739 { 0, 0, 0, 0 },
66740 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66741 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96220000 }
66742 },
66743/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66744 {
66745 { 0, 0, 0, 0 },
66746 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66747 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96320000 }
66748 },
66749/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
66750 {
66751 { 0, 0, 0, 0 },
66752 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66753 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92820000 }
66754 },
66755/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
66756 {
66757 { 0, 0, 0, 0 },
66758 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66759 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a20000 }
66760 },
66761/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
66762 {
66763 { 0, 0, 0, 0 },
66764 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66765 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b20000 }
66766 },
66767/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
66768 {
66769 { 0, 0, 0, 0 },
66770 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66771 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94820000 }
66772 },
66773/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
66774 {
66775 { 0, 0, 0, 0 },
66776 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66777 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a20000 }
66778 },
66779/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
66780 {
66781 { 0, 0, 0, 0 },
66782 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66783 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b20000 }
66784 },
66785/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
66786 {
66787 { 0, 0, 0, 0 },
66788 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66789 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c20000 }
66790 },
66791/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
66792 {
66793 { 0, 0, 0, 0 },
66794 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66795 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e20000 }
66796 },
66797/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
66798 {
66799 { 0, 0, 0, 0 },
66800 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66801 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f20000 }
66802 },
66803/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
66804 {
66805 { 0, 0, 0, 0 },
66806 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66807 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c20000 }
66808 },
66809/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
66810 {
66811 { 0, 0, 0, 0 },
66812 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66813 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e20000 }
66814 },
66815/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
66816 {
66817 { 0, 0, 0, 0 },
66818 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66819 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f20000 }
66820 },
66821/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
66822 {
66823 { 0, 0, 0, 0 },
66824 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
66825 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c20000 }
66826 },
66827/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
66828 {
66829 { 0, 0, 0, 0 },
66830 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
66831 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e20000 }
66832 },
66833/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
66834 {
66835 { 0, 0, 0, 0 },
66836 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
66837 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f20000 }
66838 },
66839/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
66840 {
66841 { 0, 0, 0, 0 },
66842 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
66843 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96820000 }
66844 },
66845/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
66846 {
66847 { 0, 0, 0, 0 },
66848 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
66849 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a20000 }
66850 },
66851/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
66852 {
66853 { 0, 0, 0, 0 },
66854 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
66855 & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b20000 }
66856 },
66857/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66858 {
66859 { 0, 0, 0, 0 },
66860 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66861 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8020000 }
66862 },
66863/* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
66864 {
66865 { 0, 0, 0, 0 },
66866 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66867 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8220000 }
66868 },
66869/* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
66870 {
66871 { 0, 0, 0, 0 },
66872 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66873 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8320000 }
66874 },
66875/* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
66876 {
66877 { 0, 0, 0, 0 },
66878 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66879 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8320000 }
66880 },
66881/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66882 {
66883 { 0, 0, 0, 0 },
66884 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66885 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0820000 }
66886 },
66887/* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
66888 {
66889 { 0, 0, 0, 0 },
66890 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66891 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a20000 }
66892 },
66893/* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
66894 {
66895 { 0, 0, 0, 0 },
66896 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66897 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b20000 }
66898 },
66899/* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
66900 {
66901 { 0, 0, 0, 0 },
66902 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66903 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b20000 }
66904 },
66905/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66906 {
66907 { 0, 0, 0, 0 },
66908 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66909 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0020000 }
66910 },
66911/* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
66912 {
66913 { 0, 0, 0, 0 },
66914 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66915 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0220000 }
66916 },
66917/* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
66918 {
66919 { 0, 0, 0, 0 },
66920 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66921 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0320000 }
66922 },
66923/* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
66924 {
66925 { 0, 0, 0, 0 },
66926 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66927 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0320000 }
66928 },
66929/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66930 {
66931 { 0, 0, 0, 0 },
66932 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66933 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2020000 }
66934 },
66935/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66936 {
66937 { 0, 0, 0, 0 },
66938 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66939 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2220000 }
66940 },
66941/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66942 {
66943 { 0, 0, 0, 0 },
66944 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66945 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2320000 }
66946 },
66947/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
66948 {
66949 { 0, 0, 0, 0 },
66950 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66951 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2320000 }
66952 },
66953/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66954 {
66955 { 0, 0, 0, 0 },
66956 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66957 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4020000 }
66958 },
66959/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66960 {
66961 { 0, 0, 0, 0 },
66962 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66963 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4220000 }
66964 },
66965/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66966 {
66967 { 0, 0, 0, 0 },
66968 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66969 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4320000 }
66970 },
66971/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
66972 {
66973 { 0, 0, 0, 0 },
66974 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66975 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4320000 }
66976 },
66977/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66978 {
66979 { 0, 0, 0, 0 },
66980 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66981 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6020000 }
66982 },
66983/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66984 {
66985 { 0, 0, 0, 0 },
66986 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66987 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6220000 }
66988 },
66989/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66990 {
66991 { 0, 0, 0, 0 },
66992 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66993 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6320000 }
66994 },
66995/* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
66996 {
66997 { 0, 0, 0, 0 },
66998 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66999 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6320000 }
67000 },
67001/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
67002 {
67003 { 0, 0, 0, 0 },
67004 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67005 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2820000 }
67006 },
67007/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
67008 {
67009 { 0, 0, 0, 0 },
67010 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67011 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a20000 }
67012 },
67013/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
67014 {
67015 { 0, 0, 0, 0 },
67016 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67017 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b20000 }
67018 },
67019/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
67020 {
67021 { 0, 0, 0, 0 },
67022 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67023 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b20000 }
67024 },
67025/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
67026 {
67027 { 0, 0, 0, 0 },
67028 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67029 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4820000 }
67030 },
67031/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
67032 {
67033 { 0, 0, 0, 0 },
67034 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67035 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a20000 }
67036 },
67037/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
67038 {
67039 { 0, 0, 0, 0 },
67040 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67041 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b20000 }
67042 },
67043/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
67044 {
67045 { 0, 0, 0, 0 },
67046 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67047 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b20000 }
67048 },
67049/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
67050 {
67051 { 0, 0, 0, 0 },
67052 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67053 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c20000 }
67054 },
67055/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
67056 {
67057 { 0, 0, 0, 0 },
67058 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67059 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e20000 }
67060 },
67061/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
67062 {
67063 { 0, 0, 0, 0 },
67064 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67065 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f20000 }
67066 },
67067/* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
67068 {
67069 { 0, 0, 0, 0 },
67070 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67071 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f20000 }
67072 },
67073/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
67074 {
67075 { 0, 0, 0, 0 },
67076 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67077 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c20000 }
67078 },
67079/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
67080 {
67081 { 0, 0, 0, 0 },
67082 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67083 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e20000 }
67084 },
67085/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
67086 {
67087 { 0, 0, 0, 0 },
67088 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67089 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f20000 }
67090 },
67091/* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
67092 {
67093 { 0, 0, 0, 0 },
67094 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67095 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f20000 }
67096 },
67097/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
67098 {
67099 { 0, 0, 0, 0 },
67100 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
67101 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c20000 }
67102 },
67103/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
67104 {
67105 { 0, 0, 0, 0 },
67106 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67107 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e20000 }
67108 },
67109/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
67110 {
67111 { 0, 0, 0, 0 },
67112 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67113 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f20000 }
67114 },
67115/* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
67116 {
67117 { 0, 0, 0, 0 },
67118 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
67119 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f20000 }
67120 },
67121/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
67122 {
67123 { 0, 0, 0, 0 },
67124 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
67125 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6820000 }
67126 },
67127/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
67128 {
67129 { 0, 0, 0, 0 },
67130 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67131 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a20000 }
67132 },
67133/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
67134 {
67135 { 0, 0, 0, 0 },
67136 { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67137 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b20000 }
67138 },
67139/* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
67140 {
67141 { 0, 0, 0, 0 },
67142 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
67143 & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b20000 }
67144 },
67145/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
67146 {
67147 { 0, 0, 0, 0 },
67148 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67149 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8020000 }
67150 },
67151/* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
67152 {
67153 { 0, 0, 0, 0 },
67154 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67155 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8220000 }
67156 },
67157/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
67158 {
67159 { 0, 0, 0, 0 },
67160 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67161 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0820000 }
67162 },
67163/* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
67164 {
67165 { 0, 0, 0, 0 },
67166 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67167 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a20000 }
67168 },
67169/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
67170 {
67171 { 0, 0, 0, 0 },
67172 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67173 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0020000 }
67174 },
67175/* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
67176 {
67177 { 0, 0, 0, 0 },
67178 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67179 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0220000 }
67180 },
67181/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
67182 {
67183 { 0, 0, 0, 0 },
67184 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67185 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2020000 }
67186 },
67187/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
67188 {
67189 { 0, 0, 0, 0 },
67190 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67191 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2220000 }
67192 },
67193/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
67194 {
67195 { 0, 0, 0, 0 },
67196 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67197 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4020000 }
67198 },
67199/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
67200 {
67201 { 0, 0, 0, 0 },
67202 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67203 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4220000 }
67204 },
67205/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
67206 {
67207 { 0, 0, 0, 0 },
67208 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67209 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6020000 }
67210 },
67211/* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
67212 {
67213 { 0, 0, 0, 0 },
67214 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67215 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6220000 }
67216 },
67217/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
67218 {
67219 { 0, 0, 0, 0 },
67220 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67221 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2820000 }
67222 },
67223/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
67224 {
67225 { 0, 0, 0, 0 },
67226 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67227 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a20000 }
67228 },
67229/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
67230 {
67231 { 0, 0, 0, 0 },
67232 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67233 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4820000 }
67234 },
67235/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
67236 {
67237 { 0, 0, 0, 0 },
67238 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67239 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a20000 }
67240 },
67241/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
67242 {
67243 { 0, 0, 0, 0 },
67244 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67245 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c20000 }
67246 },
67247/* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
67248 {
67249 { 0, 0, 0, 0 },
67250 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67251 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e20000 }
67252 },
67253/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
67254 {
67255 { 0, 0, 0, 0 },
67256 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67257 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c20000 }
67258 },
67259/* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
67260 {
67261 { 0, 0, 0, 0 },
67262 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67263 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e20000 }
67264 },
67265/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
67266 {
67267 { 0, 0, 0, 0 },
67268 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
67269 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c20000 }
67270 },
67271/* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
67272 {
67273 { 0, 0, 0, 0 },
67274 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
67275 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e20000 }
67276 },
67277/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
67278 {
67279 { 0, 0, 0, 0 },
67280 { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
67281 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6820000 }
67282 },
67283/* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
67284 {
67285 { 0, 0, 0, 0 },
67286 { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
67287 & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a20000 }
67288 },
67289/* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
67290 {
67291 { 0, 0, 0, 0 },
67292 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67293 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc802 }
67294 },
67295/* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
67296 {
67297 { 0, 0, 0, 0 },
67298 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67299 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8822 }
67300 },
67301/* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
67302 {
67303 { 0, 0, 0, 0 },
67304 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67305 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8802 }
67306 },
67307/* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
67308 {
67309 { 0, 0, 0, 0 },
67310 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67311 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc082 }
67312 },
67313/* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
67314 {
67315 { 0, 0, 0, 0 },
67316 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67317 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a2 }
67318 },
67319/* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
67320 {
67321 { 0, 0, 0, 0 },
67322 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67323 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8082 }
67324 },
67325/* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
67326 {
67327 { 0, 0, 0, 0 },
67328 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67329 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc002 }
67330 },
67331/* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
67332 {
67333 { 0, 0, 0, 0 },
67334 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67335 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8022 }
67336 },
67337/* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
67338 {
67339 { 0, 0, 0, 0 },
67340 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67341 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8002 }
67342 },
67343/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
67344 {
67345 { 0, 0, 0, 0 },
67346 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67347 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20200 }
67348 },
67349/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
67350 {
67351 { 0, 0, 0, 0 },
67352 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67353 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822200 }
67354 },
67355/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
67356 {
67357 { 0, 0, 0, 0 },
67358 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67359 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820200 }
67360 },
67361/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
67362 {
67363 { 0, 0, 0, 0 },
67364 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67365 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4020000 }
67366 },
67367/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
67368 {
67369 { 0, 0, 0, 0 },
67370 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67371 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84220000 }
67372 },
67373/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
67374 {
67375 { 0, 0, 0, 0 },
67376 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67377 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84020000 }
67378 },
67379/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
67380 {
67381 { 0, 0, 0, 0 },
67382 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67383 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6020000 }
67384 },
67385/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
67386 {
67387 { 0, 0, 0, 0 },
67388 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67389 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86220000 }
67390 },
67391/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
67392 {
67393 { 0, 0, 0, 0 },
67394 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67395 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86020000 }
67396 },
67397/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
67398 {
67399 { 0, 0, 0, 0 },
67400 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67401 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28200 }
67402 },
67403/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
67404 {
67405 { 0, 0, 0, 0 },
67406 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67407 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a200 }
67408 },
67409/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
67410 {
67411 { 0, 0, 0, 0 },
67412 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67413 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828200 }
67414 },
67415/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
67416 {
67417 { 0, 0, 0, 0 },
67418 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67419 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4820000 }
67420 },
67421/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
67422 {
67423 { 0, 0, 0, 0 },
67424 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67425 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a20000 }
67426 },
67427/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
67428 {
67429 { 0, 0, 0, 0 },
67430 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67431 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84820000 }
67432 },
67433/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
67434 {
67435 { 0, 0, 0, 0 },
67436 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67437 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c200 }
67438 },
67439/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
67440 {
67441 { 0, 0, 0, 0 },
67442 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67443 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e200 }
67444 },
67445/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
67446 {
67447 { 0, 0, 0, 0 },
67448 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67449 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c200 }
67450 },
67451/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
67452 {
67453 { 0, 0, 0, 0 },
67454 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67455 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c20000 }
67456 },
67457/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
67458 {
67459 { 0, 0, 0, 0 },
67460 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67461 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e20000 }
67462 },
67463/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
67464 {
67465 { 0, 0, 0, 0 },
67466 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67467 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c20000 }
67468 },
67469/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
67470 {
67471 { 0, 0, 0, 0 },
67472 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
67473 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c20000 }
67474 },
67475/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
67476 {
67477 { 0, 0, 0, 0 },
67478 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
67479 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e20000 }
67480 },
67481/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
67482 {
67483 { 0, 0, 0, 0 },
67484 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
67485 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c20000 }
67486 },
67487/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
67488 {
67489 { 0, 0, 0, 0 },
67490 { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
67491 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6820000 }
67492 },
67493/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
67494 {
67495 { 0, 0, 0, 0 },
67496 { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
67497 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a20000 }
67498 },
67499/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
67500 {
67501 { 0, 0, 0, 0 },
67502 { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
67503 & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86820000 }
67504 },
67505/* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
67506 {
67507 { 0, 0, 0, 0 },
67508 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67509 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x881100 }
67510 },
67511/* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
67512 {
67513 { 0, 0, 0, 0 },
67514 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67515 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x809100 }
67516 },
67517/* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
67518 {
67519 { 0, 0, 0, 0 },
67520 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67521 & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x801100 }
67522 },
67523/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
67524 {
67525 { 0, 0, 0, 0 },
67526 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67527 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82110000 }
67528 },
67529/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
67530 {
67531 { 0, 0, 0, 0 },
67532 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67533 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82910000 }
67534 },
67535/* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
67536 {
67537 { 0, 0, 0, 0 },
67538 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67539 & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82d10000 }
67540 },
67541/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
67542 {
67543 { 0, 0, 0, 0 },
67544 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67545 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84110000 }
67546 },
67547/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
67548 {
67549 { 0, 0, 0, 0 },
67550 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67551 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84910000 }
67552 },
67553/* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
67554 {
67555 { 0, 0, 0, 0 },
67556 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67557 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84d10000 }
67558 },
67559/* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
67560 {
67561 { 0, 0, 0, 0 },
67562 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
67563 & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86d10000 }
67564 },
67565/* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
67566 {
67567 { 0, 0, 0, 0 },
67568 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67569 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86110000 }
67570 },
67571/* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
67572 {
67573 { 0, 0, 0, 0 },
67574 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
67575 & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86910000 }
67576 },
67577/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
67578 {
67579 { 0, 0, 0, 0 },
67580 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67581 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990000 }
67582 },
67583/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
67584 {
67585 { 0, 0, 0, 0 },
67586 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67587 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992000 }
67588 },
67589/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
67590 {
67591 { 0, 0, 0, 0 },
67592 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67593 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993000 }
67594 },
67595/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
67596 {
67597 { 0, 0, 0, 0 },
67598 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67599 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918000 }
67600 },
67601/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
67602 {
67603 { 0, 0, 0, 0 },
67604 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67605 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a000 }
67606 },
67607/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
67608 {
67609 { 0, 0, 0, 0 },
67610 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67611 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b000 }
67612 },
67613/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
67614 {
67615 { 0, 0, 0, 0 },
67616 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67617 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910000 }
67618 },
67619/* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
67620 {
67621 { 0, 0, 0, 0 },
67622 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67623 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912000 }
67624 },
67625/* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
67626 {
67627 { 0, 0, 0, 0 },
67628 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67629 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913000 }
67630 },
67631/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
67632 {
67633 { 0, 0, 0, 0 },
67634 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67635 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930000 }
67636 },
67637/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
67638 {
67639 { 0, 0, 0, 0 },
67640 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67641 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932000 }
67642 },
67643/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
67644 {
67645 { 0, 0, 0, 0 },
67646 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67647 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933000 }
67648 },
67649/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
67650 {
67651 { 0, 0, 0, 0 },
67652 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67653 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950000 }
67654 },
67655/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
67656 {
67657 { 0, 0, 0, 0 },
67658 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67659 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952000 }
67660 },
67661/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
67662 {
67663 { 0, 0, 0, 0 },
67664 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67665 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953000 }
67666 },
67667/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
67668 {
67669 { 0, 0, 0, 0 },
67670 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67671 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970000 }
67672 },
67673/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
67674 {
67675 { 0, 0, 0, 0 },
67676 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67677 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972000 }
67678 },
67679/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
67680 {
67681 { 0, 0, 0, 0 },
67682 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67683 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973000 }
67684 },
67685/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
67686 {
67687 { 0, 0, 0, 0 },
67688 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67689 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938000 }
67690 },
67691/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
67692 {
67693 { 0, 0, 0, 0 },
67694 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67695 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a000 }
67696 },
67697/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
67698 {
67699 { 0, 0, 0, 0 },
67700 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67701 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b000 }
67702 },
67703/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
67704 {
67705 { 0, 0, 0, 0 },
67706 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67707 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958000 }
67708 },
67709/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
67710 {
67711 { 0, 0, 0, 0 },
67712 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67713 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a000 }
67714 },
67715/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
67716 {
67717 { 0, 0, 0, 0 },
67718 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67719 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b000 }
67720 },
67721/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
67722 {
67723 { 0, 0, 0, 0 },
67724 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67725 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c000 }
67726 },
67727/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
67728 {
67729 { 0, 0, 0, 0 },
67730 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67731 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e000 }
67732 },
67733/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
67734 {
67735 { 0, 0, 0, 0 },
67736 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67737 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f000 }
67738 },
67739/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
67740 {
67741 { 0, 0, 0, 0 },
67742 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67743 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c000 }
67744 },
67745/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
67746 {
67747 { 0, 0, 0, 0 },
67748 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67749 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e000 }
67750 },
67751/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
67752 {
67753 { 0, 0, 0, 0 },
67754 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67755 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f000 }
67756 },
67757/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
67758 {
67759 { 0, 0, 0, 0 },
67760 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
67761 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c000 }
67762 },
67763/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
67764 {
67765 { 0, 0, 0, 0 },
67766 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67767 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e000 }
67768 },
67769/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
67770 {
67771 { 0, 0, 0, 0 },
67772 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67773 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f000 }
67774 },
67775/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
67776 {
67777 { 0, 0, 0, 0 },
67778 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
67779 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978000 }
67780 },
67781/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
67782 {
67783 { 0, 0, 0, 0 },
67784 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67785 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a000 }
67786 },
67787/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
67788 {
67789 { 0, 0, 0, 0 },
67790 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67791 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b000 }
67792 },
67793/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
67794 {
67795 { 0, 0, 0, 0 },
67796 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67797 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90000 }
67798 },
67799/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
67800 {
67801 { 0, 0, 0, 0 },
67802 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67803 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92000 }
67804 },
67805/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
67806 {
67807 { 0, 0, 0, 0 },
67808 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67809 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93000 }
67810 },
67811/* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
67812 {
67813 { 0, 0, 0, 0 },
67814 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
67815 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93000 }
67816 },
67817/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
67818 {
67819 { 0, 0, 0, 0 },
67820 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67821 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18000 }
67822 },
67823/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
67824 {
67825 { 0, 0, 0, 0 },
67826 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67827 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a000 }
67828 },
67829/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
67830 {
67831 { 0, 0, 0, 0 },
67832 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67833 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b000 }
67834 },
67835/* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
67836 {
67837 { 0, 0, 0, 0 },
67838 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
67839 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b000 }
67840 },
67841/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
67842 {
67843 { 0, 0, 0, 0 },
67844 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67845 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10000 }
67846 },
67847/* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
67848 {
67849 { 0, 0, 0, 0 },
67850 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67851 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12000 }
67852 },
67853/* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
67854 {
67855 { 0, 0, 0, 0 },
67856 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67857 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13000 }
67858 },
67859/* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
67860 {
67861 { 0, 0, 0, 0 },
67862 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67863 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13000 }
67864 },
67865/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
67866 {
67867 { 0, 0, 0, 0 },
67868 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67869 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30000 }
67870 },
67871/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
67872 {
67873 { 0, 0, 0, 0 },
67874 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67875 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32000 }
67876 },
67877/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
67878 {
67879 { 0, 0, 0, 0 },
67880 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67881 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33000 }
67882 },
67883/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
67884 {
67885 { 0, 0, 0, 0 },
67886 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67887 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33000 }
67888 },
67889/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
67890 {
67891 { 0, 0, 0, 0 },
67892 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67893 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50000 }
67894 },
67895/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
67896 {
67897 { 0, 0, 0, 0 },
67898 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67899 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52000 }
67900 },
67901/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
67902 {
67903 { 0, 0, 0, 0 },
67904 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67905 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53000 }
67906 },
67907/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
67908 {
67909 { 0, 0, 0, 0 },
67910 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67911 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53000 }
67912 },
67913/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
67914 {
67915 { 0, 0, 0, 0 },
67916 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67917 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70000 }
67918 },
67919/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
67920 {
67921 { 0, 0, 0, 0 },
67922 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67923 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72000 }
67924 },
67925/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
67926 {
67927 { 0, 0, 0, 0 },
67928 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67929 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73000 }
67930 },
67931/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
67932 {
67933 { 0, 0, 0, 0 },
67934 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67935 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73000 }
67936 },
67937/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
67938 {
67939 { 0, 0, 0, 0 },
67940 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67941 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38000 }
67942 },
67943/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
67944 {
67945 { 0, 0, 0, 0 },
67946 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67947 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a000 }
67948 },
67949/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
67950 {
67951 { 0, 0, 0, 0 },
67952 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67953 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b000 }
67954 },
67955/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
67956 {
67957 { 0, 0, 0, 0 },
67958 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67959 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b000 }
67960 },
67961/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
67962 {
67963 { 0, 0, 0, 0 },
67964 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67965 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58000 }
67966 },
67967/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
67968 {
67969 { 0, 0, 0, 0 },
67970 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67971 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a000 }
67972 },
67973/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
67974 {
67975 { 0, 0, 0, 0 },
67976 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67977 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b000 }
67978 },
67979/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
67980 {
67981 { 0, 0, 0, 0 },
67982 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67983 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b000 }
67984 },
67985/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
67986 {
67987 { 0, 0, 0, 0 },
67988 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67989 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c000 }
67990 },
67991/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
67992 {
67993 { 0, 0, 0, 0 },
67994 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67995 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e000 }
67996 },
67997/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
67998 {
67999 { 0, 0, 0, 0 },
68000 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68001 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f000 }
68002 },
68003/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
68004 {
68005 { 0, 0, 0, 0 },
68006 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68007 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f000 }
68008 },
68009/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
68010 {
68011 { 0, 0, 0, 0 },
68012 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68013 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c000 }
68014 },
68015/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
68016 {
68017 { 0, 0, 0, 0 },
68018 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68019 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e000 }
68020 },
68021/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
68022 {
68023 { 0, 0, 0, 0 },
68024 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68025 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f000 }
68026 },
68027/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
68028 {
68029 { 0, 0, 0, 0 },
68030 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68031 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f000 }
68032 },
68033/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
68034 {
68035 { 0, 0, 0, 0 },
68036 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
68037 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c000 }
68038 },
68039/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
68040 {
68041 { 0, 0, 0, 0 },
68042 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68043 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e000 }
68044 },
68045/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
68046 {
68047 { 0, 0, 0, 0 },
68048 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68049 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f000 }
68050 },
68051/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
68052 {
68053 { 0, 0, 0, 0 },
68054 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
68055 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f000 }
68056 },
68057/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
68058 {
68059 { 0, 0, 0, 0 },
68060 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
68061 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78000 }
68062 },
68063/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
68064 {
68065 { 0, 0, 0, 0 },
68066 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68067 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a000 }
68068 },
68069/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
68070 {
68071 { 0, 0, 0, 0 },
68072 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68073 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b000 }
68074 },
68075/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
68076 {
68077 { 0, 0, 0, 0 },
68078 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
68079 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b000 }
68080 },
68081/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
68082 {
68083 { 0, 0, 0, 0 },
68084 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
68085 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90000 }
68086 },
68087/* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
68088 {
68089 { 0, 0, 0, 0 },
68090 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
68091 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92000 }
68092 },
68093/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
68094 {
68095 { 0, 0, 0, 0 },
68096 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
68097 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18000 }
68098 },
68099/* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
68100 {
68101 { 0, 0, 0, 0 },
68102 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
68103 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a000 }
68104 },
68105/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68106 {
68107 { 0, 0, 0, 0 },
68108 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68109 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10000 }
68110 },
68111/* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
68112 {
68113 { 0, 0, 0, 0 },
68114 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68115 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12000 }
68116 },
68117/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
68118 {
68119 { 0, 0, 0, 0 },
68120 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68121 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30000 }
68122 },
68123/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
68124 {
68125 { 0, 0, 0, 0 },
68126 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68127 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32000 }
68128 },
68129/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
68130 {
68131 { 0, 0, 0, 0 },
68132 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68133 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50000 }
68134 },
68135/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
68136 {
68137 { 0, 0, 0, 0 },
68138 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68139 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52000 }
68140 },
68141/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
68142 {
68143 { 0, 0, 0, 0 },
68144 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68145 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70000 }
68146 },
68147/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
68148 {
68149 { 0, 0, 0, 0 },
68150 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68151 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72000 }
68152 },
68153/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
68154 {
68155 { 0, 0, 0, 0 },
68156 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
68157 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38000 }
68158 },
68159/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
68160 {
68161 { 0, 0, 0, 0 },
68162 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
68163 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a000 }
68164 },
68165/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
68166 {
68167 { 0, 0, 0, 0 },
68168 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
68169 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58000 }
68170 },
68171/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
68172 {
68173 { 0, 0, 0, 0 },
68174 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
68175 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a000 }
68176 },
68177/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
68178 {
68179 { 0, 0, 0, 0 },
68180 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
68181 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c000 }
68182 },
68183/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
68184 {
68185 { 0, 0, 0, 0 },
68186 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
68187 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e000 }
68188 },
68189/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
68190 {
68191 { 0, 0, 0, 0 },
68192 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
68193 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c000 }
68194 },
68195/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
68196 {
68197 { 0, 0, 0, 0 },
68198 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
68199 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e000 }
68200 },
68201/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
68202 {
68203 { 0, 0, 0, 0 },
68204 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
68205 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c000 }
68206 },
68207/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
68208 {
68209 { 0, 0, 0, 0 },
68210 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
68211 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e000 }
68212 },
68213/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
68214 {
68215 { 0, 0, 0, 0 },
68216 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
68217 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78000 }
68218 },
68219/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
68220 {
68221 { 0, 0, 0, 0 },
68222 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
68223 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a000 }
68224 },
68225/* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
68226 {
68227 { 0, 0, 0, 0 },
68228 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
68229 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c900 }
68230 },
68231/* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
68232 {
68233 { 0, 0, 0, 0 },
68234 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
68235 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18920 }
68236 },
68237/* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
68238 {
68239 { 0, 0, 0, 0 },
68240 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
68241 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18900 }
68242 },
68243/* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
68244 {
68245 { 0, 0, 0, 0 },
68246 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
68247 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c180 }
68248 },
68249/* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
68250 {
68251 { 0, 0, 0, 0 },
68252 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
68253 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a0 }
68254 },
68255/* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
68256 {
68257 { 0, 0, 0, 0 },
68258 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
68259 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18180 }
68260 },
68261/* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
68262 {
68263 { 0, 0, 0, 0 },
68264 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68265 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c100 }
68266 },
68267/* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
68268 {
68269 { 0, 0, 0, 0 },
68270 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68271 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18120 }
68272 },
68273/* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
68274 {
68275 { 0, 0, 0, 0 },
68276 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68277 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18100 }
68278 },
68279/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
68280 {
68281 { 0, 0, 0, 0 },
68282 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68283 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30000 }
68284 },
68285/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
68286 {
68287 { 0, 0, 0, 0 },
68288 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68289 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832000 }
68290 },
68291/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
68292 {
68293 { 0, 0, 0, 0 },
68294 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68295 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830000 }
68296 },
68297/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
68298 {
68299 { 0, 0, 0, 0 },
68300 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68301 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50000 }
68302 },
68303/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
68304 {
68305 { 0, 0, 0, 0 },
68306 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68307 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852000 }
68308 },
68309/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
68310 {
68311 { 0, 0, 0, 0 },
68312 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68313 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850000 }
68314 },
68315/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
68316 {
68317 { 0, 0, 0, 0 },
68318 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68319 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70000 }
68320 },
68321/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
68322 {
68323 { 0, 0, 0, 0 },
68324 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68325 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872000 }
68326 },
68327/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
68328 {
68329 { 0, 0, 0, 0 },
68330 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68331 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870000 }
68332 },
68333/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
68334 {
68335 { 0, 0, 0, 0 },
68336 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68337 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38000 }
68338 },
68339/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
68340 {
68341 { 0, 0, 0, 0 },
68342 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68343 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a000 }
68344 },
68345/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
68346 {
68347 { 0, 0, 0, 0 },
68348 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68349 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838000 }
68350 },
68351/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
68352 {
68353 { 0, 0, 0, 0 },
68354 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68355 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58000 }
68356 },
68357/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
68358 {
68359 { 0, 0, 0, 0 },
68360 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68361 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a000 }
68362 },
68363/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
68364 {
68365 { 0, 0, 0, 0 },
68366 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68367 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858000 }
68368 },
68369/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
68370 {
68371 { 0, 0, 0, 0 },
68372 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68373 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c000 }
68374 },
68375/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
68376 {
68377 { 0, 0, 0, 0 },
68378 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68379 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e000 }
68380 },
68381/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
68382 {
68383 { 0, 0, 0, 0 },
68384 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68385 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c000 }
68386 },
68387/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
68388 {
68389 { 0, 0, 0, 0 },
68390 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68391 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c000 }
68392 },
68393/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
68394 {
68395 { 0, 0, 0, 0 },
68396 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68397 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e000 }
68398 },
68399/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
68400 {
68401 { 0, 0, 0, 0 },
68402 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68403 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c000 }
68404 },
68405/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
68406 {
68407 { 0, 0, 0, 0 },
68408 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
68409 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c000 }
68410 },
68411/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
68412 {
68413 { 0, 0, 0, 0 },
68414 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
68415 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e000 }
68416 },
68417/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
68418 {
68419 { 0, 0, 0, 0 },
68420 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
68421 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c000 }
68422 },
68423/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
68424 {
68425 { 0, 0, 0, 0 },
68426 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
68427 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78000 }
68428 },
68429/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
68430 {
68431 { 0, 0, 0, 0 },
68432 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
68433 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a000 }
68434 },
68435/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
68436 {
68437 { 0, 0, 0, 0 },
68438 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
68439 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878000 }
68440 },
68441/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68442 {
68443 { 0, 0, 0, 0 },
68444 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68445 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980000 }
68446 },
68447/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
68448 {
68449 { 0, 0, 0, 0 },
68450 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68451 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982000 }
68452 },
68453/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
68454 {
68455 { 0, 0, 0, 0 },
68456 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68457 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983000 }
68458 },
68459/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68460 {
68461 { 0, 0, 0, 0 },
68462 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68463 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908000 }
68464 },
68465/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
68466 {
68467 { 0, 0, 0, 0 },
68468 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68469 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a000 }
68470 },
68471/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
68472 {
68473 { 0, 0, 0, 0 },
68474 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68475 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b000 }
68476 },
68477/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68478 {
68479 { 0, 0, 0, 0 },
68480 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68481 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900000 }
68482 },
68483/* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
68484 {
68485 { 0, 0, 0, 0 },
68486 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68487 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902000 }
68488 },
68489/* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
68490 {
68491 { 0, 0, 0, 0 },
68492 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68493 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903000 }
68494 },
68495/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
68496 {
68497 { 0, 0, 0, 0 },
68498 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68499 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920000 }
68500 },
68501/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
68502 {
68503 { 0, 0, 0, 0 },
68504 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68505 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922000 }
68506 },
68507/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
68508 {
68509 { 0, 0, 0, 0 },
68510 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68511 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923000 }
68512 },
68513/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
68514 {
68515 { 0, 0, 0, 0 },
68516 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68517 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940000 }
68518 },
68519/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
68520 {
68521 { 0, 0, 0, 0 },
68522 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68523 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942000 }
68524 },
68525/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
68526 {
68527 { 0, 0, 0, 0 },
68528 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68529 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943000 }
68530 },
68531/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
68532 {
68533 { 0, 0, 0, 0 },
68534 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68535 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960000 }
68536 },
68537/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
68538 {
68539 { 0, 0, 0, 0 },
68540 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68541 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962000 }
68542 },
68543/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
68544 {
68545 { 0, 0, 0, 0 },
68546 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68547 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963000 }
68548 },
68549/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
68550 {
68551 { 0, 0, 0, 0 },
68552 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68553 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928000 }
68554 },
68555/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
68556 {
68557 { 0, 0, 0, 0 },
68558 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68559 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a000 }
68560 },
68561/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
68562 {
68563 { 0, 0, 0, 0 },
68564 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68565 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b000 }
68566 },
68567/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
68568 {
68569 { 0, 0, 0, 0 },
68570 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68571 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948000 }
68572 },
68573/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
68574 {
68575 { 0, 0, 0, 0 },
68576 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68577 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a000 }
68578 },
68579/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
68580 {
68581 { 0, 0, 0, 0 },
68582 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68583 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b000 }
68584 },
68585/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
68586 {
68587 { 0, 0, 0, 0 },
68588 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68589 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c000 }
68590 },
68591/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
68592 {
68593 { 0, 0, 0, 0 },
68594 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68595 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e000 }
68596 },
68597/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
68598 {
68599 { 0, 0, 0, 0 },
68600 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68601 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f000 }
68602 },
68603/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
68604 {
68605 { 0, 0, 0, 0 },
68606 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68607 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c000 }
68608 },
68609/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
68610 {
68611 { 0, 0, 0, 0 },
68612 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68613 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e000 }
68614 },
68615/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
68616 {
68617 { 0, 0, 0, 0 },
68618 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68619 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f000 }
68620 },
68621/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
68622 {
68623 { 0, 0, 0, 0 },
68624 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
68625 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c000 }
68626 },
68627/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
68628 {
68629 { 0, 0, 0, 0 },
68630 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
68631 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e000 }
68632 },
68633/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
68634 {
68635 { 0, 0, 0, 0 },
68636 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
68637 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f000 }
68638 },
68639/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
68640 {
68641 { 0, 0, 0, 0 },
68642 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
68643 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968000 }
68644 },
68645/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
68646 {
68647 { 0, 0, 0, 0 },
68648 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
68649 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a000 }
68650 },
68651/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
68652 {
68653 { 0, 0, 0, 0 },
68654 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
68655 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b000 }
68656 },
68657/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68658 {
68659 { 0, 0, 0, 0 },
68660 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68661 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80000 }
68662 },
68663/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
68664 {
68665 { 0, 0, 0, 0 },
68666 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68667 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82000 }
68668 },
68669/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
68670 {
68671 { 0, 0, 0, 0 },
68672 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68673 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83000 }
68674 },
68675/* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
68676 {
68677 { 0, 0, 0, 0 },
68678 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
68679 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83000 }
68680 },
68681/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68682 {
68683 { 0, 0, 0, 0 },
68684 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68685 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08000 }
68686 },
68687/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
68688 {
68689 { 0, 0, 0, 0 },
68690 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68691 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a000 }
68692 },
68693/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
68694 {
68695 { 0, 0, 0, 0 },
68696 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68697 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b000 }
68698 },
68699/* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
68700 {
68701 { 0, 0, 0, 0 },
68702 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
68703 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b000 }
68704 },
68705/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68706 {
68707 { 0, 0, 0, 0 },
68708 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68709 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00000 }
68710 },
68711/* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
68712 {
68713 { 0, 0, 0, 0 },
68714 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68715 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02000 }
68716 },
68717/* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
68718 {
68719 { 0, 0, 0, 0 },
68720 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68721 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03000 }
68722 },
68723/* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
68724 {
68725 { 0, 0, 0, 0 },
68726 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68727 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03000 }
68728 },
68729/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
68730 {
68731 { 0, 0, 0, 0 },
68732 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68733 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20000 }
68734 },
68735/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
68736 {
68737 { 0, 0, 0, 0 },
68738 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68739 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22000 }
68740 },
68741/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
68742 {
68743 { 0, 0, 0, 0 },
68744 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68745 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23000 }
68746 },
68747/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
68748 {
68749 { 0, 0, 0, 0 },
68750 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68751 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23000 }
68752 },
68753/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
68754 {
68755 { 0, 0, 0, 0 },
68756 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68757 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40000 }
68758 },
68759/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
68760 {
68761 { 0, 0, 0, 0 },
68762 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68763 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42000 }
68764 },
68765/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
68766 {
68767 { 0, 0, 0, 0 },
68768 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68769 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43000 }
68770 },
68771/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
68772 {
68773 { 0, 0, 0, 0 },
68774 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68775 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43000 }
68776 },
68777/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
68778 {
68779 { 0, 0, 0, 0 },
68780 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68781 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60000 }
68782 },
68783/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
68784 {
68785 { 0, 0, 0, 0 },
68786 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68787 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62000 }
68788 },
68789/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
68790 {
68791 { 0, 0, 0, 0 },
68792 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68793 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63000 }
68794 },
68795/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
68796 {
68797 { 0, 0, 0, 0 },
68798 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68799 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63000 }
68800 },
68801/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
68802 {
68803 { 0, 0, 0, 0 },
68804 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68805 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28000 }
68806 },
68807/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
68808 {
68809 { 0, 0, 0, 0 },
68810 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68811 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a000 }
68812 },
68813/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
68814 {
68815 { 0, 0, 0, 0 },
68816 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68817 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b000 }
68818 },
68819/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
68820 {
68821 { 0, 0, 0, 0 },
68822 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68823 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b000 }
68824 },
68825/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
68826 {
68827 { 0, 0, 0, 0 },
68828 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68829 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48000 }
68830 },
68831/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
68832 {
68833 { 0, 0, 0, 0 },
68834 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68835 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a000 }
68836 },
68837/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
68838 {
68839 { 0, 0, 0, 0 },
68840 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68841 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b000 }
68842 },
68843/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
68844 {
68845 { 0, 0, 0, 0 },
68846 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68847 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b000 }
68848 },
68849/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
68850 {
68851 { 0, 0, 0, 0 },
68852 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68853 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c000 }
68854 },
68855/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
68856 {
68857 { 0, 0, 0, 0 },
68858 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68859 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e000 }
68860 },
68861/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
68862 {
68863 { 0, 0, 0, 0 },
68864 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68865 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f000 }
68866 },
68867/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
68868 {
68869 { 0, 0, 0, 0 },
68870 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68871 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f000 }
68872 },
68873/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
68874 {
68875 { 0, 0, 0, 0 },
68876 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68877 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c000 }
68878 },
68879/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
68880 {
68881 { 0, 0, 0, 0 },
68882 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68883 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e000 }
68884 },
68885/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
68886 {
68887 { 0, 0, 0, 0 },
68888 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68889 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f000 }
68890 },
68891/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
68892 {
68893 { 0, 0, 0, 0 },
68894 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68895 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f000 }
68896 },
68897/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
68898 {
68899 { 0, 0, 0, 0 },
68900 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
68901 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c000 }
68902 },
68903/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
68904 {
68905 { 0, 0, 0, 0 },
68906 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68907 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e000 }
68908 },
68909/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
68910 {
68911 { 0, 0, 0, 0 },
68912 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68913 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f000 }
68914 },
68915/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
68916 {
68917 { 0, 0, 0, 0 },
68918 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
68919 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f000 }
68920 },
68921/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
68922 {
68923 { 0, 0, 0, 0 },
68924 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
68925 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68000 }
68926 },
68927/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
68928 {
68929 { 0, 0, 0, 0 },
68930 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68931 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a000 }
68932 },
68933/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
68934 {
68935 { 0, 0, 0, 0 },
68936 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68937 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b000 }
68938 },
68939/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
68940 {
68941 { 0, 0, 0, 0 },
68942 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
68943 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b000 }
68944 },
68945/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68946 {
68947 { 0, 0, 0, 0 },
68948 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68949 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80000 }
68950 },
68951/* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
68952 {
68953 { 0, 0, 0, 0 },
68954 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
68955 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82000 }
68956 },
68957/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68958 {
68959 { 0, 0, 0, 0 },
68960 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68961 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08000 }
68962 },
68963/* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
68964 {
68965 { 0, 0, 0, 0 },
68966 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
68967 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a000 }
68968 },
68969/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68970 {
68971 { 0, 0, 0, 0 },
68972 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68973 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00000 }
68974 },
68975/* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
68976 {
68977 { 0, 0, 0, 0 },
68978 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68979 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02000 }
68980 },
68981/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
68982 {
68983 { 0, 0, 0, 0 },
68984 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68985 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20000 }
68986 },
68987/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
68988 {
68989 { 0, 0, 0, 0 },
68990 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68991 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22000 }
68992 },
68993/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
68994 {
68995 { 0, 0, 0, 0 },
68996 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68997 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40000 }
68998 },
68999/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
69000 {
69001 { 0, 0, 0, 0 },
69002 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69003 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42000 }
69004 },
69005/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
69006 {
69007 { 0, 0, 0, 0 },
69008 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69009 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60000 }
69010 },
69011/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
69012 {
69013 { 0, 0, 0, 0 },
69014 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69015 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62000 }
69016 },
69017/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
69018 {
69019 { 0, 0, 0, 0 },
69020 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
69021 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28000 }
69022 },
69023/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
69024 {
69025 { 0, 0, 0, 0 },
69026 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
69027 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a000 }
69028 },
69029/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
69030 {
69031 { 0, 0, 0, 0 },
69032 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
69033 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48000 }
69034 },
69035/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
69036 {
69037 { 0, 0, 0, 0 },
69038 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
69039 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a000 }
69040 },
69041/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
69042 {
69043 { 0, 0, 0, 0 },
69044 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
69045 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c000 }
69046 },
69047/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
69048 {
69049 { 0, 0, 0, 0 },
69050 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
69051 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e000 }
69052 },
69053/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
69054 {
69055 { 0, 0, 0, 0 },
69056 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
69057 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c000 }
69058 },
69059/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
69060 {
69061 { 0, 0, 0, 0 },
69062 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
69063 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e000 }
69064 },
69065/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
69066 {
69067 { 0, 0, 0, 0 },
69068 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
69069 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c000 }
69070 },
69071/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
69072 {
69073 { 0, 0, 0, 0 },
69074 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
69075 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e000 }
69076 },
69077/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
69078 {
69079 { 0, 0, 0, 0 },
69080 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
69081 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68000 }
69082 },
69083/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
69084 {
69085 { 0, 0, 0, 0 },
69086 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
69087 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a000 }
69088 },
69089/* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
69090 {
69091 { 0, 0, 0, 0 },
69092 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
69093 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c800 }
69094 },
69095/* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
69096 {
69097 { 0, 0, 0, 0 },
69098 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
69099 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18820 }
69100 },
69101/* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
69102 {
69103 { 0, 0, 0, 0 },
69104 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
69105 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18800 }
69106 },
69107/* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
69108 {
69109 { 0, 0, 0, 0 },
69110 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
69111 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c080 }
69112 },
69113/* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
69114 {
69115 { 0, 0, 0, 0 },
69116 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
69117 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a0 }
69118 },
69119/* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
69120 {
69121 { 0, 0, 0, 0 },
69122 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
69123 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18080 }
69124 },
69125/* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
69126 {
69127 { 0, 0, 0, 0 },
69128 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69129 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c000 }
69130 },
69131/* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
69132 {
69133 { 0, 0, 0, 0 },
69134 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69135 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18020 }
69136 },
69137/* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
69138 {
69139 { 0, 0, 0, 0 },
69140 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69141 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18000 }
69142 },
69143/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
69144 {
69145 { 0, 0, 0, 0 },
69146 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69147 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20000 }
69148 },
69149/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
69150 {
69151 { 0, 0, 0, 0 },
69152 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69153 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822000 }
69154 },
69155/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
69156 {
69157 { 0, 0, 0, 0 },
69158 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69159 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820000 }
69160 },
69161/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
69162 {
69163 { 0, 0, 0, 0 },
69164 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69165 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40000 }
69166 },
69167/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
69168 {
69169 { 0, 0, 0, 0 },
69170 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69171 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842000 }
69172 },
69173/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
69174 {
69175 { 0, 0, 0, 0 },
69176 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69177 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840000 }
69178 },
69179/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
69180 {
69181 { 0, 0, 0, 0 },
69182 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69183 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60000 }
69184 },
69185/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
69186 {
69187 { 0, 0, 0, 0 },
69188 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69189 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862000 }
69190 },
69191/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
69192 {
69193 { 0, 0, 0, 0 },
69194 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69195 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860000 }
69196 },
69197/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
69198 {
69199 { 0, 0, 0, 0 },
69200 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69201 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28000 }
69202 },
69203/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
69204 {
69205 { 0, 0, 0, 0 },
69206 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69207 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a000 }
69208 },
69209/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
69210 {
69211 { 0, 0, 0, 0 },
69212 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69213 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828000 }
69214 },
69215/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
69216 {
69217 { 0, 0, 0, 0 },
69218 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69219 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48000 }
69220 },
69221/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
69222 {
69223 { 0, 0, 0, 0 },
69224 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69225 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a000 }
69226 },
69227/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
69228 {
69229 { 0, 0, 0, 0 },
69230 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69231 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848000 }
69232 },
69233/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
69234 {
69235 { 0, 0, 0, 0 },
69236 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69237 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c000 }
69238 },
69239/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
69240 {
69241 { 0, 0, 0, 0 },
69242 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69243 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e000 }
69244 },
69245/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
69246 {
69247 { 0, 0, 0, 0 },
69248 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69249 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c000 }
69250 },
69251/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
69252 {
69253 { 0, 0, 0, 0 },
69254 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69255 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c000 }
69256 },
69257/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
69258 {
69259 { 0, 0, 0, 0 },
69260 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69261 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e000 }
69262 },
69263/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
69264 {
69265 { 0, 0, 0, 0 },
69266 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69267 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c000 }
69268 },
69269/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
69270 {
69271 { 0, 0, 0, 0 },
69272 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
69273 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c000 }
69274 },
69275/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
69276 {
69277 { 0, 0, 0, 0 },
69278 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
69279 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e000 }
69280 },
69281/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
69282 {
69283 { 0, 0, 0, 0 },
69284 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
69285 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c000 }
69286 },
69287/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
69288 {
69289 { 0, 0, 0, 0 },
69290 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
69291 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68000 }
69292 },
69293/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
69294 {
69295 { 0, 0, 0, 0 },
69296 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
69297 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a000 }
69298 },
69299/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
69300 {
69301 { 0, 0, 0, 0 },
69302 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
69303 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868000 }
69304 },
69305/* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
69306 {
69307 { 0, 0, 0, 0 },
69308 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
69309 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1891e00 }
69310 },
69311/* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
69312 {
69313 { 0, 0, 0, 0 },
69314 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
69315 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1819e00 }
69316 },
69317/* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
69318 {
69319 { 0, 0, 0, 0 },
69320 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69321 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1811e00 }
69322 },
69323/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
69324 {
69325 { 0, 0, 0, 0 },
69326 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69327 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1831e00 }
69328 },
69329/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
69330 {
69331 { 0, 0, 0, 0 },
69332 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69333 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1839e00 }
69334 },
69335/* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
69336 {
69337 { 0, 0, 0, 0 },
69338 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69339 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183de00 }
69340 },
69341/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
69342 {
69343 { 0, 0, 0, 0 },
69344 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69345 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1851e00 }
69346 },
69347/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
69348 {
69349 { 0, 0, 0, 0 },
69350 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69351 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1859e00 }
69352 },
69353/* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
69354 {
69355 { 0, 0, 0, 0 },
69356 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69357 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185de00 }
69358 },
69359/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
69360 {
69361 { 0, 0, 0, 0 },
69362 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
69363 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187de00 }
69364 },
69365/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
69366 {
69367 { 0, 0, 0, 0 },
69368 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69369 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1871e00 }
69370 },
69371/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
69372 {
69373 { 0, 0, 0, 0 },
69374 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
69375 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1879e00 }
69376 },
69377/* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
69378 {
69379 { 0, 0, 0, 0 },
69380 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
69381 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1881e00 }
69382 },
69383/* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
69384 {
69385 { 0, 0, 0, 0 },
69386 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
69387 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1809e00 }
69388 },
69389/* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
69390 {
69391 { 0, 0, 0, 0 },
69392 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69393 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1801e00 }
69394 },
69395/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
69396 {
69397 { 0, 0, 0, 0 },
69398 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69399 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1821e00 }
69400 },
69401/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
69402 {
69403 { 0, 0, 0, 0 },
69404 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69405 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1829e00 }
69406 },
69407/* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
69408 {
69409 { 0, 0, 0, 0 },
69410 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69411 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182de00 }
69412 },
69413/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
69414 {
69415 { 0, 0, 0, 0 },
69416 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69417 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1841e00 }
69418 },
69419/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
69420 {
69421 { 0, 0, 0, 0 },
69422 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69423 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1849e00 }
69424 },
69425/* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
69426 {
69427 { 0, 0, 0, 0 },
69428 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69429 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184de00 }
69430 },
69431/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
69432 {
69433 { 0, 0, 0, 0 },
69434 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
69435 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186de00 }
69436 },
69437/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
69438 {
69439 { 0, 0, 0, 0 },
69440 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69441 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1861e00 }
69442 },
69443/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
69444 {
69445 { 0, 0, 0, 0 },
69446 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
69447 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1869e00 }
69448 },
69449/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69450 {
69451 { 0, 0, 0, 0 },
69452 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69453 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990800 }
69454 },
69455/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
69456 {
69457 { 0, 0, 0, 0 },
69458 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69459 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992800 }
69460 },
69461/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
69462 {
69463 { 0, 0, 0, 0 },
69464 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69465 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993800 }
69466 },
69467/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69468 {
69469 { 0, 0, 0, 0 },
69470 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69471 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918800 }
69472 },
69473/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
69474 {
69475 { 0, 0, 0, 0 },
69476 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69477 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a800 }
69478 },
69479/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
69480 {
69481 { 0, 0, 0, 0 },
69482 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69483 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b800 }
69484 },
69485/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69486 {
69487 { 0, 0, 0, 0 },
69488 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69489 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910800 }
69490 },
69491/* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
69492 {
69493 { 0, 0, 0, 0 },
69494 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69495 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912800 }
69496 },
69497/* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
69498 {
69499 { 0, 0, 0, 0 },
69500 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69501 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913800 }
69502 },
69503/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
69504 {
69505 { 0, 0, 0, 0 },
69506 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69507 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930800 }
69508 },
69509/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69510 {
69511 { 0, 0, 0, 0 },
69512 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69513 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932800 }
69514 },
69515/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69516 {
69517 { 0, 0, 0, 0 },
69518 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69519 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933800 }
69520 },
69521/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
69522 {
69523 { 0, 0, 0, 0 },
69524 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69525 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950800 }
69526 },
69527/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
69528 {
69529 { 0, 0, 0, 0 },
69530 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69531 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952800 }
69532 },
69533/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
69534 {
69535 { 0, 0, 0, 0 },
69536 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69537 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953800 }
69538 },
69539/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
69540 {
69541 { 0, 0, 0, 0 },
69542 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69543 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970800 }
69544 },
69545/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
69546 {
69547 { 0, 0, 0, 0 },
69548 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69549 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972800 }
69550 },
69551/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
69552 {
69553 { 0, 0, 0, 0 },
69554 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69555 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973800 }
69556 },
69557/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
69558 {
69559 { 0, 0, 0, 0 },
69560 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69561 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938800 }
69562 },
69563/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
69564 {
69565 { 0, 0, 0, 0 },
69566 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69567 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a800 }
69568 },
69569/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
69570 {
69571 { 0, 0, 0, 0 },
69572 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69573 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b800 }
69574 },
69575/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
69576 {
69577 { 0, 0, 0, 0 },
69578 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69579 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958800 }
69580 },
69581/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
69582 {
69583 { 0, 0, 0, 0 },
69584 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69585 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a800 }
69586 },
69587/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
69588 {
69589 { 0, 0, 0, 0 },
69590 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69591 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b800 }
69592 },
69593/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
69594 {
69595 { 0, 0, 0, 0 },
69596 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69597 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c800 }
69598 },
69599/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
69600 {
69601 { 0, 0, 0, 0 },
69602 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69603 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e800 }
69604 },
69605/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
69606 {
69607 { 0, 0, 0, 0 },
69608 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69609 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f800 }
69610 },
69611/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
69612 {
69613 { 0, 0, 0, 0 },
69614 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69615 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c800 }
69616 },
69617/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
69618 {
69619 { 0, 0, 0, 0 },
69620 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69621 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e800 }
69622 },
69623/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
69624 {
69625 { 0, 0, 0, 0 },
69626 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69627 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f800 }
69628 },
69629/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
69630 {
69631 { 0, 0, 0, 0 },
69632 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
69633 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c800 }
69634 },
69635/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
69636 {
69637 { 0, 0, 0, 0 },
69638 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
69639 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e800 }
69640 },
69641/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
69642 {
69643 { 0, 0, 0, 0 },
69644 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
69645 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f800 }
69646 },
69647/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
69648 {
69649 { 0, 0, 0, 0 },
69650 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
69651 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978800 }
69652 },
69653/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
69654 {
69655 { 0, 0, 0, 0 },
69656 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
69657 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a800 }
69658 },
69659/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
69660 {
69661 { 0, 0, 0, 0 },
69662 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
69663 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b800 }
69664 },
69665/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69666 {
69667 { 0, 0, 0, 0 },
69668 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69669 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90800 }
69670 },
69671/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
69672 {
69673 { 0, 0, 0, 0 },
69674 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69675 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92800 }
69676 },
69677/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
69678 {
69679 { 0, 0, 0, 0 },
69680 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69681 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93800 }
69682 },
69683/* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
69684 {
69685 { 0, 0, 0, 0 },
69686 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
69687 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93800 }
69688 },
69689/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69690 {
69691 { 0, 0, 0, 0 },
69692 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69693 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18800 }
69694 },
69695/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
69696 {
69697 { 0, 0, 0, 0 },
69698 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69699 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a800 }
69700 },
69701/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
69702 {
69703 { 0, 0, 0, 0 },
69704 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69705 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b800 }
69706 },
69707/* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
69708 {
69709 { 0, 0, 0, 0 },
69710 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
69711 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b800 }
69712 },
69713/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69714 {
69715 { 0, 0, 0, 0 },
69716 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69717 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10800 }
69718 },
69719/* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
69720 {
69721 { 0, 0, 0, 0 },
69722 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69723 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12800 }
69724 },
69725/* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
69726 {
69727 { 0, 0, 0, 0 },
69728 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69729 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13800 }
69730 },
69731/* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
69732 {
69733 { 0, 0, 0, 0 },
69734 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69735 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13800 }
69736 },
69737/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
69738 {
69739 { 0, 0, 0, 0 },
69740 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69741 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30800 }
69742 },
69743/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
69744 {
69745 { 0, 0, 0, 0 },
69746 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69747 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32800 }
69748 },
69749/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
69750 {
69751 { 0, 0, 0, 0 },
69752 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69753 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33800 }
69754 },
69755/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
69756 {
69757 { 0, 0, 0, 0 },
69758 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69759 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33800 }
69760 },
69761/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
69762 {
69763 { 0, 0, 0, 0 },
69764 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69765 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50800 }
69766 },
69767/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
69768 {
69769 { 0, 0, 0, 0 },
69770 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69771 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52800 }
69772 },
69773/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
69774 {
69775 { 0, 0, 0, 0 },
69776 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69777 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53800 }
69778 },
69779/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
69780 {
69781 { 0, 0, 0, 0 },
69782 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69783 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53800 }
69784 },
69785/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
69786 {
69787 { 0, 0, 0, 0 },
69788 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69789 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70800 }
69790 },
69791/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
69792 {
69793 { 0, 0, 0, 0 },
69794 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69795 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72800 }
69796 },
69797/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
69798 {
69799 { 0, 0, 0, 0 },
69800 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69801 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73800 }
69802 },
69803/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
69804 {
69805 { 0, 0, 0, 0 },
69806 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69807 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73800 }
69808 },
69809/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
69810 {
69811 { 0, 0, 0, 0 },
69812 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69813 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38800 }
69814 },
69815/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
69816 {
69817 { 0, 0, 0, 0 },
69818 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69819 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a800 }
69820 },
69821/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
69822 {
69823 { 0, 0, 0, 0 },
69824 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69825 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b800 }
69826 },
69827/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
69828 {
69829 { 0, 0, 0, 0 },
69830 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69831 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b800 }
69832 },
69833/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
69834 {
69835 { 0, 0, 0, 0 },
69836 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69837 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58800 }
69838 },
69839/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
69840 {
69841 { 0, 0, 0, 0 },
69842 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69843 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a800 }
69844 },
69845/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
69846 {
69847 { 0, 0, 0, 0 },
69848 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69849 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b800 }
69850 },
69851/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
69852 {
69853 { 0, 0, 0, 0 },
69854 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69855 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b800 }
69856 },
69857/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
69858 {
69859 { 0, 0, 0, 0 },
69860 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69861 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c800 }
69862 },
69863/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
69864 {
69865 { 0, 0, 0, 0 },
69866 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69867 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e800 }
69868 },
69869/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
69870 {
69871 { 0, 0, 0, 0 },
69872 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69873 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f800 }
69874 },
69875/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
69876 {
69877 { 0, 0, 0, 0 },
69878 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69879 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f800 }
69880 },
69881/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
69882 {
69883 { 0, 0, 0, 0 },
69884 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69885 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c800 }
69886 },
69887/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
69888 {
69889 { 0, 0, 0, 0 },
69890 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69891 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e800 }
69892 },
69893/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
69894 {
69895 { 0, 0, 0, 0 },
69896 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69897 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f800 }
69898 },
69899/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
69900 {
69901 { 0, 0, 0, 0 },
69902 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69903 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f800 }
69904 },
69905/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
69906 {
69907 { 0, 0, 0, 0 },
69908 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
69909 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c800 }
69910 },
69911/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
69912 {
69913 { 0, 0, 0, 0 },
69914 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
69915 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e800 }
69916 },
69917/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
69918 {
69919 { 0, 0, 0, 0 },
69920 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
69921 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f800 }
69922 },
69923/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
69924 {
69925 { 0, 0, 0, 0 },
69926 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
69927 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f800 }
69928 },
69929/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
69930 {
69931 { 0, 0, 0, 0 },
69932 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
69933 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78800 }
69934 },
69935/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
69936 {
69937 { 0, 0, 0, 0 },
69938 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
69939 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a800 }
69940 },
69941/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
69942 {
69943 { 0, 0, 0, 0 },
69944 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
69945 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b800 }
69946 },
69947/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
69948 {
69949 { 0, 0, 0, 0 },
69950 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
69951 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b800 }
69952 },
69953/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69954 {
69955 { 0, 0, 0, 0 },
69956 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69957 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90800 }
69958 },
69959/* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
69960 {
69961 { 0, 0, 0, 0 },
69962 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
69963 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92800 }
69964 },
69965/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69966 {
69967 { 0, 0, 0, 0 },
69968 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69969 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18800 }
69970 },
69971/* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
69972 {
69973 { 0, 0, 0, 0 },
69974 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
69975 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a800 }
69976 },
69977/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69978 {
69979 { 0, 0, 0, 0 },
69980 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69981 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10800 }
69982 },
69983/* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
69984 {
69985 { 0, 0, 0, 0 },
69986 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69987 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12800 }
69988 },
69989/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
69990 {
69991 { 0, 0, 0, 0 },
69992 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69993 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30800 }
69994 },
69995/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
69996 {
69997 { 0, 0, 0, 0 },
69998 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69999 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32800 }
70000 },
70001/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
70002 {
70003 { 0, 0, 0, 0 },
70004 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70005 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50800 }
70006 },
70007/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
70008 {
70009 { 0, 0, 0, 0 },
70010 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70011 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52800 }
70012 },
70013/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
70014 {
70015 { 0, 0, 0, 0 },
70016 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70017 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70800 }
70018 },
70019/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
70020 {
70021 { 0, 0, 0, 0 },
70022 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70023 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72800 }
70024 },
70025/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
70026 {
70027 { 0, 0, 0, 0 },
70028 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70029 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38800 }
70030 },
70031/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
70032 {
70033 { 0, 0, 0, 0 },
70034 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70035 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a800 }
70036 },
70037/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
70038 {
70039 { 0, 0, 0, 0 },
70040 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70041 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58800 }
70042 },
70043/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
70044 {
70045 { 0, 0, 0, 0 },
70046 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70047 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a800 }
70048 },
70049/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
70050 {
70051 { 0, 0, 0, 0 },
70052 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70053 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c800 }
70054 },
70055/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
70056 {
70057 { 0, 0, 0, 0 },
70058 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70059 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e800 }
70060 },
70061/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
70062 {
70063 { 0, 0, 0, 0 },
70064 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70065 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c800 }
70066 },
70067/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
70068 {
70069 { 0, 0, 0, 0 },
70070 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70071 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e800 }
70072 },
70073/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
70074 {
70075 { 0, 0, 0, 0 },
70076 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
70077 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c800 }
70078 },
70079/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
70080 {
70081 { 0, 0, 0, 0 },
70082 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
70083 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e800 }
70084 },
70085/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
70086 {
70087 { 0, 0, 0, 0 },
70088 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
70089 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78800 }
70090 },
70091/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
70092 {
70093 { 0, 0, 0, 0 },
70094 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
70095 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a800 }
70096 },
70097/* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
70098 {
70099 { 0, 0, 0, 0 },
70100 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
70101 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c908 }
70102 },
70103/* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
70104 {
70105 { 0, 0, 0, 0 },
70106 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
70107 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18928 }
70108 },
70109/* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
70110 {
70111 { 0, 0, 0, 0 },
70112 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
70113 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18908 }
70114 },
70115/* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
70116 {
70117 { 0, 0, 0, 0 },
70118 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
70119 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c188 }
70120 },
70121/* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
70122 {
70123 { 0, 0, 0, 0 },
70124 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
70125 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a8 }
70126 },
70127/* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
70128 {
70129 { 0, 0, 0, 0 },
70130 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
70131 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18188 }
70132 },
70133/* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
70134 {
70135 { 0, 0, 0, 0 },
70136 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70137 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c108 }
70138 },
70139/* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
70140 {
70141 { 0, 0, 0, 0 },
70142 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70143 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18128 }
70144 },
70145/* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
70146 {
70147 { 0, 0, 0, 0 },
70148 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70149 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18108 }
70150 },
70151/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
70152 {
70153 { 0, 0, 0, 0 },
70154 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70155 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30800 }
70156 },
70157/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
70158 {
70159 { 0, 0, 0, 0 },
70160 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70161 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832800 }
70162 },
70163/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
70164 {
70165 { 0, 0, 0, 0 },
70166 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70167 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830800 }
70168 },
70169/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
70170 {
70171 { 0, 0, 0, 0 },
70172 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70173 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50800 }
70174 },
70175/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
70176 {
70177 { 0, 0, 0, 0 },
70178 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70179 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852800 }
70180 },
70181/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
70182 {
70183 { 0, 0, 0, 0 },
70184 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70185 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850800 }
70186 },
70187/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
70188 {
70189 { 0, 0, 0, 0 },
70190 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70191 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70800 }
70192 },
70193/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
70194 {
70195 { 0, 0, 0, 0 },
70196 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70197 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872800 }
70198 },
70199/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
70200 {
70201 { 0, 0, 0, 0 },
70202 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70203 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870800 }
70204 },
70205/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
70206 {
70207 { 0, 0, 0, 0 },
70208 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70209 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38800 }
70210 },
70211/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
70212 {
70213 { 0, 0, 0, 0 },
70214 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70215 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a800 }
70216 },
70217/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
70218 {
70219 { 0, 0, 0, 0 },
70220 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70221 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838800 }
70222 },
70223/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
70224 {
70225 { 0, 0, 0, 0 },
70226 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70227 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58800 }
70228 },
70229/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
70230 {
70231 { 0, 0, 0, 0 },
70232 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70233 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a800 }
70234 },
70235/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
70236 {
70237 { 0, 0, 0, 0 },
70238 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70239 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858800 }
70240 },
70241/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
70242 {
70243 { 0, 0, 0, 0 },
70244 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70245 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c800 }
70246 },
70247/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
70248 {
70249 { 0, 0, 0, 0 },
70250 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70251 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e800 }
70252 },
70253/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
70254 {
70255 { 0, 0, 0, 0 },
70256 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70257 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c800 }
70258 },
70259/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
70260 {
70261 { 0, 0, 0, 0 },
70262 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70263 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c800 }
70264 },
70265/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
70266 {
70267 { 0, 0, 0, 0 },
70268 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70269 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e800 }
70270 },
70271/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
70272 {
70273 { 0, 0, 0, 0 },
70274 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70275 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c800 }
70276 },
70277/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
70278 {
70279 { 0, 0, 0, 0 },
70280 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
70281 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c800 }
70282 },
70283/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
70284 {
70285 { 0, 0, 0, 0 },
70286 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
70287 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e800 }
70288 },
70289/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
70290 {
70291 { 0, 0, 0, 0 },
70292 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
70293 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c800 }
70294 },
70295/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
70296 {
70297 { 0, 0, 0, 0 },
70298 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
70299 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78800 }
70300 },
70301/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
70302 {
70303 { 0, 0, 0, 0 },
70304 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
70305 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a800 }
70306 },
70307/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
70308 {
70309 { 0, 0, 0, 0 },
70310 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
70311 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878800 }
70312 },
70313/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70314 {
70315 { 0, 0, 0, 0 },
70316 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70317 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980800 }
70318 },
70319/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
70320 {
70321 { 0, 0, 0, 0 },
70322 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70323 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982800 }
70324 },
70325/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
70326 {
70327 { 0, 0, 0, 0 },
70328 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70329 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983800 }
70330 },
70331/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70332 {
70333 { 0, 0, 0, 0 },
70334 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70335 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908800 }
70336 },
70337/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
70338 {
70339 { 0, 0, 0, 0 },
70340 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70341 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a800 }
70342 },
70343/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
70344 {
70345 { 0, 0, 0, 0 },
70346 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70347 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b800 }
70348 },
70349/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70350 {
70351 { 0, 0, 0, 0 },
70352 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70353 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900800 }
70354 },
70355/* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
70356 {
70357 { 0, 0, 0, 0 },
70358 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70359 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902800 }
70360 },
70361/* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
70362 {
70363 { 0, 0, 0, 0 },
70364 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70365 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903800 }
70366 },
70367/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
70368 {
70369 { 0, 0, 0, 0 },
70370 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70371 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920800 }
70372 },
70373/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
70374 {
70375 { 0, 0, 0, 0 },
70376 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70377 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922800 }
70378 },
70379/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
70380 {
70381 { 0, 0, 0, 0 },
70382 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70383 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923800 }
70384 },
70385/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
70386 {
70387 { 0, 0, 0, 0 },
70388 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70389 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940800 }
70390 },
70391/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
70392 {
70393 { 0, 0, 0, 0 },
70394 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70395 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942800 }
70396 },
70397/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
70398 {
70399 { 0, 0, 0, 0 },
70400 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70401 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943800 }
70402 },
70403/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
70404 {
70405 { 0, 0, 0, 0 },
70406 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70407 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960800 }
70408 },
70409/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
70410 {
70411 { 0, 0, 0, 0 },
70412 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70413 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962800 }
70414 },
70415/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
70416 {
70417 { 0, 0, 0, 0 },
70418 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70419 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963800 }
70420 },
70421/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
70422 {
70423 { 0, 0, 0, 0 },
70424 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70425 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928800 }
70426 },
70427/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
70428 {
70429 { 0, 0, 0, 0 },
70430 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70431 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a800 }
70432 },
70433/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
70434 {
70435 { 0, 0, 0, 0 },
70436 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70437 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b800 }
70438 },
70439/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
70440 {
70441 { 0, 0, 0, 0 },
70442 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70443 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948800 }
70444 },
70445/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
70446 {
70447 { 0, 0, 0, 0 },
70448 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70449 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a800 }
70450 },
70451/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
70452 {
70453 { 0, 0, 0, 0 },
70454 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70455 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b800 }
70456 },
70457/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
70458 {
70459 { 0, 0, 0, 0 },
70460 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70461 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c800 }
70462 },
70463/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
70464 {
70465 { 0, 0, 0, 0 },
70466 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70467 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e800 }
70468 },
70469/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
70470 {
70471 { 0, 0, 0, 0 },
70472 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70473 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f800 }
70474 },
70475/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
70476 {
70477 { 0, 0, 0, 0 },
70478 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70479 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c800 }
70480 },
70481/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
70482 {
70483 { 0, 0, 0, 0 },
70484 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70485 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e800 }
70486 },
70487/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
70488 {
70489 { 0, 0, 0, 0 },
70490 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70491 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f800 }
70492 },
70493/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
70494 {
70495 { 0, 0, 0, 0 },
70496 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
70497 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c800 }
70498 },
70499/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
70500 {
70501 { 0, 0, 0, 0 },
70502 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
70503 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e800 }
70504 },
70505/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
70506 {
70507 { 0, 0, 0, 0 },
70508 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
70509 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f800 }
70510 },
70511/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
70512 {
70513 { 0, 0, 0, 0 },
70514 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
70515 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968800 }
70516 },
70517/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
70518 {
70519 { 0, 0, 0, 0 },
70520 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
70521 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a800 }
70522 },
70523/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
70524 {
70525 { 0, 0, 0, 0 },
70526 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
70527 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b800 }
70528 },
70529/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70530 {
70531 { 0, 0, 0, 0 },
70532 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70533 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80800 }
70534 },
70535/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
70536 {
70537 { 0, 0, 0, 0 },
70538 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70539 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82800 }
70540 },
70541/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
70542 {
70543 { 0, 0, 0, 0 },
70544 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70545 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83800 }
70546 },
70547/* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
70548 {
70549 { 0, 0, 0, 0 },
70550 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
70551 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83800 }
70552 },
70553/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70554 {
70555 { 0, 0, 0, 0 },
70556 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70557 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08800 }
70558 },
70559/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
70560 {
70561 { 0, 0, 0, 0 },
70562 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70563 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a800 }
70564 },
70565/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
70566 {
70567 { 0, 0, 0, 0 },
70568 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70569 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b800 }
70570 },
70571/* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
70572 {
70573 { 0, 0, 0, 0 },
70574 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
70575 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b800 }
70576 },
70577/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70578 {
70579 { 0, 0, 0, 0 },
70580 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70581 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00800 }
70582 },
70583/* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
70584 {
70585 { 0, 0, 0, 0 },
70586 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70587 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02800 }
70588 },
70589/* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
70590 {
70591 { 0, 0, 0, 0 },
70592 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70593 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03800 }
70594 },
70595/* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
70596 {
70597 { 0, 0, 0, 0 },
70598 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70599 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03800 }
70600 },
70601/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
70602 {
70603 { 0, 0, 0, 0 },
70604 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70605 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20800 }
70606 },
70607/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
70608 {
70609 { 0, 0, 0, 0 },
70610 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70611 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22800 }
70612 },
70613/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
70614 {
70615 { 0, 0, 0, 0 },
70616 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70617 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23800 }
70618 },
70619/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
70620 {
70621 { 0, 0, 0, 0 },
70622 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70623 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23800 }
70624 },
70625/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
70626 {
70627 { 0, 0, 0, 0 },
70628 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70629 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40800 }
70630 },
70631/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
70632 {
70633 { 0, 0, 0, 0 },
70634 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70635 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42800 }
70636 },
70637/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
70638 {
70639 { 0, 0, 0, 0 },
70640 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70641 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43800 }
70642 },
70643/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
70644 {
70645 { 0, 0, 0, 0 },
70646 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70647 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43800 }
70648 },
70649/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
70650 {
70651 { 0, 0, 0, 0 },
70652 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70653 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60800 }
70654 },
70655/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
70656 {
70657 { 0, 0, 0, 0 },
70658 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70659 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62800 }
70660 },
70661/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
70662 {
70663 { 0, 0, 0, 0 },
70664 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70665 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63800 }
70666 },
70667/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
70668 {
70669 { 0, 0, 0, 0 },
70670 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70671 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63800 }
70672 },
70673/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
70674 {
70675 { 0, 0, 0, 0 },
70676 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70677 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28800 }
70678 },
70679/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
70680 {
70681 { 0, 0, 0, 0 },
70682 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70683 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a800 }
70684 },
70685/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
70686 {
70687 { 0, 0, 0, 0 },
70688 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70689 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b800 }
70690 },
70691/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
70692 {
70693 { 0, 0, 0, 0 },
70694 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70695 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b800 }
70696 },
70697/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
70698 {
70699 { 0, 0, 0, 0 },
70700 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70701 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48800 }
70702 },
70703/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
70704 {
70705 { 0, 0, 0, 0 },
70706 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70707 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a800 }
70708 },
70709/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
70710 {
70711 { 0, 0, 0, 0 },
70712 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70713 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b800 }
70714 },
70715/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
70716 {
70717 { 0, 0, 0, 0 },
70718 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70719 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b800 }
70720 },
70721/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
70722 {
70723 { 0, 0, 0, 0 },
70724 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70725 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c800 }
70726 },
70727/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
70728 {
70729 { 0, 0, 0, 0 },
70730 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70731 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e800 }
70732 },
70733/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
70734 {
70735 { 0, 0, 0, 0 },
70736 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70737 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f800 }
70738 },
70739/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
70740 {
70741 { 0, 0, 0, 0 },
70742 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70743 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f800 }
70744 },
70745/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
70746 {
70747 { 0, 0, 0, 0 },
70748 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70749 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c800 }
70750 },
70751/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
70752 {
70753 { 0, 0, 0, 0 },
70754 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70755 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e800 }
70756 },
70757/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
70758 {
70759 { 0, 0, 0, 0 },
70760 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70761 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f800 }
70762 },
70763/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
70764 {
70765 { 0, 0, 0, 0 },
70766 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70767 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f800 }
70768 },
70769/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
70770 {
70771 { 0, 0, 0, 0 },
70772 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
70773 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c800 }
70774 },
70775/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
70776 {
70777 { 0, 0, 0, 0 },
70778 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
70779 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e800 }
70780 },
70781/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
70782 {
70783 { 0, 0, 0, 0 },
70784 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
70785 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f800 }
70786 },
70787/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
70788 {
70789 { 0, 0, 0, 0 },
70790 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
70791 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f800 }
70792 },
70793/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
70794 {
70795 { 0, 0, 0, 0 },
70796 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
70797 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68800 }
70798 },
70799/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
70800 {
70801 { 0, 0, 0, 0 },
70802 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
70803 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a800 }
70804 },
70805/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
70806 {
70807 { 0, 0, 0, 0 },
70808 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
70809 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b800 }
70810 },
70811/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
70812 {
70813 { 0, 0, 0, 0 },
70814 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
70815 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b800 }
70816 },
70817/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70818 {
70819 { 0, 0, 0, 0 },
70820 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70821 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80800 }
70822 },
70823/* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
70824 {
70825 { 0, 0, 0, 0 },
70826 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
70827 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82800 }
70828 },
70829/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70830 {
70831 { 0, 0, 0, 0 },
70832 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70833 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08800 }
70834 },
70835/* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
70836 {
70837 { 0, 0, 0, 0 },
70838 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
70839 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a800 }
70840 },
70841/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70842 {
70843 { 0, 0, 0, 0 },
70844 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70845 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00800 }
70846 },
70847/* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
70848 {
70849 { 0, 0, 0, 0 },
70850 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70851 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02800 }
70852 },
70853/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
70854 {
70855 { 0, 0, 0, 0 },
70856 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70857 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20800 }
70858 },
70859/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
70860 {
70861 { 0, 0, 0, 0 },
70862 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70863 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22800 }
70864 },
70865/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
70866 {
70867 { 0, 0, 0, 0 },
70868 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70869 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40800 }
70870 },
70871/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
70872 {
70873 { 0, 0, 0, 0 },
70874 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70875 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42800 }
70876 },
70877/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
70878 {
70879 { 0, 0, 0, 0 },
70880 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70881 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60800 }
70882 },
70883/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
70884 {
70885 { 0, 0, 0, 0 },
70886 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70887 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62800 }
70888 },
70889/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
70890 {
70891 { 0, 0, 0, 0 },
70892 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70893 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28800 }
70894 },
70895/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
70896 {
70897 { 0, 0, 0, 0 },
70898 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70899 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a800 }
70900 },
70901/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
70902 {
70903 { 0, 0, 0, 0 },
70904 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70905 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48800 }
70906 },
70907/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
70908 {
70909 { 0, 0, 0, 0 },
70910 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70911 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a800 }
70912 },
70913/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
70914 {
70915 { 0, 0, 0, 0 },
70916 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70917 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c800 }
70918 },
70919/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
70920 {
70921 { 0, 0, 0, 0 },
70922 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70923 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e800 }
70924 },
70925/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
70926 {
70927 { 0, 0, 0, 0 },
70928 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70929 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c800 }
70930 },
70931/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
70932 {
70933 { 0, 0, 0, 0 },
70934 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70935 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e800 }
70936 },
70937/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
70938 {
70939 { 0, 0, 0, 0 },
70940 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
70941 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c800 }
70942 },
70943/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
70944 {
70945 { 0, 0, 0, 0 },
70946 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
70947 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e800 }
70948 },
70949/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
70950 {
70951 { 0, 0, 0, 0 },
70952 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
70953 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68800 }
70954 },
70955/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
70956 {
70957 { 0, 0, 0, 0 },
70958 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
70959 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a800 }
70960 },
70961/* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
70962 {
70963 { 0, 0, 0, 0 },
70964 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
70965 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c808 }
70966 },
70967/* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
70968 {
70969 { 0, 0, 0, 0 },
70970 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
70971 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18828 }
70972 },
70973/* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
70974 {
70975 { 0, 0, 0, 0 },
70976 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70977 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18808 }
70978 },
70979/* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
70980 {
70981 { 0, 0, 0, 0 },
70982 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
70983 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c088 }
70984 },
70985/* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
70986 {
70987 { 0, 0, 0, 0 },
70988 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
70989 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a8 }
70990 },
70991/* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
70992 {
70993 { 0, 0, 0, 0 },
70994 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70995 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18088 }
70996 },
70997/* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
70998 {
70999 { 0, 0, 0, 0 },
71000 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71001 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c008 }
71002 },
71003/* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
71004 {
71005 { 0, 0, 0, 0 },
71006 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71007 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18028 }
71008 },
71009/* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
71010 {
71011 { 0, 0, 0, 0 },
71012 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71013 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18008 }
71014 },
71015/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
71016 {
71017 { 0, 0, 0, 0 },
71018 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71019 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20800 }
71020 },
71021/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
71022 {
71023 { 0, 0, 0, 0 },
71024 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71025 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822800 }
71026 },
71027/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
71028 {
71029 { 0, 0, 0, 0 },
71030 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71031 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820800 }
71032 },
71033/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
71034 {
71035 { 0, 0, 0, 0 },
71036 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71037 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40800 }
71038 },
71039/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
71040 {
71041 { 0, 0, 0, 0 },
71042 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71043 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842800 }
71044 },
71045/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
71046 {
71047 { 0, 0, 0, 0 },
71048 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71049 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840800 }
71050 },
71051/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
71052 {
71053 { 0, 0, 0, 0 },
71054 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71055 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60800 }
71056 },
71057/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
71058 {
71059 { 0, 0, 0, 0 },
71060 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71061 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862800 }
71062 },
71063/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
71064 {
71065 { 0, 0, 0, 0 },
71066 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71067 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860800 }
71068 },
71069/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
71070 {
71071 { 0, 0, 0, 0 },
71072 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71073 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28800 }
71074 },
71075/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
71076 {
71077 { 0, 0, 0, 0 },
71078 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71079 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a800 }
71080 },
71081/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
71082 {
71083 { 0, 0, 0, 0 },
71084 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71085 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828800 }
71086 },
71087/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
71088 {
71089 { 0, 0, 0, 0 },
71090 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71091 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48800 }
71092 },
71093/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
71094 {
71095 { 0, 0, 0, 0 },
71096 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71097 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a800 }
71098 },
71099/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
71100 {
71101 { 0, 0, 0, 0 },
71102 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71103 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848800 }
71104 },
71105/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
71106 {
71107 { 0, 0, 0, 0 },
71108 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71109 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c800 }
71110 },
71111/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
71112 {
71113 { 0, 0, 0, 0 },
71114 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71115 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e800 }
71116 },
71117/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
71118 {
71119 { 0, 0, 0, 0 },
71120 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71121 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c800 }
71122 },
71123/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
71124 {
71125 { 0, 0, 0, 0 },
71126 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71127 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c800 }
71128 },
71129/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
71130 {
71131 { 0, 0, 0, 0 },
71132 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71133 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e800 }
71134 },
71135/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
71136 {
71137 { 0, 0, 0, 0 },
71138 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71139 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c800 }
71140 },
71141/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
71142 {
71143 { 0, 0, 0, 0 },
71144 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
71145 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c800 }
71146 },
71147/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
71148 {
71149 { 0, 0, 0, 0 },
71150 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
71151 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e800 }
71152 },
71153/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
71154 {
71155 { 0, 0, 0, 0 },
71156 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
71157 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c800 }
71158 },
71159/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
71160 {
71161 { 0, 0, 0, 0 },
71162 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
71163 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68800 }
71164 },
71165/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
71166 {
71167 { 0, 0, 0, 0 },
71168 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
71169 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a800 }
71170 },
71171/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
71172 {
71173 { 0, 0, 0, 0 },
71174 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
71175 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868800 }
71176 },
71177/* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
71178 {
71179 { 0, 0, 0, 0 },
71180 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71181 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1890e00 }
71182 },
71183/* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
71184 {
71185 { 0, 0, 0, 0 },
71186 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71187 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1818e00 }
71188 },
71189/* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
71190 {
71191 { 0, 0, 0, 0 },
71192 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71193 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1810e00 }
71194 },
71195/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
71196 {
71197 { 0, 0, 0, 0 },
71198 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71199 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1830e00 }
71200 },
71201/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
71202 {
71203 { 0, 0, 0, 0 },
71204 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71205 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838e00 }
71206 },
71207/* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
71208 {
71209 { 0, 0, 0, 0 },
71210 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71211 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ce00 }
71212 },
71213/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
71214 {
71215 { 0, 0, 0, 0 },
71216 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71217 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1850e00 }
71218 },
71219/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
71220 {
71221 { 0, 0, 0, 0 },
71222 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71223 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858e00 }
71224 },
71225/* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
71226 {
71227 { 0, 0, 0, 0 },
71228 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71229 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ce00 }
71230 },
71231/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
71232 {
71233 { 0, 0, 0, 0 },
71234 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
71235 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ce00 }
71236 },
71237/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
71238 {
71239 { 0, 0, 0, 0 },
71240 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71241 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1870e00 }
71242 },
71243/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
71244 {
71245 { 0, 0, 0, 0 },
71246 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
71247 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1878e00 }
71248 },
71249/* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
71250 {
71251 { 0, 0, 0, 0 },
71252 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
71253 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1880e00 }
71254 },
71255/* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
71256 {
71257 { 0, 0, 0, 0 },
71258 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
71259 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1808e00 }
71260 },
71261/* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
71262 {
71263 { 0, 0, 0, 0 },
71264 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71265 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1800e00 }
71266 },
71267/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
71268 {
71269 { 0, 0, 0, 0 },
71270 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71271 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1820e00 }
71272 },
71273/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
71274 {
71275 { 0, 0, 0, 0 },
71276 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71277 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828e00 }
71278 },
71279/* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
71280 {
71281 { 0, 0, 0, 0 },
71282 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71283 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ce00 }
71284 },
71285/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
71286 {
71287 { 0, 0, 0, 0 },
71288 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71289 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1840e00 }
71290 },
71291/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
71292 {
71293 { 0, 0, 0, 0 },
71294 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71295 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848e00 }
71296 },
71297/* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
71298 {
71299 { 0, 0, 0, 0 },
71300 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71301 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ce00 }
71302 },
71303/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
71304 {
71305 { 0, 0, 0, 0 },
71306 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
71307 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ce00 }
71308 },
71309/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
71310 {
71311 { 0, 0, 0, 0 },
71312 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71313 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1860e00 }
71314 },
71315/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
71316 {
71317 { 0, 0, 0, 0 },
71318 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
71319 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1868e00 }
71320 },
71321/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71322 {
71323 { 0, 0, 0, 0 },
71324 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71325 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990400 }
71326 },
71327/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
71328 {
71329 { 0, 0, 0, 0 },
71330 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71331 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992400 }
71332 },
71333/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
71334 {
71335 { 0, 0, 0, 0 },
71336 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71337 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993400 }
71338 },
71339/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71340 {
71341 { 0, 0, 0, 0 },
71342 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71343 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918400 }
71344 },
71345/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
71346 {
71347 { 0, 0, 0, 0 },
71348 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71349 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a400 }
71350 },
71351/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
71352 {
71353 { 0, 0, 0, 0 },
71354 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71355 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b400 }
71356 },
71357/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71358 {
71359 { 0, 0, 0, 0 },
71360 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71361 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910400 }
71362 },
71363/* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
71364 {
71365 { 0, 0, 0, 0 },
71366 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71367 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912400 }
71368 },
71369/* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
71370 {
71371 { 0, 0, 0, 0 },
71372 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71373 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913400 }
71374 },
71375/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
71376 {
71377 { 0, 0, 0, 0 },
71378 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71379 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930400 }
71380 },
71381/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
71382 {
71383 { 0, 0, 0, 0 },
71384 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71385 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932400 }
71386 },
71387/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
71388 {
71389 { 0, 0, 0, 0 },
71390 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71391 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933400 }
71392 },
71393/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
71394 {
71395 { 0, 0, 0, 0 },
71396 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71397 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950400 }
71398 },
71399/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71400 {
71401 { 0, 0, 0, 0 },
71402 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71403 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952400 }
71404 },
71405/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71406 {
71407 { 0, 0, 0, 0 },
71408 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71409 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953400 }
71410 },
71411/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
71412 {
71413 { 0, 0, 0, 0 },
71414 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71415 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970400 }
71416 },
71417/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71418 {
71419 { 0, 0, 0, 0 },
71420 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71421 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972400 }
71422 },
71423/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71424 {
71425 { 0, 0, 0, 0 },
71426 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71427 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973400 }
71428 },
71429/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
71430 {
71431 { 0, 0, 0, 0 },
71432 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71433 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938400 }
71434 },
71435/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
71436 {
71437 { 0, 0, 0, 0 },
71438 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71439 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a400 }
71440 },
71441/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
71442 {
71443 { 0, 0, 0, 0 },
71444 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71445 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b400 }
71446 },
71447/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
71448 {
71449 { 0, 0, 0, 0 },
71450 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71451 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958400 }
71452 },
71453/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
71454 {
71455 { 0, 0, 0, 0 },
71456 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71457 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a400 }
71458 },
71459/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
71460 {
71461 { 0, 0, 0, 0 },
71462 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71463 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b400 }
71464 },
71465/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
71466 {
71467 { 0, 0, 0, 0 },
71468 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71469 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c400 }
71470 },
71471/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
71472 {
71473 { 0, 0, 0, 0 },
71474 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71475 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e400 }
71476 },
71477/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
71478 {
71479 { 0, 0, 0, 0 },
71480 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71481 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f400 }
71482 },
71483/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
71484 {
71485 { 0, 0, 0, 0 },
71486 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71487 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c400 }
71488 },
71489/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
71490 {
71491 { 0, 0, 0, 0 },
71492 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71493 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e400 }
71494 },
71495/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
71496 {
71497 { 0, 0, 0, 0 },
71498 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71499 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f400 }
71500 },
71501/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
71502 {
71503 { 0, 0, 0, 0 },
71504 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
71505 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c400 }
71506 },
71507/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
71508 {
71509 { 0, 0, 0, 0 },
71510 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71511 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e400 }
71512 },
71513/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
71514 {
71515 { 0, 0, 0, 0 },
71516 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71517 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f400 }
71518 },
71519/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
71520 {
71521 { 0, 0, 0, 0 },
71522 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
71523 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978400 }
71524 },
71525/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
71526 {
71527 { 0, 0, 0, 0 },
71528 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
71529 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a400 }
71530 },
71531/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
71532 {
71533 { 0, 0, 0, 0 },
71534 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
71535 & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b400 }
71536 },
71537/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71538 {
71539 { 0, 0, 0, 0 },
71540 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71541 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90400 }
71542 },
71543/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
71544 {
71545 { 0, 0, 0, 0 },
71546 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71547 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92400 }
71548 },
71549/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
71550 {
71551 { 0, 0, 0, 0 },
71552 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71553 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93400 }
71554 },
71555/* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
71556 {
71557 { 0, 0, 0, 0 },
71558 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
71559 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93400 }
71560 },
71561/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71562 {
71563 { 0, 0, 0, 0 },
71564 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71565 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18400 }
71566 },
71567/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
71568 {
71569 { 0, 0, 0, 0 },
71570 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71571 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a400 }
71572 },
71573/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
71574 {
71575 { 0, 0, 0, 0 },
71576 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71577 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b400 }
71578 },
71579/* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
71580 {
71581 { 0, 0, 0, 0 },
71582 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
71583 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b400 }
71584 },
71585/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71586 {
71587 { 0, 0, 0, 0 },
71588 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71589 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10400 }
71590 },
71591/* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
71592 {
71593 { 0, 0, 0, 0 },
71594 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71595 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12400 }
71596 },
71597/* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
71598 {
71599 { 0, 0, 0, 0 },
71600 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71601 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13400 }
71602 },
71603/* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
71604 {
71605 { 0, 0, 0, 0 },
71606 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71607 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13400 }
71608 },
71609/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
71610 {
71611 { 0, 0, 0, 0 },
71612 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71613 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30400 }
71614 },
71615/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
71616 {
71617 { 0, 0, 0, 0 },
71618 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71619 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32400 }
71620 },
71621/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
71622 {
71623 { 0, 0, 0, 0 },
71624 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71625 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33400 }
71626 },
71627/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
71628 {
71629 { 0, 0, 0, 0 },
71630 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71631 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33400 }
71632 },
71633/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
71634 {
71635 { 0, 0, 0, 0 },
71636 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71637 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50400 }
71638 },
71639/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
71640 {
71641 { 0, 0, 0, 0 },
71642 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71643 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52400 }
71644 },
71645/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
71646 {
71647 { 0, 0, 0, 0 },
71648 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71649 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53400 }
71650 },
71651/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
71652 {
71653 { 0, 0, 0, 0 },
71654 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71655 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53400 }
71656 },
71657/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
71658 {
71659 { 0, 0, 0, 0 },
71660 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71661 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70400 }
71662 },
71663/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
71664 {
71665 { 0, 0, 0, 0 },
71666 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71667 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72400 }
71668 },
71669/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
71670 {
71671 { 0, 0, 0, 0 },
71672 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71673 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73400 }
71674 },
71675/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
71676 {
71677 { 0, 0, 0, 0 },
71678 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71679 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73400 }
71680 },
71681/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
71682 {
71683 { 0, 0, 0, 0 },
71684 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71685 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38400 }
71686 },
71687/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
71688 {
71689 { 0, 0, 0, 0 },
71690 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71691 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a400 }
71692 },
71693/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
71694 {
71695 { 0, 0, 0, 0 },
71696 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71697 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b400 }
71698 },
71699/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
71700 {
71701 { 0, 0, 0, 0 },
71702 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71703 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b400 }
71704 },
71705/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
71706 {
71707 { 0, 0, 0, 0 },
71708 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71709 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58400 }
71710 },
71711/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
71712 {
71713 { 0, 0, 0, 0 },
71714 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71715 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a400 }
71716 },
71717/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
71718 {
71719 { 0, 0, 0, 0 },
71720 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71721 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b400 }
71722 },
71723/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
71724 {
71725 { 0, 0, 0, 0 },
71726 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71727 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b400 }
71728 },
71729/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
71730 {
71731 { 0, 0, 0, 0 },
71732 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71733 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c400 }
71734 },
71735/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
71736 {
71737 { 0, 0, 0, 0 },
71738 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71739 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e400 }
71740 },
71741/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
71742 {
71743 { 0, 0, 0, 0 },
71744 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71745 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f400 }
71746 },
71747/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
71748 {
71749 { 0, 0, 0, 0 },
71750 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71751 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f400 }
71752 },
71753/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
71754 {
71755 { 0, 0, 0, 0 },
71756 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71757 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c400 }
71758 },
71759/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
71760 {
71761 { 0, 0, 0, 0 },
71762 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71763 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e400 }
71764 },
71765/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
71766 {
71767 { 0, 0, 0, 0 },
71768 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71769 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f400 }
71770 },
71771/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
71772 {
71773 { 0, 0, 0, 0 },
71774 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71775 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f400 }
71776 },
71777/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
71778 {
71779 { 0, 0, 0, 0 },
71780 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
71781 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c400 }
71782 },
71783/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
71784 {
71785 { 0, 0, 0, 0 },
71786 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
71787 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e400 }
71788 },
71789/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
71790 {
71791 { 0, 0, 0, 0 },
71792 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
71793 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f400 }
71794 },
71795/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
71796 {
71797 { 0, 0, 0, 0 },
71798 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
71799 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f400 }
71800 },
71801/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
71802 {
71803 { 0, 0, 0, 0 },
71804 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
71805 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78400 }
71806 },
71807/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
71808 {
71809 { 0, 0, 0, 0 },
71810 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
71811 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a400 }
71812 },
71813/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
71814 {
71815 { 0, 0, 0, 0 },
71816 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
71817 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b400 }
71818 },
71819/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
71820 {
71821 { 0, 0, 0, 0 },
71822 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
71823 & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b400 }
71824 },
71825/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71826 {
71827 { 0, 0, 0, 0 },
71828 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71829 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90400 }
71830 },
71831/* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
71832 {
71833 { 0, 0, 0, 0 },
71834 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
71835 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92400 }
71836 },
71837/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71838 {
71839 { 0, 0, 0, 0 },
71840 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71841 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18400 }
71842 },
71843/* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
71844 {
71845 { 0, 0, 0, 0 },
71846 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
71847 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a400 }
71848 },
71849/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71850 {
71851 { 0, 0, 0, 0 },
71852 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71853 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10400 }
71854 },
71855/* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
71856 {
71857 { 0, 0, 0, 0 },
71858 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71859 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12400 }
71860 },
71861/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
71862 {
71863 { 0, 0, 0, 0 },
71864 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71865 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30400 }
71866 },
71867/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
71868 {
71869 { 0, 0, 0, 0 },
71870 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71871 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32400 }
71872 },
71873/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
71874 {
71875 { 0, 0, 0, 0 },
71876 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71877 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50400 }
71878 },
71879/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
71880 {
71881 { 0, 0, 0, 0 },
71882 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71883 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52400 }
71884 },
71885/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
71886 {
71887 { 0, 0, 0, 0 },
71888 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71889 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70400 }
71890 },
71891/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
71892 {
71893 { 0, 0, 0, 0 },
71894 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71895 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72400 }
71896 },
71897/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
71898 {
71899 { 0, 0, 0, 0 },
71900 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
71901 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38400 }
71902 },
71903/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
71904 {
71905 { 0, 0, 0, 0 },
71906 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
71907 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a400 }
71908 },
71909/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
71910 {
71911 { 0, 0, 0, 0 },
71912 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
71913 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58400 }
71914 },
71915/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
71916 {
71917 { 0, 0, 0, 0 },
71918 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
71919 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a400 }
71920 },
71921/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
71922 {
71923 { 0, 0, 0, 0 },
71924 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
71925 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c400 }
71926 },
71927/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
71928 {
71929 { 0, 0, 0, 0 },
71930 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
71931 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e400 }
71932 },
71933/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
71934 {
71935 { 0, 0, 0, 0 },
71936 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
71937 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c400 }
71938 },
71939/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
71940 {
71941 { 0, 0, 0, 0 },
71942 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
71943 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e400 }
71944 },
71945/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
71946 {
71947 { 0, 0, 0, 0 },
71948 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
71949 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c400 }
71950 },
71951/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
71952 {
71953 { 0, 0, 0, 0 },
71954 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
71955 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e400 }
71956 },
71957/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
71958 {
71959 { 0, 0, 0, 0 },
71960 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
71961 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78400 }
71962 },
71963/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
71964 {
71965 { 0, 0, 0, 0 },
71966 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
71967 & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a400 }
71968 },
71969/* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
71970 {
71971 { 0, 0, 0, 0 },
71972 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71973 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c904 }
71974 },
71975/* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
71976 {
71977 { 0, 0, 0, 0 },
71978 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71979 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18924 }
71980 },
71981/* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
71982 {
71983 { 0, 0, 0, 0 },
71984 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71985 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18904 }
71986 },
71987/* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
71988 {
71989 { 0, 0, 0, 0 },
71990 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71991 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c184 }
71992 },
71993/* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
71994 {
71995 { 0, 0, 0, 0 },
71996 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71997 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a4 }
71998 },
71999/* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
72000 {
72001 { 0, 0, 0, 0 },
72002 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
72003 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18184 }
72004 },
72005/* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
72006 {
72007 { 0, 0, 0, 0 },
72008 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72009 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c104 }
72010 },
72011/* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
72012 {
72013 { 0, 0, 0, 0 },
72014 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72015 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18124 }
72016 },
72017/* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
72018 {
72019 { 0, 0, 0, 0 },
72020 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72021 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18104 }
72022 },
72023/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72024 {
72025 { 0, 0, 0, 0 },
72026 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72027 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30400 }
72028 },
72029/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72030 {
72031 { 0, 0, 0, 0 },
72032 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72033 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832400 }
72034 },
72035/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
72036 {
72037 { 0, 0, 0, 0 },
72038 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72039 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830400 }
72040 },
72041/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72042 {
72043 { 0, 0, 0, 0 },
72044 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72045 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50400 }
72046 },
72047/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72048 {
72049 { 0, 0, 0, 0 },
72050 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72051 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852400 }
72052 },
72053/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
72054 {
72055 { 0, 0, 0, 0 },
72056 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72057 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850400 }
72058 },
72059/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72060 {
72061 { 0, 0, 0, 0 },
72062 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72063 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70400 }
72064 },
72065/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72066 {
72067 { 0, 0, 0, 0 },
72068 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72069 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872400 }
72070 },
72071/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
72072 {
72073 { 0, 0, 0, 0 },
72074 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72075 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870400 }
72076 },
72077/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
72078 {
72079 { 0, 0, 0, 0 },
72080 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72081 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38400 }
72082 },
72083/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
72084 {
72085 { 0, 0, 0, 0 },
72086 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72087 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a400 }
72088 },
72089/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
72090 {
72091 { 0, 0, 0, 0 },
72092 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72093 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838400 }
72094 },
72095/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
72096 {
72097 { 0, 0, 0, 0 },
72098 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72099 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58400 }
72100 },
72101/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
72102 {
72103 { 0, 0, 0, 0 },
72104 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72105 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a400 }
72106 },
72107/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
72108 {
72109 { 0, 0, 0, 0 },
72110 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72111 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858400 }
72112 },
72113/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
72114 {
72115 { 0, 0, 0, 0 },
72116 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72117 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c400 }
72118 },
72119/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
72120 {
72121 { 0, 0, 0, 0 },
72122 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72123 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e400 }
72124 },
72125/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
72126 {
72127 { 0, 0, 0, 0 },
72128 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72129 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c400 }
72130 },
72131/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
72132 {
72133 { 0, 0, 0, 0 },
72134 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72135 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c400 }
72136 },
72137/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
72138 {
72139 { 0, 0, 0, 0 },
72140 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72141 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e400 }
72142 },
72143/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
72144 {
72145 { 0, 0, 0, 0 },
72146 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72147 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c400 }
72148 },
72149/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
72150 {
72151 { 0, 0, 0, 0 },
72152 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
72153 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c400 }
72154 },
72155/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
72156 {
72157 { 0, 0, 0, 0 },
72158 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
72159 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e400 }
72160 },
72161/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
72162 {
72163 { 0, 0, 0, 0 },
72164 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
72165 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c400 }
72166 },
72167/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
72168 {
72169 { 0, 0, 0, 0 },
72170 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
72171 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78400 }
72172 },
72173/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
72174 {
72175 { 0, 0, 0, 0 },
72176 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
72177 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a400 }
72178 },
72179/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
72180 {
72181 { 0, 0, 0, 0 },
72182 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
72183 & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878400 }
72184 },
72185/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72186 {
72187 { 0, 0, 0, 0 },
72188 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72189 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980400 }
72190 },
72191/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
72192 {
72193 { 0, 0, 0, 0 },
72194 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72195 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982400 }
72196 },
72197/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
72198 {
72199 { 0, 0, 0, 0 },
72200 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72201 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983400 }
72202 },
72203/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72204 {
72205 { 0, 0, 0, 0 },
72206 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72207 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908400 }
72208 },
72209/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
72210 {
72211 { 0, 0, 0, 0 },
72212 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72213 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a400 }
72214 },
72215/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
72216 {
72217 { 0, 0, 0, 0 },
72218 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72219 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b400 }
72220 },
72221/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72222 {
72223 { 0, 0, 0, 0 },
72224 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72225 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900400 }
72226 },
72227/* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
72228 {
72229 { 0, 0, 0, 0 },
72230 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72231 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902400 }
72232 },
72233/* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
72234 {
72235 { 0, 0, 0, 0 },
72236 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72237 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903400 }
72238 },
72239/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
72240 {
72241 { 0, 0, 0, 0 },
72242 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72243 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920400 }
72244 },
72245/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
72246 {
72247 { 0, 0, 0, 0 },
72248 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72249 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922400 }
72250 },
72251/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
72252 {
72253 { 0, 0, 0, 0 },
72254 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72255 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923400 }
72256 },
72257/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
72258 {
72259 { 0, 0, 0, 0 },
72260 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72261 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940400 }
72262 },
72263/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
72264 {
72265 { 0, 0, 0, 0 },
72266 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72267 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942400 }
72268 },
72269/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
72270 {
72271 { 0, 0, 0, 0 },
72272 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72273 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943400 }
72274 },
72275/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
72276 {
72277 { 0, 0, 0, 0 },
72278 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72279 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960400 }
72280 },
72281/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
72282 {
72283 { 0, 0, 0, 0 },
72284 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72285 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962400 }
72286 },
72287/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
72288 {
72289 { 0, 0, 0, 0 },
72290 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72291 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963400 }
72292 },
72293/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
72294 {
72295 { 0, 0, 0, 0 },
72296 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72297 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928400 }
72298 },
72299/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
72300 {
72301 { 0, 0, 0, 0 },
72302 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72303 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a400 }
72304 },
72305/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
72306 {
72307 { 0, 0, 0, 0 },
72308 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72309 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b400 }
72310 },
72311/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
72312 {
72313 { 0, 0, 0, 0 },
72314 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72315 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948400 }
72316 },
72317/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
72318 {
72319 { 0, 0, 0, 0 },
72320 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72321 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a400 }
72322 },
72323/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
72324 {
72325 { 0, 0, 0, 0 },
72326 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72327 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b400 }
72328 },
72329/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
72330 {
72331 { 0, 0, 0, 0 },
72332 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72333 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c400 }
72334 },
72335/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
72336 {
72337 { 0, 0, 0, 0 },
72338 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72339 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e400 }
72340 },
72341/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
72342 {
72343 { 0, 0, 0, 0 },
72344 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72345 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f400 }
72346 },
72347/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
72348 {
72349 { 0, 0, 0, 0 },
72350 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
72351 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c400 }
72352 },
72353/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
72354 {
72355 { 0, 0, 0, 0 },
72356 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
72357 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e400 }
72358 },
72359/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
72360 {
72361 { 0, 0, 0, 0 },
72362 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
72363 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f400 }
72364 },
72365/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
72366 {
72367 { 0, 0, 0, 0 },
72368 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
72369 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c400 }
72370 },
72371/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
72372 {
72373 { 0, 0, 0, 0 },
72374 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
72375 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e400 }
72376 },
72377/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
72378 {
72379 { 0, 0, 0, 0 },
72380 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
72381 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f400 }
72382 },
72383/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
72384 {
72385 { 0, 0, 0, 0 },
72386 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
72387 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968400 }
72388 },
72389/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
72390 {
72391 { 0, 0, 0, 0 },
72392 { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
72393 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a400 }
72394 },
72395/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
72396 {
72397 { 0, 0, 0, 0 },
72398 { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
72399 & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b400 }
72400 },
72401/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72402 {
72403 { 0, 0, 0, 0 },
72404 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72405 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80400 }
72406 },
72407/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
72408 {
72409 { 0, 0, 0, 0 },
72410 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72411 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82400 }
72412 },
72413/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
72414 {
72415 { 0, 0, 0, 0 },
72416 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72417 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83400 }
72418 },
72419/* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
72420 {
72421 { 0, 0, 0, 0 },
72422 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
72423 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83400 }
72424 },
72425/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72426 {
72427 { 0, 0, 0, 0 },
72428 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72429 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08400 }
72430 },
72431/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
72432 {
72433 { 0, 0, 0, 0 },
72434 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72435 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a400 }
72436 },
72437/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
72438 {
72439 { 0, 0, 0, 0 },
72440 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72441 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b400 }
72442 },
72443/* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
72444 {
72445 { 0, 0, 0, 0 },
72446 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
72447 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b400 }
72448 },
72449/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72450 {
72451 { 0, 0, 0, 0 },
72452 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72453 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00400 }
72454 },
72455/* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
72456 {
72457 { 0, 0, 0, 0 },
72458 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72459 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02400 }
72460 },
72461/* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
72462 {
72463 { 0, 0, 0, 0 },
72464 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72465 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03400 }
72466 },
72467/* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
72468 {
72469 { 0, 0, 0, 0 },
72470 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72471 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03400 }
72472 },
72473/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
72474 {
72475 { 0, 0, 0, 0 },
72476 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72477 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20400 }
72478 },
72479/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
72480 {
72481 { 0, 0, 0, 0 },
72482 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72483 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22400 }
72484 },
72485/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
72486 {
72487 { 0, 0, 0, 0 },
72488 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72489 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23400 }
72490 },
72491/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
72492 {
72493 { 0, 0, 0, 0 },
72494 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72495 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23400 }
72496 },
72497/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
72498 {
72499 { 0, 0, 0, 0 },
72500 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72501 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40400 }
72502 },
72503/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
72504 {
72505 { 0, 0, 0, 0 },
72506 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72507 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42400 }
72508 },
72509/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
72510 {
72511 { 0, 0, 0, 0 },
72512 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72513 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43400 }
72514 },
72515/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
72516 {
72517 { 0, 0, 0, 0 },
72518 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72519 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43400 }
72520 },
72521/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
72522 {
72523 { 0, 0, 0, 0 },
72524 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72525 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60400 }
72526 },
72527/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
72528 {
72529 { 0, 0, 0, 0 },
72530 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72531 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62400 }
72532 },
72533/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
72534 {
72535 { 0, 0, 0, 0 },
72536 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72537 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63400 }
72538 },
72539/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
72540 {
72541 { 0, 0, 0, 0 },
72542 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72543 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63400 }
72544 },
72545/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
72546 {
72547 { 0, 0, 0, 0 },
72548 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72549 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28400 }
72550 },
72551/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
72552 {
72553 { 0, 0, 0, 0 },
72554 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72555 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a400 }
72556 },
72557/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
72558 {
72559 { 0, 0, 0, 0 },
72560 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72561 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b400 }
72562 },
72563/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
72564 {
72565 { 0, 0, 0, 0 },
72566 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72567 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b400 }
72568 },
72569/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
72570 {
72571 { 0, 0, 0, 0 },
72572 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72573 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48400 }
72574 },
72575/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
72576 {
72577 { 0, 0, 0, 0 },
72578 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72579 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a400 }
72580 },
72581/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
72582 {
72583 { 0, 0, 0, 0 },
72584 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72585 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b400 }
72586 },
72587/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
72588 {
72589 { 0, 0, 0, 0 },
72590 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72591 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b400 }
72592 },
72593/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
72594 {
72595 { 0, 0, 0, 0 },
72596 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72597 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c400 }
72598 },
72599/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
72600 {
72601 { 0, 0, 0, 0 },
72602 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72603 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e400 }
72604 },
72605/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
72606 {
72607 { 0, 0, 0, 0 },
72608 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72609 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f400 }
72610 },
72611/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
72612 {
72613 { 0, 0, 0, 0 },
72614 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72615 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f400 }
72616 },
72617/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
72618 {
72619 { 0, 0, 0, 0 },
72620 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72621 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c400 }
72622 },
72623/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
72624 {
72625 { 0, 0, 0, 0 },
72626 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72627 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e400 }
72628 },
72629/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
72630 {
72631 { 0, 0, 0, 0 },
72632 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72633 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f400 }
72634 },
72635/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
72636 {
72637 { 0, 0, 0, 0 },
72638 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72639 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f400 }
72640 },
72641/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
72642 {
72643 { 0, 0, 0, 0 },
72644 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
72645 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c400 }
72646 },
72647/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
72648 {
72649 { 0, 0, 0, 0 },
72650 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
72651 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e400 }
72652 },
72653/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
72654 {
72655 { 0, 0, 0, 0 },
72656 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
72657 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f400 }
72658 },
72659/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
72660 {
72661 { 0, 0, 0, 0 },
72662 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
72663 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f400 }
72664 },
72665/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
72666 {
72667 { 0, 0, 0, 0 },
72668 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
72669 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68400 }
72670 },
72671/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
72672 {
72673 { 0, 0, 0, 0 },
72674 { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
72675 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a400 }
72676 },
72677/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
72678 {
72679 { 0, 0, 0, 0 },
72680 { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
72681 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b400 }
72682 },
72683/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
72684 {
72685 { 0, 0, 0, 0 },
72686 { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
72687 & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b400 }
72688 },
72689/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72690 {
72691 { 0, 0, 0, 0 },
72692 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72693 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80400 }
72694 },
72695/* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
72696 {
72697 { 0, 0, 0, 0 },
72698 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
72699 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82400 }
72700 },
72701/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72702 {
72703 { 0, 0, 0, 0 },
72704 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72705 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08400 }
72706 },
72707/* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
72708 {
72709 { 0, 0, 0, 0 },
72710 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
72711 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a400 }
72712 },
72713/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72714 {
72715 { 0, 0, 0, 0 },
72716 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72717 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00400 }
72718 },
72719/* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
72720 {
72721 { 0, 0, 0, 0 },
72722 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72723 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02400 }
72724 },
72725/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
72726 {
72727 { 0, 0, 0, 0 },
72728 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72729 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20400 }
72730 },
72731/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
72732 {
72733 { 0, 0, 0, 0 },
72734 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72735 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22400 }
72736 },
72737/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
72738 {
72739 { 0, 0, 0, 0 },
72740 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72741 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40400 }
72742 },
72743/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
72744 {
72745 { 0, 0, 0, 0 },
72746 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72747 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42400 }
72748 },
72749/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
72750 {
72751 { 0, 0, 0, 0 },
72752 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72753 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60400 }
72754 },
72755/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
72756 {
72757 { 0, 0, 0, 0 },
72758 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72759 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62400 }
72760 },
72761/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
72762 {
72763 { 0, 0, 0, 0 },
72764 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
72765 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28400 }
72766 },
72767/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
72768 {
72769 { 0, 0, 0, 0 },
72770 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
72771 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a400 }
72772 },
72773/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
72774 {
72775 { 0, 0, 0, 0 },
72776 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
72777 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48400 }
72778 },
72779/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
72780 {
72781 { 0, 0, 0, 0 },
72782 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
72783 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a400 }
72784 },
72785/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
72786 {
72787 { 0, 0, 0, 0 },
72788 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
72789 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c400 }
72790 },
72791/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
72792 {
72793 { 0, 0, 0, 0 },
72794 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
72795 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e400 }
72796 },
72797/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
72798 {
72799 { 0, 0, 0, 0 },
72800 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
72801 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c400 }
72802 },
72803/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
72804 {
72805 { 0, 0, 0, 0 },
72806 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
72807 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e400 }
72808 },
72809/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
72810 {
72811 { 0, 0, 0, 0 },
72812 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
72813 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c400 }
72814 },
72815/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
72816 {
72817 { 0, 0, 0, 0 },
72818 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
72819 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e400 }
72820 },
72821/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
72822 {
72823 { 0, 0, 0, 0 },
72824 { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
72825 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68400 }
72826 },
72827/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
72828 {
72829 { 0, 0, 0, 0 },
72830 { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
72831 & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a400 }
72832 },
72833/* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
72834 {
72835 { 0, 0, 0, 0 },
72836 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
72837 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c804 }
72838 },
72839/* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
72840 {
72841 { 0, 0, 0, 0 },
72842 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
72843 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18824 }
72844 },
72845/* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
72846 {
72847 { 0, 0, 0, 0 },
72848 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72849 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18804 }
72850 },
72851/* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
72852 {
72853 { 0, 0, 0, 0 },
72854 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
72855 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c084 }
72856 },
72857/* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
72858 {
72859 { 0, 0, 0, 0 },
72860 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
72861 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a4 }
72862 },
72863/* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
72864 {
72865 { 0, 0, 0, 0 },
72866 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72867 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18084 }
72868 },
72869/* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
72870 {
72871 { 0, 0, 0, 0 },
72872 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72873 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c004 }
72874 },
72875/* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
72876 {
72877 { 0, 0, 0, 0 },
72878 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72879 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18024 }
72880 },
72881/* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
72882 {
72883 { 0, 0, 0, 0 },
72884 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72885 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18004 }
72886 },
72887/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72888 {
72889 { 0, 0, 0, 0 },
72890 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72891 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20400 }
72892 },
72893/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72894 {
72895 { 0, 0, 0, 0 },
72896 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72897 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822400 }
72898 },
72899/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
72900 {
72901 { 0, 0, 0, 0 },
72902 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72903 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820400 }
72904 },
72905/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72906 {
72907 { 0, 0, 0, 0 },
72908 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72909 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40400 }
72910 },
72911/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72912 {
72913 { 0, 0, 0, 0 },
72914 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72915 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842400 }
72916 },
72917/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
72918 {
72919 { 0, 0, 0, 0 },
72920 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72921 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840400 }
72922 },
72923/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72924 {
72925 { 0, 0, 0, 0 },
72926 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72927 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60400 }
72928 },
72929/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72930 {
72931 { 0, 0, 0, 0 },
72932 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72933 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862400 }
72934 },
72935/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
72936 {
72937 { 0, 0, 0, 0 },
72938 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72939 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860400 }
72940 },
72941/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
72942 {
72943 { 0, 0, 0, 0 },
72944 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72945 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28400 }
72946 },
72947/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
72948 {
72949 { 0, 0, 0, 0 },
72950 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72951 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a400 }
72952 },
72953/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
72954 {
72955 { 0, 0, 0, 0 },
72956 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72957 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828400 }
72958 },
72959/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
72960 {
72961 { 0, 0, 0, 0 },
72962 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72963 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48400 }
72964 },
72965/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
72966 {
72967 { 0, 0, 0, 0 },
72968 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72969 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a400 }
72970 },
72971/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
72972 {
72973 { 0, 0, 0, 0 },
72974 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72975 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848400 }
72976 },
72977/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
72978 {
72979 { 0, 0, 0, 0 },
72980 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72981 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c400 }
72982 },
72983/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
72984 {
72985 { 0, 0, 0, 0 },
72986 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72987 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e400 }
72988 },
72989/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
72990 {
72991 { 0, 0, 0, 0 },
72992 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72993 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c400 }
72994 },
72995/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
72996 {
72997 { 0, 0, 0, 0 },
72998 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72999 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c400 }
73000 },
73001/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
73002 {
73003 { 0, 0, 0, 0 },
73004 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
73005 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e400 }
73006 },
73007/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
73008 {
73009 { 0, 0, 0, 0 },
73010 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
73011 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c400 }
73012 },
73013/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
73014 {
73015 { 0, 0, 0, 0 },
73016 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
73017 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c400 }
73018 },
73019/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
73020 {
73021 { 0, 0, 0, 0 },
73022 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
73023 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e400 }
73024 },
73025/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
73026 {
73027 { 0, 0, 0, 0 },
73028 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
73029 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c400 }
73030 },
73031/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
73032 {
73033 { 0, 0, 0, 0 },
73034 { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
73035 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68400 }
73036 },
73037/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
73038 {
73039 { 0, 0, 0, 0 },
73040 { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
73041 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a400 }
73042 },
73043/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
73044 {
73045 { 0, 0, 0, 0 },
73046 { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
73047 & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868400 }
73048 },
73049/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
73050 {
73051 { 0, 0, 0, 0 },
73052 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
73053 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb18000 }
73054 },
73055/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
73056 {
73057 { 0, 0, 0, 0 },
73058 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
73059 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1a000 }
73060 },
73061/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
73062 {
73063 { 0, 0, 0, 0 },
73064 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
73065 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb1b000 }
73066 },
73067/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
73068 {
73069 { 0, 0, 0, 0 },
73070 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
73071 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb18400 }
73072 },
73073/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
73074 {
73075 { 0, 0, 0, 0 },
73076 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
73077 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb1a400 }
73078 },
73079/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
73080 {
73081 { 0, 0, 0, 0 },
73082 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
73083 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb1b400 }
73084 },
73085/* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
73086 {
73087 { 0, 0, 0, 0 },
73088 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73089 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb18600 }
73090 },
73091/* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
73092 {
73093 { 0, 0, 0, 0 },
73094 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73095 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb1a600 }
73096 },
73097/* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
73098 {
73099 { 0, 0, 0, 0 },
73100 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73101 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb1b600 }
73102 },
73103/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
73104 {
73105 { 0, 0, 0, 0 },
73106 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73107 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb1880000 }
73108 },
73109/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
73110 {
73111 { 0, 0, 0, 0 },
73112 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73113 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1a80000 }
73114 },
73115/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
73116 {
73117 { 0, 0, 0, 0 },
73118 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73119 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1b80000 }
73120 },
73121/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
73122 {
73123 { 0, 0, 0, 0 },
73124 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73125 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb18c0000 }
73126 },
73127/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
73128 {
73129 { 0, 0, 0, 0 },
73130 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73131 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1ac0000 }
73132 },
73133/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
73134 {
73135 { 0, 0, 0, 0 },
73136 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73137 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1bc0000 }
73138 },
73139/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
73140 {
73141 { 0, 0, 0, 0 },
73142 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73143 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb18a0000 }
73144 },
73145/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
73146 {
73147 { 0, 0, 0, 0 },
73148 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73149 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1aa0000 }
73150 },
73151/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
73152 {
73153 { 0, 0, 0, 0 },
73154 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73155 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1ba0000 }
73156 },
73157/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
73158 {
73159 { 0, 0, 0, 0 },
73160 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73161 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb18e0000 }
73162 },
73163/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
73164 {
73165 { 0, 0, 0, 0 },
73166 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73167 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1ae0000 }
73168 },
73169/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
73170 {
73171 { 0, 0, 0, 0 },
73172 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73173 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1be0000 }
73174 },
73175/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
73176 {
73177 { 0, 0, 0, 0 },
73178 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73179 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb18b0000 }
73180 },
73181/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
73182 {
73183 { 0, 0, 0, 0 },
73184 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73185 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1ab0000 }
73186 },
73187/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
73188 {
73189 { 0, 0, 0, 0 },
73190 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73191 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1bb0000 }
73192 },
73193/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
73194 {
73195 { 0, 0, 0, 0 },
73196 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
73197 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb18f0000 }
73198 },
73199/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
73200 {
73201 { 0, 0, 0, 0 },
73202 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73203 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb1af0000 }
73204 },
73205/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
73206 {
73207 { 0, 0, 0, 0 },
73208 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73209 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb1bf0000 }
73210 },
73211/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
73212 {
73213 { 0, 0, 0, 0 },
73214 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
73215 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb1c00000 }
73216 },
73217/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
73218 {
73219 { 0, 0, 0, 0 },
73220 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
73221 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1e00000 }
73222 },
73223/* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
73224 {
73225 { 0, 0, 0, 0 },
73226 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
73227 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb1f00000 }
73228 },
73229/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
73230 {
73231 { 0, 0, 0, 0 },
73232 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
73233 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb1c40000 }
73234 },
73235/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
73236 {
73237 { 0, 0, 0, 0 },
73238 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
73239 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb1e40000 }
73240 },
73241/* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
73242 {
73243 { 0, 0, 0, 0 },
73244 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
73245 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb1f40000 }
73246 },
73247/* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
73248 {
73249 { 0, 0, 0, 0 },
73250 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73251 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb1c60000 }
73252 },
73253/* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
73254 {
73255 { 0, 0, 0, 0 },
73256 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73257 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb1e60000 }
73258 },
73259/* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
73260 {
73261 { 0, 0, 0, 0 },
73262 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
73263 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb1f60000 }
73264 },
73265/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
73266 {
73267 { 0, 0, 0, 0 },
73268 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73269 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb1c80000 }
73270 },
73271/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
73272 {
73273 { 0, 0, 0, 0 },
73274 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73275 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb1e80000 }
73276 },
73277/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
73278 {
73279 { 0, 0, 0, 0 },
73280 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73281 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb1f80000 }
73282 },
73283/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
73284 {
73285 { 0, 0, 0, 0 },
73286 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73287 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb1cc0000 }
73288 },
73289/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
73290 {
73291 { 0, 0, 0, 0 },
73292 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73293 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb1ec0000 }
73294 },
73295/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
73296 {
73297 { 0, 0, 0, 0 },
73298 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73299 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb1fc0000 }
73300 },
73301/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
73302 {
73303 { 0, 0, 0, 0 },
73304 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73305 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ca0000 }
73306 },
73307/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
73308 {
73309 { 0, 0, 0, 0 },
73310 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73311 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ea0000 }
73312 },
73313/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
73314 {
73315 { 0, 0, 0, 0 },
73316 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73317 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb1fa0000 }
73318 },
73319/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
73320 {
73321 { 0, 0, 0, 0 },
73322 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73323 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ce0000 }
73324 },
73325/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
73326 {
73327 { 0, 0, 0, 0 },
73328 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73329 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ee0000 }
73330 },
73331/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
73332 {
73333 { 0, 0, 0, 0 },
73334 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73335 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb1fe0000 }
73336 },
73337/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
73338 {
73339 { 0, 0, 0, 0 },
73340 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73341 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1cb0000 }
73342 },
73343/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
73344 {
73345 { 0, 0, 0, 0 },
73346 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73347 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1eb0000 }
73348 },
73349/* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
73350 {
73351 { 0, 0, 0, 0 },
73352 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73353 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb1fb0000 }
73354 },
73355/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
73356 {
73357 { 0, 0, 0, 0 },
73358 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
73359 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb1cf0000 }
73360 },
73361/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
73362 {
73363 { 0, 0, 0, 0 },
73364 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
73365 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb1ef0000 }
73366 },
73367/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
73368 {
73369 { 0, 0, 0, 0 },
73370 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
73371 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb1ff0000 }
73372 },
73373/* adc.w${X} $Src16RnHI,$Dst16RnHI */
73374 {
73375 { 0, 0, 0, 0 },
73376 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
73377 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb100 }
73378 },
73379/* adc.w${X} $Src16AnHI,$Dst16RnHI */
73380 {
73381 { 0, 0, 0, 0 },
73382 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
73383 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb140 }
73384 },
73385/* adc.w${X} [$Src16An],$Dst16RnHI */
73386 {
73387 { 0, 0, 0, 0 },
73388 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
73389 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb160 }
73390 },
73391/* adc.w${X} $Src16RnHI,$Dst16AnHI */
73392 {
73393 { 0, 0, 0, 0 },
73394 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
73395 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb104 }
73396 },
73397/* adc.w${X} $Src16AnHI,$Dst16AnHI */
73398 {
73399 { 0, 0, 0, 0 },
73400 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
73401 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb144 }
73402 },
73403/* adc.w${X} [$Src16An],$Dst16AnHI */
73404 {
73405 { 0, 0, 0, 0 },
73406 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
73407 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb164 }
73408 },
73409/* adc.w${X} $Src16RnHI,[$Dst16An] */
73410 {
73411 { 0, 0, 0, 0 },
73412 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
73413 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb106 }
73414 },
73415/* adc.w${X} $Src16AnHI,[$Dst16An] */
73416 {
73417 { 0, 0, 0, 0 },
73418 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
73419 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb146 }
73420 },
73421/* adc.w${X} [$Src16An],[$Dst16An] */
73422 {
73423 { 0, 0, 0, 0 },
73424 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73425 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb166 }
73426 },
73427/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
73428 {
73429 { 0, 0, 0, 0 },
73430 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73431 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb10800 }
73432 },
73433/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
73434 {
73435 { 0, 0, 0, 0 },
73436 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73437 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb14800 }
73438 },
73439/* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
73440 {
73441 { 0, 0, 0, 0 },
73442 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73443 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb16800 }
73444 },
73445/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
73446 {
73447 { 0, 0, 0, 0 },
73448 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73449 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb10c0000 }
73450 },
73451/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
73452 {
73453 { 0, 0, 0, 0 },
73454 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73455 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb14c0000 }
73456 },
73457/* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
73458 {
73459 { 0, 0, 0, 0 },
73460 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73461 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb16c0000 }
73462 },
73463/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
73464 {
73465 { 0, 0, 0, 0 },
73466 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73467 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb10a00 }
73468 },
73469/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
73470 {
73471 { 0, 0, 0, 0 },
73472 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73473 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb14a00 }
73474 },
73475/* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
73476 {
73477 { 0, 0, 0, 0 },
73478 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73479 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb16a00 }
73480 },
73481/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
73482 {
73483 { 0, 0, 0, 0 },
73484 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73485 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb10e0000 }
73486 },
73487/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
73488 {
73489 { 0, 0, 0, 0 },
73490 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73491 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb14e0000 }
73492 },
73493/* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
73494 {
73495 { 0, 0, 0, 0 },
73496 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73497 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb16e0000 }
73498 },
73499/* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
73500 {
73501 { 0, 0, 0, 0 },
73502 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73503 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb10b00 }
73504 },
73505/* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
73506 {
73507 { 0, 0, 0, 0 },
73508 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73509 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb14b00 }
73510 },
73511/* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
73512 {
73513 { 0, 0, 0, 0 },
73514 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73515 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb16b00 }
73516 },
73517/* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
73518 {
73519 { 0, 0, 0, 0 },
73520 { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
73521 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb10f0000 }
73522 },
73523/* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
73524 {
73525 { 0, 0, 0, 0 },
73526 { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
73527 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb14f0000 }
73528 },
73529/* adc.w${X} [$Src16An],${Dsp-16-u16} */
73530 {
73531 { 0, 0, 0, 0 },
73532 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
73533 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb16f0000 }
73534 },
73535/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
73536 {
73537 { 0, 0, 0, 0 },
73538 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73539 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb08000 }
73540 },
73541/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
73542 {
73543 { 0, 0, 0, 0 },
73544 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
73545 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0a000 }
73546 },
73547/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
73548 {
73549 { 0, 0, 0, 0 },
73550 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
73551 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb0b000 }
73552 },
73553/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
73554 {
73555 { 0, 0, 0, 0 },
73556 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73557 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb08400 }
73558 },
73559/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
73560 {
73561 { 0, 0, 0, 0 },
73562 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
73563 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb0a400 }
73564 },
73565/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
73566 {
73567 { 0, 0, 0, 0 },
73568 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
73569 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb0b400 }
73570 },
73571/* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
73572 {
73573 { 0, 0, 0, 0 },
73574 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73575 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb08600 }
73576 },
73577/* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
73578 {
73579 { 0, 0, 0, 0 },
73580 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73581 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb0a600 }
73582 },
73583/* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
73584 {
73585 { 0, 0, 0, 0 },
73586 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73587 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb0b600 }
73588 },
73589/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
73590 {
73591 { 0, 0, 0, 0 },
73592 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73593 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb0880000 }
73594 },
73595/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
73596 {
73597 { 0, 0, 0, 0 },
73598 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73599 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0a80000 }
73600 },
73601/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
73602 {
73603 { 0, 0, 0, 0 },
73604 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73605 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0b80000 }
73606 },
73607/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
73608 {
73609 { 0, 0, 0, 0 },
73610 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73611 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb08c0000 }
73612 },
73613/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
73614 {
73615 { 0, 0, 0, 0 },
73616 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73617 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0ac0000 }
73618 },
73619/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
73620 {
73621 { 0, 0, 0, 0 },
73622 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73623 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0bc0000 }
73624 },
73625/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
73626 {
73627 { 0, 0, 0, 0 },
73628 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73629 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb08a0000 }
73630 },
73631/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
73632 {
73633 { 0, 0, 0, 0 },
73634 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73635 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0aa0000 }
73636 },
73637/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
73638 {
73639 { 0, 0, 0, 0 },
73640 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73641 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0ba0000 }
73642 },
73643/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
73644 {
73645 { 0, 0, 0, 0 },
73646 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73647 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb08e0000 }
73648 },
73649/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
73650 {
73651 { 0, 0, 0, 0 },
73652 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73653 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0ae0000 }
73654 },
73655/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
73656 {
73657 { 0, 0, 0, 0 },
73658 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73659 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0be0000 }
73660 },
73661/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
73662 {
73663 { 0, 0, 0, 0 },
73664 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73665 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb08b0000 }
73666 },
73667/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
73668 {
73669 { 0, 0, 0, 0 },
73670 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73671 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0ab0000 }
73672 },
73673/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
73674 {
73675 { 0, 0, 0, 0 },
73676 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73677 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0bb0000 }
73678 },
73679/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
73680 {
73681 { 0, 0, 0, 0 },
73682 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
73683 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb08f0000 }
73684 },
73685/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
73686 {
73687 { 0, 0, 0, 0 },
73688 { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73689 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb0af0000 }
73690 },
73691/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
73692 {
73693 { 0, 0, 0, 0 },
73694 { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73695 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb0bf0000 }
73696 },
73697/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
73698 {
73699 { 0, 0, 0, 0 },
73700 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73701 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb0c00000 }
73702 },
73703/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
73704 {
73705 { 0, 0, 0, 0 },
73706 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
73707 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0e00000 }
73708 },
73709/* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
73710 {
73711 { 0, 0, 0, 0 },
73712 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
73713 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb0f00000 }
73714 },
73715/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
73716 {
73717 { 0, 0, 0, 0 },
73718 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73719 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb0c40000 }
73720 },
73721/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
73722 {
73723 { 0, 0, 0, 0 },
73724 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
73725 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb0e40000 }
73726 },
73727/* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
73728 {
73729 { 0, 0, 0, 0 },
73730 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
73731 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb0f40000 }
73732 },
73733/* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
73734 {
73735 { 0, 0, 0, 0 },
73736 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73737 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb0c60000 }
73738 },
73739/* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
73740 {
73741 { 0, 0, 0, 0 },
73742 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73743 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb0e60000 }
73744 },
73745/* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
73746 {
73747 { 0, 0, 0, 0 },
73748 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
73749 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb0f60000 }
73750 },
73751/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
73752 {
73753 { 0, 0, 0, 0 },
73754 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73755 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb0c80000 }
73756 },
73757/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
73758 {
73759 { 0, 0, 0, 0 },
73760 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73761 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb0e80000 }
73762 },
73763/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
73764 {
73765 { 0, 0, 0, 0 },
73766 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73767 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb0f80000 }
73768 },
73769/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
73770 {
73771 { 0, 0, 0, 0 },
73772 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73773 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb0cc0000 }
73774 },
73775/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
73776 {
73777 { 0, 0, 0, 0 },
73778 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73779 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb0ec0000 }
73780 },
73781/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
73782 {
73783 { 0, 0, 0, 0 },
73784 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73785 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb0fc0000 }
73786 },
73787/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
73788 {
73789 { 0, 0, 0, 0 },
73790 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73791 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ca0000 }
73792 },
73793/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
73794 {
73795 { 0, 0, 0, 0 },
73796 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73797 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ea0000 }
73798 },
73799/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
73800 {
73801 { 0, 0, 0, 0 },
73802 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73803 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb0fa0000 }
73804 },
73805/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
73806 {
73807 { 0, 0, 0, 0 },
73808 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73809 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ce0000 }
73810 },
73811/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
73812 {
73813 { 0, 0, 0, 0 },
73814 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73815 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ee0000 }
73816 },
73817/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
73818 {
73819 { 0, 0, 0, 0 },
73820 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73821 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb0fe0000 }
73822 },
73823/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
73824 {
73825 { 0, 0, 0, 0 },
73826 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73827 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0cb0000 }
73828 },
73829/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
73830 {
73831 { 0, 0, 0, 0 },
73832 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73833 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0eb0000 }
73834 },
73835/* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
73836 {
73837 { 0, 0, 0, 0 },
73838 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73839 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb0fb0000 }
73840 },
73841/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
73842 {
73843 { 0, 0, 0, 0 },
73844 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
73845 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb0cf0000 }
73846 },
73847/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
73848 {
73849 { 0, 0, 0, 0 },
73850 { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
73851 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb0ef0000 }
73852 },
73853/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
73854 {
73855 { 0, 0, 0, 0 },
73856 { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
73857 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb0ff0000 }
73858 },
73859/* adc.b${X} $Src16RnQI,$Dst16RnQI */
73860 {
73861 { 0, 0, 0, 0 },
73862 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
73863 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb000 }
73864 },
73865/* adc.b${X} $Src16AnQI,$Dst16RnQI */
73866 {
73867 { 0, 0, 0, 0 },
73868 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
73869 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb040 }
73870 },
73871/* adc.b${X} [$Src16An],$Dst16RnQI */
73872 {
73873 { 0, 0, 0, 0 },
73874 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73875 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb060 }
73876 },
73877/* adc.b${X} $Src16RnQI,$Dst16AnQI */
73878 {
73879 { 0, 0, 0, 0 },
73880 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
73881 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb004 }
73882 },
73883/* adc.b${X} $Src16AnQI,$Dst16AnQI */
73884 {
73885 { 0, 0, 0, 0 },
73886 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
73887 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb044 }
73888 },
73889/* adc.b${X} [$Src16An],$Dst16AnQI */
73890 {
73891 { 0, 0, 0, 0 },
73892 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73893 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb064 }
73894 },
73895/* adc.b${X} $Src16RnQI,[$Dst16An] */
73896 {
73897 { 0, 0, 0, 0 },
73898 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
73899 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb006 }
73900 },
73901/* adc.b${X} $Src16AnQI,[$Dst16An] */
73902 {
73903 { 0, 0, 0, 0 },
73904 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
73905 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb046 }
73906 },
73907/* adc.b${X} [$Src16An],[$Dst16An] */
73908 {
73909 { 0, 0, 0, 0 },
73910 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73911 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb066 }
73912 },
73913/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
73914 {
73915 { 0, 0, 0, 0 },
73916 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73917 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb00800 }
73918 },
73919/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
73920 {
73921 { 0, 0, 0, 0 },
73922 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73923 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb04800 }
73924 },
73925/* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
73926 {
73927 { 0, 0, 0, 0 },
73928 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73929 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb06800 }
73930 },
73931/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
73932 {
73933 { 0, 0, 0, 0 },
73934 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73935 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb00c0000 }
73936 },
73937/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
73938 {
73939 { 0, 0, 0, 0 },
73940 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73941 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb04c0000 }
73942 },
73943/* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
73944 {
73945 { 0, 0, 0, 0 },
73946 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73947 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb06c0000 }
73948 },
73949/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
73950 {
73951 { 0, 0, 0, 0 },
73952 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73953 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb00a00 }
73954 },
73955/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
73956 {
73957 { 0, 0, 0, 0 },
73958 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73959 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb04a00 }
73960 },
73961/* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
73962 {
73963 { 0, 0, 0, 0 },
73964 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73965 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb06a00 }
73966 },
73967/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
73968 {
73969 { 0, 0, 0, 0 },
73970 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73971 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb00e0000 }
73972 },
73973/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
73974 {
73975 { 0, 0, 0, 0 },
73976 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73977 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb04e0000 }
73978 },
73979/* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
73980 {
73981 { 0, 0, 0, 0 },
73982 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73983 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb06e0000 }
73984 },
73985/* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
73986 {
73987 { 0, 0, 0, 0 },
73988 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73989 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb00b00 }
73990 },
73991/* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
73992 {
73993 { 0, 0, 0, 0 },
73994 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73995 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb04b00 }
73996 },
73997/* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
73998 {
73999 { 0, 0, 0, 0 },
74000 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74001 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb06b00 }
74002 },
74003/* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
74004 {
74005 { 0, 0, 0, 0 },
74006 { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
74007 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb00f0000 }
74008 },
74009/* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
74010 {
74011 { 0, 0, 0, 0 },
74012 { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
74013 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb04f0000 }
74014 },
74015/* adc.b${X} [$Src16An],${Dsp-16-u16} */
74016 {
74017 { 0, 0, 0, 0 },
74018 { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
74019 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb06f0000 }
74020 },
74021/* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
74022 {
74023 { 0, 0, 0, 0 },
74024 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
74025 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892e00 }
74026 },
74027/* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
74028 {
74029 { 0, 0, 0, 0 },
74030 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
74031 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181ae00 }
74032 },
74033/* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
74034 {
74035 { 0, 0, 0, 0 },
74036 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
74037 & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812e00 }
74038 },
74039/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
74040 {
74041 { 0, 0, 0, 0 },
74042 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
74043 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832e00 }
74044 },
74045/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
74046 {
74047 { 0, 0, 0, 0 },
74048 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74049 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ae00 }
74050 },
74051/* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
74052 {
74053 { 0, 0, 0, 0 },
74054 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74055 & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ee00 }
74056 },
74057/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
74058 {
74059 { 0, 0, 0, 0 },
74060 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
74061 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852e00 }
74062 },
74063/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
74064 {
74065 { 0, 0, 0, 0 },
74066 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74067 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ae00 }
74068 },
74069/* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
74070 {
74071 { 0, 0, 0, 0 },
74072 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74073 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ee00 }
74074 },
74075/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
74076 {
74077 { 0, 0, 0, 0 },
74078 { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
74079 & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ee00 }
74080 },
74081/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
74082 {
74083 { 0, 0, 0, 0 },
74084 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
74085 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872e00 }
74086 },
74087/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
74088 {
74089 { 0, 0, 0, 0 },
74090 { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
74091 & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187ae00 }
74092 },
74093/* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
74094 {
74095 { 0, 0, 0, 0 },
74096 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
74097 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882e00 }
74098 },
74099/* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
74100 {
74101 { 0, 0, 0, 0 },
74102 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
74103 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180ae00 }
74104 },
74105/* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
74106 {
74107 { 0, 0, 0, 0 },
74108 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
74109 & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802e00 }
74110 },
74111/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
74112 {
74113 { 0, 0, 0, 0 },
74114 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
74115 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822e00 }
74116 },
74117/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
74118 {
74119 { 0, 0, 0, 0 },
74120 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74121 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ae00 }
74122 },
74123/* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
74124 {
74125 { 0, 0, 0, 0 },
74126 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74127 & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ee00 }
74128 },
74129/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
74130 {
74131 { 0, 0, 0, 0 },
74132 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
74133 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842e00 }
74134 },
74135/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
74136 {
74137 { 0, 0, 0, 0 },
74138 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74139 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ae00 }
74140 },
74141/* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
74142 {
74143 { 0, 0, 0, 0 },
74144 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74145 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ee00 }
74146 },
74147/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
74148 {
74149 { 0, 0, 0, 0 },
74150 { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
74151 & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ee00 }
74152 },
74153/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
74154 {
74155 { 0, 0, 0, 0 },
74156 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
74157 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862e00 }
74158 },
74159/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
74160 {
74161 { 0, 0, 0, 0 },
74162 { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
74163 & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186ae00 }
74164 },
74165/* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
74166 {
74167 { 0, 0, 0, 0 },
74168 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
74169 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77600000 }
74170 },
74171/* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
74172 {
74173 { 0, 0, 0, 0 },
74174 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
74175 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77640000 }
74176 },
74177/* adc.w${X} #${Imm-16-HI},[$Dst16An] */
74178 {
74179 { 0, 0, 0, 0 },
74180 { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
74181 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77660000 }
74182 },
74183/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
74184 {
74185 { 0, 0, 0, 0 },
74186 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
74187 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77680000 }
74188 },
74189/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
74190 {
74191 { 0, 0, 0, 0 },
74192 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
74193 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x776a0000 }
74194 },
74195/* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
74196 {
74197 { 0, 0, 0, 0 },
74198 { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74199 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x776b0000 }
74200 },
74201/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
74202 {
74203 { 0, 0, 0, 0 },
74204 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
74205 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x776c0000 }
74206 },
74207/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
74208 {
74209 { 0, 0, 0, 0 },
74210 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
74211 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x776e0000 }
74212 },
74213/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
74214 {
74215 { 0, 0, 0, 0 },
74216 { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
74217 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x776f0000 }
74218 },
74219/* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
74220 {
74221 { 0, 0, 0, 0 },
74222 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
74223 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x766000 }
74224 },
74225/* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
74226 {
74227 { 0, 0, 0, 0 },
74228 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
74229 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x766400 }
74230 },
74231/* adc.b${X} #${Imm-16-QI},[$Dst16An] */
74232 {
74233 { 0, 0, 0, 0 },
74234 { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
74235 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x766600 }
74236 },
74237/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
74238 {
74239 { 0, 0, 0, 0 },
74240 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
74241 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76680000 }
74242 },
74243/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
74244 {
74245 { 0, 0, 0, 0 },
74246 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
74247 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x766a0000 }
74248 },
74249/* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
74250 {
74251 { 0, 0, 0, 0 },
74252 { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74253 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x766b0000 }
74254 },
74255/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
74256 {
74257 { 0, 0, 0, 0 },
74258 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
74259 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x766c0000 }
74260 },
74261/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
74262 {
74263 { 0, 0, 0, 0 },
74264 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
74265 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x766e0000 }
74266 },
74267/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
74268 {
74269 { 0, 0, 0, 0 },
74270 { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
74271 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x766f0000 }
74272 },
74273/* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
74274 {
74275 { 0, 0, 0, 0 },
74276 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
74277 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x27000000 }
74278 },
74279/* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
74280 {
74281 { 0, 0, 0, 0 },
74282 { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
74283 & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x37000000 }
74284 },
74285/* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
74286 {
74287 { 0, 0, 0, 0 },
74288 { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
74289 & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x17000000 }
74290 },
74291/* add.w${S} #${Imm-8-HI},r0 */
74292 {
74293 { 0, 0, 0, 0 },
74294 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
74295 & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x70000 }
74296 },
74297/* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
74298 {
74299 { 0, 0, 0, 0 },
74300 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
74301 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x260000 }
74302 },
74303/* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
74304 {
74305 { 0, 0, 0, 0 },
74306 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
74307 & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x360000 }
74308 },
74309/* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
74310 {
74311 { 0, 0, 0, 0 },
74312 { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
74313 & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x16000000 }
74314 },
74315/* add.b${S} #${Imm-8-QI},r0l */
74316 {
74317 { 0, 0, 0, 0 },
74318 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
74319 & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x600 }
74320 },
74321/* add.l${S} #${Imm1-S},a0 */
74322 {
74323 { 0, 0, 0, 0 },
74324 { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '0', 0 } },
74325 & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI, { 0x8c }
74326 },
74327/* add.l${S} #${Imm1-S},a1 */
74328 {
74329 { 0, 0, 0, 0 },
74330 { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '1', 0 } },
74331 & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI, { 0x8d }
74332 },
74333/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74334 {
74335 { 0, 0, 0, 0 },
74336 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74337 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990200 }
74338 },
74339/* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
74340 {
74341 { 0, 0, 0, 0 },
74342 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74343 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992200 }
74344 },
74345/* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
74346 {
74347 { 0, 0, 0, 0 },
74348 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74349 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993200 }
74350 },
74351/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74352 {
74353 { 0, 0, 0, 0 },
74354 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74355 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918200 }
74356 },
74357/* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
74358 {
74359 { 0, 0, 0, 0 },
74360 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74361 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a200 }
74362 },
74363/* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
74364 {
74365 { 0, 0, 0, 0 },
74366 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74367 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b200 }
74368 },
74369/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74370 {
74371 { 0, 0, 0, 0 },
74372 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74373 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910200 }
74374 },
74375/* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
74376 {
74377 { 0, 0, 0, 0 },
74378 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74379 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912200 }
74380 },
74381/* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
74382 {
74383 { 0, 0, 0, 0 },
74384 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74385 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913200 }
74386 },
74387/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74388 {
74389 { 0, 0, 0, 0 },
74390 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74391 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93020000 }
74392 },
74393/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74394 {
74395 { 0, 0, 0, 0 },
74396 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74397 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93220000 }
74398 },
74399/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74400 {
74401 { 0, 0, 0, 0 },
74402 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74403 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93320000 }
74404 },
74405/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74406 {
74407 { 0, 0, 0, 0 },
74408 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74409 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95020000 }
74410 },
74411/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74412 {
74413 { 0, 0, 0, 0 },
74414 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74415 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95220000 }
74416 },
74417/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74418 {
74419 { 0, 0, 0, 0 },
74420 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74421 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95320000 }
74422 },
74423/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74424 {
74425 { 0, 0, 0, 0 },
74426 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74427 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97020000 }
74428 },
74429/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74430 {
74431 { 0, 0, 0, 0 },
74432 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74433 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97220000 }
74434 },
74435/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74436 {
74437 { 0, 0, 0, 0 },
74438 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74439 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97320000 }
74440 },
74441/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
74442 {
74443 { 0, 0, 0, 0 },
74444 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74445 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93820000 }
74446 },
74447/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
74448 {
74449 { 0, 0, 0, 0 },
74450 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74451 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a20000 }
74452 },
74453/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
74454 {
74455 { 0, 0, 0, 0 },
74456 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74457 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b20000 }
74458 },
74459/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
74460 {
74461 { 0, 0, 0, 0 },
74462 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74463 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95820000 }
74464 },
74465/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
74466 {
74467 { 0, 0, 0, 0 },
74468 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74469 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a20000 }
74470 },
74471/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
74472 {
74473 { 0, 0, 0, 0 },
74474 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74475 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b20000 }
74476 },
74477/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
74478 {
74479 { 0, 0, 0, 0 },
74480 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74481 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c20000 }
74482 },
74483/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
74484 {
74485 { 0, 0, 0, 0 },
74486 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74487 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e20000 }
74488 },
74489/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
74490 {
74491 { 0, 0, 0, 0 },
74492 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74493 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f20000 }
74494 },
74495/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
74496 {
74497 { 0, 0, 0, 0 },
74498 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74499 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c20000 }
74500 },
74501/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
74502 {
74503 { 0, 0, 0, 0 },
74504 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74505 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e20000 }
74506 },
74507/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
74508 {
74509 { 0, 0, 0, 0 },
74510 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74511 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f20000 }
74512 },
74513/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
74514 {
74515 { 0, 0, 0, 0 },
74516 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
74517 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c20000 }
74518 },
74519/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
74520 {
74521 { 0, 0, 0, 0 },
74522 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
74523 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e20000 }
74524 },
74525/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
74526 {
74527 { 0, 0, 0, 0 },
74528 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
74529 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f20000 }
74530 },
74531/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
74532 {
74533 { 0, 0, 0, 0 },
74534 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
74535 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97820000 }
74536 },
74537/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
74538 {
74539 { 0, 0, 0, 0 },
74540 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
74541 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a20000 }
74542 },
74543/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
74544 {
74545 { 0, 0, 0, 0 },
74546 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
74547 & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b20000 }
74548 },
74549/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74550 {
74551 { 0, 0, 0, 0 },
74552 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74553 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9020000 }
74554 },
74555/* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
74556 {
74557 { 0, 0, 0, 0 },
74558 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74559 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9220000 }
74560 },
74561/* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
74562 {
74563 { 0, 0, 0, 0 },
74564 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74565 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9320000 }
74566 },
74567/* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
74568 {
74569 { 0, 0, 0, 0 },
74570 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74571 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9320000 }
74572 },
74573/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74574 {
74575 { 0, 0, 0, 0 },
74576 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74577 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1820000 }
74578 },
74579/* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
74580 {
74581 { 0, 0, 0, 0 },
74582 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74583 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a20000 }
74584 },
74585/* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
74586 {
74587 { 0, 0, 0, 0 },
74588 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74589 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b20000 }
74590 },
74591/* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
74592 {
74593 { 0, 0, 0, 0 },
74594 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74595 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b20000 }
74596 },
74597/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74598 {
74599 { 0, 0, 0, 0 },
74600 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74601 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1020000 }
74602 },
74603/* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
74604 {
74605 { 0, 0, 0, 0 },
74606 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74607 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1220000 }
74608 },
74609/* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
74610 {
74611 { 0, 0, 0, 0 },
74612 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74613 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1320000 }
74614 },
74615/* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
74616 {
74617 { 0, 0, 0, 0 },
74618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74619 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1320000 }
74620 },
74621/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74622 {
74623 { 0, 0, 0, 0 },
74624 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74625 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3020000 }
74626 },
74627/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74628 {
74629 { 0, 0, 0, 0 },
74630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74631 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3220000 }
74632 },
74633/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74634 {
74635 { 0, 0, 0, 0 },
74636 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74637 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3320000 }
74638 },
74639/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
74640 {
74641 { 0, 0, 0, 0 },
74642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74643 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3320000 }
74644 },
74645/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74646 {
74647 { 0, 0, 0, 0 },
74648 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74649 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5020000 }
74650 },
74651/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74652 {
74653 { 0, 0, 0, 0 },
74654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74655 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5220000 }
74656 },
74657/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74658 {
74659 { 0, 0, 0, 0 },
74660 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74661 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5320000 }
74662 },
74663/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
74664 {
74665 { 0, 0, 0, 0 },
74666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74667 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5320000 }
74668 },
74669/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74670 {
74671 { 0, 0, 0, 0 },
74672 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74673 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7020000 }
74674 },
74675/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74676 {
74677 { 0, 0, 0, 0 },
74678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74679 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7220000 }
74680 },
74681/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74682 {
74683 { 0, 0, 0, 0 },
74684 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74685 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7320000 }
74686 },
74687/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
74688 {
74689 { 0, 0, 0, 0 },
74690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74691 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7320000 }
74692 },
74693/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
74694 {
74695 { 0, 0, 0, 0 },
74696 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74697 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3820000 }
74698 },
74699/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
74700 {
74701 { 0, 0, 0, 0 },
74702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74703 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a20000 }
74704 },
74705/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
74706 {
74707 { 0, 0, 0, 0 },
74708 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74709 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b20000 }
74710 },
74711/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
74712 {
74713 { 0, 0, 0, 0 },
74714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74715 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b20000 }
74716 },
74717/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
74718 {
74719 { 0, 0, 0, 0 },
74720 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74721 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5820000 }
74722 },
74723/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
74724 {
74725 { 0, 0, 0, 0 },
74726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74727 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a20000 }
74728 },
74729/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
74730 {
74731 { 0, 0, 0, 0 },
74732 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74733 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b20000 }
74734 },
74735/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
74736 {
74737 { 0, 0, 0, 0 },
74738 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74739 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b20000 }
74740 },
74741/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
74742 {
74743 { 0, 0, 0, 0 },
74744 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74745 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c20000 }
74746 },
74747/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
74748 {
74749 { 0, 0, 0, 0 },
74750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74751 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e20000 }
74752 },
74753/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
74754 {
74755 { 0, 0, 0, 0 },
74756 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74757 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f20000 }
74758 },
74759/* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
74760 {
74761 { 0, 0, 0, 0 },
74762 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74763 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f20000 }
74764 },
74765/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
74766 {
74767 { 0, 0, 0, 0 },
74768 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74769 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c20000 }
74770 },
74771/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
74772 {
74773 { 0, 0, 0, 0 },
74774 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74775 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e20000 }
74776 },
74777/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
74778 {
74779 { 0, 0, 0, 0 },
74780 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74781 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f20000 }
74782 },
74783/* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
74784 {
74785 { 0, 0, 0, 0 },
74786 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74787 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f20000 }
74788 },
74789/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
74790 {
74791 { 0, 0, 0, 0 },
74792 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
74793 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c20000 }
74794 },
74795/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
74796 {
74797 { 0, 0, 0, 0 },
74798 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
74799 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e20000 }
74800 },
74801/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
74802 {
74803 { 0, 0, 0, 0 },
74804 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
74805 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f20000 }
74806 },
74807/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
74808 {
74809 { 0, 0, 0, 0 },
74810 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
74811 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f20000 }
74812 },
74813/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
74814 {
74815 { 0, 0, 0, 0 },
74816 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
74817 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7820000 }
74818 },
74819/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
74820 {
74821 { 0, 0, 0, 0 },
74822 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
74823 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a20000 }
74824 },
74825/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
74826 {
74827 { 0, 0, 0, 0 },
74828 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
74829 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b20000 }
74830 },
74831/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
74832 {
74833 { 0, 0, 0, 0 },
74834 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
74835 & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b20000 }
74836 },
74837/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74838 {
74839 { 0, 0, 0, 0 },
74840 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74841 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9020000 }
74842 },
74843/* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
74844 {
74845 { 0, 0, 0, 0 },
74846 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74847 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9220000 }
74848 },
74849/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74850 {
74851 { 0, 0, 0, 0 },
74852 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74853 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1820000 }
74854 },
74855/* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
74856 {
74857 { 0, 0, 0, 0 },
74858 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74859 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a20000 }
74860 },
74861/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74862 {
74863 { 0, 0, 0, 0 },
74864 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74865 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1020000 }
74866 },
74867/* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
74868 {
74869 { 0, 0, 0, 0 },
74870 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74871 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1220000 }
74872 },
74873/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
74874 {
74875 { 0, 0, 0, 0 },
74876 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74877 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3020000 }
74878 },
74879/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
74880 {
74881 { 0, 0, 0, 0 },
74882 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74883 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3220000 }
74884 },
74885/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
74886 {
74887 { 0, 0, 0, 0 },
74888 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74889 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5020000 }
74890 },
74891/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
74892 {
74893 { 0, 0, 0, 0 },
74894 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74895 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5220000 }
74896 },
74897/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
74898 {
74899 { 0, 0, 0, 0 },
74900 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74901 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7020000 }
74902 },
74903/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
74904 {
74905 { 0, 0, 0, 0 },
74906 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74907 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7220000 }
74908 },
74909/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
74910 {
74911 { 0, 0, 0, 0 },
74912 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
74913 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3820000 }
74914 },
74915/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
74916 {
74917 { 0, 0, 0, 0 },
74918 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
74919 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a20000 }
74920 },
74921/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
74922 {
74923 { 0, 0, 0, 0 },
74924 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
74925 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5820000 }
74926 },
74927/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
74928 {
74929 { 0, 0, 0, 0 },
74930 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
74931 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a20000 }
74932 },
74933/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
74934 {
74935 { 0, 0, 0, 0 },
74936 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
74937 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c20000 }
74938 },
74939/* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
74940 {
74941 { 0, 0, 0, 0 },
74942 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
74943 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e20000 }
74944 },
74945/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
74946 {
74947 { 0, 0, 0, 0 },
74948 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
74949 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c20000 }
74950 },
74951/* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
74952 {
74953 { 0, 0, 0, 0 },
74954 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
74955 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e20000 }
74956 },
74957/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
74958 {
74959 { 0, 0, 0, 0 },
74960 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
74961 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c20000 }
74962 },
74963/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
74964 {
74965 { 0, 0, 0, 0 },
74966 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
74967 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e20000 }
74968 },
74969/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
74970 {
74971 { 0, 0, 0, 0 },
74972 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
74973 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7820000 }
74974 },
74975/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
74976 {
74977 { 0, 0, 0, 0 },
74978 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
74979 & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a20000 }
74980 },
74981/* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
74982 {
74983 { 0, 0, 0, 0 },
74984 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74985 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc902 }
74986 },
74987/* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
74988 {
74989 { 0, 0, 0, 0 },
74990 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74991 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8922 }
74992 },
74993/* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74994 {
74995 { 0, 0, 0, 0 },
74996 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74997 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8902 }
74998 },
74999/* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
75000 {
75001 { 0, 0, 0, 0 },
75002 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
75003 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc182 }
75004 },
75005/* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
75006 {
75007 { 0, 0, 0, 0 },
75008 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
75009 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a2 }
75010 },
75011/* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
75012 {
75013 { 0, 0, 0, 0 },
75014 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
75015 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8182 }
75016 },
75017/* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
75018 {
75019 { 0, 0, 0, 0 },
75020 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75021 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc102 }
75022 },
75023/* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
75024 {
75025 { 0, 0, 0, 0 },
75026 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75027 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8122 }
75028 },
75029/* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75030 {
75031 { 0, 0, 0, 0 },
75032 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75033 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8102 }
75034 },
75035/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75036 {
75037 { 0, 0, 0, 0 },
75038 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75039 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30200 }
75040 },
75041/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75042 {
75043 { 0, 0, 0, 0 },
75044 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75045 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832200 }
75046 },
75047/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
75048 {
75049 { 0, 0, 0, 0 },
75050 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75051 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830200 }
75052 },
75053/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75054 {
75055 { 0, 0, 0, 0 },
75056 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75057 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5020000 }
75058 },
75059/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75060 {
75061 { 0, 0, 0, 0 },
75062 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75063 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85220000 }
75064 },
75065/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
75066 {
75067 { 0, 0, 0, 0 },
75068 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75069 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85020000 }
75070 },
75071/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75072 {
75073 { 0, 0, 0, 0 },
75074 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75075 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7020000 }
75076 },
75077/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75078 {
75079 { 0, 0, 0, 0 },
75080 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75081 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87220000 }
75082 },
75083/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
75084 {
75085 { 0, 0, 0, 0 },
75086 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75087 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87020000 }
75088 },
75089/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
75090 {
75091 { 0, 0, 0, 0 },
75092 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75093 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38200 }
75094 },
75095/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
75096 {
75097 { 0, 0, 0, 0 },
75098 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75099 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a200 }
75100 },
75101/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
75102 {
75103 { 0, 0, 0, 0 },
75104 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75105 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838200 }
75106 },
75107/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
75108 {
75109 { 0, 0, 0, 0 },
75110 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75111 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5820000 }
75112 },
75113/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
75114 {
75115 { 0, 0, 0, 0 },
75116 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75117 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a20000 }
75118 },
75119/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
75120 {
75121 { 0, 0, 0, 0 },
75122 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75123 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85820000 }
75124 },
75125/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
75126 {
75127 { 0, 0, 0, 0 },
75128 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75129 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c200 }
75130 },
75131/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
75132 {
75133 { 0, 0, 0, 0 },
75134 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75135 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e200 }
75136 },
75137/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
75138 {
75139 { 0, 0, 0, 0 },
75140 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75141 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c200 }
75142 },
75143/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
75144 {
75145 { 0, 0, 0, 0 },
75146 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75147 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c20000 }
75148 },
75149/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
75150 {
75151 { 0, 0, 0, 0 },
75152 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75153 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e20000 }
75154 },
75155/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
75156 {
75157 { 0, 0, 0, 0 },
75158 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75159 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c20000 }
75160 },
75161/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
75162 {
75163 { 0, 0, 0, 0 },
75164 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
75165 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c20000 }
75166 },
75167/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
75168 {
75169 { 0, 0, 0, 0 },
75170 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
75171 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e20000 }
75172 },
75173/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
75174 {
75175 { 0, 0, 0, 0 },
75176 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
75177 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c20000 }
75178 },
75179/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
75180 {
75181 { 0, 0, 0, 0 },
75182 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
75183 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7820000 }
75184 },
75185/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
75186 {
75187 { 0, 0, 0, 0 },
75188 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
75189 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a20000 }
75190 },
75191/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
75192 {
75193 { 0, 0, 0, 0 },
75194 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
75195 & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87820000 }
75196 },
75197/* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
75198 {
75199 { 0, 0, 0, 0 },
75200 { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
5348b81e 75201 & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x20 }
49f58d10
JB		 75202 },
75203/* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
75204 {
75205 { 0, 0, 0, 0 },
75206 { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 75207 & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2100 }
49f58d10
JB		 75208 },
75209/* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
75210 {
75211 { 0, 0, 0, 0 },
75212 { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
5348b81e 75213 & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2200 }
49f58d10
JB		 75214 },
75215/* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
75216 {
75217 { 0, 0, 0, 0 },
75218 { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
5348b81e 75219 & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x230000 }
49f58d10
JB		 75220 },
75221/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75222 {
75223 { 0, 0, 0, 0 },
75224 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75225 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990800 }
75226 },
75227/* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
75228 {
75229 { 0, 0, 0, 0 },
75230 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75231 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992800 }
75232 },
75233/* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
75234 {
75235 { 0, 0, 0, 0 },
75236 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75237 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993800 }
75238 },
75239/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75240 {
75241 { 0, 0, 0, 0 },
75242 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75243 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918800 }
75244 },
75245/* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
75246 {
75247 { 0, 0, 0, 0 },
75248 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75249 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a800 }
75250 },
75251/* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
75252 {
75253 { 0, 0, 0, 0 },
75254 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75255 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b800 }
75256 },
75257/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75258 {
75259 { 0, 0, 0, 0 },
75260 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75261 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910800 }
75262 },
75263/* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
75264 {
75265 { 0, 0, 0, 0 },
75266 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75267 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912800 }
75268 },
75269/* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
75270 {
75271 { 0, 0, 0, 0 },
75272 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75273 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913800 }
75274 },
75275/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75276 {
75277 { 0, 0, 0, 0 },
75278 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75279 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93080000 }
75280 },
75281/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75282 {
75283 { 0, 0, 0, 0 },
75284 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75285 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93280000 }
75286 },
75287/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75288 {
75289 { 0, 0, 0, 0 },
75290 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75291 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93380000 }
75292 },
75293/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75294 {
75295 { 0, 0, 0, 0 },
75296 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75297 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95080000 }
75298 },
75299/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75300 {
75301 { 0, 0, 0, 0 },
75302 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75303 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95280000 }
75304 },
75305/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75306 {
75307 { 0, 0, 0, 0 },
75308 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75309 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95380000 }
75310 },
75311/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75312 {
75313 { 0, 0, 0, 0 },
75314 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75315 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97080000 }
75316 },
75317/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75318 {
75319 { 0, 0, 0, 0 },
75320 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75321 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97280000 }
75322 },
75323/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75324 {
75325 { 0, 0, 0, 0 },
75326 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75327 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97380000 }
75328 },
75329/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
75330 {
75331 { 0, 0, 0, 0 },
75332 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75333 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93880000 }
75334 },
75335/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
75336 {
75337 { 0, 0, 0, 0 },
75338 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75339 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a80000 }
75340 },
75341/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
75342 {
75343 { 0, 0, 0, 0 },
75344 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75345 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b80000 }
75346 },
75347/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
75348 {
75349 { 0, 0, 0, 0 },
75350 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75351 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95880000 }
75352 },
75353/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
75354 {
75355 { 0, 0, 0, 0 },
75356 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75357 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a80000 }
75358 },
75359/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
75360 {
75361 { 0, 0, 0, 0 },
75362 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75363 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b80000 }
75364 },
75365/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
75366 {
75367 { 0, 0, 0, 0 },
75368 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75369 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c80000 }
75370 },
75371/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
75372 {
75373 { 0, 0, 0, 0 },
75374 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75375 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e80000 }
75376 },
75377/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
75378 {
75379 { 0, 0, 0, 0 },
75380 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75381 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f80000 }
75382 },
75383/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
75384 {
75385 { 0, 0, 0, 0 },
75386 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75387 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c80000 }
75388 },
75389/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
75390 {
75391 { 0, 0, 0, 0 },
75392 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75393 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e80000 }
75394 },
75395/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
75396 {
75397 { 0, 0, 0, 0 },
75398 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75399 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f80000 }
75400 },
75401/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
75402 {
75403 { 0, 0, 0, 0 },
75404 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
75405 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c80000 }
75406 },
75407/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
75408 {
75409 { 0, 0, 0, 0 },
75410 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75411 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e80000 }
75412 },
75413/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
75414 {
75415 { 0, 0, 0, 0 },
75416 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75417 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f80000 }
75418 },
75419/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
75420 {
75421 { 0, 0, 0, 0 },
75422 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
75423 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97880000 }
75424 },
75425/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
75426 {
75427 { 0, 0, 0, 0 },
75428 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75429 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a80000 }
75430 },
75431/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
75432 {
75433 { 0, 0, 0, 0 },
75434 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75435 & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b80000 }
75436 },
75437/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75438 {
75439 { 0, 0, 0, 0 },
75440 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75441 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9080000 }
75442 },
75443/* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
75444 {
75445 { 0, 0, 0, 0 },
75446 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75447 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9280000 }
75448 },
75449/* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
75450 {
75451 { 0, 0, 0, 0 },
75452 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75453 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9380000 }
75454 },
75455/* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
75456 {
75457 { 0, 0, 0, 0 },
75458 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75459 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9380000 }
75460 },
75461/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75462 {
75463 { 0, 0, 0, 0 },
75464 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75465 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1880000 }
75466 },
75467/* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
75468 {
75469 { 0, 0, 0, 0 },
75470 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75471 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a80000 }
75472 },
75473/* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
75474 {
75475 { 0, 0, 0, 0 },
75476 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75477 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b80000 }
75478 },
75479/* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
75480 {
75481 { 0, 0, 0, 0 },
75482 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75483 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b80000 }
75484 },
75485/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75486 {
75487 { 0, 0, 0, 0 },
75488 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75489 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1080000 }
75490 },
75491/* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
75492 {
75493 { 0, 0, 0, 0 },
75494 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75495 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1280000 }
75496 },
75497/* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
75498 {
75499 { 0, 0, 0, 0 },
75500 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75501 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1380000 }
75502 },
75503/* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
75504 {
75505 { 0, 0, 0, 0 },
75506 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75507 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1380000 }
75508 },
75509/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75510 {
75511 { 0, 0, 0, 0 },
75512 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75513 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3080000 }
75514 },
75515/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75516 {
75517 { 0, 0, 0, 0 },
75518 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75519 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3280000 }
75520 },
75521/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75522 {
75523 { 0, 0, 0, 0 },
75524 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75525 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3380000 }
75526 },
75527/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
75528 {
75529 { 0, 0, 0, 0 },
75530 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75531 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3380000 }
75532 },
75533/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75534 {
75535 { 0, 0, 0, 0 },
75536 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75537 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5080000 }
75538 },
75539/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75540 {
75541 { 0, 0, 0, 0 },
75542 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75543 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5280000 }
75544 },
75545/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75546 {
75547 { 0, 0, 0, 0 },
75548 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75549 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5380000 }
75550 },
75551/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
75552 {
75553 { 0, 0, 0, 0 },
75554 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75555 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5380000 }
75556 },
75557/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75558 {
75559 { 0, 0, 0, 0 },
75560 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75561 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7080000 }
75562 },
75563/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75564 {
75565 { 0, 0, 0, 0 },
75566 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75567 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7280000 }
75568 },
75569/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75570 {
75571 { 0, 0, 0, 0 },
75572 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75573 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7380000 }
75574 },
75575/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
75576 {
75577 { 0, 0, 0, 0 },
75578 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75579 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7380000 }
75580 },
75581/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
75582 {
75583 { 0, 0, 0, 0 },
75584 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75585 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3880000 }
75586 },
75587/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
75588 {
75589 { 0, 0, 0, 0 },
75590 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75591 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a80000 }
75592 },
75593/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
75594 {
75595 { 0, 0, 0, 0 },
75596 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75597 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b80000 }
75598 },
75599/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
75600 {
75601 { 0, 0, 0, 0 },
75602 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75603 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b80000 }
75604 },
75605/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
75606 {
75607 { 0, 0, 0, 0 },
75608 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75609 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5880000 }
75610 },
75611/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
75612 {
75613 { 0, 0, 0, 0 },
75614 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75615 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a80000 }
75616 },
75617/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
75618 {
75619 { 0, 0, 0, 0 },
75620 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75621 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b80000 }
75622 },
75623/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
75624 {
75625 { 0, 0, 0, 0 },
75626 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75627 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b80000 }
75628 },
75629/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
75630 {
75631 { 0, 0, 0, 0 },
75632 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75633 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c80000 }
75634 },
75635/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
75636 {
75637 { 0, 0, 0, 0 },
75638 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75639 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e80000 }
75640 },
75641/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
75642 {
75643 { 0, 0, 0, 0 },
75644 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75645 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f80000 }
75646 },
75647/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
75648 {
75649 { 0, 0, 0, 0 },
75650 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75651 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f80000 }
75652 },
75653/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
75654 {
75655 { 0, 0, 0, 0 },
75656 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75657 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c80000 }
75658 },
75659/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
75660 {
75661 { 0, 0, 0, 0 },
75662 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75663 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e80000 }
75664 },
75665/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
75666 {
75667 { 0, 0, 0, 0 },
75668 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75669 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f80000 }
75670 },
75671/* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
75672 {
75673 { 0, 0, 0, 0 },
75674 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75675 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f80000 }
75676 },
75677/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
75678 {
75679 { 0, 0, 0, 0 },
75680 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
75681 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c80000 }
75682 },
75683/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
75684 {
75685 { 0, 0, 0, 0 },
75686 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
75687 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e80000 }
75688 },
75689/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
75690 {
75691 { 0, 0, 0, 0 },
75692 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
75693 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f80000 }
75694 },
75695/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
75696 {
75697 { 0, 0, 0, 0 },
75698 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
75699 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f80000 }
75700 },
75701/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
75702 {
75703 { 0, 0, 0, 0 },
75704 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
75705 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7880000 }
75706 },
75707/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
75708 {
75709 { 0, 0, 0, 0 },
75710 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
75711 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a80000 }
75712 },
75713/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
75714 {
75715 { 0, 0, 0, 0 },
75716 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
75717 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b80000 }
75718 },
75719/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
75720 {
75721 { 0, 0, 0, 0 },
75722 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
75723 & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b80000 }
75724 },
75725/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75726 {
75727 { 0, 0, 0, 0 },
75728 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75729 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9080000 }
75730 },
75731/* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
75732 {
75733 { 0, 0, 0, 0 },
75734 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75735 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9280000 }
75736 },
75737/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75738 {
75739 { 0, 0, 0, 0 },
75740 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75741 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1880000 }
75742 },
75743/* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
75744 {
75745 { 0, 0, 0, 0 },
75746 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75747 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a80000 }
75748 },
75749/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75750 {
75751 { 0, 0, 0, 0 },
75752 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75753 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1080000 }
75754 },
75755/* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
75756 {
75757 { 0, 0, 0, 0 },
75758 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75759 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1280000 }
75760 },
75761/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
75762 {
75763 { 0, 0, 0, 0 },
75764 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75765 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3080000 }
75766 },
75767/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
75768 {
75769 { 0, 0, 0, 0 },
75770 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75771 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3280000 }
75772 },
75773/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
75774 {
75775 { 0, 0, 0, 0 },
75776 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75777 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5080000 }
75778 },
75779/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
75780 {
75781 { 0, 0, 0, 0 },
75782 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75783 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5280000 }
75784 },
75785/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
75786 {
75787 { 0, 0, 0, 0 },
75788 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75789 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7080000 }
75790 },
75791/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
75792 {
75793 { 0, 0, 0, 0 },
75794 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75795 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7280000 }
75796 },
75797/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
75798 {
75799 { 0, 0, 0, 0 },
75800 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
75801 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3880000 }
75802 },
75803/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
75804 {
75805 { 0, 0, 0, 0 },
75806 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
75807 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a80000 }
75808 },
75809/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
75810 {
75811 { 0, 0, 0, 0 },
75812 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
75813 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5880000 }
75814 },
75815/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
75816 {
75817 { 0, 0, 0, 0 },
75818 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
75819 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a80000 }
75820 },
75821/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
75822 {
75823 { 0, 0, 0, 0 },
75824 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
75825 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c80000 }
75826 },
75827/* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
75828 {
75829 { 0, 0, 0, 0 },
75830 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
75831 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e80000 }
75832 },
75833/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
75834 {
75835 { 0, 0, 0, 0 },
75836 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
75837 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c80000 }
75838 },
75839/* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
75840 {
75841 { 0, 0, 0, 0 },
75842 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
75843 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e80000 }
75844 },
75845/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
75846 {
75847 { 0, 0, 0, 0 },
75848 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
75849 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c80000 }
75850 },
75851/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
75852 {
75853 { 0, 0, 0, 0 },
75854 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
75855 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e80000 }
75856 },
75857/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
75858 {
75859 { 0, 0, 0, 0 },
75860 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
75861 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7880000 }
75862 },
75863/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
75864 {
75865 { 0, 0, 0, 0 },
75866 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
75867 & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a80000 }
75868 },
75869/* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
75870 {
75871 { 0, 0, 0, 0 },
75872 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75873 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc908 }
75874 },
75875/* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
75876 {
75877 { 0, 0, 0, 0 },
75878 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75879 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8928 }
75880 },
75881/* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75882 {
75883 { 0, 0, 0, 0 },
75884 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75885 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8908 }
75886 },
75887/* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
75888 {
75889 { 0, 0, 0, 0 },
75890 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75891 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc188 }
75892 },
75893/* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
75894 {
75895 { 0, 0, 0, 0 },
75896 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75897 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a8 }
75898 },
75899/* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75900 {
75901 { 0, 0, 0, 0 },
75902 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75903 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8188 }
75904 },
75905/* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
75906 {
75907 { 0, 0, 0, 0 },
75908 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75909 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc108 }
75910 },
75911/* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
75912 {
75913 { 0, 0, 0, 0 },
75914 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75915 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8128 }
75916 },
75917/* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75918 {
75919 { 0, 0, 0, 0 },
75920 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75921 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8108 }
75922 },
75923/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75924 {
75925 { 0, 0, 0, 0 },
75926 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75927 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30800 }
75928 },
75929/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75930 {
75931 { 0, 0, 0, 0 },
75932 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75933 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832800 }
75934 },
75935/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
75936 {
75937 { 0, 0, 0, 0 },
75938 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75939 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830800 }
75940 },
75941/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75942 {
75943 { 0, 0, 0, 0 },
75944 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75945 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5080000 }
75946 },
75947/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75948 {
75949 { 0, 0, 0, 0 },
75950 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75951 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85280000 }
75952 },
75953/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
75954 {
75955 { 0, 0, 0, 0 },
75956 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75957 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85080000 }
75958 },
75959/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75960 {
75961 { 0, 0, 0, 0 },
75962 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75963 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7080000 }
75964 },
75965/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75966 {
75967 { 0, 0, 0, 0 },
75968 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75969 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87280000 }
75970 },
75971/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
75972 {
75973 { 0, 0, 0, 0 },
75974 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75975 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87080000 }
75976 },
75977/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
75978 {
75979 { 0, 0, 0, 0 },
75980 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75981 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38800 }
75982 },
75983/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
75984 {
75985 { 0, 0, 0, 0 },
75986 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75987 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a800 }
75988 },
75989/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
75990 {
75991 { 0, 0, 0, 0 },
75992 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75993 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838800 }
75994 },
75995/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
75996 {
75997 { 0, 0, 0, 0 },
75998 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75999 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5880000 }
76000 },
76001/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
76002 {
76003 { 0, 0, 0, 0 },
76004 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76005 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a80000 }
76006 },
76007/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
76008 {
76009 { 0, 0, 0, 0 },
76010 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76011 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85880000 }
76012 },
76013/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
76014 {
76015 { 0, 0, 0, 0 },
76016 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76017 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c800 }
76018 },
76019/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
76020 {
76021 { 0, 0, 0, 0 },
76022 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76023 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e800 }
76024 },
76025/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
76026 {
76027 { 0, 0, 0, 0 },
76028 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76029 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c800 }
76030 },
76031/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
76032 {
76033 { 0, 0, 0, 0 },
76034 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76035 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c80000 }
76036 },
76037/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
76038 {
76039 { 0, 0, 0, 0 },
76040 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76041 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e80000 }
76042 },
76043/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
76044 {
76045 { 0, 0, 0, 0 },
76046 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76047 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c80000 }
76048 },
76049/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
76050 {
76051 { 0, 0, 0, 0 },
76052 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
76053 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c80000 }
76054 },
76055/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
76056 {
76057 { 0, 0, 0, 0 },
76058 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
76059 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e80000 }
76060 },
76061/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
76062 {
76063 { 0, 0, 0, 0 },
76064 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
76065 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c80000 }
76066 },
76067/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
76068 {
76069 { 0, 0, 0, 0 },
76070 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
76071 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7880000 }
76072 },
76073/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
76074 {
76075 { 0, 0, 0, 0 },
76076 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
76077 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a80000 }
76078 },
76079/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
76080 {
76081 { 0, 0, 0, 0 },
76082 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
76083 & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87880000 }
76084 },
76085/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76086 {
76087 { 0, 0, 0, 0 },
76088 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76089 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980800 }
76090 },
76091/* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
76092 {
76093 { 0, 0, 0, 0 },
76094 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76095 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982800 }
76096 },
76097/* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
76098 {
76099 { 0, 0, 0, 0 },
76100 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76101 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983800 }
76102 },
76103/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76104 {
76105 { 0, 0, 0, 0 },
76106 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76107 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908800 }
76108 },
76109/* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
76110 {
76111 { 0, 0, 0, 0 },
76112 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76113 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a800 }
76114 },
76115/* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
76116 {
76117 { 0, 0, 0, 0 },
76118 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76119 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b800 }
76120 },
76121/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76122 {
76123 { 0, 0, 0, 0 },
76124 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76125 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900800 }
76126 },
76127/* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
76128 {
76129 { 0, 0, 0, 0 },
76130 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76131 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902800 }
76132 },
76133/* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
76134 {
76135 { 0, 0, 0, 0 },
76136 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76137 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903800 }
76138 },
76139/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
76140 {
76141 { 0, 0, 0, 0 },
76142 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76143 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92080000 }
76144 },
76145/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
76146 {
76147 { 0, 0, 0, 0 },
76148 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76149 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92280000 }
76150 },
76151/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
76152 {
76153 { 0, 0, 0, 0 },
76154 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76155 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92380000 }
76156 },
76157/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
76158 {
76159 { 0, 0, 0, 0 },
76160 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76161 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94080000 }
76162 },
76163/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
76164 {
76165 { 0, 0, 0, 0 },
76166 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76167 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94280000 }
76168 },
76169/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
76170 {
76171 { 0, 0, 0, 0 },
76172 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76173 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94380000 }
76174 },
76175/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
76176 {
76177 { 0, 0, 0, 0 },
76178 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76179 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96080000 }
76180 },
76181/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
76182 {
76183 { 0, 0, 0, 0 },
76184 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76185 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96280000 }
76186 },
76187/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
76188 {
76189 { 0, 0, 0, 0 },
76190 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76191 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96380000 }
76192 },
76193/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
76194 {
76195 { 0, 0, 0, 0 },
76196 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76197 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92880000 }
76198 },
76199/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
76200 {
76201 { 0, 0, 0, 0 },
76202 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76203 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a80000 }
76204 },
76205/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
76206 {
76207 { 0, 0, 0, 0 },
76208 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76209 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b80000 }
76210 },
76211/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
76212 {
76213 { 0, 0, 0, 0 },
76214 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76215 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94880000 }
76216 },
76217/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
76218 {
76219 { 0, 0, 0, 0 },
76220 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76221 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a80000 }
76222 },
76223/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
76224 {
76225 { 0, 0, 0, 0 },
76226 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76227 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b80000 }
76228 },
76229/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
76230 {
76231 { 0, 0, 0, 0 },
76232 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76233 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c80000 }
76234 },
76235/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
76236 {
76237 { 0, 0, 0, 0 },
76238 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76239 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e80000 }
76240 },
76241/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
76242 {
76243 { 0, 0, 0, 0 },
76244 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76245 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f80000 }
76246 },
76247/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
76248 {
76249 { 0, 0, 0, 0 },
76250 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
76251 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c80000 }
76252 },
76253/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
76254 {
76255 { 0, 0, 0, 0 },
76256 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
76257 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e80000 }
76258 },
76259/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
76260 {
76261 { 0, 0, 0, 0 },
76262 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
76263 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f80000 }
76264 },
76265/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
76266 {
76267 { 0, 0, 0, 0 },
76268 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
76269 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c80000 }
76270 },
76271/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
76272 {
76273 { 0, 0, 0, 0 },
76274 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
76275 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e80000 }
76276 },
76277/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
76278 {
76279 { 0, 0, 0, 0 },
76280 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
76281 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f80000 }
76282 },
76283/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
76284 {
76285 { 0, 0, 0, 0 },
76286 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
76287 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96880000 }
76288 },
76289/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
76290 {
76291 { 0, 0, 0, 0 },
76292 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
76293 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a80000 }
76294 },
76295/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
76296 {
76297 { 0, 0, 0, 0 },
76298 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
76299 & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b80000 }
76300 },
76301/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76302 {
76303 { 0, 0, 0, 0 },
76304 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76305 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8080000 }
76306 },
76307/* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
76308 {
76309 { 0, 0, 0, 0 },
76310 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76311 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8280000 }
76312 },
76313/* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
76314 {
76315 { 0, 0, 0, 0 },
76316 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76317 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8380000 }
76318 },
76319/* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
76320 {
76321 { 0, 0, 0, 0 },
76322 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76323 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8380000 }
76324 },
76325/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76326 {
76327 { 0, 0, 0, 0 },
76328 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76329 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0880000 }
76330 },
76331/* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
76332 {
76333 { 0, 0, 0, 0 },
76334 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76335 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a80000 }
76336 },
76337/* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
76338 {
76339 { 0, 0, 0, 0 },
76340 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76341 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b80000 }
76342 },
76343/* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
76344 {
76345 { 0, 0, 0, 0 },
76346 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76347 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b80000 }
76348 },
76349/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76350 {
76351 { 0, 0, 0, 0 },
76352 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76353 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0080000 }
76354 },
76355/* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
76356 {
76357 { 0, 0, 0, 0 },
76358 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76359 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0280000 }
76360 },
76361/* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
76362 {
76363 { 0, 0, 0, 0 },
76364 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76365 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0380000 }
76366 },
76367/* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
76368 {
76369 { 0, 0, 0, 0 },
76370 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76371 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0380000 }
76372 },
76373/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
76374 {
76375 { 0, 0, 0, 0 },
76376 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76377 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2080000 }
76378 },
76379/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
76380 {
76381 { 0, 0, 0, 0 },
76382 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76383 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2280000 }
76384 },
76385/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
76386 {
76387 { 0, 0, 0, 0 },
76388 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76389 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2380000 }
76390 },
76391/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
76392 {
76393 { 0, 0, 0, 0 },
76394 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76395 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2380000 }
76396 },
76397/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76398 {
76399 { 0, 0, 0, 0 },
76400 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76401 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4080000 }
76402 },
76403/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76404 {
76405 { 0, 0, 0, 0 },
76406 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76407 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4280000 }
76408 },
76409/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76410 {
76411 { 0, 0, 0, 0 },
76412 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76413 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4380000 }
76414 },
76415/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
76416 {
76417 { 0, 0, 0, 0 },
76418 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76419 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4380000 }
76420 },
76421/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76422 {
76423 { 0, 0, 0, 0 },
76424 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76425 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6080000 }
76426 },
76427/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76428 {
76429 { 0, 0, 0, 0 },
76430 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76431 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6280000 }
76432 },
76433/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76434 {
76435 { 0, 0, 0, 0 },
76436 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76437 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6380000 }
76438 },
76439/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
76440 {
76441 { 0, 0, 0, 0 },
76442 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76443 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6380000 }
76444 },
76445/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
76446 {
76447 { 0, 0, 0, 0 },
76448 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76449 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2880000 }
76450 },
76451/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
76452 {
76453 { 0, 0, 0, 0 },
76454 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76455 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a80000 }
76456 },
76457/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
76458 {
76459 { 0, 0, 0, 0 },
76460 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76461 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b80000 }
76462 },
76463/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
76464 {
76465 { 0, 0, 0, 0 },
76466 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76467 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b80000 }
76468 },
76469/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
76470 {
76471 { 0, 0, 0, 0 },
76472 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76473 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4880000 }
76474 },
76475/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
76476 {
76477 { 0, 0, 0, 0 },
76478 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76479 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a80000 }
76480 },
76481/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
76482 {
76483 { 0, 0, 0, 0 },
76484 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76485 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b80000 }
76486 },
76487/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
76488 {
76489 { 0, 0, 0, 0 },
76490 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76491 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b80000 }
76492 },
76493/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
76494 {
76495 { 0, 0, 0, 0 },
76496 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76497 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c80000 }
76498 },
76499/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
76500 {
76501 { 0, 0, 0, 0 },
76502 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76503 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e80000 }
76504 },
76505/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
76506 {
76507 { 0, 0, 0, 0 },
76508 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76509 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f80000 }
76510 },
76511/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
76512 {
76513 { 0, 0, 0, 0 },
76514 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76515 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f80000 }
76516 },
76517/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
76518 {
76519 { 0, 0, 0, 0 },
76520 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76521 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c80000 }
76522 },
76523/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
76524 {
76525 { 0, 0, 0, 0 },
76526 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76527 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e80000 }
76528 },
76529/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
76530 {
76531 { 0, 0, 0, 0 },
76532 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76533 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f80000 }
76534 },
76535/* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
76536 {
76537 { 0, 0, 0, 0 },
76538 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76539 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f80000 }
76540 },
76541/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
76542 {
76543 { 0, 0, 0, 0 },
76544 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
76545 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c80000 }
76546 },
76547/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
76548 {
76549 { 0, 0, 0, 0 },
76550 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
76551 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e80000 }
76552 },
76553/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
76554 {
76555 { 0, 0, 0, 0 },
76556 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
76557 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f80000 }
76558 },
76559/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
76560 {
76561 { 0, 0, 0, 0 },
76562 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
76563 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f80000 }
76564 },
76565/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
76566 {
76567 { 0, 0, 0, 0 },
76568 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
76569 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6880000 }
76570 },
76571/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
76572 {
76573 { 0, 0, 0, 0 },
76574 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
76575 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a80000 }
76576 },
76577/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
76578 {
76579 { 0, 0, 0, 0 },
76580 { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
76581 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b80000 }
76582 },
76583/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
76584 {
76585 { 0, 0, 0, 0 },
76586 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
76587 & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b80000 }
76588 },
76589/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76590 {
76591 { 0, 0, 0, 0 },
76592 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76593 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8080000 }
76594 },
76595/* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
76596 {
76597 { 0, 0, 0, 0 },
76598 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76599 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8280000 }
76600 },
76601/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76602 {
76603 { 0, 0, 0, 0 },
76604 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76605 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0880000 }
76606 },
76607/* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
76608 {
76609 { 0, 0, 0, 0 },
76610 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76611 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a80000 }
76612 },
76613/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76614 {
76615 { 0, 0, 0, 0 },
76616 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76617 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0080000 }
76618 },
76619/* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
76620 {
76621 { 0, 0, 0, 0 },
76622 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76623 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0280000 }
76624 },
76625/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
76626 {
76627 { 0, 0, 0, 0 },
76628 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76629 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2080000 }
76630 },
76631/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
76632 {
76633 { 0, 0, 0, 0 },
76634 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76635 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2280000 }
76636 },
76637/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
76638 {
76639 { 0, 0, 0, 0 },
76640 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76641 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4080000 }
76642 },
76643/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
76644 {
76645 { 0, 0, 0, 0 },
76646 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76647 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4280000 }
76648 },
76649/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
76650 {
76651 { 0, 0, 0, 0 },
76652 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76653 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6080000 }
76654 },
76655/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
76656 {
76657 { 0, 0, 0, 0 },
76658 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76659 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6280000 }
76660 },
76661/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
76662 {
76663 { 0, 0, 0, 0 },
76664 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
76665 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2880000 }
76666 },
76667/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
76668 {
76669 { 0, 0, 0, 0 },
76670 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
76671 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a80000 }
76672 },
76673/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
76674 {
76675 { 0, 0, 0, 0 },
76676 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
76677 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4880000 }
76678 },
76679/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
76680 {
76681 { 0, 0, 0, 0 },
76682 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
76683 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a80000 }
76684 },
76685/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
76686 {
76687 { 0, 0, 0, 0 },
76688 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
76689 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c80000 }
76690 },
76691/* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
76692 {
76693 { 0, 0, 0, 0 },
76694 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
76695 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e80000 }
76696 },
76697/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
76698 {
76699 { 0, 0, 0, 0 },
76700 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
76701 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c80000 }
76702 },
76703/* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
76704 {
76705 { 0, 0, 0, 0 },
76706 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
76707 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e80000 }
76708 },
76709/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
76710 {
76711 { 0, 0, 0, 0 },
76712 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
76713 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c80000 }
76714 },
76715/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
76716 {
76717 { 0, 0, 0, 0 },
76718 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
76719 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e80000 }
76720 },
76721/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
76722 {
76723 { 0, 0, 0, 0 },
76724 { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
76725 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6880000 }
76726 },
76727/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
76728 {
76729 { 0, 0, 0, 0 },
76730 { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
76731 & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a80000 }
76732 },
76733/* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
76734 {
76735 { 0, 0, 0, 0 },
76736 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76737 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc808 }
76738 },
76739/* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
76740 {
76741 { 0, 0, 0, 0 },
76742 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76743 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8828 }
76744 },
76745/* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76746 {
76747 { 0, 0, 0, 0 },
76748 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76749 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8808 }
76750 },
76751/* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
76752 {
76753 { 0, 0, 0, 0 },
76754 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76755 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc088 }
76756 },
76757/* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
76758 {
76759 { 0, 0, 0, 0 },
76760 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76761 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a8 }
76762 },
76763/* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76764 {
76765 { 0, 0, 0, 0 },
76766 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76767 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8088 }
76768 },
76769/* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
76770 {
76771 { 0, 0, 0, 0 },
76772 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76773 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc008 }
76774 },
76775/* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
76776 {
76777 { 0, 0, 0, 0 },
76778 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76779 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8028 }
76780 },
76781/* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76782 {
76783 { 0, 0, 0, 0 },
76784 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76785 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8008 }
76786 },
76787/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
76788 {
76789 { 0, 0, 0, 0 },
76790 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76791 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20800 }
76792 },
76793/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
76794 {
76795 { 0, 0, 0, 0 },
76796 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76797 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822800 }
76798 },
76799/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
76800 {
76801 { 0, 0, 0, 0 },
76802 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76803 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820800 }
76804 },
76805/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
76806 {
76807 { 0, 0, 0, 0 },
76808 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76809 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4080000 }
76810 },
76811/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
76812 {
76813 { 0, 0, 0, 0 },
76814 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76815 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84280000 }
76816 },
76817/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
76818 {
76819 { 0, 0, 0, 0 },
76820 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76821 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84080000 }
76822 },
76823/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
76824 {
76825 { 0, 0, 0, 0 },
76826 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76827 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6080000 }
76828 },
76829/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
76830 {
76831 { 0, 0, 0, 0 },
76832 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76833 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86280000 }
76834 },
76835/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
76836 {
76837 { 0, 0, 0, 0 },
76838 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76839 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86080000 }
76840 },
76841/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
76842 {
76843 { 0, 0, 0, 0 },
76844 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76845 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28800 }
76846 },
76847/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
76848 {
76849 { 0, 0, 0, 0 },
76850 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76851 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a800 }
76852 },
76853/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
76854 {
76855 { 0, 0, 0, 0 },
76856 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76857 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828800 }
76858 },
76859/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
76860 {
76861 { 0, 0, 0, 0 },
76862 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76863 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4880000 }
76864 },
76865/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
76866 {
76867 { 0, 0, 0, 0 },
76868 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76869 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a80000 }
76870 },
76871/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
76872 {
76873 { 0, 0, 0, 0 },
76874 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76875 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84880000 }
76876 },
76877/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
76878 {
76879 { 0, 0, 0, 0 },
76880 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76881 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c800 }
76882 },
76883/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
76884 {
76885 { 0, 0, 0, 0 },
76886 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76887 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e800 }
76888 },
76889/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
76890 {
76891 { 0, 0, 0, 0 },
76892 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76893 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c800 }
76894 },
76895/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
76896 {
76897 { 0, 0, 0, 0 },
76898 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76899 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c80000 }
76900 },
76901/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
76902 {
76903 { 0, 0, 0, 0 },
76904 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76905 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e80000 }
76906 },
76907/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
76908 {
76909 { 0, 0, 0, 0 },
76910 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76911 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c80000 }
76912 },
76913/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
76914 {
76915 { 0, 0, 0, 0 },
76916 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
76917 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c80000 }
76918 },
76919/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
76920 {
76921 { 0, 0, 0, 0 },
76922 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
76923 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e80000 }
76924 },
76925/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
76926 {
76927 { 0, 0, 0, 0 },
76928 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
76929 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c80000 }
76930 },
76931/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
76932 {
76933 { 0, 0, 0, 0 },
76934 { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
76935 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6880000 }
76936 },
76937/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
76938 {
76939 { 0, 0, 0, 0 },
76940 { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
76941 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a80000 }
76942 },
76943/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
76944 {
76945 { 0, 0, 0, 0 },
76946 { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
76947 & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86880000 }
76948 },
76949/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
76950 {
76951 { 0, 0, 0, 0 },
76952 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
76953 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa18000 }
76954 },
76955/* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
76956 {
76957 { 0, 0, 0, 0 },
76958 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
76959 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1a000 }
76960 },
76961/* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
76962 {
76963 { 0, 0, 0, 0 },
76964 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
76965 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa1b000 }
76966 },
76967/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
76968 {
76969 { 0, 0, 0, 0 },
76970 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
76971 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa18400 }
76972 },
76973/* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
76974 {
76975 { 0, 0, 0, 0 },
76976 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
76977 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa1a400 }
76978 },
76979/* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
76980 {
76981 { 0, 0, 0, 0 },
76982 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
76983 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa1b400 }
76984 },
76985/* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
76986 {
76987 { 0, 0, 0, 0 },
76988 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
76989 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa18600 }
76990 },
76991/* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
76992 {
76993 { 0, 0, 0, 0 },
76994 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
76995 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa1a600 }
76996 },
76997/* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
76998 {
76999 { 0, 0, 0, 0 },
77000 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77001 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa1b600 }
77002 },
77003/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
77004 {
77005 { 0, 0, 0, 0 },
77006 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77007 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa1880000 }
77008 },
77009/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
77010 {
77011 { 0, 0, 0, 0 },
77012 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77013 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1a80000 }
77014 },
77015/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
77016 {
77017 { 0, 0, 0, 0 },
77018 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77019 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1b80000 }
77020 },
77021/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
77022 {
77023 { 0, 0, 0, 0 },
77024 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77025 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa18c0000 }
77026 },
77027/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
77028 {
77029 { 0, 0, 0, 0 },
77030 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77031 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1ac0000 }
77032 },
77033/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
77034 {
77035 { 0, 0, 0, 0 },
77036 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77037 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1bc0000 }
77038 },
77039/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
77040 {
77041 { 0, 0, 0, 0 },
77042 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77043 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa18a0000 }
77044 },
77045/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
77046 {
77047 { 0, 0, 0, 0 },
77048 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77049 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1aa0000 }
77050 },
77051/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
77052 {
77053 { 0, 0, 0, 0 },
77054 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77055 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1ba0000 }
77056 },
77057/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
77058 {
77059 { 0, 0, 0, 0 },
77060 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77061 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa18e0000 }
77062 },
77063/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
77064 {
77065 { 0, 0, 0, 0 },
77066 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77067 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1ae0000 }
77068 },
77069/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
77070 {
77071 { 0, 0, 0, 0 },
77072 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77073 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1be0000 }
77074 },
77075/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
77076 {
77077 { 0, 0, 0, 0 },
77078 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77079 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa18b0000 }
77080 },
77081/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
77082 {
77083 { 0, 0, 0, 0 },
77084 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77085 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1ab0000 }
77086 },
77087/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
77088 {
77089 { 0, 0, 0, 0 },
77090 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77091 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1bb0000 }
77092 },
77093/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
77094 {
77095 { 0, 0, 0, 0 },
77096 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
77097 & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa18f0000 }
77098 },
77099/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
77100 {
77101 { 0, 0, 0, 0 },
77102 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77103 & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa1af0000 }
77104 },
77105/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
77106 {
77107 { 0, 0, 0, 0 },
77108 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77109 & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa1bf0000 }
77110 },
77111/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
77112 {
77113 { 0, 0, 0, 0 },
77114 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
77115 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa1c00000 }
77116 },
77117/* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
77118 {
77119 { 0, 0, 0, 0 },
77120 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
77121 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1e00000 }
77122 },
77123/* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
77124 {
77125 { 0, 0, 0, 0 },
77126 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
77127 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa1f00000 }
77128 },
77129/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
77130 {
77131 { 0, 0, 0, 0 },
77132 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
77133 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa1c40000 }
77134 },
77135/* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
77136 {
77137 { 0, 0, 0, 0 },
77138 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
77139 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa1e40000 }
77140 },
77141/* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
77142 {
77143 { 0, 0, 0, 0 },
77144 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
77145 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa1f40000 }
77146 },
77147/* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
77148 {
77149 { 0, 0, 0, 0 },
77150 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77151 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa1c60000 }
77152 },
77153/* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
77154 {
77155 { 0, 0, 0, 0 },
77156 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77157 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa1e60000 }
77158 },
77159/* add.w${G} ${Dsp-16-u16},[$Dst16An] */
77160 {
77161 { 0, 0, 0, 0 },
77162 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
77163 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa1f60000 }
77164 },
77165/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
77166 {
77167 { 0, 0, 0, 0 },
77168 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77169 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa1c80000 }
77170 },
77171/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
77172 {
77173 { 0, 0, 0, 0 },
77174 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77175 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa1e80000 }
77176 },
77177/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
77178 {
77179 { 0, 0, 0, 0 },
77180 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77181 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa1f80000 }
77182 },
77183/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
77184 {
77185 { 0, 0, 0, 0 },
77186 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77187 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa1cc0000 }
77188 },
77189/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
77190 {
77191 { 0, 0, 0, 0 },
77192 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77193 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa1ec0000 }
77194 },
77195/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
77196 {
77197 { 0, 0, 0, 0 },
77198 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77199 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa1fc0000 }
77200 },
77201/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
77202 {
77203 { 0, 0, 0, 0 },
77204 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77205 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ca0000 }
77206 },
77207/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
77208 {
77209 { 0, 0, 0, 0 },
77210 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77211 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ea0000 }
77212 },
77213/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
77214 {
77215 { 0, 0, 0, 0 },
77216 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77217 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa1fa0000 }
77218 },
77219/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
77220 {
77221 { 0, 0, 0, 0 },
77222 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77223 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ce0000 }
77224 },
77225/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
77226 {
77227 { 0, 0, 0, 0 },
77228 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77229 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ee0000 }
77230 },
77231/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
77232 {
77233 { 0, 0, 0, 0 },
77234 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77235 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa1fe0000 }
77236 },
77237/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
77238 {
77239 { 0, 0, 0, 0 },
77240 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77241 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1cb0000 }
77242 },
77243/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
77244 {
77245 { 0, 0, 0, 0 },
77246 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77247 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1eb0000 }
77248 },
77249/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
77250 {
77251 { 0, 0, 0, 0 },
77252 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77253 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa1fb0000 }
77254 },
77255/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
77256 {
77257 { 0, 0, 0, 0 },
77258 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
77259 & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa1cf0000 }
77260 },
77261/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
77262 {
77263 { 0, 0, 0, 0 },
77264 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
77265 & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa1ef0000 }
77266 },
77267/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
77268 {
77269 { 0, 0, 0, 0 },
77270 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
77271 & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa1ff0000 }
77272 },
77273/* add.w${G} $Src16RnHI,$Dst16RnHI */
77274 {
77275 { 0, 0, 0, 0 },
77276 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
77277 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa100 }
77278 },
77279/* add.w${G} $Src16AnHI,$Dst16RnHI */
77280 {
77281 { 0, 0, 0, 0 },
77282 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
77283 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa140 }
77284 },
77285/* add.w${G} [$Src16An],$Dst16RnHI */
77286 {
77287 { 0, 0, 0, 0 },
77288 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
77289 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa160 }
77290 },
77291/* add.w${G} $Src16RnHI,$Dst16AnHI */
77292 {
77293 { 0, 0, 0, 0 },
77294 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
77295 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa104 }
77296 },
77297/* add.w${G} $Src16AnHI,$Dst16AnHI */
77298 {
77299 { 0, 0, 0, 0 },
77300 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
77301 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa144 }
77302 },
77303/* add.w${G} [$Src16An],$Dst16AnHI */
77304 {
77305 { 0, 0, 0, 0 },
77306 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
77307 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa164 }
77308 },
77309/* add.w${G} $Src16RnHI,[$Dst16An] */
77310 {
77311 { 0, 0, 0, 0 },
77312 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
77313 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa106 }
77314 },
77315/* add.w${G} $Src16AnHI,[$Dst16An] */
77316 {
77317 { 0, 0, 0, 0 },
77318 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
77319 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa146 }
77320 },
77321/* add.w${G} [$Src16An],[$Dst16An] */
77322 {
77323 { 0, 0, 0, 0 },
77324 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77325 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa166 }
77326 },
77327/* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
77328 {
77329 { 0, 0, 0, 0 },
77330 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77331 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa10800 }
77332 },
77333/* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
77334 {
77335 { 0, 0, 0, 0 },
77336 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77337 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa14800 }
77338 },
77339/* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
77340 {
77341 { 0, 0, 0, 0 },
77342 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77343 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa16800 }
77344 },
77345/* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
77346 {
77347 { 0, 0, 0, 0 },
77348 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77349 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa10c0000 }
77350 },
77351/* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
77352 {
77353 { 0, 0, 0, 0 },
77354 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77355 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa14c0000 }
77356 },
77357/* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
77358 {
77359 { 0, 0, 0, 0 },
77360 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77361 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa16c0000 }
77362 },
77363/* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
77364 {
77365 { 0, 0, 0, 0 },
77366 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77367 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa10a00 }
77368 },
77369/* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
77370 {
77371 { 0, 0, 0, 0 },
77372 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77373 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa14a00 }
77374 },
77375/* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
77376 {
77377 { 0, 0, 0, 0 },
77378 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77379 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa16a00 }
77380 },
77381/* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
77382 {
77383 { 0, 0, 0, 0 },
77384 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77385 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa10e0000 }
77386 },
77387/* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
77388 {
77389 { 0, 0, 0, 0 },
77390 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77391 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa14e0000 }
77392 },
77393/* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
77394 {
77395 { 0, 0, 0, 0 },
77396 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77397 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa16e0000 }
77398 },
77399/* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
77400 {
77401 { 0, 0, 0, 0 },
77402 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77403 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa10b00 }
77404 },
77405/* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
77406 {
77407 { 0, 0, 0, 0 },
77408 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77409 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa14b00 }
77410 },
77411/* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
77412 {
77413 { 0, 0, 0, 0 },
77414 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77415 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa16b00 }
77416 },
77417/* add.w${G} $Src16RnHI,${Dsp-16-u16} */
77418 {
77419 { 0, 0, 0, 0 },
77420 { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
77421 & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa10f0000 }
77422 },
77423/* add.w${G} $Src16AnHI,${Dsp-16-u16} */
77424 {
77425 { 0, 0, 0, 0 },
77426 { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
77427 & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa14f0000 }
77428 },
77429/* add.w${G} [$Src16An],${Dsp-16-u16} */
77430 {
77431 { 0, 0, 0, 0 },
77432 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
77433 & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa16f0000 }
77434 },
77435/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
77436 {
77437 { 0, 0, 0, 0 },
77438 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77439 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa08000 }
77440 },
77441/* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
77442 {
77443 { 0, 0, 0, 0 },
77444 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
77445 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0a000 }
77446 },
77447/* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
77448 {
77449 { 0, 0, 0, 0 },
77450 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
77451 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa0b000 }
77452 },
77453/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
77454 {
77455 { 0, 0, 0, 0 },
77456 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77457 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa08400 }
77458 },
77459/* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
77460 {
77461 { 0, 0, 0, 0 },
77462 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
77463 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa0a400 }
77464 },
77465/* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
77466 {
77467 { 0, 0, 0, 0 },
77468 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
77469 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa0b400 }
77470 },
77471/* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
77472 {
77473 { 0, 0, 0, 0 },
77474 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77475 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa08600 }
77476 },
77477/* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
77478 {
77479 { 0, 0, 0, 0 },
77480 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77481 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa0a600 }
77482 },
77483/* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
77484 {
77485 { 0, 0, 0, 0 },
77486 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77487 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa0b600 }
77488 },
77489/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
77490 {
77491 { 0, 0, 0, 0 },
77492 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77493 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa0880000 }
77494 },
77495/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
77496 {
77497 { 0, 0, 0, 0 },
77498 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77499 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0a80000 }
77500 },
77501/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
77502 {
77503 { 0, 0, 0, 0 },
77504 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77505 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0b80000 }
77506 },
77507/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
77508 {
77509 { 0, 0, 0, 0 },
77510 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77511 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa08c0000 }
77512 },
77513/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
77514 {
77515 { 0, 0, 0, 0 },
77516 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77517 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0ac0000 }
77518 },
77519/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
77520 {
77521 { 0, 0, 0, 0 },
77522 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77523 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0bc0000 }
77524 },
77525/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
77526 {
77527 { 0, 0, 0, 0 },
77528 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77529 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa08a0000 }
77530 },
77531/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
77532 {
77533 { 0, 0, 0, 0 },
77534 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77535 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0aa0000 }
77536 },
77537/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
77538 {
77539 { 0, 0, 0, 0 },
77540 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77541 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0ba0000 }
77542 },
77543/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
77544 {
77545 { 0, 0, 0, 0 },
77546 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77547 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa08e0000 }
77548 },
77549/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
77550 {
77551 { 0, 0, 0, 0 },
77552 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77553 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0ae0000 }
77554 },
77555/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
77556 {
77557 { 0, 0, 0, 0 },
77558 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77559 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0be0000 }
77560 },
77561/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
77562 {
77563 { 0, 0, 0, 0 },
77564 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77565 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa08b0000 }
77566 },
77567/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
77568 {
77569 { 0, 0, 0, 0 },
77570 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77571 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0ab0000 }
77572 },
77573/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
77574 {
77575 { 0, 0, 0, 0 },
77576 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77577 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0bb0000 }
77578 },
77579/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
77580 {
77581 { 0, 0, 0, 0 },
77582 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
77583 & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa08f0000 }
77584 },
77585/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
77586 {
77587 { 0, 0, 0, 0 },
77588 { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77589 & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa0af0000 }
77590 },
77591/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
77592 {
77593 { 0, 0, 0, 0 },
77594 { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77595 & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa0bf0000 }
77596 },
77597/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
77598 {
77599 { 0, 0, 0, 0 },
77600 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77601 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa0c00000 }
77602 },
77603/* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
77604 {
77605 { 0, 0, 0, 0 },
77606 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
77607 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0e00000 }
77608 },
77609/* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
77610 {
77611 { 0, 0, 0, 0 },
77612 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
77613 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa0f00000 }
77614 },
77615/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
77616 {
77617 { 0, 0, 0, 0 },
77618 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77619 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa0c40000 }
77620 },
77621/* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
77622 {
77623 { 0, 0, 0, 0 },
77624 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
77625 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa0e40000 }
77626 },
77627/* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
77628 {
77629 { 0, 0, 0, 0 },
77630 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
77631 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa0f40000 }
77632 },
77633/* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
77634 {
77635 { 0, 0, 0, 0 },
77636 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77637 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa0c60000 }
77638 },
77639/* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
77640 {
77641 { 0, 0, 0, 0 },
77642 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77643 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa0e60000 }
77644 },
77645/* add.b${G} ${Dsp-16-u16},[$Dst16An] */
77646 {
77647 { 0, 0, 0, 0 },
77648 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
77649 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa0f60000 }
77650 },
77651/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
77652 {
77653 { 0, 0, 0, 0 },
77654 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77655 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa0c80000 }
77656 },
77657/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
77658 {
77659 { 0, 0, 0, 0 },
77660 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77661 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa0e80000 }
77662 },
77663/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
77664 {
77665 { 0, 0, 0, 0 },
77666 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77667 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa0f80000 }
77668 },
77669/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
77670 {
77671 { 0, 0, 0, 0 },
77672 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77673 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa0cc0000 }
77674 },
77675/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
77676 {
77677 { 0, 0, 0, 0 },
77678 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77679 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa0ec0000 }
77680 },
77681/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
77682 {
77683 { 0, 0, 0, 0 },
77684 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77685 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa0fc0000 }
77686 },
77687/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
77688 {
77689 { 0, 0, 0, 0 },
77690 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77691 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ca0000 }
77692 },
77693/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
77694 {
77695 { 0, 0, 0, 0 },
77696 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77697 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ea0000 }
77698 },
77699/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
77700 {
77701 { 0, 0, 0, 0 },
77702 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77703 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa0fa0000 }
77704 },
77705/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
77706 {
77707 { 0, 0, 0, 0 },
77708 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77709 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ce0000 }
77710 },
77711/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
77712 {
77713 { 0, 0, 0, 0 },
77714 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77715 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ee0000 }
77716 },
77717/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
77718 {
77719 { 0, 0, 0, 0 },
77720 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77721 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa0fe0000 }
77722 },
77723/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
77724 {
77725 { 0, 0, 0, 0 },
77726 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77727 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0cb0000 }
77728 },
77729/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
77730 {
77731 { 0, 0, 0, 0 },
77732 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77733 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0eb0000 }
77734 },
77735/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
77736 {
77737 { 0, 0, 0, 0 },
77738 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77739 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa0fb0000 }
77740 },
77741/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
77742 {
77743 { 0, 0, 0, 0 },
77744 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
77745 & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa0cf0000 }
77746 },
77747/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
77748 {
77749 { 0, 0, 0, 0 },
77750 { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
77751 & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa0ef0000 }
77752 },
77753/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
77754 {
77755 { 0, 0, 0, 0 },
77756 { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
77757 & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa0ff0000 }
77758 },
77759/* add.b${G} $Src16RnQI,$Dst16RnQI */
77760 {
77761 { 0, 0, 0, 0 },
77762 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
77763 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa000 }
77764 },
77765/* add.b${G} $Src16AnQI,$Dst16RnQI */
77766 {
77767 { 0, 0, 0, 0 },
77768 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
77769 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa040 }
77770 },
77771/* add.b${G} [$Src16An],$Dst16RnQI */
77772 {
77773 { 0, 0, 0, 0 },
77774 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77775 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa060 }
77776 },
77777/* add.b${G} $Src16RnQI,$Dst16AnQI */
77778 {
77779 { 0, 0, 0, 0 },
77780 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
77781 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa004 }
77782 },
77783/* add.b${G} $Src16AnQI,$Dst16AnQI */
77784 {
77785 { 0, 0, 0, 0 },
77786 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
77787 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa044 }
77788 },
77789/* add.b${G} [$Src16An],$Dst16AnQI */
77790 {
77791 { 0, 0, 0, 0 },
77792 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77793 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa064 }
77794 },
77795/* add.b${G} $Src16RnQI,[$Dst16An] */
77796 {
77797 { 0, 0, 0, 0 },
77798 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
77799 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa006 }
77800 },
77801/* add.b${G} $Src16AnQI,[$Dst16An] */
77802 {
77803 { 0, 0, 0, 0 },
77804 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
77805 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa046 }
77806 },
77807/* add.b${G} [$Src16An],[$Dst16An] */
77808 {
77809 { 0, 0, 0, 0 },
77810 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77811 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa066 }
77812 },
77813/* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
77814 {
77815 { 0, 0, 0, 0 },
77816 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77817 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa00800 }
77818 },
77819/* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
77820 {
77821 { 0, 0, 0, 0 },
77822 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77823 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa04800 }
77824 },
77825/* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
77826 {
77827 { 0, 0, 0, 0 },
77828 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77829 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa06800 }
77830 },
77831/* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
77832 {
77833 { 0, 0, 0, 0 },
77834 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77835 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa00c0000 }
77836 },
77837/* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
77838 {
77839 { 0, 0, 0, 0 },
77840 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77841 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa04c0000 }
77842 },
77843/* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
77844 {
77845 { 0, 0, 0, 0 },
77846 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77847 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa06c0000 }
77848 },
77849/* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
77850 {
77851 { 0, 0, 0, 0 },
77852 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77853 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa00a00 }
77854 },
77855/* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
77856 {
77857 { 0, 0, 0, 0 },
77858 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77859 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa04a00 }
77860 },
77861/* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
77862 {
77863 { 0, 0, 0, 0 },
77864 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77865 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa06a00 }
77866 },
77867/* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
77868 {
77869 { 0, 0, 0, 0 },
77870 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77871 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa00e0000 }
77872 },
77873/* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
77874 {
77875 { 0, 0, 0, 0 },
77876 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77877 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa04e0000 }
77878 },
77879/* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
77880 {
77881 { 0, 0, 0, 0 },
77882 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77883 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa06e0000 }
77884 },
77885/* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
77886 {
77887 { 0, 0, 0, 0 },
77888 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77889 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa00b00 }
77890 },
77891/* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
77892 {
77893 { 0, 0, 0, 0 },
77894 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77895 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa04b00 }
77896 },
77897/* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
77898 {
77899 { 0, 0, 0, 0 },
77900 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77901 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa06b00 }
77902 },
77903/* add.b${G} $Src16RnQI,${Dsp-16-u16} */
77904 {
77905 { 0, 0, 0, 0 },
77906 { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
77907 & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa00f0000 }
77908 },
77909/* add.b${G} $Src16AnQI,${Dsp-16-u16} */
77910 {
77911 { 0, 0, 0, 0 },
77912 { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
77913 & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa04f0000 }
77914 },
77915/* add.b${G} [$Src16An],${Dsp-16-u16} */
77916 {
77917 { 0, 0, 0, 0 },
77918 { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
77919 & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa06f0000 }
77920 },
77921/* add.b${S} #${Imm-8-QI},r0l */
77922 {
77923 { 0, 0, 0, 0 },
77924 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
77925 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8400 }
77926 },
77927/* add.b${S} #${Imm-8-QI},r0h */
77928 {
77929 { 0, 0, 0, 0 },
77930 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
77931 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8300 }
77932 },
77933/* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
77934 {
77935 { 0, 0, 0, 0 },
77936 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77937 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x850000 }
77938 },
77939/* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
77940 {
77941 { 0, 0, 0, 0 },
77942 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77943 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x860000 }
77944 },
77945/* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
77946 {
77947 { 0, 0, 0, 0 },
77948 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
77949 & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x87000000 }
77950 },
77951/* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
77952 {
77953 { 0, 0, 0, 0 },
77954 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
77955 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xf830 }
77956 },
77957/* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
77958 {
77959 { 0, 0, 0, 0 },
77960 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
77961 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xf0b0 }
77962 },
77963/* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
77964 {
77965 { 0, 0, 0, 0 },
77966 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77967 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xf030 }
77968 },
77969/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
77970 {
77971 { 0, 0, 0, 0 },
77972 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77973 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xf23000 }
77974 },
77975/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
77976 {
77977 { 0, 0, 0, 0 },
77978 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77979 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xf4300000 }
77980 },
77981/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
77982 {
77983 { 0, 0, 0, 0 },
77984 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77985 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xf6300000 }
77986 },
77987/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
77988 {
77989 { 0, 0, 0, 0 },
77990 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77991 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xf2b000 }
77992 },
77993/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
77994 {
77995 { 0, 0, 0, 0 },
77996 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77997 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xf4b00000 }
77998 },
77999/* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
78000 {
78001 { 0, 0, 0, 0 },
78002 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78003 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xf2f000 }
78004 },
78005/* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
78006 {
78007 { 0, 0, 0, 0 },
78008 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78009 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xf4f00000 }
78010 },
78011/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
78012 {
78013 { 0, 0, 0, 0 },
78014 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
78015 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xf6f00000 }
78016 },
78017/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
78018 {
78019 { 0, 0, 0, 0 },
78020 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
78021 & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xf6b00000 }
78022 },
78023/* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
78024 {
78025 { 0, 0, 0, 0 },
78026 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
78027 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe930 }
78028 },
78029/* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
78030 {
78031 { 0, 0, 0, 0 },
78032 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
78033 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1b0 }
78034 },
78035/* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
78036 {
78037 { 0, 0, 0, 0 },
78038 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78039 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe130 }
78040 },
78041/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78042 {
78043 { 0, 0, 0, 0 },
78044 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78045 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe33000 }
78046 },
78047/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78048 {
78049 { 0, 0, 0, 0 },
78050 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78051 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5300000 }
78052 },
78053/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78054 {
78055 { 0, 0, 0, 0 },
78056 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78057 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7300000 }
78058 },
78059/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
78060 {
78061 { 0, 0, 0, 0 },
78062 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78063 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3b000 }
78064 },
78065/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
78066 {
78067 { 0, 0, 0, 0 },
78068 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78069 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5b00000 }
78070 },
78071/* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
78072 {
78073 { 0, 0, 0, 0 },
78074 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78075 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3f000 }
78076 },
78077/* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
78078 {
78079 { 0, 0, 0, 0 },
78080 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78081 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5f00000 }
78082 },
78083/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
78084 {
78085 { 0, 0, 0, 0 },
78086 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
78087 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7f00000 }
78088 },
78089/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
78090 {
78091 { 0, 0, 0, 0 },
78092 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
78093 & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7b00000 }
78094 },
78095/* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
78096 {
78097 { 0, 0, 0, 0 },
78098 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
78099 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe830 }
78100 },
78101/* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
78102 {
78103 { 0, 0, 0, 0 },
78104 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
78105 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0b0 }
78106 },
78107/* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
78108 {
78109 { 0, 0, 0, 0 },
78110 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78111 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe030 }
78112 },
78113/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78114 {
78115 { 0, 0, 0, 0 },
78116 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78117 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe23000 }
78118 },
78119/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78120 {
78121 { 0, 0, 0, 0 },
78122 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78123 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4300000 }
78124 },
78125/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78126 {
78127 { 0, 0, 0, 0 },
78128 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78129 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6300000 }
78130 },
78131/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
78132 {
78133 { 0, 0, 0, 0 },
78134 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78135 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2b000 }
78136 },
78137/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
78138 {
78139 { 0, 0, 0, 0 },
78140 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78141 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4b00000 }
78142 },
78143/* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
78144 {
78145 { 0, 0, 0, 0 },
78146 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78147 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2f000 }
78148 },
78149/* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
78150 {
78151 { 0, 0, 0, 0 },
78152 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78153 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4f00000 }
78154 },
78155/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
78156 {
78157 { 0, 0, 0, 0 },
78158 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
78159 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6f00000 }
78160 },
78161/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
78162 {
78163 { 0, 0, 0, 0 },
78164 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
78165 & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6b00000 }
78166 },
78167/* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
78168 {
78169 { 0, 0, 0, 0 },
78170 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
db313fa6 78171 & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xc900 }
49f58d10
JB		 78172 },
78173/* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
78174 {
78175 { 0, 0, 0, 0 },
78176 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
db313fa6 78177 & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xc904 }
49f58d10
JB		 78178 },
78179/* add.w${Q} #${Imm-8-s4},[$Dst16An] */
78180 {
78181 { 0, 0, 0, 0 },
78182 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
db313fa6 78183 & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xc906 }
49f58d10
JB		 78184 },
78185/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
78186 {
78187 { 0, 0, 0, 0 },
78188 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
db313fa6 78189 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xc90800 }
49f58d10
JB		 78190 },
78191/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
78192 {
78193 { 0, 0, 0, 0 },
78194 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
db313fa6 78195 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xc90c0000 }
49f58d10
JB		 78196 },
78197/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
78198 {
78199 { 0, 0, 0, 0 },
78200 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
db313fa6 78201 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xc90a00 }
49f58d10
JB		 78202 },
78203/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
78204 {
78205 { 0, 0, 0, 0 },
78206 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
db313fa6 78207 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xc90e0000 }
49f58d10
JB		 78208 },
78209/* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
78210 {
78211 { 0, 0, 0, 0 },
78212 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
db313fa6 78213 & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xc90b00 }
49f58d10
JB		 78214 },
78215/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
78216 {
78217 { 0, 0, 0, 0 },
78218 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
db313fa6 78219 & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xc90f0000 }
49f58d10
JB		 78220 },
78221/* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
78222 {
78223 { 0, 0, 0, 0 },
78224 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
db313fa6 78225 & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xc800 }
49f58d10
JB		 78226 },
78227/* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
78228 {
78229 { 0, 0, 0, 0 },
78230 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
db313fa6 78231 & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xc804 }
49f58d10
JB		 78232 },
78233/* add.b${Q} #${Imm-8-s4},[$Dst16An] */
78234 {
78235 { 0, 0, 0, 0 },
78236 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
db313fa6 78237 & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xc806 }
49f58d10
JB		 78238 },
78239/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
78240 {
78241 { 0, 0, 0, 0 },
78242 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
db313fa6 78243 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xc80800 }
49f58d10
JB		 78244 },
78245/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
78246 {
78247 { 0, 0, 0, 0 },
78248 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
db313fa6 78249 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xc80c0000 }
49f58d10
JB		 78250 },
78251/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
78252 {
78253 { 0, 0, 0, 0 },
78254 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
db313fa6 78255 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xc80a00 }
49f58d10
JB		 78256 },
78257/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
78258 {
78259 { 0, 0, 0, 0 },
78260 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
db313fa6 78261 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xc80e0000 }
49f58d10
JB		 78262 },
78263/* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
78264 {
78265 { 0, 0, 0, 0 },
78266 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
db313fa6 78267 & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xc80b00 }
49f58d10
JB		 78268 },
78269/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
78270 {
78271 { 0, 0, 0, 0 },
78272 { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
db313fa6 78273 & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xc80f0000 }
49f58d10
JB		 78274 },
78275/* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
78276 {
78277 { 0, 0, 0, 0 },
78278 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
78279 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892e0000 }
78280 },
78281/* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
78282 {
78283 { 0, 0, 0, 0 },
78284 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
78285 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81ae0000 }
78286 },
78287/* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
78288 {
78289 { 0, 0, 0, 0 },
78290 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78291 & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812e0000 }
78292 },
78293/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78294 {
78295 { 0, 0, 0, 0 },
78296 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78297 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832e0000 }
78298 },
78299/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
78300 {
78301 { 0, 0, 0, 0 },
78302 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78303 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ae0000 }
78304 },
78305/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
78306 {
78307 { 0, 0, 0, 0 },
78308 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78309 & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ee0000 }
78310 },
78311/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78312 {
78313 { 0, 0, 0, 0 },
78314 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78315 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852e0000 }
78316 },
78317/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
78318 {
78319 { 0, 0, 0, 0 },
78320 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78321 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ae0000 }
78322 },
78323/* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
78324 {
78325 { 0, 0, 0, 0 },
78326 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78327 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ee0000 }
78328 },
78329/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
78330 {
78331 { 0, 0, 0, 0 },
78332 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
78333 & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ee0000 }
78334 },
78335/* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78336 {
78337 { 0, 0, 0, 0 },
78338 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78339 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872e0000 }
78340 },
78341/* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
78342 {
78343 { 0, 0, 0, 0 },
78344 { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
78345 & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87ae0000 }
78346 },
78347/* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
78348 {
78349 { 0, 0, 0, 0 },
78350 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
78351 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882e00 }
78352 },
78353/* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
78354 {
78355 { 0, 0, 0, 0 },
78356 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
78357 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80ae00 }
78358 },
78359/* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
78360 {
78361 { 0, 0, 0, 0 },
78362 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78363 & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802e00 }
78364 },
78365/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78366 {
78367 { 0, 0, 0, 0 },
78368 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78369 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822e0000 }
78370 },
78371/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
78372 {
78373 { 0, 0, 0, 0 },
78374 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78375 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ae0000 }
78376 },
78377/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
78378 {
78379 { 0, 0, 0, 0 },
78380 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78381 & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ee0000 }
78382 },
78383/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78384 {
78385 { 0, 0, 0, 0 },
78386 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78387 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842e0000 }
78388 },
78389/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
78390 {
78391 { 0, 0, 0, 0 },
78392 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78393 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ae0000 }
78394 },
78395/* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
78396 {
78397 { 0, 0, 0, 0 },
78398 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78399 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ee0000 }
78400 },
78401/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
78402 {
78403 { 0, 0, 0, 0 },
78404 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
78405 & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ee0000 }
78406 },
78407/* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78408 {
78409 { 0, 0, 0, 0 },
78410 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78411 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862e0000 }
78412 },
78413/* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
78414 {
78415 { 0, 0, 0, 0 },
78416 { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
78417 & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86ae0000 }
78418 },
78419/* add.w${G} #${Imm-16-HI},$Dst16RnHI */
78420 {
78421 { 0, 0, 0, 0 },
78422 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
78423 & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77400000 }
78424 },
78425/* add.w${G} #${Imm-16-HI},$Dst16AnHI */
78426 {
78427 { 0, 0, 0, 0 },
78428 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
78429 & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77440000 }
78430 },
78431/* add.w${G} #${Imm-16-HI},[$Dst16An] */
78432 {
78433 { 0, 0, 0, 0 },
78434 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
78435 & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77460000 }
78436 },
78437/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
78438 {
78439 { 0, 0, 0, 0 },
78440 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78441 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77480000 }
78442 },
78443/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
78444 {
78445 { 0, 0, 0, 0 },
78446 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78447 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x774a0000 }
78448 },
78449/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
78450 {
78451 { 0, 0, 0, 0 },
78452 { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78453 & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x774b0000 }
78454 },
78455/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
78456 {
78457 { 0, 0, 0, 0 },
78458 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78459 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x774c0000 }
78460 },
78461/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
78462 {
78463 { 0, 0, 0, 0 },
78464 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78465 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x774e0000 }
78466 },
78467/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
78468 {
78469 { 0, 0, 0, 0 },
78470 { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
78471 & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x774f0000 }
78472 },
78473/* add.b${G} #${Imm-16-QI},$Dst16RnQI */
78474 {
78475 { 0, 0, 0, 0 },
78476 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
78477 & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x764000 }
78478 },
78479/* add.b${G} #${Imm-16-QI},$Dst16AnQI */
78480 {
78481 { 0, 0, 0, 0 },
78482 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
78483 & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x764400 }
78484 },
78485/* add.b${G} #${Imm-16-QI},[$Dst16An] */
78486 {
78487 { 0, 0, 0, 0 },
78488 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
78489 & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x764600 }
78490 },
78491/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
78492 {
78493 { 0, 0, 0, 0 },
78494 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78495 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76480000 }
78496 },
78497/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
78498 {
78499 { 0, 0, 0, 0 },
78500 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78501 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x764a0000 }
78502 },
78503/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
78504 {
78505 { 0, 0, 0, 0 },
78506 { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78507 & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x764b0000 }
78508 },
78509/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
78510 {
78511 { 0, 0, 0, 0 },
78512 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78513 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x764c0000 }
78514 },
78515/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
78516 {
78517 { 0, 0, 0, 0 },
78518 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78519 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x764e0000 }
78520 },
78521/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
78522 {
78523 { 0, 0, 0, 0 },
78524 { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
78525 & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x764f0000 }
78526 },
78527/* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
78528 {
78529 { 0, 0, 0, 0 },
78530 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
78531 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x88310000 }
78532 },
78533/* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
78534 {
78535 { 0, 0, 0, 0 },
78536 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
78537 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80b10000 }
78538 },
78539/* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
78540 {
78541 { 0, 0, 0, 0 },
78542 { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78543 & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x80310000 }
78544 },
78545/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78546 {
78547 { 0, 0, 0, 0 },
78548 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78549 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82310000 }
78550 },
78551/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
78552 {
78553 { 0, 0, 0, 0 },
78554 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78555 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82b10000 }
78556 },
78557/* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
78558 {
78559 { 0, 0, 0, 0 },
78560 { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78561 & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82f10000 }
78562 },
78563/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78564 {
78565 { 0, 0, 0, 0 },
78566 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78567 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84310000 }
78568 },
78569/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
78570 {
78571 { 0, 0, 0, 0 },
78572 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78573 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84b10000 }
78574 },
78575/* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
78576 {
78577 { 0, 0, 0, 0 },
78578 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78579 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84f10000 }
78580 },
78581/* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
78582 {
78583 { 0, 0, 0, 0 },
78584 { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
78585 & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86f10000 }
78586 },
78587/* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78588 {
78589 { 0, 0, 0, 0 },
78590 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78591 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86310000 }
78592 },
78593/* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
78594 {
78595 { 0, 0, 0, 0 },
78596 { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
78597 & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86b10000 }
78598 },
78599/* adcf.w $Dst32RnUnprefixedHI */
78600 {
78601 { 0, 0, 0, 0 },
78602 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
78603 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb91e }
78604 },
78605/* adcf.w $Dst32AnUnprefixedHI */
78606 {
78607 { 0, 0, 0, 0 },
78608 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
78609 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb19e }
78610 },
78611/* adcf.w [$Dst32AnUnprefixed] */
78612 {
78613 { 0, 0, 0, 0 },
78614 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78615 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb11e }
78616 },
78617/* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78618 {
78619 { 0, 0, 0, 0 },
78620 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78621 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb31e00 }
78622 },
78623/* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78624 {
78625 { 0, 0, 0, 0 },
78626 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78627 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb51e0000 }
78628 },
78629/* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78630 {
78631 { 0, 0, 0, 0 },
78632 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78633 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb71e0000 }
78634 },
78635/* adcf.w ${Dsp-16-u8}[sb] */
78636 {
78637 { 0, 0, 0, 0 },
78638 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78639 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb39e00 }
78640 },
78641/* adcf.w ${Dsp-16-u16}[sb] */
78642 {
78643 { 0, 0, 0, 0 },
78644 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78645 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb59e0000 }
78646 },
78647/* adcf.w ${Dsp-16-s8}[fb] */
78648 {
78649 { 0, 0, 0, 0 },
78650 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78651 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3de00 }
78652 },
78653/* adcf.w ${Dsp-16-s16}[fb] */
78654 {
78655 { 0, 0, 0, 0 },
78656 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78657 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5de0000 }
78658 },
78659/* adcf.w ${Dsp-16-u16} */
78660 {
78661 { 0, 0, 0, 0 },
78662 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78663 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7de0000 }
78664 },
78665/* adcf.w ${Dsp-16-u24} */
78666 {
78667 { 0, 0, 0, 0 },
78668 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78669 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb79e0000 }
78670 },
78671/* adcf.b $Dst32RnUnprefixedQI */
78672 {
78673 { 0, 0, 0, 0 },
78674 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
78675 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb81e }
78676 },
78677/* adcf.b $Dst32AnUnprefixedQI */
78678 {
78679 { 0, 0, 0, 0 },
78680 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
78681 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb09e }
78682 },
78683/* adcf.b [$Dst32AnUnprefixed] */
78684 {
78685 { 0, 0, 0, 0 },
78686 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78687 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb01e }
78688 },
78689/* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78690 {
78691 { 0, 0, 0, 0 },
78692 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78693 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb21e00 }
78694 },
78695/* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78696 {
78697 { 0, 0, 0, 0 },
78698 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78699 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb41e0000 }
78700 },
78701/* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78702 {
78703 { 0, 0, 0, 0 },
78704 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78705 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb61e0000 }
78706 },
78707/* adcf.b ${Dsp-16-u8}[sb] */
78708 {
78709 { 0, 0, 0, 0 },
78710 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78711 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb29e00 }
78712 },
78713/* adcf.b ${Dsp-16-u16}[sb] */
78714 {
78715 { 0, 0, 0, 0 },
78716 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78717 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb49e0000 }
78718 },
78719/* adcf.b ${Dsp-16-s8}[fb] */
78720 {
78721 { 0, 0, 0, 0 },
78722 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78723 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2de00 }
78724 },
78725/* adcf.b ${Dsp-16-s16}[fb] */
78726 {
78727 { 0, 0, 0, 0 },
78728 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78729 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4de0000 }
78730 },
78731/* adcf.b ${Dsp-16-u16} */
78732 {
78733 { 0, 0, 0, 0 },
78734 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78735 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6de0000 }
78736 },
78737/* adcf.b ${Dsp-16-u24} */
78738 {
78739 { 0, 0, 0, 0 },
78740 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78741 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb69e0000 }
78742 },
78743/* adcf.w $Dst16RnHI */
78744 {
78745 { 0, 0, 0, 0 },
78746 { { MNEM, ' ', OP (DST16RNHI), 0 } },
78747 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77e0 }
78748 },
78749/* adcf.w $Dst16AnHI */
78750 {
78751 { 0, 0, 0, 0 },
78752 { { MNEM, ' ', OP (DST16ANHI), 0 } },
78753 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77e4 }
78754 },
78755/* adcf.w [$Dst16An] */
78756 {
78757 { 0, 0, 0, 0 },
78758 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78759 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77e6 }
78760 },
78761/* adcf.w ${Dsp-16-u8}[$Dst16An] */
78762 {
78763 { 0, 0, 0, 0 },
78764 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78765 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77e800 }
78766 },
78767/* adcf.w ${Dsp-16-u16}[$Dst16An] */
78768 {
78769 { 0, 0, 0, 0 },
78770 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78771 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ec0000 }
78772 },
78773/* adcf.w ${Dsp-16-u8}[sb] */
78774 {
78775 { 0, 0, 0, 0 },
78776 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78777 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ea00 }
78778 },
78779/* adcf.w ${Dsp-16-u16}[sb] */
78780 {
78781 { 0, 0, 0, 0 },
78782 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78783 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ee0000 }
78784 },
78785/* adcf.w ${Dsp-16-s8}[fb] */
78786 {
78787 { 0, 0, 0, 0 },
78788 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78789 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77eb00 }
78790 },
78791/* adcf.w ${Dsp-16-u16} */
78792 {
78793 { 0, 0, 0, 0 },
78794 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78795 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ef0000 }
78796 },
78797/* adcf.b $Dst16RnQI */
78798 {
78799 { 0, 0, 0, 0 },
78800 { { MNEM, ' ', OP (DST16RNQI), 0 } },
78801 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76e0 }
78802 },
78803/* adcf.b $Dst16AnQI */
78804 {
78805 { 0, 0, 0, 0 },
78806 { { MNEM, ' ', OP (DST16ANQI), 0 } },
78807 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76e4 }
78808 },
78809/* adcf.b [$Dst16An] */
78810 {
78811 { 0, 0, 0, 0 },
78812 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78813 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76e6 }
78814 },
78815/* adcf.b ${Dsp-16-u8}[$Dst16An] */
78816 {
78817 { 0, 0, 0, 0 },
78818 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78819 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76e800 }
78820 },
78821/* adcf.b ${Dsp-16-u16}[$Dst16An] */
78822 {
78823 { 0, 0, 0, 0 },
78824 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78825 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ec0000 }
78826 },
78827/* adcf.b ${Dsp-16-u8}[sb] */
78828 {
78829 { 0, 0, 0, 0 },
78830 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78831 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ea00 }
78832 },
78833/* adcf.b ${Dsp-16-u16}[sb] */
78834 {
78835 { 0, 0, 0, 0 },
78836 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78837 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ee0000 }
78838 },
78839/* adcf.b ${Dsp-16-s8}[fb] */
78840 {
78841 { 0, 0, 0, 0 },
78842 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78843 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76eb00 }
78844 },
78845/* adcf.b ${Dsp-16-u16} */
78846 {
78847 { 0, 0, 0, 0 },
78848 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78849 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ef0000 }
78850 },
78851/* abs.w $Dst32RnUnprefixedHI */
78852 {
78853 { 0, 0, 0, 0 },
78854 { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
78855 & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91f }
78856 },
78857/* abs.w $Dst32AnUnprefixedHI */
78858 {
78859 { 0, 0, 0, 0 },
78860 { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
78861 & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19f }
78862 },
78863/* abs.w [$Dst32AnUnprefixed] */
78864 {
78865 { 0, 0, 0, 0 },
78866 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78867 & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11f }
78868 },
78869/* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78870 {
78871 { 0, 0, 0, 0 },
78872 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78873 & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31f00 }
78874 },
78875/* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78876 {
78877 { 0, 0, 0, 0 },
78878 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78879 & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51f0000 }
78880 },
78881/* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78882 {
78883 { 0, 0, 0, 0 },
78884 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78885 & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71f0000 }
78886 },
78887/* abs.w ${Dsp-16-u8}[sb] */
78888 {
78889 { 0, 0, 0, 0 },
78890 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78891 & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39f00 }
78892 },
78893/* abs.w ${Dsp-16-u16}[sb] */
78894 {
78895 { 0, 0, 0, 0 },
78896 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78897 & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59f0000 }
78898 },
78899/* abs.w ${Dsp-16-s8}[fb] */
78900 {
78901 { 0, 0, 0, 0 },
78902 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78903 & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3df00 }
78904 },
78905/* abs.w ${Dsp-16-s16}[fb] */
78906 {
78907 { 0, 0, 0, 0 },
78908 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78909 & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5df0000 }
78910 },
78911/* abs.w ${Dsp-16-u16} */
78912 {
78913 { 0, 0, 0, 0 },
78914 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78915 & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7df0000 }
78916 },
78917/* abs.w ${Dsp-16-u24} */
78918 {
78919 { 0, 0, 0, 0 },
78920 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78921 & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79f0000 }
78922 },
78923/* abs.b $Dst32RnUnprefixedQI */
78924 {
78925 { 0, 0, 0, 0 },
78926 { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
78927 & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81f }
78928 },
78929/* abs.b $Dst32AnUnprefixedQI */
78930 {
78931 { 0, 0, 0, 0 },
78932 { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
78933 & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09f }
78934 },
78935/* abs.b [$Dst32AnUnprefixed] */
78936 {
78937 { 0, 0, 0, 0 },
78938 { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78939 & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01f }
78940 },
78941/* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78942 {
78943 { 0, 0, 0, 0 },
78944 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78945 & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21f00 }
78946 },
78947/* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78948 {
78949 { 0, 0, 0, 0 },
78950 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78951 & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41f0000 }
78952 },
78953/* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78954 {
78955 { 0, 0, 0, 0 },
78956 { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78957 & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61f0000 }
78958 },
78959/* abs.b ${Dsp-16-u8}[sb] */
78960 {
78961 { 0, 0, 0, 0 },
78962 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78963 & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29f00 }
78964 },
78965/* abs.b ${Dsp-16-u16}[sb] */
78966 {
78967 { 0, 0, 0, 0 },
78968 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78969 & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49f0000 }
78970 },
78971/* abs.b ${Dsp-16-s8}[fb] */
78972 {
78973 { 0, 0, 0, 0 },
78974 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78975 & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2df00 }
78976 },
78977/* abs.b ${Dsp-16-s16}[fb] */
78978 {
78979 { 0, 0, 0, 0 },
78980 { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78981 & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4df0000 }
78982 },
78983/* abs.b ${Dsp-16-u16} */
78984 {
78985 { 0, 0, 0, 0 },
78986 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78987 & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6df0000 }
78988 },
78989/* abs.b ${Dsp-16-u24} */
78990 {
78991 { 0, 0, 0, 0 },
78992 { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78993 & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69f0000 }
78994 },
78995/* abs.w $Dst16RnHI */
78996 {
78997 { 0, 0, 0, 0 },
78998 { { MNEM, ' ', OP (DST16RNHI), 0 } },
78999 & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77f0 }
79000 },
79001/* abs.w $Dst16AnHI */
79002 {
79003 { 0, 0, 0, 0 },
79004 { { MNEM, ' ', OP (DST16ANHI), 0 } },
79005 & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77f4 }
79006 },
79007/* abs.w [$Dst16An] */
79008 {
79009 { 0, 0, 0, 0 },
79010 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
79011 & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77f6 }
79012 },
79013/* abs.w ${Dsp-16-u8}[$Dst16An] */
79014 {
79015 { 0, 0, 0, 0 },
79016 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
79017 & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77f800 }
79018 },
79019/* abs.w ${Dsp-16-u16}[$Dst16An] */
79020 {
79021 { 0, 0, 0, 0 },
79022 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
79023 & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77fc0000 }
79024 },
79025/* abs.w ${Dsp-16-u8}[sb] */
79026 {
79027 { 0, 0, 0, 0 },
79028 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
79029 & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77fa00 }
79030 },
79031/* abs.w ${Dsp-16-u16}[sb] */
79032 {
79033 { 0, 0, 0, 0 },
79034 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
79035 & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77fe0000 }
79036 },
79037/* abs.w ${Dsp-16-s8}[fb] */
79038 {
79039 { 0, 0, 0, 0 },
79040 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
79041 & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77fb00 }
79042 },
79043/* abs.w ${Dsp-16-u16} */
79044 {
79045 { 0, 0, 0, 0 },
79046 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
79047 & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ff0000 }
79048 },
79049/* abs.b $Dst16RnQI */
79050 {
79051 { 0, 0, 0, 0 },
79052 { { MNEM, ' ', OP (DST16RNQI), 0 } },
79053 & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76f0 }
79054 },
79055/* abs.b $Dst16AnQI */
79056 {
79057 { 0, 0, 0, 0 },
79058 { { MNEM, ' ', OP (DST16ANQI), 0 } },
79059 & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76f4 }
79060 },
79061/* abs.b [$Dst16An] */
79062 {
79063 { 0, 0, 0, 0 },
79064 { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
79065 & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76f6 }
79066 },
79067/* abs.b ${Dsp-16-u8}[$Dst16An] */
79068 {
79069 { 0, 0, 0, 0 },
79070 { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
79071 & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76f800 }
79072 },
79073/* abs.b ${Dsp-16-u16}[$Dst16An] */
79074 {
79075 { 0, 0, 0, 0 },
79076 { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
79077 & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76fc0000 }
79078 },
79079/* abs.b ${Dsp-16-u8}[sb] */
79080 {
79081 { 0, 0, 0, 0 },
79082 { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
79083 & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76fa00 }
79084 },
79085/* abs.b ${Dsp-16-u16}[sb] */
79086 {
79087 { 0, 0, 0, 0 },
79088 { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
79089 & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76fe0000 }
79090 },
79091/* abs.b ${Dsp-16-s8}[fb] */
79092 {
79093 { 0, 0, 0, 0 },
79094 { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
79095 & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76fb00 }
79096 },
79097/* abs.b ${Dsp-16-u16} */
79098 {
79099 { 0, 0, 0, 0 },
79100 { { MNEM, ' ', OP (DSP_16_U16), 0 } },
79101 & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 }
79102 },
92e0a941 79103/* add.w$Q #${Imm-12-s4},sp */
49f58d10
JB		 79104 {
79105 { 0, 0, 0, 0 },
92e0a941
DD		 79106 { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
79107 & ifmt_add16_wQ_sp, { 0x7db0 }
49f58d10
JB		 79108 },
79109/* add.b$G #${Imm-16-QI},sp */
79110 {
79111 { 0, 0, 0, 0 },
79112 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } },
79113 & ifmt_add16_b_G_sp, { 0x7ceb00 }
79114 },
79115/* add.w$G #${Imm-16-HI},sp */
79116 {
79117 { 0, 0, 0, 0 },
79118 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } },
79119 & ifmt_add16_w_G_sp, { 0x7deb0000 }
79120 },
79121/* add.l$Q #${Imm3-S},sp */
79122 {
79123 { 0, 0, 0, 0 },
79124 { { MNEM, OP (Q), ' ', '#', OP (IMM3_S), ',', 's', 'p', 0 } },
79125 & ifmt_add32_l_imm3_Q, { 0x42 }
79126 },
79127/* add.l$S #${Imm-16-QI},sp */
79128 {
79129 { 0, 0, 0, 0 },
79130 { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } },
79131 & ifmt_add32_l_imm8_S, { 0xb60300 }
79132 },
79133/* add.l$G #${Imm-16-HI},sp */
79134 {
79135 { 0, 0, 0, 0 },
79136 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } },
79137 & ifmt_add32_l_imm16_G, { 0xb6130000 }
79138 },
5348b81e 79139/* dadc.b #${Imm-16-QI},r0l */
49f58d10
JB		 79140 {
79141 { 0, 0, 0, 0 },
5348b81e 79142 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
49f58d10
JB		 79143 & ifmt_add32_l_imm8_S, { 0x7cee00 }
79144 },
5348b81e 79145/* dadc.w #${Imm-16-HI},r0 */
49f58d10
JB		 79146 {
79147 { 0, 0, 0, 0 },
5348b81e 79148 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
49f58d10
JB		 79149 & ifmt_add32_l_imm16_G, { 0x7dee0000 }
79150 },
79151/* dadc.b r0h,r0l */
79152 {
79153 { 0, 0, 0, 0 },
79154 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79155 & ifmt_dadc16_b_r0h_r0l, { 0x7ce6 }
79156 },
79157/* dadc.w r1,r0 */
79158 {
79159 { 0, 0, 0, 0 },
79160 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79161 & ifmt_dadc16_b_r0h_r0l, { 0x7de6 }
79162 },
5348b81e 79163/* dadd.b #${Imm-16-QI},r0l */
49f58d10
JB		 79164 {
79165 { 0, 0, 0, 0 },
5348b81e 79166 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
49f58d10
JB		 79167 & ifmt_add32_l_imm8_S, { 0x7cec00 }
79168 },
5348b81e 79169/* dadd.w #${Imm-16-HI},r0 */
49f58d10
JB		 79170 {
79171 { 0, 0, 0, 0 },
5348b81e 79172 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
49f58d10
JB		 79173 & ifmt_add32_l_imm16_G, { 0x7dec0000 }
79174 },
79175/* dadd.b r0h,r0l */
79176 {
79177 { 0, 0, 0, 0 },
79178 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79179 & ifmt_dadc16_b_r0h_r0l, { 0x7ce4 }
79180 },
79181/* dadd.w r1,r0 */
79182 {
79183 { 0, 0, 0, 0 },
79184 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79185 & ifmt_dadc16_b_r0h_r0l, { 0x7de4 }
79186 },
79187/* bm$cond16c c */
79188 {
79189 { 0, 0, 0, 0 },
79190 { { MNEM, OP (COND16C), ' ', 'c', 0 } },
79191 & ifmt_bm16_c, { 0x7dd0 }
79192 },
79193/* bm$cond32 c */
79194 {
79195 { 0, 0, 0, 0 },
79196 { { MNEM, OP (COND32), ' ', 'c', 0 } },
79197 & ifmt_bm32_c, { 0xd928 }
79198 },
79199/* brk */
79200 {
79201 { 0, 0, 0, 0 },
79202 { { MNEM, 0 } },
79203 & ifmt_brk16, { 0x0 }
79204 },
79205/* brk */
79206 {
79207 { 0, 0, 0, 0 },
79208 { { MNEM, 0 } },
79209 & ifmt_brk16, { 0x0 }
79210 },
79211/* brk2 */
79212 {
79213 { 0, 0, 0, 0 },
79214 { { MNEM, 0 } },
79215 & ifmt_brk16, { 0x8 }
79216 },
5398310a
DD		 79217/* btst:s ${Bit3-S},${Dsp-8-u16} */
79218 {
79219 { 0, 0, 0, 0 },
79220 { { MNEM, ' ', OP (BIT3_S), ',', OP (DSP_8_U16), 0 } },
79221 & ifmt_btst_s, { 0xa0000 }
79222 },
49f58d10
JB		 79223/* dec.w ${Dst16An-S} */
79224 {
79225 { 0, 0, 0, 0 },
79226 { { MNEM, ' ', OP (DST16AN_S), 0 } },
79227 & ifmt_dec16_w, { 0xf2 }
79228 },
79229/* div.b #${Imm-16-QI} */
79230 {
79231 { 0, 0, 0, 0 },
79232 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79233 & ifmt_add16_b_G_sp, { 0x7ce100 }
79234 },
79235/* div.w #${Imm-16-HI} */
79236 {
79237 { 0, 0, 0, 0 },
79238 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79239 & ifmt_add16_w_G_sp, { 0x7de10000 }
79240 },
79241/* div.b #${Imm-16-QI} */
79242 {
79243 { 0, 0, 0, 0 },
79244 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79245 & ifmt_div32_b_Imm_16_QI, { 0xb04300 }
79246 },
79247/* div.w #${Imm-16-HI} */
79248 {
79249 { 0, 0, 0, 0 },
79250 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79251 & ifmt_div32_w_Imm_16_HI, { 0xb0530000 }
79252 },
79253/* divu.b #${Imm-16-QI} */
79254 {
79255 { 0, 0, 0, 0 },
79256 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79257 & ifmt_add16_b_G_sp, { 0x7ce000 }
79258 },
79259/* divu.w #${Imm-16-HI} */
79260 {
79261 { 0, 0, 0, 0 },
79262 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79263 & ifmt_add16_w_G_sp, { 0x7de00000 }
79264 },
79265/* divu.b #${Imm-16-QI} */
79266 {
79267 { 0, 0, 0, 0 },
79268 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79269 & ifmt_div32_b_Imm_16_QI, { 0xb00300 }
79270 },
79271/* divu.w #${Imm-16-HI} */
79272 {
79273 { 0, 0, 0, 0 },
79274 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79275 & ifmt_div32_w_Imm_16_HI, { 0xb0130000 }
79276 },
79277/* divx.b #${Imm-16-QI} */
79278 {
79279 { 0, 0, 0, 0 },
79280 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79281 & ifmt_add16_b_G_sp, { 0x7ce300 }
79282 },
79283/* divx.w #${Imm-16-HI} */
79284 {
79285 { 0, 0, 0, 0 },
79286 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79287 & ifmt_add16_w_G_sp, { 0x7de30000 }
79288 },
79289/* divx.b #${Imm-16-QI} */
79290 {
79291 { 0, 0, 0, 0 },
79292 { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79293 & ifmt_div32_b_Imm_16_QI, { 0xb24300 }
79294 },
79295/* divx.w #${Imm-16-HI} */
79296 {
79297 { 0, 0, 0, 0 },
79298 { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79299 & ifmt_div32_w_Imm_16_HI, { 0xb2530000 }
79300 },
5348b81e 79301/* dsbb.b #${Imm-16-QI},r0l */
49f58d10
JB		 79302 {
79303 { 0, 0, 0, 0 },
5348b81e 79304 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
49f58d10
JB		 79305 & ifmt_add32_l_imm8_S, { 0x7cef00 }
79306 },
5348b81e 79307/* dsbb.w #${Imm-16-HI},r0 */
49f58d10
JB		 79308 {
79309 { 0, 0, 0, 0 },
5348b81e 79310 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
49f58d10
JB		 79311 & ifmt_add32_l_imm16_G, { 0x7def0000 }
79312 },
79313/* dsbb.b r0h,r0l */
79314 {
79315 { 0, 0, 0, 0 },
79316 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79317 & ifmt_dadc16_b_r0h_r0l, { 0x7ce7 }
79318 },
79319/* dsbb.w r1,r0 */
79320 {
79321 { 0, 0, 0, 0 },
79322 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79323 & ifmt_dadc16_b_r0h_r0l, { 0x7de7 }
79324 },
5348b81e 79325/* dsub.b #${Imm-16-QI},r0l */
49f58d10
JB		 79326 {
79327 { 0, 0, 0, 0 },
5348b81e 79328 { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
49f58d10
JB		 79329 & ifmt_add32_l_imm8_S, { 0x7ced00 }
79330 },
5348b81e 79331/* dsub.w #${Imm-16-HI},r0 */
49f58d10
JB		 79332 {
79333 { 0, 0, 0, 0 },
5348b81e 79334 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
49f58d10
JB		 79335 & ifmt_add32_l_imm16_G, { 0x7ded0000 }
79336 },
79337/* dsub.b r0h,r0l */
79338 {
79339 { 0, 0, 0, 0 },
79340 { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79341 & ifmt_dadc16_b_r0h_r0l, { 0x7ce5 }
79342 },
79343/* dsub.w r1,r0 */
79344 {
79345 { 0, 0, 0, 0 },
79346 { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79347 & ifmt_dadc16_b_r0h_r0l, { 0x7de5 }
79348 },
79349/* enter #${Dsp-16-u8} */
79350 {
79351 { 0, 0, 0, 0 },
79352 { { MNEM, ' ', '#', OP (DSP_16_U8), 0 } },
79353 & ifmt_enter16, { 0x7cf200 }
79354 },
79355/* exitd */
79356 {
79357 { 0, 0, 0, 0 },
79358 { { MNEM, 0 } },
79359 & ifmt_dadc16_b_r0h_r0l, { 0x7df2 }
79360 },
79361/* enter #${Dsp-8-u8} */
79362 {
79363 { 0, 0, 0, 0 },
79364 { { MNEM, ' ', '#', OP (DSP_8_U8), 0 } },
79365 & ifmt_enter32, { 0xec00 }
79366 },
79367/* exitd */
79368 {
79369 { 0, 0, 0, 0 },
79370 { { MNEM, 0 } },
79371 & ifmt_brk16, { 0xfc }
79372 },
79373/* fclr ${flags16} */
79374 {
79375 { 0, 0, 0, 0 },
79376 { { MNEM, ' ', OP (FLAGS16), 0 } },
79377 & ifmt_fclr16, { 0xeb05 }
79378 },
79379/* fset ${flags16} */
79380 {
79381 { 0, 0, 0, 0 },
79382 { { MNEM, ' ', OP (FLAGS16), 0 } },
79383 & ifmt_fclr16, { 0xeb04 }
79384 },
79385/* fclr ${flags32} */
79386 {
79387 { 0, 0, 0, 0 },
79388 { { MNEM, ' ', OP (FLAGS32), 0 } },
79389 & ifmt_fclr, { 0xd3e8 }
79390 },
79391/* fset ${flags32} */
79392 {
79393 { 0, 0, 0, 0 },
79394 { { MNEM, ' ', OP (FLAGS32), 0 } },
79395 & ifmt_fclr, { 0xd1e8 }
79396 },
79397/* inc.w ${Dst16An-S} */
79398 {
79399 { 0, 0, 0, 0 },
79400 { { MNEM, ' ', OP (DST16AN_S), 0 } },
79401 & ifmt_dec16_w, { 0xb2 }
79402 },
79403/* freit */
79404 {
79405 { 0, 0, 0, 0 },
79406 { { MNEM, 0 } },
79407 & ifmt_brk16, { 0x9f }
79408 },
79409/* int #${Dsp-10-u6} */
79410 {
79411 { 0, 0, 0, 0 },
79412 { { MNEM, ' ', '#', OP (DSP_10_U6), 0 } },
79413 & ifmt_int16, { 0xebc0 }
79414 },
79415/* into */
79416 {
79417 { 0, 0, 0, 0 },
79418 { { MNEM, 0 } },
79419 & ifmt_brk16, { 0xf6 }
79420 },
79421/* int #${Dsp-8-u6} */
79422 {
79423 { 0, 0, 0, 0 },
79424 { { MNEM, ' ', '#', OP (DSP_8_U6), 0 } },
79425 & ifmt_int32, { 0xbe00 }
79426 },
79427/* into */
79428 {
79429 { 0, 0, 0, 0 },
79430 { { MNEM, 0 } },
79431 & ifmt_brk16, { 0xbf }
79432 },
79433/* j$cond16j5 ${Lab-8-8} */
79434 {
79435 { 0, 0, 0, 0 },
79436 { { MNEM, OP (COND16J5), ' ', OP (LAB_8_8), 0 } },
79437 & ifmt_jcnd16_5, { 0x6800 }
79438 },
79439/* j$cond16j ${Lab-16-8} */
79440 {
79441 { 0, 0, 0, 0 },
79442 { { MNEM, OP (COND16J), ' ', OP (LAB_16_8), 0 } },
79443 & ifmt_jcnd16, { 0x7dc000 }
79444 },
79445/* j$cond32j ${Lab-8-8} */
79446 {
79447 { 0, 0, 0, 0 },
79448 { { MNEM, OP (COND32J), ' ', OP (LAB_8_8), 0 } },
79449 & ifmt_jcnd32, { 0x8a00 }
79450 },
79451/* jmp.s ${Lab-5-3} */
79452 {
79453 { 0, 0, 0, 0 },
79454 { { MNEM, ' ', OP (LAB_5_3), 0 } },
79455 & ifmt_jmp16_s, { 0x60 }
79456 },
79457/* jmp.b ${Lab-8-8} */
79458 {
79459 { 0, 0, 0, 0 },
79460 { { MNEM, ' ', OP (LAB_8_8), 0 } },
79461 & ifmt_jmp16_b, { 0xfe00 }
79462 },
79463/* jmp.w ${Lab-8-16} */
79464 {
79465 { 0, 0, 0, 0 },
79466 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79467 & ifmt_jmp16_w, { 0xf40000 }
79468 },
79469/* jmp.a ${Lab-8-24} */
79470 {
79471 { 0, 0, 0, 0 },
79472 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79473 & ifmt_jmp16_a, { 0xfc000000 }
79474 },
79475/* jmps #${Imm-8-QI} */
79476 {
79477 { 0, 0, 0, 0 },
79478 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79479 & ifmt_jmps16, { 0xee00 }
79480 },
79481/* jmp.s ${Lab32-jmp-s} */
79482 {
79483 { 0, 0, 0, 0 },
79484 { { MNEM, ' ', OP (LAB32_JMP_S), 0 } },
79485 & ifmt_jmp32_s, { 0x4a }
79486 },
79487/* jmp.b ${Lab-8-8} */
79488 {
79489 { 0, 0, 0, 0 },
79490 { { MNEM, ' ', OP (LAB_8_8), 0 } },
79491 & ifmt_jmp16_b, { 0xbb00 }
79492 },
79493/* jmp.w ${Lab-8-16} */
79494 {
79495 { 0, 0, 0, 0 },
79496 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79497 & ifmt_jmp16_w, { 0xce0000 }
79498 },
79499/* jmp.a ${Lab-8-24} */
79500 {
79501 { 0, 0, 0, 0 },
79502 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79503 & ifmt_jmp16_a, { 0xcc000000 }
79504 },
79505/* jmps #${Imm-8-QI} */
79506 {
79507 { 0, 0, 0, 0 },
79508 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79509 & ifmt_jmps16, { 0xdc00 }
79510 },
79511/* jsr.w ${Lab-8-16} */
79512 {
79513 { 0, 0, 0, 0 },
79514 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79515 & ifmt_jmp16_w, { 0xf50000 }
79516 },
79517/* jsr.a ${Lab-8-24} */
79518 {
79519 { 0, 0, 0, 0 },
79520 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79521 & ifmt_jmp16_a, { 0xfd000000 }
79522 },
79523/* jsr.w ${Lab-8-16} */
79524 {
79525 { 0, 0, 0, 0 },
79526 { { MNEM, ' ', OP (LAB_8_16), 0 } },
79527 & ifmt_jmp16_w, { 0xcf0000 }
79528 },
79529/* jsr.a ${Lab-8-24} */
79530 {
79531 { 0, 0, 0, 0 },
79532 { { MNEM, ' ', OP (LAB_8_24), 0 } },
79533 & ifmt_jmp16_a, { 0xcd000000 }
79534 },
79535/* jsrs #${Imm-8-QI} */
79536 {
79537 { 0, 0, 0, 0 },
79538 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79539 & ifmt_jmps16, { 0xef00 }
79540 },
79541/* jsrs #${Imm-8-QI} */
79542 {
79543 { 0, 0, 0, 0 },
79544 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79545 & ifmt_jmps16, { 0xdd00 }
79546 },
79547/* ldc #${Imm-16-HI},${cr16} */
79548 {
79549 { 0, 0, 0, 0 },
79550 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR16), 0 } },
79551 & ifmt_ldc16_imm16, { 0xeb000000 }
79552 },
79553/* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
79554 {
79555 { 0, 0, 0, 0 },
79556 { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR1_UNPREFIXED_32), 0 } },
79557 & ifmt_ldc32_imm16_cr1, { 0xd5a80000 }
79558 },
79559/* ldc #${Dsp-16-u24},${cr2-32} */
79560 {
79561 { 0, 0, 0, 0 },
79562 { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR2_32), 0 } },
79563 & ifmt_ldc32_imm16_cr2, { 0xd5280000 }
79564 },
79565/* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
79566 {
79567 { 0, 0, 0, 0 },
79568 { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR3_UNPREFIXED_32), 0 } },
79569 & ifmt_ldc32_imm16_cr3, { 0xd5680000 }
79570 },
79571/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
79572 {
79573 { 0, 0, 0, 0 },
79574 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79575 & ifmt_ldctx16, { 0x7cf00000 }
79576 },
79577/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
79578 {
79579 { 0, 0, 0, 0 },
79580 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79581 & ifmt_ldctx16, { 0xb6c30000 }
79582 },
79583/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
79584 {
79585 { 0, 0, 0, 0 },
79586 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79587 & ifmt_ldctx16, { 0x7df00000 }
79588 },
79589/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
79590 {
79591 { 0, 0, 0, 0 },
79592 { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79593 & ifmt_ldctx16, { 0xb6d30000 }
79594 },
79595/* ldipl #${Imm-13-u3} */
79596 {
79597 { 0, 0, 0, 0 },
79598 { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } },
79599 & ifmt_ldipl16_imm, { 0x7da0 }
79600 },
79601/* ldipl #${Imm-13-u3} */
79602 {
79603 { 0, 0, 0, 0 },
79604 { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } },
79605 & ifmt_ldipl16_imm, { 0xd5e8 }
79606 },
79607/* mov.b$S #${Imm-8-QI},a0 */
79608 {
79609 { 0, 0, 0, 0 },
79610 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '0', 0 } },
79611 & ifmt_jmps16, { 0xe200 }
79612 },
79613/* mov.b$S #${Imm-8-QI},a1 */
79614 {
79615 { 0, 0, 0, 0 },
79616 { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '1', 0 } },
79617 & ifmt_jmps16, { 0xea00 }
79618 },
79619/* mov.w$S #${Imm-8-HI},a0 */
79620 {
79621 { 0, 0, 0, 0 },
79622 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } },
79623 & ifmt_mov16_w_S_imm_a0, { 0xa20000 }
79624 },
79625/* mov.w$S #${Imm-8-HI},a1 */
79626 {
79627 { 0, 0, 0, 0 },
79628 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
79629 & ifmt_mov16_w_S_imm_a0, { 0xaa0000 }
79630 },
79631/* mov.w$S #${Imm-8-HI},a0 */
79632 {
79633 { 0, 0, 0, 0 },
79634 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } },
79635 & ifmt_mov16_w_S_imm_a0, { 0x9c0000 }
79636 },
79637/* mov.w$S #${Imm-8-HI},a1 */
79638 {
79639 { 0, 0, 0, 0 },
79640 { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
79641 & ifmt_mov16_w_S_imm_a0, { 0x9d0000 }
79642 },
f75eb1c0 79643/* mov.l$S #${Dsp-8-s24},a0 */
49f58d10
JB		 79644 {
79645 { 0, 0, 0, 0 },
f75eb1c0 79646 { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '0', 0 } },
49f58d10
JB		 79647 & ifmt_mov32_l_a0, { 0xbc000000 }
79648 },
f75eb1c0 79649/* mov.l$S #${Dsp-8-s24},a1 */
49f58d10
JB		 79650 {
79651 { 0, 0, 0, 0 },
f75eb1c0 79652 { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '1', 0 } },
49f58d10
JB		 79653 & ifmt_mov32_l_a0, { 0xbd000000 }
79654 },
79655/* mov.b$S r0l,a1 */
79656 {
79657 { 0, 0, 0, 0 },
79658 { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'a', '1', 0 } },
79659 & ifmt_brk16, { 0x34 }
79660 },
79661/* mov.b$S r0h,a0 */
79662 {
79663 { 0, 0, 0, 0 },
79664 { { MNEM, OP (S), ' ', 'r', '0', 'h', ',', 'a', '0', 0 } },
79665 & ifmt_brk16, { 0x30 }
79666 },
79667/* nop */
79668 {
79669 { 0, 0, 0, 0 },
79670 { { MNEM, 0 } },
79671 & ifmt_brk16, { 0x4 }
79672 },
79673/* nop */
79674 {
79675 { 0, 0, 0, 0 },
79676 { { MNEM, 0 } },
79677 & ifmt_brk16, { 0xde }
79678 },
79679/* popc ${cr16} */
79680 {
79681 { 0, 0, 0, 0 },
79682 { { MNEM, ' ', OP (CR16), 0 } },
79683 & ifmt_popc16_imm16, { 0xeb03 }
79684 },
79685/* popc ${cr1-Unprefixed-32} */
79686 {
79687 { 0, 0, 0, 0 },
79688 { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } },
79689 & ifmt_popc32_imm16_cr1, { 0xd3a8 }
79690 },
79691/* popc ${cr2-32} */
79692 {
79693 { 0, 0, 0, 0 },
79694 { { MNEM, ' ', OP (CR2_32), 0 } },
79695 & ifmt_popc32_imm16_cr2, { 0xd328 }
79696 },
79697/* pushc ${cr16} */
79698 {
79699 { 0, 0, 0, 0 },
79700 { { MNEM, ' ', OP (CR16), 0 } },
79701 & ifmt_popc16_imm16, { 0xeb02 }
79702 },
79703/* pushc ${cr1-Unprefixed-32} */
79704 {
79705 { 0, 0, 0, 0 },
79706 { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } },
79707 & ifmt_popc32_imm16_cr1, { 0xd1a8 }
79708 },
79709/* pushc ${cr2-32} */
79710 {
79711 { 0, 0, 0, 0 },
79712 { { MNEM, ' ', OP (CR2_32), 0 } },
79713 & ifmt_popc32_imm16_cr2, { 0xd128 }
79714 },
79715/* popm ${Regsetpop} */
79716 {
79717 { 0, 0, 0, 0 },
79718 { { MNEM, ' ', OP (REGSETPOP), 0 } },
79719 & ifmt_popm16, { 0xed00 }
79720 },
79721/* pushm ${Regsetpush} */
79722 {
79723 { 0, 0, 0, 0 },
79724 { { MNEM, ' ', OP (REGSETPUSH), 0 } },
79725 & ifmt_pushm16, { 0xec00 }
79726 },
79727/* popm ${Regsetpop} */
79728 {
79729 { 0, 0, 0, 0 },
79730 { { MNEM, ' ', OP (REGSETPOP), 0 } },
79731 & ifmt_popm16, { 0x8e00 }
79732 },
79733/* pushm ${Regsetpush} */
79734 {
79735 { 0, 0, 0, 0 },
79736 { { MNEM, ' ', OP (REGSETPUSH), 0 } },
79737 & ifmt_pushm16, { 0x8f00 }
79738 },
79739/* push.b$G #${Imm-16-QI} */
79740 {
79741 { 0, 0, 0, 0 },
79742 { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), 0 } },
79743 & ifmt_add32_l_imm8_S, { 0x7ce200 }
79744 },
79745/* push.w$G #${Imm-16-HI} */
79746 {
79747 { 0, 0, 0, 0 },
79748 { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), 0 } },
79749 & ifmt_add32_l_imm16_G, { 0x7de20000 }
79750 },
5348b81e 79751/* push.b #${Imm-8-QI} */
49f58d10
JB		 79752 {
79753 { 0, 0, 0, 0 },
5348b81e 79754 { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
49f58d10
JB		 79755 & ifmt_jmps16, { 0xae00 }
79756 },
79757/* push.w #${Imm-8-HI} */
79758 {
79759 { 0, 0, 0, 0 },
79760 { { MNEM, ' ', '#', OP (IMM_8_HI), 0 } },
79761 & ifmt_mov16_w_S_imm_a0, { 0xaf0000 }
79762 },
79763/* push.l #${Imm-16-SI} */
79764 {
79765 { 0, 0, 0, 0 },
79766 { { MNEM, ' ', '#', OP (IMM_16_SI), 0 } },
79767 & ifmt_push32_l_imm, { 0xb6530000 }
79768 },
79769/* reit */
79770 {
79771 { 0, 0, 0, 0 },
79772 { { MNEM, 0 } },
79773 & ifmt_brk16, { 0xfb }
79774 },
79775/* reit */
79776 {
79777 { 0, 0, 0, 0 },
79778 { { MNEM, 0 } },
79779 & ifmt_brk16, { 0x9e }
79780 },
79781/* rmpa.b */
79782 {
79783 { 0, 0, 0, 0 },
79784 { { MNEM, 0 } },
79785 & ifmt_dadc16_b_r0h_r0l, { 0x7cf1 }
79786 },
79787/* rmpa.w */
79788 {
79789 { 0, 0, 0, 0 },
79790 { { MNEM, 0 } },
79791 & ifmt_dadc16_b_r0h_r0l, { 0x7df1 }
79792 },
79793/* rmpa.b */
79794 {
79795 { 0, 0, 0, 0 },
79796 { { MNEM, 0 } },
79797 & ifmt_dadc16_b_r0h_r0l, { 0xb843 }
79798 },
79799/* rmpa.w */
79800 {
79801 { 0, 0, 0, 0 },
79802 { { MNEM, 0 } },
79803 & ifmt_dadc16_b_r0h_r0l, { 0xb853 }
79804 },
79805/* rts */
79806 {
79807 { 0, 0, 0, 0 },
79808 { { MNEM, 0 } },
79809 & ifmt_brk16, { 0xf3 }
79810 },
79811/* rts */
79812 {
79813 { 0, 0, 0, 0 },
79814 { { MNEM, 0 } },
79815 & ifmt_brk16, { 0xdf }
79816 },
79817/* scmpu.b */
79818 {
79819 { 0, 0, 0, 0 },
79820 { { MNEM, 0 } },
79821 & ifmt_dadc16_b_r0h_r0l, { 0xb8c3 }
79822 },
79823/* scmpu.w */
79824 {
79825 { 0, 0, 0, 0 },
79826 { { MNEM, 0 } },
79827 & ifmt_dadc16_b_r0h_r0l, { 0xb8d3 }
79828 },
79829/* sha.l #${Imm-sh-12-s4},r2r0 */
79830 {
79831 { 0, 0, 0, 0 },
79832 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } },
79833 & ifmt_sha16_L_imm_r2r0, { 0xeba0 }
79834 },
79835/* sha.l #${Imm-sh-12-s4},r3r1 */
79836 {
79837 { 0, 0, 0, 0 },
79838 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } },
79839 & ifmt_sha16_L_imm_r2r0, { 0xebb0 }
79840 },
79841/* sha.l r1h,r2r0 */
79842 {
79843 { 0, 0, 0, 0 },
79844 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } },
79845 & ifmt_dadc16_b_r0h_r0l, { 0xeb21 }
79846 },
79847/* sha.l r1h,r3r1 */
79848 {
79849 { 0, 0, 0, 0 },
79850 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } },
79851 & ifmt_dadc16_b_r0h_r0l, { 0xeb31 }
79852 },
79853/* shl.l #${Imm-sh-12-s4},r2r0 */
79854 {
79855 { 0, 0, 0, 0 },
79856 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } },
79857 & ifmt_sha16_L_imm_r2r0, { 0xeb80 }
79858 },
79859/* shl.l #${Imm-sh-12-s4},r3r1 */
79860 {
79861 { 0, 0, 0, 0 },
79862 { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } },
79863 & ifmt_sha16_L_imm_r2r0, { 0xeb90 }
79864 },
79865/* shl.l r1h,r2r0 */
79866 {
79867 { 0, 0, 0, 0 },
79868 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } },
79869 & ifmt_dadc16_b_r0h_r0l, { 0xeb01 }
79870 },
79871/* shl.l r1h,r3r1 */
79872 {
79873 { 0, 0, 0, 0 },
79874 { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } },
79875 & ifmt_dadc16_b_r0h_r0l, { 0xeb11 }
79876 },
79877/* sin.b */
79878 {
79879 { 0, 0, 0, 0 },
79880 { { MNEM, 0 } },
79881 & ifmt_dadc16_b_r0h_r0l, { 0xb283 }
79882 },
79883/* sin.w */
79884 {
79885 { 0, 0, 0, 0 },
79886 { { MNEM, 0 } },
79887 & ifmt_dadc16_b_r0h_r0l, { 0xb293 }
79888 },
79889/* smovb.b */
79890 {
79891 { 0, 0, 0, 0 },
79892 { { MNEM, 0 } },
79893 & ifmt_dadc16_b_r0h_r0l, { 0x7ce9 }
79894 },
79895/* smovb.w */
79896 {
79897 { 0, 0, 0, 0 },
79898 { { MNEM, 0 } },
79899 & ifmt_dadc16_b_r0h_r0l, { 0x7de9 }
79900 },
79901/* smovb.b */
79902 {
79903 { 0, 0, 0, 0 },
79904 { { MNEM, 0 } },
79905 & ifmt_dadc16_b_r0h_r0l, { 0xb683 }
79906 },
79907/* smovb.w */
79908 {
79909 { 0, 0, 0, 0 },
79910 { { MNEM, 0 } },
79911 & ifmt_dadc16_b_r0h_r0l, { 0xb693 }
79912 },
79913/* smovf.b */
79914 {
79915 { 0, 0, 0, 0 },
79916 { { MNEM, 0 } },
79917 & ifmt_dadc16_b_r0h_r0l, { 0x7ce8 }
79918 },
79919/* smovf.w */
79920 {
79921 { 0, 0, 0, 0 },
79922 { { MNEM, 0 } },
79923 & ifmt_dadc16_b_r0h_r0l, { 0x7de8 }
79924 },
79925/* smovf.b */
79926 {
79927 { 0, 0, 0, 0 },
79928 { { MNEM, 0 } },
79929 & ifmt_dadc16_b_r0h_r0l, { 0xb083 }
79930 },
79931/* smovf.w */
79932 {
79933 { 0, 0, 0, 0 },
79934 { { MNEM, 0 } },
79935 & ifmt_dadc16_b_r0h_r0l, { 0xb093 }
79936 },
79937/* smovu.b */
79938 {
79939 { 0, 0, 0, 0 },
79940 { { MNEM, 0 } },
79941 & ifmt_dadc16_b_r0h_r0l, { 0xb883 }
79942 },
79943/* smovu.w */
79944 {
79945 { 0, 0, 0, 0 },
79946 { { MNEM, 0 } },
79947 & ifmt_dadc16_b_r0h_r0l, { 0xb893 }
79948 },
79949/* sout.b */
79950 {
79951 { 0, 0, 0, 0 },
79952 { { MNEM, 0 } },
79953 & ifmt_dadc16_b_r0h_r0l, { 0xb483 }
79954 },
79955/* sout.w */
79956 {
79957 { 0, 0, 0, 0 },
79958 { { MNEM, 0 } },
79959 & ifmt_dadc16_b_r0h_r0l, { 0xb493 }
79960 },
79961/* sstr.b */
79962 {
79963 { 0, 0, 0, 0 },
79964 { { MNEM, 0 } },
79965 & ifmt_dadc16_b_r0h_r0l, { 0x7cea }
79966 },
79967/* sstr.w */
79968 {
79969 { 0, 0, 0, 0 },
79970 { { MNEM, 0 } },
79971 & ifmt_dadc16_b_r0h_r0l, { 0x7dea }
79972 },
79973/* sstr.b */
79974 {
79975 { 0, 0, 0, 0 },
79976 { { MNEM, 0 } },
79977 & ifmt_dadc16_b_r0h_r0l, { 0xb803 }
79978 },
79979/* sstr.w */
79980 {
79981 { 0, 0, 0, 0 },
79982 { { MNEM, 0 } },
79983 & ifmt_dadc16_b_r0h_r0l, { 0xb813 }
79984 },
79985/* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
79986 {
79987 { 0, 0, 0, 0 },
79988 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'h', 0 } },
79989 & ifmt_stzx16_imm8_imm8_r0h, { 0xdb0000 }
79990 },
79991/* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
79992 {
79993 { 0, 0, 0, 0 },
79994 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
79995 & ifmt_stzx16_imm8_imm8_r0h, { 0xdc0000 }
79996 },
c6552317 79997/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 79998 {
79999 { 0, 0, 0, 0 },
c6552317 80000 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49f58d10
JB		 80001 & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xdd000000 }
80002 },
c6552317 80003/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 80004 {
80005 { 0, 0, 0, 0 },
c6552317
DD		 80006 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
80007 & ifmt_stzx16_imm8_imm8_dsp8fb, { 0xde000000 }
49f58d10 80008 },
c6552317 80009/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 80010 {
80011 { 0, 0, 0, 0 },
c6552317 80012 { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
75b06e7b 80013 & ifmt_stzx16_imm8_imm8_abs16, { 0xdf000000 }
49f58d10
JB		 80014 },
80015/* und */
80016 {
80017 { 0, 0, 0, 0 },
80018 { { MNEM, 0 } },
80019 & ifmt_brk16, { 0xff }
80020 },
80021/* und */
80022 {
80023 { 0, 0, 0, 0 },
80024 { { MNEM, 0 } },
80025 & ifmt_brk16, { 0xff }
80026 },
80027/* wait */
80028 {
80029 { 0, 0, 0, 0 },
80030 { { MNEM, 0 } },
80031 & ifmt_dadc16_b_r0h_r0l, { 0x7df3 }
80032 },
80033/* wait */
80034 {
80035 { 0, 0, 0, 0 },
80036 { { MNEM, 0 } },
80037 & ifmt_dadc16_b_r0h_r0l, { 0xb203 }
80038 },
80039/* exts.w r0 */
80040 {
80041 { 0, 0, 0, 0 },
80042 { { MNEM, ' ', 'r', '0', 0 } },
80043 & ifmt_dadc16_b_r0h_r0l, { 0x7cf3 }
80044 },
80045/* src-indirect */
80046 {
80047 { 0, 0, 0, 0 },
80048 { { MNEM, 0 } },
80049 & ifmt_brk16, { 0x41 }
80050 },
80051/* dest-indirect */
80052 {
80053 { 0, 0, 0, 0 },
80054 { { MNEM, 0 } },
80055 & ifmt_brk16, { 0x9 }
80056 },
80057/* src-dest-indirect */
80058 {
80059 { 0, 0, 0, 0 },
80060 { { MNEM, 0 } },
80061 & ifmt_brk16, { 0x49 }
80062 },
80063};
80064
80065#undef A
80066#undef OPERAND
80067#undef MNEM
80068#undef OP
80069
80070/* Formats for ALIAS macro-insns. */
80071
80072#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
80073#define F(f) & m32c_cgen_ifld_table[M32C_##f]
80074#else
80075#define F(f) & m32c_cgen_ifld_table[M32C_/**/f]
80076#endif
92e0a941
DD		 80077static const CGEN_IFMT ifmt_add16_bQ_sp ATTRIBUTE_UNUSED = {
80078 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
80079};
80080
49f58d10
JB		 80081#undef F
80082
80083/* Each non-simple macro entry points to an array of expansion possibilities. */
80084
80085#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
80086#define A(a) (1 << CGEN_INSN_##a)
80087#else
80088#define A(a) (1 << CGEN_INSN_/**/a)
80089#endif
80090#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
80091#define OPERAND(op) M32C_OPERAND_##op
80092#else
80093#define OPERAND(op) M32C_OPERAND_/**/op
80094#endif
80095#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
80096#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
80097
80098/* The macro instruction table. */
80099
80100static const CGEN_IBASE m32c_cgen_macro_insn_table[] =
80101{
92e0a941
DD		 80102/* add.b:q #${Imm-12-s4},sp */
80103 {
80104 -1, "add16-bQ-sp", "add.b:q", 16,
6772dd07 80105 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
92e0a941 80106 },
49f58d10
JB		 80107};
80108
80109/* The macro instruction opcode table. */
80110
80111static const CGEN_OPCODE m32c_cgen_macro_insn_opcode_table[] =
80112{
92e0a941
DD		 80113/* add.b:q #${Imm-12-s4},sp */
80114 {
80115 { 0, 0, 0, 0 },
80116 { { MNEM, ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
80117 & ifmt_add16_bQ_sp, { 0x7db0 }
80118 },
49f58d10
JB		 80119};
80120
80121#undef A
80122#undef OPERAND
80123#undef MNEM
80124#undef OP
80125
80126#ifndef CGEN_ASM_HASH_P
80127#define CGEN_ASM_HASH_P(insn) 1
80128#endif
80129
80130#ifndef CGEN_DIS_HASH_P
80131#define CGEN_DIS_HASH_P(insn) 1
80132#endif
80133
80134/* Return non-zero if INSN is to be added to the hash table.
80135 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
80136
80137static int
80138asm_hash_insn_p (insn)
80139 const CGEN_INSN *insn ATTRIBUTE_UNUSED;
80140{
80141 return CGEN_ASM_HASH_P (insn);
80142}
80143
80144static int
80145dis_hash_insn_p (insn)
80146 const CGEN_INSN *insn;
80147{
80148 /* If building the hash table and the NO-DIS attribute is present,
80149 ignore. */
80150 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
80151 return 0;
80152 return CGEN_DIS_HASH_P (insn);
80153}
80154
80155#ifndef CGEN_ASM_HASH
80156#define CGEN_ASM_HASH_SIZE 127
80157#ifdef CGEN_MNEMONIC_OPERANDS
80158#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
80159#else
80160#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
80161#endif
80162#endif
80163
80164/* It doesn't make much sense to provide a default here,
80165 but while this is under development we do.
80166 BUFFER is a pointer to the bytes of the insn, target order.
80167 VALUE is the first base_insn_bitsize bits as an int in host order. */
80168
80169#ifndef CGEN_DIS_HASH
80170#define CGEN_DIS_HASH_SIZE 256
80171#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
80172#endif
80173
80174/* The result is the hash value of the insn.
80175 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
80176
80177static unsigned int
80178asm_hash_insn (mnem)
80179 const char * mnem;
80180{
80181 return CGEN_ASM_HASH (mnem);
80182}
80183
80184/* BUF is a pointer to the bytes of the insn, target order.
80185 VALUE is the first base_insn_bitsize bits as an int in host order. */
80186
80187static unsigned int
80188dis_hash_insn (buf, value)
80189 const char * buf ATTRIBUTE_UNUSED;
80190 CGEN_INSN_INT value ATTRIBUTE_UNUSED;
80191{
80192 return CGEN_DIS_HASH (buf, value);
80193}
80194
49f58d10
JB		 80195/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
80196
80197static void
e729279b 80198set_fields_bitsize (CGEN_FIELDS *fields, int size)
49f58d10
JB		 80199{
80200 CGEN_FIELDS_BITSIZE (fields) = size;
80201}
80202
80203/* Function to call before using the operand instance table.
80204 This plugs the opcode entries and macro instructions into the cpu table. */
80205
80206void
e729279b 80207m32c_cgen_init_opcode_table (CGEN_CPU_DESC cd)
49f58d10
JB		 80208{
80209 int i;
80210 int num_macros = (sizeof (m32c_cgen_macro_insn_table) /
80211 sizeof (m32c_cgen_macro_insn_table[0]));
80212 const CGEN_IBASE *ib = & m32c_cgen_macro_insn_table[0];
80213 const CGEN_OPCODE *oc = & m32c_cgen_macro_insn_opcode_table[0];
e729279b
NC		 80214 CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
80215
49f58d10
JB		 80216 memset (insns, 0, num_macros * sizeof (CGEN_INSN));
80217 for (i = 0; i < num_macros; ++i)
80218 {
80219 insns[i].base = &ib[i];
80220 insns[i].opcode = &oc[i];
80221 m32c_cgen_build_insn_regex (& insns[i]);
80222 }
80223 cd->macro_insn_table.init_entries = insns;
80224 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
80225 cd->macro_insn_table.num_init_entries = num_macros;
80226
80227 oc = & m32c_cgen_insn_opcode_table[0];
80228 insns = (CGEN_INSN *) cd->insn_table.init_entries;
80229 for (i = 0; i < MAX_INSNS; ++i)
80230 {
80231 insns[i].opcode = &oc[i];
80232 m32c_cgen_build_insn_regex (& insns[i]);
80233 }
80234
80235 cd->sizeof_fields = sizeof (CGEN_FIELDS);
80236 cd->set_fields_bitsize = set_fields_bitsize;
80237
80238 cd->asm_hash_p = asm_hash_insn_p;
80239 cd->asm_hash = asm_hash_insn;
80240 cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
80241
80242 cd->dis_hash_p = dis_hash_insn_p;
80243 cd->dis_hash = dis_hash_insn;
80244 cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
80245}
GDB Binutils - Deliverables
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