projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix extraneous complaints about missing expected TLS relocation (i386).
[deliverable/binutils-gdb.git] / opcodes / m32r-ibld.c
CommitLineData
252b5132
RH		 1/* Instruction building/extraction support for m32r. -*- C -*-
2
47b0e7ad
NC		 3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
252b5132 5
6f2750fe 6 Copyright (C) 1996-2016 Free Software Foundation, Inc.
252b5132 7
9b201bb5 8 This file is part of libopcodes.
252b5132 9
9b201bb5 10 This library is free software; you can redistribute it and/or modify
47b0e7ad 11 it under the terms of the GNU General Public License as published by
9b201bb5 12 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 13 any later version.
252b5132 14
9b201bb5
NC		 15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
252b5132 19
47b0e7ad
NC		 20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132
RH		 23
24/* ??? Eventually more and more of this stuff can go to cpu-independent files.
25 Keep that in mind. */
26
27#include "sysdep.h"
252b5132
RH		 28#include <stdio.h>
29#include "ansidecl.h"
30#include "dis-asm.h"
31#include "bfd.h"
32#include "symcat.h"
33#include "m32r-desc.h"
34#include "m32r-opc.h"
fe8afbc4 35#include "cgen/basic-modes.h"
252b5132 36#include "opintl.h"
37111cc7 37#include "safe-ctype.h"
252b5132 38
47b0e7ad 39#undef min
252b5132 40#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 41#undef max
252b5132
RH		 42#define max(a,b) ((a) > (b) ? (a) : (b))
43
44/* Used by the ifield rtx function. */
45#define FLD(f) (fields->f)
46
47static const char * insert_normal
ffead7ae
MM		 48 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
49 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
252b5132 50static const char * insert_insn_normal
ffead7ae
MM		 51 (CGEN_CPU_DESC, const CGEN_INSN *,
52 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
252b5132 53static int extract_normal
ffead7ae
MM		 54 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
55 unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int, bfd_vma, long *);
252b5132 57static int extract_insn_normal
ffead7ae
MM		 58 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
59 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 60#if CGEN_INT_INSN_P
f40c3ea3 61static void put_insn_int_value
ffead7ae 62 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
0e2ee3ca
NC		 63#endif
64#if ! CGEN_INT_INSN_P
65static CGEN_INLINE void insert_1
ffead7ae 66 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
0e2ee3ca 67static CGEN_INLINE int fill_cache
ffead7ae 68 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
0e2ee3ca 69static CGEN_INLINE long extract_1
ffead7ae 70 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
0e2ee3ca 71#endif
252b5132
RH		 72\f
73/* Operand insertion. */
74
75#if ! CGEN_INT_INSN_P
76
77/* Subroutine of insert_normal. */
78
79static CGEN_INLINE void
ffead7ae
MM		 80insert_1 (CGEN_CPU_DESC cd,
81 unsigned long value,
82 int start,
83 int length,
84 int word_length,
85 unsigned char *bufp)
252b5132
RH		 86{
87 unsigned long x,mask;
88 int shift;
252b5132 89
0e2ee3ca 90 x = cgen_get_insn_value (cd, bufp, word_length);
252b5132
RH		 91
92 /* Written this way to avoid undefined behaviour. */
93 mask = (((1L << (length - 1)) - 1) << 1) | 1;
94 if (CGEN_INSN_LSB0_P)
95 shift = (start + 1) - length;
96 else
97 shift = (word_length - (start + length));
98 x = (x & ~(mask << shift)) | ((value & mask) << shift);
99
0e2ee3ca 100 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
252b5132
RH		 101}
102
103#endif /* ! CGEN_INT_INSN_P */
104
105/* Default insertion routine.
106
107 ATTRS is a mask of the boolean attributes.
108 WORD_OFFSET is the offset in bits from the start of the insn of the value.
109 WORD_LENGTH is the length of the word in bits in which the value resides.
110 START is the starting bit number in the word, architecture origin.
111 LENGTH is the length of VALUE in bits.
112 TOTAL_LENGTH is the total length of the insn in bits.
113
114 The result is an error message or NULL if success. */
115
116/* ??? This duplicates functionality with bfd's howto table and
117 bfd_install_relocation. */
118/* ??? This doesn't handle bfd_vma's. Create another function when
119 necessary. */
120
121static const char *
ffead7ae
MM		 122insert_normal (CGEN_CPU_DESC cd,
123 long value,
124 unsigned int attrs,
125 unsigned int word_offset,
126 unsigned int start,
127 unsigned int length,
128 unsigned int word_length,
129 unsigned int total_length,
130 CGEN_INSN_BYTES_PTR buffer)
252b5132
RH		 131{
132 static char errbuf[100];
133 /* Written this way to avoid undefined behaviour. */
134 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
135
136 /* If LENGTH is zero, this operand doesn't contribute to the value. */
137 if (length == 0)
138 return NULL;
139
b7cd1872 140 if (word_length > 8 * sizeof (CGEN_INSN_INT))
252b5132
RH		 141 abort ();
142
143 /* For architectures with insns smaller than the base-insn-bitsize,
144 word_length may be too big. */
145 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
146 {
147 if (word_offset == 0
148 && word_length > total_length)
149 word_length = total_length;
150 }
151
152 /* Ensure VALUE will fit. */
fc7bc883
RH		 153 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
154 {
155 long minval = - (1L << (length - 1));
156 unsigned long maxval = mask;
43e65147 157
fc7bc883
RH		 158 if ((value > 0 && (unsigned long) value > maxval)
159 || value < minval)
160 {
161 /* xgettext:c-format */
162 sprintf (errbuf,
163 _("operand out of range (%ld not between %ld and %lu)"),
164 value, minval, maxval);
165 return errbuf;
166 }
167 }
168 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
252b5132
RH		 169 {
170 unsigned long maxval = mask;
ed963e2d
NC		 171 unsigned long val = (unsigned long) value;
172
173 /* For hosts with a word size > 32 check to see if value has been sign
174 extended beyond 32 bits. If so then ignore these higher sign bits
175 as the user is attempting to store a 32-bit signed value into an
176 unsigned 32-bit field which is allowed. */
177 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
178 val &= 0xFFFFFFFF;
179
180 if (val > maxval)
252b5132
RH		 181 {
182 /* xgettext:c-format */
183 sprintf (errbuf,
ed963e2d
NC		 184 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
185 val, maxval);
252b5132
RH		 186 return errbuf;
187 }
188 }
189 else
190 {
cfcdbe97 191 if (! cgen_signed_overflow_ok_p (cd))
252b5132 192 {
cfcdbe97
AH		 193 long minval = - (1L << (length - 1));
194 long maxval = (1L << (length - 1)) - 1;
43e65147 195
cfcdbe97
AH		 196 if (value < minval || value > maxval)
197 {
198 sprintf
199 /* xgettext:c-format */
200 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
201 value, minval, maxval);
202 return errbuf;
203 }
252b5132
RH		 204 }
205 }
206
207#if CGEN_INT_INSN_P
208
209 {
a143b004 210 int shift_within_word, shift_to_word, shift;
252b5132 211
a143b004
AB		 212 /* How to shift the value to BIT0 of the word. */
213 shift_to_word = total_length - (word_offset + word_length);
214
215 /* How to shift the value to the field within the word. */
252b5132 216 if (CGEN_INSN_LSB0_P)
a143b004 217 shift_within_word = start + 1 - length;
252b5132 218 else
a143b004
AB		 219 shift_within_word = word_length - start - length;
220
221 /* The total SHIFT, then mask in the value. */
222 shift = shift_to_word + shift_within_word;
252b5132
RH		 223 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
224 }
225
226#else /* ! CGEN_INT_INSN_P */
227
228 {
229 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
230
231 insert_1 (cd, value, start, length, word_length, bufp);
232 }
233
234#endif /* ! CGEN_INT_INSN_P */
235
236 return NULL;
237}
238
239/* Default insn builder (insert handler).
52646233
FCE		 240 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
241 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
242 recorded in host byte order, otherwise BUFFER is an array of bytes
243 and the value is recorded in target byte order).
252b5132
RH		 244 The result is an error message or NULL if success. */
245
246static const char *
ffead7ae
MM		 247insert_insn_normal (CGEN_CPU_DESC cd,
248 const CGEN_INSN * insn,
249 CGEN_FIELDS * fields,
250 CGEN_INSN_BYTES_PTR buffer,
251 bfd_vma pc)
252b5132
RH		 252{
253 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
254 unsigned long value;
b3466c39 255 const CGEN_SYNTAX_CHAR_TYPE * syn;
252b5132
RH		 256
257 CGEN_INIT_INSERT (cd);
258 value = CGEN_INSN_BASE_VALUE (insn);
259
260 /* If we're recording insns as numbers (rather than a string of bytes),
261 target byte order handling is deferred until later. */
262
263#if CGEN_INT_INSN_P
264
f40c3ea3
DB		 265 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
266 CGEN_FIELDS_BITSIZE (fields), value);
252b5132
RH		 267
268#else
269
0e2ee3ca
NC		 270 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
271 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
252b5132
RH		 272 value);
273
274#endif /* ! CGEN_INT_INSN_P */
275
276 /* ??? It would be better to scan the format's fields.
277 Still need to be able to insert a value based on the operand though;
278 e.g. storing a branch displacement that got resolved later.
279 Needs more thought first. */
280
b3466c39 281 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
252b5132
RH		 282 {
283 const char *errmsg;
284
285 if (CGEN_SYNTAX_CHAR_P (* syn))
286 continue;
287
288 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
289 fields, buffer, pc);
290 if (errmsg)
291 return errmsg;
292 }
293
294 return NULL;
295}
6bb95a0f 296
0e2ee3ca 297#if CGEN_INT_INSN_P
6bb95a0f 298/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 299 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
6bb95a0f 300
f40c3ea3 301static void
ffead7ae
MM		 302put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
303 CGEN_INSN_BYTES_PTR buf,
304 int length,
305 int insn_length,
306 CGEN_INSN_INT value)
6bb95a0f
DB		 307{
308 /* For architectures with insns smaller than the base-insn-bitsize,
309 length may be too big. */
310 if (length > insn_length)
311 *buf = value;
312 else
313 {
314 int shift = insn_length - length;
315 /* Written this way to avoid undefined behaviour. */
316 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 317
6bb95a0f
DB		 318 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
319 }
320}
0e2ee3ca 321#endif
252b5132
RH		 322\f
323/* Operand extraction. */
324
325#if ! CGEN_INT_INSN_P
326
327/* Subroutine of extract_normal.
328 Ensure sufficient bytes are cached in EX_INFO.
329 OFFSET is the offset in bytes from the start of the insn of the value.
330 BYTES is the length of the needed value.
331 Returns 1 for success, 0 for failure. */
332
333static CGEN_INLINE int
ffead7ae
MM		 334fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
335 CGEN_EXTRACT_INFO *ex_info,
336 int offset,
337 int bytes,
338 bfd_vma pc)
252b5132
RH		 339{
340 /* It's doubtful that the middle part has already been fetched so
341 we don't optimize that case. kiss. */
0e2ee3ca 342 unsigned int mask;
252b5132
RH		 343 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
344
345 /* First do a quick check. */
346 mask = (1 << bytes) - 1;
347 if (((ex_info->valid >> offset) & mask) == mask)
348 return 1;
349
350 /* Search for the first byte we need to read. */
351 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
352 if (! (mask & ex_info->valid))
353 break;
354
355 if (bytes)
356 {
357 int status;
358
359 pc += offset;
360 status = (*info->read_memory_func)
361 (pc, ex_info->insn_bytes + offset, bytes, info);
362
363 if (status != 0)
364 {
365 (*info->memory_error_func) (status, pc, info);
366 return 0;
367 }
368
369 ex_info->valid |= ((1 << bytes) - 1) << offset;
370 }
371
372 return 1;
373}
374
375/* Subroutine of extract_normal. */
376
377static CGEN_INLINE long
ffead7ae
MM		 378extract_1 (CGEN_CPU_DESC cd,
379 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
380 int start,
381 int length,
382 int word_length,
383 unsigned char *bufp,
384 bfd_vma pc ATTRIBUTE_UNUSED)
252b5132 385{
b3466c39 386 unsigned long x;
252b5132 387 int shift;
47b0e7ad 388
e333d2c4
NC		 389 x = cgen_get_insn_value (cd, bufp, word_length);
390
252b5132
RH		 391 if (CGEN_INSN_LSB0_P)
392 shift = (start + 1) - length;
393 else
394 shift = (word_length - (start + length));
b3466c39 395 return x >> shift;
252b5132
RH		 396}
397
398#endif /* ! CGEN_INT_INSN_P */
399
400/* Default extraction routine.
401
402 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
403 or sometimes less for cases like the m32r where the base insn size is 32
404 but some insns are 16 bits.
405 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
406 but for generality we take a bitmask of all of them.
407 WORD_OFFSET is the offset in bits from the start of the insn of the value.
408 WORD_LENGTH is the length of the word in bits in which the value resides.
409 START is the starting bit number in the word, architecture origin.
410 LENGTH is the length of VALUE in bits.
411 TOTAL_LENGTH is the total length of the insn in bits.
412
413 Returns 1 for success, 0 for failure. */
414
415/* ??? The return code isn't properly used. wip. */
416
417/* ??? This doesn't handle bfd_vma's. Create another function when
418 necessary. */
419
420static int
ffead7ae 421extract_normal (CGEN_CPU_DESC cd,
6bb95a0f 422#if ! CGEN_INT_INSN_P
ffead7ae 423 CGEN_EXTRACT_INFO *ex_info,
6bb95a0f 424#else
ffead7ae 425 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
6bb95a0f 426#endif
ffead7ae
MM		 427 CGEN_INSN_INT insn_value,
428 unsigned int attrs,
429 unsigned int word_offset,
430 unsigned int start,
431 unsigned int length,
432 unsigned int word_length,
433 unsigned int total_length,
6bb95a0f 434#if ! CGEN_INT_INSN_P
ffead7ae 435 bfd_vma pc,
6bb95a0f 436#else
ffead7ae 437 bfd_vma pc ATTRIBUTE_UNUSED,
6bb95a0f 438#endif
ffead7ae 439 long *valuep)
252b5132 440{
fc7bc883 441 long value, mask;
252b5132
RH		 442
443 /* If LENGTH is zero, this operand doesn't contribute to the value
444 so give it a standard value of zero. */
445 if (length == 0)
446 {
447 *valuep = 0;
448 return 1;
449 }
450
b7cd1872 451 if (word_length > 8 * sizeof (CGEN_INSN_INT))
252b5132
RH		 452 abort ();
453
454 /* For architectures with insns smaller than the insn-base-bitsize,
455 word_length may be too big. */
456 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
457 {
ed963e2d
NC		 458 if (word_offset + word_length > total_length)
459 word_length = total_length - word_offset;
252b5132
RH		 460 }
461
fc7bc883 462 /* Does the value reside in INSN_VALUE, and at the right alignment? */
252b5132 463
fc7bc883 464 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
252b5132 465 {
252b5132 466 if (CGEN_INSN_LSB0_P)
6bb95a0f 467 value = insn_value >> ((word_offset + start + 1) - length);
252b5132 468 else
6bb95a0f 469 value = insn_value >> (total_length - ( word_offset + start + length));
252b5132
RH		 470 }
471
472#if ! CGEN_INT_INSN_P
473
474 else
475 {
476 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
477
b7cd1872 478 if (word_length > 8 * sizeof (CGEN_INSN_INT))
252b5132
RH		 479 abort ();
480
481 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
482 return 0;
483
484 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
485 }
486
487#endif /* ! CGEN_INT_INSN_P */
488
b3466c39
DB		 489 /* Written this way to avoid undefined behaviour. */
490 mask = (((1L << (length - 1)) - 1) << 1) | 1;
491
492 value &= mask;
493 /* sign extend? */
494 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
495 && (value & (1L << (length - 1))))
496 value |= ~mask;
497
252b5132
RH		 498 *valuep = value;
499
500 return 1;
501}
502
503/* Default insn extractor.
504
505 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
506 The extracted fields are stored in FIELDS.
507 EX_INFO is used to handle reading variable length insns.
508 Return the length of the insn in bits, or 0 if no match,
509 or -1 if an error occurs fetching data (memory_error_func will have
510 been called). */
511
512static int
ffead7ae
MM		 513extract_insn_normal (CGEN_CPU_DESC cd,
514 const CGEN_INSN *insn,
515 CGEN_EXTRACT_INFO *ex_info,
516 CGEN_INSN_INT insn_value,
517 CGEN_FIELDS *fields,
518 bfd_vma pc)
252b5132
RH		 519{
520 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
b3466c39 521 const CGEN_SYNTAX_CHAR_TYPE *syn;
252b5132
RH		 522
523 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
524
525 CGEN_INIT_EXTRACT (cd);
526
527 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
528 {
529 int length;
530
531 if (CGEN_SYNTAX_CHAR_P (*syn))
532 continue;
533
534 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
535 ex_info, insn_value, fields, pc);
536 if (length <= 0)
537 return length;
538 }
539
540 /* We recognized and successfully extracted this insn. */
541 return CGEN_INSN_BITSIZE (insn);
542}
543\f
47b0e7ad 544/* Machine generated code added here. */
252b5132 545
0e2ee3ca 546const char * m32r_cgen_insert_operand
47b0e7ad 547 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
0e2ee3ca 548
252b5132
RH		 549/* Main entry point for operand insertion.
550
551 This function is basically just a big switch statement. Earlier versions
552 used tables to look up the function to use, but
553 - if the table contains both assembler and disassembler functions then
554 the disassembler contains much of the assembler and vice-versa,
555 - there's a lot of inlining possibilities as things grow,
556 - using a switch statement avoids the function call overhead.
557
558 This function could be moved into `parse_insn_normal', but keeping it
559 separate makes clear the interface between `parse_insn_normal' and each of
560 the handlers. It's also needed by GAS to insert operands that couldn't be
9a2e995d 561 resolved during parsing. */
252b5132
RH		 562
563const char *
47b0e7ad
NC		 564m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
565 int opindex,
566 CGEN_FIELDS * fields,
567 CGEN_INSN_BYTES_PTR buffer,
568 bfd_vma pc ATTRIBUTE_UNUSED)
252b5132 569{
eb1b03df 570 const char * errmsg = NULL;
252b5132
RH		 571 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
572
573 switch (opindex)
574 {
1fa60b5d
DE		 575 case M32R_OPERAND_ACC :
576 errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
577 break;
578 case M32R_OPERAND_ACCD :
579 errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
580 break;
581 case M32R_OPERAND_ACCS :
582 errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
583 break;
252b5132
RH		 584 case M32R_OPERAND_DCR :
585 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
586 break;
587 case M32R_OPERAND_DISP16 :
588 {
589 long value = fields->f_disp16;
fe8afbc4 590 value = ((SI) (((value) - (pc))) >> (2));
252b5132
RH		 591 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
592 }
593 break;
594 case M32R_OPERAND_DISP24 :
595 {
596 long value = fields->f_disp24;
fe8afbc4 597 value = ((SI) (((value) - (pc))) >> (2));
252b5132
RH		 598 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
599 }
600 break;
601 case M32R_OPERAND_DISP8 :
602 {
603 long value = fields->f_disp8;
fe8afbc4 604 value = ((SI) (((value) - (((pc) & (-4))))) >> (2));
252b5132
RH		 605 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
606 }
607 break;
608 case M32R_OPERAND_DR :
609 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
610 break;
611 case M32R_OPERAND_HASH :
252b5132
RH		 612 break;
613 case M32R_OPERAND_HI16 :
614 errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
615 break;
1fa60b5d
DE		 616 case M32R_OPERAND_IMM1 :
617 {
618 long value = fields->f_imm1;
619 value = ((value) - (1));
620 errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
621 }
622 break;
252b5132
RH		 623 case M32R_OPERAND_SCR :
624 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
625 break;
626 case M32R_OPERAND_SIMM16 :
627 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
628 break;
629 case M32R_OPERAND_SIMM8 :
630 errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
631 break;
632 case M32R_OPERAND_SLO16 :
633 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
634 break;
635 case M32R_OPERAND_SR :
636 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
637 break;
638 case M32R_OPERAND_SRC1 :
639 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
640 break;
641 case M32R_OPERAND_SRC2 :
642 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
643 break;
644 case M32R_OPERAND_UIMM16 :
645 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
646 break;
647 case M32R_OPERAND_UIMM24 :
648 errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
649 break;
88845958
NC		 650 case M32R_OPERAND_UIMM3 :
651 errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
652 break;
252b5132
RH		 653 case M32R_OPERAND_UIMM4 :
654 errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
655 break;
656 case M32R_OPERAND_UIMM5 :
657 errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
658 break;
88845958
NC		 659 case M32R_OPERAND_UIMM8 :
660 errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
661 break;
252b5132
RH		 662 case M32R_OPERAND_ULO16 :
663 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
664 break;
665
666 default :
667 /* xgettext:c-format */
668 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
669 opindex);
670 abort ();
671 }
672
673 return errmsg;
674}
675
0e2ee3ca 676int m32r_cgen_extract_operand
47b0e7ad 677 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 678
252b5132 679/* Main entry point for operand extraction.
eb1b03df
DE		 680 The result is <= 0 for error, >0 for success.
681 ??? Actual values aren't well defined right now.
252b5132
RH		 682
683 This function is basically just a big switch statement. Earlier versions
684 used tables to look up the function to use, but
685 - if the table contains both assembler and disassembler functions then
686 the disassembler contains much of the assembler and vice-versa,
687 - there's a lot of inlining possibilities as things grow,
688 - using a switch statement avoids the function call overhead.
689
690 This function could be moved into `print_insn_normal', but keeping it
691 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 692 the handlers. */
252b5132
RH		 693
694int
47b0e7ad
NC		 695m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
696 int opindex,
697 CGEN_EXTRACT_INFO *ex_info,
698 CGEN_INSN_INT insn_value,
699 CGEN_FIELDS * fields,
700 bfd_vma pc)
252b5132 701{
eb1b03df
DE		 702 /* Assume success (for those operands that are nops). */
703 int length = 1;
252b5132
RH		 704 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
705
706 switch (opindex)
707 {
1fa60b5d
DE		 708 case M32R_OPERAND_ACC :
709 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
710 break;
711 case M32R_OPERAND_ACCD :
712 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
713 break;
714 case M32R_OPERAND_ACCS :
715 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
716 break;
252b5132
RH		 717 case M32R_OPERAND_DCR :
718 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
719 break;
720 case M32R_OPERAND_DISP16 :
721 {
722 long value;
723 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
724 value = ((((value) << (2))) + (pc));
725 fields->f_disp16 = value;
726 }
727 break;
728 case M32R_OPERAND_DISP24 :
729 {
730 long value;
731 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
732 value = ((((value) << (2))) + (pc));
733 fields->f_disp24 = value;
734 }
735 break;
736 case M32R_OPERAND_DISP8 :
737 {
738 long value;
739 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
740 value = ((((value) << (2))) + (((pc) & (-4))));
741 fields->f_disp8 = value;
742 }
743 break;
744 case M32R_OPERAND_DR :
745 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
746 break;
747 case M32R_OPERAND_HASH :
252b5132
RH		 748 break;
749 case M32R_OPERAND_HI16 :
750 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
751 break;
1fa60b5d
DE		 752 case M32R_OPERAND_IMM1 :
753 {
754 long value;
755 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
756 value = ((value) + (1));
757 fields->f_imm1 = value;
758 }
759 break;
252b5132
RH		 760 case M32R_OPERAND_SCR :
761 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
762 break;
763 case M32R_OPERAND_SIMM16 :
764 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
765 break;
766 case M32R_OPERAND_SIMM8 :
767 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
768 break;
769 case M32R_OPERAND_SLO16 :
770 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
771 break;
772 case M32R_OPERAND_SR :
773 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
774 break;
775 case M32R_OPERAND_SRC1 :
776 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
777 break;
778 case M32R_OPERAND_SRC2 :
779 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
780 break;
781 case M32R_OPERAND_UIMM16 :
782 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
783 break;
784 case M32R_OPERAND_UIMM24 :
785 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
786 break;
88845958
NC		 787 case M32R_OPERAND_UIMM3 :
788 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
789 break;
252b5132
RH		 790 case M32R_OPERAND_UIMM4 :
791 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
792 break;
793 case M32R_OPERAND_UIMM5 :
794 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
795 break;
88845958
NC		 796 case M32R_OPERAND_UIMM8 :
797 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
798 break;
252b5132
RH		 799 case M32R_OPERAND_ULO16 :
800 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
801 break;
802
803 default :
804 /* xgettext:c-format */
805 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
806 opindex);
807 abort ();
808 }
809
810 return length;
811}
812
43e65147 813cgen_insert_fn * const m32r_cgen_insert_handlers[] =
252b5132
RH		 814{
815 insert_insn_normal,
816};
817
43e65147 818cgen_extract_fn * const m32r_cgen_extract_handlers[] =
252b5132
RH		 819{
820 extract_insn_normal,
821};
822
47b0e7ad
NC		 823int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
824bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
0e2ee3ca 825
252b5132
RH		 826/* Getting values from cgen_fields is handled by a collection of functions.
827 They are distinguished by the type of the VALUE argument they return.
828 TODO: floating point, inlining support, remove cases where result type
829 not appropriate. */
830
831int
47b0e7ad
NC		 832m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
833 int opindex,
834 const CGEN_FIELDS * fields)
252b5132
RH		 835{
836 int value;
837
838 switch (opindex)
839 {
1fa60b5d
DE		 840 case M32R_OPERAND_ACC :
841 value = fields->f_acc;
842 break;
843 case M32R_OPERAND_ACCD :
844 value = fields->f_accd;
845 break;
846 case M32R_OPERAND_ACCS :
847 value = fields->f_accs;
848 break;
252b5132
RH		 849 case M32R_OPERAND_DCR :
850 value = fields->f_r1;
851 break;
852 case M32R_OPERAND_DISP16 :
853 value = fields->f_disp16;
854 break;
855 case M32R_OPERAND_DISP24 :
856 value = fields->f_disp24;
857 break;
858 case M32R_OPERAND_DISP8 :
859 value = fields->f_disp8;
860 break;
861 case M32R_OPERAND_DR :
862 value = fields->f_r1;
863 break;
864 case M32R_OPERAND_HASH :
eb1b03df 865 value = 0;
252b5132
RH		 866 break;
867 case M32R_OPERAND_HI16 :
868 value = fields->f_hi16;
869 break;
1fa60b5d
DE		 870 case M32R_OPERAND_IMM1 :
871 value = fields->f_imm1;
872 break;
252b5132
RH		 873 case M32R_OPERAND_SCR :
874 value = fields->f_r2;
875 break;
876 case M32R_OPERAND_SIMM16 :
877 value = fields->f_simm16;
878 break;
879 case M32R_OPERAND_SIMM8 :
880 value = fields->f_simm8;
881 break;
882 case M32R_OPERAND_SLO16 :
883 value = fields->f_simm16;
884 break;
885 case M32R_OPERAND_SR :
886 value = fields->f_r2;
887 break;
888 case M32R_OPERAND_SRC1 :
889 value = fields->f_r1;
890 break;
891 case M32R_OPERAND_SRC2 :
892 value = fields->f_r2;
893 break;
894 case M32R_OPERAND_UIMM16 :
895 value = fields->f_uimm16;
896 break;
897 case M32R_OPERAND_UIMM24 :
898 value = fields->f_uimm24;
899 break;
88845958
NC		 900 case M32R_OPERAND_UIMM3 :
901 value = fields->f_uimm3;
902 break;
252b5132
RH		 903 case M32R_OPERAND_UIMM4 :
904 value = fields->f_uimm4;
905 break;
906 case M32R_OPERAND_UIMM5 :
907 value = fields->f_uimm5;
908 break;
88845958
NC		 909 case M32R_OPERAND_UIMM8 :
910 value = fields->f_uimm8;
911 break;
252b5132
RH		 912 case M32R_OPERAND_ULO16 :
913 value = fields->f_uimm16;
914 break;
915
916 default :
917 /* xgettext:c-format */
918 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
919 opindex);
920 abort ();
921 }
922
923 return value;
924}
925
926bfd_vma
47b0e7ad
NC		 927m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
928 int opindex,
929 const CGEN_FIELDS * fields)
252b5132
RH		 930{
931 bfd_vma value;
932
933 switch (opindex)
934 {
1fa60b5d
DE		 935 case M32R_OPERAND_ACC :
936 value = fields->f_acc;
937 break;
938 case M32R_OPERAND_ACCD :
939 value = fields->f_accd;
940 break;
941 case M32R_OPERAND_ACCS :
942 value = fields->f_accs;
943 break;
252b5132
RH		 944 case M32R_OPERAND_DCR :
945 value = fields->f_r1;
946 break;
947 case M32R_OPERAND_DISP16 :
948 value = fields->f_disp16;
949 break;
950 case M32R_OPERAND_DISP24 :
951 value = fields->f_disp24;
952 break;
953 case M32R_OPERAND_DISP8 :
954 value = fields->f_disp8;
955 break;
956 case M32R_OPERAND_DR :
957 value = fields->f_r1;
958 break;
959 case M32R_OPERAND_HASH :
eb1b03df 960 value = 0;
252b5132
RH		 961 break;
962 case M32R_OPERAND_HI16 :
963 value = fields->f_hi16;
964 break;
1fa60b5d
DE		 965 case M32R_OPERAND_IMM1 :
966 value = fields->f_imm1;
967 break;
252b5132
RH		 968 case M32R_OPERAND_SCR :
969 value = fields->f_r2;
970 break;
971 case M32R_OPERAND_SIMM16 :
972 value = fields->f_simm16;
973 break;
974 case M32R_OPERAND_SIMM8 :
975 value = fields->f_simm8;
976 break;
977 case M32R_OPERAND_SLO16 :
978 value = fields->f_simm16;
979 break;
980 case M32R_OPERAND_SR :
981 value = fields->f_r2;
982 break;
983 case M32R_OPERAND_SRC1 :
984 value = fields->f_r1;
985 break;
986 case M32R_OPERAND_SRC2 :
987 value = fields->f_r2;
988 break;
989 case M32R_OPERAND_UIMM16 :
990 value = fields->f_uimm16;
991 break;
992 case M32R_OPERAND_UIMM24 :
993 value = fields->f_uimm24;
994 break;
88845958
NC		 995 case M32R_OPERAND_UIMM3 :
996 value = fields->f_uimm3;
997 break;
252b5132
RH		 998 case M32R_OPERAND_UIMM4 :
999 value = fields->f_uimm4;
1000 break;
1001 case M32R_OPERAND_UIMM5 :
1002 value = fields->f_uimm5;
1003 break;
88845958
NC		 1004 case M32R_OPERAND_UIMM8 :
1005 value = fields->f_uimm8;
1006 break;
252b5132
RH		 1007 case M32R_OPERAND_ULO16 :
1008 value = fields->f_uimm16;
1009 break;
1010
1011 default :
1012 /* xgettext:c-format */
1013 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
1014 opindex);
1015 abort ();
1016 }
1017
1018 return value;
1019}
1020
47b0e7ad
NC		 1021void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
1022void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 1023
252b5132
RH		 1024/* Stuffing values in cgen_fields is handled by a collection of functions.
1025 They are distinguished by the type of the VALUE argument they accept.
1026 TODO: floating point, inlining support, remove cases where argument type
1027 not appropriate. */
1028
1029void
47b0e7ad
NC		 1030m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1031 int opindex,
1032 CGEN_FIELDS * fields,
1033 int value)
252b5132
RH		 1034{
1035 switch (opindex)
1036 {
1fa60b5d
DE		 1037 case M32R_OPERAND_ACC :
1038 fields->f_acc = value;
1039 break;
1040 case M32R_OPERAND_ACCD :
1041 fields->f_accd = value;
1042 break;
1043 case M32R_OPERAND_ACCS :
1044 fields->f_accs = value;
1045 break;
252b5132
RH		 1046 case M32R_OPERAND_DCR :
1047 fields->f_r1 = value;
1048 break;
1049 case M32R_OPERAND_DISP16 :
1050 fields->f_disp16 = value;
1051 break;
1052 case M32R_OPERAND_DISP24 :
1053 fields->f_disp24 = value;
1054 break;
1055 case M32R_OPERAND_DISP8 :
1056 fields->f_disp8 = value;
1057 break;
1058 case M32R_OPERAND_DR :
1059 fields->f_r1 = value;
1060 break;
1061 case M32R_OPERAND_HASH :
252b5132
RH		 1062 break;
1063 case M32R_OPERAND_HI16 :
1064 fields->f_hi16 = value;
1065 break;
1fa60b5d
DE		 1066 case M32R_OPERAND_IMM1 :
1067 fields->f_imm1 = value;
1068 break;
252b5132
RH		 1069 case M32R_OPERAND_SCR :
1070 fields->f_r2 = value;
1071 break;
1072 case M32R_OPERAND_SIMM16 :
1073 fields->f_simm16 = value;
1074 break;
1075 case M32R_OPERAND_SIMM8 :
1076 fields->f_simm8 = value;
1077 break;
1078 case M32R_OPERAND_SLO16 :
1079 fields->f_simm16 = value;
1080 break;
1081 case M32R_OPERAND_SR :
1082 fields->f_r2 = value;
1083 break;
1084 case M32R_OPERAND_SRC1 :
1085 fields->f_r1 = value;
1086 break;
1087 case M32R_OPERAND_SRC2 :
1088 fields->f_r2 = value;
1089 break;
1090 case M32R_OPERAND_UIMM16 :
1091 fields->f_uimm16 = value;
1092 break;
1093 case M32R_OPERAND_UIMM24 :
1094 fields->f_uimm24 = value;
1095 break;
88845958
NC		 1096 case M32R_OPERAND_UIMM3 :
1097 fields->f_uimm3 = value;
1098 break;
252b5132
RH		 1099 case M32R_OPERAND_UIMM4 :
1100 fields->f_uimm4 = value;
1101 break;
1102 case M32R_OPERAND_UIMM5 :
1103 fields->f_uimm5 = value;
1104 break;
88845958
NC		 1105 case M32R_OPERAND_UIMM8 :
1106 fields->f_uimm8 = value;
1107 break;
252b5132
RH		 1108 case M32R_OPERAND_ULO16 :
1109 fields->f_uimm16 = value;
1110 break;
1111
1112 default :
1113 /* xgettext:c-format */
1114 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1115 opindex);
1116 abort ();
1117 }
1118}
1119
1120void
47b0e7ad
NC		 1121m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1122 int opindex,
1123 CGEN_FIELDS * fields,
1124 bfd_vma value)
252b5132
RH		 1125{
1126 switch (opindex)
1127 {
1fa60b5d
DE		 1128 case M32R_OPERAND_ACC :
1129 fields->f_acc = value;
1130 break;
1131 case M32R_OPERAND_ACCD :
1132 fields->f_accd = value;
1133 break;
1134 case M32R_OPERAND_ACCS :
1135 fields->f_accs = value;
1136 break;
252b5132
RH		 1137 case M32R_OPERAND_DCR :
1138 fields->f_r1 = value;
1139 break;
1140 case M32R_OPERAND_DISP16 :
1141 fields->f_disp16 = value;
1142 break;
1143 case M32R_OPERAND_DISP24 :
1144 fields->f_disp24 = value;
1145 break;
1146 case M32R_OPERAND_DISP8 :
1147 fields->f_disp8 = value;
1148 break;
1149 case M32R_OPERAND_DR :
1150 fields->f_r1 = value;
1151 break;
1152 case M32R_OPERAND_HASH :
252b5132
RH		 1153 break;
1154 case M32R_OPERAND_HI16 :
1155 fields->f_hi16 = value;
1156 break;
1fa60b5d
DE		 1157 case M32R_OPERAND_IMM1 :
1158 fields->f_imm1 = value;
1159 break;
252b5132
RH		 1160 case M32R_OPERAND_SCR :
1161 fields->f_r2 = value;
1162 break;
1163 case M32R_OPERAND_SIMM16 :
1164 fields->f_simm16 = value;
1165 break;
1166 case M32R_OPERAND_SIMM8 :
1167 fields->f_simm8 = value;
1168 break;
1169 case M32R_OPERAND_SLO16 :
1170 fields->f_simm16 = value;
1171 break;
1172 case M32R_OPERAND_SR :
1173 fields->f_r2 = value;
1174 break;
1175 case M32R_OPERAND_SRC1 :
1176 fields->f_r1 = value;
1177 break;
1178 case M32R_OPERAND_SRC2 :
1179 fields->f_r2 = value;
1180 break;
1181 case M32R_OPERAND_UIMM16 :
1182 fields->f_uimm16 = value;
1183 break;
1184 case M32R_OPERAND_UIMM24 :
1185 fields->f_uimm24 = value;
1186 break;
88845958
NC		 1187 case M32R_OPERAND_UIMM3 :
1188 fields->f_uimm3 = value;
1189 break;
252b5132
RH		 1190 case M32R_OPERAND_UIMM4 :
1191 fields->f_uimm4 = value;
1192 break;
1193 case M32R_OPERAND_UIMM5 :
1194 fields->f_uimm5 = value;
1195 break;
88845958
NC		 1196 case M32R_OPERAND_UIMM8 :
1197 fields->f_uimm8 = value;
1198 break;
252b5132
RH		 1199 case M32R_OPERAND_ULO16 :
1200 fields->f_uimm16 = value;
1201 break;
1202
1203 default :
1204 /* xgettext:c-format */
1205 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1206 opindex);
1207 abort ();
1208 }
1209}
1210
1211/* Function to call before using the instruction builder tables. */
1212
1213void
47b0e7ad 1214m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
252b5132
RH		 1215{
1216 cd->insert_handlers = & m32r_cgen_insert_handlers[0];
1217 cd->extract_handlers = & m32r_cgen_extract_handlers[0];
1218
1219 cd->insert_operand = m32r_cgen_insert_operand;
1220 cd->extract_operand = m32r_cgen_extract_operand;
1221
1222 cd->get_int_operand = m32r_cgen_get_int_operand;
1223 cd->set_int_operand = m32r_cgen_set_int_operand;
1224 cd->get_vma_operand = m32r_cgen_get_vma_operand;
1225 cd->set_vma_operand = m32r_cgen_set_vma_operand;
1226}
GDB Binutils - Deliverables
This page took 0.832317 seconds and 4 git commands to generate.