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* config/obj-elf.c: (obj_elf_change_section): Add "group" param.
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
CommitLineData
252b5132
RH		 1/* Instruction opcode table for m32r.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
060d22b0 5Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
252b5132
RH		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include "ansidecl.h"
27#include "bfd.h"
28#include "symcat.h"
29#include "m32r-desc.h"
30#include "m32r-opc.h"
6bb95a0f 31#include "libiberty.h"
252b5132
RH		 32
33/* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
35
fc05c67f
NC		 36static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37static unsigned int asm_hash_insn PARAMS ((const char *));
38static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
39static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
40static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
252b5132
RH		 41
42/* Instruction formats. */
43
b3466c39
DB		 44#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
45#define F(f) & m32r_cgen_ifld_table[M32R_##f]
46#else
47#define F(f) & m32r_cgen_ifld_table[M32R_/**/f]
48#endif
252b5132 49static const CGEN_IFMT ifmt_empty = {
6bb95a0f 50 0, 0, 0x0, { { 0 } }
252b5132
RH		 51};
52
53static const CGEN_IFMT ifmt_add = {
6bb95a0f 54 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 55};
56
57static const CGEN_IFMT ifmt_add3 = {
6bb95a0f 58 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 59};
60
61static const CGEN_IFMT ifmt_and3 = {
6bb95a0f 62 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
252b5132
RH		 63};
64
65static const CGEN_IFMT ifmt_or3 = {
6bb95a0f 66 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
252b5132
RH		 67};
68
69static const CGEN_IFMT ifmt_addi = {
6bb95a0f 70 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
252b5132
RH		 71};
72
73static const CGEN_IFMT ifmt_addv3 = {
6bb95a0f 74 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 75};
76
77static const CGEN_IFMT ifmt_bc8 = {
6bb95a0f 78 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
252b5132
RH		 79};
80
81static const CGEN_IFMT ifmt_bc24 = {
6bb95a0f 82 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
252b5132
RH		 83};
84
85static const CGEN_IFMT ifmt_beq = {
6bb95a0f 86 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
252b5132
RH		 87};
88
89static const CGEN_IFMT ifmt_beqz = {
6bb95a0f 90 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
252b5132
RH		 91};
92
93static const CGEN_IFMT ifmt_cmp = {
6bb95a0f 94 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 95};
96
97static const CGEN_IFMT ifmt_cmpi = {
6bb95a0f 98 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 99};
100
1fa60b5d 101static const CGEN_IFMT ifmt_cmpz = {
6bb95a0f 102 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
1fa60b5d
DE		 103};
104
252b5132 105static const CGEN_IFMT ifmt_div = {
6bb95a0f 106 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 107};
108
1fa60b5d 109static const CGEN_IFMT ifmt_jc = {
6bb95a0f 110 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 111};
112
113static const CGEN_IFMT ifmt_ld24 = {
6bb95a0f 114 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } }
252b5132
RH		 115};
116
117static const CGEN_IFMT ifmt_ldi16 = {
6bb95a0f 118 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 119};
120
1fa60b5d 121static const CGEN_IFMT ifmt_machi_a = {
6bb95a0f 122 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } }
1fa60b5d
DE		 123};
124
252b5132 125static const CGEN_IFMT ifmt_mvfachi = {
6bb95a0f 126 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 127};
128
1fa60b5d 129static const CGEN_IFMT ifmt_mvfachi_a = {
6bb95a0f 130 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
1fa60b5d
DE		 131};
132
252b5132 133static const CGEN_IFMT ifmt_mvfc = {
6bb95a0f 134 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 135};
136
137static const CGEN_IFMT ifmt_mvtachi = {
6bb95a0f 138 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 139};
140
1fa60b5d 141static const CGEN_IFMT ifmt_mvtachi_a = {
6bb95a0f 142 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
1fa60b5d
DE		 143};
144
252b5132 145static const CGEN_IFMT ifmt_mvtc = {
6bb95a0f 146 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 147};
148
149static const CGEN_IFMT ifmt_nop = {
6bb95a0f 150 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 151};
152
1fa60b5d 153static const CGEN_IFMT ifmt_rac_dsi = {
6bb95a0f 154 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1fa60b5d
DE		 155};
156
252b5132 157static const CGEN_IFMT ifmt_seth = {
6bb95a0f 158 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } }
252b5132
RH		 159};
160
161static const CGEN_IFMT ifmt_slli = {
6bb95a0f 162 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } }
252b5132
RH		 163};
164
165static const CGEN_IFMT ifmt_st_d = {
6bb95a0f 166 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 167};
168
169static const CGEN_IFMT ifmt_trap = {
6bb95a0f 170 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } }
252b5132
RH		 171};
172
1fa60b5d 173static const CGEN_IFMT ifmt_satb = {
6bb95a0f 174 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
1fa60b5d
DE		 175};
176
252b5132
RH		 177#undef F
178
b3466c39
DB		 179#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
180#define A(a) (1 << CGEN_INSN_##a)
181#else
182#define A(a) (1 << CGEN_INSN_/**/a)
183#endif
184#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
185#define OPERAND(op) M32R_OPERAND_##op
186#else
187#define OPERAND(op) M32R_OPERAND_/**/op
188#endif
252b5132 189#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
252b5132
RH		 190#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
191
192/* The instruction table. */
193
194static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
195{
196 /* Special null first entry.
197 A `num' value of zero is thus invalid.
198 Also, the special `invalid' insn resides here. */
6bb95a0f 199 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
252b5132
RH		 200/* add $dr,$sr */
201 {
202 { 0, 0, 0, 0 },
203 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
204 & ifmt_add, { 0xa0 }
205 },
206/* add3 $dr,$sr,$hash$slo16 */
207 {
208 { 0, 0, 0, 0 },
209 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
210 & ifmt_add3, { 0x80a00000 }
211 },
212/* and $dr,$sr */
213 {
214 { 0, 0, 0, 0 },
215 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
216 & ifmt_add, { 0xc0 }
217 },
218/* and3 $dr,$sr,$uimm16 */
219 {
220 { 0, 0, 0, 0 },
221 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
222 & ifmt_and3, { 0x80c00000 }
223 },
224/* or $dr,$sr */
225 {
226 { 0, 0, 0, 0 },
227 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
228 & ifmt_add, { 0xe0 }
229 },
230/* or3 $dr,$sr,$hash$ulo16 */
231 {
232 { 0, 0, 0, 0 },
233 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
234 & ifmt_or3, { 0x80e00000 }
235 },
236/* xor $dr,$sr */
237 {
238 { 0, 0, 0, 0 },
239 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
240 & ifmt_add, { 0xd0 }
241 },
242/* xor3 $dr,$sr,$uimm16 */
243 {
244 { 0, 0, 0, 0 },
245 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
246 & ifmt_and3, { 0x80d00000 }
247 },
248/* addi $dr,$simm8 */
249 {
250 { 0, 0, 0, 0 },
251 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
252 & ifmt_addi, { 0x4000 }
253 },
254/* addv $dr,$sr */
255 {
256 { 0, 0, 0, 0 },
257 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
258 & ifmt_add, { 0x80 }
259 },
260/* addv3 $dr,$sr,$simm16 */
261 {
262 { 0, 0, 0, 0 },
263 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
264 & ifmt_addv3, { 0x80800000 }
265 },
266/* addx $dr,$sr */
267 {
268 { 0, 0, 0, 0 },
269 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
270 & ifmt_add, { 0x90 }
271 },
272/* bc.s $disp8 */
273 {
274 { 0, 0, 0, 0 },
275 { { MNEM, ' ', OP (DISP8), 0 } },
276 & ifmt_bc8, { 0x7c00 }
277 },
278/* bc.l $disp24 */
279 {
280 { 0, 0, 0, 0 },
281 { { MNEM, ' ', OP (DISP24), 0 } },
282 & ifmt_bc24, { 0xfc000000 }
283 },
284/* beq $src1,$src2,$disp16 */
285 {
286 { 0, 0, 0, 0 },
287 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
288 & ifmt_beq, { 0xb0000000 }
289 },
290/* beqz $src2,$disp16 */
291 {
292 { 0, 0, 0, 0 },
293 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
294 & ifmt_beqz, { 0xb0800000 }
295 },
296/* bgez $src2,$disp16 */
297 {
298 { 0, 0, 0, 0 },
299 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
300 & ifmt_beqz, { 0xb0b00000 }
301 },
302/* bgtz $src2,$disp16 */
303 {
304 { 0, 0, 0, 0 },
305 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
306 & ifmt_beqz, { 0xb0d00000 }
307 },
308/* blez $src2,$disp16 */
309 {
310 { 0, 0, 0, 0 },
311 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
312 & ifmt_beqz, { 0xb0c00000 }
313 },
314/* bltz $src2,$disp16 */
315 {
316 { 0, 0, 0, 0 },
317 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
318 & ifmt_beqz, { 0xb0a00000 }
319 },
320/* bnez $src2,$disp16 */
321 {
322 { 0, 0, 0, 0 },
323 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
324 & ifmt_beqz, { 0xb0900000 }
325 },
326/* bl.s $disp8 */
327 {
328 { 0, 0, 0, 0 },
329 { { MNEM, ' ', OP (DISP8), 0 } },
330 & ifmt_bc8, { 0x7e00 }
331 },
332/* bl.l $disp24 */
333 {
334 { 0, 0, 0, 0 },
335 { { MNEM, ' ', OP (DISP24), 0 } },
336 & ifmt_bc24, { 0xfe000000 }
337 },
1fa60b5d
DE		 338/* bcl.s $disp8 */
339 {
340 { 0, 0, 0, 0 },
341 { { MNEM, ' ', OP (DISP8), 0 } },
342 & ifmt_bc8, { 0x7800 }
343 },
344/* bcl.l $disp24 */
345 {
346 { 0, 0, 0, 0 },
347 { { MNEM, ' ', OP (DISP24), 0 } },
348 & ifmt_bc24, { 0xf8000000 }
349 },
252b5132
RH		 350/* bnc.s $disp8 */
351 {
352 { 0, 0, 0, 0 },
353 { { MNEM, ' ', OP (DISP8), 0 } },
354 & ifmt_bc8, { 0x7d00 }
355 },
356/* bnc.l $disp24 */
357 {
358 { 0, 0, 0, 0 },
359 { { MNEM, ' ', OP (DISP24), 0 } },
360 & ifmt_bc24, { 0xfd000000 }
361 },
362/* bne $src1,$src2,$disp16 */
363 {
364 { 0, 0, 0, 0 },
365 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
366 & ifmt_beq, { 0xb0100000 }
367 },
368/* bra.s $disp8 */
369 {
370 { 0, 0, 0, 0 },
371 { { MNEM, ' ', OP (DISP8), 0 } },
372 & ifmt_bc8, { 0x7f00 }
373 },
374/* bra.l $disp24 */
375 {
376 { 0, 0, 0, 0 },
377 { { MNEM, ' ', OP (DISP24), 0 } },
378 & ifmt_bc24, { 0xff000000 }
379 },
1fa60b5d
DE		 380/* bncl.s $disp8 */
381 {
382 { 0, 0, 0, 0 },
383 { { MNEM, ' ', OP (DISP8), 0 } },
384 & ifmt_bc8, { 0x7900 }
385 },
386/* bncl.l $disp24 */
387 {
388 { 0, 0, 0, 0 },
389 { { MNEM, ' ', OP (DISP24), 0 } },
390 & ifmt_bc24, { 0xf9000000 }
391 },
252b5132
RH		 392/* cmp $src1,$src2 */
393 {
394 { 0, 0, 0, 0 },
395 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
396 & ifmt_cmp, { 0x40 }
397 },
398/* cmpi $src2,$simm16 */
399 {
400 { 0, 0, 0, 0 },
401 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
402 & ifmt_cmpi, { 0x80400000 }
403 },
404/* cmpu $src1,$src2 */
405 {
406 { 0, 0, 0, 0 },
407 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
408 & ifmt_cmp, { 0x50 }
409 },
410/* cmpui $src2,$simm16 */
411 {
412 { 0, 0, 0, 0 },
413 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
414 & ifmt_cmpi, { 0x80500000 }
415 },
1fa60b5d
DE		 416/* cmpeq $src1,$src2 */
417 {
418 { 0, 0, 0, 0 },
419 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
420 & ifmt_cmp, { 0x60 }
421 },
422/* cmpz $src2 */
423 {
424 { 0, 0, 0, 0 },
425 { { MNEM, ' ', OP (SRC2), 0 } },
426 & ifmt_cmpz, { 0x70 }
427 },
252b5132
RH		 428/* div $dr,$sr */
429 {
430 { 0, 0, 0, 0 },
431 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
432 & ifmt_div, { 0x90000000 }
433 },
434/* divu $dr,$sr */
435 {
436 { 0, 0, 0, 0 },
437 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
438 & ifmt_div, { 0x90100000 }
439 },
440/* rem $dr,$sr */
441 {
442 { 0, 0, 0, 0 },
443 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
444 & ifmt_div, { 0x90200000 }
445 },
446/* remu $dr,$sr */
447 {
448 { 0, 0, 0, 0 },
449 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
450 & ifmt_div, { 0x90300000 }
451 },
1fa60b5d
DE		 452/* divh $dr,$sr */
453 {
454 { 0, 0, 0, 0 },
455 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
456 & ifmt_div, { 0x90000010 }
457 },
458/* jc $sr */
459 {
460 { 0, 0, 0, 0 },
461 { { MNEM, ' ', OP (SR), 0 } },
462 & ifmt_jc, { 0x1cc0 }
463 },
464/* jnc $sr */
465 {
466 { 0, 0, 0, 0 },
467 { { MNEM, ' ', OP (SR), 0 } },
468 & ifmt_jc, { 0x1dc0 }
469 },
252b5132
RH		 470/* jl $sr */
471 {
472 { 0, 0, 0, 0 },
473 { { MNEM, ' ', OP (SR), 0 } },
1fa60b5d 474 & ifmt_jc, { 0x1ec0 }
252b5132
RH		 475 },
476/* jmp $sr */
477 {
478 { 0, 0, 0, 0 },
479 { { MNEM, ' ', OP (SR), 0 } },
1fa60b5d 480 & ifmt_jc, { 0x1fc0 }
252b5132
RH		 481 },
482/* ld $dr,@$sr */
483 {
484 { 0, 0, 0, 0 },
485 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
486 & ifmt_add, { 0x20c0 }
487 },
488/* ld $dr,@($slo16,$sr) */
489 {
490 { 0, 0, 0, 0 },
491 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
492 & ifmt_add3, { 0xa0c00000 }
493 },
494/* ldb $dr,@$sr */
495 {
496 { 0, 0, 0, 0 },
497 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
498 & ifmt_add, { 0x2080 }
499 },
500/* ldb $dr,@($slo16,$sr) */
501 {
502 { 0, 0, 0, 0 },
503 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
504 & ifmt_add3, { 0xa0800000 }
505 },
506/* ldh $dr,@$sr */
507 {
508 { 0, 0, 0, 0 },
509 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
510 & ifmt_add, { 0x20a0 }
511 },
512/* ldh $dr,@($slo16,$sr) */
513 {
514 { 0, 0, 0, 0 },
515 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
516 & ifmt_add3, { 0xa0a00000 }
517 },
518/* ldub $dr,@$sr */
519 {
520 { 0, 0, 0, 0 },
521 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
522 & ifmt_add, { 0x2090 }
523 },
524/* ldub $dr,@($slo16,$sr) */
525 {
526 { 0, 0, 0, 0 },
527 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
528 & ifmt_add3, { 0xa0900000 }
529 },
530/* lduh $dr,@$sr */
531 {
532 { 0, 0, 0, 0 },
533 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
534 & ifmt_add, { 0x20b0 }
535 },
536/* lduh $dr,@($slo16,$sr) */
537 {
538 { 0, 0, 0, 0 },
539 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
540 & ifmt_add3, { 0xa0b00000 }
541 },
542/* ld $dr,@$sr+ */
543 {
544 { 0, 0, 0, 0 },
545 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
546 & ifmt_add, { 0x20e0 }
547 },
548/* ld24 $dr,$uimm24 */
549 {
550 { 0, 0, 0, 0 },
551 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
552 & ifmt_ld24, { 0xe0000000 }
553 },
554/* ldi8 $dr,$simm8 */
555 {
556 { 0, 0, 0, 0 },
557 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
558 & ifmt_addi, { 0x6000 }
559 },
560/* ldi16 $dr,$hash$slo16 */
561 {
562 { 0, 0, 0, 0 },
563 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
564 & ifmt_ldi16, { 0x90f00000 }
565 },
566/* lock $dr,@$sr */
567 {
568 { 0, 0, 0, 0 },
569 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
570 & ifmt_add, { 0x20d0 }
571 },
572/* machi $src1,$src2 */
573 {
574 { 0, 0, 0, 0 },
575 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
576 & ifmt_cmp, { 0x3040 }
577 },
1fa60b5d
DE		 578/* machi $src1,$src2,$acc */
579 {
580 { 0, 0, 0, 0 },
581 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
582 & ifmt_machi_a, { 0x3040 }
583 },
252b5132
RH		 584/* maclo $src1,$src2 */
585 {
586 { 0, 0, 0, 0 },
587 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
588 & ifmt_cmp, { 0x3050 }
589 },
1fa60b5d
DE		 590/* maclo $src1,$src2,$acc */
591 {
592 { 0, 0, 0, 0 },
593 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
594 & ifmt_machi_a, { 0x3050 }
595 },
252b5132
RH		 596/* macwhi $src1,$src2 */
597 {
598 { 0, 0, 0, 0 },
599 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
600 & ifmt_cmp, { 0x3060 }
601 },
1fa60b5d
DE		 602/* macwhi $src1,$src2,$acc */
603 {
604 { 0, 0, 0, 0 },
605 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
606 & ifmt_machi_a, { 0x3060 }
607 },
252b5132
RH		 608/* macwlo $src1,$src2 */
609 {
610 { 0, 0, 0, 0 },
611 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
612 & ifmt_cmp, { 0x3070 }
613 },
1fa60b5d
DE		 614/* macwlo $src1,$src2,$acc */
615 {
616 { 0, 0, 0, 0 },
617 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
618 & ifmt_machi_a, { 0x3070 }
619 },
252b5132
RH		 620/* mul $dr,$sr */
621 {
622 { 0, 0, 0, 0 },
623 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
624 & ifmt_add, { 0x1060 }
625 },
626/* mulhi $src1,$src2 */
627 {
628 { 0, 0, 0, 0 },
629 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
630 & ifmt_cmp, { 0x3000 }
631 },
1fa60b5d
DE		 632/* mulhi $src1,$src2,$acc */
633 {
634 { 0, 0, 0, 0 },
635 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
636 & ifmt_machi_a, { 0x3000 }
637 },
252b5132
RH		 638/* mullo $src1,$src2 */
639 {
640 { 0, 0, 0, 0 },
641 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
642 & ifmt_cmp, { 0x3010 }
643 },
1fa60b5d
DE		 644/* mullo $src1,$src2,$acc */
645 {
646 { 0, 0, 0, 0 },
647 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
648 & ifmt_machi_a, { 0x3010 }
649 },
252b5132
RH		 650/* mulwhi $src1,$src2 */
651 {
652 { 0, 0, 0, 0 },
653 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
654 & ifmt_cmp, { 0x3020 }
655 },
1fa60b5d
DE		 656/* mulwhi $src1,$src2,$acc */
657 {
658 { 0, 0, 0, 0 },
659 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
660 & ifmt_machi_a, { 0x3020 }
661 },
252b5132
RH		 662/* mulwlo $src1,$src2 */
663 {
664 { 0, 0, 0, 0 },
665 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
666 & ifmt_cmp, { 0x3030 }
667 },
1fa60b5d
DE		 668/* mulwlo $src1,$src2,$acc */
669 {
670 { 0, 0, 0, 0 },
671 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
672 & ifmt_machi_a, { 0x3030 }
673 },
252b5132
RH		 674/* mv $dr,$sr */
675 {
676 { 0, 0, 0, 0 },
677 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
678 & ifmt_add, { 0x1080 }
679 },
680/* mvfachi $dr */
681 {
682 { 0, 0, 0, 0 },
683 { { MNEM, ' ', OP (DR), 0 } },
684 & ifmt_mvfachi, { 0x50f0 }
685 },
1fa60b5d
DE		 686/* mvfachi $dr,$accs */
687 {
688 { 0, 0, 0, 0 },
689 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
690 & ifmt_mvfachi_a, { 0x50f0 }
691 },
252b5132
RH		 692/* mvfaclo $dr */
693 {
694 { 0, 0, 0, 0 },
695 { { MNEM, ' ', OP (DR), 0 } },
696 & ifmt_mvfachi, { 0x50f1 }
697 },
1fa60b5d
DE		 698/* mvfaclo $dr,$accs */
699 {
700 { 0, 0, 0, 0 },
701 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
702 & ifmt_mvfachi_a, { 0x50f1 }
703 },
252b5132
RH		 704/* mvfacmi $dr */
705 {
706 { 0, 0, 0, 0 },
707 { { MNEM, ' ', OP (DR), 0 } },
708 & ifmt_mvfachi, { 0x50f2 }
709 },
1fa60b5d
DE		 710/* mvfacmi $dr,$accs */
711 {
712 { 0, 0, 0, 0 },
713 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
714 & ifmt_mvfachi_a, { 0x50f2 }
715 },
252b5132
RH		 716/* mvfc $dr,$scr */
717 {
718 { 0, 0, 0, 0 },
719 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
720 & ifmt_mvfc, { 0x1090 }
721 },
722/* mvtachi $src1 */
723 {
724 { 0, 0, 0, 0 },
725 { { MNEM, ' ', OP (SRC1), 0 } },
726 & ifmt_mvtachi, { 0x5070 }
727 },
1fa60b5d
DE		 728/* mvtachi $src1,$accs */
729 {
730 { 0, 0, 0, 0 },
731 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
732 & ifmt_mvtachi_a, { 0x5070 }
733 },
252b5132
RH		 734/* mvtaclo $src1 */
735 {
736 { 0, 0, 0, 0 },
737 { { MNEM, ' ', OP (SRC1), 0 } },
738 & ifmt_mvtachi, { 0x5071 }
739 },
1fa60b5d
DE		 740/* mvtaclo $src1,$accs */
741 {
742 { 0, 0, 0, 0 },
743 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
744 & ifmt_mvtachi_a, { 0x5071 }
745 },
252b5132
RH		 746/* mvtc $sr,$dcr */
747 {
748 { 0, 0, 0, 0 },
749 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
750 & ifmt_mvtc, { 0x10a0 }
751 },
752/* neg $dr,$sr */
753 {
754 { 0, 0, 0, 0 },
755 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
756 & ifmt_add, { 0x30 }
757 },
758/* nop */
759 {
760 { 0, 0, 0, 0 },
761 { { MNEM, 0 } },
762 & ifmt_nop, { 0x7000 }
763 },
764/* not $dr,$sr */
765 {
766 { 0, 0, 0, 0 },
767 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
768 & ifmt_add, { 0xb0 }
769 },
770/* rac */
771 {
772 { 0, 0, 0, 0 },
773 { { MNEM, 0 } },
774 & ifmt_nop, { 0x5090 }
775 },
1fa60b5d
DE		 776/* rac $accd,$accs,$imm1 */
777 {
778 { 0, 0, 0, 0 },
779 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
780 & ifmt_rac_dsi, { 0x5090 }
781 },
252b5132
RH		 782/* rach */
783 {
784 { 0, 0, 0, 0 },
785 { { MNEM, 0 } },
786 & ifmt_nop, { 0x5080 }
787 },
1fa60b5d
DE		 788/* rach $accd,$accs,$imm1 */
789 {
790 { 0, 0, 0, 0 },
791 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
792 & ifmt_rac_dsi, { 0x5080 }
793 },
252b5132
RH		 794/* rte */
795 {
796 { 0, 0, 0, 0 },
797 { { MNEM, 0 } },
798 & ifmt_nop, { 0x10d6 }
799 },
800/* seth $dr,$hash$hi16 */
801 {
802 { 0, 0, 0, 0 },
803 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
804 & ifmt_seth, { 0xd0c00000 }
805 },
806/* sll $dr,$sr */
807 {
808 { 0, 0, 0, 0 },
809 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
810 & ifmt_add, { 0x1040 }
811 },
812/* sll3 $dr,$sr,$simm16 */
813 {
814 { 0, 0, 0, 0 },
815 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
816 & ifmt_addv3, { 0x90c00000 }
817 },
818/* slli $dr,$uimm5 */
819 {
820 { 0, 0, 0, 0 },
821 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
822 & ifmt_slli, { 0x5040 }
823 },
824/* sra $dr,$sr */
825 {
826 { 0, 0, 0, 0 },
827 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
828 & ifmt_add, { 0x1020 }
829 },
830/* sra3 $dr,$sr,$simm16 */
831 {
832 { 0, 0, 0, 0 },
833 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
834 & ifmt_addv3, { 0x90a00000 }
835 },
836/* srai $dr,$uimm5 */
837 {
838 { 0, 0, 0, 0 },
839 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
840 & ifmt_slli, { 0x5020 }
841 },
842/* srl $dr,$sr */
843 {
844 { 0, 0, 0, 0 },
845 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
846 & ifmt_add, { 0x1000 }
847 },
848/* srl3 $dr,$sr,$simm16 */
849 {
850 { 0, 0, 0, 0 },
851 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
852 & ifmt_addv3, { 0x90800000 }
853 },
854/* srli $dr,$uimm5 */
855 {
856 { 0, 0, 0, 0 },
857 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
858 & ifmt_slli, { 0x5000 }
859 },
860/* st $src1,@$src2 */
861 {
862 { 0, 0, 0, 0 },
863 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
864 & ifmt_cmp, { 0x2040 }
865 },
866/* st $src1,@($slo16,$src2) */
867 {
868 { 0, 0, 0, 0 },
869 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
870 & ifmt_st_d, { 0xa0400000 }
871 },
872/* stb $src1,@$src2 */
873 {
874 { 0, 0, 0, 0 },
875 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
876 & ifmt_cmp, { 0x2000 }
877 },
878/* stb $src1,@($slo16,$src2) */
879 {
880 { 0, 0, 0, 0 },
881 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
882 & ifmt_st_d, { 0xa0000000 }
883 },
884/* sth $src1,@$src2 */
885 {
886 { 0, 0, 0, 0 },
887 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
888 & ifmt_cmp, { 0x2020 }
889 },
890/* sth $src1,@($slo16,$src2) */
891 {
892 { 0, 0, 0, 0 },
893 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
894 & ifmt_st_d, { 0xa0200000 }
895 },
896/* st $src1,@+$src2 */
897 {
898 { 0, 0, 0, 0 },
899 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
900 & ifmt_cmp, { 0x2060 }
901 },
902/* st $src1,@-$src2 */
903 {
904 { 0, 0, 0, 0 },
905 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
906 & ifmt_cmp, { 0x2070 }
907 },
908/* sub $dr,$sr */
909 {
910 { 0, 0, 0, 0 },
911 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
912 & ifmt_add, { 0x20 }
913 },
914/* subv $dr,$sr */
915 {
916 { 0, 0, 0, 0 },
917 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
918 & ifmt_add, { 0x0 }
919 },
920/* subx $dr,$sr */
921 {
922 { 0, 0, 0, 0 },
923 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
924 & ifmt_add, { 0x10 }
925 },
926/* trap $uimm4 */
927 {
928 { 0, 0, 0, 0 },
929 { { MNEM, ' ', OP (UIMM4), 0 } },
930 & ifmt_trap, { 0x10f0 }
931 },
932/* unlock $src1,@$src2 */
933 {
934 { 0, 0, 0, 0 },
935 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
936 & ifmt_cmp, { 0x2050 }
937 },
1fa60b5d
DE		 938/* satb $dr,$sr */
939 {
940 { 0, 0, 0, 0 },
941 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
942 & ifmt_satb, { 0x80600300 }
943 },
944/* sath $dr,$sr */
945 {
946 { 0, 0, 0, 0 },
947 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
948 & ifmt_satb, { 0x80600200 }
949 },
950/* sat $dr,$sr */
951 {
952 { 0, 0, 0, 0 },
953 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
954 & ifmt_satb, { 0x80600000 }
955 },
956/* pcmpbz $src2 */
957 {
958 { 0, 0, 0, 0 },
959 { { MNEM, ' ', OP (SRC2), 0 } },
960 & ifmt_cmpz, { 0x370 }
961 },
962/* sadd */
963 {
964 { 0, 0, 0, 0 },
965 { { MNEM, 0 } },
966 & ifmt_nop, { 0x50e4 }
967 },
968/* macwu1 $src1,$src2 */
969 {
970 { 0, 0, 0, 0 },
971 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
972 & ifmt_cmp, { 0x50b0 }
973 },
974/* msblo $src1,$src2 */
975 {
976 { 0, 0, 0, 0 },
977 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
978 & ifmt_cmp, { 0x50d0 }
979 },
980/* mulwu1 $src1,$src2 */
981 {
982 { 0, 0, 0, 0 },
983 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
984 & ifmt_cmp, { 0x50a0 }
985 },
986/* maclh1 $src1,$src2 */
987 {
988 { 0, 0, 0, 0 },
989 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
990 & ifmt_cmp, { 0x50c0 }
991 },
992/* sc */
993 {
994 { 0, 0, 0, 0 },
995 { { MNEM, 0 } },
996 & ifmt_nop, { 0x7401 }
997 },
998/* snc */
999 {
1000 { 0, 0, 0, 0 },
1001 { { MNEM, 0 } },
1002 & ifmt_nop, { 0x7501 }
1003 },
252b5132
RH		 1004};
1005
1006#undef A
252b5132 1007#undef OPERAND
b3466c39 1008#undef MNEM
252b5132
RH		 1009#undef OP
1010
1011/* Formats for ALIAS macro-insns. */
1012
b3466c39
DB		 1013#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1014#define F(f) & m32r_cgen_ifld_table[M32R_##f]
1015#else
1016#define F(f) & m32r_cgen_ifld_table[M32R_/**/f]
1017#endif
252b5132 1018static const CGEN_IFMT ifmt_bc8r = {
6bb95a0f 1019 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
252b5132
RH		 1020};
1021
1022static const CGEN_IFMT ifmt_bc24r = {
6bb95a0f 1023 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
252b5132
RH		 1024};
1025
1026static const CGEN_IFMT ifmt_bl8r = {
6bb95a0f 1027 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
252b5132
RH		 1028};
1029
1030static const CGEN_IFMT ifmt_bl24r = {
6bb95a0f 1031 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
252b5132
RH		 1032};
1033
1fa60b5d 1034static const CGEN_IFMT ifmt_bcl8r = {
6bb95a0f 1035 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1fa60b5d
DE		 1036};
1037
1038static const CGEN_IFMT ifmt_bcl24r = {
6bb95a0f 1039 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1fa60b5d
DE		 1040};
1041
252b5132 1042static const CGEN_IFMT ifmt_bnc8r = {
6bb95a0f 1043 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
252b5132
RH		 1044};
1045
1046static const CGEN_IFMT ifmt_bnc24r = {
6bb95a0f 1047 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
252b5132
RH		 1048};
1049
1050static const CGEN_IFMT ifmt_bra8r = {
6bb95a0f 1051 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
252b5132
RH		 1052};
1053
1054static const CGEN_IFMT ifmt_bra24r = {
6bb95a0f 1055 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
252b5132
RH		 1056};
1057
1fa60b5d 1058static const CGEN_IFMT ifmt_bncl8r = {
6bb95a0f 1059 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1fa60b5d
DE		 1060};
1061
1062static const CGEN_IFMT ifmt_bncl24r = {
6bb95a0f 1063 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1fa60b5d
DE		 1064};
1065
252b5132 1066static const CGEN_IFMT ifmt_ld_2 = {
6bb95a0f 1067 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1068};
1069
1070static const CGEN_IFMT ifmt_ld_d2 = {
6bb95a0f 1071 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1072};
1073
1074static const CGEN_IFMT ifmt_ldb_2 = {
6bb95a0f 1075 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1076};
1077
1078static const CGEN_IFMT ifmt_ldb_d2 = {
6bb95a0f 1079 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1080};
1081
1082static const CGEN_IFMT ifmt_ldh_2 = {
6bb95a0f 1083 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1084};
1085
1086static const CGEN_IFMT ifmt_ldh_d2 = {
6bb95a0f 1087 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1088};
1089
1090static const CGEN_IFMT ifmt_ldub_2 = {
6bb95a0f 1091 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1092};
1093
1094static const CGEN_IFMT ifmt_ldub_d2 = {
6bb95a0f 1095 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1096};
1097
1098static const CGEN_IFMT ifmt_lduh_2 = {
6bb95a0f 1099 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1100};
1101
1102static const CGEN_IFMT ifmt_lduh_d2 = {
6bb95a0f 1103 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1104};
1105
1106static const CGEN_IFMT ifmt_pop = {
6bb95a0f 1107 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1108};
1109
1110static const CGEN_IFMT ifmt_ldi8a = {
6bb95a0f 1111 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
252b5132
RH		 1112};
1113
1114static const CGEN_IFMT ifmt_ldi16a = {
6bb95a0f 1115 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1116};
1117
1fa60b5d 1118static const CGEN_IFMT ifmt_rac_d = {
6bb95a0f 1119 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1fa60b5d
DE		 1120};
1121
1122static const CGEN_IFMT ifmt_rac_ds = {
6bb95a0f 1123 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1fa60b5d
DE		 1124};
1125
1126static const CGEN_IFMT ifmt_rach_d = {
6bb95a0f 1127 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1fa60b5d
DE		 1128};
1129
1130static const CGEN_IFMT ifmt_rach_ds = {
6bb95a0f 1131 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1fa60b5d
DE		 1132};
1133
252b5132 1134static const CGEN_IFMT ifmt_st_2 = {
6bb95a0f 1135 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1136};
1137
1138static const CGEN_IFMT ifmt_st_d2 = {
6bb95a0f 1139 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1140};
1141
1142static const CGEN_IFMT ifmt_stb_2 = {
6bb95a0f 1143 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1144};
1145
1146static const CGEN_IFMT ifmt_stb_d2 = {
6bb95a0f 1147 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1148};
1149
1150static const CGEN_IFMT ifmt_sth_2 = {
6bb95a0f 1151 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1152};
1153
1154static const CGEN_IFMT ifmt_sth_d2 = {
6bb95a0f 1155 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
252b5132
RH		 1156};
1157
1158static const CGEN_IFMT ifmt_push = {
6bb95a0f 1159 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
252b5132
RH		 1160};
1161
1162#undef F
1163
1164/* Each non-simple macro entry points to an array of expansion possibilities. */
1165
b3466c39
DB		 1166#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1167#define A(a) (1 << CGEN_INSN_##a)
1168#else
1169#define A(a) (1 << CGEN_INSN_/**/a)
1170#endif
1171#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1172#define OPERAND(op) M32R_OPERAND_##op
1173#else
1174#define OPERAND(op) M32R_OPERAND_/**/op
1175#endif
252b5132 1176#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
252b5132
RH		 1177#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1178
1179/* The macro instruction table. */
1180
1181static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
1182{
1183/* bc $disp8 */
1184 {
1185 -1, "bc8r", "bc", 16,
1fa60b5d 1186 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1187 },
1188/* bc $disp24 */
1189 {
1190 -1, "bc24r", "bc", 32,
1fa60b5d 1191 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1192 },
1193/* bl $disp8 */
1194 {
1195 -1, "bl8r", "bl", 16,
1fa60b5d 1196 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1197 },
1198/* bl $disp24 */
1199 {
1200 -1, "bl24r", "bl", 32,
1fa60b5d
DE		 1201 { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1202 },
1203/* bcl $disp8 */
1204 {
1205 -1, "bcl8r", "bcl", 16,
1206 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1207 },
1208/* bcl $disp24 */
1209 {
1210 -1, "bcl24r", "bcl", 32,
1211 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
252b5132
RH		 1212 },
1213/* bnc $disp8 */
1214 {
1215 -1, "bnc8r", "bnc", 16,
1fa60b5d 1216 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1217 },
1218/* bnc $disp24 */
1219 {
1220 -1, "bnc24r", "bnc", 32,
1fa60b5d 1221 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1222 },
1223/* bra $disp8 */
1224 {
1225 -1, "bra8r", "bra", 16,
1fa60b5d 1226 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1227 },
1228/* bra $disp24 */
1229 {
1230 -1, "bra24r", "bra", 32,
1fa60b5d
DE		 1231 { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1232 },
1233/* bncl $disp8 */
1234 {
1235 -1, "bncl8r", "bncl", 16,
1236 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1237 },
1238/* bncl $disp24 */
1239 {
1240 -1, "bncl24r", "bncl", 32,
1241 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
252b5132
RH		 1242 },
1243/* ld $dr,@($sr) */
1244 {
1245 -1, "ld-2", "ld", 16,
1fa60b5d 1246 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1247 },
1248/* ld $dr,@($sr,$slo16) */
1249 {
1250 -1, "ld-d2", "ld", 32,
1fa60b5d 1251 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1252 },
1253/* ldb $dr,@($sr) */
1254 {
1255 -1, "ldb-2", "ldb", 16,
1fa60b5d 1256 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1257 },
1258/* ldb $dr,@($sr,$slo16) */
1259 {
1260 -1, "ldb-d2", "ldb", 32,
1fa60b5d 1261 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1262 },
1263/* ldh $dr,@($sr) */
1264 {
1265 -1, "ldh-2", "ldh", 16,
1fa60b5d 1266 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1267 },
1268/* ldh $dr,@($sr,$slo16) */
1269 {
1270 -1, "ldh-d2", "ldh", 32,
1fa60b5d 1271 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1272 },
1273/* ldub $dr,@($sr) */
1274 {
1275 -1, "ldub-2", "ldub", 16,
1fa60b5d 1276 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1277 },
1278/* ldub $dr,@($sr,$slo16) */
1279 {
1280 -1, "ldub-d2", "ldub", 32,
1fa60b5d 1281 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1282 },
1283/* lduh $dr,@($sr) */
1284 {
1285 -1, "lduh-2", "lduh", 16,
1fa60b5d 1286 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1287 },
1288/* lduh $dr,@($sr,$slo16) */
1289 {
1290 -1, "lduh-d2", "lduh", 32,
1fa60b5d 1291 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1292 },
1293/* pop $dr */
1294 {
1295 -1, "pop", "pop", 16,
1fa60b5d 1296 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1297 },
1298/* ldi $dr,$simm8 */
1299 {
1300 -1, "ldi8a", "ldi", 16,
1fa60b5d 1301 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
252b5132
RH		 1302 },
1303/* ldi $dr,$hash$slo16 */
1304 {
1305 -1, "ldi16a", "ldi", 32,
1fa60b5d
DE		 1306 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1307 },
1308/* rac $accd */
1309 {
1310 -1, "rac-d", "rac", 16,
1311 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
1312 },
1313/* rac $accd,$accs */
1314 {
1315 -1, "rac-ds", "rac", 16,
1316 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
1317 },
1318/* rach $accd */
1319 {
1320 -1, "rach-d", "rach", 16,
1321 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
1322 },
1323/* rach $accd,$accs */
1324 {
1325 -1, "rach-ds", "rach", 16,
1326 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
252b5132
RH		 1327 },
1328/* st $src1,@($src2) */
1329 {
1330 -1, "st-2", "st", 16,
1fa60b5d 1331 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1332 },
1333/* st $src1,@($src2,$slo16) */
1334 {
1335 -1, "st-d2", "st", 32,
1fa60b5d 1336 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1337 },
1338/* stb $src1,@($src2) */
1339 {
1340 -1, "stb-2", "stb", 16,
1fa60b5d 1341 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1342 },
1343/* stb $src1,@($src2,$slo16) */
1344 {
1345 -1, "stb-d2", "stb", 32,
1fa60b5d 1346 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1347 },
1348/* sth $src1,@($src2) */
1349 {
1350 -1, "sth-2", "sth", 16,
1fa60b5d 1351 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
252b5132
RH		 1352 },
1353/* sth $src1,@($src2,$slo16) */
1354 {
1355 -1, "sth-d2", "sth", 32,
1fa60b5d 1356 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1357 },
1358/* push $src1 */
1359 {
1360 -1, "push", "push", 16,
1fa60b5d 1361 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
252b5132
RH		 1362 },
1363};
1364
1365/* The macro instruction opcode table. */
1366
1367static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
1368{
1369/* bc $disp8 */
1370 {
1371 { 0, 0, 0, 0 },
1372 { { MNEM, ' ', OP (DISP8), 0 } },
1373 & ifmt_bc8r, { 0x7c00 }
1374 },
1375/* bc $disp24 */
1376 {
1377 { 0, 0, 0, 0 },
1378 { { MNEM, ' ', OP (DISP24), 0 } },
1379 & ifmt_bc24r, { 0xfc000000 }
1380 },
1381/* bl $disp8 */
1382 {
1383 { 0, 0, 0, 0 },
1384 { { MNEM, ' ', OP (DISP8), 0 } },
1385 & ifmt_bl8r, { 0x7e00 }
1386 },
1387/* bl $disp24 */
1388 {
1389 { 0, 0, 0, 0 },
1390 { { MNEM, ' ', OP (DISP24), 0 } },
1391 & ifmt_bl24r, { 0xfe000000 }
1392 },
1fa60b5d
DE		 1393/* bcl $disp8 */
1394 {
1395 { 0, 0, 0, 0 },
1396 { { MNEM, ' ', OP (DISP8), 0 } },
1397 & ifmt_bcl8r, { 0x7800 }
1398 },
1399/* bcl $disp24 */
1400 {
1401 { 0, 0, 0, 0 },
1402 { { MNEM, ' ', OP (DISP24), 0 } },
1403 & ifmt_bcl24r, { 0xf8000000 }
1404 },
252b5132
RH		 1405/* bnc $disp8 */
1406 {
1407 { 0, 0, 0, 0 },
1408 { { MNEM, ' ', OP (DISP8), 0 } },
1409 & ifmt_bnc8r, { 0x7d00 }
1410 },
1411/* bnc $disp24 */
1412 {
1413 { 0, 0, 0, 0 },
1414 { { MNEM, ' ', OP (DISP24), 0 } },
1415 & ifmt_bnc24r, { 0xfd000000 }
1416 },
1417/* bra $disp8 */
1418 {
1419 { 0, 0, 0, 0 },
1420 { { MNEM, ' ', OP (DISP8), 0 } },
1421 & ifmt_bra8r, { 0x7f00 }
1422 },
1423/* bra $disp24 */
1424 {
1425 { 0, 0, 0, 0 },
1426 { { MNEM, ' ', OP (DISP24), 0 } },
1427 & ifmt_bra24r, { 0xff000000 }
1428 },
1fa60b5d
DE		 1429/* bncl $disp8 */
1430 {
1431 { 0, 0, 0, 0 },
1432 { { MNEM, ' ', OP (DISP8), 0 } },
1433 & ifmt_bncl8r, { 0x7900 }
1434 },
1435/* bncl $disp24 */
1436 {
1437 { 0, 0, 0, 0 },
1438 { { MNEM, ' ', OP (DISP24), 0 } },
1439 & ifmt_bncl24r, { 0xf9000000 }
1440 },
252b5132
RH		 1441/* ld $dr,@($sr) */
1442 {
1443 { 0, 0, 0, 0 },
1444 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1445 & ifmt_ld_2, { 0x20c0 }
1446 },
1447/* ld $dr,@($sr,$slo16) */
1448 {
1449 { 0, 0, 0, 0 },
1450 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1451 & ifmt_ld_d2, { 0xa0c00000 }
1452 },
1453/* ldb $dr,@($sr) */
1454 {
1455 { 0, 0, 0, 0 },
1456 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1457 & ifmt_ldb_2, { 0x2080 }
1458 },
1459/* ldb $dr,@($sr,$slo16) */
1460 {
1461 { 0, 0, 0, 0 },
1462 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1463 & ifmt_ldb_d2, { 0xa0800000 }
1464 },
1465/* ldh $dr,@($sr) */
1466 {
1467 { 0, 0, 0, 0 },
1468 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1469 & ifmt_ldh_2, { 0x20a0 }
1470 },
1471/* ldh $dr,@($sr,$slo16) */
1472 {
1473 { 0, 0, 0, 0 },
1474 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1475 & ifmt_ldh_d2, { 0xa0a00000 }
1476 },
1477/* ldub $dr,@($sr) */
1478 {
1479 { 0, 0, 0, 0 },
1480 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1481 & ifmt_ldub_2, { 0x2090 }
1482 },
1483/* ldub $dr,@($sr,$slo16) */
1484 {
1485 { 0, 0, 0, 0 },
1486 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1487 & ifmt_ldub_d2, { 0xa0900000 }
1488 },
1489/* lduh $dr,@($sr) */
1490 {
1491 { 0, 0, 0, 0 },
1492 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1493 & ifmt_lduh_2, { 0x20b0 }
1494 },
1495/* lduh $dr,@($sr,$slo16) */
1496 {
1497 { 0, 0, 0, 0 },
1498 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1499 & ifmt_lduh_d2, { 0xa0b00000 }
1500 },
1501/* pop $dr */
1502 {
1503 { 0, 0, 0, 0 },
1504 { { MNEM, ' ', OP (DR), 0 } },
1505 & ifmt_pop, { 0x20ef }
1506 },
1507/* ldi $dr,$simm8 */
1508 {
1509 { 0, 0, 0, 0 },
1510 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1511 & ifmt_ldi8a, { 0x6000 }
1512 },
1513/* ldi $dr,$hash$slo16 */
1514 {
1515 { 0, 0, 0, 0 },
1516 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1517 & ifmt_ldi16a, { 0x90f00000 }
1518 },
1fa60b5d
DE		 1519/* rac $accd */
1520 {
1521 { 0, 0, 0, 0 },
1522 { { MNEM, ' ', OP (ACCD), 0 } },
1523 & ifmt_rac_d, { 0x5090 }
1524 },
1525/* rac $accd,$accs */
1526 {
1527 { 0, 0, 0, 0 },
1528 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1529 & ifmt_rac_ds, { 0x5090 }
1530 },
1531/* rach $accd */
1532 {
1533 { 0, 0, 0, 0 },
1534 { { MNEM, ' ', OP (ACCD), 0 } },
1535 & ifmt_rach_d, { 0x5080 }
1536 },
1537/* rach $accd,$accs */
1538 {
1539 { 0, 0, 0, 0 },
1540 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1541 & ifmt_rach_ds, { 0x5080 }
1542 },
252b5132
RH		 1543/* st $src1,@($src2) */
1544 {
1545 { 0, 0, 0, 0 },
1546 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1547 & ifmt_st_2, { 0x2040 }
1548 },
1549/* st $src1,@($src2,$slo16) */
1550 {
1551 { 0, 0, 0, 0 },
1552 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1553 & ifmt_st_d2, { 0xa0400000 }
1554 },
1555/* stb $src1,@($src2) */
1556 {
1557 { 0, 0, 0, 0 },
1558 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1559 & ifmt_stb_2, { 0x2000 }
1560 },
1561/* stb $src1,@($src2,$slo16) */
1562 {
1563 { 0, 0, 0, 0 },
1564 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1565 & ifmt_stb_d2, { 0xa0000000 }
1566 },
1567/* sth $src1,@($src2) */
1568 {
1569 { 0, 0, 0, 0 },
1570 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1571 & ifmt_sth_2, { 0x2020 }
1572 },
1573/* sth $src1,@($src2,$slo16) */
1574 {
1575 { 0, 0, 0, 0 },
1576 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1577 & ifmt_sth_d2, { 0xa0200000 }
1578 },
1579/* push $src1 */
1580 {
1581 { 0, 0, 0, 0 },
1582 { { MNEM, ' ', OP (SRC1), 0 } },
1583 & ifmt_push, { 0x207f }
1584 },
1585};
1586
1587#undef A
252b5132 1588#undef OPERAND
b3466c39 1589#undef MNEM
252b5132
RH		 1590#undef OP
1591
1592#ifndef CGEN_ASM_HASH_P
1593#define CGEN_ASM_HASH_P(insn) 1
1594#endif
1595
1596#ifndef CGEN_DIS_HASH_P
1597#define CGEN_DIS_HASH_P(insn) 1
1598#endif
1599
1600/* Return non-zero if INSN is to be added to the hash table.
1601 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1602
1603static int
1604asm_hash_insn_p (insn)
fc05c67f 1605 const CGEN_INSN *insn ATTRIBUTE_UNUSED;
252b5132
RH		 1606{
1607 return CGEN_ASM_HASH_P (insn);
1608}
1609
1610static int
1611dis_hash_insn_p (insn)
1612 const CGEN_INSN *insn;
1613{
1614 /* If building the hash table and the NO-DIS attribute is present,
1615 ignore. */
1616 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
1617 return 0;
1618 return CGEN_DIS_HASH_P (insn);
1619}
1620
1621#ifndef CGEN_ASM_HASH
1622#define CGEN_ASM_HASH_SIZE 127
1623#ifdef CGEN_MNEMONIC_OPERANDS
1624#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1625#else
1626#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1627#endif
1628#endif
1629
1630/* It doesn't make much sense to provide a default here,
1631 but while this is under development we do.
1632 BUFFER is a pointer to the bytes of the insn, target order.
1633 VALUE is the first base_insn_bitsize bits as an int in host order. */
1634
1635#ifndef CGEN_DIS_HASH
1636#define CGEN_DIS_HASH_SIZE 256
1637#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1638#endif
1639
1640/* The result is the hash value of the insn.
1641 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1642
1643static unsigned int
1644asm_hash_insn (mnem)
1645 const char * mnem;
1646{
1647 return CGEN_ASM_HASH (mnem);
1648}
1649
1650/* BUF is a pointer to the bytes of the insn, target order.
1651 VALUE is the first base_insn_bitsize bits as an int in host order. */
1652
1653static unsigned int
1654dis_hash_insn (buf, value)
1655 const char * buf;
fc05c67f 1656 CGEN_INSN_INT value ATTRIBUTE_UNUSED;
252b5132
RH		 1657{
1658 return CGEN_DIS_HASH (buf, value);
1659}
1660
1661/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1662
1663static void
1664set_fields_bitsize (fields, size)
1665 CGEN_FIELDS *fields;
1666 int size;
1667{
1668 CGEN_FIELDS_BITSIZE (fields) = size;
1669}
1670
1671/* Function to call before using the operand instance table.
1672 This plugs the opcode entries and macro instructions into the cpu table. */
1673
1674void
1675m32r_cgen_init_opcode_table (cd)
1676 CGEN_CPU_DESC cd;
1677{
1678 int i;
1679 int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
1680 sizeof (m32r_cgen_macro_insn_table[0]));
1681 const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
1682 const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
1683 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
1684 memset (insns, 0, num_macros * sizeof (CGEN_INSN));
1685 for (i = 0; i < num_macros; ++i)
1686 {
1687 insns[i].base = &ib[i];
1688 insns[i].opcode = &oc[i];
fc7bc883 1689 m32r_cgen_build_insn_regex (& insns[i]);
252b5132
RH		 1690 }
1691 cd->macro_insn_table.init_entries = insns;
1692 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
1693 cd->macro_insn_table.num_init_entries = num_macros;
1694
1695 oc = & m32r_cgen_insn_opcode_table[0];
1696 insns = (CGEN_INSN *) cd->insn_table.init_entries;
1697 for (i = 0; i < MAX_INSNS; ++i)
fc7bc883
RH		 1698 {
1699 insns[i].opcode = &oc[i];
1700 m32r_cgen_build_insn_regex (& insns[i]);
1701 }
252b5132
RH		 1702
1703 cd->sizeof_fields = sizeof (CGEN_FIELDS);
1704 cd->set_fields_bitsize = set_fields_bitsize;
1705
1706 cd->asm_hash_p = asm_hash_insn_p;
1707 cd->asm_hash = asm_hash_insn;
1708 cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
1709
1710 cd->dis_hash_p = dis_hash_insn_p;
1711 cd->dis_hash = dis_hash_insn;
1712 cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
1713}
GDB Binutils - Deliverables
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