Commit | Line | Data |
---|---|---|
23cf992f NC |
1 | /* Instruction description for m32r. |
2 | ||
0499462e | 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
7c26196f | 4 | |
5d07b6cf | 5 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
23cf992f NC |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
0499462e DE |
25 | #ifndef M32R_OPC_H |
26 | #define M32R_OPC_H | |
23cf992f NC |
27 | |
28 | #define CGEN_ARCH m32r | |
35e689de | 29 | |
5730d39d | 30 | /* Given symbol S, return m32r_cgen_<S>. */ |
0bf55db8 | 31 | #define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s) |
23cf992f | 32 | |
35e689de | 33 | /* Selected cpu families. */ |
5730d39d | 34 | #define HAVE_CPU_M32RBF |
7c26196f | 35 | /* start-sanitize-m32rx */ |
5730d39d | 36 | #define HAVE_CPU_M32RXF |
7c26196f | 37 | /* end-sanitize-m32rx */ |
35e689de | 38 | |
5730d39d | 39 | #define CGEN_INSN_LSB0_P 0 |
23cf992f NC |
40 | #define CGEN_WORD_BITSIZE 32 |
41 | #define CGEN_DEFAULT_INSN_BITSIZE 32 | |
42 | #define CGEN_BASE_INSN_BITSIZE 32 | |
fbc8134d | 43 | #define CGEN_MIN_INSN_BITSIZE 16 |
23cf992f NC |
44 | #define CGEN_MAX_INSN_BITSIZE 32 |
45 | #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) | |
46 | #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) | |
fbc8134d | 47 | #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8) |
23cf992f | 48 | #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) |
5730d39d | 49 | #define CGEN_INT_INSN_P 1 |
23cf992f | 50 | |
23cf992f NC |
51 | /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ |
52 | ||
53 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. | |
54 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands | |
55 | we can't hash on everything up to the space. */ | |
56 | #define CGEN_MNEMONIC_OPERANDS | |
0499462e DE |
57 | /* Maximum number of operands any insn or macro-insn has. */ |
58 | #define CGEN_MAX_INSN_OPERANDS 16 | |
23cf992f | 59 | |
5730d39d DE |
60 | /* Maximum number of fields in an instruction. */ |
61 | #define CGEN_MAX_IFMT_OPERANDS 7 | |
62 | ||
23cf992f NC |
63 | /* Enums. */ |
64 | ||
65 | /* Enum declaration for insn format enums. */ | |
66 | typedef enum insn_op1 { | |
7c26196f DE |
67 | OP1_0, OP1_1, OP1_2, OP1_3 |
68 | , OP1_4, OP1_5, OP1_6, OP1_7 | |
69 | , OP1_8, OP1_9, OP1_10, OP1_11 | |
70 | , OP1_12, OP1_13, OP1_14, OP1_15 | |
23cf992f NC |
71 | } INSN_OP1; |
72 | ||
73 | /* Enum declaration for op2 enums. */ | |
74 | typedef enum insn_op2 { | |
7c26196f DE |
75 | OP2_0, OP2_1, OP2_2, OP2_3 |
76 | , OP2_4, OP2_5, OP2_6, OP2_7 | |
77 | , OP2_8, OP2_9, OP2_10, OP2_11 | |
78 | , OP2_12, OP2_13, OP2_14, OP2_15 | |
23cf992f NC |
79 | } INSN_OP2; |
80 | ||
0499462e DE |
81 | /* Enum declaration for general registers. */ |
82 | typedef enum h_gr { | |
83 | H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 | |
84 | , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 | |
85 | , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 | |
86 | , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 | |
87 | , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 | |
88 | } H_GR; | |
89 | ||
90 | /* Enum declaration for control registers. */ | |
91 | typedef enum h_cr { | |
92 | H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 | |
5730d39d DE |
93 | , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0 |
94 | , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4 | |
95 | , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8 | |
96 | , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12 | |
97 | , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 | |
0499462e DE |
98 | } H_CR; |
99 | ||
100 | /* start-sanitize-m32rx */ | |
101 | /* Enum declaration for accumulators. */ | |
102 | typedef enum h_accums { | |
103 | H_ACCUMS_A0, H_ACCUMS_A1 | |
104 | } H_ACCUMS; | |
105 | ||
106 | /* end-sanitize-m32rx */ | |
5730d39d | 107 | /* Attributes. */ |
23cf992f NC |
108 | |
109 | /* Enum declaration for machine type selection. */ | |
110 | typedef enum mach_attr { | |
5730d39d | 111 | MACH_BASE, MACH_M32R |
7c26196f DE |
112 | /* start-sanitize-m32rx */ |
113 | , MACH_M32RX | |
114 | /* end-sanitize-m32rx */ | |
115 | , MACH_MAX | |
23cf992f NC |
116 | } MACH_ATTR; |
117 | ||
7c26196f DE |
118 | /* start-sanitize-m32rx */ |
119 | /* Enum declaration for parallel execution pipeline selection. */ | |
120 | typedef enum pipe_attr { | |
121 | PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS | |
122 | } PIPE_ATTR; | |
123 | ||
124 | /* end-sanitize-m32rx */ | |
125 | /* Number of architecture variants. */ | |
126 | #define MAX_MACHS ((int) MACH_MAX) | |
127 | ||
5730d39d | 128 | /* Ifield attribute indices. */ |
7c26196f | 129 | |
5730d39d DE |
130 | /* Enum declaration for cgen_ifld attrs. */ |
131 | typedef enum cgen_ifld_attr { | |
132 | CGEN_IFLD_MACH, CGEN_IFLD_VIRTUAL, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR | |
133 | , CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_RELOC | |
134 | } CGEN_IFLD_ATTR; | |
135 | ||
136 | /* Number of non-boolean elements in cgen_ifld. */ | |
137 | #define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_VIRTUAL) | |
138 | ||
139 | /* Enum declaration for m32r ifield types. */ | |
140 | typedef enum ifield_type { | |
141 | M32R_F_NIL, M32R_F_OP1, M32R_F_OP2, M32R_F_COND | |
142 | , M32R_F_R1, M32R_F_R2, M32R_F_SIMM8, M32R_F_SIMM16 | |
143 | , M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM16 | |
144 | , M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16 | |
145 | , M32R_F_DISP24 | |
146 | /* start-sanitize-m32rx */ | |
147 | , M32R_F_OP23 | |
148 | /* end-sanitize-m32rx */ | |
149 | /* start-sanitize-m32rx */ | |
150 | , M32R_F_OP3 | |
151 | /* end-sanitize-m32rx */ | |
152 | /* start-sanitize-m32rx */ | |
153 | , M32R_F_ACC | |
154 | /* end-sanitize-m32rx */ | |
155 | /* start-sanitize-m32rx */ | |
156 | , M32R_F_ACCS | |
157 | /* end-sanitize-m32rx */ | |
158 | /* start-sanitize-m32rx */ | |
159 | , M32R_F_ACCD | |
160 | /* end-sanitize-m32rx */ | |
161 | /* start-sanitize-m32rx */ | |
162 | , M32R_F_BITS67 | |
163 | /* end-sanitize-m32rx */ | |
164 | /* start-sanitize-m32rx */ | |
165 | , M32R_F_BIT14 | |
166 | /* end-sanitize-m32rx */ | |
167 | /* start-sanitize-m32rx */ | |
168 | , M32R_F_IMM1 | |
169 | /* end-sanitize-m32rx */ | |
170 | , M32R_F_MAX | |
171 | } IFIELD_TYPE; | |
172 | ||
173 | #define MAX_IFLD ((int) M32R_F_MAX) | |
ab0bd049 | 174 | |
5730d39d DE |
175 | /* Hardware attribute indices. */ |
176 | ||
177 | /* Enum declaration for cgen_hw attrs. */ | |
178 | typedef enum cgen_hw_attr { | |
179 | CGEN_HW_MACH, CGEN_HW_VIRTUAL, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED | |
180 | , CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE | |
181 | } CGEN_HW_ATTR; | |
182 | ||
183 | /* Number of non-boolean elements in cgen_hw. */ | |
184 | #define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_VIRTUAL) | |
185 | ||
186 | /* Enum declaration for m32r hardware types. */ | |
187 | typedef enum hw_type { | |
188 | HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT | |
189 | , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16 | |
190 | , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM | |
191 | /* start-sanitize-m32rx */ | |
192 | , HW_H_ACCUMS | |
193 | /* end-sanitize-m32rx */ | |
194 | , HW_H_COND, HW_H_PSW, HW_H_BPSW, HW_H_BBPSW | |
195 | , HW_H_LOCK, HW_MAX | |
196 | } HW_TYPE; | |
197 | ||
198 | #define MAX_HW ((int) HW_MAX) | |
199 | ||
200 | /* Operand attribute indices. */ | |
23cf992f NC |
201 | |
202 | /* Enum declaration for cgen_operand attrs. */ | |
203 | typedef enum cgen_operand_attr { | |
5730d39d DE |
204 | CGEN_OPERAND_MACH, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR |
205 | , CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX | |
206 | , CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX | |
23cf992f NC |
207 | } CGEN_OPERAND_ATTR; |
208 | ||
7c26196f | 209 | /* Number of non-boolean elements in cgen_operand. */ |
5730d39d DE |
210 | #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_VIRTUAL) |
211 | ||
212 | /* Enum declaration for m32r operand types. */ | |
213 | typedef enum cgen_operand_type { | |
214 | M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 | |
215 | , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 | |
216 | , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16 | |
217 | /* start-sanitize-m32rx */ | |
218 | , M32R_OPERAND_IMM1 | |
219 | /* end-sanitize-m32rx */ | |
220 | /* start-sanitize-m32rx */ | |
221 | , M32R_OPERAND_ACCD | |
222 | /* end-sanitize-m32rx */ | |
223 | /* start-sanitize-m32rx */ | |
224 | , M32R_OPERAND_ACCS | |
225 | /* end-sanitize-m32rx */ | |
226 | /* start-sanitize-m32rx */ | |
227 | , M32R_OPERAND_ACC | |
228 | /* end-sanitize-m32rx */ | |
229 | , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16 | |
230 | , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24 | |
231 | , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX | |
232 | } CGEN_OPERAND_TYPE; | |
233 | ||
234 | /* Number of operands types. */ | |
235 | #define MAX_OPERANDS ((int) M32R_OPERAND_MAX) | |
236 | ||
237 | /* Maximum number of operands referenced by any insn. */ | |
238 | #define MAX_OPERAND_INSTANCES 11 | |
239 | ||
240 | /* Insn attribute indices. */ | |
7c26196f | 241 | |
23cf992f NC |
242 | /* Enum declaration for cgen_insn attrs. */ |
243 | typedef enum cgen_insn_attr { | |
7c26196f DE |
244 | CGEN_INSN_MACH |
245 | /* start-sanitize-m32rx */ | |
246 | , CGEN_INSN_PIPE | |
247 | /* end-sanitize-m32rx */ | |
5730d39d DE |
248 | , CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI |
249 | , CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX, CGEN_INSN_ALIAS | |
250 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT | |
251 | /* start-sanitize-m32rx */ | |
252 | , CGEN_INSN_SPECIAL | |
253 | /* end-sanitize-m32rx */ | |
23cf992f NC |
254 | } CGEN_INSN_ATTR; |
255 | ||
7c26196f | 256 | /* Number of non-boolean elements in cgen_insn. */ |
5730d39d | 257 | #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_VIRTUAL) |
7c26196f | 258 | |
23cf992f NC |
259 | /* Enum declaration for m32r instruction types. */ |
260 | typedef enum cgen_insn_type { | |
5730d39d | 261 | M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND |
0499462e DE |
262 | , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR |
263 | , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3 | |
264 | , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ | |
7c26196f | 265 | , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ |
0499462e | 266 | , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24 |
7c26196f DE |
267 | /* start-sanitize-m32rx */ |
268 | , M32R_INSN_BCL8 | |
269 | /* end-sanitize-m32rx */ | |
7c26196f DE |
270 | /* start-sanitize-m32rx */ |
271 | , M32R_INSN_BCL24 | |
272 | /* end-sanitize-m32rx */ | |
0499462e DE |
273 | , M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8 |
274 | , M32R_INSN_BRA24 | |
7c26196f DE |
275 | /* start-sanitize-m32rx */ |
276 | , M32R_INSN_BNCL8 | |
277 | /* end-sanitize-m32rx */ | |
7c26196f DE |
278 | /* start-sanitize-m32rx */ |
279 | , M32R_INSN_BNCL24 | |
280 | /* end-sanitize-m32rx */ | |
0499462e | 281 | , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI |
7c26196f DE |
282 | /* start-sanitize-m32rx */ |
283 | , M32R_INSN_CMPEQ | |
284 | /* end-sanitize-m32rx */ | |
285 | /* start-sanitize-m32rx */ | |
286 | , M32R_INSN_CMPZ | |
287 | /* end-sanitize-m32rx */ | |
288 | , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU | |
ab0bd049 DE |
289 | /* start-sanitize-m32rx */ |
290 | , M32R_INSN_DIVH | |
291 | /* end-sanitize-m32rx */ | |
7c26196f DE |
292 | /* start-sanitize-m32rx */ |
293 | , M32R_INSN_JC | |
294 | /* end-sanitize-m32rx */ | |
295 | /* start-sanitize-m32rx */ | |
296 | , M32R_INSN_JNC | |
297 | /* end-sanitize-m32rx */ | |
0499462e DE |
298 | , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D |
299 | , M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D | |
300 | , M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D | |
301 | , M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16 | |
302 | , M32R_INSN_LOCK, M32R_INSN_MACHI | |
7c26196f DE |
303 | /* start-sanitize-m32rx */ |
304 | , M32R_INSN_MACHI_A | |
305 | /* end-sanitize-m32rx */ | |
306 | , M32R_INSN_MACLO | |
307 | /* start-sanitize-m32rx */ | |
308 | , M32R_INSN_MACLO_A | |
309 | /* end-sanitize-m32rx */ | |
c2009f4a DE |
310 | , M32R_INSN_MACWHI |
311 | /* start-sanitize-m32rx */ | |
312 | , M32R_INSN_MACWHI_A | |
313 | /* end-sanitize-m32rx */ | |
314 | , M32R_INSN_MACWLO | |
315 | /* start-sanitize-m32rx */ | |
316 | , M32R_INSN_MACWLO_A | |
317 | /* end-sanitize-m32rx */ | |
318 | , M32R_INSN_MUL, M32R_INSN_MULHI | |
7c26196f DE |
319 | /* start-sanitize-m32rx */ |
320 | , M32R_INSN_MULHI_A | |
321 | /* end-sanitize-m32rx */ | |
322 | , M32R_INSN_MULLO | |
323 | /* start-sanitize-m32rx */ | |
324 | , M32R_INSN_MULLO_A | |
325 | /* end-sanitize-m32rx */ | |
c2009f4a DE |
326 | , M32R_INSN_MULWHI |
327 | /* start-sanitize-m32rx */ | |
328 | , M32R_INSN_MULWHI_A | |
329 | /* end-sanitize-m32rx */ | |
330 | , M32R_INSN_MULWLO | |
331 | /* start-sanitize-m32rx */ | |
332 | , M32R_INSN_MULWLO_A | |
333 | /* end-sanitize-m32rx */ | |
334 | , M32R_INSN_MV, M32R_INSN_MVFACHI | |
7c26196f DE |
335 | /* start-sanitize-m32rx */ |
336 | , M32R_INSN_MVFACHI_A | |
337 | /* end-sanitize-m32rx */ | |
338 | , M32R_INSN_MVFACLO | |
339 | /* start-sanitize-m32rx */ | |
340 | , M32R_INSN_MVFACLO_A | |
341 | /* end-sanitize-m32rx */ | |
342 | , M32R_INSN_MVFACMI | |
343 | /* start-sanitize-m32rx */ | |
344 | , M32R_INSN_MVFACMI_A | |
345 | /* end-sanitize-m32rx */ | |
346 | , M32R_INSN_MVFC, M32R_INSN_MVTACHI | |
347 | /* start-sanitize-m32rx */ | |
348 | , M32R_INSN_MVTACHI_A | |
349 | /* end-sanitize-m32rx */ | |
350 | , M32R_INSN_MVTACLO | |
351 | /* start-sanitize-m32rx */ | |
352 | , M32R_INSN_MVTACLO_A | |
353 | /* end-sanitize-m32rx */ | |
354 | , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT | |
355 | , M32R_INSN_RAC | |
ab0bd049 DE |
356 | /* start-sanitize-m32rx */ |
357 | , M32R_INSN_RAC_DSI | |
7c26196f DE |
358 | /* end-sanitize-m32rx */ |
359 | , M32R_INSN_RACH | |
ab0bd049 DE |
360 | /* start-sanitize-m32rx */ |
361 | , M32R_INSN_RACH_DSI | |
7c26196f | 362 | /* end-sanitize-m32rx */ |
0499462e DE |
363 | , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3 |
364 | , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI | |
365 | , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST | |
366 | , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH | |
367 | , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB | |
368 | , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK | |
7c26196f DE |
369 | /* start-sanitize-m32rx */ |
370 | , M32R_INSN_SATB | |
371 | /* end-sanitize-m32rx */ | |
372 | /* start-sanitize-m32rx */ | |
373 | , M32R_INSN_SATH | |
374 | /* end-sanitize-m32rx */ | |
375 | /* start-sanitize-m32rx */ | |
376 | , M32R_INSN_SAT | |
377 | /* end-sanitize-m32rx */ | |
378 | /* start-sanitize-m32rx */ | |
379 | , M32R_INSN_PCMPBZ | |
380 | /* end-sanitize-m32rx */ | |
381 | /* start-sanitize-m32rx */ | |
382 | , M32R_INSN_SADD | |
383 | /* end-sanitize-m32rx */ | |
384 | /* start-sanitize-m32rx */ | |
385 | , M32R_INSN_MACWU1 | |
386 | /* end-sanitize-m32rx */ | |
387 | /* start-sanitize-m32rx */ | |
388 | , M32R_INSN_MSBLO | |
389 | /* end-sanitize-m32rx */ | |
390 | /* start-sanitize-m32rx */ | |
391 | , M32R_INSN_MULWU1 | |
392 | /* end-sanitize-m32rx */ | |
393 | /* start-sanitize-m32rx */ | |
ab0bd049 | 394 | , M32R_INSN_MACLH1 |
7c26196f DE |
395 | /* end-sanitize-m32rx */ |
396 | /* start-sanitize-m32rx */ | |
397 | , M32R_INSN_SC | |
398 | /* end-sanitize-m32rx */ | |
399 | /* start-sanitize-m32rx */ | |
400 | , M32R_INSN_SNC | |
401 | /* end-sanitize-m32rx */ | |
402 | , M32R_INSN_MAX | |
23cf992f NC |
403 | } CGEN_INSN_TYPE; |
404 | ||
5730d39d DE |
405 | /* Index of `invalid' insn place holder. */ |
406 | #define CGEN_INSN_INVALID M32R_INSN_INVALID | |
23cf992f | 407 | /* Total number of insns in table. */ |
7c26196f | 408 | #define MAX_INSNS ((int) M32R_INSN_MAX) |
23cf992f NC |
409 | |
410 | /* cgen.h uses things we just defined. */ | |
411 | #include "opcode/cgen.h" | |
412 | ||
413 | /* This struct records data prior to insertion or after extraction. */ | |
ab0bd049 | 414 | struct cgen_fields |
5d07b6cf DE |
415 | { |
416 | long f_nil; | |
23cf992f NC |
417 | long f_op1; |
418 | long f_op2; | |
419 | long f_cond; | |
420 | long f_r1; | |
421 | long f_r2; | |
422 | long f_simm8; | |
423 | long f_simm16; | |
424 | long f_shift_op2; | |
425 | long f_uimm4; | |
426 | long f_uimm5; | |
427 | long f_uimm16; | |
428 | long f_uimm24; | |
429 | long f_hi16; | |
430 | long f_disp8; | |
431 | long f_disp16; | |
432 | long f_disp24; | |
7c26196f DE |
433 | /* start-sanitize-m32rx */ |
434 | long f_op23; | |
435 | /* end-sanitize-m32rx */ | |
436 | /* start-sanitize-m32rx */ | |
437 | long f_op3; | |
438 | /* end-sanitize-m32rx */ | |
439 | /* start-sanitize-m32rx */ | |
440 | long f_acc; | |
441 | /* end-sanitize-m32rx */ | |
442 | /* start-sanitize-m32rx */ | |
443 | long f_accs; | |
ab0bd049 DE |
444 | /* end-sanitize-m32rx */ |
445 | /* start-sanitize-m32rx */ | |
446 | long f_accd; | |
447 | /* end-sanitize-m32rx */ | |
448 | /* start-sanitize-m32rx */ | |
449 | long f_bits67; | |
450 | /* end-sanitize-m32rx */ | |
451 | /* start-sanitize-m32rx */ | |
452 | long f_bit14; | |
453 | /* end-sanitize-m32rx */ | |
454 | /* start-sanitize-m32rx */ | |
455 | long f_imm1; | |
7c26196f | 456 | /* end-sanitize-m32rx */ |
23cf992f | 457 | int length; |
ab0bd049 | 458 | }; |
23cf992f NC |
459 | |
460 | /* Attributes. */ | |
5730d39d | 461 | extern const CGEN_ATTR_TABLE m32r_cgen_hw_attr_table[]; |
23cf992f NC |
462 | extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; |
463 | extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; | |
464 | ||
ab0bd049 DE |
465 | /* Hardware decls. */ |
466 | ||
23cf992f NC |
467 | extern CGEN_KEYWORD m32r_cgen_opval_h_gr; |
468 | extern CGEN_KEYWORD m32r_cgen_opval_h_cr; | |
7c26196f DE |
469 | /* start-sanitize-m32rx */ |
470 | extern CGEN_KEYWORD m32r_cgen_opval_h_accums; | |
471 | /* end-sanitize-m32rx */ | |
23cf992f | 472 | |
c2009f4a | 473 | #define CGEN_INIT_PARSE(od) \ |
23cf992f NC |
474 | {\ |
475 | } | |
c2009f4a | 476 | #define CGEN_INIT_INSERT(od) \ |
23cf992f NC |
477 | {\ |
478 | } | |
c2009f4a | 479 | #define CGEN_INIT_EXTRACT(od) \ |
23cf992f NC |
480 | {\ |
481 | } | |
c2009f4a | 482 | #define CGEN_INIT_PRINT(od) \ |
23cf992f NC |
483 | {\ |
484 | } | |
485 | ||
486 | /* -- opc.h */ | |
487 | ||
488 | #undef CGEN_DIS_HASH_SIZE | |
489 | #define CGEN_DIS_HASH_SIZE 256 | |
490 | #undef CGEN_DIS_HASH | |
491 | #define X(b) (((unsigned char *) (b))[0] & 0xf0) | |
0499462e | 492 | #define CGEN_DIS_HASH(buffer, value) \ |
23cf992f NC |
493 | (X (buffer) | \ |
494 | (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ | |
495 | : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ | |
ab0bd049 | 496 | : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ |
23cf992f NC |
497 | : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) |
498 | ||
499 | /* -- */ | |
500 | ||
501 | ||
0499462e | 502 | #endif /* M32R_OPC_H */ |