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gdbtypes.h (TYPE_SELF_TYPE): Renamed from TYPE_DOMAIN_TYPE.
[deliverable/binutils-gdb.git] / opcodes / mep-dis.c
CommitLineData
bd2f2e55
DB		 1/* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
6
b90efa5b 7 Copyright (C) 1996-2015 Free Software Foundation, Inc.
bd2f2e55 8
9b201bb5 9 This file is part of libopcodes.
bd2f2e55 10
9b201bb5 11 This library is free software; you can redistribute it and/or modify
bd2f2e55 12 it under the terms of the GNU General Public License as published by
9b201bb5 13 the Free Software Foundation; either version 3, or (at your option)
bd2f2e55
DB		 14 any later version.
15
9b201bb5
NC		 16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
bd2f2e55
DB		 20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
34#include "libiberty.h"
35#include "mep-desc.h"
36#include "mep-opc.h"
37#include "opintl.h"
38
39/* Default text to print if an instruction isn't recognized. */
40#define UNKNOWN_INSN_MSG _("*unknown*")
41
42static void print_normal
43 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
44static void print_address
45 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
46static void print_keyword
47 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
48static void print_insn_normal
49 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
50static int print_insn
51 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
52static int default_print_insn
53 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
54static int read_insn
55 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
56 unsigned long *);
57\f
58/* -- disassembler routines inserted here. */
59
60/* -- dis.c */
61
62#include "elf/mep.h"
63#include "elf-bfd.h"
64
65#define CGEN_VALIDATE_INSN_SUPPORTED
66
67static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
68static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
69
70static void
71print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
72 CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
73 unsigned int flags ATTRIBUTE_UNUSED)
74{
75 disassemble_info *info = (disassemble_info *) dis_info;
76
77 (*info->fprintf_func) (info->stream, "$tp");
78}
79
80static void
81print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
82 CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
83 unsigned int flags ATTRIBUTE_UNUSED)
84{
85 disassemble_info *info = (disassemble_info *) dis_info;
86
87 (*info->fprintf_func) (info->stream, "$sp");
88}
89
90/* begin-cop-ip-print-handlers */
3526b680
DD		 91static void
92print_ivc2_cr (CGEN_CPU_DESC,
93 void *,
94 CGEN_KEYWORD *,
95 long,
96 unsigned int) ATTRIBUTE_UNUSED;
97static void
98print_ivc2_cr (CGEN_CPU_DESC cd,
99 void *dis_info,
100 CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
101 long value,
102 unsigned int attrs)
103{
104 print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs);
105}
106static void
107print_ivc2_ccr (CGEN_CPU_DESC,
108 void *,
109 CGEN_KEYWORD *,
110 long,
111 unsigned int) ATTRIBUTE_UNUSED;
112static void
113print_ivc2_ccr (CGEN_CPU_DESC cd,
114 void *dis_info,
115 CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
116 long value,
117 unsigned int attrs)
118{
119 print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs);
120}
bd2f2e55
DB		 121/* end-cop-ip-print-handlers */
122
123/************************************************************\
124*********************** Experimental *************************
125\************************************************************/
126
127#undef CGEN_PRINT_INSN
128#define CGEN_PRINT_INSN mep_print_insn
129
130static int
131mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
132 bfd_byte *buf, int corelength, int copro1length,
133 int copro2length ATTRIBUTE_UNUSED)
134{
135 int i;
136 int status = 0;
137 /* char insnbuf[CGEN_MAX_INSN_SIZE]; */
138 bfd_byte insnbuf[64];
139
140 /* If corelength > 0 then there is a core insn present. It
141 will be at the beginning of the buffer. After printing
142 the core insn, we need to print the + on the next line. */
143 if (corelength > 0)
144 {
145 int my_status = 0;
146
147 for (i = 0; i < corelength; i++ )
148 insnbuf[i] = buf[i];
149 cd->isas = & MEP_CORE_ISA;
150
151 my_status = print_insn (cd, pc, info, insnbuf, corelength);
152 if (my_status != corelength)
153 {
154 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
155 my_status = corelength;
156 }
157 status += my_status;
158
159 /* Print the + to indicate that the following copro insn is */
160 /* part of a vliw group. */
161 if (copro1length > 0)
162 (*info->fprintf_func) (info->stream, " + ");
163 }
164
165 /* Now all that is left to be processed is the coprocessor insns
166 In vliw mode, there will always be one. Its positioning will
167 be from byte corelength to byte corelength+copro1length -1.
168 No need to check for existence. Also, the first vliw insn,
169 will, as spec'd, always be at least as long as the core insn
170 so we don't need to flush the buffer. */
171 if (copro1length > 0)
172 {
173 int my_status = 0;
174
175 for (i = corelength; i < corelength + copro1length; i++ )
176 insnbuf[i - corelength] = buf[i];
177
178 switch (copro1length)
179 {
180 case 0:
181 break;
182 case 2:
183 cd->isas = & MEP_COP16_ISA;
184 break;
185 case 4:
186 cd->isas = & MEP_COP32_ISA;
187 break;
188 case 6:
189 cd->isas = & MEP_COP48_ISA;
190 break;
191 case 8:
192 cd->isas = & MEP_COP64_ISA;
193 break;
194 default:
195 /* Shouldn't be anything but 16,32,48,64. */
196 break;
197 }
198
199 my_status = print_insn (cd, pc, info, insnbuf, copro1length);
200
201 if (my_status != copro1length)
202 {
203 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
204 my_status = copro1length;
205 }
206 status += my_status;
207 }
208
209#if 0
210 /* Now we need to process the second copro insn if it exists. We
211 have no guarantee that the second copro insn will be longer
212 than the first, so we have to flush the buffer if we are have
213 a second copro insn to process. If present, this insn will
214 be in the position from byte corelength+copro1length to byte
215 corelength+copro1length+copro2length-1 (which better equal 8
216 or else we're in big trouble. */
217 if (copro2length > 0)
218 {
219 int my_status = 0;
220
221 for (i = 0; i < 64 ; i++)
222 insnbuf[i] = 0;
223
224 for (i = corelength + copro1length; i < 64; i++)
225 insnbuf[i - (corelength + copro1length)] = buf[i];
226
227 switch (copro2length)
228 {
229 case 2:
230 cd->isas = 1 << ISA_EXT_COP1_16;
231 break;
232 case 4:
233 cd->isas = 1 << ISA_EXT_COP1_32;
234 break;
235 case 6:
236 cd->isas = 1 << ISA_EXT_COP1_48;
237 break;
238 case 8:
239 cd->isas = 1 << ISA_EXT_COP1_64;
240 break;
241 default:
242 /* Shouldn't be anything but 16,32,48,64. */
243 break;
244 }
245
246 my_status = print_insn (cd, pc, info, insnbuf, copro2length);
247
248 if (my_status != copro2length)
249 {
250 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
251 my_status = copro2length;
252 }
253
254 status += my_status;
255 }
256#endif
257
258 /* Status should now be the number of bytes that were printed
259 which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */
260
261 if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8)))
262 return -1;
263 else
264 return status;
265}
266
267/* The two functions mep_examine_vliw[32,64]_insns are used find out
268 which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
269 with 32 bit copro, etc.) is present. Later on, when internally
270 parallel coprocessors are handled, only these functions should
271 need to be changed.
272
273 At this time only the following combinations are supported:
274
275 VLIW32 Mode:
276 16 bit core insn (core) and 16 bit coprocessor insn (cop1)
277 32 bit core insn (core)
278 32 bit coprocessor insn (cop1)
279 Note: As of this time, I do not believe we have enough information
280 to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
281 no 16 bit coprocessor insns have been specified.
282
283 VLIW64 Mode:
284 16 bit core insn (core) and 48 bit coprocessor insn (cop1)
285 32 bit core insn (core) and 32 bit coprocessor insn (cop1)
286 64 bit coprocessor insn (cop1)
287
288 The framework for an internally parallel coprocessor is also
289 present (2nd coprocessor insn is cop2), but at this time it
290 is not used. This only appears to be valid in VLIW64 mode. */
291
292static int
293mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
294{
295 int status;
296 int buflength;
297 int corebuflength;
298 int cop1buflength;
299 int cop2buflength;
300 bfd_byte buf[CGEN_MAX_INSN_SIZE];
301 char indicator16[1];
302 char indicatorcop32[2];
303
304 /* At this time we're not supporting internally parallel coprocessors,
305 so cop2buflength will always be 0. */
306 cop2buflength = 0;
307
308 /* Read in 32 bits. */
309 buflength = 4; /* VLIW insn spans 4 bytes. */
310 status = (*info->read_memory_func) (pc, buf, buflength, info);
311
312 if (status != 0)
313 {
314 (*info->memory_error_func) (status, pc, info);
315 return -1;
316 }
317
318 /* Put the big endian representation of the bytes to be examined
319 in the temporary buffers for examination. */
320
321 if (info->endian == BFD_ENDIAN_BIG)
322 {
323 indicator16[0] = buf[0];
324 indicatorcop32[0] = buf[0];
325 indicatorcop32[1] = buf[1];
326 }
327 else
328 {
329 indicator16[0] = buf[1];
330 indicatorcop32[0] = buf[1];
331 indicatorcop32[1] = buf[0];
332 }
333
334 /* If the two high order bits are 00, 01 or 10, we have a 16 bit
335 core insn and a 48 bit copro insn. */
336
337 if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
338 {
339 if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
340 {
341 /* We have a 32 bit copro insn. */
342 corebuflength = 0;
343 /* All 4 4ytes are one copro insn. */
344 cop1buflength = 4;
345 }
346 else
347 {
348 /* We have a 32 bit core. */
349 corebuflength = 4;
350 cop1buflength = 0;
351 }
352 }
353 else
354 {
355 /* We have a 16 bit core insn and a 16 bit copro insn. */
356 corebuflength = 2;
357 cop1buflength = 2;
358 }
359
360 /* Now we have the distrubution set. Print them out. */
361 status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
362 cop1buflength, cop2buflength);
363
364 return status;
365}
366
367static int
368mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
369{
370 int status;
371 int buflength;
372 int corebuflength;
373 int cop1buflength;
374 int cop2buflength;
375 bfd_byte buf[CGEN_MAX_INSN_SIZE];
376 char indicator16[1];
377 char indicator64[4];
378
379 /* At this time we're not supporting internally parallel
380 coprocessors, so cop2buflength will always be 0. */
381 cop2buflength = 0;
382
383 /* Read in 64 bits. */
384 buflength = 8; /* VLIW insn spans 8 bytes. */
385 status = (*info->read_memory_func) (pc, buf, buflength, info);
386
387 if (status != 0)
388 {
389 (*info->memory_error_func) (status, pc, info);
390 return -1;
391 }
392
393 /* We have all 64 bits in the buffer now. We have to figure out
394 what combination of instruction sizes are present. The two
395 high order bits will indicate whether or not we have a 16 bit
396 core insn or not. If not, then we have to look at the 7,8th
397 bytes to tell whether we have 64 bit copro insn or a 32 bit
398 core insn with a 32 bit copro insn. Endianness will make a
399 difference here. */
400
401 /* Put the big endian representation of the bytes to be examined
402 in the temporary buffers for examination. */
403
404 /* indicator16[0] = buf[0]; */
405 if (info->endian == BFD_ENDIAN_BIG)
406 {
407 indicator16[0] = buf[0];
408 indicator64[0] = buf[0];
409 indicator64[1] = buf[1];
410 indicator64[2] = buf[2];
411 indicator64[3] = buf[3];
412 }
413 else
414 {
415 indicator16[0] = buf[1];
416 indicator64[0] = buf[1];
417 indicator64[1] = buf[0];
418 indicator64[2] = buf[3];
419 indicator64[3] = buf[2];
420 }
421
422 /* If the two high order bits are 00, 01 or 10, we have a 16 bit
423 core insn and a 48 bit copro insn. */
424
425 if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
426 {
427 if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
428 && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
429 {
430 /* We have a 64 bit copro insn. */
431 corebuflength = 0;
432 /* All 8 bytes are one copro insn. */
433 cop1buflength = 8;
434 }
435 else
436 {
437 /* We have a 32 bit core insn and a 32 bit copro insn. */
438 corebuflength = 4;
439 cop1buflength = 4;
440 }
441 }
442 else
443 {
444 /* We have a 16 bit core insn and a 48 bit copro insn. */
445 corebuflength = 2;
446 cop1buflength = 6;
447 }
448
449 /* Now we have the distrubution set. Print them out. */
450 status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
451 cop1buflength, cop2buflength);
452
453 return status;
454}
455
3526b680
DD		 456#ifdef MEP_IVC2_SUPPORTED
457
458static int
459print_slot_insn (CGEN_CPU_DESC cd,
460 bfd_vma pc,
461 disassemble_info *info,
462 SLOTS_ATTR slot,
463 bfd_byte *buf)
464{
465 const CGEN_INSN_LIST *insn_list;
466 CGEN_INSN_INT insn_value;
467 CGEN_EXTRACT_INFO ex_info;
468
469 insn_value = cgen_get_insn_value (cd, buf, 32);
470
471 /* Fill in ex_info fields like read_insn would. Don't actually call
472 read_insn, since the incoming buffer is already read (and possibly
473 modified a la m32r). */
474 ex_info.valid = (1 << 8) - 1;
475 ex_info.dis_info = info;
476 ex_info.insn_bytes = buf;
477
478 /* The instructions are stored in hash lists.
479 Pick the first one and keep trying until we find the right one. */
480
481 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
482 while (insn_list != NULL)
483 {
484 const CGEN_INSN *insn = insn_list->insn;
485 CGEN_FIELDS fields;
486 int length;
487
488 if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
489 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
490 || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
491 {
492 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
493 continue;
494 }
495
496 if ((insn_value & CGEN_INSN_BASE_MASK (insn))
497 == CGEN_INSN_BASE_VALUE (insn))
498 {
499 /* Printing is handled in two passes. The first pass parses the
500 machine insn and extracts the fields. The second pass prints
501 them. */
502
503 length = CGEN_EXTRACT_FN (cd, insn)
504 (cd, insn, &ex_info, insn_value, &fields, pc);
505
506 /* Length < 0 -> error. */
507 if (length < 0)
508 return length;
509 if (length > 0)
510 {
511 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
512 /* Length is in bits, result is in bytes. */
513 return length / 8;
514 }
515 }
516
517 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
518 }
519
520 if (slot == SLOTS_P0S)
521 (*info->fprintf_func) (info->stream, "*unknown-p0s*");
522 else if (slot == SLOTS_P0)
523 (*info->fprintf_func) (info->stream, "*unknown-p0*");
524 else if (slot == SLOTS_P1)
525 (*info->fprintf_func) (info->stream, "*unknown-p1*");
526 else if (slot == SLOTS_C3)
527 (*info->fprintf_func) (info->stream, "*unknown-c3*");
528 return 0;
529}
530
531static int
532mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED)
533{
534 int status;
535 int buflength;
3526b680
DD		 536 bfd_byte buf[8];
537 bfd_byte insn[8];
538 int e;
539
3526b680
DD		 540 /* Read in 64 bits. */
541 buflength = 8; /* VLIW insn spans 8 bytes. */
542 status = (*info->read_memory_func) (pc, buf, buflength, info);
543
544 if (status != 0)
545 {
546 (*info->memory_error_func) (status, pc, info);
547 return -1;
548 }
549
550 if (info->endian == BFD_ENDIAN_LITTLE)
551 e = 1;
552 else
553 e = 0;
554
1d74713b 555 if (((unsigned char)buf[0^e] & 0xf0) < 0xc0)
3526b680
DD		 556 {
557 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
558 /* V1 [-----core-----][--------p0s-------][------------p1------------] */
559
560 print_insn (cd, pc, info, buf, 2);
561
562 insn[0^e] = 0;
563 insn[1^e] = buf[2^e];
564 insn[2^e] = buf[3^e];
565 insn[3^e] = buf[4^e] & 0xf0;
566 (*info->fprintf_func) (info->stream, " + ");
567 print_slot_insn (cd, pc, info, SLOTS_P0S, insn);
568
569 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
570 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
571 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
572 insn[3^e] = buf[7^e] << 4;
573 (*info->fprintf_func) (info->stream, " + ");
574 print_slot_insn (cd, pc, info, SLOTS_P1, insn);
575 }
576 else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07)
577 {
578 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
579 /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */
580 /* 00000000111111112222222233333333 */
581
582 insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4;
583 insn[1^e] = buf[2^e];
584 insn[2^e] = buf[3^e];
585 insn[3^e] = buf[4^e] & 0xf0;
586 print_slot_insn (cd, pc, info, SLOTS_P0, insn);
587
588 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
589 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
590 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
591 insn[3^e] = buf[7^e] << 4;
592 (*info->fprintf_func) (info->stream, " + ");
593 print_slot_insn (cd, pc, info, SLOTS_P1, insn);
594 }
595 else
596 {
597 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
598 /* V2 [-------------core-------------]xxxx[------------p1------------] */
599 print_insn (cd, pc, info, buf, 4);
600
601 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
602 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
603 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
604 insn[3^e] = buf[7^e] << 4;
605 (*info->fprintf_func) (info->stream, " + ");
606 print_slot_insn (cd, pc, info, SLOTS_P1, insn);
607 }
608
609 return 8;
610}
611
612#endif /* MEP_IVC2_SUPPORTED */
613
614/* This is a hack. SID calls this to update the disassembler as the
615 CPU changes modes. */
616static int mep_ivc2_disassemble_p = 0;
617static int mep_ivc2_vliw_disassemble_p = 0;
618
619void
620mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx);
621void
622mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx)
623{
624 mep_ivc2_disassemble_p = ivc2_p;
625 mep_ivc2_vliw_disassemble_p = vliw_p;
626 mep_config_index = cfg_idx;
627}
628
bd2f2e55
DB		 629static int
630mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
631{
632 int status;
3526b680
DD		 633 int cop_type;
634 int ivc2 = 0;
635 static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL;
636
637 if (ivc2_core_isa == NULL)
638 {
639 /* IVC2 has some core-only coprocessor instructions. We
640 use COP32 to flag those, and COP64 for the VLIW ones,
641 since they have the same names. */
642 ivc2_core_isa = cgen_bitset_create (MAX_ISAS);
643 }
bd2f2e55
DB		 644
645 /* Extract and adapt to configuration number, if available. */
646 if (info->section && info->section->owner)
647 {
648 bfd *abfd = info->section->owner;
649 mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
650 /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
3526b680
DD		 651
652 cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
653 if (cop_type == EF_MEP_COP_IVC2)
654 ivc2 = 1;
bd2f2e55
DB		 655 }
656
657 /* Picking the right ISA bitmask for the current context is tricky. */
658 if (info->section)
659 {
660 if (info->section->flags & SEC_MEP_VLIW)
661 {
3526b680
DD		 662#ifdef MEP_IVC2_SUPPORTED
663 if (ivc2)
664 {
665 /* ivc2 has its own way of selecting its functions. */
666 cd->isas = & MEP_CORE_ISA;
667 status = mep_examine_ivc2_insns (cd, pc, info);
668 }
bd2f2e55 669 else
3526b680
DD		 670#endif
671 /* Are we in 32 or 64 bit vliw mode? */
672 if (MEP_VLIW64)
673 status = mep_examine_vliw64_insns (cd, pc, info);
674 else
675 status = mep_examine_vliw32_insns (cd, pc, info);
bd2f2e55
DB		 676 /* Both the above branches set their own isa bitmasks. */
677 }
678 else
679 {
3526b680
DD		 680 if (ivc2)
681 {
682 cgen_bitset_clear (ivc2_core_isa);
683 cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa);
684 cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa);
685 cd->isas = ivc2_core_isa;
686 }
687 else
688 cd->isas = & MEP_CORE_ISA;
bd2f2e55
DB		 689 status = default_print_insn (cd, pc, info);
690 }
691 }
692 else /* sid or gdb */
693 {
3526b680
DD		 694#ifdef MEP_IVC2_SUPPORTED
695 if (mep_ivc2_disassemble_p)
696 {
697 if (mep_ivc2_vliw_disassemble_p)
698 {
699 cd->isas = & MEP_CORE_ISA;
700 status = mep_examine_ivc2_insns (cd, pc, info);
701 return status;
702 }
703 else
704 {
705 if (ivc2)
706 cd->isas = ivc2_core_isa;
707 }
708 }
709#endif
710
bd2f2e55
DB		 711 status = default_print_insn (cd, pc, info);
712 }
713
714 return status;
715}
716
717
718/* -- opc.c */
719
720void mep_cgen_print_operand
721 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
722
723/* Main entry point for printing operands.
724 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
725 of dis-asm.h on cgen.h.
726
727 This function is basically just a big switch statement. Earlier versions
728 used tables to look up the function to use, but
729 - if the table contains both assembler and disassembler functions then
730 the disassembler contains much of the assembler and vice-versa,
731 - there's a lot of inlining possibilities as things grow,
732 - using a switch statement avoids the function call overhead.
733
734 This function could be moved into `print_insn_normal', but keeping it
735 separate makes clear the interface between `print_insn_normal' and each of
736 the handlers. */
737
738void
739mep_cgen_print_operand (CGEN_CPU_DESC cd,
740 int opindex,
741 void * xinfo,
742 CGEN_FIELDS *fields,
743 void const *attrs ATTRIBUTE_UNUSED,
744 bfd_vma pc,
745 int length)
746{
747 disassemble_info *info = (disassemble_info *) xinfo;
748
749 switch (opindex)
750 {
751 case MEP_OPERAND_ADDR24A4 :
752 print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
753 break;
40493983
DD		 754 case MEP_OPERAND_C5RMUIMM20 :
755 print_normal (cd, info, fields->f_c5_rmuimm20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
756 break;
757 case MEP_OPERAND_C5RNMUIMM24 :
758 print_normal (cd, info, fields->f_c5_rnmuimm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
759 break;
bd2f2e55
DB		 760 case MEP_OPERAND_CALLNUM :
761 print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
762 break;
763 case MEP_OPERAND_CCCC :
764 print_normal (cd, info, fields->f_rm, 0, pc, length);
765 break;
766 case MEP_OPERAND_CCRN :
767 print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
768 break;
40493983
DD		 769 case MEP_OPERAND_CDISP10 :
770 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
bd2f2e55 771 break;
40493983
DD		 772 case MEP_OPERAND_CDISP10A2 :
773 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
bd2f2e55 774 break;
40493983
DD		 775 case MEP_OPERAND_CDISP10A4 :
776 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
bd2f2e55 777 break;
40493983
DD		 778 case MEP_OPERAND_CDISP10A8 :
779 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
780 break;
781 case MEP_OPERAND_CDISP12 :
782 print_normal (cd, info, fields->f_12s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
bd2f2e55
DB		 783 break;
784 case MEP_OPERAND_CIMM4 :
785 print_normal (cd, info, fields->f_rn, 0, pc, length);
786 break;
787 case MEP_OPERAND_CIMM5 :
788 print_normal (cd, info, fields->f_5u24, 0, pc, length);
789 break;
790 case MEP_OPERAND_CODE16 :
791 print_normal (cd, info, fields->f_16u16, 0, pc, length);
792 break;
793 case MEP_OPERAND_CODE24 :
794 print_normal (cd, info, fields->f_24u4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
795 break;
796 case MEP_OPERAND_CP_FLAG :
797 print_keyword (cd, info, & mep_cgen_opval_h_ccr, 0, 0);
798 break;
799 case MEP_OPERAND_CRN :
800 print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crn, 0);
801 break;
802 case MEP_OPERAND_CRN64 :
803 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crn, 0);
804 break;
805 case MEP_OPERAND_CRNX :
806 print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
807 break;
808 case MEP_OPERAND_CRNX64 :
809 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
810 break;
3526b680
DD		 811 case MEP_OPERAND_CROC :
812 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u7, 0);
813 break;
814 case MEP_OPERAND_CROP :
815 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u23, 0);
816 break;
817 case MEP_OPERAND_CRPC :
818 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u26, 0);
819 break;
820 case MEP_OPERAND_CRPP :
821 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u18, 0);
822 break;
823 case MEP_OPERAND_CRQC :
824 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u21, 0);
825 break;
826 case MEP_OPERAND_CRQP :
827 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u13, 0);
828 break;
bd2f2e55
DB		 829 case MEP_OPERAND_CSRN :
830 print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
831 break;
832 case MEP_OPERAND_CSRN_IDX :
833 print_normal (cd, info, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
834 break;
835 case MEP_OPERAND_DBG :
836 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
837 break;
838 case MEP_OPERAND_DEPC :
839 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
840 break;
841 case MEP_OPERAND_EPC :
842 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
843 break;
844 case MEP_OPERAND_EXC :
845 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
846 break;
bd2f2e55
DB		 847 case MEP_OPERAND_HI :
848 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
849 break;
3526b680
DD		 850 case MEP_OPERAND_IMM16P0 :
851 print_normal (cd, info, fields->f_ivc2_imm16p0, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
852 break;
853 case MEP_OPERAND_IMM3P12 :
854 print_normal (cd, info, fields->f_ivc2_3u12, 0, pc, length);
855 break;
856 case MEP_OPERAND_IMM3P25 :
857 print_normal (cd, info, fields->f_ivc2_3u25, 0, pc, length);
858 break;
859 case MEP_OPERAND_IMM3P4 :
860 print_normal (cd, info, fields->f_ivc2_3u4, 0, pc, length);
861 break;
862 case MEP_OPERAND_IMM3P5 :
863 print_normal (cd, info, fields->f_ivc2_3u5, 0, pc, length);
864 break;
865 case MEP_OPERAND_IMM3P9 :
866 print_normal (cd, info, fields->f_ivc2_3u9, 0, pc, length);
867 break;
868 case MEP_OPERAND_IMM4P10 :
869 print_normal (cd, info, fields->f_ivc2_4u10, 0, pc, length);
870 break;
871 case MEP_OPERAND_IMM4P4 :
872 print_normal (cd, info, fields->f_ivc2_4u4, 0, pc, length);
873 break;
874 case MEP_OPERAND_IMM4P8 :
875 print_normal (cd, info, fields->f_ivc2_4u8, 0, pc, length);
876 break;
877 case MEP_OPERAND_IMM5P23 :
878 print_normal (cd, info, fields->f_ivc2_5u23, 0, pc, length);
879 break;
880 case MEP_OPERAND_IMM5P3 :
881 print_normal (cd, info, fields->f_ivc2_5u3, 0, pc, length);
882 break;
883 case MEP_OPERAND_IMM5P7 :
884 print_normal (cd, info, fields->f_ivc2_5u7, 0, pc, length);
885 break;
886 case MEP_OPERAND_IMM5P8 :
887 print_normal (cd, info, fields->f_ivc2_5u8, 0, pc, length);
888 break;
889 case MEP_OPERAND_IMM6P2 :
890 print_normal (cd, info, fields->f_ivc2_6u2, 0, pc, length);
891 break;
892 case MEP_OPERAND_IMM6P6 :
893 print_normal (cd, info, fields->f_ivc2_6u6, 0, pc, length);
894 break;
895 case MEP_OPERAND_IMM8P0 :
896 print_normal (cd, info, fields->f_ivc2_8u0, 0, pc, length);
897 break;
898 case MEP_OPERAND_IMM8P20 :
899 print_normal (cd, info, fields->f_ivc2_8u20, 0, pc, length);
900 break;
901 case MEP_OPERAND_IMM8P4 :
902 print_normal (cd, info, fields->f_ivc2_8u4, 0, pc, length);
903 break;
904 case MEP_OPERAND_IVC_X_0_2 :
905 print_normal (cd, info, fields->f_ivc2_2u0, 0, pc, length);
906 break;
907 case MEP_OPERAND_IVC_X_0_3 :
908 print_normal (cd, info, fields->f_ivc2_3u0, 0, pc, length);
909 break;
910 case MEP_OPERAND_IVC_X_0_4 :
911 print_normal (cd, info, fields->f_ivc2_4u0, 0, pc, length);
912 break;
913 case MEP_OPERAND_IVC_X_0_5 :
914 print_normal (cd, info, fields->f_ivc2_5u0, 0, pc, length);
915 break;
916 case MEP_OPERAND_IVC_X_6_1 :
917 print_normal (cd, info, fields->f_ivc2_1u6, 0, pc, length);
918 break;
919 case MEP_OPERAND_IVC_X_6_2 :
920 print_normal (cd, info, fields->f_ivc2_2u6, 0, pc, length);
921 break;
922 case MEP_OPERAND_IVC_X_6_3 :
923 print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
924 break;
dab97f24
DD		 925 case MEP_OPERAND_IVC2_ACC0_0 :
926 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
927 break;
928 case MEP_OPERAND_IVC2_ACC0_1 :
929 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
930 break;
931 case MEP_OPERAND_IVC2_ACC0_2 :
932 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
933 break;
934 case MEP_OPERAND_IVC2_ACC0_3 :
935 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
936 break;
937 case MEP_OPERAND_IVC2_ACC0_4 :
938 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
939 break;
940 case MEP_OPERAND_IVC2_ACC0_5 :
941 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
942 break;
943 case MEP_OPERAND_IVC2_ACC0_6 :
944 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
945 break;
946 case MEP_OPERAND_IVC2_ACC0_7 :
947 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
948 break;
949 case MEP_OPERAND_IVC2_ACC1_0 :
950 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
951 break;
952 case MEP_OPERAND_IVC2_ACC1_1 :
953 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
954 break;
955 case MEP_OPERAND_IVC2_ACC1_2 :
956 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
957 break;
958 case MEP_OPERAND_IVC2_ACC1_3 :
959 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
960 break;
961 case MEP_OPERAND_IVC2_ACC1_4 :
962 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
963 break;
964 case MEP_OPERAND_IVC2_ACC1_5 :
965 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
966 break;
967 case MEP_OPERAND_IVC2_ACC1_6 :
968 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
969 break;
970 case MEP_OPERAND_IVC2_ACC1_7 :
971 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
972 break;
973 case MEP_OPERAND_IVC2_CC :
974 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
975 break;
976 case MEP_OPERAND_IVC2_COFA0 :
977 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
978 break;
979 case MEP_OPERAND_IVC2_COFA1 :
980 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
981 break;
982 case MEP_OPERAND_IVC2_COFR0 :
983 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
984 break;
985 case MEP_OPERAND_IVC2_COFR1 :
986 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
987 break;
988 case MEP_OPERAND_IVC2_CSAR0 :
989 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
990 break;
991 case MEP_OPERAND_IVC2_CSAR1 :
992 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
993 break;
1d74713b 994 case MEP_OPERAND_IVC2C3CCRN :
2f3565a3 995 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
1d74713b 996 break;
3526b680 997 case MEP_OPERAND_IVC2CCRN :
1d74713b 998 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
3526b680
DD		 999 break;
1000 case MEP_OPERAND_IVC2CRN :
1001 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
1002 break;
1003 case MEP_OPERAND_IVC2RM :
1004 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_ivc2_crm, 0);
1005 break;
bd2f2e55
DB		 1006 case MEP_OPERAND_LO :
1007 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1008 break;
1009 case MEP_OPERAND_LP :
1010 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1011 break;
1012 case MEP_OPERAND_MB0 :
1013 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1014 break;
1015 case MEP_OPERAND_MB1 :
1016 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1017 break;
1018 case MEP_OPERAND_ME0 :
1019 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1020 break;
1021 case MEP_OPERAND_ME1 :
1022 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1023 break;
1024 case MEP_OPERAND_NPC :
1025 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1026 break;
1027 case MEP_OPERAND_OPT :
1028 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1029 break;
1030 case MEP_OPERAND_PCABS24A2 :
1031 print_address (cd, info, fields->f_24u5a2n, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1032 break;
1033 case MEP_OPERAND_PCREL12A2 :
1034 print_address (cd, info, fields->f_12s4a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1035 break;
1036 case MEP_OPERAND_PCREL17A2 :
1037 print_address (cd, info, fields->f_17s16a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1038 break;
1039 case MEP_OPERAND_PCREL24A2 :
1040 print_address (cd, info, fields->f_24s5a2n, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1041 break;
1042 case MEP_OPERAND_PCREL8A2 :
1043 print_address (cd, info, fields->f_8s8a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1044 break;
1045 case MEP_OPERAND_PSW :
1046 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1047 break;
1048 case MEP_OPERAND_R0 :
1049 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1050 break;
1051 case MEP_OPERAND_R1 :
1052 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1053 break;
1054 case MEP_OPERAND_RL :
1055 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0);
1056 break;
40493983
DD		 1057 case MEP_OPERAND_RL5 :
1058 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0);
1059 break;
bd2f2e55
DB		 1060 case MEP_OPERAND_RM :
1061 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
1062 break;
1063 case MEP_OPERAND_RMA :
1064 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
1065 break;
1066 case MEP_OPERAND_RN :
1067 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1068 break;
1069 case MEP_OPERAND_RN3 :
1070 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1071 break;
1072 case MEP_OPERAND_RN3C :
1073 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1074 break;
1075 case MEP_OPERAND_RN3L :
1076 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1077 break;
1078 case MEP_OPERAND_RN3S :
1079 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1080 break;
1081 case MEP_OPERAND_RN3UC :
1082 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1083 break;
1084 case MEP_OPERAND_RN3UL :
1085 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1086 break;
1087 case MEP_OPERAND_RN3US :
1088 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1089 break;
1090 case MEP_OPERAND_RNC :
1091 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1092 break;
1093 case MEP_OPERAND_RNL :
1094 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1095 break;
1096 case MEP_OPERAND_RNS :
1097 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1098 break;
1099 case MEP_OPERAND_RNUC :
1100 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1101 break;
1102 case MEP_OPERAND_RNUL :
1103 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1104 break;
1105 case MEP_OPERAND_RNUS :
1106 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1107 break;
1108 case MEP_OPERAND_SAR :
1109 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1110 break;
1111 case MEP_OPERAND_SDISP16 :
1112 print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1113 break;
1114 case MEP_OPERAND_SIMM16 :
1115 print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1116 break;
3526b680
DD		 1117 case MEP_OPERAND_SIMM16P0 :
1118 print_normal (cd, info, fields->f_ivc2_simm16p0, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1119 break;
bd2f2e55
DB		 1120 case MEP_OPERAND_SIMM6 :
1121 print_normal (cd, info, fields->f_6s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1122 break;
1123 case MEP_OPERAND_SIMM8 :
1124 print_normal (cd, info, fields->f_8s8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW), pc, length);
1125 break;
3526b680
DD		 1126 case MEP_OPERAND_SIMM8P0 :
1127 print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1128 break;
1d74713b
DD		 1129 case MEP_OPERAND_SIMM8P20 :
1130 print_normal (cd, info, fields->f_ivc2_8s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1131 break;
3526b680
DD		 1132 case MEP_OPERAND_SIMM8P4 :
1133 print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1134 break;
bd2f2e55
DB		 1135 case MEP_OPERAND_SP :
1136 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1137 break;
1138 case MEP_OPERAND_SPR :
1139 print_spreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1140 break;
1141 case MEP_OPERAND_TP :
1142 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1143 break;
1144 case MEP_OPERAND_TPR :
1145 print_tpreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1146 break;
1147 case MEP_OPERAND_UDISP2 :
1148 print_normal (cd, info, fields->f_2u6, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1149 break;
1150 case MEP_OPERAND_UDISP7 :
1151 print_normal (cd, info, fields->f_7u9, 0, pc, length);
1152 break;
1153 case MEP_OPERAND_UDISP7A2 :
1154 print_normal (cd, info, fields->f_7u9a2, 0, pc, length);
1155 break;
1156 case MEP_OPERAND_UDISP7A4 :
1157 print_normal (cd, info, fields->f_7u9a4, 0, pc, length);
1158 break;
1159 case MEP_OPERAND_UIMM16 :
1160 print_normal (cd, info, fields->f_16u16, 0, pc, length);
1161 break;
1162 case MEP_OPERAND_UIMM2 :
1163 print_normal (cd, info, fields->f_2u10, 0, pc, length);
1164 break;
1165 case MEP_OPERAND_UIMM24 :
1166 print_normal (cd, info, fields->f_24u8n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1167 break;
1168 case MEP_OPERAND_UIMM3 :
1169 print_normal (cd, info, fields->f_3u5, 0, pc, length);
1170 break;
1171 case MEP_OPERAND_UIMM4 :
1172 print_normal (cd, info, fields->f_4u8, 0, pc, length);
1173 break;
1174 case MEP_OPERAND_UIMM5 :
1175 print_normal (cd, info, fields->f_5u8, 0, pc, length);
1176 break;
1177 case MEP_OPERAND_UIMM7A4 :
1178 print_normal (cd, info, fields->f_7u9a4, 0, pc, length);
1179 break;
1180 case MEP_OPERAND_ZERO :
1181 print_normal (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1182 break;
1183
1184 default :
1185 /* xgettext:c-format */
1186 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
1187 opindex);
1188 abort ();
1189 }
1190}
1191
1192cgen_print_fn * const mep_cgen_print_handlers[] =
1193{
1194 print_insn_normal,
1195};
1196
1197
1198void
1199mep_cgen_init_dis (CGEN_CPU_DESC cd)
1200{
1201 mep_cgen_init_opcode_table (cd);
1202 mep_cgen_init_ibld_table (cd);
1203 cd->print_handlers = & mep_cgen_print_handlers[0];
1204 cd->print_operand = mep_cgen_print_operand;
1205}
1206
1207\f
1208/* Default print handler. */
1209
1210static void
1211print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1212 void *dis_info,
1213 long value,
1214 unsigned int attrs,
1215 bfd_vma pc ATTRIBUTE_UNUSED,
1216 int length ATTRIBUTE_UNUSED)
1217{
1218 disassemble_info *info = (disassemble_info *) dis_info;
1219
bd2f2e55
DB		 1220 /* Print the operand as directed by the attributes. */
1221 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
1222 ; /* nothing to do */
1223 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
1224 (*info->fprintf_func) (info->stream, "%ld", value);
1225 else
1226 (*info->fprintf_func) (info->stream, "0x%lx", value);
1227}
1228
1229/* Default address handler. */
1230
1231static void
1232print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1233 void *dis_info,
1234 bfd_vma value,
1235 unsigned int attrs,
1236 bfd_vma pc ATTRIBUTE_UNUSED,
1237 int length ATTRIBUTE_UNUSED)
1238{
1239 disassemble_info *info = (disassemble_info *) dis_info;
1240
bd2f2e55
DB		 1241 /* Print the operand as directed by the attributes. */
1242 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
1243 ; /* Nothing to do. */
1244 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
1245 (*info->print_address_func) (value, info);
1246 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
1247 (*info->print_address_func) (value, info);
1248 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
1249 (*info->fprintf_func) (info->stream, "%ld", (long) value);
1250 else
1251 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
1252}
1253
1254/* Keyword print handler. */
1255
1256static void
1257print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1258 void *dis_info,
1259 CGEN_KEYWORD *keyword_table,
1260 long value,
1261 unsigned int attrs ATTRIBUTE_UNUSED)
1262{
1263 disassemble_info *info = (disassemble_info *) dis_info;
1264 const CGEN_KEYWORD_ENTRY *ke;
1265
1266 ke = cgen_keyword_lookup_value (keyword_table, value);
1267 if (ke != NULL)
1268 (*info->fprintf_func) (info->stream, "%s", ke->name);
1269 else
1270 (*info->fprintf_func) (info->stream, "???");
1271}
1272\f
1273/* Default insn printer.
1274
1275 DIS_INFO is defined as `void *' so the disassembler needn't know anything
1276 about disassemble_info. */
1277
1278static void
1279print_insn_normal (CGEN_CPU_DESC cd,
1280 void *dis_info,
1281 const CGEN_INSN *insn,
1282 CGEN_FIELDS *fields,
1283 bfd_vma pc,
1284 int length)
1285{
1286 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
1287 disassemble_info *info = (disassemble_info *) dis_info;
1288 const CGEN_SYNTAX_CHAR_TYPE *syn;
1289
1290 CGEN_INIT_PRINT (cd);
1291
1292 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
1293 {
1294 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
1295 {
1296 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
1297 continue;
1298 }
1299 if (CGEN_SYNTAX_CHAR_P (*syn))
1300 {
1301 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
1302 continue;
1303 }
1304
1305 /* We have an operand. */
1306 mep_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
1307 fields, CGEN_INSN_ATTRS (insn), pc, length);
1308 }
1309}
1310\f
1311/* Subroutine of print_insn. Reads an insn into the given buffers and updates
1312 the extract info.
1313 Returns 0 if all is well, non-zero otherwise. */
1314
1315static int
1316read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1317 bfd_vma pc,
1318 disassemble_info *info,
1319 bfd_byte *buf,
1320 int buflen,
1321 CGEN_EXTRACT_INFO *ex_info,
1322 unsigned long *insn_value)
1323{
1324 int status = (*info->read_memory_func) (pc, buf, buflen, info);
1325
1326 if (status != 0)
1327 {
1328 (*info->memory_error_func) (status, pc, info);
1329 return -1;
1330 }
1331
1332 ex_info->dis_info = info;
1333 ex_info->valid = (1 << buflen) - 1;
1334 ex_info->insn_bytes = buf;
1335
1336 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
1337 return 0;
1338}
1339
1340/* Utility to print an insn.
1341 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
1342 The result is the size of the insn in bytes or zero for an unknown insn
1343 or -1 if an error occurs fetching data (memory_error_func will have
1344 been called). */
1345
1346static int
1347print_insn (CGEN_CPU_DESC cd,
1348 bfd_vma pc,
1349 disassemble_info *info,
1350 bfd_byte *buf,
1351 unsigned int buflen)
1352{
1353 CGEN_INSN_INT insn_value;
1354 const CGEN_INSN_LIST *insn_list;
1355 CGEN_EXTRACT_INFO ex_info;
1356 int basesize;
1357
1358 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
1359 basesize = cd->base_insn_bitsize < buflen * 8 ?
1360 cd->base_insn_bitsize : buflen * 8;
1361 insn_value = cgen_get_insn_value (cd, buf, basesize);
1362
1363
1364 /* Fill in ex_info fields like read_insn would. Don't actually call
1365 read_insn, since the incoming buffer is already read (and possibly
1366 modified a la m32r). */
1367 ex_info.valid = (1 << buflen) - 1;
1368 ex_info.dis_info = info;
1369 ex_info.insn_bytes = buf;
1370
1371 /* The instructions are stored in hash lists.
1372 Pick the first one and keep trying until we find the right one. */
1373
1374 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
1375 while (insn_list != NULL)
1376 {
1377 const CGEN_INSN *insn = insn_list->insn;
1378 CGEN_FIELDS fields;
1379 int length;
1380 unsigned long insn_value_cropped;
1381
1382#ifdef CGEN_VALIDATE_INSN_SUPPORTED
1383 /* Not needed as insn shouldn't be in hash lists if not supported. */
1384 /* Supported by this cpu? */
1385 if (! mep_cgen_insn_supported (cd, insn))
1386 {
1387 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1388 continue;
1389 }
1390#endif
1391
1392 /* Basic bit mask must be correct. */
1393 /* ??? May wish to allow target to defer this check until the extract
1394 handler. */
1395
1396 /* Base size may exceed this instruction's size. Extract the
1397 relevant part from the buffer. */
1398 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
1399 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1400 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
1401 info->endian == BFD_ENDIAN_BIG);
1402 else
1403 insn_value_cropped = insn_value;
1404
1405 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
1406 == CGEN_INSN_BASE_VALUE (insn))
1407 {
1408 /* Printing is handled in two passes. The first pass parses the
1409 machine insn and extracts the fields. The second pass prints
1410 them. */
1411
1412 /* Make sure the entire insn is loaded into insn_value, if it
1413 can fit. */
1414 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
1415 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1416 {
1417 unsigned long full_insn_value;
1418 int rc = read_insn (cd, pc, info, buf,
1419 CGEN_INSN_BITSIZE (insn) / 8,
1420 & ex_info, & full_insn_value);
1421 if (rc != 0)
1422 return rc;
1423 length = CGEN_EXTRACT_FN (cd, insn)
1424 (cd, insn, &ex_info, full_insn_value, &fields, pc);
1425 }
1426 else
1427 length = CGEN_EXTRACT_FN (cd, insn)
1428 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
1429
1430 /* Length < 0 -> error. */
1431 if (length < 0)
1432 return length;
1433 if (length > 0)
1434 {
1435 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
1436 /* Length is in bits, result is in bytes. */
1437 return length / 8;
1438 }
1439 }
1440
1441 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1442 }
1443
1444 return 0;
1445}
1446
1447/* Default value for CGEN_PRINT_INSN.
1448 The result is the size of the insn in bytes or zero for an unknown insn
1449 or -1 if an error occured fetching bytes. */
1450
1451#ifndef CGEN_PRINT_INSN
1452#define CGEN_PRINT_INSN default_print_insn
1453#endif
1454
1455static int
1456default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
1457{
1458 bfd_byte buf[CGEN_MAX_INSN_SIZE];
1459 int buflen;
1460 int status;
1461
1462 /* Attempt to read the base part of the insn. */
1463 buflen = cd->base_insn_bitsize / 8;
1464 status = (*info->read_memory_func) (pc, buf, buflen, info);
1465
1466 /* Try again with the minimum part, if min < base. */
1467 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
1468 {
1469 buflen = cd->min_insn_bitsize / 8;
1470 status = (*info->read_memory_func) (pc, buf, buflen, info);
1471 }
1472
1473 if (status != 0)
1474 {
1475 (*info->memory_error_func) (status, pc, info);
1476 return -1;
1477 }
1478
1479 return print_insn (cd, pc, info, buf, buflen);
1480}
1481
1482/* Main entry point.
1483 Print one instruction from PC on INFO->STREAM.
1484 Return the size of the instruction (in bytes). */
1485
1486typedef struct cpu_desc_list
1487{
1488 struct cpu_desc_list *next;
1489 CGEN_BITSET *isa;
1490 int mach;
1491 int endian;
1492 CGEN_CPU_DESC cd;
1493} cpu_desc_list;
1494
1495int
1496print_insn_mep (bfd_vma pc, disassemble_info *info)
1497{
1498 static cpu_desc_list *cd_list = 0;
1499 cpu_desc_list *cl = 0;
1500 static CGEN_CPU_DESC cd = 0;
1501 static CGEN_BITSET *prev_isa;
1502 static int prev_mach;
1503 static int prev_endian;
1504 int length;
1505 CGEN_BITSET *isa;
1506 int mach;
1507 int endian = (info->endian == BFD_ENDIAN_BIG
1508 ? CGEN_ENDIAN_BIG
1509 : CGEN_ENDIAN_LITTLE);
1510 enum bfd_architecture arch;
1511
1512 /* ??? gdb will set mach but leave the architecture as "unknown" */
1513#ifndef CGEN_BFD_ARCH
1514#define CGEN_BFD_ARCH bfd_arch_mep
1515#endif
1516 arch = info->arch;
1517 if (arch == bfd_arch_unknown)
1518 arch = CGEN_BFD_ARCH;
1519
1520 /* There's no standard way to compute the machine or isa number
1521 so we leave it to the target. */
1522#ifdef CGEN_COMPUTE_MACH
1523 mach = CGEN_COMPUTE_MACH (info);
1524#else
1525 mach = info->mach;
1526#endif
1527
1528#ifdef CGEN_COMPUTE_ISA
1529 {
1530 static CGEN_BITSET *permanent_isa;
1531
1532 if (!permanent_isa)
1533 permanent_isa = cgen_bitset_create (MAX_ISAS);
1534 isa = permanent_isa;
1535 cgen_bitset_clear (isa);
1536 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
1537 }
1538#else
1539 isa = info->insn_sets;
1540#endif
1541
1542 /* If we've switched cpu's, try to find a handle we've used before */
1543 if (cd
1544 && (cgen_bitset_compare (isa, prev_isa) != 0
1545 || mach != prev_mach
1546 || endian != prev_endian))
1547 {
1548 cd = 0;
1549 for (cl = cd_list; cl; cl = cl->next)
1550 {
1551 if (cgen_bitset_compare (cl->isa, isa) == 0 &&
1552 cl->mach == mach &&
1553 cl->endian == endian)
1554 {
1555 cd = cl->cd;
1556 prev_isa = cd->isas;
1557 break;
1558 }
1559 }
1560 }
1561
1562 /* If we haven't initialized yet, initialize the opcode table. */
1563 if (! cd)
1564 {
1565 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
1566 const char *mach_name;
1567
1568 if (!arch_type)
1569 abort ();
1570 mach_name = arch_type->printable_name;
1571
1572 prev_isa = cgen_bitset_copy (isa);
1573 prev_mach = mach;
1574 prev_endian = endian;
1575 cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
1576 CGEN_CPU_OPEN_BFDMACH, mach_name,
1577 CGEN_CPU_OPEN_ENDIAN, prev_endian,
1578 CGEN_CPU_OPEN_END);
1579 if (!cd)
1580 abort ();
1581
1582 /* Save this away for future reference. */
1583 cl = xmalloc (sizeof (struct cpu_desc_list));
1584 cl->cd = cd;
1585 cl->isa = prev_isa;
1586 cl->mach = mach;
1587 cl->endian = endian;
1588 cl->next = cd_list;
1589 cd_list = cl;
1590
1591 mep_cgen_init_dis (cd);
1592 }
1593
1594 /* We try to have as much common code as possible.
1595 But at this point some targets need to take over. */
1596 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
1597 but if not possible try to move this hook elsewhere rather than
1598 have two hooks. */
1599 length = CGEN_PRINT_INSN (cd, pc, info);
1600 if (length > 0)
1601 return length;
1602 if (length < 0)
1603 return -1;
1604
1605 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
1606 return cd->default_insn_bitsize / 8;
1607}
GDB Binutils - Deliverables
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