Commit | Line | Data |
---|---|---|
bd2f2e55 DB |
1 | /* Instruction opcode header for mep. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
9b201bb5 | 5 | Copyright 1996-2007 Free Software Foundation, Inc. |
bd2f2e55 DB |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9b201bb5 NC |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
bd2f2e55 | 13 | |
9b201bb5 NC |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
bd2f2e55 | 18 | |
9b201bb5 NC |
19 | You should have received a copy of the GNU General Public License along |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
bd2f2e55 DB |
22 | |
23 | */ | |
24 | ||
25 | #ifndef MEP_OPC_H | |
26 | #define MEP_OPC_H | |
27 | ||
28 | /* -- opc.h */ | |
29 | ||
30 | #undef CGEN_DIS_HASH_SIZE | |
31 | #define CGEN_DIS_HASH_SIZE 1 | |
32 | ||
33 | #undef CGEN_DIS_HASH | |
34 | #define CGEN_DIS_HASH(buffer, insn) 0 | |
35 | ||
36 | #define CGEN_VERBOSE_ASSEMBLER_ERRORS | |
37 | ||
38 | typedef struct | |
39 | { | |
40 | char * name; | |
41 | int config_enum; | |
42 | unsigned cpu_flag; | |
43 | int big_endian; | |
44 | int vliw_bits; | |
45 | CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; | |
46 | CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; | |
47 | CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; | |
48 | CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; | |
49 | CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; | |
50 | CGEN_ATTR_VALUE_BITSET_TYPE core_isa; | |
51 | unsigned int option_mask; | |
52 | } mep_config_map_struct; | |
53 | ||
54 | extern mep_config_map_struct mep_config_map[]; | |
55 | extern int mep_config_index; | |
56 | ||
57 | extern void init_mep_all_core_isas_mask (void); | |
58 | extern void init_mep_all_cop_isas_mask (void); | |
59 | extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); | |
60 | ||
61 | #define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) | |
62 | #define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) | |
63 | #define MEP_OMASK (mep_config_map[mep_config_index].option_mask) | |
64 | #define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) | |
65 | #define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) | |
66 | #define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) | |
67 | #define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) | |
68 | #define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) | |
69 | #define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) | |
70 | #define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) | |
71 | #define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) | |
72 | #define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) | |
73 | ||
74 | extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); | |
75 | ||
76 | /* A mask for all ISAs executed by the core. */ | |
77 | #define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask | |
78 | extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; | |
79 | ||
80 | #define MEP_INSN_CORE_P(insn) ( \ | |
81 | init_mep_all_core_isas_mask (), \ | |
82 | mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ | |
83 | ) | |
84 | ||
85 | /* A mask for all ISAs executed by a VLIW coprocessor. */ | |
86 | #define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask | |
87 | extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; | |
88 | ||
89 | #define MEP_INSN_COP_P(insn) ( \ | |
90 | init_mep_all_cop_isas_mask (), \ | |
91 | mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ | |
92 | ) | |
93 | ||
94 | extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); | |
95 | ||
96 | /* -- asm.c */ | |
97 | /* Enum declaration for mep instruction types. */ | |
98 | typedef enum cgen_insn_type { | |
99 | MEP_INSN_INVALID, MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW | |
100 | , MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU | |
101 | , MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP | |
102 | , MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP | |
103 | , MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16 | |
104 | , MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16 | |
105 | , MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24 | |
106 | , MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB | |
107 | , MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8 | |
108 | , MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH | |
109 | , MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3 | |
110 | , MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3 | |
111 | , MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3 | |
112 | , MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X | |
113 | , MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR | |
114 | , MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA | |
115 | , MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI | |
116 | , MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA | |
117 | , MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI | |
118 | , MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE | |
119 | , MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24 | |
120 | , MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT | |
121 | , MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC | |
122 | , MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC | |
123 | , MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT | |
124 | , MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM | |
125 | , MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM | |
126 | , MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE | |
127 | , MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU | |
128 | , MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU | |
129 | , MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK | |
130 | , MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN | |
131 | , MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP | |
132 | , MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU | |
133 | , MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP | |
134 | , MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI | |
135 | , MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16 | |
136 | , MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA | |
137 | , MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA | |
138 | , MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0 | |
139 | , MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0 | |
140 | , MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1 | |
141 | , MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1 | |
142 | , MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT | |
143 | , MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV | |
144 | , MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2 | |
145 | , MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6 | |
146 | , MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10 | |
147 | , MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14 | |
148 | , MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21 | |
149 | , MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25 | |
150 | , MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19 | |
151 | , MEP_INSN_FADDS, MEP_INSN_FSUBS, MEP_INSN_FMULS, MEP_INSN_FDIVS | |
152 | , MEP_INSN_FSQRTS, MEP_INSN_FABSS, MEP_INSN_FNEGS, MEP_INSN_FMOVS | |
153 | , MEP_INSN_FROUNDWS, MEP_INSN_FTRUNCWS, MEP_INSN_FCEILWS, MEP_INSN_FFLOORWS | |
154 | , MEP_INSN_FCVTWS, MEP_INSN_FCVTSW, MEP_INSN_FCMPFS, MEP_INSN_FCMPUS | |
155 | , MEP_INSN_FCMPES, MEP_INSN_FCMPUES, MEP_INSN_FCMPLS, MEP_INSN_FCMPULS | |
156 | , MEP_INSN_FCMPLES, MEP_INSN_FCMPULES, MEP_INSN_FCMPFIS, MEP_INSN_FCMPUIS | |
157 | , MEP_INSN_FCMPEIS, MEP_INSN_FCMPUEIS, MEP_INSN_FCMPLIS, MEP_INSN_FCMPULIS | |
158 | , MEP_INSN_FCMPLEIS, MEP_INSN_FCMPULEIS, MEP_INSN_CMOV_FRN_RM, MEP_INSN_CMOV_RM_FRN | |
159 | , MEP_INSN_CMOVC_CCRN_RM, MEP_INSN_CMOVC_RM_CCRN | |
160 | } CGEN_INSN_TYPE; | |
161 | ||
162 | /* Index of `invalid' insn place holder. */ | |
163 | #define CGEN_INSN_INVALID MEP_INSN_INVALID | |
164 | ||
165 | /* Total number of insns in table. */ | |
166 | #define MAX_INSNS ((int) MEP_INSN_CMOVC_RM_CCRN + 1) | |
167 | ||
168 | /* This struct records data prior to insertion or after extraction. */ | |
169 | struct cgen_fields | |
170 | { | |
171 | int length; | |
172 | long f_nil; | |
173 | long f_anyof; | |
174 | long f_major; | |
175 | long f_rn; | |
176 | long f_rn3; | |
177 | long f_rm; | |
178 | long f_rl; | |
179 | long f_sub2; | |
180 | long f_sub3; | |
181 | long f_sub4; | |
182 | long f_ext; | |
183 | long f_crn; | |
184 | long f_csrn_hi; | |
185 | long f_csrn_lo; | |
186 | long f_csrn; | |
187 | long f_crnx_hi; | |
188 | long f_crnx_lo; | |
189 | long f_crnx; | |
190 | long f_0; | |
191 | long f_1; | |
192 | long f_2; | |
193 | long f_3; | |
194 | long f_4; | |
195 | long f_5; | |
196 | long f_6; | |
197 | long f_7; | |
198 | long f_8; | |
199 | long f_9; | |
200 | long f_10; | |
201 | long f_11; | |
202 | long f_12; | |
203 | long f_13; | |
204 | long f_14; | |
205 | long f_15; | |
206 | long f_16; | |
207 | long f_17; | |
208 | long f_18; | |
209 | long f_19; | |
210 | long f_20; | |
211 | long f_21; | |
212 | long f_22; | |
213 | long f_23; | |
214 | long f_24; | |
215 | long f_25; | |
216 | long f_26; | |
217 | long f_27; | |
218 | long f_28; | |
219 | long f_29; | |
220 | long f_30; | |
221 | long f_31; | |
222 | long f_8s8a2; | |
223 | long f_12s4a2; | |
224 | long f_17s16a2; | |
225 | long f_24s5a2n_hi; | |
226 | long f_24s5a2n_lo; | |
227 | long f_24s5a2n; | |
228 | long f_24u5a2n_hi; | |
229 | long f_24u5a2n_lo; | |
230 | long f_24u5a2n; | |
231 | long f_2u6; | |
232 | long f_7u9; | |
233 | long f_7u9a2; | |
234 | long f_7u9a4; | |
235 | long f_16s16; | |
236 | long f_2u10; | |
237 | long f_3u5; | |
238 | long f_4u8; | |
239 | long f_5u8; | |
240 | long f_5u24; | |
241 | long f_6s8; | |
242 | long f_8s8; | |
243 | long f_16u16; | |
244 | long f_12u16; | |
245 | long f_3u29; | |
246 | long f_8s24; | |
247 | long f_8s24a2; | |
248 | long f_8s24a4; | |
249 | long f_8s24a8; | |
250 | long f_24u8a4n_hi; | |
251 | long f_24u8a4n_lo; | |
252 | long f_24u8a4n; | |
253 | long f_24u8n_hi; | |
254 | long f_24u8n_lo; | |
255 | long f_24u8n; | |
256 | long f_24u4n_hi; | |
257 | long f_24u4n_lo; | |
258 | long f_24u4n; | |
259 | long f_callnum; | |
260 | long f_ccrn_hi; | |
261 | long f_ccrn_lo; | |
262 | long f_ccrn; | |
263 | long f_fmax_0_4; | |
264 | long f_fmax_4_4; | |
265 | long f_fmax_8_4; | |
266 | long f_fmax_12_4; | |
267 | long f_fmax_16_4; | |
268 | long f_fmax_20_4; | |
269 | long f_fmax_24_4; | |
270 | long f_fmax_28_1; | |
271 | long f_fmax_29_1; | |
272 | long f_fmax_30_1; | |
273 | long f_fmax_31_1; | |
274 | long f_fmax_frd; | |
275 | long f_fmax_frn; | |
276 | long f_fmax_frm; | |
277 | long f_fmax_rm; | |
278 | }; | |
279 | ||
280 | #define CGEN_INIT_PARSE(od) \ | |
281 | {\ | |
282 | } | |
283 | #define CGEN_INIT_INSERT(od) \ | |
284 | {\ | |
285 | } | |
286 | #define CGEN_INIT_EXTRACT(od) \ | |
287 | {\ | |
288 | } | |
289 | #define CGEN_INIT_PRINT(od) \ | |
290 | {\ | |
291 | } | |
292 | ||
293 | ||
294 | #endif /* MEP_OPC_H */ |