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2008-09-26 Florian Krohm <fkrohm@us.ibm.com>
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
CommitLineData
252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
060d22b0 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
57b592a3 3 2000, 2001, 2002, 2003, 2005, 2007, 2008
73da6b6b 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
9b201bb5 7 This file is part of the GNU opcodes library.
252b5132 8
9b201bb5 9 This library is free software; you can redistribute it and/or modify
47b0e7ad 10 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
252b5132 13
9b201bb5
NC		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
252b5132 18
47b0e7ad
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
252b5132
RH		 24#include "sysdep.h"
25#include "dis-asm.h"
640c0ccd 26#include "libiberty.h"
252b5132
RH		 27#include "opcode/mips.h"
28#include "opintl.h"
29
30/* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
7f6621cd 33 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 34
35#if !defined(EMBEDDED_ENV)
36#define SYMTAB_AVAILABLE 1
37#include "elf-bfd.h"
38#include "elf/mips.h"
39#endif
40
aa5f19f2
NC		 41/* Mips instructions are at maximum this many bytes long. */
42#define INSNLEN 4
43
252b5132 44\f
aa5f19f2 45/* FIXME: These should be shared with gdb somehow. */
252b5132 46
47b0e7ad
NC		 47struct mips_cp0sel_name
48{
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
bbcc0807
CD		 52};
53
654c225a
TS		 54/* The mips16 registers. */
55static const unsigned int mips16_to_32_reg_map[] =
47b0e7ad 56{
654c225a 57 16, 17, 2, 3, 4, 5, 6, 7
252b5132 58};
fb48caed 59
654c225a
TS		 60#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
47b0e7ad
NC		 63static const char * const mips_gpr_names_numeric[32] =
64{
640c0ccd
CD		 65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 69};
70
47b0e7ad
NC		 71static const char * const mips_gpr_names_oldabi[32] =
72{
640c0ccd
CD		 73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 77};
78
47b0e7ad
NC		 79static const char * const mips_gpr_names_newabi[32] =
80{
640c0ccd 81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
0b14f26e 82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
640c0ccd
CD		 83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85};
86
47b0e7ad
NC		 87static const char * const mips_fpr_names_numeric[32] =
88{
640c0ccd
CD		 89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93};
94
47b0e7ad
NC		 95static const char * const mips_fpr_names_32[32] =
96{
640c0ccd
CD		 97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101};
102
47b0e7ad
NC		 103static const char * const mips_fpr_names_n32[32] =
104{
640c0ccd
CD		 105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109};
110
47b0e7ad
NC		 111static const char * const mips_fpr_names_64[32] =
112{
640c0ccd
CD		 113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117};
118
47b0e7ad
NC		 119static const char * const mips_cp0_names_numeric[32] =
120{
640c0ccd
CD		 121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125};
126
f409fd1e
MR		 127static const char * const mips_cp0_names_r3000[32] =
128{
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137};
138
139static const char * const mips_cp0_names_r4000[32] =
140{
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149};
150
47b0e7ad
NC		 151static const char * const mips_cp0_names_mips3264[32] =
152{
640c0ccd
CD		 153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161};
162
47b0e7ad
NC		 163static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164{
bbcc0807
CD		 165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194};
195
47b0e7ad
NC		 196static const char * const mips_cp0_names_mips3264r2[32] =
197{
af7ee8bf
CD		 198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206};
207
47b0e7ad
NC		 208static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209{
bbcc0807 210 { 4, 1, "c0_contextconfig" },
59c455b3
TS		 211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
bbcc0807 227 { 5, 1, "c0_pagegrain" },
59c455b3
TS		 228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
bbcc0807
CD		 233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282};
283
640c0ccd 284/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
47b0e7ad
NC		 285static const char * const mips_cp0_names_sb1[32] =
286{
640c0ccd
CD		 287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295};
296
47b0e7ad
NC		 297static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298{
bbcc0807
CD		 299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320};
321
47b0e7ad
NC		 322static const char * const mips_hwr_names_numeric[32] =
323{
af7ee8bf
CD		 324 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
325 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
326 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
327 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
328};
329
47b0e7ad
NC		 330static const char * const mips_hwr_names_mips3264r2[32] =
331{
af7ee8bf
CD		 332 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
333 "$4", "$5", "$6", "$7",
334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
336 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
337};
338
47b0e7ad
NC		 339struct mips_abi_choice
340{
341 const char * name;
640c0ccd
CD		 342 const char * const *gpr_names;
343 const char * const *fpr_names;
344};
345
47b0e7ad
NC		 346struct mips_abi_choice mips_abi_choices[] =
347{
640c0ccd
CD		 348 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
349 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
350 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
351 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
352};
353
47b0e7ad
NC		 354struct mips_arch_choice
355{
640c0ccd
CD		 356 const char *name;
357 int bfd_mach_valid;
358 unsigned long bfd_mach;
359 int processor;
360 int isa;
361 const char * const *cp0_names;
bbcc0807
CD		 362 const struct mips_cp0sel_name *cp0sel_names;
363 unsigned int cp0sel_names_len;
af7ee8bf 364 const char * const *hwr_names;
640c0ccd
CD		 365};
366
47b0e7ad
NC		 367const struct mips_arch_choice mips_arch_choices[] =
368{
640c0ccd 369 { "numeric", 0, 0, 0, 0,
bbcc0807
CD		 370 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
371
640c0ccd 372 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
f409fd1e 373 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
640c0ccd 374 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
bbcc0807 375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 376 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
f409fd1e 377 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
640c0ccd 378 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
bbcc0807 379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 380 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
bbcc0807 381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 382 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
bbcc0807 383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 384 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
bbcc0807 385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 386 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
bbcc0807 387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 388 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
f409fd1e 389 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
640c0ccd 390 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
bbcc0807 391 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 392 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
bbcc0807 393 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 394 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
bbcc0807 395 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 396 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
bbcc0807 397 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 398 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
bbcc0807 399 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 400 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
bbcc0807 401 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
5a7ea749
RS		 402 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
403 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
404 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
405 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 406 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
bbcc0807 407 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 408 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
bbcc0807 409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 410 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
bbcc0807 411 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 412 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
bbcc0807
CD		 413 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
414
640c0ccd
CD		 415 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
416 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
417 _MIPS32 Architecture For Programmers Volume I: Introduction to the
418 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
419 page 1. */
420 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
39a7806d 421 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
bbcc0807
CD		 422 mips_cp0_names_mips3264,
423 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
424 mips_hwr_names_numeric },
425
af7ee8bf 426 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
8b082fb1
TS		 427 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
428 | INSN_MIPS3D | INSN_MT),
bbcc0807
CD		 429 mips_cp0_names_mips3264r2,
430 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
431 mips_hwr_names_mips3264r2 },
432
640c0ccd
CD		 433 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
434 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
39a7806d 435 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
bbcc0807
CD		 436 mips_cp0_names_mips3264,
437 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
438 mips_hwr_names_numeric },
439
5f74bc13 440 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
8b082fb1
TS		 441 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
442 | INSN_DSP64 | INSN_MT | INSN_MDMX),
5f74bc13
CD		 443 mips_cp0_names_mips3264r2,
444 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
445 mips_hwr_names_mips3264r2 },
446
640c0ccd
CD		 447 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
448 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
bbcc0807
CD		 449 mips_cp0_names_sb1,
450 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
451 mips_hwr_names_numeric },
640c0ccd 452
350cc38d
MS		 453 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
454 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
455 NULL, 0, mips_hwr_names_numeric },
456
457 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
458 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
459 NULL, 0, mips_hwr_names_numeric },
460
57b592a3
AN		 461 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
462 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
463 mips_hwr_names_numeric },
464
640c0ccd
CD		 465 /* This entry, mips16, is here only for ISA/processor selection; do
466 not print its name. */
467 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
bbcc0807 468 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd
CD		 469};
470
471/* ISA and processor type to disassemble for, and register names to use.
472 set_default_mips_dis_options and parse_mips_dis_options fill in these
473 values. */
474static int mips_processor;
475static int mips_isa;
476static const char * const *mips_gpr_names;
477static const char * const *mips_fpr_names;
478static const char * const *mips_cp0_names;
bbcc0807
CD		 479static const struct mips_cp0sel_name *mips_cp0sel_names;
480static int mips_cp0sel_names_len;
af7ee8bf 481static const char * const *mips_hwr_names;
640c0ccd 482
986e18a5 483/* Other options */
47b0e7ad 484static int no_aliases; /* If set disassemble as most general inst. */
640c0ccd
CD		 485\f
486static const struct mips_abi_choice *
47b0e7ad 487choose_abi_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 488{
489 const struct mips_abi_choice *c;
490 unsigned int i;
491
492 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
47b0e7ad
NC		 493 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
494 && strlen (mips_abi_choices[i].name) == namelen)
495 c = &mips_abi_choices[i];
496
640c0ccd
CD		 497 return c;
498}
499
500static const struct mips_arch_choice *
47b0e7ad 501choose_arch_by_name (const char *name, unsigned int namelen)
640c0ccd
CD		 502{
503 const struct mips_arch_choice *c = NULL;
504 unsigned int i;
505
506 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
47b0e7ad
NC		 507 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
508 && strlen (mips_arch_choices[i].name) == namelen)
509 c = &mips_arch_choices[i];
510
640c0ccd
CD		 511 return c;
512}
513
514static const struct mips_arch_choice *
47b0e7ad 515choose_arch_by_number (unsigned long mach)
640c0ccd
CD		 516{
517 static unsigned long hint_bfd_mach;
518 static const struct mips_arch_choice *hint_arch_choice;
519 const struct mips_arch_choice *c;
520 unsigned int i;
521
522 /* We optimize this because even if the user specifies no
523 flags, this will be done for every instruction! */
524 if (hint_bfd_mach == mach
525 && hint_arch_choice != NULL
526 && hint_arch_choice->bfd_mach == hint_bfd_mach)
527 return hint_arch_choice;
528
529 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
530 {
531 if (mips_arch_choices[i].bfd_mach_valid
532 && mips_arch_choices[i].bfd_mach == mach)
533 {
534 c = &mips_arch_choices[i];
535 hint_bfd_mach = mach;
536 hint_arch_choice = c;
537 }
538 }
539 return c;
540}
541
47b0e7ad
NC		 542/* Check if the object uses NewABI conventions. */
543
544static int
545is_newabi (Elf_Internal_Ehdr *header)
546{
547 /* There are no old-style ABIs which use 64-bit ELF. */
548 if (header->e_ident[EI_CLASS] == ELFCLASS64)
549 return 1;
550
551 /* If a 32-bit ELF file, n32 is a new-style ABI. */
552 if ((header->e_flags & EF_MIPS_ABI2) != 0)
553 return 1;
554
555 return 0;
556}
557
558static void
559set_default_mips_dis_options (struct disassemble_info *info)
640c0ccd
CD		 560{
561 const struct mips_arch_choice *chosen_arch;
562
563 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
af7ee8bf 564 and numeric FPR, CP0 register, and HWR names. */
640c0ccd
CD		 565 mips_isa = ISA_MIPS3;
566 mips_processor = CPU_R3000;
567 mips_gpr_names = mips_gpr_names_oldabi;
568 mips_fpr_names = mips_fpr_names_numeric;
569 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 570 mips_cp0sel_names = NULL;
571 mips_cp0sel_names_len = 0;
af7ee8bf 572 mips_hwr_names = mips_hwr_names_numeric;
986e18a5 573 no_aliases = 0;
640c0ccd
CD		 574
575 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
fec06546 576 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
640c0ccd
CD		 577 {
578 Elf_Internal_Ehdr *header;
579
fec06546 580 header = elf_elfheader (info->section->owner);
640c0ccd
CD		 581 if (is_newabi (header))
582 mips_gpr_names = mips_gpr_names_newabi;
583 }
584
585 /* Set ISA, architecture, and cp0 register names as best we can. */
586#if ! SYMTAB_AVAILABLE
587 /* This is running out on a target machine, not in a host tool.
588 FIXME: Where does mips_target_info come from? */
589 target_processor = mips_target_info.processor;
590 mips_isa = mips_target_info.isa;
591#else
592 chosen_arch = choose_arch_by_number (info->mach);
593 if (chosen_arch != NULL)
594 {
595 mips_processor = chosen_arch->processor;
596 mips_isa = chosen_arch->isa;
bbcc0807
CD		 597 mips_cp0_names = chosen_arch->cp0_names;
598 mips_cp0sel_names = chosen_arch->cp0sel_names;
599 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
600 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 601 }
602#endif
603}
604
47b0e7ad
NC		 605static void
606parse_mips_dis_option (const char *option, unsigned int len)
640c0ccd
CD		 607{
608 unsigned int i, optionlen, vallen;
609 const char *val;
610 const struct mips_abi_choice *chosen_abi;
611 const struct mips_arch_choice *chosen_arch;
612
986e18a5 613 /* Try to match options that are simple flags */
0112cd26 614 if (CONST_STRNEQ (option, "no-aliases"))
986e18a5
FF		 615 {
616 no_aliases = 1;
617 return;
618 }
619
640c0ccd
CD		 620 /* Look for the = that delimits the end of the option name. */
621 for (i = 0; i < len; i++)
47b0e7ad
NC		 622 if (option[i] == '=')
623 break;
624
640c0ccd
CD		 625 if (i == 0) /* Invalid option: no name before '='. */
626 return;
627 if (i == len) /* Invalid option: no '='. */
628 return;
629 if (i == (len - 1)) /* Invalid option: no value after '='. */
630 return;
631
632 optionlen = i;
633 val = option + (optionlen + 1);
634 vallen = len - (optionlen + 1);
635
47b0e7ad
NC		 636 if (strncmp ("gpr-names", option, optionlen) == 0
637 && strlen ("gpr-names") == optionlen)
640c0ccd
CD		 638 {
639 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 640 if (chosen_abi != NULL)
640c0ccd
CD		 641 mips_gpr_names = chosen_abi->gpr_names;
642 return;
643 }
644
47b0e7ad
NC		 645 if (strncmp ("fpr-names", option, optionlen) == 0
646 && strlen ("fpr-names") == optionlen)
640c0ccd
CD		 647 {
648 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 649 if (chosen_abi != NULL)
640c0ccd
CD		 650 mips_fpr_names = chosen_abi->fpr_names;
651 return;
652 }
653
47b0e7ad
NC		 654 if (strncmp ("cp0-names", option, optionlen) == 0
655 && strlen ("cp0-names") == optionlen)
640c0ccd
CD		 656 {
657 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 658 if (chosen_arch != NULL)
659 {
660 mips_cp0_names = chosen_arch->cp0_names;
661 mips_cp0sel_names = chosen_arch->cp0sel_names;
662 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
663 }
640c0ccd
CD		 664 return;
665 }
666
47b0e7ad
NC		 667 if (strncmp ("hwr-names", option, optionlen) == 0
668 && strlen ("hwr-names") == optionlen)
af7ee8bf
CD		 669 {
670 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 671 if (chosen_arch != NULL)
af7ee8bf
CD		 672 mips_hwr_names = chosen_arch->hwr_names;
673 return;
674 }
675
47b0e7ad
NC		 676 if (strncmp ("reg-names", option, optionlen) == 0
677 && strlen ("reg-names") == optionlen)
640c0ccd
CD		 678 {
679 /* We check both ABI and ARCH here unconditionally, so
680 that "numeric" will do the desirable thing: select
681 numeric register names for all registers. Other than
682 that, a given name probably won't match both. */
683 chosen_abi = choose_abi_by_name (val, vallen);
684 if (chosen_abi != NULL)
685 {
bbcc0807
CD		 686 mips_gpr_names = chosen_abi->gpr_names;
687 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 688 }
689 chosen_arch = choose_arch_by_name (val, vallen);
690 if (chosen_arch != NULL)
691 {
bbcc0807
CD		 692 mips_cp0_names = chosen_arch->cp0_names;
693 mips_cp0sel_names = chosen_arch->cp0sel_names;
694 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
695 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 696 }
697 return;
698 }
699
700 /* Invalid option. */
701}
702
47b0e7ad
NC		 703static void
704parse_mips_dis_options (const char *options)
640c0ccd
CD		 705{
706 const char *option_end;
707
708 if (options == NULL)
709 return;
710
711 while (*options != '\0')
712 {
713 /* Skip empty options. */
714 if (*options == ',')
715 {
716 options++;
717 continue;
718 }
719
720 /* We know that *options is neither NUL or a comma. */
721 option_end = options + 1;
722 while (*option_end != ',' && *option_end != '\0')
723 option_end++;
724
725 parse_mips_dis_option (options, option_end - options);
726
727 /* Go on to the next one. If option_end points to a comma, it
728 will be skipped above. */
729 options = option_end;
730 }
731}
732
bbcc0807 733static const struct mips_cp0sel_name *
47b0e7ad
NC		 734lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
735 unsigned int len,
736 unsigned int cp0reg,
737 unsigned int sel)
bbcc0807
CD		 738{
739 unsigned int i;
740
741 for (i = 0; i < len; i++)
742 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
743 return &names[i];
744 return NULL;
745}
252b5132 746\f
7f6621cd 747/* Print insn arguments for 32/64-bit code. */
aa5f19f2 748
794ac9d0 749static void
47b0e7ad
NC		 750print_insn_args (const char *d,
751 register unsigned long int l,
752 bfd_vma pc,
cc0ca239
TS		 753 struct disassemble_info *info,
754 const struct mips_opcode *opp)
252b5132 755{
794ac9d0 756 int op, delta;
440cc0bc
CD		 757 unsigned int lsb, msb, msbd;
758
759 lsb = 0;
252b5132 760
794ac9d0 761 for (; *d != '\0'; d++)
252b5132 762 {
af7ee8bf
CD		 763 switch (*d)
764 {
794ac9d0
CD		 765 case ',':
766 case '(':
767 case ')':
768 case '[':
769 case ']':
770 (*info->fprintf_func) (info->stream, "%c", *d);
771 break;
772
773 case '+':
774 /* Extension character; switch for second char. */
775 d++;
776 switch (*d)
777 {
778 case '\0':
779 /* xgettext:c-format */
780 (*info->fprintf_func) (info->stream,
781 _("# internal error, incomplete extension sequence (+)"));
782 return;
783
784 case 'A':
440cc0bc
CD		 785 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
786 (*info->fprintf_func) (info->stream, "0x%x", lsb);
794ac9d0
CD		 787 break;
788
789 case 'B':
440cc0bc
CD		 790 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
791 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
794ac9d0
CD		 792 break;
793
9bcd4f99
TS		 794 case '1':
795 (*info->fprintf_func) (info->stream, "0x%lx",
796 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
797 break;
798
799 case '2':
800 (*info->fprintf_func) (info->stream, "0x%lx",
801 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
802 break;
803
804 case '3':
805 (*info->fprintf_func) (info->stream, "0x%lx",
806 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
807 break;
808
809 case '4':
810 (*info->fprintf_func) (info->stream, "0x%lx",
811 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
812 break;
813
794ac9d0 814 case 'C':
5f74bc13 815 case 'H':
440cc0bc
CD		 816 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
817 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
794ac9d0
CD		 818 break;
819
820 case 'D':
821 {
822 const struct mips_cp0sel_name *n;
823 unsigned int cp0reg, sel;
824
825 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
826 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
827
828 /* CP0 register including 'sel' code for mtcN (et al.), to be
829 printed textually if known. If not known, print both
830 CP0 register name and sel numerically since CP0 register
831 with sel 0 may have a name unrelated to register being
832 printed. */
833 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
834 mips_cp0sel_names_len, cp0reg, sel);
835 if (n != NULL)
836 (*info->fprintf_func) (info->stream, "%s", n->name);
837 else
838 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
839 break;
840 }
841
5f74bc13
CD		 842 case 'E':
843 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
844 (*info->fprintf_func) (info->stream, "0x%x", lsb);
845 break;
846
847 case 'F':
848 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
849 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
850 break;
851
852 case 'G':
853 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
854 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
855 break;
856
61cc0267
CF		 857 case 't': /* Coprocessor 0 reg name */
858 (*info->fprintf_func) (info->stream, "%s",
859 mips_cp0_names[(l >> OP_SH_RT) &
860 OP_MASK_RT]);
861 break;
862
863 case 'T': /* Coprocessor 0 reg name */
864 {
865 const struct mips_cp0sel_name *n;
866 unsigned int cp0reg, sel;
867
868 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
869 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
870
871 /* CP0 register including 'sel' code for mftc0, to be
872 printed textually if known. If not known, print both
873 CP0 register name and sel numerically since CP0 register
874 with sel 0 may have a name unrelated to register being
875 printed. */
876 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
877 mips_cp0sel_names_len, cp0reg, sel);
878 if (n != NULL)
879 (*info->fprintf_func) (info->stream, "%s", n->name);
880 else
881 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
882 break;
883 }
884
bb35fb24
NC		 885 case 'x': /* bbit bit index */
886 (*info->fprintf_func) (info->stream, "0x%lx",
887 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
888 break;
889
890 case 'p': /* cins, cins32, exts and exts32 position */
891 (*info->fprintf_func) (info->stream, "0x%lx",
892 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
893 break;
894
895 case 's': /* cins and exts length-minus-one */
896 (*info->fprintf_func) (info->stream, "0x%lx",
897 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
898 break;
899
900 case 'S': /* cins32 and exts32 length-minus-one field */
901 (*info->fprintf_func) (info->stream, "0x%lx",
902 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
903 break;
904
dd3cbb7e
NC		 905 case 'Q': /* seqi/snei immediate field */
906 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
907 /* Sign-extend it. */
908 op = (op ^ 512) - 512;
909 (*info->fprintf_func) (info->stream, "%d", op);
910 break;
911
794ac9d0
CD		 912 default:
913 /* xgettext:c-format */
914 (*info->fprintf_func) (info->stream,
915 _("# internal error, undefined extension sequence (+%c)"),
916 *d);
917 return;
918 }
919 break;
920
8b082fb1
TS		 921 case '2':
922 (*info->fprintf_func) (info->stream, "0x%lx",
923 (l >> OP_SH_BP) & OP_MASK_BP);
924 break;
925
fd25c5a9
CF		 926 case '3':
927 (*info->fprintf_func) (info->stream, "0x%lx",
928 (l >> OP_SH_SA3) & OP_MASK_SA3);
929 break;
930
931 case '4':
932 (*info->fprintf_func) (info->stream, "0x%lx",
933 (l >> OP_SH_SA4) & OP_MASK_SA4);
934 break;
935
936 case '5':
937 (*info->fprintf_func) (info->stream, "0x%lx",
938 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
939 break;
940
941 case '6':
942 (*info->fprintf_func) (info->stream, "0x%lx",
943 (l >> OP_SH_RS) & OP_MASK_RS);
944 break;
945
946 case '7':
947 (*info->fprintf_func) (info->stream, "$ac%ld",
948 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
949 break;
950
951 case '8':
952 (*info->fprintf_func) (info->stream, "0x%lx",
953 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
954 break;
955
956 case '9':
957 (*info->fprintf_func) (info->stream, "$ac%ld",
958 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
959 break;
960
961 case '0': /* dsp 6-bit signed immediate in bit 20 */
962 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
963 if (delta & 0x20) /* test sign bit */
964 delta |= ~OP_MASK_DSPSFT;
965 (*info->fprintf_func) (info->stream, "%d", delta);
966 break;
967
968 case ':': /* dsp 7-bit signed immediate in bit 19 */
969 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
970 if (delta & 0x40) /* test sign bit */
971 delta |= ~OP_MASK_DSPSFT_7;
972 (*info->fprintf_func) (info->stream, "%d", delta);
973 break;
974
975 case '\'':
976 (*info->fprintf_func) (info->stream, "0x%lx",
977 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
978 break;
979
980 case '@': /* dsp 10-bit signed immediate in bit 16 */
981 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
982 if (delta & 0x200) /* test sign bit */
983 delta |= ~OP_MASK_IMM10;
984 (*info->fprintf_func) (info->stream, "%d", delta);
985 break;
986
61cc0267
CF		 987 case '!':
988 (*info->fprintf_func) (info->stream, "%ld",
989 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
990 break;
991
992 case '$':
993 (*info->fprintf_func) (info->stream, "%ld",
994 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
995 break;
996
997 case '*':
998 (*info->fprintf_func) (info->stream, "$ac%ld",
999 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1000 break;
1001
1002 case '&':
1003 (*info->fprintf_func) (info->stream, "$ac%ld",
1004 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1005 break;
1006
1007 case 'g':
1008 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1009 (*info->fprintf_func) (info->stream, "$%ld",
1010 (l >> OP_SH_RD) & OP_MASK_RD);
1011 break;
1012
794ac9d0
CD		 1013 case 's':
1014 case 'b':
1015 case 'r':
1016 case 'v':
1017 (*info->fprintf_func) (info->stream, "%s",
1018 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1019 break;
1020
1021 case 't':
1022 case 'w':
1023 (*info->fprintf_func) (info->stream, "%s",
1024 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1025 break;
1026
1027 case 'i':
1028 case 'u':
0fd3a477 1029 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1030 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1031 break;
1032
1033 case 'j': /* Same as i, but sign-extended. */
1034 case 'o':
1035 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1036 if (delta & 0x8000)
1037 delta |= ~0xffff;
1038 (*info->fprintf_func) (info->stream, "%d",
1039 delta);
1040 break;
1041
1042 case 'h':
1043 (*info->fprintf_func) (info->stream, "0x%x",
1044 (unsigned int) ((l >> OP_SH_PREFX)
1045 & OP_MASK_PREFX));
1046 break;
1047
1048 case 'k':
1049 (*info->fprintf_func) (info->stream, "0x%x",
1050 (unsigned int) ((l >> OP_SH_CACHE)
1051 & OP_MASK_CACHE));
1052 break;
1053
1054 case 'a':
1055 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1056 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
022fac6d
TS		 1057 /* For gdb disassembler, force odd address on jalx. */
1058 if (info->flavour == bfd_target_unknown_flavour
1059 && strcmp (opp->name, "jalx") == 0)
1060 info->target |= 1;
794ac9d0
CD		 1061 (*info->print_address_func) (info->target, info);
1062 break;
1063
1064 case 'p':
1065 /* Sign extend the displacement. */
1066 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1067 if (delta & 0x8000)
1068 delta |= ~0xffff;
1069 info->target = (delta << 2) + pc + INSNLEN;
1070 (*info->print_address_func) (info->target, info);
1071 break;
1072
1073 case 'd':
1074 (*info->fprintf_func) (info->stream, "%s",
1075 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1076 break;
1077
1078 case 'U':
1079 {
1080 /* First check for both rd and rt being equal. */
1081 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1082 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1083 (*info->fprintf_func) (info->stream, "%s",
1084 mips_gpr_names[reg]);
1085 else
1086 {
1087 /* If one is zero use the other. */
1088 if (reg == 0)
1089 (*info->fprintf_func) (info->stream, "%s",
1090 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1091 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1092 (*info->fprintf_func) (info->stream, "%s",
1093 mips_gpr_names[reg]);
1094 else /* Bogus, result depends on processor. */
1095 (*info->fprintf_func) (info->stream, "%s or %s",
1096 mips_gpr_names[reg],
1097 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1098 }
1099 }
1100 break;
1101
1102 case 'z':
1103 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1104 break;
1105
1106 case '<':
0fd3a477 1107 (*info->fprintf_func) (info->stream, "0x%lx",
af7ee8bf
CD		 1108 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1109 break;
794ac9d0
CD		 1110
1111 case 'c':
0fd3a477 1112 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1113 (l >> OP_SH_CODE) & OP_MASK_CODE);
1114 break;
1115
1116 case 'q':
0fd3a477 1117 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0 1118 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
af7ee8bf
CD		 1119 break;
1120
1121 case 'C':
0fd3a477 1122 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1123 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1124 break;
1125
1126 case 'B':
0fd3a477
JW		 1127 (*info->fprintf_func) (info->stream, "0x%lx",
1128
794ac9d0
CD		 1129 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1130 break;
1131
1132 case 'J':
0fd3a477 1133 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1134 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1135 break;
1136
1137 case 'S':
1138 case 'V':
1139 (*info->fprintf_func) (info->stream, "%s",
1140 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1141 break;
1142
1143 case 'T':
1144 case 'W':
1145 (*info->fprintf_func) (info->stream, "%s",
1146 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
af7ee8bf
CD		 1147 break;
1148
bbcc0807 1149 case 'D':
794ac9d0
CD		 1150 (*info->fprintf_func) (info->stream, "%s",
1151 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1152 break;
1153
1154 case 'R':
1155 (*info->fprintf_func) (info->stream, "%s",
1156 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1157 break;
1158
1159 case 'E':
1160 /* Coprocessor register for lwcN instructions, et al.
1161
1162 Note that there is no load/store cp0 instructions, and
1163 that FPU (cp1) instructions disassemble this field using
1164 'T' format. Therefore, until we gain understanding of
1165 cp2 register names, we can simply print the register
1166 numbers. */
0fd3a477 1167 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1168 (l >> OP_SH_RT) & OP_MASK_RT);
1169 break;
1170
1171 case 'G':
1172 /* Coprocessor register for mtcN instructions, et al. Note
1173 that FPU (cp1) instructions disassemble this field using
1174 'S' format. Therefore, we only need to worry about cp0,
1175 cp2, and cp3. */
1176 op = (l >> OP_SH_OP) & OP_MASK_OP;
1177 if (op == OP_OP_COP0)
1178 (*info->fprintf_func) (info->stream, "%s",
1179 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1180 else
0fd3a477 1181 (*info->fprintf_func) (info->stream, "$%ld",
794ac9d0
CD		 1182 (l >> OP_SH_RD) & OP_MASK_RD);
1183 break;
1184
1185 case 'K':
1186 (*info->fprintf_func) (info->stream, "%s",
1187 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1188 break;
1189
1190 case 'N':
0d09bfe6
TS		 1191 (*info->fprintf_func) (info->stream,
1192 ((opp->pinfo & (FP_D | FP_S)) != 0
1193 ? "$fcc%ld" : "$cc%ld"),
794ac9d0
CD		 1194 (l >> OP_SH_BCC) & OP_MASK_BCC);
1195 break;
1196
1197 case 'M':
0fd3a477 1198 (*info->fprintf_func) (info->stream, "$fcc%ld",
794ac9d0
CD		 1199 (l >> OP_SH_CCC) & OP_MASK_CCC);
1200 break;
1201
1202 case 'P':
0fd3a477 1203 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1204 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1205 break;
1206
1207 case 'e':
0fd3a477 1208 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1209 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1210 break;
1211
1212 case '%':
0fd3a477 1213 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1214 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1215 break;
1216
1217 case 'H':
0fd3a477 1218 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1219 (l >> OP_SH_SEL) & OP_MASK_SEL);
1220 break;
1221
1222 case 'O':
0fd3a477 1223 (*info->fprintf_func) (info->stream, "%ld",
794ac9d0
CD		 1224 (l >> OP_SH_ALN) & OP_MASK_ALN);
1225 break;
1226
1227 case 'Q':
bbcc0807 1228 {
794ac9d0 1229 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
47b0e7ad 1230
794ac9d0
CD		 1231 if ((vsel & 0x10) == 0)
1232 {
1233 int fmt;
47b0e7ad 1234
794ac9d0
CD		 1235 vsel &= 0x0f;
1236 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1237 if ((vsel & 1) == 0)
1238 break;
0fd3a477 1239 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
794ac9d0
CD		 1240 (l >> OP_SH_FT) & OP_MASK_FT,
1241 vsel >> 1);
1242 }
1243 else if ((vsel & 0x08) == 0)
1244 {
0fd3a477 1245 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1246 (l >> OP_SH_FT) & OP_MASK_FT);
1247 }
bbcc0807 1248 else
794ac9d0 1249 {
0fd3a477 1250 (*info->fprintf_func) (info->stream, "0x%lx",
794ac9d0
CD		 1251 (l >> OP_SH_FT) & OP_MASK_FT);
1252 }
bbcc0807 1253 }
794ac9d0
CD		 1254 break;
1255
1256 case 'X':
0fd3a477 1257 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1258 (l >> OP_SH_FD) & OP_MASK_FD);
1259 break;
1260
1261 case 'Y':
0fd3a477 1262 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1263 (l >> OP_SH_FS) & OP_MASK_FS);
1264 break;
1265
1266 case 'Z':
0fd3a477 1267 (*info->fprintf_func) (info->stream, "$v%ld",
794ac9d0
CD		 1268 (l >> OP_SH_FT) & OP_MASK_FT);
1269 break;
bbcc0807 1270
af7ee8bf
CD		 1271 default:
1272 /* xgettext:c-format */
1273 (*info->fprintf_func) (info->stream,
168411b1 1274 _("# internal error, undefined modifier (%c)"),
af7ee8bf 1275 *d);
794ac9d0 1276 return;
af7ee8bf 1277 }
252b5132
RH		 1278 }
1279}
1280\f
252b5132
RH		 1281/* Print the mips instruction at address MEMADDR in debugged memory,
1282 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1283 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1284 this is little-endian code. */
1285
1286static int
47b0e7ad
NC		 1287print_insn_mips (bfd_vma memaddr,
1288 unsigned long int word,
1289 struct disassemble_info *info)
252b5132 1290{
47b0e7ad 1291 const struct mips_opcode *op;
b34976b6 1292 static bfd_boolean init = 0;
252b5132
RH		 1293 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1294
1295 /* Build a hash table to shorten the search time. */
1296 if (! init)
1297 {
1298 unsigned int i;
1299
1300 for (i = 0; i <= OP_MASK_OP; i++)
1301 {
1302 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1303 {
986e18a5 1304 if (op->pinfo == INSN_MACRO
9e836e3d 1305 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
252b5132
RH		 1306 continue;
1307 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1308 {
1309 mips_hash[i] = op;
1310 break;
1311 }
1312 }
7f6621cd 1313 }
252b5132
RH		 1314
1315 init = 1;
1316 }
1317
aa5f19f2 1318 info->bytes_per_chunk = INSNLEN;
252b5132 1319 info->display_endian = info->endian;
9bb28706
CD		 1320 info->insn_info_valid = 1;
1321 info->branch_delay_insns = 0;
def7143b 1322 info->data_size = 0;
9bb28706
CD		 1323 info->insn_type = dis_nonbranch;
1324 info->target = 0;
1325 info->target2 = 0;
252b5132
RH		 1326
1327 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1328 if (op != NULL)
1329 {
1330 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1331 {
986e18a5 1332 if (op->pinfo != INSN_MACRO
9e836e3d 1333 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
986e18a5 1334 && (word & op->mask) == op->match)
252b5132 1335 {
47b0e7ad 1336 const char *d;
2bd7f1f3 1337
3396de36 1338 /* We always allow to disassemble the jalx instruction. */
640c0ccd 1339 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3396de36 1340 && strcmp (op->name, "jalx"))
252b5132
RH		 1341 continue;
1342
9bb28706
CD		 1343 /* Figure out instruction type and branch delay information. */
1344 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1345 {
1346 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1347 info->insn_type = dis_jsr;
1348 else
1349 info->insn_type = dis_branch;
1350 info->branch_delay_insns = 1;
1351 }
1352 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1353 | INSN_COND_BRANCH_LIKELY)) != 0)
1354 {
1355 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1356 info->insn_type = dis_condjsr;
1357 else
1358 info->insn_type = dis_condbranch;
1359 info->branch_delay_insns = 1;
1360 }
1361 else if ((op->pinfo & (INSN_STORE_MEMORY
1362 | INSN_LOAD_MEMORY_DELAY)) != 0)
1363 info->insn_type = dis_dref;
1364
252b5132
RH		 1365 (*info->fprintf_func) (info->stream, "%s", op->name);
1366
1367 d = op->args;
1368 if (d != NULL && *d != '\0')
1369 {
7f6621cd 1370 (*info->fprintf_func) (info->stream, "\t");
cc0ca239 1371 print_insn_args (d, word, memaddr, info, op);
252b5132
RH		 1372 }
1373
aa5f19f2 1374 return INSNLEN;
252b5132
RH		 1375 }
1376 }
1377 }
1378
1379 /* Handle undefined instructions. */
9bb28706 1380 info->insn_type = dis_noninsn;
0fd3a477 1381 (*info->fprintf_func) (info->stream, "0x%lx", word);
aa5f19f2 1382 return INSNLEN;
252b5132 1383}
aa5f19f2 1384\f
252b5132
RH		 1385/* Disassemble an operand for a mips16 instruction. */
1386
1387static void
47b0e7ad
NC		 1388print_mips16_insn_arg (char type,
1389 const struct mips_opcode *op,
1390 int l,
1391 bfd_boolean use_extend,
1392 int extend,
1393 bfd_vma memaddr,
1394 struct disassemble_info *info)
252b5132
RH		 1395{
1396 switch (type)
1397 {
1398 case ',':
1399 case '(':
1400 case ')':
1401 (*info->fprintf_func) (info->stream, "%c", type);
1402 break;
1403
1404 case 'y':
1405 case 'w':
aa5f19f2 1406 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1407 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1408 & MIPS16OP_MASK_RY)));
252b5132
RH		 1409 break;
1410
1411 case 'x':
1412 case 'v':
aa5f19f2 1413 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1414 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1415 & MIPS16OP_MASK_RX)));
252b5132
RH		 1416 break;
1417
1418 case 'z':
aa5f19f2 1419 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1420 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1421 & MIPS16OP_MASK_RZ)));
252b5132
RH		 1422 break;
1423
1424 case 'Z':
aa5f19f2 1425 (*info->fprintf_func) (info->stream, "%s",
654c225a
TS		 1426 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1427 & MIPS16OP_MASK_MOVE32Z)));
252b5132
RH		 1428 break;
1429
1430 case '0':
640c0ccd 1431 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
252b5132
RH		 1432 break;
1433
1434 case 'S':
640c0ccd 1435 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
252b5132
RH		 1436 break;
1437
1438 case 'P':
1439 (*info->fprintf_func) (info->stream, "$pc");
1440 break;
1441
1442 case 'R':
640c0ccd 1443 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
252b5132
RH		 1444 break;
1445
1446 case 'X':
aa5f19f2 1447 (*info->fprintf_func) (info->stream, "%s",
640c0ccd
CD		 1448 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1449 & MIPS16OP_MASK_REGR32)]);
252b5132
RH		 1450 break;
1451
1452 case 'Y':
aa5f19f2 1453 (*info->fprintf_func) (info->stream, "%s",
640c0ccd 1454 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
252b5132
RH		 1455 break;
1456
1457 case '<':
1458 case '>':
1459 case '[':
1460 case ']':
1461 case '4':
1462 case '5':
1463 case 'H':
1464 case 'W':
1465 case 'D':
1466 case 'j':
1467 case '6':
1468 case '8':
1469 case 'V':
1470 case 'C':
1471 case 'U':
1472 case 'k':
1473 case 'K':
1474 case 'p':
1475 case 'q':
1476 case 'A':
1477 case 'B':
1478 case 'E':
1479 {
1480 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1481
1482 shift = 0;
1483 signedp = 0;
1484 extbits = 16;
1485 pcrel = 0;
1486 extu = 0;
1487 branch = 0;
1488 switch (type)
1489 {
1490 case '<':
1491 nbits = 3;
1492 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1493 extbits = 5;
1494 extu = 1;
1495 break;
1496 case '>':
1497 nbits = 3;
1498 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1499 extbits = 5;
1500 extu = 1;
1501 break;
1502 case '[':
1503 nbits = 3;
1504 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1505 extbits = 6;
1506 extu = 1;
1507 break;
1508 case ']':
1509 nbits = 3;
1510 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1511 extbits = 6;
1512 extu = 1;
1513 break;
1514 case '4':
1515 nbits = 4;
1516 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1517 signedp = 1;
1518 extbits = 15;
1519 break;
1520 case '5':
1521 nbits = 5;
1522 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1523 info->insn_type = dis_dref;
1524 info->data_size = 1;
1525 break;
1526 case 'H':
1527 nbits = 5;
1528 shift = 1;
1529 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1530 info->insn_type = dis_dref;
1531 info->data_size = 2;
1532 break;
1533 case 'W':
1534 nbits = 5;
1535 shift = 2;
1536 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1537 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1538 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1539 {
1540 info->insn_type = dis_dref;
1541 info->data_size = 4;
1542 }
1543 break;
1544 case 'D':
1545 nbits = 5;
1546 shift = 3;
1547 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1548 info->insn_type = dis_dref;
1549 info->data_size = 8;
1550 break;
1551 case 'j':
1552 nbits = 5;
1553 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1554 signedp = 1;
1555 break;
1556 case '6':
1557 nbits = 6;
1558 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1559 break;
1560 case '8':
1561 nbits = 8;
1562 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1563 break;
1564 case 'V':
1565 nbits = 8;
1566 shift = 2;
1567 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1568 /* FIXME: This might be lw, or it might be addiu to $sp or
1569 $pc. We assume it's load. */
1570 info->insn_type = dis_dref;
1571 info->data_size = 4;
1572 break;
1573 case 'C':
1574 nbits = 8;
1575 shift = 3;
1576 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1577 info->insn_type = dis_dref;
1578 info->data_size = 8;
1579 break;
1580 case 'U':
1581 nbits = 8;
1582 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1583 extu = 1;
1584 break;
1585 case 'k':
1586 nbits = 8;
1587 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1588 signedp = 1;
1589 break;
1590 case 'K':
1591 nbits = 8;
1592 shift = 3;
1593 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1594 signedp = 1;
1595 break;
1596 case 'p':
1597 nbits = 8;
1598 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1599 signedp = 1;
1600 pcrel = 1;
1601 branch = 1;
1602 info->insn_type = dis_condbranch;
1603 break;
1604 case 'q':
1605 nbits = 11;
1606 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1607 signedp = 1;
1608 pcrel = 1;
1609 branch = 1;
1610 info->insn_type = dis_branch;
1611 break;
1612 case 'A':
1613 nbits = 8;
1614 shift = 2;
1615 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1616 pcrel = 1;
1617 /* FIXME: This can be lw or la. We assume it is lw. */
1618 info->insn_type = dis_dref;
1619 info->data_size = 4;
1620 break;
1621 case 'B':
1622 nbits = 5;
1623 shift = 3;
1624 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1625 pcrel = 1;
1626 info->insn_type = dis_dref;
1627 info->data_size = 8;
1628 break;
1629 case 'E':
1630 nbits = 5;
1631 shift = 2;
1632 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1633 pcrel = 1;
1634 break;
1635 default:
1636 abort ();
1637 }
1638
1639 if (! use_extend)
1640 {
1641 if (signedp && immed >= (1 << (nbits - 1)))
1642 immed -= 1 << nbits;
1643 immed <<= shift;
1644 if ((type == '<' || type == '>' || type == '[' || type == ']')
1645 && immed == 0)
1646 immed = 8;
1647 }
1648 else
1649 {
1650 if (extbits == 16)
1651 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1652 else if (extbits == 15)
1653 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1654 else
1655 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1656 immed &= (1 << extbits) - 1;
1657 if (! extu && immed >= (1 << (extbits - 1)))
1658 immed -= 1 << extbits;
1659 }
1660
1661 if (! pcrel)
1662 (*info->fprintf_func) (info->stream, "%d", immed);
1663 else
1664 {
1665 bfd_vma baseaddr;
252b5132
RH		 1666
1667 if (branch)
1668 {
1669 immed *= 2;
1670 baseaddr = memaddr + 2;
1671 }
1672 else if (use_extend)
1673 baseaddr = memaddr - 2;
1674 else
1675 {
1676 int status;
1677 bfd_byte buffer[2];
1678
1679 baseaddr = memaddr;
1680
1681 /* If this instruction is in the delay slot of a jr
1682 instruction, the base address is the address of the
1683 jr instruction. If it is in the delay slot of jalr
1684 instruction, the base address is the address of the
1685 jalr instruction. This test is unreliable: we have
1686 no way of knowing whether the previous word is
1687 instruction or data. */
1688 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1689 info);
1690 if (status == 0
1691 && (((info->endian == BFD_ENDIAN_BIG
1692 ? bfd_getb16 (buffer)
1693 : bfd_getl16 (buffer))
1694 & 0xf800) == 0x1800))
1695 baseaddr = memaddr - 4;
1696 else
1697 {
1698 status = (*info->read_memory_func) (memaddr - 2, buffer,
1699 2, info);
1700 if (status == 0
1701 && (((info->endian == BFD_ENDIAN_BIG
1702 ? bfd_getb16 (buffer)
1703 : bfd_getl16 (buffer))
1704 & 0xf81f) == 0xe800))
1705 baseaddr = memaddr - 2;
1706 }
1707 }
9bb28706 1708 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
022fac6d
TS		 1709 if (pcrel && branch
1710 && info->flavour == bfd_target_unknown_flavour)
1711 /* For gdb disassembler, maintain odd address. */
1712 info->target |= 1;
9bb28706 1713 (*info->print_address_func) (info->target, info);
252b5132
RH		 1714 }
1715 }
1716 break;
1717
1718 case 'a':
022fac6d
TS		 1719 {
1720 int jalx = l & 0x400;
1721
1722 if (! use_extend)
1723 extend = 0;
1724 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1725 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1726 /* For gdb disassembler, maintain odd address. */
1727 l |= 1;
1728 }
9bb28706
CD		 1729 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1730 (*info->print_address_func) (info->target, info);
252b5132 1731 info->insn_type = dis_jsr;
252b5132
RH		 1732 info->branch_delay_insns = 1;
1733 break;
1734
1735 case 'l':
1736 case 'L':
1737 {
1738 int need_comma, amask, smask;
1739
1740 need_comma = 0;
1741
1742 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1743
1744 amask = (l >> 3) & 7;
1745
1746 if (amask > 0 && amask < 5)
1747 {
640c0ccd 1748 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
252b5132 1749 if (amask > 1)
aa5f19f2 1750 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1751 mips_gpr_names[amask + 3]);
252b5132
RH		 1752 need_comma = 1;
1753 }
1754
1755 smask = (l >> 1) & 3;
1756 if (smask == 3)
1757 {
1758 (*info->fprintf_func) (info->stream, "%s??",
1759 need_comma ? "," : "");
1760 need_comma = 1;
1761 }
1762 else if (smask > 0)
1763 {
aa5f19f2 1764 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1765 need_comma ? "," : "",
640c0ccd 1766 mips_gpr_names[16]);
252b5132 1767 if (smask > 1)
aa5f19f2 1768 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1769 mips_gpr_names[smask + 15]);
252b5132
RH		 1770 need_comma = 1;
1771 }
1772
1773 if (l & 1)
1774 {
aa5f19f2 1775 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1776 need_comma ? "," : "",
640c0ccd 1777 mips_gpr_names[31]);
252b5132
RH		 1778 need_comma = 1;
1779 }
1780
1781 if (amask == 5 || amask == 6)
1782 {
1783 (*info->fprintf_func) (info->stream, "%s$f0",
1784 need_comma ? "," : "");
1785 if (amask == 6)
1786 (*info->fprintf_func) (info->stream, "-$f1");
1787 }
1788 }
1789 break;
1790
0499d65b
TS		 1791 case 'm':
1792 case 'M':
1793 /* MIPS16e save/restore. */
1794 {
1795 int need_comma = 0;
1796 int amask, args, statics;
1797 int nsreg, smask;
1798 int framesz;
1799 int i, j;
1800
1801 l = l & 0x7f;
1802 if (use_extend)
1803 l |= extend << 16;
1804
1805 amask = (l >> 16) & 0xf;
1806 if (amask == MIPS16_ALL_ARGS)
1807 {
1808 args = 4;
1809 statics = 0;
1810 }
1811 else if (amask == MIPS16_ALL_STATICS)
1812 {
1813 args = 0;
1814 statics = 4;
1815 }
1816 else
1817 {
1818 args = amask >> 2;
1819 statics = amask & 3;
1820 }
1821
1822 if (args > 0) {
1823 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1824 if (args > 1)
1825 (*info->fprintf_func) (info->stream, "-%s",
1826 mips_gpr_names[4 + args - 1]);
1827 need_comma = 1;
1828 }
1829
1830 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1831 if (framesz == 0 && !use_extend)
1832 framesz = 128;
1833
1834 (*info->fprintf_func) (info->stream, "%s%d",
1835 need_comma ? "," : "",
1836 framesz);
1837
1838 if (l & 0x40) /* $ra */
1839 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1840
1841 nsreg = (l >> 24) & 0x7;
1842 smask = 0;
1843 if (l & 0x20) /* $s0 */
1844 smask |= 1 << 0;
1845 if (l & 0x10) /* $s1 */
1846 smask |= 1 << 1;
1847 if (nsreg > 0) /* $s2-$s8 */
1848 smask |= ((1 << nsreg) - 1) << 2;
1849
1850 /* Find first set static reg bit. */
1851 for (i = 0; i < 9; i++)
1852 {
1853 if (smask & (1 << i))
1854 {
1855 (*info->fprintf_func) (info->stream, ",%s",
1856 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1857 /* Skip over string of set bits. */
1858 for (j = i; smask & (2 << j); j++)
1859 continue;
1860 if (j > i)
1861 (*info->fprintf_func) (info->stream, "-%s",
1862 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1863 i = j + 1;
1864 }
1865 }
1866
1867 /* Statics $ax - $a3. */
1868 if (statics == 1)
1869 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1870 else if (statics > 0)
1871 (*info->fprintf_func) (info->stream, ",%s-%s",
1872 mips_gpr_names[7 - statics + 1],
1873 mips_gpr_names[7]);
1874 }
1875 break;
1876
252b5132 1877 default:
aa5f19f2
NC		 1878 /* xgettext:c-format */
1879 (*info->fprintf_func)
1880 (info->stream,
1881 _("# internal disassembler error, unrecognised modifier (%c)"),
1882 type);
252b5132
RH		 1883 abort ();
1884 }
1885}
640c0ccd 1886
47b0e7ad
NC		 1887/* Disassemble mips16 instructions. */
1888
1889static int
1890print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1891{
1892 int status;
1893 bfd_byte buffer[2];
1894 int length;
1895 int insn;
1896 bfd_boolean use_extend;
1897 int extend = 0;
1898 const struct mips_opcode *op, *opend;
1899
1900 info->bytes_per_chunk = 2;
1901 info->display_endian = info->endian;
1902 info->insn_info_valid = 1;
1903 info->branch_delay_insns = 0;
1904 info->data_size = 0;
1905 info->insn_type = dis_nonbranch;
1906 info->target = 0;
1907 info->target2 = 0;
1908
1909 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1910 if (status != 0)
1911 {
1912 (*info->memory_error_func) (status, memaddr, info);
1913 return -1;
1914 }
1915
1916 length = 2;
1917
1918 if (info->endian == BFD_ENDIAN_BIG)
1919 insn = bfd_getb16 (buffer);
1920 else
1921 insn = bfd_getl16 (buffer);
1922
1923 /* Handle the extend opcode specially. */
1924 use_extend = FALSE;
1925 if ((insn & 0xf800) == 0xf000)
1926 {
1927 use_extend = TRUE;
1928 extend = insn & 0x7ff;
1929
1930 memaddr += 2;
1931
1932 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1933 if (status != 0)
1934 {
1935 (*info->fprintf_func) (info->stream, "extend 0x%x",
1936 (unsigned int) extend);
1937 (*info->memory_error_func) (status, memaddr, info);
1938 return -1;
1939 }
1940
1941 if (info->endian == BFD_ENDIAN_BIG)
1942 insn = bfd_getb16 (buffer);
1943 else
1944 insn = bfd_getl16 (buffer);
1945
1946 /* Check for an extend opcode followed by an extend opcode. */
1947 if ((insn & 0xf800) == 0xf000)
1948 {
1949 (*info->fprintf_func) (info->stream, "extend 0x%x",
1950 (unsigned int) extend);
1951 info->insn_type = dis_noninsn;
1952 return length;
1953 }
1954
1955 length += 2;
1956 }
1957
1958 /* FIXME: Should probably use a hash table on the major opcode here. */
1959
1960 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1961 for (op = mips16_opcodes; op < opend; op++)
1962 {
1963 if (op->pinfo != INSN_MACRO
1964 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1965 && (insn & op->mask) == op->match)
1966 {
1967 const char *s;
1968
1969 if (strchr (op->args, 'a') != NULL)
1970 {
1971 if (use_extend)
1972 {
1973 (*info->fprintf_func) (info->stream, "extend 0x%x",
1974 (unsigned int) extend);
1975 info->insn_type = dis_noninsn;
1976 return length - 2;
1977 }
1978
1979 use_extend = FALSE;
1980
1981 memaddr += 2;
1982
1983 status = (*info->read_memory_func) (memaddr, buffer, 2,
1984 info);
1985 if (status == 0)
1986 {
1987 use_extend = TRUE;
1988 if (info->endian == BFD_ENDIAN_BIG)
1989 extend = bfd_getb16 (buffer);
1990 else
1991 extend = bfd_getl16 (buffer);
1992 length += 2;
1993 }
1994 }
1995
1996 (*info->fprintf_func) (info->stream, "%s", op->name);
1997 if (op->args[0] != '\0')
1998 (*info->fprintf_func) (info->stream, "\t");
1999
2000 for (s = op->args; *s != '\0'; s++)
2001 {
2002 if (*s == ','
2003 && s[1] == 'w'
2004 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2005 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2006 {
2007 /* Skip the register and the comma. */
2008 ++s;
2009 continue;
2010 }
2011 if (*s == ','
2012 && s[1] == 'v'
2013 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2014 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2015 {
2016 /* Skip the register and the comma. */
2017 ++s;
2018 continue;
2019 }
2020 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2021 info);
2022 }
2023
2024 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2025 {
2026 info->branch_delay_insns = 1;
2027 if (info->insn_type != dis_jsr)
2028 info->insn_type = dis_branch;
2029 }
2030
2031 return length;
2032 }
2033 }
2034
2035 if (use_extend)
2036 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2037 (*info->fprintf_func) (info->stream, "0x%x", insn);
2038 info->insn_type = dis_noninsn;
2039
2040 return length;
2041}
2042
2043/* In an environment where we do not know the symbol type of the
2044 instruction we are forced to assume that the low order bit of the
2045 instructions' address may mark it as a mips16 instruction. If we
2046 are single stepping, or the pc is within the disassembled function,
2047 this works. Otherwise, we need a clue. Sometimes. */
2048
2049static int
2050_print_insn_mips (bfd_vma memaddr,
2051 struct disassemble_info *info,
2052 enum bfd_endian endianness)
2053{
2054 bfd_byte buffer[INSNLEN];
2055 int status;
2056
2057 set_default_mips_dis_options (info);
2058 parse_mips_dis_options (info->disassembler_options);
2059
2060#if 1
2061 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2062 /* Only a few tools will work this way. */
2063 if (memaddr & 0x01)
2064 return print_insn_mips16 (memaddr, info);
2065#endif
2066
2067#if SYMTAB_AVAILABLE
2068 if (info->mach == bfd_mach_mips16
6ba2a415
RS		 2069 || (info->symbols != NULL
2070 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
30c09090
RS		 2071 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2072 ->internal_elf_sym.st_other)))
47b0e7ad
NC		 2073 return print_insn_mips16 (memaddr, info);
2074#endif
2075
2076 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2077 if (status == 0)
2078 {
2079 unsigned long insn;
2080
2081 if (endianness == BFD_ENDIAN_BIG)
2082 insn = (unsigned long) bfd_getb32 (buffer);
2083 else
2084 insn = (unsigned long) bfd_getl32 (buffer);
2085
2086 return print_insn_mips (memaddr, insn, info);
2087 }
2088 else
2089 {
2090 (*info->memory_error_func) (status, memaddr, info);
2091 return -1;
2092 }
2093}
2094
2095int
2096print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2097{
2098 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2099}
2100
2101int
2102print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2103{
2104 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2105}
2106\f
640c0ccd 2107void
47b0e7ad 2108print_mips_disassembler_options (FILE *stream)
640c0ccd 2109{
4a9a3c54 2110 unsigned int i;
640c0ccd
CD		 2111
2112 fprintf (stream, _("\n\
2113The following MIPS specific disassembler options are supported for use\n\
2114with the -M switch (multiple options should be separated by commas):\n"));
2115
2116 fprintf (stream, _("\n\
2117 gpr-names=ABI Print GPR names according to specified ABI.\n\
2118 Default: based on binary being disassembled.\n"));
2119
2120 fprintf (stream, _("\n\
2121 fpr-names=ABI Print FPR names according to specified ABI.\n\
2122 Default: numeric.\n"));
2123
2124 fprintf (stream, _("\n\
2125 cp0-names=ARCH Print CP0 register names according to\n\
2126 specified architecture.\n\
2127 Default: based on binary being disassembled.\n"));
2128
af7ee8bf
CD		 2129 fprintf (stream, _("\n\
2130 hwr-names=ARCH Print HWR names according to specified \n\
2131 architecture.\n\
2132 Default: based on binary being disassembled.\n"));
2133
640c0ccd
CD		 2134 fprintf (stream, _("\n\
2135 reg-names=ABI Print GPR and FPR names according to\n\
2136 specified ABI.\n"));
2137
2138 fprintf (stream, _("\n\
af7ee8bf 2139 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 2140 specified architecture.\n"));
2141
2142 fprintf (stream, _("\n\
2143 For the options above, the following values are supported for \"ABI\":\n\
2144 "));
4a9a3c54 2145 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
640c0ccd
CD		 2146 fprintf (stream, " %s", mips_abi_choices[i].name);
2147 fprintf (stream, _("\n"));
2148
2149 fprintf (stream, _("\n\
2150 For the options above, The following values are supported for \"ARCH\":\n\
2151 "));
4a9a3c54 2152 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
640c0ccd
CD		 2153 if (*mips_arch_choices[i].name != '\0')
2154 fprintf (stream, " %s", mips_arch_choices[i].name);
2155 fprintf (stream, _("\n"));
2156
2157 fprintf (stream, _("\n"));
2158}
GDB Binutils - Deliverables
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