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2005-01-21 Fred Fish <fnf@specifixinc.com>
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
CommitLineData
252b5132 1/* Print mips instructions for GDB, the GNU debugger, or for objdump.
060d22b0 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
794ac9d0 3 2000, 2001, 2002, 2003
73da6b6b 4 Free Software Foundation, Inc.
252b5132
RH		 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7This file is part of GDB, GAS, and the GNU binutils.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2 of the License, or
12(at your option) any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program; if not, write to the Free Software
21Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
252b5132
RH		 23#include "sysdep.h"
24#include "dis-asm.h"
640c0ccd 25#include "libiberty.h"
252b5132
RH		 26#include "opcode/mips.h"
27#include "opintl.h"
28
29/* FIXME: These are needed to figure out if the code is mips16 or
30 not. The low bit of the address is often a good indicator. No
31 symbol table is available when this code runs out in an embedded
7f6621cd 32 system as when it is used for disassembler support in a monitor. */
252b5132
RH		 33
34#if !defined(EMBEDDED_ENV)
35#define SYMTAB_AVAILABLE 1
36#include "elf-bfd.h"
37#include "elf/mips.h"
38#endif
39
aa5f19f2
NC		 40/* Mips instructions are at maximum this many bytes long. */
41#define INSNLEN 4
42
640c0ccd
CD		 43static void set_default_mips_dis_options
44 PARAMS ((struct disassemble_info *));
45static void parse_mips_dis_option
46 PARAMS ((const char *, unsigned int));
47static void parse_mips_dis_options
48 PARAMS ((const char *));
aa5f19f2
NC		 49static int _print_insn_mips
50 PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
51static int print_insn_mips
52 PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
794ac9d0 53static void print_insn_args
aa5f19f2
NC		 54 PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
55static int print_insn_mips16
56 PARAMS ((bfd_vma, struct disassemble_info *));
7fa108a4
AJ		 57static int is_newabi
58 PARAMS ((Elf_Internal_Ehdr *));
252b5132 59static void print_mips16_insn_arg
b34976b6 60 PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
252b5132 61 struct disassemble_info *));
252b5132 62\f
aa5f19f2 63/* FIXME: These should be shared with gdb somehow. */
252b5132 64
bbcc0807
CD		 65struct mips_cp0sel_name {
66 unsigned int cp0reg;
67 unsigned int sel;
68 const char * const name;
69};
70
252b5132 71/* The mips16 register names. */
7f6621cd 72static const char * const mips16_reg_names[] = {
252b5132
RH		 73 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
74};
fb48caed 75
640c0ccd
CD		 76static const char * const mips_gpr_names_numeric[32] = {
77 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
78 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
79 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
80 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
aa5f19f2
NC		 81};
82
640c0ccd
CD		 83static const char * const mips_gpr_names_oldabi[32] = {
84 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
85 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
86 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
87 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
aa5f19f2
NC		 88};
89
640c0ccd
CD		 90static const char * const mips_gpr_names_newabi[32] = {
91 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
0b14f26e 92 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
640c0ccd
CD		 93 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
94 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
95};
96
97static const char * const mips_fpr_names_numeric[32] = {
98 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
99 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
100 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
101 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
102};
103
104static const char * const mips_fpr_names_32[32] = {
105 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
106 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
107 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
108 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
109};
110
111static const char * const mips_fpr_names_n32[32] = {
112 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
113 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
114 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
115 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
116};
117
118static const char * const mips_fpr_names_64[32] = {
119 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
120 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
121 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
122 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
123};
124
125static const char * const mips_cp0_names_numeric[32] = {
126 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
127 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
128 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
129 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
130};
131
132static const char * const mips_cp0_names_mips3264[32] = {
133 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
134 "c0_context", "c0_pagemask", "c0_wired", "$7",
135 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
136 "c0_status", "c0_cause", "c0_epc", "c0_prid",
137 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
138 "c0_xcontext", "$21", "$22", "c0_debug",
139 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
140 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
141};
142
bbcc0807
CD		 143static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
144 { 16, 1, "c0_config1" },
145 { 16, 2, "c0_config2" },
146 { 16, 3, "c0_config3" },
147 { 18, 1, "c0_watchlo,1" },
148 { 18, 2, "c0_watchlo,2" },
149 { 18, 3, "c0_watchlo,3" },
150 { 18, 4, "c0_watchlo,4" },
151 { 18, 5, "c0_watchlo,5" },
152 { 18, 6, "c0_watchlo,6" },
153 { 18, 7, "c0_watchlo,7" },
154 { 19, 1, "c0_watchhi,1" },
155 { 19, 2, "c0_watchhi,2" },
156 { 19, 3, "c0_watchhi,3" },
157 { 19, 4, "c0_watchhi,4" },
158 { 19, 5, "c0_watchhi,5" },
159 { 19, 6, "c0_watchhi,6" },
160 { 19, 7, "c0_watchhi,7" },
161 { 25, 1, "c0_perfcnt,1" },
162 { 25, 2, "c0_perfcnt,2" },
163 { 25, 3, "c0_perfcnt,3" },
164 { 25, 4, "c0_perfcnt,4" },
165 { 25, 5, "c0_perfcnt,5" },
166 { 25, 6, "c0_perfcnt,6" },
167 { 25, 7, "c0_perfcnt,7" },
168 { 27, 1, "c0_cacheerr,1" },
169 { 27, 2, "c0_cacheerr,2" },
170 { 27, 3, "c0_cacheerr,3" },
171 { 28, 1, "c0_datalo" },
172 { 29, 1, "c0_datahi" }
173};
174
af7ee8bf
CD		 175static const char * const mips_cp0_names_mips3264r2[32] = {
176 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
177 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
178 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
179 "c0_status", "c0_cause", "c0_epc", "c0_prid",
180 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
181 "c0_xcontext", "$21", "$22", "c0_debug",
182 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
183 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
184};
185
bbcc0807
CD		 186static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
187 { 4, 1, "c0_contextconfig" },
188 { 5, 1, "c0_pagegrain" },
189 { 12, 1, "c0_intctl" },
190 { 12, 2, "c0_srsctl" },
191 { 12, 3, "c0_srsmap" },
192 { 15, 1, "c0_ebase" },
193 { 16, 1, "c0_config1" },
194 { 16, 2, "c0_config2" },
195 { 16, 3, "c0_config3" },
196 { 18, 1, "c0_watchlo,1" },
197 { 18, 2, "c0_watchlo,2" },
198 { 18, 3, "c0_watchlo,3" },
199 { 18, 4, "c0_watchlo,4" },
200 { 18, 5, "c0_watchlo,5" },
201 { 18, 6, "c0_watchlo,6" },
202 { 18, 7, "c0_watchlo,7" },
203 { 19, 1, "c0_watchhi,1" },
204 { 19, 2, "c0_watchhi,2" },
205 { 19, 3, "c0_watchhi,3" },
206 { 19, 4, "c0_watchhi,4" },
207 { 19, 5, "c0_watchhi,5" },
208 { 19, 6, "c0_watchhi,6" },
209 { 19, 7, "c0_watchhi,7" },
210 { 23, 1, "c0_tracecontrol" },
211 { 23, 2, "c0_tracecontrol2" },
212 { 23, 3, "c0_usertracedata" },
213 { 23, 4, "c0_tracebpc" },
214 { 25, 1, "c0_perfcnt,1" },
215 { 25, 2, "c0_perfcnt,2" },
216 { 25, 3, "c0_perfcnt,3" },
217 { 25, 4, "c0_perfcnt,4" },
218 { 25, 5, "c0_perfcnt,5" },
219 { 25, 6, "c0_perfcnt,6" },
220 { 25, 7, "c0_perfcnt,7" },
221 { 27, 1, "c0_cacheerr,1" },
222 { 27, 2, "c0_cacheerr,2" },
223 { 27, 3, "c0_cacheerr,3" },
224 { 28, 1, "c0_datalo" },
225 { 28, 2, "c0_taglo1" },
226 { 28, 3, "c0_datalo1" },
227 { 28, 4, "c0_taglo2" },
228 { 28, 5, "c0_datalo2" },
229 { 28, 6, "c0_taglo3" },
230 { 28, 7, "c0_datalo3" },
231 { 29, 1, "c0_datahi" },
232 { 29, 2, "c0_taghi1" },
233 { 29, 3, "c0_datahi1" },
234 { 29, 4, "c0_taghi2" },
235 { 29, 5, "c0_datahi2" },
236 { 29, 6, "c0_taghi3" },
237 { 29, 7, "c0_datahi3" },
238};
239
640c0ccd
CD		 240/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
241static const char * const mips_cp0_names_sb1[32] = {
242 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
243 "c0_context", "c0_pagemask", "c0_wired", "$7",
244 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
245 "c0_status", "c0_cause", "c0_epc", "c0_prid",
246 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
247 "c0_xcontext", "$21", "$22", "c0_debug",
248 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
249 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
250};
251
bbcc0807
CD		 252static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
253 { 16, 1, "c0_config1" },
254 { 18, 1, "c0_watchlo,1" },
255 { 19, 1, "c0_watchhi,1" },
256 { 22, 0, "c0_perftrace" },
257 { 23, 3, "c0_edebug" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 26, 1, "c0_buserr_pa" },
266 { 27, 1, "c0_cacheerr_d" },
267 { 27, 3, "c0_cacheerr_d_pa" },
268 { 28, 1, "c0_datalo_i" },
269 { 28, 2, "c0_taglo_d" },
270 { 28, 3, "c0_datalo_d" },
271 { 29, 1, "c0_datahi_i" },
272 { 29, 2, "c0_taghi_d" },
273 { 29, 3, "c0_datahi_d" },
274};
275
af7ee8bf
CD		 276static const char * const mips_hwr_names_numeric[32] = {
277 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
278 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
279 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
280 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
281};
282
283static const char * const mips_hwr_names_mips3264r2[32] = {
284 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
285 "$4", "$5", "$6", "$7",
286 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
287 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
288 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
289};
290
640c0ccd
CD		 291struct mips_abi_choice {
292 const char *name;
293 const char * const *gpr_names;
294 const char * const *fpr_names;
295};
296
297struct mips_abi_choice mips_abi_choices[] = {
298 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
299 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
300 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
301 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
302};
303
304struct mips_arch_choice {
305 const char *name;
306 int bfd_mach_valid;
307 unsigned long bfd_mach;
308 int processor;
309 int isa;
310 const char * const *cp0_names;
bbcc0807
CD		 311 const struct mips_cp0sel_name *cp0sel_names;
312 unsigned int cp0sel_names_len;
af7ee8bf 313 const char * const *hwr_names;
640c0ccd
CD		 314};
315
bbcc0807 316const struct mips_arch_choice mips_arch_choices[] = {
640c0ccd 317 { "numeric", 0, 0, 0, 0,
bbcc0807
CD		 318 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
319
640c0ccd 320 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
bbcc0807 321 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 322 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
bbcc0807 323 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 324 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
bbcc0807 325 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 326 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
bbcc0807 327 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 328 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
bbcc0807 329 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 330 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
bbcc0807 331 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 332 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
bbcc0807 333 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 334 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
bbcc0807 335 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 336 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
bbcc0807 337 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 338 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
bbcc0807 339 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 340 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
bbcc0807 341 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 342 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
bbcc0807 343 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 344 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
bbcc0807 345 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 346 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
bbcc0807 347 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 348 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
bbcc0807 349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
5a7ea749
RS		 350 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
352 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 354 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
bbcc0807 355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 356 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
bbcc0807 357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 358 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
bbcc0807 359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd 360 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
bbcc0807
CD		 361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362
640c0ccd
CD		 363 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
364 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
365 _MIPS32 Architecture For Programmers Volume I: Introduction to the
366 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
367 page 1. */
368 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
369 ISA_MIPS32 | INSN_MIPS16,
bbcc0807
CD		 370 mips_cp0_names_mips3264,
371 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
372 mips_hwr_names_numeric },
373
af7ee8bf
CD		 374 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
375 ISA_MIPS32R2 | INSN_MIPS16,
bbcc0807
CD		 376 mips_cp0_names_mips3264r2,
377 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
378 mips_hwr_names_mips3264r2 },
379
640c0ccd
CD		 380 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
381 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
382 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
bbcc0807
CD		 383 mips_cp0_names_mips3264,
384 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
385 mips_hwr_names_numeric },
386
5f74bc13
CD		 387 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
388 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
389 mips_cp0_names_mips3264r2,
390 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
391 mips_hwr_names_mips3264r2 },
392
640c0ccd
CD		 393 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
394 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
bbcc0807
CD		 395 mips_cp0_names_sb1,
396 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
397 mips_hwr_names_numeric },
640c0ccd
CD		 398
399 /* This entry, mips16, is here only for ISA/processor selection; do
400 not print its name. */
401 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
bbcc0807 402 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
640c0ccd
CD		 403};
404
405/* ISA and processor type to disassemble for, and register names to use.
406 set_default_mips_dis_options and parse_mips_dis_options fill in these
407 values. */
408static int mips_processor;
409static int mips_isa;
410static const char * const *mips_gpr_names;
411static const char * const *mips_fpr_names;
412static const char * const *mips_cp0_names;
bbcc0807
CD		 413static const struct mips_cp0sel_name *mips_cp0sel_names;
414static int mips_cp0sel_names_len;
af7ee8bf 415static const char * const *mips_hwr_names;
640c0ccd 416
986e18a5
FF		 417/* Other options */
418static int no_aliases; /* If set disassemble as most general inst. */
419
640c0ccd
CD		 420static const struct mips_abi_choice *choose_abi_by_name
421 PARAMS ((const char *, unsigned int));
422static const struct mips_arch_choice *choose_arch_by_name
423 PARAMS ((const char *, unsigned int));
424static const struct mips_arch_choice *choose_arch_by_number
425 PARAMS ((unsigned long));
bbcc0807
CD		 426static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
427 PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
428 unsigned int));
640c0ccd
CD		 429\f
430static const struct mips_abi_choice *
431choose_abi_by_name (name, namelen)
432 const char *name;
433 unsigned int namelen;
434{
435 const struct mips_abi_choice *c;
436 unsigned int i;
437
438 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
439 {
440 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
441 && strlen (mips_abi_choices[i].name) == namelen)
442 c = &mips_abi_choices[i];
443 }
444 return c;
445}
446
447static const struct mips_arch_choice *
448choose_arch_by_name (name, namelen)
449 const char *name;
450 unsigned int namelen;
451{
452 const struct mips_arch_choice *c = NULL;
453 unsigned int i;
454
455 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
456 {
457 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
458 && strlen (mips_arch_choices[i].name) == namelen)
459 c = &mips_arch_choices[i];
460 }
461 return c;
462}
463
464static const struct mips_arch_choice *
465choose_arch_by_number (mach)
466 unsigned long mach;
467{
468 static unsigned long hint_bfd_mach;
469 static const struct mips_arch_choice *hint_arch_choice;
470 const struct mips_arch_choice *c;
471 unsigned int i;
472
473 /* We optimize this because even if the user specifies no
474 flags, this will be done for every instruction! */
475 if (hint_bfd_mach == mach
476 && hint_arch_choice != NULL
477 && hint_arch_choice->bfd_mach == hint_bfd_mach)
478 return hint_arch_choice;
479
480 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
481 {
482 if (mips_arch_choices[i].bfd_mach_valid
483 && mips_arch_choices[i].bfd_mach == mach)
484 {
485 c = &mips_arch_choices[i];
486 hint_bfd_mach = mach;
487 hint_arch_choice = c;
488 }
489 }
490 return c;
491}
492
493void
494set_default_mips_dis_options (info)
495 struct disassemble_info *info;
496{
497 const struct mips_arch_choice *chosen_arch;
498
499 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
af7ee8bf 500 and numeric FPR, CP0 register, and HWR names. */
640c0ccd
CD		 501 mips_isa = ISA_MIPS3;
502 mips_processor = CPU_R3000;
503 mips_gpr_names = mips_gpr_names_oldabi;
504 mips_fpr_names = mips_fpr_names_numeric;
505 mips_cp0_names = mips_cp0_names_numeric;
bbcc0807
CD		 506 mips_cp0sel_names = NULL;
507 mips_cp0sel_names_len = 0;
af7ee8bf 508 mips_hwr_names = mips_hwr_names_numeric;
986e18a5 509 no_aliases = 0;
640c0ccd
CD		 510
511 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
fec06546 512 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
640c0ccd
CD		 513 {
514 Elf_Internal_Ehdr *header;
515
fec06546 516 header = elf_elfheader (info->section->owner);
640c0ccd
CD		 517 if (is_newabi (header))
518 mips_gpr_names = mips_gpr_names_newabi;
519 }
520
521 /* Set ISA, architecture, and cp0 register names as best we can. */
522#if ! SYMTAB_AVAILABLE
523 /* This is running out on a target machine, not in a host tool.
524 FIXME: Where does mips_target_info come from? */
525 target_processor = mips_target_info.processor;
526 mips_isa = mips_target_info.isa;
527#else
528 chosen_arch = choose_arch_by_number (info->mach);
529 if (chosen_arch != NULL)
530 {
531 mips_processor = chosen_arch->processor;
532 mips_isa = chosen_arch->isa;
bbcc0807
CD		 533 mips_cp0_names = chosen_arch->cp0_names;
534 mips_cp0sel_names = chosen_arch->cp0sel_names;
535 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
536 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 537 }
538#endif
539}
540
541void
542parse_mips_dis_option (option, len)
543 const char *option;
544 unsigned int len;
545{
546 unsigned int i, optionlen, vallen;
547 const char *val;
548 const struct mips_abi_choice *chosen_abi;
549 const struct mips_arch_choice *chosen_arch;
550
986e18a5
FF		 551 /* Try to match options that are simple flags */
552 if (strncmp (option, "no-aliases", 10) == 0)
553 {
554 no_aliases = 1;
555 return;
556 }
557
640c0ccd
CD		 558 /* Look for the = that delimits the end of the option name. */
559 for (i = 0; i < len; i++)
560 {
561 if (option[i] == '=')
562 break;
563 }
564 if (i == 0) /* Invalid option: no name before '='. */
565 return;
566 if (i == len) /* Invalid option: no '='. */
567 return;
568 if (i == (len - 1)) /* Invalid option: no value after '='. */
569 return;
570
571 optionlen = i;
572 val = option + (optionlen + 1);
573 vallen = len - (optionlen + 1);
574
575 if (strncmp("gpr-names", option, optionlen) == 0
576 && strlen("gpr-names") == optionlen)
577 {
578 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 579 if (chosen_abi != NULL)
640c0ccd
CD		 580 mips_gpr_names = chosen_abi->gpr_names;
581 return;
582 }
583
584 if (strncmp("fpr-names", option, optionlen) == 0
585 && strlen("fpr-names") == optionlen)
586 {
587 chosen_abi = choose_abi_by_name (val, vallen);
bbcc0807 588 if (chosen_abi != NULL)
640c0ccd
CD		 589 mips_fpr_names = chosen_abi->fpr_names;
590 return;
591 }
592
593 if (strncmp("cp0-names", option, optionlen) == 0
594 && strlen("cp0-names") == optionlen)
595 {
596 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807
CD		 597 if (chosen_arch != NULL)
598 {
599 mips_cp0_names = chosen_arch->cp0_names;
600 mips_cp0sel_names = chosen_arch->cp0sel_names;
601 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
602 }
640c0ccd
CD		 603 return;
604 }
605
af7ee8bf
CD		 606 if (strncmp("hwr-names", option, optionlen) == 0
607 && strlen("hwr-names") == optionlen)
608 {
609 chosen_arch = choose_arch_by_name (val, vallen);
bbcc0807 610 if (chosen_arch != NULL)
af7ee8bf
CD		 611 mips_hwr_names = chosen_arch->hwr_names;
612 return;
613 }
614
640c0ccd
CD		 615 if (strncmp("reg-names", option, optionlen) == 0
616 && strlen("reg-names") == optionlen)
617 {
618 /* We check both ABI and ARCH here unconditionally, so
619 that "numeric" will do the desirable thing: select
620 numeric register names for all registers. Other than
621 that, a given name probably won't match both. */
622 chosen_abi = choose_abi_by_name (val, vallen);
623 if (chosen_abi != NULL)
624 {
bbcc0807
CD		 625 mips_gpr_names = chosen_abi->gpr_names;
626 mips_fpr_names = chosen_abi->fpr_names;
640c0ccd
CD		 627 }
628 chosen_arch = choose_arch_by_name (val, vallen);
629 if (chosen_arch != NULL)
630 {
bbcc0807
CD		 631 mips_cp0_names = chosen_arch->cp0_names;
632 mips_cp0sel_names = chosen_arch->cp0sel_names;
633 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
634 mips_hwr_names = chosen_arch->hwr_names;
640c0ccd
CD		 635 }
636 return;
637 }
638
639 /* Invalid option. */
640}
641
642void
643parse_mips_dis_options (options)
644 const char *options;
645{
646 const char *option_end;
647
648 if (options == NULL)
649 return;
650
651 while (*options != '\0')
652 {
653 /* Skip empty options. */
654 if (*options == ',')
655 {
656 options++;
657 continue;
658 }
659
660 /* We know that *options is neither NUL or a comma. */
661 option_end = options + 1;
662 while (*option_end != ',' && *option_end != '\0')
663 option_end++;
664
665 parse_mips_dis_option (options, option_end - options);
666
667 /* Go on to the next one. If option_end points to a comma, it
668 will be skipped above. */
669 options = option_end;
670 }
671}
672
bbcc0807
CD		 673static const struct mips_cp0sel_name *
674lookup_mips_cp0sel_name(names, len, cp0reg, sel)
675 const struct mips_cp0sel_name *names;
676 unsigned int len, cp0reg, sel;
677{
678 unsigned int i;
679
680 for (i = 0; i < len; i++)
681 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
682 return &names[i];
683 return NULL;
684}
252b5132 685\f
7f6621cd 686/* Print insn arguments for 32/64-bit code. */
aa5f19f2 687
794ac9d0
CD		 688static void
689print_insn_args (d, l, pc, info)
252b5132
RH		 690 const char *d;
691 register unsigned long int l;
692 bfd_vma pc;
693 struct disassemble_info *info;
694{
794ac9d0 695 int op, delta;
440cc0bc
CD		 696 unsigned int lsb, msb, msbd;
697
698 lsb = 0;
252b5132 699
794ac9d0 700 for (; *d != '\0'; d++)
252b5132 701 {
af7ee8bf
CD		 702 switch (*d)
703 {
794ac9d0
CD		 704 case ',':
705 case '(':
706 case ')':
707 case '[':
708 case ']':
709 (*info->fprintf_func) (info->stream, "%c", *d);
710 break;
711
712 case '+':
713 /* Extension character; switch for second char. */
714 d++;
715 switch (*d)
716 {
717 case '\0':
718 /* xgettext:c-format */
719 (*info->fprintf_func) (info->stream,
720 _("# internal error, incomplete extension sequence (+)"));
721 return;
722
723 case 'A':
440cc0bc
CD		 724 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
725 (*info->fprintf_func) (info->stream, "0x%x", lsb);
794ac9d0
CD		 726 break;
727
728 case 'B':
440cc0bc
CD		 729 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
730 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
794ac9d0
CD		 731 break;
732
733 case 'C':
5f74bc13 734 case 'H':
440cc0bc
CD		 735 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
736 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
794ac9d0
CD		 737 break;
738
739 case 'D':
740 {
741 const struct mips_cp0sel_name *n;
742 unsigned int cp0reg, sel;
743
744 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
745 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
746
747 /* CP0 register including 'sel' code for mtcN (et al.), to be
748 printed textually if known. If not known, print both
749 CP0 register name and sel numerically since CP0 register
750 with sel 0 may have a name unrelated to register being
751 printed. */
752 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
753 mips_cp0sel_names_len, cp0reg, sel);
754 if (n != NULL)
755 (*info->fprintf_func) (info->stream, "%s", n->name);
756 else
757 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
758 break;
759 }
760
5f74bc13
CD		 761 case 'E':
762 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
763 (*info->fprintf_func) (info->stream, "0x%x", lsb);
764 break;
765
766 case 'F':
767 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
768 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
769 break;
770
771 case 'G':
772 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
773 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
774 break;
775
794ac9d0
CD		 776 default:
777 /* xgettext:c-format */
778 (*info->fprintf_func) (info->stream,
779 _("# internal error, undefined extension sequence (+%c)"),
780 *d);
781 return;
782 }
783 break;
784
785 case 's':
786 case 'b':
787 case 'r':
788 case 'v':
789 (*info->fprintf_func) (info->stream, "%s",
790 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
791 break;
792
793 case 't':
794 case 'w':
795 (*info->fprintf_func) (info->stream, "%s",
796 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
797 break;
798
799 case 'i':
800 case 'u':
801 (*info->fprintf_func) (info->stream, "0x%x",
802 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
803 break;
804
805 case 'j': /* Same as i, but sign-extended. */
806 case 'o':
807 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
808 if (delta & 0x8000)
809 delta |= ~0xffff;
810 (*info->fprintf_func) (info->stream, "%d",
811 delta);
812 break;
813
814 case 'h':
815 (*info->fprintf_func) (info->stream, "0x%x",
816 (unsigned int) ((l >> OP_SH_PREFX)
817 & OP_MASK_PREFX));
818 break;
819
820 case 'k':
821 (*info->fprintf_func) (info->stream, "0x%x",
822 (unsigned int) ((l >> OP_SH_CACHE)
823 & OP_MASK_CACHE));
824 break;
825
826 case 'a':
827 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
828 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
829 (*info->print_address_func) (info->target, info);
830 break;
831
832 case 'p':
833 /* Sign extend the displacement. */
834 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
835 if (delta & 0x8000)
836 delta |= ~0xffff;
837 info->target = (delta << 2) + pc + INSNLEN;
838 (*info->print_address_func) (info->target, info);
839 break;
840
841 case 'd':
842 (*info->fprintf_func) (info->stream, "%s",
843 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
844 break;
845
846 case 'U':
847 {
848 /* First check for both rd and rt being equal. */
849 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
850 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
851 (*info->fprintf_func) (info->stream, "%s",
852 mips_gpr_names[reg]);
853 else
854 {
855 /* If one is zero use the other. */
856 if (reg == 0)
857 (*info->fprintf_func) (info->stream, "%s",
858 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
859 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
860 (*info->fprintf_func) (info->stream, "%s",
861 mips_gpr_names[reg]);
862 else /* Bogus, result depends on processor. */
863 (*info->fprintf_func) (info->stream, "%s or %s",
864 mips_gpr_names[reg],
865 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
866 }
867 }
868 break;
869
870 case 'z':
871 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
872 break;
873
874 case '<':
af7ee8bf
CD		 875 (*info->fprintf_func) (info->stream, "0x%x",
876 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
877 break;
794ac9d0
CD		 878
879 case 'c':
af7ee8bf 880 (*info->fprintf_func) (info->stream, "0x%x",
794ac9d0
CD		 881 (l >> OP_SH_CODE) & OP_MASK_CODE);
882 break;
883
884 case 'q':
885 (*info->fprintf_func) (info->stream, "0x%x",
886 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
af7ee8bf
CD		 887 break;
888
889 case 'C':
890 (*info->fprintf_func) (info->stream, "0x%x",
794ac9d0
CD		 891 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
892 break;
893
894 case 'B':
895 (*info->fprintf_func) (info->stream, "0x%x",
896 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
897 break;
898
899 case 'J':
900 (*info->fprintf_func) (info->stream, "0x%x",
901 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
902 break;
903
904 case 'S':
905 case 'V':
906 (*info->fprintf_func) (info->stream, "%s",
907 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
908 break;
909
910 case 'T':
911 case 'W':
912 (*info->fprintf_func) (info->stream, "%s",
913 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
af7ee8bf
CD		 914 break;
915
bbcc0807 916 case 'D':
794ac9d0
CD		 917 (*info->fprintf_func) (info->stream, "%s",
918 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
919 break;
920
921 case 'R':
922 (*info->fprintf_func) (info->stream, "%s",
923 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
924 break;
925
926 case 'E':
927 /* Coprocessor register for lwcN instructions, et al.
928
929 Note that there is no load/store cp0 instructions, and
930 that FPU (cp1) instructions disassemble this field using
931 'T' format. Therefore, until we gain understanding of
932 cp2 register names, we can simply print the register
933 numbers. */
934 (*info->fprintf_func) (info->stream, "$%d",
935 (l >> OP_SH_RT) & OP_MASK_RT);
936 break;
937
938 case 'G':
939 /* Coprocessor register for mtcN instructions, et al. Note
940 that FPU (cp1) instructions disassemble this field using
941 'S' format. Therefore, we only need to worry about cp0,
942 cp2, and cp3. */
943 op = (l >> OP_SH_OP) & OP_MASK_OP;
944 if (op == OP_OP_COP0)
945 (*info->fprintf_func) (info->stream, "%s",
946 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
947 else
948 (*info->fprintf_func) (info->stream, "$%d",
949 (l >> OP_SH_RD) & OP_MASK_RD);
950 break;
951
952 case 'K':
953 (*info->fprintf_func) (info->stream, "%s",
954 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
955 break;
956
957 case 'N':
958 (*info->fprintf_func) (info->stream, "$fcc%d",
959 (l >> OP_SH_BCC) & OP_MASK_BCC);
960 break;
961
962 case 'M':
963 (*info->fprintf_func) (info->stream, "$fcc%d",
964 (l >> OP_SH_CCC) & OP_MASK_CCC);
965 break;
966
967 case 'P':
968 (*info->fprintf_func) (info->stream, "%d",
969 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
970 break;
971
972 case 'e':
973 (*info->fprintf_func) (info->stream, "%d",
974 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
975 break;
976
977 case '%':
978 (*info->fprintf_func) (info->stream, "%d",
979 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
980 break;
981
982 case 'H':
983 (*info->fprintf_func) (info->stream, "%d",
984 (l >> OP_SH_SEL) & OP_MASK_SEL);
985 break;
986
987 case 'O':
988 (*info->fprintf_func) (info->stream, "%d",
989 (l >> OP_SH_ALN) & OP_MASK_ALN);
990 break;
991
992 case 'Q':
bbcc0807 993 {
794ac9d0
CD		 994 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
995 if ((vsel & 0x10) == 0)
996 {
997 int fmt;
998 vsel &= 0x0f;
999 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1000 if ((vsel & 1) == 0)
1001 break;
1002 (*info->fprintf_func) (info->stream, "$v%d[%d]",
1003 (l >> OP_SH_FT) & OP_MASK_FT,
1004 vsel >> 1);
1005 }
1006 else if ((vsel & 0x08) == 0)
1007 {
1008 (*info->fprintf_func) (info->stream, "$v%d",
1009 (l >> OP_SH_FT) & OP_MASK_FT);
1010 }
bbcc0807 1011 else
794ac9d0
CD		 1012 {
1013 (*info->fprintf_func) (info->stream, "0x%x",
1014 (l >> OP_SH_FT) & OP_MASK_FT);
1015 }
bbcc0807 1016 }
794ac9d0
CD		 1017 break;
1018
1019 case 'X':
1020 (*info->fprintf_func) (info->stream, "$v%d",
1021 (l >> OP_SH_FD) & OP_MASK_FD);
1022 break;
1023
1024 case 'Y':
1025 (*info->fprintf_func) (info->stream, "$v%d",
1026 (l >> OP_SH_FS) & OP_MASK_FS);
1027 break;
1028
1029 case 'Z':
1030 (*info->fprintf_func) (info->stream, "$v%d",
1031 (l >> OP_SH_FT) & OP_MASK_FT);
1032 break;
bbcc0807 1033
af7ee8bf
CD		 1034 default:
1035 /* xgettext:c-format */
1036 (*info->fprintf_func) (info->stream,
794ac9d0 1037 _("# internal error, undefined modifier(%c)"),
af7ee8bf 1038 *d);
794ac9d0 1039 return;
af7ee8bf 1040 }
252b5132
RH		 1041 }
1042}
1043\f
21d34b1c 1044/* Check if the object uses NewABI conventions. */
aa5f19f2
NC		 1045
1046static int
7f6621cd 1047is_newabi (header)
21d34b1c 1048 Elf_Internal_Ehdr *header;
aa5f19f2 1049{
4c563ebf
CD		 1050 /* There are no old-style ABIs which use 64-bit ELF. */
1051 if (header->e_ident[EI_CLASS] == ELFCLASS64)
1052 return 1;
1053
563773fe
TS		 1054 /* If a 32-bit ELF file, n32 is a new-style ABI. */
1055 if ((header->e_flags & EF_MIPS_ABI2) != 0)
21d34b1c 1056 return 1;
252b5132 1057
21d34b1c 1058 return 0;
aa5f19f2
NC		 1059}
1060\f
252b5132
RH		 1061/* Print the mips instruction at address MEMADDR in debugged memory,
1062 on using INFO. Returns length of the instruction, in bytes, which is
aa5f19f2 1063 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
252b5132
RH		 1064 this is little-endian code. */
1065
1066static int
aa5f19f2 1067print_insn_mips (memaddr, word, info)
252b5132
RH		 1068 bfd_vma memaddr;
1069 unsigned long int word;
1070 struct disassemble_info *info;
1071{
1072 register const struct mips_opcode *op;
b34976b6 1073 static bfd_boolean init = 0;
252b5132
RH		 1074 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1075
1076 /* Build a hash table to shorten the search time. */
1077 if (! init)
1078 {
1079 unsigned int i;
1080
1081 for (i = 0; i <= OP_MASK_OP; i++)
1082 {
1083 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1084 {
986e18a5
FF		 1085 if (op->pinfo == INSN_MACRO
1086 || (no_aliases && (op->pinfo2 & INSN_ALIAS)))
252b5132
RH		 1087 continue;
1088 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1089 {
1090 mips_hash[i] = op;
1091 break;
1092 }
1093 }
7f6621cd 1094 }
252b5132
RH		 1095
1096 init = 1;
1097 }
1098
aa5f19f2 1099 info->bytes_per_chunk = INSNLEN;
252b5132 1100 info->display_endian = info->endian;
9bb28706
CD		 1101 info->insn_info_valid = 1;
1102 info->branch_delay_insns = 0;
def7143b 1103 info->data_size = 0;
9bb28706
CD		 1104 info->insn_type = dis_nonbranch;
1105 info->target = 0;
1106 info->target2 = 0;
252b5132
RH		 1107
1108 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1109 if (op != NULL)
1110 {
1111 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1112 {
986e18a5
FF		 1113 if (op->pinfo != INSN_MACRO
1114 && !(no_aliases && (op->pinfo2 & INSN_ALIAS))
1115 && (word & op->mask) == op->match)
252b5132
RH		 1116 {
1117 register const char *d;
2bd7f1f3 1118
3396de36 1119 /* We always allow to disassemble the jalx instruction. */
640c0ccd 1120 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3396de36 1121 && strcmp (op->name, "jalx"))
252b5132
RH		 1122 continue;
1123
9bb28706
CD		 1124 /* Figure out instruction type and branch delay information. */
1125 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1126 {
1127 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1128 info->insn_type = dis_jsr;
1129 else
1130 info->insn_type = dis_branch;
1131 info->branch_delay_insns = 1;
1132 }
1133 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1134 | INSN_COND_BRANCH_LIKELY)) != 0)
1135 {
1136 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1137 info->insn_type = dis_condjsr;
1138 else
1139 info->insn_type = dis_condbranch;
1140 info->branch_delay_insns = 1;
1141 }
1142 else if ((op->pinfo & (INSN_STORE_MEMORY
1143 | INSN_LOAD_MEMORY_DELAY)) != 0)
1144 info->insn_type = dis_dref;
1145
252b5132
RH		 1146 (*info->fprintf_func) (info->stream, "%s", op->name);
1147
1148 d = op->args;
1149 if (d != NULL && *d != '\0')
1150 {
7f6621cd 1151 (*info->fprintf_func) (info->stream, "\t");
794ac9d0 1152 print_insn_args (d, word, memaddr, info);
252b5132
RH		 1153 }
1154
aa5f19f2 1155 return INSNLEN;
252b5132
RH		 1156 }
1157 }
1158 }
1159
1160 /* Handle undefined instructions. */
9bb28706 1161 info->insn_type = dis_noninsn;
252b5132 1162 (*info->fprintf_func) (info->stream, "0x%x", word);
aa5f19f2 1163 return INSNLEN;
252b5132 1164}
aa5f19f2 1165\f
252b5132
RH		 1166/* In an environment where we do not know the symbol type of the
1167 instruction we are forced to assume that the low order bit of the
1168 instructions' address may mark it as a mips16 instruction. If we
1169 are single stepping, or the pc is within the disassembled function,
1170 this works. Otherwise, we need a clue. Sometimes. */
1171
aa5f19f2
NC		 1172static int
1173_print_insn_mips (memaddr, info, endianness)
252b5132
RH		 1174 bfd_vma memaddr;
1175 struct disassemble_info *info;
aa5f19f2 1176 enum bfd_endian endianness;
252b5132 1177{
aa5f19f2 1178 bfd_byte buffer[INSNLEN];
252b5132
RH		 1179 int status;
1180
640c0ccd
CD		 1181 set_default_mips_dis_options (info);
1182 parse_mips_dis_options (info->disassembler_options);
1183
252b5132
RH		 1184#if 1
1185 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1186 /* Only a few tools will work this way. */
1187 if (memaddr & 0x01)
1188 return print_insn_mips16 (memaddr, info);
e93d7199 1189#endif
252b5132
RH		 1190
1191#if SYMTAB_AVAILABLE
53f32ea5 1192 if (info->mach == bfd_mach_mips16
252b5132
RH		 1193 || (info->flavour == bfd_target_elf_flavour
1194 && info->symbols != NULL
1195 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1196 == STO_MIPS16)))
1197 return print_insn_mips16 (memaddr, info);
e93d7199 1198#endif
252b5132 1199
aa5f19f2 1200 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
252b5132 1201 if (status == 0)
aa5f19f2
NC		 1202 {
1203 unsigned long insn;
1204
1205 if (endianness == BFD_ENDIAN_BIG)
7f6621cd 1206 insn = (unsigned long) bfd_getb32 (buffer);
aa5f19f2
NC		 1207 else
1208 insn = (unsigned long) bfd_getl32 (buffer);
1209
1210 return print_insn_mips (memaddr, insn, info);
1211 }
252b5132
RH		 1212 else
1213 {
1214 (*info->memory_error_func) (status, memaddr, info);
1215 return -1;
1216 }
1217}
1218
1219int
aa5f19f2 1220print_insn_big_mips (memaddr, info)
252b5132
RH		 1221 bfd_vma memaddr;
1222 struct disassemble_info *info;
1223{
aa5f19f2
NC		 1224 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
1225}
252b5132 1226
aa5f19f2
NC		 1227int
1228print_insn_little_mips (memaddr, info)
1229 bfd_vma memaddr;
1230 struct disassemble_info *info;
1231{
1232 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
252b5132
RH		 1233}
1234\f
1235/* Disassemble mips16 instructions. */
1236
1237static int
1238print_insn_mips16 (memaddr, info)
1239 bfd_vma memaddr;
1240 struct disassemble_info *info;
1241{
1242 int status;
1243 bfd_byte buffer[2];
1244 int length;
1245 int insn;
b34976b6 1246 bfd_boolean use_extend;
252b5132
RH		 1247 int extend = 0;
1248 const struct mips_opcode *op, *opend;
1249
1250 info->bytes_per_chunk = 2;
1251 info->display_endian = info->endian;
252b5132
RH		 1252 info->insn_info_valid = 1;
1253 info->branch_delay_insns = 0;
1254 info->data_size = 0;
1255 info->insn_type = dis_nonbranch;
1256 info->target = 0;
1257 info->target2 = 0;
1258
1259 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1260 if (status != 0)
1261 {
1262 (*info->memory_error_func) (status, memaddr, info);
1263 return -1;
1264 }
1265
1266 length = 2;
1267
1268 if (info->endian == BFD_ENDIAN_BIG)
1269 insn = bfd_getb16 (buffer);
1270 else
1271 insn = bfd_getl16 (buffer);
1272
1273 /* Handle the extend opcode specially. */
b34976b6 1274 use_extend = FALSE;
252b5132
RH		 1275 if ((insn & 0xf800) == 0xf000)
1276 {
b34976b6 1277 use_extend = TRUE;
252b5132
RH		 1278 extend = insn & 0x7ff;
1279
1280 memaddr += 2;
1281
1282 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1283 if (status != 0)
1284 {
1285 (*info->fprintf_func) (info->stream, "extend 0x%x",
1286 (unsigned int) extend);
1287 (*info->memory_error_func) (status, memaddr, info);
1288 return -1;
1289 }
1290
1291 if (info->endian == BFD_ENDIAN_BIG)
1292 insn = bfd_getb16 (buffer);
1293 else
1294 insn = bfd_getl16 (buffer);
1295
1296 /* Check for an extend opcode followed by an extend opcode. */
1297 if ((insn & 0xf800) == 0xf000)
1298 {
1299 (*info->fprintf_func) (info->stream, "extend 0x%x",
1300 (unsigned int) extend);
1301 info->insn_type = dis_noninsn;
1302 return length;
1303 }
1304
1305 length += 2;
1306 }
1307
1308 /* FIXME: Should probably use a hash table on the major opcode here. */
1309
1310 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1311 for (op = mips16_opcodes; op < opend; op++)
1312 {
986e18a5
FF		 1313 if (op->pinfo != INSN_MACRO
1314 && !(no_aliases && (op->pinfo2 & INSN_ALIAS))
1315 && (insn & op->mask) == op->match)
252b5132
RH		 1316 {
1317 const char *s;
1318
1319 if (strchr (op->args, 'a') != NULL)
1320 {
1321 if (use_extend)
1322 {
1323 (*info->fprintf_func) (info->stream, "extend 0x%x",
1324 (unsigned int) extend);
1325 info->insn_type = dis_noninsn;
1326 return length - 2;
1327 }
1328
b34976b6 1329 use_extend = FALSE;
252b5132
RH		 1330
1331 memaddr += 2;
1332
1333 status = (*info->read_memory_func) (memaddr, buffer, 2,
1334 info);
1335 if (status == 0)
1336 {
b34976b6 1337 use_extend = TRUE;
252b5132
RH		 1338 if (info->endian == BFD_ENDIAN_BIG)
1339 extend = bfd_getb16 (buffer);
1340 else
1341 extend = bfd_getl16 (buffer);
1342 length += 2;
1343 }
1344 }
1345
1346 (*info->fprintf_func) (info->stream, "%s", op->name);
1347 if (op->args[0] != '\0')
1348 (*info->fprintf_func) (info->stream, "\t");
1349
1350 for (s = op->args; *s != '\0'; s++)
1351 {
1352 if (*s == ','
1353 && s[1] == 'w'
1354 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1355 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1356 {
1357 /* Skip the register and the comma. */
1358 ++s;
1359 continue;
1360 }
1361 if (*s == ','
1362 && s[1] == 'v'
1363 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1364 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1365 {
1366 /* Skip the register and the comma. */
1367 ++s;
1368 continue;
1369 }
1370 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1371 info);
1372 }
1373
1374 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1375 {
1376 info->branch_delay_insns = 1;
1377 if (info->insn_type != dis_jsr)
1378 info->insn_type = dis_branch;
1379 }
1380
1381 return length;
1382 }
1383 }
1384
1385 if (use_extend)
1386 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1387 (*info->fprintf_func) (info->stream, "0x%x", insn);
1388 info->insn_type = dis_noninsn;
1389
1390 return length;
1391}
1392
1393/* Disassemble an operand for a mips16 instruction. */
1394
1395static void
1396print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
aa5f19f2 1397 char type;
252b5132
RH		 1398 const struct mips_opcode *op;
1399 int l;
b34976b6 1400 bfd_boolean use_extend;
252b5132
RH		 1401 int extend;
1402 bfd_vma memaddr;
1403 struct disassemble_info *info;
1404{
1405 switch (type)
1406 {
1407 case ',':
1408 case '(':
1409 case ')':
1410 (*info->fprintf_func) (info->stream, "%c", type);
1411 break;
1412
1413 case 'y':
1414 case 'w':
aa5f19f2 1415 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1416 mips16_reg_names[((l >> MIPS16OP_SH_RY)
1417 & MIPS16OP_MASK_RY)]);
1418 break;
1419
1420 case 'x':
1421 case 'v':
aa5f19f2 1422 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1423 mips16_reg_names[((l >> MIPS16OP_SH_RX)
1424 & MIPS16OP_MASK_RX)]);
1425 break;
1426
1427 case 'z':
aa5f19f2 1428 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1429 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
1430 & MIPS16OP_MASK_RZ)]);
1431 break;
1432
1433 case 'Z':
aa5f19f2 1434 (*info->fprintf_func) (info->stream, "%s",
252b5132
RH		 1435 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
1436 & MIPS16OP_MASK_MOVE32Z)]);
1437 break;
1438
1439 case '0':
640c0ccd 1440 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
252b5132
RH		 1441 break;
1442
1443 case 'S':
640c0ccd 1444 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
252b5132
RH		 1445 break;
1446
1447 case 'P':
1448 (*info->fprintf_func) (info->stream, "$pc");
1449 break;
1450
1451 case 'R':
640c0ccd 1452 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
252b5132
RH		 1453 break;
1454
1455 case 'X':
aa5f19f2 1456 (*info->fprintf_func) (info->stream, "%s",
640c0ccd
CD		 1457 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1458 & MIPS16OP_MASK_REGR32)]);
252b5132
RH		 1459 break;
1460
1461 case 'Y':
aa5f19f2 1462 (*info->fprintf_func) (info->stream, "%s",
640c0ccd 1463 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
252b5132
RH		 1464 break;
1465
1466 case '<':
1467 case '>':
1468 case '[':
1469 case ']':
1470 case '4':
1471 case '5':
1472 case 'H':
1473 case 'W':
1474 case 'D':
1475 case 'j':
1476 case '6':
1477 case '8':
1478 case 'V':
1479 case 'C':
1480 case 'U':
1481 case 'k':
1482 case 'K':
1483 case 'p':
1484 case 'q':
1485 case 'A':
1486 case 'B':
1487 case 'E':
1488 {
1489 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1490
1491 shift = 0;
1492 signedp = 0;
1493 extbits = 16;
1494 pcrel = 0;
1495 extu = 0;
1496 branch = 0;
1497 switch (type)
1498 {
1499 case '<':
1500 nbits = 3;
1501 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1502 extbits = 5;
1503 extu = 1;
1504 break;
1505 case '>':
1506 nbits = 3;
1507 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1508 extbits = 5;
1509 extu = 1;
1510 break;
1511 case '[':
1512 nbits = 3;
1513 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1514 extbits = 6;
1515 extu = 1;
1516 break;
1517 case ']':
1518 nbits = 3;
1519 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1520 extbits = 6;
1521 extu = 1;
1522 break;
1523 case '4':
1524 nbits = 4;
1525 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1526 signedp = 1;
1527 extbits = 15;
1528 break;
1529 case '5':
1530 nbits = 5;
1531 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1532 info->insn_type = dis_dref;
1533 info->data_size = 1;
1534 break;
1535 case 'H':
1536 nbits = 5;
1537 shift = 1;
1538 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1539 info->insn_type = dis_dref;
1540 info->data_size = 2;
1541 break;
1542 case 'W':
1543 nbits = 5;
1544 shift = 2;
1545 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1546 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1547 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1548 {
1549 info->insn_type = dis_dref;
1550 info->data_size = 4;
1551 }
1552 break;
1553 case 'D':
1554 nbits = 5;
1555 shift = 3;
1556 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1557 info->insn_type = dis_dref;
1558 info->data_size = 8;
1559 break;
1560 case 'j':
1561 nbits = 5;
1562 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1563 signedp = 1;
1564 break;
1565 case '6':
1566 nbits = 6;
1567 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1568 break;
1569 case '8':
1570 nbits = 8;
1571 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1572 break;
1573 case 'V':
1574 nbits = 8;
1575 shift = 2;
1576 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1577 /* FIXME: This might be lw, or it might be addiu to $sp or
1578 $pc. We assume it's load. */
1579 info->insn_type = dis_dref;
1580 info->data_size = 4;
1581 break;
1582 case 'C':
1583 nbits = 8;
1584 shift = 3;
1585 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1586 info->insn_type = dis_dref;
1587 info->data_size = 8;
1588 break;
1589 case 'U':
1590 nbits = 8;
1591 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1592 extu = 1;
1593 break;
1594 case 'k':
1595 nbits = 8;
1596 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1597 signedp = 1;
1598 break;
1599 case 'K':
1600 nbits = 8;
1601 shift = 3;
1602 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1603 signedp = 1;
1604 break;
1605 case 'p':
1606 nbits = 8;
1607 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1608 signedp = 1;
1609 pcrel = 1;
1610 branch = 1;
1611 info->insn_type = dis_condbranch;
1612 break;
1613 case 'q':
1614 nbits = 11;
1615 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1616 signedp = 1;
1617 pcrel = 1;
1618 branch = 1;
1619 info->insn_type = dis_branch;
1620 break;
1621 case 'A':
1622 nbits = 8;
1623 shift = 2;
1624 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1625 pcrel = 1;
1626 /* FIXME: This can be lw or la. We assume it is lw. */
1627 info->insn_type = dis_dref;
1628 info->data_size = 4;
1629 break;
1630 case 'B':
1631 nbits = 5;
1632 shift = 3;
1633 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1634 pcrel = 1;
1635 info->insn_type = dis_dref;
1636 info->data_size = 8;
1637 break;
1638 case 'E':
1639 nbits = 5;
1640 shift = 2;
1641 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1642 pcrel = 1;
1643 break;
1644 default:
1645 abort ();
1646 }
1647
1648 if (! use_extend)
1649 {
1650 if (signedp && immed >= (1 << (nbits - 1)))
1651 immed -= 1 << nbits;
1652 immed <<= shift;
1653 if ((type == '<' || type == '>' || type == '[' || type == ']')
1654 && immed == 0)
1655 immed = 8;
1656 }
1657 else
1658 {
1659 if (extbits == 16)
1660 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1661 else if (extbits == 15)
1662 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1663 else
1664 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1665 immed &= (1 << extbits) - 1;
1666 if (! extu && immed >= (1 << (extbits - 1)))
1667 immed -= 1 << extbits;
1668 }
1669
1670 if (! pcrel)
1671 (*info->fprintf_func) (info->stream, "%d", immed);
1672 else
1673 {
1674 bfd_vma baseaddr;
252b5132
RH		 1675
1676 if (branch)
1677 {
1678 immed *= 2;
1679 baseaddr = memaddr + 2;
1680 }
1681 else if (use_extend)
1682 baseaddr = memaddr - 2;
1683 else
1684 {
1685 int status;
1686 bfd_byte buffer[2];
1687
1688 baseaddr = memaddr;
1689
1690 /* If this instruction is in the delay slot of a jr
1691 instruction, the base address is the address of the
1692 jr instruction. If it is in the delay slot of jalr
1693 instruction, the base address is the address of the
1694 jalr instruction. This test is unreliable: we have
1695 no way of knowing whether the previous word is
1696 instruction or data. */
1697 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1698 info);
1699 if (status == 0
1700 && (((info->endian == BFD_ENDIAN_BIG
1701 ? bfd_getb16 (buffer)
1702 : bfd_getl16 (buffer))
1703 & 0xf800) == 0x1800))
1704 baseaddr = memaddr - 4;
1705 else
1706 {
1707 status = (*info->read_memory_func) (memaddr - 2, buffer,
1708 2, info);
1709 if (status == 0
1710 && (((info->endian == BFD_ENDIAN_BIG
1711 ? bfd_getb16 (buffer)
1712 : bfd_getl16 (buffer))
1713 & 0xf81f) == 0xe800))
1714 baseaddr = memaddr - 2;
1715 }
1716 }
9bb28706
CD		 1717 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1718 (*info->print_address_func) (info->target, info);
252b5132
RH		 1719 }
1720 }
1721 break;
1722
1723 case 'a':
1724 if (! use_extend)
1725 extend = 0;
1726 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
9bb28706
CD		 1727 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1728 (*info->print_address_func) (info->target, info);
252b5132 1729 info->insn_type = dis_jsr;
252b5132
RH		 1730 info->branch_delay_insns = 1;
1731 break;
1732
1733 case 'l':
1734 case 'L':
1735 {
1736 int need_comma, amask, smask;
1737
1738 need_comma = 0;
1739
1740 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1741
1742 amask = (l >> 3) & 7;
1743
1744 if (amask > 0 && amask < 5)
1745 {
640c0ccd 1746 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
252b5132 1747 if (amask > 1)
aa5f19f2 1748 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1749 mips_gpr_names[amask + 3]);
252b5132
RH		 1750 need_comma = 1;
1751 }
1752
1753 smask = (l >> 1) & 3;
1754 if (smask == 3)
1755 {
1756 (*info->fprintf_func) (info->stream, "%s??",
1757 need_comma ? "," : "");
1758 need_comma = 1;
1759 }
1760 else if (smask > 0)
1761 {
aa5f19f2 1762 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1763 need_comma ? "," : "",
640c0ccd 1764 mips_gpr_names[16]);
252b5132 1765 if (smask > 1)
aa5f19f2 1766 (*info->fprintf_func) (info->stream, "-%s",
640c0ccd 1767 mips_gpr_names[smask + 15]);
252b5132
RH		 1768 need_comma = 1;
1769 }
1770
1771 if (l & 1)
1772 {
aa5f19f2 1773 (*info->fprintf_func) (info->stream, "%s%s",
252b5132 1774 need_comma ? "," : "",
640c0ccd 1775 mips_gpr_names[31]);
252b5132
RH		 1776 need_comma = 1;
1777 }
1778
1779 if (amask == 5 || amask == 6)
1780 {
1781 (*info->fprintf_func) (info->stream, "%s$f0",
1782 need_comma ? "," : "");
1783 if (amask == 6)
1784 (*info->fprintf_func) (info->stream, "-$f1");
1785 }
1786 }
1787 break;
1788
1789 default:
aa5f19f2
NC		 1790 /* xgettext:c-format */
1791 (*info->fprintf_func)
1792 (info->stream,
1793 _("# internal disassembler error, unrecognised modifier (%c)"),
1794 type);
252b5132
RH		 1795 abort ();
1796 }
1797}
640c0ccd
CD		 1798
1799void
1800print_mips_disassembler_options (stream)
1801 FILE *stream;
1802{
4a9a3c54 1803 unsigned int i;
640c0ccd
CD		 1804
1805 fprintf (stream, _("\n\
1806The following MIPS specific disassembler options are supported for use\n\
1807with the -M switch (multiple options should be separated by commas):\n"));
1808
1809 fprintf (stream, _("\n\
1810 gpr-names=ABI Print GPR names according to specified ABI.\n\
1811 Default: based on binary being disassembled.\n"));
1812
1813 fprintf (stream, _("\n\
1814 fpr-names=ABI Print FPR names according to specified ABI.\n\
1815 Default: numeric.\n"));
1816
1817 fprintf (stream, _("\n\
1818 cp0-names=ARCH Print CP0 register names according to\n\
1819 specified architecture.\n\
1820 Default: based on binary being disassembled.\n"));
1821
af7ee8bf
CD		 1822 fprintf (stream, _("\n\
1823 hwr-names=ARCH Print HWR names according to specified \n\
1824 architecture.\n\
1825 Default: based on binary being disassembled.\n"));
1826
640c0ccd
CD		 1827 fprintf (stream, _("\n\
1828 reg-names=ABI Print GPR and FPR names according to\n\
1829 specified ABI.\n"));
1830
1831 fprintf (stream, _("\n\
af7ee8bf 1832 reg-names=ARCH Print CP0 register and HWR names according to\n\
640c0ccd
CD		 1833 specified architecture.\n"));
1834
1835 fprintf (stream, _("\n\
1836 For the options above, the following values are supported for \"ABI\":\n\
1837 "));
4a9a3c54 1838 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
640c0ccd
CD		 1839 fprintf (stream, " %s", mips_abi_choices[i].name);
1840 fprintf (stream, _("\n"));
1841
1842 fprintf (stream, _("\n\
1843 For the options above, The following values are supported for \"ARCH\":\n\
1844 "));
4a9a3c54 1845 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
640c0ccd
CD		 1846 if (*mips_arch_choices[i].name != '\0')
1847 fprintf (stream, " %s", mips_arch_choices[i].name);
1848 fprintf (stream, _("\n"));
1849
1850 fprintf (stream, _("\n"));
1851}
GDB Binutils - Deliverables
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