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* ppc-opc.c (insert_li): Give an error if the offset has the two
[deliverable/binutils-gdb.git] / opcodes / mn10300-opc.c
CommitLineData
ae1b99e4 1/* Assemble Matsushita MN10300 instructions.
e7c50cef
JL		 2 Copyright (C) 1996 Free Software Foundation, Inc.
3
4This program is free software; you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation; either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program; if not, write to the Free Software
16Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#include "ansidecl.h"
ae1b99e4 19#include "opcode/mn10300.h"
e7c50cef
JL		 20
21\f
ae1b99e4 22const struct mn10300_operand mn10300_operands[] = {
e7c50cef 23#define UNUSED 0
5ab7bce6
JL		 24 {0, 0, 0},
25
36b34aa4 26#define DN0 (UNUSED+1)
5ab7bce6
JL		 27 {2, 0, MN10300_OPERAND_DREG},
28
36b34aa4
JL		 29#define DN1 (DN0+1)
30 {2, 2, MN10300_OPERAND_DREG},
31
bb5e141a
JL		 32#define DN2 (DN1+1)
33 {2, 4, MN10300_OPERAND_DREG},
34
35#define DM0 (DN2+1)
5ab7bce6
JL		 36 {2, 0, MN10300_OPERAND_DREG},
37
36b34aa4
JL		 38#define DM1 (DM0+1)
39 {2, 2, MN10300_OPERAND_DREG},
40
bb5e141a
JL		 41#define DM2 (DM1+1)
42 {2, 4, MN10300_OPERAND_DREG},
43
44#define AN0 (DM2+1)
5ab7bce6
JL		 45 {2, 0, MN10300_OPERAND_AREG},
46
36b34aa4
JL		 47#define AN1 (AN0+1)
48 {2, 2, MN10300_OPERAND_AREG},
49
bb5e141a
JL		 50#define AN2 (AN1+1)
51 {2, 4, MN10300_OPERAND_AREG},
52
53#define AM0 (AN2+1)
5ab7bce6
JL		 54 {2, 0, MN10300_OPERAND_AREG},
55
36b34aa4
JL		 56#define AM1 (AM0+1)
57 {2, 2, MN10300_OPERAND_AREG},
58
bb5e141a
JL		 59#define AM2 (AM1+1)
60 {2, 4, MN10300_OPERAND_AREG},
61
62#define IMM8 (AM2+1)
5ab7bce6
JL		 63 {8, 0, MN10300_OPERAND_PROMOTE},
64
65#define IMM16 (IMM8+1)
66 {16, 0, MN10300_OPERAND_PROMOTE},
67
aa9c04cd
JL		 68#define IMM16_PCREL (IMM16+1)
69 {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
70
71#define IMM16_MEM (IMM16_PCREL+1)
72 {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
73
64ce0668 74/* 32bit immediate, high 16 bits in the main instruction
26433754
JL		 75 word, 16bits in the extension word.
76
77 The "bits" field indicates how many bits are in the
78 main instruction word for MN10300_OPERAND_SPLIT! */
aa9c04cd 79#define IMM32 (IMM16_MEM+1)
26433754 80 {16, 0, MN10300_OPERAND_SPLIT},
5ab7bce6 81
aa9c04cd
JL		 82#define IMM32_PCREL (IMM32+1)
83 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
84
85#define IMM32_MEM (IMM32_PCREL+1)
86 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
87
64ce0668
JL		 88/* 32bit immediate, high 16 bits in the main instruction
89 word, 16bits in the extension word, low 16bits are left
26433754
JL		 90 shifted 8 places.
91
92 The "bits" field indicates how many bits are in the
93 main instruction word for MN10300_OPERAND_SPLIT! */
aa9c04cd
JL		 94#define IMM32_LOWSHIFT8 (IMM32_MEM+1)
95 {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
26433754
JL		 96
97/* 32bit immediate, high 24 bits in the main instruction
98 word, 8 in the extension word.
99
100 The "bits" field indicates how many bits are in the
101 main instruction word for MN10300_OPERAND_SPLIT! */
102#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
aa9c04cd 103 {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
64ce0668 104
26433754
JL		 105/* 32bit immediate, high 24 bits in the main instruction
106 word, 8 in the extension word, low 8 bits are left
107 shifted 16 places.
108
109 The "bits" field indicates how many bits are in the
110 main instruction word for MN10300_OPERAND_SPLIT! */
111#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
aa9c04cd 112 {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
26433754
JL		 113
114#define SP (IMM32_HIGH24_LOWSHIFT16+1)
5ab7bce6
JL		 115 {8, 0, MN10300_OPERAND_SP},
116
117#define PSW (SP+1)
118 {0, 0, MN10300_OPERAND_PSW},
119
120#define MDR (PSW+1)
121 {0, 0, MN10300_OPERAND_MDR},
122
fdef41f3 123#define DI (MDR+1)
bb5e141a 124 {2, 2, MN10300_OPERAND_DREG},
5ab7bce6 125
db229054 126#define SD8 (DI+1)
5ab7bce6
JL		 127 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
128
129#define SD16 (SD8+1)
130 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
131
132#define SD8N (SD16+1)
133 {8, 0, MN10300_OPERAND_SIGNED},
134
aa9c04cd
JL		 135#define SD8N_PCREL (SD8N+1)
136 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL},
137
138#define SD8N_SHIFT8 (SD8N_PCREL+1)
bb5e141a
JL		 139 {8, 8, MN10300_OPERAND_SIGNED},
140
141#define SIMM8 (SD8N_SHIFT8+1)
5ab7bce6
JL		 142 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
143
144#define SIMM16 (SIMM8+1)
145 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
db229054
JL		 146
147#define PAREN (SIMM16+1)
148 {0, 0, MN10300_OPERAND_PAREN},
e85c140a
JL		 149
150#define DN01 (PAREN+1)
151 {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
152
153#define AN01 (DN01+1)
154 {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
155
bb5e141a 156#define D16_SHIFT (AN01+1)
aa9c04cd 157 {16, 8, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL},
bb5e141a
JL		 158
159#define IMM8E (D16_SHIFT+1)
160 {8, 0, MN10300_OPERAND_EXTENDED},
161
f0398190
JL		 162#define REGSE_SHIFT8 (IMM8E+1)
163 {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
26433754 164
f0398190
JL		 165#define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
166 {8, 8, MN10300_OPERAND_REG_LIST},
bb5e141a 167
f0398190 168#define REGS (REGS_SHIFT8+1)
99246e03
JL		 169 {8, 0, MN10300_OPERAND_REG_LIST},
170
e7c50cef
JL		 171} ;
172
db229054
JL		 173#define MEM(ADDR) PAREN, ADDR, PAREN
174#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
e7c50cef
JL		 175\f
176/* The opcode table.
177
178 The format of the opcode table is:
179
180 NAME OPCODE MASK { OPERANDS }
181
182 NAME is the name of the instruction.
183 OPCODE is the instruction opcode.
184 MASK is the opcode mask; this is used to tell the disassembler
185 which bits in the actual opcode must match OPCODE.
186 OPERANDS is the list of operands.
187
188 The disassembler reads the table in order and prints the first
189 instruction which matches, so this table is sorted to put more
190 specific instructions before more general instructions. It is also
191 sorted by major opcode. */
192
ae1b99e4 193const struct mn10300_opcode mn10300_opcodes[] = {
e85c140a 194{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}},
36b34aa4
JL		 195{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}},
196{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}},
197{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}},
e85c140a 198{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN01}},
36b34aa4
JL		 199{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}},
200{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}},
201{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}},
202{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}},
203{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}},
204{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}},
205{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}},
206{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}},
207{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
208{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
fdef41f3
JL		 209{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
210{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(IMM8, SP), DN0}},
211{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
212{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
bb5e141a 213{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
aa9c04cd
JL		 214{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
215{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
36b34aa4 216{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
fdef41f3
JL		 217{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(SD8,AM0), AN1}},
218{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), AN1}},
219{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), AN1}},
220{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(IMM8, SP), AN0}},
221{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), AN0}},
222{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), AN0}},
bb5e141a 223{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}},
aa9c04cd
JL		 224{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(IMM16_MEM), AN0}},
225{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), AN0}},
36b34aa4
JL		 226{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
227{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}},
228{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
229{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
fdef41f3
JL		 230{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
231{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(IMM8, SP)}},
232{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
233{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
bb5e141a 234{ "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
aa9c04cd
JL		 235{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
236{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
36b34aa4
JL		 237{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
238{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}},
239{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}},
fdef41f3
JL		 240{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(IMM32,AN0)}},
241{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(IMM8, SP)}},
242{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(IMM16, SP)}},
23b01150 243{ "mov", 0xfc900000, 0xfff30000, FMT_D4, {AM1, MEM2(IMM32, SP)}},
bb5e141a 244{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}},
aa9c04cd
JL		 245{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(IMM16_MEM)}},
246{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(IMM32_MEM)}},
36b34aa4
JL		 247{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
248{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}},
fdef41f3 249{ "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
36b34aa4
JL		 250{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}},
251{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
252
253{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
254{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
255{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
fdef41f3
JL		 256{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
257{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
258{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
259{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
bb5e141a 260{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
aa9c04cd
JL		 261{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
262{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
36b34aa4
JL		 263{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
264{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
265{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
fdef41f3
JL		 266{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
267{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
268{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
269{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
bb5e141a 270{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
aa9c04cd
JL		 271{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
272{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
36b34aa4
JL		 273
274{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
275{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
276{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
fdef41f3
JL		 277{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
278{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
279{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
280{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
bb5e141a 281{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
aa9c04cd
JL		 282{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
283{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
36b34aa4
JL		 284{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
285{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
286{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
fdef41f3
JL		 287{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
288{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
289{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
290{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
bb5e141a 291{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
aa9c04cd
JL		 292{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
293{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
36b34aa4
JL		 294
295{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}},
296{ "extb", 0x10, 0xfc, FMT_S0, {DN0}},
297{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}},
298{ "exth", 0x18, 0xfc, FMT_S0, {DN0}},
299{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}},
db229054 300
99246e03
JL		 301{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), REGS}},
302{ "movm", 0xcf00, 0xff00, FMT_S1, {REGS, MEM(SP)}},
db229054 303
36b34aa4
JL		 304{ "clr", 0x00, 0xf3, FMT_S0, {DN1}},
305
306{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}},
307{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}},
308{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}},
309{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}},
310{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}},
311{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
312{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
313{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}},
314{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}},
315{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
db229054 316{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
4aa92185
JL		 317{ "add", 0xfafe0000, 0xffff0000, FMT_D2, {SIMM16, SP}},
318{ "add", 0xfcfe0000, 0xffff0000, FMT_D4, {IMM32, SP}},
36b34aa4
JL		 319{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}},
320
321{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}},
322{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}},
323{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}},
324{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}},
325{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
326{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
327{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}},
328
329{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}},
330{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}},
331
332{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}},
333{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}},
334
335{ "inc", 0x40, 0xf3, FMT_S0, {DN1}},
336{ "inc", 0x41, 0xf3, FMT_S0, {AN1}},
337{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}},
338
e85c140a 339{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN01}},
36b34aa4
JL		 340{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}},
341{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}},
342{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}},
e85c140a 343{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN01}},
36b34aa4
JL		 344{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}},
345{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
346{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
347{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}},
348{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
349
350{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}},
351{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}},
352{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
353{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
4aa92185 354{ "and", 0xfafc0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
36b34aa4
JL		 355{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}},
356{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}},
357{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
358{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
4aa92185 359{ "or", 0xfafd0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
36b34aa4
JL		 360{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}},
361{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
362{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
363{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}},
364
365{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
366{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
367{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
64ce0668
JL		 368{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E,
369 MEM(IMM32_LOWSHIFT8)}},
bb5e141a
JL		 370{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
371 {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
36b34aa4 372{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
64ce0668
JL		 373{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E,
374 MEM(IMM32_LOWSHIFT8)}},
bb5e141a
JL		 375{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
376 {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
36b34aa4 377{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
64ce0668
JL		 378{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E,
379 MEM(IMM32_LOWSHIFT8)}},
bb5e141a 380{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
64ce0668 381 MEM2(SD8N_SHIFT8,AN0)}},
36b34aa4 382
1e5ddd3b 383{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4 384{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
1e5ddd3b 385{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4 386{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
1e5ddd3b 387{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
36b34aa4
JL		 388{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
389{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
390{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
391{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}},
db229054 392
aa9c04cd
JL		 393{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N_PCREL}},
394{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N_PCREL}},
395{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N_PCREL}},
396{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N_PCREL}},
397{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N_PCREL}},
398{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N_PCREL}},
399{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N_PCREL}},
400{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N_PCREL}},
401{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N_PCREL}},
402{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N_PCREL}},
403{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N_PCREL}},
404{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N_PCREL}},
405{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N_PCREL}},
406{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N_PCREL}},
407{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N_PCREL}},
db229054
JL		 408
409{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
410{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
411{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
412{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
413{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
414{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
415{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
416{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
417{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
418{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
419{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
db229054
JL		 420{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
421
54dfaf0a 422{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
aa9c04cd 423{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {IMM16_PCREL}},
26433754 424{ "jmp", 0xdc000000, 0xff000000, FMT_S4, {IMM32_HIGH24}},
f0398190 425{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,REGS,IMM8E}},
26433754 426{ "call", 0xdd000000, 0xff000000, FMT_S6,
f0398190 427 {IMM32_HIGH24_LOWSHIFT16,REGSE_SHIFT8,IMM8E}},
54dfaf0a 428{ "calls", 0xf0f0, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
aa9c04cd
JL		 429{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {IMM16_PCREL}},
430{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {IMM32_PCREL}},
db229054 431
f0398190
JL		 432{ "ret", 0xdf0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}},
433{ "retf", 0xde0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}},
db229054
JL		 434{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
435{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
436{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
437{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
438{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
439/* { "udf", 0, 0, {0}}, */
344d6417 440
f2ab9a75
JL		 441{ "putx", 0xf500, 0xfff0, FMT_D0, {DN01}},
442{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN01}},
36b34aa4
JL		 443{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}},
444{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}},
445{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
446{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
447{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}},
f2ab9a75
JL		 448{ "mulqu", 0xf91400, 0xfffc00, FMT_D1, {SIMM8, DN0}},
449{ "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
450{ "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
36b34aa4
JL		 451{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}},
452{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}},
453{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}},
db229054 454{ 0, 0, 0, 0, {0}},
5ab7bce6 455
cd8a9026 456} ;
e7c50cef 457
ae1b99e4
JL		 458const int mn10300_num_opcodes =
459 sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
e7c50cef
JL		 460
461\f
GDB Binutils - Deliverables
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