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ac188222 DB |
1 | /* CPU data for ms1. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright 1996-2005 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #include "sysdep.h" | |
26 | #include <stdio.h> | |
27 | #include <stdarg.h> | |
28 | #include "ansidecl.h" | |
29 | #include "bfd.h" | |
30 | #include "symcat.h" | |
31 | #include "ms1-desc.h" | |
32 | #include "ms1-opc.h" | |
33 | #include "opintl.h" | |
34 | #include "libiberty.h" | |
35 | #include "xregex.h" | |
36 | ||
37 | /* Attributes. */ | |
38 | ||
39 | static const CGEN_ATTR_ENTRY bool_attr[] = | |
40 | { | |
41 | { "#f", 0 }, | |
42 | { "#t", 1 }, | |
43 | { 0, 0 } | |
44 | }; | |
45 | ||
46 | static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = | |
47 | { | |
48 | { "base", MACH_BASE }, | |
49 | { "ms1", MACH_MS1 }, | |
50 | { "ms1_003", MACH_MS1_003 }, | |
51 | { "max", MACH_MAX }, | |
52 | { 0, 0 } | |
53 | }; | |
54 | ||
55 | static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = | |
56 | { | |
57 | { "ms1", ISA_MS1 }, | |
58 | { "max", ISA_MAX }, | |
59 | { 0, 0 } | |
60 | }; | |
61 | ||
62 | const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[] = | |
63 | { | |
64 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
65 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
66 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
67 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
68 | { "RESERVED", &bool_attr[0], &bool_attr[0] }, | |
69 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
70 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
71 | { 0, 0, 0 } | |
72 | }; | |
73 | ||
74 | const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[] = | |
75 | { | |
76 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
77 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
78 | { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, | |
79 | { "PC", &bool_attr[0], &bool_attr[0] }, | |
80 | { "PROFILE", &bool_attr[0], &bool_attr[0] }, | |
81 | { 0, 0, 0 } | |
82 | }; | |
83 | ||
84 | const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[] = | |
85 | { | |
86 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
87 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
88 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
89 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
90 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
91 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
92 | { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, | |
93 | { "RELAX", &bool_attr[0], &bool_attr[0] }, | |
94 | { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, | |
95 | { 0, 0, 0 } | |
96 | }; | |
97 | ||
98 | const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[] = | |
99 | { | |
100 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
101 | { "ALIAS", &bool_attr[0], &bool_attr[0] }, | |
102 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
103 | { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, | |
104 | { "COND-CTI", &bool_attr[0], &bool_attr[0] }, | |
105 | { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, | |
106 | { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, | |
107 | { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, | |
108 | { "RELAXED", &bool_attr[0], &bool_attr[0] }, | |
109 | { "NO-DIS", &bool_attr[0], &bool_attr[0] }, | |
110 | { "PBB", &bool_attr[0], &bool_attr[0] }, | |
111 | { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, | |
112 | { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] }, | |
113 | { "AL-INSN", &bool_attr[0], &bool_attr[0] }, | |
114 | { "IO-INSN", &bool_attr[0], &bool_attr[0] }, | |
115 | { "BR-INSN", &bool_attr[0], &bool_attr[0] }, | |
116 | { "USES-FRDR", &bool_attr[0], &bool_attr[0] }, | |
117 | { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] }, | |
118 | { "USES-FRSR1", &bool_attr[0], &bool_attr[0] }, | |
119 | { "USES-FRSR2", &bool_attr[0], &bool_attr[0] }, | |
120 | { "SKIPA", &bool_attr[0], &bool_attr[0] }, | |
121 | { 0, 0, 0 } | |
122 | }; | |
123 | ||
124 | /* Instruction set variants. */ | |
125 | ||
126 | static const CGEN_ISA ms1_cgen_isa_table[] = { | |
127 | { "ms1", 32, 32, 32, 32 }, | |
128 | { 0, 0, 0, 0, 0 } | |
129 | }; | |
130 | ||
131 | /* Machine variants. */ | |
132 | ||
133 | static const CGEN_MACH ms1_cgen_mach_table[] = { | |
134 | { "ms1", "ms1", MACH_MS1, 0 }, | |
135 | { "ms1-003", "ms1-003", MACH_MS1_003, 0 }, | |
136 | { 0, 0, 0, 0 } | |
137 | }; | |
138 | ||
139 | static CGEN_KEYWORD_ENTRY ms1_cgen_opval_msys_syms_entries[] = | |
140 | { | |
141 | { "DUP", 1, {0, {0}}, 0, 0 }, | |
142 | { "XX", 0, {0, {0}}, 0, 0 } | |
143 | }; | |
144 | ||
145 | CGEN_KEYWORD ms1_cgen_opval_msys_syms = | |
146 | { | |
147 | & ms1_cgen_opval_msys_syms_entries[0], | |
148 | 2, | |
149 | 0, 0, 0, 0, "" | |
150 | }; | |
151 | ||
152 | static CGEN_KEYWORD_ENTRY ms1_cgen_opval_h_spr_entries[] = | |
153 | { | |
154 | { "R0", 0, {0, {0}}, 0, 0 }, | |
155 | { "R1", 1, {0, {0}}, 0, 0 }, | |
156 | { "R2", 2, {0, {0}}, 0, 0 }, | |
157 | { "R3", 3, {0, {0}}, 0, 0 }, | |
158 | { "R4", 4, {0, {0}}, 0, 0 }, | |
159 | { "R5", 5, {0, {0}}, 0, 0 }, | |
160 | { "R6", 6, {0, {0}}, 0, 0 }, | |
161 | { "R7", 7, {0, {0}}, 0, 0 }, | |
162 | { "R8", 8, {0, {0}}, 0, 0 }, | |
163 | { "R9", 9, {0, {0}}, 0, 0 }, | |
164 | { "R10", 10, {0, {0}}, 0, 0 }, | |
165 | { "R11", 11, {0, {0}}, 0, 0 }, | |
166 | { "R12", 12, {0, {0}}, 0, 0 }, | |
167 | { "fp", 12, {0, {0}}, 0, 0 }, | |
168 | { "R13", 13, {0, {0}}, 0, 0 }, | |
169 | { "sp", 13, {0, {0}}, 0, 0 }, | |
170 | { "R14", 14, {0, {0}}, 0, 0 }, | |
171 | { "ra", 14, {0, {0}}, 0, 0 }, | |
172 | { "R15", 15, {0, {0}}, 0, 0 }, | |
173 | { "ira", 15, {0, {0}}, 0, 0 } | |
174 | }; | |
175 | ||
176 | CGEN_KEYWORD ms1_cgen_opval_h_spr = | |
177 | { | |
178 | & ms1_cgen_opval_h_spr_entries[0], | |
179 | 20, | |
180 | 0, 0, 0, 0, "" | |
181 | }; | |
182 | ||
183 | ||
184 | /* The hardware table. */ | |
185 | ||
186 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
187 | #define A(a) (1 << CGEN_HW_##a) | |
188 | #else | |
189 | #define A(a) (1 << CGEN_HW_/**/a) | |
190 | #endif | |
191 | ||
192 | const CGEN_HW_ENTRY ms1_cgen_hw_table[] = | |
193 | { | |
194 | { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
195 | { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
196 | { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
197 | { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
198 | { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
199 | { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & ms1_cgen_opval_h_spr, { 0, { (1<<MACH_BASE) } } }, | |
200 | { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, | |
201 | { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } | |
202 | }; | |
203 | ||
204 | #undef A | |
205 | ||
206 | ||
207 | /* The instruction field table. */ | |
208 | ||
209 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
210 | #define A(a) (1 << CGEN_IFLD_##a) | |
211 | #else | |
212 | #define A(a) (1 << CGEN_IFLD_/**/a) | |
213 | #endif | |
214 | ||
215 | const CGEN_IFLD ms1_cgen_ifld_table[] = | |
216 | { | |
217 | { MS1_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, | |
218 | { MS1_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, | |
219 | { MS1_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } } }, | |
220 | { MS1_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, | |
221 | { MS1_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } } }, | |
222 | { MS1_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { (1<<MACH_BASE) } } }, | |
223 | { MS1_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
224 | { MS1_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
225 | { MS1_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
226 | { MS1_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
227 | { MS1_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, | |
228 | { MS1_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, | |
229 | { MS1_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
230 | { MS1_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { (1<<MACH_BASE) } } }, | |
231 | { MS1_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { (1<<MACH_BASE) } } }, | |
232 | { MS1_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, | |
233 | { MS1_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, | |
234 | { MS1_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { (1<<MACH_BASE) } } }, | |
235 | { MS1_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { (1<<MACH_BASE) } } }, | |
236 | { MS1_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { (1<<MACH_BASE) } } }, | |
237 | { MS1_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { (1<<MACH_BASE) } } }, | |
238 | { MS1_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, | |
239 | { MS1_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, | |
240 | { MS1_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, | |
241 | { MS1_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, | |
242 | { MS1_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, | |
243 | { MS1_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } } }, | |
244 | { MS1_F_WR, "f-wr", 0, 32, 24, 1, { 0, { (1<<MACH_BASE) } } }, | |
245 | { MS1_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { (1<<MACH_BASE) } } }, | |
246 | { MS1_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { (1<<MACH_BASE) } } }, | |
247 | { MS1_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { (1<<MACH_BASE) } } }, | |
248 | { MS1_F_A23, "f-a23", 0, 32, 23, 1, { 0, { (1<<MACH_BASE) } } }, | |
249 | { MS1_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } } }, | |
250 | { MS1_F_CR, "f-cr", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } } }, | |
251 | { MS1_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { (1<<MACH_BASE) } } }, | |
252 | { MS1_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { (1<<MACH_BASE) } } }, | |
253 | { MS1_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { (1<<MACH_BASE) } } }, | |
254 | { MS1_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } }, | |
255 | { MS1_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } }, | |
256 | { MS1_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { (1<<MACH_BASE) } } }, | |
257 | { MS1_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { (1<<MACH_BASE) } } }, | |
258 | { MS1_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, | |
259 | { MS1_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { (1<<MACH_BASE) } } }, | |
260 | { MS1_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { (1<<MACH_BASE) } } }, | |
261 | { MS1_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } } }, | |
262 | { MS1_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, | |
263 | { MS1_F_RC, "f-rc", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, | |
264 | { MS1_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, | |
265 | { MS1_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, | |
266 | { MS1_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, | |
267 | { MS1_F_ID, "f-id", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } }, | |
268 | { MS1_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { (1<<MACH_BASE) } } }, | |
269 | { MS1_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { (1<<MACH_BASE) } } }, | |
270 | { MS1_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } } }, | |
271 | { MS1_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } }, | |
272 | { MS1_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } }, | |
273 | { MS1_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } } }, | |
274 | { MS1_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } } }, | |
275 | { MS1_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, | |
276 | { MS1_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, | |
277 | { MS1_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } }, | |
278 | { MS1_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { (1<<MACH_BASE) } } }, | |
279 | { MS1_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } } }, | |
280 | { MS1_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } } }, | |
281 | { MS1_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { (1<<MACH_BASE) } } }, | |
282 | { MS1_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, | |
283 | { MS1_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { (1<<MACH_BASE) } } }, | |
284 | { MS1_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, | |
285 | { MS1_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, | |
286 | { 0, 0, 0, 0, 0, 0, {0, {0}} } | |
287 | }; | |
288 | ||
289 | #undef A | |
290 | ||
291 | ||
292 | ||
293 | /* multi ifield declarations */ | |
294 | ||
295 | ||
296 | ||
297 | /* multi ifield definitions */ | |
298 | ||
299 | ||
300 | /* The operand table. */ | |
301 | ||
302 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
303 | #define A(a) (1 << CGEN_OPERAND_##a) | |
304 | #else | |
305 | #define A(a) (1 << CGEN_OPERAND_/**/a) | |
306 | #endif | |
307 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
308 | #define OPERAND(op) MS1_OPERAND_##op | |
309 | #else | |
310 | #define OPERAND(op) MS1_OPERAND_/**/op | |
311 | #endif | |
312 | ||
313 | const CGEN_OPERAND ms1_cgen_operand_table[] = | |
314 | { | |
315 | /* pc: program counter */ | |
316 | { "pc", MS1_OPERAND_PC, HW_H_PC, 0, 0, | |
317 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_NIL] } }, | |
318 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, | |
319 | /* frsr1: register */ | |
320 | { "frsr1", MS1_OPERAND_FRSR1, HW_H_SPR, 23, 4, | |
321 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR1] } }, | |
322 | { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
323 | /* frsr2: register */ | |
324 | { "frsr2", MS1_OPERAND_FRSR2, HW_H_SPR, 19, 4, | |
325 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SR2] } }, | |
326 | { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
327 | /* frdr: register */ | |
328 | { "frdr", MS1_OPERAND_FRDR, HW_H_SPR, 19, 4, | |
329 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DR] } }, | |
330 | { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
331 | /* frdrrr: register */ | |
332 | { "frdrrr", MS1_OPERAND_FRDRRR, HW_H_SPR, 15, 4, | |
333 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DRRR] } }, | |
334 | { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
335 | /* imm16: immediate value - sign extd */ | |
336 | { "imm16", MS1_OPERAND_IMM16, HW_H_SINT, 15, 16, | |
337 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } }, | |
338 | { 0, { (1<<MACH_BASE) } } }, | |
339 | /* imm16z: immediate value - zero extd */ | |
340 | { "imm16z", MS1_OPERAND_IMM16Z, HW_H_UINT, 15, 16, | |
341 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16U] } }, | |
342 | { 0, { (1<<MACH_BASE) } } }, | |
343 | /* imm16o: immediate value */ | |
344 | { "imm16o", MS1_OPERAND_IMM16O, HW_H_UINT, 15, 16, | |
345 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_IMM16S] } }, | |
346 | { 0, { (1<<MACH_BASE) } } }, | |
347 | /* rc: rc */ | |
348 | { "rc", MS1_OPERAND_RC, HW_H_UINT, 15, 1, | |
349 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC] } }, | |
350 | { 0, { (1<<MACH_BASE) } } }, | |
351 | /* rcnum: rcnum */ | |
352 | { "rcnum", MS1_OPERAND_RCNUM, HW_H_UINT, 14, 3, | |
353 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RCNUM] } }, | |
354 | { 0, { (1<<MACH_BASE) } } }, | |
355 | /* contnum: context number */ | |
356 | { "contnum", MS1_OPERAND_CONTNUM, HW_H_UINT, 8, 9, | |
357 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CONTNUM] } }, | |
358 | { 0, { (1<<MACH_BASE) } } }, | |
359 | /* rbbc: omega network configuration */ | |
360 | { "rbbc", MS1_OPERAND_RBBC, HW_H_UINT, 25, 2, | |
361 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RBBC] } }, | |
362 | { 0, { (1<<MACH_BASE) } } }, | |
363 | /* colnum: column number */ | |
364 | { "colnum", MS1_OPERAND_COLNUM, HW_H_UINT, 18, 3, | |
365 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_COLNUM] } }, | |
366 | { 0, { (1<<MACH_BASE) } } }, | |
367 | /* rownum: row number */ | |
368 | { "rownum", MS1_OPERAND_ROWNUM, HW_H_UINT, 14, 3, | |
369 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM] } }, | |
370 | { 0, { (1<<MACH_BASE) } } }, | |
371 | /* rownum1: row number */ | |
372 | { "rownum1", MS1_OPERAND_ROWNUM1, HW_H_UINT, 12, 3, | |
373 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM1] } }, | |
374 | { 0, { (1<<MACH_BASE) } } }, | |
375 | /* rownum2: row number */ | |
376 | { "rownum2", MS1_OPERAND_ROWNUM2, HW_H_UINT, 9, 3, | |
377 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ROWNUM2] } }, | |
378 | { 0, { (1<<MACH_BASE) } } }, | |
379 | /* rc1: rc1 */ | |
380 | { "rc1", MS1_OPERAND_RC1, HW_H_UINT, 11, 1, | |
381 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC1] } }, | |
382 | { 0, { (1<<MACH_BASE) } } }, | |
383 | /* rc2: rc2 */ | |
384 | { "rc2", MS1_OPERAND_RC2, HW_H_UINT, 6, 1, | |
385 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RC2] } }, | |
386 | { 0, { (1<<MACH_BASE) } } }, | |
387 | /* cbrb: data-bus orientation */ | |
388 | { "cbrb", MS1_OPERAND_CBRB, HW_H_UINT, 10, 1, | |
389 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBRB] } }, | |
390 | { 0, { (1<<MACH_BASE) } } }, | |
391 | /* cell: cell */ | |
392 | { "cell", MS1_OPERAND_CELL, HW_H_UINT, 9, 3, | |
393 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CELL] } }, | |
394 | { 0, { (1<<MACH_BASE) } } }, | |
395 | /* dup: dup */ | |
396 | { "dup", MS1_OPERAND_DUP, HW_H_UINT, 6, 1, | |
397 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_DUP] } }, | |
398 | { 0, { (1<<MACH_BASE) } } }, | |
399 | /* ctxdisp: context displacement */ | |
400 | { "ctxdisp", MS1_OPERAND_CTXDISP, HW_H_UINT, 5, 6, | |
401 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CTXDISP] } }, | |
402 | { 0, { (1<<MACH_BASE) } } }, | |
403 | /* fbdisp: frame buffer displacement */ | |
404 | { "fbdisp", MS1_OPERAND_FBDISP, HW_H_UINT, 15, 6, | |
405 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBDISP] } }, | |
406 | { 0, { (1<<MACH_BASE) } } }, | |
407 | /* type: type */ | |
408 | { "type", MS1_OPERAND_TYPE, HW_H_UINT, 21, 2, | |
409 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_TYPE] } }, | |
410 | { 0, { (1<<MACH_BASE) } } }, | |
411 | /* mask: mask */ | |
412 | { "mask", MS1_OPERAND_MASK, HW_H_UINT, 25, 16, | |
413 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK] } }, | |
414 | { 0, { (1<<MACH_BASE) } } }, | |
415 | /* bankaddr: bank address */ | |
416 | { "bankaddr", MS1_OPERAND_BANKADDR, HW_H_UINT, 25, 13, | |
417 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BANKADDR] } }, | |
418 | { 0, { (1<<MACH_BASE) } } }, | |
419 | /* incamt: increment amount */ | |
420 | { "incamt", MS1_OPERAND_INCAMT, HW_H_UINT, 19, 8, | |
421 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCAMT] } }, | |
422 | { 0, { (1<<MACH_BASE) } } }, | |
423 | /* xmode: xmode */ | |
424 | { "xmode", MS1_OPERAND_XMODE, HW_H_UINT, 23, 1, | |
425 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_XMODE] } }, | |
426 | { 0, { (1<<MACH_BASE) } } }, | |
427 | /* mask1: mask1 */ | |
428 | { "mask1", MS1_OPERAND_MASK1, HW_H_UINT, 22, 3, | |
429 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MASK1] } }, | |
430 | { 0, { (1<<MACH_BASE) } } }, | |
431 | /* ball: b_all */ | |
432 | { "ball", MS1_OPERAND_BALL, HW_H_UINT, 19, 1, | |
433 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL] } }, | |
434 | { 0, { (1<<MACH_BASE) } } }, | |
435 | /* brc: b_r_c */ | |
436 | { "brc", MS1_OPERAND_BRC, HW_H_UINT, 18, 3, | |
437 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC] } }, | |
438 | { 0, { (1<<MACH_BASE) } } }, | |
439 | /* rda: rd */ | |
440 | { "rda", MS1_OPERAND_RDA, HW_H_UINT, 25, 1, | |
441 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_RDA] } }, | |
442 | { 0, { (1<<MACH_BASE) } } }, | |
443 | /* wr: wr */ | |
444 | { "wr", MS1_OPERAND_WR, HW_H_UINT, 24, 1, | |
445 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_WR] } }, | |
446 | { 0, { (1<<MACH_BASE) } } }, | |
447 | /* ball2: b_all2 */ | |
448 | { "ball2", MS1_OPERAND_BALL2, HW_H_UINT, 15, 1, | |
449 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BALL2] } }, | |
450 | { 0, { (1<<MACH_BASE) } } }, | |
451 | /* brc2: b_r_c2 */ | |
452 | { "brc2", MS1_OPERAND_BRC2, HW_H_UINT, 14, 3, | |
453 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_BRC2] } }, | |
454 | { 0, { (1<<MACH_BASE) } } }, | |
455 | /* perm: perm */ | |
456 | { "perm", MS1_OPERAND_PERM, HW_H_UINT, 25, 2, | |
457 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_PERM] } }, | |
458 | { 0, { (1<<MACH_BASE) } } }, | |
459 | /* a23: a23 */ | |
460 | { "a23", MS1_OPERAND_A23, HW_H_UINT, 23, 1, | |
461 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_A23] } }, | |
462 | { 0, { (1<<MACH_BASE) } } }, | |
463 | /* cr: c-r */ | |
464 | { "cr", MS1_OPERAND_CR, HW_H_UINT, 22, 3, | |
465 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CR] } }, | |
466 | { 0, { (1<<MACH_BASE) } } }, | |
467 | /* cbs: cbs */ | |
468 | { "cbs", MS1_OPERAND_CBS, HW_H_UINT, 19, 2, | |
469 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBS] } }, | |
470 | { 0, { (1<<MACH_BASE) } } }, | |
471 | /* incr: incr */ | |
472 | { "incr", MS1_OPERAND_INCR, HW_H_UINT, 17, 6, | |
473 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_INCR] } }, | |
474 | { 0, { (1<<MACH_BASE) } } }, | |
475 | /* length: length */ | |
476 | { "length", MS1_OPERAND_LENGTH, HW_H_UINT, 15, 3, | |
477 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_LENGTH] } }, | |
478 | { 0, { (1<<MACH_BASE) } } }, | |
479 | /* cbx: cbx */ | |
480 | { "cbx", MS1_OPERAND_CBX, HW_H_UINT, 14, 3, | |
481 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CBX] } }, | |
482 | { 0, { (1<<MACH_BASE) } } }, | |
483 | /* ccb: ccb */ | |
484 | { "ccb", MS1_OPERAND_CCB, HW_H_UINT, 11, 1, | |
485 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CCB] } }, | |
486 | { 0, { (1<<MACH_BASE) } } }, | |
487 | /* cdb: cdb */ | |
488 | { "cdb", MS1_OPERAND_CDB, HW_H_UINT, 10, 1, | |
489 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_CDB] } }, | |
490 | { 0, { (1<<MACH_BASE) } } }, | |
491 | /* mode: mode */ | |
492 | { "mode", MS1_OPERAND_MODE, HW_H_UINT, 25, 2, | |
493 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_MODE] } }, | |
494 | { 0, { (1<<MACH_BASE) } } }, | |
495 | /* id: i/d */ | |
496 | { "id", MS1_OPERAND_ID, HW_H_UINT, 14, 1, | |
497 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_ID] } }, | |
498 | { 0, { (1<<MACH_BASE) } } }, | |
499 | /* size: size */ | |
500 | { "size", MS1_OPERAND_SIZE, HW_H_UINT, 13, 14, | |
501 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_SIZE] } }, | |
502 | { 0, { (1<<MACH_BASE) } } }, | |
503 | /* fbincr: fb incr */ | |
504 | { "fbincr", MS1_OPERAND_FBINCR, HW_H_UINT, 23, 4, | |
505 | { 0, { (const PTR) &ms1_cgen_ifld_table[MS1_F_FBINCR] } }, | |
506 | { 0, { (1<<MACH_BASE) } } }, | |
507 | /* sentinel */ | |
508 | { 0, 0, 0, 0, 0, | |
509 | { 0, { (const PTR) 0 } }, | |
510 | { 0, { 0 } } } | |
511 | }; | |
512 | ||
513 | #undef A | |
514 | ||
515 | ||
516 | /* The instruction table. */ | |
517 | ||
518 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) | |
519 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
520 | #define A(a) (1 << CGEN_INSN_##a) | |
521 | #else | |
522 | #define A(a) (1 << CGEN_INSN_/**/a) | |
523 | #endif | |
524 | ||
525 | static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] = | |
526 | { | |
527 | /* Special null first entry. | |
528 | A `num' value of zero is thus invalid. | |
529 | Also, the special `invalid' insn resides here. */ | |
530 | { 0, 0, 0, 0, {0, {0}} }, | |
531 | /* add $frdrrr,$frsr1,$frsr2 */ | |
532 | { | |
533 | MS1_INSN_ADD, "add", "add", 32, | |
534 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
535 | }, | |
536 | /* addu $frdrrr,$frsr1,$frsr2 */ | |
537 | { | |
538 | MS1_INSN_ADDU, "addu", "addu", 32, | |
539 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
540 | }, | |
541 | /* addi $frdr,$frsr1,#$imm16 */ | |
542 | { | |
543 | MS1_INSN_ADDI, "addi", "addi", 32, | |
544 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
545 | }, | |
546 | /* addui $frdr,$frsr1,#$imm16z */ | |
547 | { | |
548 | MS1_INSN_ADDUI, "addui", "addui", 32, | |
549 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
550 | }, | |
551 | /* sub $frdrrr,$frsr1,$frsr2 */ | |
552 | { | |
553 | MS1_INSN_SUB, "sub", "sub", 32, | |
554 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
555 | }, | |
556 | /* subu $frdrrr,$frsr1,$frsr2 */ | |
557 | { | |
558 | MS1_INSN_SUBU, "subu", "subu", 32, | |
559 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
560 | }, | |
561 | /* subi $frdr,$frsr1,#$imm16 */ | |
562 | { | |
563 | MS1_INSN_SUBI, "subi", "subi", 32, | |
564 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
565 | }, | |
566 | /* subui $frdr,$frsr1,#$imm16z */ | |
567 | { | |
568 | MS1_INSN_SUBUI, "subui", "subui", 32, | |
569 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
570 | }, | |
571 | /* mul $frdrrr,$frsr1,$frsr2 */ | |
572 | { | |
573 | MS1_INSN_MUL, "mul", "mul", 32, | |
574 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_MS1_003) } } | |
575 | }, | |
576 | /* muli $frdr,$frsr1,#$imm16 */ | |
577 | { | |
578 | MS1_INSN_MULI, "muli", "muli", 32, | |
579 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_MS1_003) } } | |
580 | }, | |
581 | /* and $frdrrr,$frsr1,$frsr2 */ | |
582 | { | |
583 | MS1_INSN_AND, "and", "and", 32, | |
584 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
585 | }, | |
586 | /* andi $frdr,$frsr1,#$imm16z */ | |
587 | { | |
588 | MS1_INSN_ANDI, "andi", "andi", 32, | |
589 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
590 | }, | |
591 | /* or $frdrrr,$frsr1,$frsr2 */ | |
592 | { | |
593 | MS1_INSN_OR, "or", "or", 32, | |
594 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
595 | }, | |
596 | /* nop */ | |
597 | { | |
598 | MS1_INSN_NOP, "nop", "nop", 32, | |
599 | { 0, { (1<<MACH_BASE) } } | |
600 | }, | |
601 | /* ori $frdr,$frsr1,#$imm16z */ | |
602 | { | |
603 | MS1_INSN_ORI, "ori", "ori", 32, | |
604 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
605 | }, | |
606 | /* xor $frdrrr,$frsr1,$frsr2 */ | |
607 | { | |
608 | MS1_INSN_XOR, "xor", "xor", 32, | |
609 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
610 | }, | |
611 | /* xori $frdr,$frsr1,#$imm16z */ | |
612 | { | |
613 | MS1_INSN_XORI, "xori", "xori", 32, | |
614 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
615 | }, | |
616 | /* nand $frdrrr,$frsr1,$frsr2 */ | |
617 | { | |
618 | MS1_INSN_NAND, "nand", "nand", 32, | |
619 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
620 | }, | |
621 | /* nandi $frdr,$frsr1,#$imm16z */ | |
622 | { | |
623 | MS1_INSN_NANDI, "nandi", "nandi", 32, | |
624 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
625 | }, | |
626 | /* nor $frdrrr,$frsr1,$frsr2 */ | |
627 | { | |
628 | MS1_INSN_NOR, "nor", "nor", 32, | |
629 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
630 | }, | |
631 | /* nori $frdr,$frsr1,#$imm16z */ | |
632 | { | |
633 | MS1_INSN_NORI, "nori", "nori", 32, | |
634 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
635 | }, | |
636 | /* xnor $frdrrr,$frsr1,$frsr2 */ | |
637 | { | |
638 | MS1_INSN_XNOR, "xnor", "xnor", 32, | |
639 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
640 | }, | |
641 | /* xnori $frdr,$frsr1,#$imm16z */ | |
642 | { | |
643 | MS1_INSN_XNORI, "xnori", "xnori", 32, | |
644 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
645 | }, | |
646 | /* ldui $frdr,#$imm16z */ | |
647 | { | |
648 | MS1_INSN_LDUI, "ldui", "ldui", 32, | |
649 | { 0|A(USES_FRDR)|A(AL_INSN), { (1<<MACH_BASE) } } | |
650 | }, | |
651 | /* lsl $frdrrr,$frsr1,$frsr2 */ | |
652 | { | |
653 | MS1_INSN_LSL, "lsl", "lsl", 32, | |
654 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } } | |
655 | }, | |
656 | /* lsli $frdr,$frsr1,#$imm16 */ | |
657 | { | |
658 | MS1_INSN_LSLI, "lsli", "lsli", 32, | |
659 | { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } } | |
660 | }, | |
661 | /* lsr $frdrrr,$frsr1,$frsr2 */ | |
662 | { | |
663 | MS1_INSN_LSR, "lsr", "lsr", 32, | |
664 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } } | |
665 | }, | |
666 | /* lsri $frdr,$frsr1,#$imm16 */ | |
667 | { | |
668 | MS1_INSN_LSRI, "lsri", "lsri", 32, | |
669 | { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } } | |
670 | }, | |
671 | /* asr $frdrrr,$frsr1,$frsr2 */ | |
672 | { | |
673 | MS1_INSN_ASR, "asr", "asr", 32, | |
674 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { (1<<MACH_BASE) } } | |
675 | }, | |
676 | /* asri $frdr,$frsr1,#$imm16 */ | |
677 | { | |
678 | MS1_INSN_ASRI, "asri", "asri", 32, | |
679 | { 0|A(USES_FRSR1)|A(USES_FRDR), { (1<<MACH_BASE) } } | |
680 | }, | |
681 | /* brlt $frsr1,$frsr2,$imm16o */ | |
682 | { | |
683 | MS1_INSN_BRLT, "brlt", "brlt", 32, | |
684 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } | |
685 | }, | |
686 | /* brle $frsr1,$frsr2,$imm16o */ | |
687 | { | |
688 | MS1_INSN_BRLE, "brle", "brle", 32, | |
689 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } | |
690 | }, | |
691 | /* breq $frsr1,$frsr2,$imm16o */ | |
692 | { | |
693 | MS1_INSN_BREQ, "breq", "breq", 32, | |
694 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } | |
695 | }, | |
696 | /* brne $frsr1,$frsr2,$imm16o */ | |
697 | { | |
698 | MS1_INSN_BRNE, "brne", "brne", 32, | |
699 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_BASE) } } | |
700 | }, | |
701 | /* jmp $imm16o */ | |
702 | { | |
703 | MS1_INSN_JMP, "jmp", "jmp", 32, | |
704 | { 0|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } | |
705 | }, | |
706 | /* jal $frdrrr,$frsr1 */ | |
707 | { | |
708 | MS1_INSN_JAL, "jal", "jal", 32, | |
709 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } | |
710 | }, | |
711 | /* dbnz $frsr1,$imm16o */ | |
712 | { | |
713 | MS1_INSN_DBNZ, "dbnz", "dbnz", 32, | |
714 | { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { (1<<MACH_MS1_003) } } | |
715 | }, | |
716 | /* ei */ | |
717 | { | |
718 | MS1_INSN_EI, "ei", "ei", 32, | |
719 | { 0, { (1<<MACH_BASE) } } | |
720 | }, | |
721 | /* di */ | |
722 | { | |
723 | MS1_INSN_DI, "di", "di", 32, | |
724 | { 0, { (1<<MACH_BASE) } } | |
725 | }, | |
726 | /* si $frdrrr */ | |
727 | { | |
728 | MS1_INSN_SI, "si", "si", 32, | |
729 | { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } | |
730 | }, | |
731 | /* reti $frsr1 */ | |
732 | { | |
733 | MS1_INSN_RETI, "reti", "reti", 32, | |
734 | { 0|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { (1<<MACH_BASE) } } | |
735 | }, | |
736 | /* ldw $frdr,$frsr1,#$imm16 */ | |
737 | { | |
738 | MS1_INSN_LDW, "ldw", "ldw", 32, | |
739 | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { (1<<MACH_BASE) } } | |
740 | }, | |
741 | /* stw $frsr2,$frsr1,#$imm16 */ | |
742 | { | |
743 | MS1_INSN_STW, "stw", "stw", 32, | |
744 | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { (1<<MACH_BASE) } } | |
745 | }, | |
746 | /* break */ | |
747 | { | |
748 | MS1_INSN_BREAK, "break", "break", 32, | |
749 | { 0, { (1<<MACH_BASE) } } | |
750 | }, | |
751 | /* iflush */ | |
752 | { | |
753 | MS1_INSN_IFLUSH, "iflush", "iflush", 32, | |
754 | { 0, { (1<<MACH_MS1_003) } } | |
755 | }, | |
756 | /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */ | |
757 | { | |
758 | MS1_INSN_LDCTXT, "ldctxt", "ldctxt", 32, | |
759 | { 0, { (1<<MACH_BASE) } } | |
760 | }, | |
761 | /* ldfb $frsr1,$frsr2,#$imm16z */ | |
762 | { | |
763 | MS1_INSN_LDFB, "ldfb", "ldfb", 32, | |
764 | { 0, { (1<<MACH_BASE) } } | |
765 | }, | |
766 | /* stfb $frsr1,$frsr2,#$imm16z */ | |
767 | { | |
768 | MS1_INSN_STFB, "stfb", "stfb", 32, | |
769 | { 0, { (1<<MACH_BASE) } } | |
770 | }, | |
771 | /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ | |
772 | { | |
773 | MS1_INSN_FBCB, "fbcb", "fbcb", 32, | |
774 | { 0, { (1<<MACH_BASE) } } | |
775 | }, | |
776 | /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ | |
777 | { | |
778 | MS1_INSN_MFBCB, "mfbcb", "mfbcb", 32, | |
779 | { 0, { (1<<MACH_BASE) } } | |
780 | }, | |
781 | /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
782 | { | |
783 | MS1_INSN_FBCCI, "fbcci", "fbcci", 32, | |
784 | { 0, { (1<<MACH_BASE) } } | |
785 | }, | |
786 | /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
787 | { | |
788 | MS1_INSN_FBRCI, "fbrci", "fbrci", 32, | |
789 | { 0, { (1<<MACH_BASE) } } | |
790 | }, | |
791 | /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
792 | { | |
793 | MS1_INSN_FBCRI, "fbcri", "fbcri", 32, | |
794 | { 0, { (1<<MACH_BASE) } } | |
795 | }, | |
796 | /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
797 | { | |
798 | MS1_INSN_FBRRI, "fbrri", "fbrri", 32, | |
799 | { 0, { (1<<MACH_BASE) } } | |
800 | }, | |
801 | /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
802 | { | |
803 | MS1_INSN_MFBCCI, "mfbcci", "mfbcci", 32, | |
804 | { 0, { (1<<MACH_BASE) } } | |
805 | }, | |
806 | /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
807 | { | |
808 | MS1_INSN_MFBRCI, "mfbrci", "mfbrci", 32, | |
809 | { 0, { (1<<MACH_BASE) } } | |
810 | }, | |
811 | /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
812 | { | |
813 | MS1_INSN_MFBCRI, "mfbcri", "mfbcri", 32, | |
814 | { 0, { (1<<MACH_BASE) } } | |
815 | }, | |
816 | /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ | |
817 | { | |
818 | MS1_INSN_MFBRRI, "mfbrri", "mfbrri", 32, | |
819 | { 0, { (1<<MACH_BASE) } } | |
820 | }, | |
821 | /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ | |
822 | { | |
823 | MS1_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32, | |
824 | { 0, { (1<<MACH_BASE) } } | |
825 | }, | |
826 | /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ | |
827 | { | |
828 | MS1_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32, | |
829 | { 0, { (1<<MACH_BASE) } } | |
830 | }, | |
831 | /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ | |
832 | { | |
833 | MS1_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32, | |
834 | { 0, { (1<<MACH_BASE) } } | |
835 | }, | |
836 | /* cbcast #$mask,#$rc2,#$ctxdisp */ | |
837 | { | |
838 | MS1_INSN_CBCAST, "cbcast", "cbcast", 32, | |
839 | { 0, { (1<<MACH_BASE) } } | |
840 | }, | |
841 | /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */ | |
842 | { | |
843 | MS1_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32, | |
844 | { 0, { (1<<MACH_BASE) } } | |
845 | }, | |
846 | /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */ | |
847 | { | |
848 | MS1_INSN_WFBI, "wfbi", "wfbi", 32, | |
849 | { 0, { (1<<MACH_BASE) } } | |
850 | }, | |
851 | /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */ | |
852 | { | |
853 | MS1_INSN_WFB, "wfb", "wfb", 32, | |
854 | { 0, { (1<<MACH_BASE) } } | |
855 | }, | |
856 | /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ | |
857 | { | |
858 | MS1_INSN_RCRISC, "rcrisc", "rcrisc", 32, | |
859 | { 0, { (1<<MACH_BASE) } } | |
860 | }, | |
861 | /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ | |
862 | { | |
863 | MS1_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32, | |
864 | { 0, { (1<<MACH_BASE) } } | |
865 | }, | |
866 | /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */ | |
867 | { | |
868 | MS1_INSN_RCXMODE, "rcxmode", "rcxmode", 32, | |
869 | { 0, { (1<<MACH_BASE) } } | |
870 | }, | |
871 | /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */ | |
872 | { | |
873 | MS1_INSN_INTERLEAVER, "interleaver", "intlvr", 32, | |
874 | { 0, { (1<<MACH_BASE) } } | |
875 | }, | |
876 | /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ | |
877 | { | |
878 | MS1_INSN_WFBINC, "wfbinc", "wfbinc", 32, | |
879 | { 0, { (1<<MACH_MS1_003) } } | |
880 | }, | |
881 | /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ | |
882 | { | |
883 | MS1_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32, | |
884 | { 0, { (1<<MACH_MS1_003) } } | |
885 | }, | |
886 | /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ | |
887 | { | |
888 | MS1_INSN_WFBINCR, "wfbincr", "wfbincr", 32, | |
889 | { 0, { (1<<MACH_MS1_003) } } | |
890 | }, | |
891 | /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ | |
892 | { | |
893 | MS1_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32, | |
894 | { 0, { (1<<MACH_MS1_003) } } | |
895 | }, | |
896 | /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ | |
897 | { | |
898 | MS1_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32, | |
899 | { 0, { (1<<MACH_MS1_003) } } | |
900 | }, | |
901 | /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ | |
902 | { | |
903 | MS1_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32, | |
904 | { 0, { (1<<MACH_MS1_003) } } | |
905 | }, | |
906 | /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ | |
907 | { | |
908 | MS1_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32, | |
909 | { 0, { (1<<MACH_MS1_003) } } | |
910 | }, | |
911 | /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ | |
912 | { | |
913 | MS1_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32, | |
914 | { 0, { (1<<MACH_MS1_003) } } | |
915 | }, | |
916 | }; | |
917 | ||
918 | #undef OP | |
919 | #undef A | |
920 | ||
921 | /* Initialize anything needed to be done once, before any cpu_open call. */ | |
ac188222 DB |
922 | |
923 | static void | |
47b0e7ad | 924 | init_tables (void) |
ac188222 DB |
925 | { |
926 | } | |
927 | ||
47b0e7ad NC |
928 | static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); |
929 | static void build_hw_table (CGEN_CPU_TABLE *); | |
930 | static void build_ifield_table (CGEN_CPU_TABLE *); | |
931 | static void build_operand_table (CGEN_CPU_TABLE *); | |
932 | static void build_insn_table (CGEN_CPU_TABLE *); | |
933 | static void ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *); | |
ac188222 DB |
934 | |
935 | /* Subroutine of ms1_cgen_cpu_open to look up a mach via its bfd name. */ | |
936 | ||
937 | static const CGEN_MACH * | |
47b0e7ad | 938 | lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) |
ac188222 DB |
939 | { |
940 | while (table->name) | |
941 | { | |
942 | if (strcmp (name, table->bfd_name) == 0) | |
943 | return table; | |
944 | ++table; | |
945 | } | |
946 | abort (); | |
947 | } | |
948 | ||
949 | /* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ | |
950 | ||
951 | static void | |
47b0e7ad | 952 | build_hw_table (CGEN_CPU_TABLE *cd) |
ac188222 DB |
953 | { |
954 | int i; | |
955 | int machs = cd->machs; | |
956 | const CGEN_HW_ENTRY *init = & ms1_cgen_hw_table[0]; | |
957 | /* MAX_HW is only an upper bound on the number of selected entries. | |
958 | However each entry is indexed by it's enum so there can be holes in | |
959 | the table. */ | |
960 | const CGEN_HW_ENTRY **selected = | |
961 | (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
962 | ||
963 | cd->hw_table.init_entries = init; | |
964 | cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); | |
965 | memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
966 | /* ??? For now we just use machs to determine which ones we want. */ | |
967 | for (i = 0; init[i].name != NULL; ++i) | |
968 | if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) | |
969 | & machs) | |
970 | selected[init[i].type] = &init[i]; | |
971 | cd->hw_table.entries = selected; | |
972 | cd->hw_table.num_entries = MAX_HW; | |
973 | } | |
974 | ||
975 | /* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ | |
976 | ||
977 | static void | |
47b0e7ad | 978 | build_ifield_table (CGEN_CPU_TABLE *cd) |
ac188222 DB |
979 | { |
980 | cd->ifld_table = & ms1_cgen_ifld_table[0]; | |
981 | } | |
982 | ||
983 | /* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ | |
984 | ||
985 | static void | |
47b0e7ad | 986 | build_operand_table (CGEN_CPU_TABLE *cd) |
ac188222 DB |
987 | { |
988 | int i; | |
989 | int machs = cd->machs; | |
990 | const CGEN_OPERAND *init = & ms1_cgen_operand_table[0]; | |
991 | /* MAX_OPERANDS is only an upper bound on the number of selected entries. | |
992 | However each entry is indexed by it's enum so there can be holes in | |
993 | the table. */ | |
47b0e7ad | 994 | const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); |
ac188222 DB |
995 | |
996 | cd->operand_table.init_entries = init; | |
997 | cd->operand_table.entry_size = sizeof (CGEN_OPERAND); | |
998 | memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); | |
999 | /* ??? For now we just use mach to determine which ones we want. */ | |
1000 | for (i = 0; init[i].name != NULL; ++i) | |
1001 | if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) | |
1002 | & machs) | |
1003 | selected[init[i].type] = &init[i]; | |
1004 | cd->operand_table.entries = selected; | |
1005 | cd->operand_table.num_entries = MAX_OPERANDS; | |
1006 | } | |
1007 | ||
1008 | /* Subroutine of ms1_cgen_cpu_open to build the hardware table. | |
1009 | ??? This could leave out insns not supported by the specified mach/isa, | |
1010 | but that would cause errors like "foo only supported by bar" to become | |
1011 | "unknown insn", so for now we include all insns and require the app to | |
1012 | do the checking later. | |
1013 | ??? On the other hand, parsing of such insns may require their hardware or | |
1014 | operand elements to be in the table [which they mightn't be]. */ | |
1015 | ||
1016 | static void | |
47b0e7ad | 1017 | build_insn_table (CGEN_CPU_TABLE *cd) |
ac188222 DB |
1018 | { |
1019 | int i; | |
1020 | const CGEN_IBASE *ib = & ms1_cgen_insn_table[0]; | |
47b0e7ad | 1021 | CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); |
ac188222 DB |
1022 | |
1023 | memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); | |
1024 | for (i = 0; i < MAX_INSNS; ++i) | |
1025 | insns[i].base = &ib[i]; | |
1026 | cd->insn_table.init_entries = insns; | |
1027 | cd->insn_table.entry_size = sizeof (CGEN_IBASE); | |
1028 | cd->insn_table.num_init_entries = MAX_INSNS; | |
1029 | } | |
1030 | ||
1031 | /* Subroutine of ms1_cgen_cpu_open to rebuild the tables. */ | |
1032 | ||
1033 | static void | |
47b0e7ad | 1034 | ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) |
ac188222 DB |
1035 | { |
1036 | int i; | |
1037 | unsigned int isas = cd->isas; | |
1038 | unsigned int machs = cd->machs; | |
1039 | ||
1040 | cd->int_insn_p = CGEN_INT_INSN_P; | |
1041 | ||
1042 | /* Data derived from the isa spec. */ | |
1043 | #define UNSET (CGEN_SIZE_UNKNOWN + 1) | |
1044 | cd->default_insn_bitsize = UNSET; | |
1045 | cd->base_insn_bitsize = UNSET; | |
47b0e7ad | 1046 | cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ |
ac188222 DB |
1047 | cd->max_insn_bitsize = 0; |
1048 | for (i = 0; i < MAX_ISAS; ++i) | |
1049 | if (((1 << i) & isas) != 0) | |
1050 | { | |
1051 | const CGEN_ISA *isa = & ms1_cgen_isa_table[i]; | |
1052 | ||
1053 | /* Default insn sizes of all selected isas must be | |
1054 | equal or we set the result to 0, meaning "unknown". */ | |
1055 | if (cd->default_insn_bitsize == UNSET) | |
1056 | cd->default_insn_bitsize = isa->default_insn_bitsize; | |
1057 | else if (isa->default_insn_bitsize == cd->default_insn_bitsize) | |
47b0e7ad | 1058 | ; /* This is ok. */ |
ac188222 DB |
1059 | else |
1060 | cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
1061 | ||
1062 | /* Base insn sizes of all selected isas must be equal | |
1063 | or we set the result to 0, meaning "unknown". */ | |
1064 | if (cd->base_insn_bitsize == UNSET) | |
1065 | cd->base_insn_bitsize = isa->base_insn_bitsize; | |
1066 | else if (isa->base_insn_bitsize == cd->base_insn_bitsize) | |
47b0e7ad | 1067 | ; /* This is ok. */ |
ac188222 DB |
1068 | else |
1069 | cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
1070 | ||
1071 | /* Set min,max insn sizes. */ | |
1072 | if (isa->min_insn_bitsize < cd->min_insn_bitsize) | |
1073 | cd->min_insn_bitsize = isa->min_insn_bitsize; | |
1074 | if (isa->max_insn_bitsize > cd->max_insn_bitsize) | |
1075 | cd->max_insn_bitsize = isa->max_insn_bitsize; | |
1076 | } | |
1077 | ||
1078 | /* Data derived from the mach spec. */ | |
1079 | for (i = 0; i < MAX_MACHS; ++i) | |
1080 | if (((1 << i) & machs) != 0) | |
1081 | { | |
1082 | const CGEN_MACH *mach = & ms1_cgen_mach_table[i]; | |
1083 | ||
1084 | if (mach->insn_chunk_bitsize != 0) | |
1085 | { | |
1086 | if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) | |
1087 | { | |
1088 | fprintf (stderr, "ms1_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", | |
1089 | cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); | |
1090 | abort (); | |
1091 | } | |
1092 | ||
1093 | cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | /* Determine which hw elements are used by MACH. */ | |
1098 | build_hw_table (cd); | |
1099 | ||
1100 | /* Build the ifield table. */ | |
1101 | build_ifield_table (cd); | |
1102 | ||
1103 | /* Determine which operands are used by MACH/ISA. */ | |
1104 | build_operand_table (cd); | |
1105 | ||
1106 | /* Build the instruction table. */ | |
1107 | build_insn_table (cd); | |
1108 | } | |
1109 | ||
1110 | /* Initialize a cpu table and return a descriptor. | |
1111 | It's much like opening a file, and must be the first function called. | |
1112 | The arguments are a set of (type/value) pairs, terminated with | |
1113 | CGEN_CPU_OPEN_END. | |
1114 | ||
1115 | Currently supported values: | |
1116 | CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr | |
1117 | CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr | |
1118 | CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name | |
1119 | CGEN_CPU_OPEN_ENDIAN: specify endian choice | |
1120 | CGEN_CPU_OPEN_END: terminates arguments | |
1121 | ||
1122 | ??? Simultaneous multiple isas might not make sense, but it's not (yet) | |
1123 | precluded. | |
1124 | ||
1125 | ??? We only support ISO C stdargs here, not K&R. | |
1126 | Laziness, plus experiment to see if anything requires K&R - eventually | |
1127 | K&R will no longer be supported - e.g. GDB is currently trying this. */ | |
1128 | ||
1129 | CGEN_CPU_DESC | |
1130 | ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) | |
1131 | { | |
1132 | CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); | |
1133 | static int init_p; | |
1134 | unsigned int isas = 0; /* 0 = "unspecified" */ | |
1135 | unsigned int machs = 0; /* 0 = "unspecified" */ | |
1136 | enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; | |
1137 | va_list ap; | |
1138 | ||
1139 | if (! init_p) | |
1140 | { | |
1141 | init_tables (); | |
1142 | init_p = 1; | |
1143 | } | |
1144 | ||
1145 | memset (cd, 0, sizeof (*cd)); | |
1146 | ||
1147 | va_start (ap, arg_type); | |
1148 | while (arg_type != CGEN_CPU_OPEN_END) | |
1149 | { | |
1150 | switch (arg_type) | |
1151 | { | |
1152 | case CGEN_CPU_OPEN_ISAS : | |
1153 | isas = va_arg (ap, unsigned int); | |
1154 | break; | |
1155 | case CGEN_CPU_OPEN_MACHS : | |
1156 | machs = va_arg (ap, unsigned int); | |
1157 | break; | |
1158 | case CGEN_CPU_OPEN_BFDMACH : | |
1159 | { | |
1160 | const char *name = va_arg (ap, const char *); | |
1161 | const CGEN_MACH *mach = | |
1162 | lookup_mach_via_bfd_name (ms1_cgen_mach_table, name); | |
1163 | ||
1164 | machs |= 1 << mach->num; | |
1165 | break; | |
1166 | } | |
1167 | case CGEN_CPU_OPEN_ENDIAN : | |
1168 | endian = va_arg (ap, enum cgen_endian); | |
1169 | break; | |
1170 | default : | |
1171 | fprintf (stderr, "ms1_cgen_cpu_open: unsupported argument `%d'\n", | |
1172 | arg_type); | |
1173 | abort (); /* ??? return NULL? */ | |
1174 | } | |
1175 | arg_type = va_arg (ap, enum cgen_cpu_open_arg); | |
1176 | } | |
1177 | va_end (ap); | |
1178 | ||
47b0e7ad | 1179 | /* Mach unspecified means "all". */ |
ac188222 DB |
1180 | if (machs == 0) |
1181 | machs = (1 << MAX_MACHS) - 1; | |
47b0e7ad | 1182 | /* Base mach is always selected. */ |
ac188222 | 1183 | machs |= 1; |
47b0e7ad | 1184 | /* ISA unspecified means "all". */ |
ac188222 DB |
1185 | if (isas == 0) |
1186 | isas = (1 << MAX_ISAS) - 1; | |
1187 | if (endian == CGEN_ENDIAN_UNKNOWN) | |
1188 | { | |
1189 | /* ??? If target has only one, could have a default. */ | |
1190 | fprintf (stderr, "ms1_cgen_cpu_open: no endianness specified\n"); | |
1191 | abort (); | |
1192 | } | |
1193 | ||
1194 | cd->isas = isas; | |
1195 | cd->machs = machs; | |
1196 | cd->endian = endian; | |
1197 | /* FIXME: for the sparc case we can determine insn-endianness statically. | |
1198 | The worry here is where both data and insn endian can be independently | |
1199 | chosen, in which case this function will need another argument. | |
1200 | Actually, will want to allow for more arguments in the future anyway. */ | |
1201 | cd->insn_endian = endian; | |
1202 | ||
1203 | /* Table (re)builder. */ | |
1204 | cd->rebuild_tables = ms1_cgen_rebuild_tables; | |
1205 | ms1_cgen_rebuild_tables (cd); | |
1206 | ||
1207 | /* Default to not allowing signed overflow. */ | |
1208 | cd->signed_overflow_ok_p = 0; | |
1209 | ||
1210 | return (CGEN_CPU_DESC) cd; | |
1211 | } | |
1212 | ||
1213 | /* Cover fn to ms1_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. | |
1214 | MACH_NAME is the bfd name of the mach. */ | |
1215 | ||
1216 | CGEN_CPU_DESC | |
47b0e7ad | 1217 | ms1_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) |
ac188222 DB |
1218 | { |
1219 | return ms1_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
1220 | CGEN_CPU_OPEN_ENDIAN, endian, | |
1221 | CGEN_CPU_OPEN_END); | |
1222 | } | |
1223 | ||
1224 | /* Close a cpu table. | |
1225 | ??? This can live in a machine independent file, but there's currently | |
1226 | no place to put this file (there's no libcgen). libopcodes is the wrong | |
1227 | place as some simulator ports use this but they don't use libopcodes. */ | |
1228 | ||
1229 | void | |
47b0e7ad | 1230 | ms1_cgen_cpu_close (CGEN_CPU_DESC cd) |
ac188222 DB |
1231 | { |
1232 | unsigned int i; | |
1233 | const CGEN_INSN *insns; | |
1234 | ||
1235 | if (cd->macro_insn_table.init_entries) | |
1236 | { | |
1237 | insns = cd->macro_insn_table.init_entries; | |
1238 | for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) | |
47b0e7ad NC |
1239 | if (CGEN_INSN_RX ((insns))) |
1240 | regfree (CGEN_INSN_RX (insns)); | |
ac188222 DB |
1241 | } |
1242 | ||
1243 | if (cd->insn_table.init_entries) | |
1244 | { | |
1245 | insns = cd->insn_table.init_entries; | |
1246 | for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) | |
47b0e7ad NC |
1247 | if (CGEN_INSN_RX (insns)) |
1248 | regfree (CGEN_INSN_RX (insns)); | |
1249 | } | |
ac188222 DB |
1250 | |
1251 | if (cd->macro_insn_table.init_entries) | |
1252 | free ((CGEN_INSN *) cd->macro_insn_table.init_entries); | |
1253 | ||
1254 | if (cd->insn_table.init_entries) | |
1255 | free ((CGEN_INSN *) cd->insn_table.init_entries); | |
1256 | ||
1257 | if (cd->hw_table.entries) | |
1258 | free ((CGEN_HW_ENTRY *) cd->hw_table.entries); | |
1259 | ||
1260 | if (cd->operand_table.entries) | |
1261 | free ((CGEN_HW_ENTRY *) cd->operand_table.entries); | |
1262 | ||
1263 | free (cd); | |
1264 | } | |
1265 |