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ac188222 DB |
1 | /* Instruction opcode header for ms1. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright 1996-2005 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifndef MS1_OPC_H | |
26 | #define MS1_OPC_H | |
27 | ||
28 | /* -- opc.h */ | |
29 | ||
30 | /* Check applicability of instructions against machines. */ | |
31 | #define CGEN_VALIDATE_INSN_SUPPORTED | |
32 | ||
33 | /* Allows reason codes to be output when assembler errors occur. */ | |
34 | #define CGEN_VERBOSE_ASSEMBLER_ERRORS | |
35 | ||
36 | /* Override disassembly hashing - there are variable bits in the top | |
37 | byte of these instructions. */ | |
38 | #define CGEN_DIS_HASH_SIZE 8 | |
39 | #define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) | |
40 | ||
41 | #define CGEN_ASM_HASH_SIZE 127 | |
42 | #define CGEN_ASM_HASH(insn) ms1_asm_hash (insn) | |
43 | ||
44 | extern unsigned int ms1_asm_hash (const char *); | |
45 | ||
46 | extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); | |
47 | ||
48 | \f | |
49 | /* -- opc.c */ | |
50 | /* Enum declaration for ms1 instruction types. */ | |
51 | typedef enum cgen_insn_type { | |
52 | MS1_INSN_INVALID, MS1_INSN_ADD, MS1_INSN_ADDU, MS1_INSN_ADDI | |
53 | , MS1_INSN_ADDUI, MS1_INSN_SUB, MS1_INSN_SUBU, MS1_INSN_SUBI | |
54 | , MS1_INSN_SUBUI, MS1_INSN_MUL, MS1_INSN_MULI, MS1_INSN_AND | |
55 | , MS1_INSN_ANDI, MS1_INSN_OR, MS1_INSN_NOP, MS1_INSN_ORI | |
56 | , MS1_INSN_XOR, MS1_INSN_XORI, MS1_INSN_NAND, MS1_INSN_NANDI | |
57 | , MS1_INSN_NOR, MS1_INSN_NORI, MS1_INSN_XNOR, MS1_INSN_XNORI | |
58 | , MS1_INSN_LDUI, MS1_INSN_LSL, MS1_INSN_LSLI, MS1_INSN_LSR | |
59 | , MS1_INSN_LSRI, MS1_INSN_ASR, MS1_INSN_ASRI, MS1_INSN_BRLT | |
60 | , MS1_INSN_BRLE, MS1_INSN_BREQ, MS1_INSN_BRNE, MS1_INSN_JMP | |
61 | , MS1_INSN_JAL, MS1_INSN_DBNZ, MS1_INSN_EI, MS1_INSN_DI | |
62 | , MS1_INSN_SI, MS1_INSN_RETI, MS1_INSN_LDW, MS1_INSN_STW | |
63 | , MS1_INSN_BREAK, MS1_INSN_IFLUSH, MS1_INSN_LDCTXT, MS1_INSN_LDFB | |
64 | , MS1_INSN_STFB, MS1_INSN_FBCB, MS1_INSN_MFBCB, MS1_INSN_FBCCI | |
65 | , MS1_INSN_FBRCI, MS1_INSN_FBCRI, MS1_INSN_FBRRI, MS1_INSN_MFBCCI | |
66 | , MS1_INSN_MFBRCI, MS1_INSN_MFBCRI, MS1_INSN_MFBRRI, MS1_INSN_FBCBDR | |
67 | , MS1_INSN_RCFBCB, MS1_INSN_MRCFBCB, MS1_INSN_CBCAST, MS1_INSN_DUPCBCAST | |
68 | , MS1_INSN_WFBI, MS1_INSN_WFB, MS1_INSN_RCRISC, MS1_INSN_FBCBINC | |
69 | , MS1_INSN_RCXMODE, MS1_INSN_INTERLEAVER, MS1_INSN_WFBINC, MS1_INSN_MWFBINC | |
70 | , MS1_INSN_WFBINCR, MS1_INSN_MWFBINCR, MS1_INSN_FBCBINCS, MS1_INSN_MFBCBINCS | |
71 | , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS | |
72 | } CGEN_INSN_TYPE; | |
73 | ||
74 | /* Index of `invalid' insn place holder. */ | |
75 | #define CGEN_INSN_INVALID MS1_INSN_INVALID | |
76 | ||
77 | /* Total number of insns in table. */ | |
78 | #define MAX_INSNS ((int) MS1_INSN_MFBCBINCRS + 1) | |
79 | ||
80 | /* This struct records data prior to insertion or after extraction. */ | |
81 | struct cgen_fields | |
82 | { | |
83 | int length; | |
84 | long f_nil; | |
85 | long f_anyof; | |
86 | long f_msys; | |
87 | long f_opc; | |
88 | long f_imm; | |
89 | long f_uu24; | |
90 | long f_sr1; | |
91 | long f_sr2; | |
92 | long f_dr; | |
93 | long f_drrr; | |
94 | long f_imm16u; | |
95 | long f_imm16s; | |
96 | long f_imm16a; | |
97 | long f_uu4a; | |
98 | long f_uu4b; | |
99 | long f_uu12; | |
100 | long f_uu16; | |
101 | long f_msopc; | |
102 | long f_uu_26_25; | |
103 | long f_mask; | |
104 | long f_bankaddr; | |
105 | long f_rda; | |
106 | long f_uu_2_25; | |
107 | long f_rbbc; | |
108 | long f_perm; | |
109 | long f_mode; | |
110 | long f_uu_1_24; | |
111 | long f_wr; | |
112 | long f_fbincr; | |
113 | long f_uu_2_23; | |
114 | long f_xmode; | |
115 | long f_a23; | |
116 | long f_mask1; | |
117 | long f_cr; | |
118 | long f_type; | |
119 | long f_incamt; | |
120 | long f_cbs; | |
121 | long f_uu_1_19; | |
122 | long f_ball; | |
123 | long f_colnum; | |
124 | long f_brc; | |
125 | long f_incr; | |
126 | long f_fbdisp; | |
127 | long f_uu_4_15; | |
128 | long f_length; | |
129 | long f_uu_1_15; | |
130 | long f_rc; | |
131 | long f_rcnum; | |
132 | long f_rownum; | |
133 | long f_cbx; | |
134 | long f_id; | |
135 | long f_size; | |
136 | long f_rownum1; | |
137 | long f_uu_3_11; | |
138 | long f_rc1; | |
139 | long f_ccb; | |
140 | long f_cbrb; | |
141 | long f_cdb; | |
142 | long f_rownum2; | |
143 | long f_cell; | |
144 | long f_uu_3_9; | |
145 | long f_contnum; | |
146 | long f_uu_1_6; | |
147 | long f_dup; | |
148 | long f_rc2; | |
149 | long f_ctxdisp; | |
150 | long f_msysfrsr2; | |
151 | long f_brc2; | |
152 | long f_ball2; | |
153 | }; | |
154 | ||
155 | #define CGEN_INIT_PARSE(od) \ | |
156 | {\ | |
157 | } | |
158 | #define CGEN_INIT_INSERT(od) \ | |
159 | {\ | |
160 | } | |
161 | #define CGEN_INIT_EXTRACT(od) \ | |
162 | {\ | |
163 | } | |
164 | #define CGEN_INIT_PRINT(od) \ | |
165 | {\ | |
166 | } | |
167 | ||
168 | ||
169 | #endif /* MS1_OPC_H */ |