* infcall.c (call_function_by_hand): Check for function pointer
[deliverable/binutils-gdb.git] / opcodes / mt-desc.h
CommitLineData
d031aafb 1/* CPU data header for mt.
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2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996-2005 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2151 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
d031aafb
NS
25#ifndef MT_CPU_H
26#define MT_CPU_H
ac188222 27
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28#include "opcode/cgen-bitset.h"
29
d031aafb 30#define CGEN_ARCH mt
ac188222 31
d031aafb 32/* Given symbol S, return mt_cgen_<S>. */
ac188222 33#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
d031aafb 34#define CGEN_SYM(s) mt##_cgen_##s
ac188222 35#else
d031aafb 36#define CGEN_SYM(s) mt/**/_cgen_/**/s
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37#endif
38
39
40/* Selected cpu families. */
41#define HAVE_CPU_MS1BF
42#define HAVE_CPU_MS1_003BF
6f84a2a6 43#define HAVE_CPU_MS2BF
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44
45#define CGEN_INSN_LSB0_P 1
46
47/* Minimum size of any insn (in bytes). */
48#define CGEN_MIN_INSN_SIZE 4
49
50/* Maximum size of any insn (in bytes). */
51#define CGEN_MAX_INSN_SIZE 4
52
53#define CGEN_INT_INSN_P 1
54
55/* Maximum number of syntax elements in an instruction. */
56#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 40
57
58/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
59 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
60 we can't hash on everything up to the space. */
61#define CGEN_MNEMONIC_OPERANDS
62
63/* Maximum number of fields in an instruction. */
64#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 14
65
66/* Enums. */
67
68/* Enum declaration for msys enums. */
69typedef enum insn_msys {
70 MSYS_NO, MSYS_YES
71} INSN_MSYS;
72
73/* Enum declaration for opc enums. */
74typedef enum insn_opc {
75 OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3
76 , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10
77 , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
78 , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
79 , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
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80 , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32
81 , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50
82 , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53
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83} INSN_OPC;
84
85/* Enum declaration for msopc enums. */
86typedef enum insn_msopc {
87 MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB
88 , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI
89 , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI
90 , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB
91 , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB
92 , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR
93 , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR
94 , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS
95} INSN_MSOPC;
96
97/* Enum declaration for imm enums. */
98typedef enum insn_imm {
99 IMM_NO, IMM_YES
100} INSN_IMM;
101
102/* Enum declaration for . */
103typedef enum msys_syms {
104 H_NIL_DUP = 1, H_NIL_XX = 0
105} MSYS_SYMS;
106
107/* Attributes. */
108
109/* Enum declaration for machine type selection. */
110typedef enum mach_attr {
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111 MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2
112 , MACH_MAX
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113} MACH_ATTR;
114
115/* Enum declaration for instruction set selection. */
116typedef enum isa_attr {
d031aafb 117 ISA_MT, ISA_MAX
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118} ISA_ATTR;
119
120/* Number of architecture variants. */
121#define MAX_ISAS 1
122#define MAX_MACHS ((int) MACH_MAX)
123
124/* Ifield support. */
125
126/* Ifield attribute indices. */
127
128/* Enum declaration for cgen_ifld attrs. */
129typedef enum cgen_ifld_attr {
130 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
131 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
132 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
133} CGEN_IFLD_ATTR;
134
135/* Number of non-boolean elements in cgen_ifld_attr. */
136#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
137
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138/* cgen_ifld attribute accessor macros. */
139#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
140#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
141#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
142#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
143#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
144#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
145#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
146
d031aafb 147/* Enum declaration for mt ifield types. */
ac188222 148typedef enum ifield_type {
d031aafb
NS
149 MT_F_NIL, MT_F_ANYOF, MT_F_MSYS, MT_F_OPC
150 , MT_F_IMM, MT_F_UU24, MT_F_SR1, MT_F_SR2
151 , MT_F_DR, MT_F_DRRR, MT_F_IMM16U, MT_F_IMM16S
152 , MT_F_IMM16A, MT_F_UU4A, MT_F_UU4B, MT_F_UU12
153 , MT_F_UU8, MT_F_UU16, MT_F_UU1, MT_F_MSOPC
154 , MT_F_UU_26_25, MT_F_MASK, MT_F_BANKADDR, MT_F_RDA
155 , MT_F_UU_2_25, MT_F_RBBC, MT_F_PERM, MT_F_MODE
156 , MT_F_UU_1_24, MT_F_WR, MT_F_FBINCR, MT_F_UU_2_23
157 , MT_F_XMODE, MT_F_A23, MT_F_MASK1, MT_F_CR
158 , MT_F_TYPE, MT_F_INCAMT, MT_F_CBS, MT_F_UU_1_19
159 , MT_F_BALL, MT_F_COLNUM, MT_F_BRC, MT_F_INCR
160 , MT_F_FBDISP, MT_F_UU_4_15, MT_F_LENGTH, MT_F_UU_1_15
161 , MT_F_RC, MT_F_RCNUM, MT_F_ROWNUM, MT_F_CBX
162 , MT_F_ID, MT_F_SIZE, MT_F_ROWNUM1, MT_F_UU_3_11
163 , MT_F_RC1, MT_F_CCB, MT_F_CBRB, MT_F_CDB
164 , MT_F_ROWNUM2, MT_F_CELL, MT_F_UU_3_9, MT_F_CONTNUM
165 , MT_F_UU_1_6, MT_F_DUP, MT_F_RC2, MT_F_CTXDISP
166 , MT_F_IMM16L, MT_F_LOOPO, MT_F_CB1SEL, MT_F_CB2SEL
167 , MT_F_CB1INCR, MT_F_CB2INCR, MT_F_RC3, MT_F_MSYSFRSR2
168 , MT_F_BRC2, MT_F_BALL2, MT_F_MAX
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169} IFIELD_TYPE;
170
d031aafb 171#define MAX_IFLD ((int) MT_F_MAX)
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172
173/* Hardware attribute indices. */
174
175/* Enum declaration for cgen_hw attrs. */
176typedef enum cgen_hw_attr {
177 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
178 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
179} CGEN_HW_ATTR;
180
181/* Number of non-boolean elements in cgen_hw_attr. */
182#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
183
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184/* cgen_hw attribute accessor macros. */
185#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
186#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
187#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
188#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
189#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
190
d031aafb 191/* Enum declaration for mt hardware types. */
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192typedef enum cgen_hw_type {
193 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
194 , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX
195} CGEN_HW_TYPE;
196
197#define MAX_HW ((int) HW_MAX)
198
199/* Operand attribute indices. */
200
201/* Enum declaration for cgen_operand attrs. */
202typedef enum cgen_operand_attr {
203 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
204 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
205 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
206} CGEN_OPERAND_ATTR;
207
208/* Number of non-boolean elements in cgen_operand_attr. */
209#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
210
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211/* cgen_operand attribute accessor macros. */
212#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
213#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
214#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
215#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
216#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
217#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
218#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
219#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
220#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
221
d031aafb 222/* Enum declaration for mt operand types. */
ac188222 223typedef enum cgen_operand_type {
d031aafb
NS
224 MT_OPERAND_PC, MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR
225 , MT_OPERAND_FRDRRR, MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O
226 , MT_OPERAND_RC, MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC
227 , MT_OPERAND_COLNUM, MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2
228 , MT_OPERAND_RC1, MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL
229 , MT_OPERAND_DUP, MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE
230 , MT_OPERAND_MASK, MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE
231 , MT_OPERAND_MASK1, MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA
232 , MT_OPERAND_WR, MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM
233 , MT_OPERAND_A23, MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR
234 , MT_OPERAND_LENGTH, MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB
235 , MT_OPERAND_MODE, MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR
236 , MT_OPERAND_LOOPSIZE, MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL
237 , MT_OPERAND_CB2SEL, MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX
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238} CGEN_OPERAND_TYPE;
239
240/* Number of operands types. */
6f84a2a6 241#define MAX_OPERANDS 55
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242
243/* Maximum number of operands referenced by any insn. */
244#define MAX_OPERAND_INSTANCES 8
245
246/* Insn attribute indices. */
247
248/* Enum declaration for cgen_insn attrs. */
249typedef enum cgen_insn_attr {
250 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
251 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
252 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
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NS
253 , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD
254 , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2
255 , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
256 , CGEN_INSN_END_NBOOLS
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257} CGEN_INSN_ATTR;
258
259/* Number of non-boolean elements in cgen_insn_attr. */
260#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
261
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262/* cgen_insn attribute accessor macros. */
263#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
264#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
265#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
266#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
267#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
268#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
269#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
270#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
271#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
272#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
273#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
274#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
275#define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0)
276#define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_AL_INSN)) != 0)
277#define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_IO_INSN)) != 0)
278#define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_BR_INSN)) != 0)
6f84a2a6 279#define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_JAL_HAZARD)) != 0)
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280#define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDR)) != 0)
281#define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRDRRR)) != 0)
282#define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR1)) != 0)
283#define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_FRSR2)) != 0)
284#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIPA)) != 0)
285
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DB
286/* cgen.h uses things we just defined. */
287#include "opcode/cgen.h"
288
d031aafb 289extern const struct cgen_ifld mt_cgen_ifld_table[];
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DB
290
291/* Attributes. */
d031aafb
NS
292extern const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[];
293extern const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[];
294extern const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[];
295extern const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[];
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DB
296
297/* Hardware decls. */
298
d031aafb 299extern CGEN_KEYWORD mt_cgen_opval_h_spr;
ac188222 300
d031aafb 301extern const CGEN_HW_ENTRY mt_cgen_hw_table[];
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DB
302
303
304
d031aafb 305#endif /* MT_CPU_H */
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