btrace: async support
[deliverable/binutils-gdb.git] / opcodes / or1k-ibld.c
CommitLineData
73589c9d 1/* Instruction building/extraction support for or1k. -*- C -*-
87e6d782 2
47b0e7ad
NC
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
87e6d782 5
73589c9d
CS
6 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
7 2008, 2010 Free Software Foundation, Inc.
87e6d782 8
9b201bb5 9 This file is part of libopcodes.
87e6d782 10
9b201bb5 11 This library is free software; you can redistribute it and/or modify
47b0e7ad 12 it under the terms of the GNU General Public License as published by
9b201bb5 13 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 14 any later version.
87e6d782 15
9b201bb5
NC
16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
87e6d782 20
47b0e7ad
NC
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
87e6d782
NC
24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
87e6d782
NC
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
73589c9d
CS
34#include "or1k-desc.h"
35#include "or1k-opc.h"
fe8afbc4 36#include "cgen/basic-modes.h"
87e6d782 37#include "opintl.h"
37111cc7 38#include "safe-ctype.h"
87e6d782 39
47b0e7ad 40#undef min
87e6d782 41#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 42#undef max
87e6d782
NC
43#define max(a,b) ((a) > (b) ? (a) : (b))
44
45/* Used by the ifield rtx function. */
46#define FLD(f) (fields->f)
47
48static const char * insert_normal
ffead7ae
MM
49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
87e6d782 51static const char * insert_insn_normal
ffead7ae
MM
52 (CGEN_CPU_DESC, const CGEN_INSN *,
53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
87e6d782 54static int extract_normal
ffead7ae
MM
55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
56 unsigned int, unsigned int, unsigned int, unsigned int,
57 unsigned int, unsigned int, bfd_vma, long *);
87e6d782 58static int extract_insn_normal
ffead7ae
MM
59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 61#if CGEN_INT_INSN_P
87e6d782 62static void put_insn_int_value
ffead7ae 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
0e2ee3ca
NC
64#endif
65#if ! CGEN_INT_INSN_P
66static CGEN_INLINE void insert_1
ffead7ae 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
0e2ee3ca 68static CGEN_INLINE int fill_cache
ffead7ae 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
0e2ee3ca 70static CGEN_INLINE long extract_1
ffead7ae 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
0e2ee3ca 72#endif
87e6d782
NC
73\f
74/* Operand insertion. */
75
76#if ! CGEN_INT_INSN_P
77
78/* Subroutine of insert_normal. */
79
80static CGEN_INLINE void
ffead7ae
MM
81insert_1 (CGEN_CPU_DESC cd,
82 unsigned long value,
83 int start,
84 int length,
85 int word_length,
86 unsigned char *bufp)
87e6d782
NC
87{
88 unsigned long x,mask;
89 int shift;
87e6d782 90
0e2ee3ca 91 x = cgen_get_insn_value (cd, bufp, word_length);
87e6d782
NC
92
93 /* Written this way to avoid undefined behaviour. */
94 mask = (((1L << (length - 1)) - 1) << 1) | 1;
95 if (CGEN_INSN_LSB0_P)
96 shift = (start + 1) - length;
97 else
98 shift = (word_length - (start + length));
99 x = (x & ~(mask << shift)) | ((value & mask) << shift);
100
0e2ee3ca 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
87e6d782
NC
102}
103
104#endif /* ! CGEN_INT_INSN_P */
105
106/* Default insertion routine.
107
108 ATTRS is a mask of the boolean attributes.
109 WORD_OFFSET is the offset in bits from the start of the insn of the value.
110 WORD_LENGTH is the length of the word in bits in which the value resides.
111 START is the starting bit number in the word, architecture origin.
112 LENGTH is the length of VALUE in bits.
113 TOTAL_LENGTH is the total length of the insn in bits.
114
115 The result is an error message or NULL if success. */
116
117/* ??? This duplicates functionality with bfd's howto table and
118 bfd_install_relocation. */
119/* ??? This doesn't handle bfd_vma's. Create another function when
120 necessary. */
121
122static const char *
ffead7ae
MM
123insert_normal (CGEN_CPU_DESC cd,
124 long value,
125 unsigned int attrs,
126 unsigned int word_offset,
127 unsigned int start,
128 unsigned int length,
129 unsigned int word_length,
130 unsigned int total_length,
131 CGEN_INSN_BYTES_PTR buffer)
87e6d782
NC
132{
133 static char errbuf[100];
134 /* Written this way to avoid undefined behaviour. */
135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
136
137 /* If LENGTH is zero, this operand doesn't contribute to the value. */
138 if (length == 0)
139 return NULL;
140
b7cd1872 141 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
142 abort ();
143
144 /* For architectures with insns smaller than the base-insn-bitsize,
145 word_length may be too big. */
146 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
147 {
148 if (word_offset == 0
149 && word_length > total_length)
150 word_length = total_length;
151 }
152
153 /* Ensure VALUE will fit. */
fc7bc883
RH
154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
155 {
156 long minval = - (1L << (length - 1));
157 unsigned long maxval = mask;
73589c9d 158
fc7bc883
RH
159 if ((value > 0 && (unsigned long) value > maxval)
160 || value < minval)
161 {
162 /* xgettext:c-format */
163 sprintf (errbuf,
164 _("operand out of range (%ld not between %ld and %lu)"),
165 value, minval, maxval);
166 return errbuf;
167 }
168 }
169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
87e6d782
NC
170 {
171 unsigned long maxval = mask;
ed963e2d
NC
172 unsigned long val = (unsigned long) value;
173
174 /* For hosts with a word size > 32 check to see if value has been sign
175 extended beyond 32 bits. If so then ignore these higher sign bits
176 as the user is attempting to store a 32-bit signed value into an
177 unsigned 32-bit field which is allowed. */
178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
179 val &= 0xFFFFFFFF;
180
181 if (val > maxval)
87e6d782
NC
182 {
183 /* xgettext:c-format */
184 sprintf (errbuf,
ed963e2d
NC
185 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
186 val, maxval);
87e6d782
NC
187 return errbuf;
188 }
189 }
190 else
191 {
192 if (! cgen_signed_overflow_ok_p (cd))
193 {
194 long minval = - (1L << (length - 1));
195 long maxval = (1L << (length - 1)) - 1;
73589c9d 196
87e6d782
NC
197 if (value < minval || value > maxval)
198 {
199 sprintf
200 /* xgettext:c-format */
201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
202 value, minval, maxval);
203 return errbuf;
204 }
205 }
206 }
207
208#if CGEN_INT_INSN_P
209
210 {
211 int shift;
212
213 if (CGEN_INSN_LSB0_P)
214 shift = (word_offset + start + 1) - length;
215 else
216 shift = total_length - (word_offset + start + length);
217 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
218 }
219
220#else /* ! CGEN_INT_INSN_P */
221
222 {
223 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
224
225 insert_1 (cd, value, start, length, word_length, bufp);
226 }
227
228#endif /* ! CGEN_INT_INSN_P */
229
230 return NULL;
231}
232
233/* Default insn builder (insert handler).
234 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
235 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
236 recorded in host byte order, otherwise BUFFER is an array of bytes
237 and the value is recorded in target byte order).
238 The result is an error message or NULL if success. */
239
240static const char *
ffead7ae
MM
241insert_insn_normal (CGEN_CPU_DESC cd,
242 const CGEN_INSN * insn,
243 CGEN_FIELDS * fields,
244 CGEN_INSN_BYTES_PTR buffer,
245 bfd_vma pc)
87e6d782
NC
246{
247 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
248 unsigned long value;
249 const CGEN_SYNTAX_CHAR_TYPE * syn;
250
251 CGEN_INIT_INSERT (cd);
252 value = CGEN_INSN_BASE_VALUE (insn);
253
254 /* If we're recording insns as numbers (rather than a string of bytes),
255 target byte order handling is deferred until later. */
256
257#if CGEN_INT_INSN_P
258
259 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
260 CGEN_FIELDS_BITSIZE (fields), value);
261
262#else
263
0e2ee3ca
NC
264 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
265 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
87e6d782
NC
266 value);
267
268#endif /* ! CGEN_INT_INSN_P */
269
270 /* ??? It would be better to scan the format's fields.
271 Still need to be able to insert a value based on the operand though;
272 e.g. storing a branch displacement that got resolved later.
273 Needs more thought first. */
274
275 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
276 {
277 const char *errmsg;
278
279 if (CGEN_SYNTAX_CHAR_P (* syn))
280 continue;
281
282 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
283 fields, buffer, pc);
284 if (errmsg)
285 return errmsg;
286 }
287
288 return NULL;
289}
290
0e2ee3ca 291#if CGEN_INT_INSN_P
87e6d782 292/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 293 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
87e6d782
NC
294
295static void
ffead7ae
MM
296put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
297 CGEN_INSN_BYTES_PTR buf,
298 int length,
299 int insn_length,
300 CGEN_INSN_INT value)
87e6d782
NC
301{
302 /* For architectures with insns smaller than the base-insn-bitsize,
303 length may be too big. */
304 if (length > insn_length)
305 *buf = value;
306 else
307 {
308 int shift = insn_length - length;
309 /* Written this way to avoid undefined behaviour. */
310 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 311
87e6d782
NC
312 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
313 }
314}
0e2ee3ca 315#endif
87e6d782
NC
316\f
317/* Operand extraction. */
318
319#if ! CGEN_INT_INSN_P
320
321/* Subroutine of extract_normal.
322 Ensure sufficient bytes are cached in EX_INFO.
323 OFFSET is the offset in bytes from the start of the insn of the value.
324 BYTES is the length of the needed value.
325 Returns 1 for success, 0 for failure. */
326
327static CGEN_INLINE int
ffead7ae
MM
328fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
329 CGEN_EXTRACT_INFO *ex_info,
330 int offset,
331 int bytes,
332 bfd_vma pc)
87e6d782
NC
333{
334 /* It's doubtful that the middle part has already been fetched so
335 we don't optimize that case. kiss. */
0e2ee3ca 336 unsigned int mask;
87e6d782
NC
337 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
338
339 /* First do a quick check. */
340 mask = (1 << bytes) - 1;
341 if (((ex_info->valid >> offset) & mask) == mask)
342 return 1;
343
344 /* Search for the first byte we need to read. */
345 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
346 if (! (mask & ex_info->valid))
347 break;
348
349 if (bytes)
350 {
351 int status;
352
353 pc += offset;
354 status = (*info->read_memory_func)
355 (pc, ex_info->insn_bytes + offset, bytes, info);
356
357 if (status != 0)
358 {
359 (*info->memory_error_func) (status, pc, info);
360 return 0;
361 }
362
363 ex_info->valid |= ((1 << bytes) - 1) << offset;
364 }
365
366 return 1;
367}
368
369/* Subroutine of extract_normal. */
370
371static CGEN_INLINE long
ffead7ae
MM
372extract_1 (CGEN_CPU_DESC cd,
373 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
374 int start,
375 int length,
376 int word_length,
377 unsigned char *bufp,
378 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
379{
380 unsigned long x;
381 int shift;
47b0e7ad 382
e333d2c4
NC
383 x = cgen_get_insn_value (cd, bufp, word_length);
384
87e6d782
NC
385 if (CGEN_INSN_LSB0_P)
386 shift = (start + 1) - length;
387 else
388 shift = (word_length - (start + length));
389 return x >> shift;
390}
391
392#endif /* ! CGEN_INT_INSN_P */
393
394/* Default extraction routine.
395
396 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
397 or sometimes less for cases like the m32r where the base insn size is 32
398 but some insns are 16 bits.
399 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
400 but for generality we take a bitmask of all of them.
401 WORD_OFFSET is the offset in bits from the start of the insn of the value.
402 WORD_LENGTH is the length of the word in bits in which the value resides.
403 START is the starting bit number in the word, architecture origin.
404 LENGTH is the length of VALUE in bits.
405 TOTAL_LENGTH is the total length of the insn in bits.
406
407 Returns 1 for success, 0 for failure. */
408
409/* ??? The return code isn't properly used. wip. */
410
411/* ??? This doesn't handle bfd_vma's. Create another function when
412 necessary. */
413
414static int
ffead7ae 415extract_normal (CGEN_CPU_DESC cd,
87e6d782 416#if ! CGEN_INT_INSN_P
ffead7ae 417 CGEN_EXTRACT_INFO *ex_info,
87e6d782 418#else
ffead7ae 419 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
87e6d782 420#endif
ffead7ae
MM
421 CGEN_INSN_INT insn_value,
422 unsigned int attrs,
423 unsigned int word_offset,
424 unsigned int start,
425 unsigned int length,
426 unsigned int word_length,
427 unsigned int total_length,
87e6d782 428#if ! CGEN_INT_INSN_P
ffead7ae 429 bfd_vma pc,
87e6d782 430#else
ffead7ae 431 bfd_vma pc ATTRIBUTE_UNUSED,
87e6d782 432#endif
ffead7ae 433 long *valuep)
87e6d782 434{
fc7bc883 435 long value, mask;
87e6d782
NC
436
437 /* If LENGTH is zero, this operand doesn't contribute to the value
438 so give it a standard value of zero. */
439 if (length == 0)
440 {
441 *valuep = 0;
442 return 1;
443 }
444
b7cd1872 445 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
446 abort ();
447
448 /* For architectures with insns smaller than the insn-base-bitsize,
449 word_length may be too big. */
450 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
451 {
ed963e2d
NC
452 if (word_offset + word_length > total_length)
453 word_length = total_length - word_offset;
87e6d782
NC
454 }
455
fc7bc883 456 /* Does the value reside in INSN_VALUE, and at the right alignment? */
87e6d782 457
fc7bc883 458 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
87e6d782
NC
459 {
460 if (CGEN_INSN_LSB0_P)
461 value = insn_value >> ((word_offset + start + 1) - length);
462 else
463 value = insn_value >> (total_length - ( word_offset + start + length));
464 }
465
466#if ! CGEN_INT_INSN_P
467
468 else
469 {
470 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
471
b7cd1872 472 if (word_length > 8 * sizeof (CGEN_INSN_INT))
87e6d782
NC
473 abort ();
474
475 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
476 return 0;
477
478 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
479 }
480
481#endif /* ! CGEN_INT_INSN_P */
482
483 /* Written this way to avoid undefined behaviour. */
484 mask = (((1L << (length - 1)) - 1) << 1) | 1;
485
486 value &= mask;
487 /* sign extend? */
488 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
489 && (value & (1L << (length - 1))))
490 value |= ~mask;
491
492 *valuep = value;
493
494 return 1;
495}
496
497/* Default insn extractor.
498
499 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
500 The extracted fields are stored in FIELDS.
501 EX_INFO is used to handle reading variable length insns.
502 Return the length of the insn in bits, or 0 if no match,
503 or -1 if an error occurs fetching data (memory_error_func will have
504 been called). */
505
506static int
ffead7ae
MM
507extract_insn_normal (CGEN_CPU_DESC cd,
508 const CGEN_INSN *insn,
509 CGEN_EXTRACT_INFO *ex_info,
510 CGEN_INSN_INT insn_value,
511 CGEN_FIELDS *fields,
512 bfd_vma pc)
87e6d782
NC
513{
514 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
515 const CGEN_SYNTAX_CHAR_TYPE *syn;
516
517 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
518
519 CGEN_INIT_EXTRACT (cd);
520
521 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
522 {
523 int length;
524
525 if (CGEN_SYNTAX_CHAR_P (*syn))
526 continue;
527
528 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
529 ex_info, insn_value, fields, pc);
530 if (length <= 0)
531 return length;
532 }
533
534 /* We recognized and successfully extracted this insn. */
535 return CGEN_INSN_BITSIZE (insn);
536}
537\f
47b0e7ad 538/* Machine generated code added here. */
87e6d782 539
73589c9d 540const char * or1k_cgen_insert_operand
47b0e7ad 541 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
0e2ee3ca 542
87e6d782
NC
543/* Main entry point for operand insertion.
544
545 This function is basically just a big switch statement. Earlier versions
546 used tables to look up the function to use, but
547 - if the table contains both assembler and disassembler functions then
548 the disassembler contains much of the assembler and vice-versa,
549 - there's a lot of inlining possibilities as things grow,
550 - using a switch statement avoids the function call overhead.
551
552 This function could be moved into `parse_insn_normal', but keeping it
553 separate makes clear the interface between `parse_insn_normal' and each of
554 the handlers. It's also needed by GAS to insert operands that couldn't be
9a2e995d 555 resolved during parsing. */
87e6d782
NC
556
557const char *
73589c9d 558or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
559 int opindex,
560 CGEN_FIELDS * fields,
561 CGEN_INSN_BYTES_PTR buffer,
562 bfd_vma pc ATTRIBUTE_UNUSED)
87e6d782
NC
563{
564 const char * errmsg = NULL;
565 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
566
567 switch (opindex)
568 {
73589c9d 569 case OR1K_OPERAND_DISP26 :
87e6d782
NC
570 {
571 long value = fields->f_disp26;
fe8afbc4 572 value = ((SI) (((value) - (pc))) >> (2));
87e6d782
NC
573 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer);
574 }
575 break;
73589c9d
CS
576 case OR1K_OPERAND_RA :
577 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 578 break;
73589c9d
CS
579 case OR1K_OPERAND_RADF :
580 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 581 break;
73589c9d
CS
582 case OR1K_OPERAND_RASF :
583 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
87e6d782 584 break;
73589c9d
CS
585 case OR1K_OPERAND_RB :
586 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
87e6d782 587 break;
73589c9d
CS
588 case OR1K_OPERAND_RBDF :
589 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 590 break;
73589c9d 591 case OR1K_OPERAND_RBSF :
87e6d782
NC
592 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
593 break;
73589c9d 594 case OR1K_OPERAND_RD :
87e6d782
NC
595 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
596 break;
73589c9d
CS
597 case OR1K_OPERAND_RDDF :
598 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782 599 break;
73589c9d
CS
600 case OR1K_OPERAND_RDSF :
601 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
602 break;
603 case OR1K_OPERAND_SIMM16 :
604 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer);
605 break;
606 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782
NC
607 {
608{
73589c9d
CS
609 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31));
610 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047));
87e6d782 611}
73589c9d 612 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
87e6d782
NC
613 if (errmsg)
614 break;
73589c9d 615 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
87e6d782
NC
616 if (errmsg)
617 break;
618 }
619 break;
73589c9d 620 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
621 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer);
622 break;
73589c9d
CS
623 case OR1K_OPERAND_UIMM16_SPLIT :
624 {
625{
626 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31));
627 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047));
628}
629 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer);
630 if (errmsg)
631 break;
632 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer);
633 if (errmsg)
634 break;
635 }
636 break;
637 case OR1K_OPERAND_UIMM6 :
638 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer);
87e6d782
NC
639 break;
640
641 default :
642 /* xgettext:c-format */
643 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
644 opindex);
645 abort ();
646 }
647
648 return errmsg;
649}
650
73589c9d 651int or1k_cgen_extract_operand
47b0e7ad 652 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 653
87e6d782
NC
654/* Main entry point for operand extraction.
655 The result is <= 0 for error, >0 for success.
656 ??? Actual values aren't well defined right now.
657
658 This function is basically just a big switch statement. Earlier versions
659 used tables to look up the function to use, but
660 - if the table contains both assembler and disassembler functions then
661 the disassembler contains much of the assembler and vice-versa,
662 - there's a lot of inlining possibilities as things grow,
663 - using a switch statement avoids the function call overhead.
664
665 This function could be moved into `print_insn_normal', but keeping it
666 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 667 the handlers. */
87e6d782
NC
668
669int
73589c9d 670or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
47b0e7ad
NC
671 int opindex,
672 CGEN_EXTRACT_INFO *ex_info,
673 CGEN_INSN_INT insn_value,
674 CGEN_FIELDS * fields,
675 bfd_vma pc)
87e6d782
NC
676{
677 /* Assume success (for those operands that are nops). */
678 int length = 1;
679 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
680
681 switch (opindex)
682 {
73589c9d 683 case OR1K_OPERAND_DISP26 :
87e6d782
NC
684 {
685 long value;
686 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value);
687 value = ((((value) << (2))) + (pc));
688 fields->f_disp26 = value;
689 }
690 break;
73589c9d
CS
691 case OR1K_OPERAND_RA :
692 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 693 break;
73589c9d
CS
694 case OR1K_OPERAND_RADF :
695 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 696 break;
73589c9d
CS
697 case OR1K_OPERAND_RASF :
698 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
87e6d782 699 break;
73589c9d
CS
700 case OR1K_OPERAND_RB :
701 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
87e6d782 702 break;
73589c9d
CS
703 case OR1K_OPERAND_RBDF :
704 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
87e6d782 705 break;
73589c9d 706 case OR1K_OPERAND_RBSF :
87e6d782
NC
707 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
708 break;
73589c9d
CS
709 case OR1K_OPERAND_RD :
710 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
711 break;
712 case OR1K_OPERAND_RDDF :
713 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
714 break;
715 case OR1K_OPERAND_RDSF :
87e6d782
NC
716 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
717 break;
73589c9d
CS
718 case OR1K_OPERAND_SIMM16 :
719 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16);
87e6d782 720 break;
73589c9d 721 case OR1K_OPERAND_SIMM16_SPLIT :
87e6d782 722 {
73589c9d 723 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
87e6d782 724 if (length <= 0) break;
73589c9d 725 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
87e6d782 726 if (length <= 0) break;
73589c9d 727 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
87e6d782
NC
728 }
729 break;
73589c9d 730 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
731 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16);
732 break;
73589c9d
CS
733 case OR1K_OPERAND_UIMM16_SPLIT :
734 {
735 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5);
736 if (length <= 0) break;
737 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11);
738 if (length <= 0) break;
739 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11)))));
740 }
741 break;
742 case OR1K_OPERAND_UIMM6 :
743 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6);
87e6d782
NC
744 break;
745
746 default :
747 /* xgettext:c-format */
748 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
749 opindex);
750 abort ();
751 }
752
753 return length;
754}
755
73589c9d 756cgen_insert_fn * const or1k_cgen_insert_handlers[] =
87e6d782
NC
757{
758 insert_insn_normal,
759};
760
73589c9d 761cgen_extract_fn * const or1k_cgen_extract_handlers[] =
87e6d782
NC
762{
763 extract_insn_normal,
764};
765
73589c9d
CS
766int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
767bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
0e2ee3ca 768
87e6d782
NC
769/* Getting values from cgen_fields is handled by a collection of functions.
770 They are distinguished by the type of the VALUE argument they return.
771 TODO: floating point, inlining support, remove cases where result type
772 not appropriate. */
773
774int
73589c9d 775or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
776 int opindex,
777 const CGEN_FIELDS * fields)
87e6d782
NC
778{
779 int value;
780
781 switch (opindex)
782 {
73589c9d 783 case OR1K_OPERAND_DISP26 :
87e6d782
NC
784 value = fields->f_disp26;
785 break;
73589c9d
CS
786 case OR1K_OPERAND_RA :
787 value = fields->f_r2;
87e6d782 788 break;
73589c9d
CS
789 case OR1K_OPERAND_RADF :
790 value = fields->f_r1;
87e6d782 791 break;
73589c9d
CS
792 case OR1K_OPERAND_RASF :
793 value = fields->f_r2;
87e6d782 794 break;
73589c9d
CS
795 case OR1K_OPERAND_RB :
796 value = fields->f_r3;
87e6d782 797 break;
73589c9d
CS
798 case OR1K_OPERAND_RBDF :
799 value = fields->f_r1;
87e6d782 800 break;
73589c9d 801 case OR1K_OPERAND_RBSF :
87e6d782
NC
802 value = fields->f_r3;
803 break;
73589c9d
CS
804 case OR1K_OPERAND_RD :
805 value = fields->f_r1;
806 break;
807 case OR1K_OPERAND_RDDF :
87e6d782
NC
808 value = fields->f_r1;
809 break;
73589c9d
CS
810 case OR1K_OPERAND_RDSF :
811 value = fields->f_r1;
812 break;
813 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
814 value = fields->f_simm16;
815 break;
73589c9d
CS
816 case OR1K_OPERAND_SIMM16_SPLIT :
817 value = fields->f_simm16_split;
87e6d782 818 break;
73589c9d 819 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
820 value = fields->f_uimm16;
821 break;
73589c9d
CS
822 case OR1K_OPERAND_UIMM16_SPLIT :
823 value = fields->f_uimm16_split;
824 break;
825 case OR1K_OPERAND_UIMM6 :
826 value = fields->f_uimm6;
87e6d782
NC
827 break;
828
829 default :
830 /* xgettext:c-format */
831 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
832 opindex);
833 abort ();
834 }
835
836 return value;
837}
838
839bfd_vma
73589c9d 840or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
841 int opindex,
842 const CGEN_FIELDS * fields)
87e6d782
NC
843{
844 bfd_vma value;
845
846 switch (opindex)
847 {
73589c9d 848 case OR1K_OPERAND_DISP26 :
87e6d782
NC
849 value = fields->f_disp26;
850 break;
73589c9d
CS
851 case OR1K_OPERAND_RA :
852 value = fields->f_r2;
87e6d782 853 break;
73589c9d
CS
854 case OR1K_OPERAND_RADF :
855 value = fields->f_r1;
87e6d782 856 break;
73589c9d
CS
857 case OR1K_OPERAND_RASF :
858 value = fields->f_r2;
87e6d782 859 break;
73589c9d
CS
860 case OR1K_OPERAND_RB :
861 value = fields->f_r3;
87e6d782 862 break;
73589c9d
CS
863 case OR1K_OPERAND_RBDF :
864 value = fields->f_r1;
87e6d782 865 break;
73589c9d 866 case OR1K_OPERAND_RBSF :
87e6d782
NC
867 value = fields->f_r3;
868 break;
73589c9d
CS
869 case OR1K_OPERAND_RD :
870 value = fields->f_r1;
871 break;
872 case OR1K_OPERAND_RDDF :
873 value = fields->f_r1;
874 break;
875 case OR1K_OPERAND_RDSF :
87e6d782
NC
876 value = fields->f_r1;
877 break;
73589c9d 878 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
879 value = fields->f_simm16;
880 break;
73589c9d
CS
881 case OR1K_OPERAND_SIMM16_SPLIT :
882 value = fields->f_simm16_split;
87e6d782 883 break;
73589c9d 884 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
885 value = fields->f_uimm16;
886 break;
73589c9d
CS
887 case OR1K_OPERAND_UIMM16_SPLIT :
888 value = fields->f_uimm16_split;
889 break;
890 case OR1K_OPERAND_UIMM6 :
891 value = fields->f_uimm6;
87e6d782
NC
892 break;
893
894 default :
895 /* xgettext:c-format */
896 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
897 opindex);
898 abort ();
899 }
900
901 return value;
902}
903
73589c9d
CS
904void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
905void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 906
87e6d782
NC
907/* Stuffing values in cgen_fields is handled by a collection of functions.
908 They are distinguished by the type of the VALUE argument they accept.
909 TODO: floating point, inlining support, remove cases where argument type
910 not appropriate. */
911
912void
73589c9d 913or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
914 int opindex,
915 CGEN_FIELDS * fields,
916 int value)
87e6d782
NC
917{
918 switch (opindex)
919 {
73589c9d 920 case OR1K_OPERAND_DISP26 :
87e6d782
NC
921 fields->f_disp26 = value;
922 break;
73589c9d
CS
923 case OR1K_OPERAND_RA :
924 fields->f_r2 = value;
87e6d782 925 break;
73589c9d
CS
926 case OR1K_OPERAND_RADF :
927 fields->f_r1 = value;
87e6d782 928 break;
73589c9d
CS
929 case OR1K_OPERAND_RASF :
930 fields->f_r2 = value;
87e6d782 931 break;
73589c9d
CS
932 case OR1K_OPERAND_RB :
933 fields->f_r3 = value;
87e6d782 934 break;
73589c9d
CS
935 case OR1K_OPERAND_RBDF :
936 fields->f_r1 = value;
87e6d782 937 break;
73589c9d 938 case OR1K_OPERAND_RBSF :
87e6d782
NC
939 fields->f_r3 = value;
940 break;
73589c9d 941 case OR1K_OPERAND_RD :
87e6d782
NC
942 fields->f_r1 = value;
943 break;
73589c9d
CS
944 case OR1K_OPERAND_RDDF :
945 fields->f_r1 = value;
946 break;
947 case OR1K_OPERAND_RDSF :
948 fields->f_r1 = value;
949 break;
950 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
951 fields->f_simm16 = value;
952 break;
73589c9d
CS
953 case OR1K_OPERAND_SIMM16_SPLIT :
954 fields->f_simm16_split = value;
87e6d782 955 break;
73589c9d 956 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
957 fields->f_uimm16 = value;
958 break;
73589c9d
CS
959 case OR1K_OPERAND_UIMM16_SPLIT :
960 fields->f_uimm16_split = value;
961 break;
962 case OR1K_OPERAND_UIMM6 :
963 fields->f_uimm6 = value;
87e6d782
NC
964 break;
965
966 default :
967 /* xgettext:c-format */
968 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
969 opindex);
970 abort ();
971 }
972}
973
974void
73589c9d 975or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
47b0e7ad
NC
976 int opindex,
977 CGEN_FIELDS * fields,
978 bfd_vma value)
87e6d782
NC
979{
980 switch (opindex)
981 {
73589c9d 982 case OR1K_OPERAND_DISP26 :
87e6d782
NC
983 fields->f_disp26 = value;
984 break;
73589c9d
CS
985 case OR1K_OPERAND_RA :
986 fields->f_r2 = value;
87e6d782 987 break;
73589c9d
CS
988 case OR1K_OPERAND_RADF :
989 fields->f_r1 = value;
87e6d782 990 break;
73589c9d
CS
991 case OR1K_OPERAND_RASF :
992 fields->f_r2 = value;
87e6d782 993 break;
73589c9d
CS
994 case OR1K_OPERAND_RB :
995 fields->f_r3 = value;
87e6d782 996 break;
73589c9d
CS
997 case OR1K_OPERAND_RBDF :
998 fields->f_r1 = value;
87e6d782 999 break;
73589c9d 1000 case OR1K_OPERAND_RBSF :
87e6d782
NC
1001 fields->f_r3 = value;
1002 break;
73589c9d
CS
1003 case OR1K_OPERAND_RD :
1004 fields->f_r1 = value;
1005 break;
1006 case OR1K_OPERAND_RDDF :
87e6d782
NC
1007 fields->f_r1 = value;
1008 break;
73589c9d
CS
1009 case OR1K_OPERAND_RDSF :
1010 fields->f_r1 = value;
1011 break;
1012 case OR1K_OPERAND_SIMM16 :
87e6d782
NC
1013 fields->f_simm16 = value;
1014 break;
73589c9d
CS
1015 case OR1K_OPERAND_SIMM16_SPLIT :
1016 fields->f_simm16_split = value;
87e6d782 1017 break;
73589c9d 1018 case OR1K_OPERAND_UIMM16 :
87e6d782
NC
1019 fields->f_uimm16 = value;
1020 break;
73589c9d
CS
1021 case OR1K_OPERAND_UIMM16_SPLIT :
1022 fields->f_uimm16_split = value;
1023 break;
1024 case OR1K_OPERAND_UIMM6 :
1025 fields->f_uimm6 = value;
87e6d782
NC
1026 break;
1027
1028 default :
1029 /* xgettext:c-format */
1030 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1031 opindex);
1032 abort ();
1033 }
1034}
1035
1036/* Function to call before using the instruction builder tables. */
1037
1038void
73589c9d 1039or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd)
87e6d782 1040{
73589c9d
CS
1041 cd->insert_handlers = & or1k_cgen_insert_handlers[0];
1042 cd->extract_handlers = & or1k_cgen_extract_handlers[0];
87e6d782 1043
73589c9d
CS
1044 cd->insert_operand = or1k_cgen_insert_operand;
1045 cd->extract_operand = or1k_cgen_extract_operand;
87e6d782 1046
73589c9d
CS
1047 cd->get_int_operand = or1k_cgen_get_int_operand;
1048 cd->set_int_operand = or1k_cgen_set_int_operand;
1049 cd->get_vma_operand = or1k_cgen_get_vma_operand;
1050 cd->set_vma_operand = or1k_cgen_set_vma_operand;
87e6d782 1051}
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