[deliverable/binutils-gdb.git] / opcodes / ppc-dis.c

/* ppc-dis.c -- Disassemble PowerPC instructions
   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
   2008, 2009 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include <stdio.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opintl.h"
#include "opcode/ppc.h"

/* This file provides several disassembler functions, all of which use
   the disassembler interface defined in dis-asm.h.  Several functions
   are provided because this file handles disassembly for the PowerPC
   in both big and little endian mode and also for the POWER (RS/6000)
   chip.  */
static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
			       ppc_cpu_t);

struct dis_private
{
  /* Stash the result of parsing disassembler_options here.  */
  ppc_cpu_t dialect;
};

#define POWERPC_DIALECT(INFO) \
  (((struct dis_private *) ((INFO)->private_data))->dialect)

struct ppc_mopt {
  const char *opt;
  ppc_cpu_t cpu;
  ppc_cpu_t sticky;
};

struct ppc_mopt ppc_opts[] = {
  { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403
		| PPC_OPCODE_32),
    0 },
  { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403
		| PPC_OPCODE_405 | PPC_OPCODE_32),
    0 },
  { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
    0 },
  { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
		| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
    0 },
  { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_601
		| PPC_OPCODE_32),
    0 },
  { "603",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "604",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64),
    0 },
  { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_32),
    0 },
  { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
    , 0 },
  { "altivec", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
    PPC_OPCODE_ALTIVEC },
  { "any",     0,
    PPC_OPCODE_ANY },
  { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32),
    0 },
  { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32),
    0 },
  { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
    0 },
  { "com",     (PPC_OPCODE_COMMON | PPC_OPCODE_32),
    0 },
  { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32
		| PPC_OPCODE_E300),
    0 },
  { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
		| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC),
    0 },
  { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC),
    0 },
  { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
		| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
		| PPC_OPCODE_E500MC),
    0 },
  { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
    0 },
  { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4),
    0 },
  { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
    0 },
  { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
		| PPC_OPCODE_ALTIVEC),
    0 },
  { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
		| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
		| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC
		| PPC_OPCODE_VSX),
    0 },
  { "ppc",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "ppc32",   (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
    0 },
  { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64),
    0 },
  { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
		    | PPC_OPCODE_64),
    0 },
  { "ppca2",   (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
		| PPC_OPCODE_64 | PPC_OPCODE_PPCA2),
    0 },
  { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
    0 },
  { "pwr",     (PPC_OPCODE_POWER | PPC_OPCODE_32),
    0 },
  { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
    0 },
  { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
    0 },
  { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
    PPC_OPCODE_SPE },
  { "vsx",     (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
    PPC_OPCODE_VSX },
};

/* Handle -m and -M options that set cpu type, and .machine arg.  */

ppc_cpu_t
ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
{
  /* Sticky bits.  */
  ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
				      | PPC_OPCODE_SPE | PPC_OPCODE_ANY);
  unsigned int i;

  for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
    if (strcmp (ppc_opts[i].opt, arg) == 0)
      {
	if (ppc_opts[i].sticky)
	  {
	    retain_flags |= ppc_opts[i].sticky;
	    if ((ppc_cpu & ~(PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
			     | PPC_OPCODE_SPE | PPC_OPCODE_ANY)) != 0)
	      break;
	  }
	ppc_cpu = ppc_opts[i].cpu;
	break;
      }
  if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
    return 0;

  ppc_cpu |= retain_flags;
  return ppc_cpu;
}

/* Determine which set of machines to disassemble for.  */

static int
powerpc_init_dialect (struct disassemble_info *info)
{
  ppc_cpu_t dialect = 0;
  char *arg;
  struct dis_private *priv = calloc (sizeof (*priv), 1);

  if (priv == NULL)
    return FALSE;

  arg = info->disassembler_options;
  while (arg != NULL)
    {
      ppc_cpu_t new_cpu = 0;
      char *end = strchr (arg, ',');

      if (end != NULL)
	*end = 0;

      if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
	dialect = new_cpu;
      else if (strcmp (arg, "32") == 0)
	{
	  dialect &= ~PPC_OPCODE_64;
	  dialect |= PPC_OPCODE_32;
	}
      else if (strcmp (arg, "64") == 0)
	{
	  dialect |= PPC_OPCODE_64;
	  dialect &= ~PPC_OPCODE_32;
	}
      else
	fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);

      if (end != NULL)
	*end++ = ',';
      arg = end;
    }

  if ((dialect & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) == 0)
    {
      if (info->mach == bfd_mach_ppc64)
	dialect |= PPC_OPCODE_64;
      else
	dialect |= PPC_OPCODE_32;
      /* Choose a reasonable default.  */
      dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_CLASSIC
		  | PPC_OPCODE_601 | PPC_OPCODE_ALTIVEC);
    }

  info->private_data = priv;
  POWERPC_DIALECT(info) = dialect;

  return TRUE;
}

/* Print a big endian PowerPC instruction.  */

int
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  if (info->private_data == NULL && !powerpc_init_dialect (info))
    return -1;
  return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
}

/* Print a little endian PowerPC instruction.  */

int
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
{
  if (info->private_data == NULL && !powerpc_init_dialect (info))
    return -1;
  return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
}

/* Print a POWER (RS/6000) instruction.  */

int
print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
{
  return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
}

/* Extract the operand value from the PowerPC or POWER instruction.  */

static long
operand_value_powerpc (const struct powerpc_operand *operand,
		       unsigned long insn, ppc_cpu_t dialect)
{
  long value;
  int invalid;
  /* Extract the value from the instruction.  */
  if (operand->extract)
    value = (*operand->extract) (insn, dialect, &invalid);
  else
    {
      value = (insn >> operand->shift) & operand->bitm;
      if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
	{
	  /* BITM is always some number of zeros followed by some
	     number of ones, followed by some numer of zeros.  */
	  unsigned long top = operand->bitm;
	  /* top & -top gives the rightmost 1 bit, so this
	     fills in any trailing zeros.  */
	  top |= (top & -top) - 1;
	  top &= ~(top >> 1);
	  value = (value ^ top) - top;
	}
    }

  return value;
}

/* Determine whether the optional operand(s) should be printed.  */

static int
skip_optional_operands (const unsigned char *opindex,
			unsigned long insn, ppc_cpu_t dialect)
{
  const struct powerpc_operand *operand;

  for (; *opindex != 0; opindex++)
    {
      operand = &powerpc_operands[*opindex];
      if ((operand->flags & PPC_OPERAND_NEXT) != 0
	  || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	      && operand_value_powerpc (operand, insn, dialect) != 0))
	return 0;
    }

  return 1;
}

/* Print a PowerPC or POWER instruction.  */

static int
print_insn_powerpc (bfd_vma memaddr,
		    struct disassemble_info *info,
		    int bigendian,
		    ppc_cpu_t dialect)
{
  bfd_byte buffer[4];
  int status;
  unsigned long insn;
  const struct powerpc_opcode *opcode;
  const struct powerpc_opcode *opcode_end;
  unsigned long op;
  ppc_cpu_t dialect_orig = dialect;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  if (bigendian)
    insn = bfd_getb32 (buffer);
  else
    insn = bfd_getl32 (buffer);

  /* Get the major opcode of the instruction.  */
  op = PPC_OP (insn);

  /* Find the first match in the opcode table.  We could speed this up
     a bit by doing a binary search on the major opcode.  */
  opcode_end = powerpc_opcodes + powerpc_num_opcodes;
 again:
  for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
    {
      unsigned long table_op;
      const unsigned char *opindex;
      const struct powerpc_operand *operand;
      int invalid;
      int need_comma;
      int need_paren;
      int skip_optional;

      table_op = PPC_OP (opcode->opcode);
      if (op < table_op)
	break;
      if (op > table_op)
	continue;

      if ((insn & opcode->mask) != opcode->opcode
	  || (opcode->flags & dialect) == 0
	  || (opcode->deprecated & dialect_orig) != 0)
	continue;

      /* Make two passes over the operands.  First see if any of them
	 have extraction functions, and, if they do, make sure the
	 instruction is valid.  */
      invalid = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  operand = powerpc_operands + *opindex;
	  if (operand->extract)
	    (*operand->extract) (insn, dialect, &invalid);
	}
      if (invalid)
	continue;

      /* The instruction is valid.  */
      if (opcode->operands[0] != 0)
	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
      else
	(*info->fprintf_func) (info->stream, "%s", opcode->name);

      /* Now extract and print the operands.  */
      need_comma = 0;
      need_paren = 0;
      skip_optional = -1;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
	{
	  long value;

	  operand = powerpc_operands + *opindex;

	  /* Operands that are marked FAKE are simply ignored.  We
	     already made sure that the extract function considered
	     the instruction to be valid.  */
	  if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	    continue;

	  /* If all of the optional operands have the value zero,
	     then don't print any of them.  */
	  if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
	    {
	      if (skip_optional < 0)
		skip_optional = skip_optional_operands (opindex, insn,
							dialect);
	      if (skip_optional)
		continue;
	    }

	  value = operand_value_powerpc (operand, insn, dialect);

	  if (need_comma)
	    {
	      (*info->fprintf_func) (info->stream, ",");
	      need_comma = 0;
	    }

	  /* Print the operand as directed by the flags.  */
	  if ((operand->flags & PPC_OPERAND_GPR) != 0
	      || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
	    (*info->fprintf_func) (info->stream, "r%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	    (*info->fprintf_func) (info->stream, "f%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VR) != 0)
	    (*info->fprintf_func) (info->stream, "v%ld", value);
	  else if ((operand->flags & PPC_OPERAND_VSR) != 0)
	    (*info->fprintf_func) (info->stream, "vs%ld", value);
	  else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	    (*info->print_address_func) (memaddr + value, info);
	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	  else if ((operand->flags & PPC_OPERAND_FSL) != 0) 
	    (*info->fprintf_func) (info->stream, "fsl%ld", value);
	  else if ((operand->flags & PPC_OPERAND_FCR) != 0)
	    (*info->fprintf_func) (info->stream, "fcr%ld", value);
	  else if ((operand->flags & PPC_OPERAND_UDI) != 0)
	    (*info->fprintf_func) (info->stream, "%ld", value);
	  else if ((operand->flags & PPC_OPERAND_CR) != 0
		   && (dialect & PPC_OPCODE_PPC) != 0)
	    {
	      if (operand->bitm == 7)
		(*info->fprintf_func) (info->stream, "cr%ld", value);
	      else
		{
		  static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
		  int cr;
		  int cc;

		  cr = value >> 2;
		  if (cr != 0)
		    (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
		  cc = value & 3;
		  (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
		}
	    }
	  else
	    (*info->fprintf_func) (info->stream, "%ld", value);

	  if (need_paren)
	    {
	      (*info->fprintf_func) (info->stream, ")");
	      need_paren = 0;
	    }

	  if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	    need_comma = 1;
	  else
	    {
	      (*info->fprintf_func) (info->stream, "(");
	      need_paren = 1;
	    }
	}

      /* We have found and printed an instruction; return.  */
      return 4;
    }

  if ((dialect & PPC_OPCODE_ANY) != 0)
    {
      dialect = ~PPC_OPCODE_ANY;
      goto again;
    }

  /* We could not find a match.  */
  (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);

  return 4;
}

void
print_ppc_disassembler_options (FILE *stream)
{
  unsigned int i, col;

  fprintf (stream, _("\n\
The following PPC specific disassembler options are supported for use with\n\
the -M switch:\n"));

  for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
    {
      col += fprintf (stream, " %s,", ppc_opts[i].opt);
      if (col > 66)
	{
	  fprintf (stream, "\n");
	  col = 0;
	}
    }
  fprintf (stream, " 32, 64\n");
}
Commit	Line	Data
252b5132	1	/* ppc-dis.c -- Disassemble PowerPC instructions
081ba1b3	2	Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
69fe9ce5	3	2008, 2009 Free Software Foundation, Inc.
252b5132 RH	4	Written by Ian Lance Taylor, Cygnus Support
252b5132 RH	5
9b201bb5 NC	6	This file is part of the GNU opcodes library.
	7
	8	This library is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3, or (at your option)
	11	any later version.
	12
	13	It is distributed in the hope that it will be useful, but WITHOUT
	14	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this file; see the file COPYING. If not, write to the
	20	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	21	MA 02110-1301, USA. */
252b5132 RH	22
252b5132 RH	23	#include <stdio.h>
252b5132 RH	24	#include "sysdep.h"
252b5132 RH	25	#include "dis-asm.h"
69fe9ce5	26	#include "opintl.h"
252b5132 RH	27	#include "opcode/ppc.h"
	28
	29	/* This file provides several disassembler functions, all of which use
	30	the disassembler interface defined in dis-asm.h. Several functions
	31	are provided because this file handles disassembly for the PowerPC
	32	in both big and little endian mode and also for the POWER (RS/6000)
	33	chip. */
fa452fa6 PB	34	static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
fa452fa6 PB	35	ppc_cpu_t);
252b5132	36
fa452fa6 PB	37	struct dis_private
	38	{
	39	/* Stash the result of parsing disassembler_options here. */
	40	ppc_cpu_t dialect;
	41	};
	42
	43	#define POWERPC_DIALECT(INFO) \
	44	(((struct dis_private *) ((INFO)->private_data))->dialect)
418c1742	45
69fe9ce5 AM	46	struct ppc_mopt {
	47	const char *opt;
	48	ppc_cpu_t cpu;
	49	ppc_cpu_t sticky;
	50	};
	51
	52	struct ppc_mopt ppc_opts[] = {
	53	{ "403", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_403
	54	\| PPC_OPCODE_32),
	55	0 },
	56	{ "405", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_403
	57	\| PPC_OPCODE_405 \| PPC_OPCODE_32),
	58	0 },
	59	{ "440", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32
	60	\| PPC_OPCODE_440 \| PPC_OPCODE_ISEL \| PPC_OPCODE_RFMCI),
	61	0 },
	62	{ "464", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32
	63	\| PPC_OPCODE_440 \| PPC_OPCODE_ISEL \| PPC_OPCODE_RFMCI),
	64	0 },
	65	{ "601", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_601
	66	\| PPC_OPCODE_32),
	67	0 },
	68	{ "603", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
	69	0 },
	70	{ "604", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
	71	0 },
	72	{ "620", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64),
	73	0 },
	74	{ "7400", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	75	\| PPC_OPCODE_32),
	76	0 },
	77	{ "7410", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	78	\| PPC_OPCODE_32),
	79	0 },
	80	{ "7450", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	81	\| PPC_OPCODE_32),
	82	0 },
	83	{ "7455", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ALTIVEC
	84	\| PPC_OPCODE_32),
	85	0 },
	86	{ "750cl", (PPC_OPCODE_PPC \| PPC_OPCODE_PPCPS)
	87	, 0 },
	88	{ "altivec", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC),
	89	PPC_OPCODE_ALTIVEC },
	90	{ "any", 0,
	91	PPC_OPCODE_ANY },
	92	{ "booke", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32),
	93	0 },
	94	{ "booke32", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_32),
	95	0 },
	96	{ "cell", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
	97	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_CELL \| PPC_OPCODE_ALTIVEC),
	98	0 },
	99	{ "com", (PPC_OPCODE_COMMON \| PPC_OPCODE_32),
	100	0 },
	101	{ "e300", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32
	102	\| PPC_OPCODE_E300),
	103	0 },
	104	{ "e500", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_SPE
	105	\| PPC_OPCODE_ISEL \| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
	106	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
	107	\| PPC_OPCODE_E500MC),
	108	0 },
	109	{ "e500mc", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_ISEL
110	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
111	\| PPC_OPCODE_E500MC),
112	0 },
113	{ "e500x2", (PPC_OPCODE_PPC \| PPC_OPCODE_BOOKE \| PPC_OPCODE_SPE
114	\| PPC_OPCODE_ISEL \| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
115	\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK \| PPC_OPCODE_RFMCI
116	\| PPC_OPCODE_E500MC),
117	0 },
118	{ "efs", (PPC_OPCODE_PPC \| PPC_OPCODE_EFS),
119	0 },
120	{ "power4", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
121	\| PPC_OPCODE_POWER4),
122	0 },
123	{ "power5", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
124	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5),
125	0 },
126	{ "power6", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64
127	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6
128	\| PPC_OPCODE_ALTIVEC),
129	0 },
130	{ "power7", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ISEL
131	\| PPC_OPCODE_64 \| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5
132	\| PPC_OPCODE_POWER6 \| PPC_OPCODE_POWER7 \| PPC_OPCODE_ALTIVEC
133	\| PPC_OPCODE_VSX),
134	0 },
135	{ "ppc", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
136	0 },
137	{ "ppc32", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_32),
138	0 },
139	{ "ppc64", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64),
140	0 },
141	{ "ppc64bridge", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_64_BRIDGE
142	\| PPC_OPCODE_64),
143	0 },
e0d602ec BE	144	{ "ppca2", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_ISEL
	145	\| PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_CACHELCK
	146	\| PPC_OPCODE_64 \| PPC_OPCODE_PPCA2),
	147	0 },
69fe9ce5 AM	148	{ "ppcps", (PPC_OPCODE_PPC \| PPC_OPCODE_PPCPS),
	149	0 },
	150	{ "pwr", (PPC_OPCODE_POWER \| PPC_OPCODE_32),
	151	0 },
	152	{ "pwr2", (PPC_OPCODE_POWER \| PPC_OPCODE_POWER2 \| PPC_OPCODE_32),
	153	0 },
	154	{ "pwrx", (PPC_OPCODE_POWER \| PPC_OPCODE_POWER2 \| PPC_OPCODE_32),
	155	0 },
	156	{ "spe", (PPC_OPCODE_PPC \| PPC_OPCODE_EFS),
	157	PPC_OPCODE_SPE },
	158	{ "vsx", (PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC),
	159	PPC_OPCODE_VSX },
	160	};
	161
	162	/* Handle -m and -M options that set cpu type, and .machine arg. */
	163
	164	ppc_cpu_t
	165	ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
	166	{
	167	/* Sticky bits. */
	168	ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX
	169	\| PPC_OPCODE_SPE \| PPC_OPCODE_ANY);
	170	unsigned int i;
	171
	172	for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
	173	if (strcmp (ppc_opts[i].opt, arg) == 0)
	174	{
	175	if (ppc_opts[i].sticky)
	176	{
	177	retain_flags \|= ppc_opts[i].sticky;
	178	if ((ppc_cpu & ~(PPC_OPCODE_ALTIVEC \| PPC_OPCODE_VSX
	179	\| PPC_OPCODE_SPE \| PPC_OPCODE_ANY)) != 0)
	180	break;
	181	}
	182	ppc_cpu = ppc_opts[i].cpu;
	183	break;
	184	}
	185	if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
	186	return 0;
	187
	188	ppc_cpu \|= retain_flags;
	189	return ppc_cpu;
	190	}
	191
	192	/* Determine which set of machines to disassemble for. */
418c1742	193
661bd698	194	static int
fa452fa6	195	powerpc_init_dialect (struct disassemble_info *info)
418c1742	196	{
69fe9ce5 AM	197	ppc_cpu_t dialect = 0;
69fe9ce5 AM	198	char *arg;
fa452fa6 PB	199	struct dis_private priv = calloc (sizeof (priv), 1);
	200
	201	if (priv == NULL)
	202	return FALSE;
418c1742	203
69fe9ce5 AM	204	arg = info->disassembler_options;
	205	while (arg != NULL)
	206	{
	207	ppc_cpu_t new_cpu = 0;
	208	char *end = strchr (arg, ',');
9b4e5766	209
69fe9ce5 AM	210	if (end != NULL)
69fe9ce5 AM	211	*end = 0;
9b4e5766	212
69fe9ce5 AM	213	if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
	214	dialect = new_cpu;
	215	else if (strcmp (arg, "32") == 0)
	216	{
	217	dialect &= ~PPC_OPCODE_64;
	218	dialect \|= PPC_OPCODE_32;
	219	}
	220	else if (strcmp (arg, "64") == 0)
	221	{
	222	dialect \|= PPC_OPCODE_64;
	223	dialect &= ~PPC_OPCODE_32;
	224	}
	225	else
	226	fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
9622b051	227
69fe9ce5 AM	228	if (end != NULL)
	229	*end++ = ',';
	230	arg = end;
	231	}
661bd698	232
70dc4e32	233	if ((dialect & ~(PPC_OPCODE_32 \| PPC_OPCODE_64)) == 0)
802a735e	234	{
70dc4e32 PB	235	if (info->mach == bfd_mach_ppc64)
	236	dialect \|= PPC_OPCODE_64;
	237	else
	238	dialect \|= PPC_OPCODE_32;
69fe9ce5 AM	239	/* Choose a reasonable default. */
	240	dialect \|= (PPC_OPCODE_PPC \| PPC_OPCODE_COMMON \| PPC_OPCODE_CLASSIC
	241	\| PPC_OPCODE_601 \| PPC_OPCODE_ALTIVEC);
802a735e AM	242	}
802a735e AM	243
fa452fa6 PB	244	info->private_data = priv;
	245	POWERPC_DIALECT(info) = dialect;
	246
	247	return TRUE;
418c1742 MG	248	}
	249
	250	/* Print a big endian PowerPC instruction. */
252b5132 RH	251
252b5132 RH	252	int
823bbe9d	253	print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	254	{
fa452fa6 PB	255	if (info->private_data == NULL && !powerpc_init_dialect (info))
	256	return -1;
	257	return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
252b5132 RH	258	}
252b5132 RH	259
418c1742	260	/* Print a little endian PowerPC instruction. */
252b5132 RH	261
252b5132 RH	262	int
823bbe9d	263	print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
252b5132	264	{
fa452fa6 PB	265	if (info->private_data == NULL && !powerpc_init_dialect (info))
	266	return -1;
	267	return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
252b5132 RH	268	}
	269
	270	/* Print a POWER (RS/6000) instruction. */
	271
	272	int
823bbe9d	273	print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
252b5132 RH	274	{
	275	return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
	276	}
	277
ea192fa3 PB	278	/* Extract the operand value from the PowerPC or POWER instruction. */
	279
	280	static long
	281	operand_value_powerpc (const struct powerpc_operand *operand,
fa452fa6	282	unsigned long insn, ppc_cpu_t dialect)
ea192fa3 PB	283	{
	284	long value;
	285	int invalid;
	286	/* Extract the value from the instruction. */
	287	if (operand->extract)
	288	value = (*operand->extract) (insn, dialect, &invalid);
	289	else
	290	{
	291	value = (insn >> operand->shift) & operand->bitm;
	292	if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
	293	{
	294	/* BITM is always some number of zeros followed by some
	295	number of ones, followed by some numer of zeros. */
	296	unsigned long top = operand->bitm;
	297	/* top & -top gives the rightmost 1 bit, so this
	298	fills in any trailing zeros. */
	299	top \|= (top & -top) - 1;
	300	top &= ~(top >> 1);
	301	value = (value ^ top) - top;
	302	}
	303	}
	304
	305	return value;
	306	}
	307
	308	/* Determine whether the optional operand(s) should be printed. */
	309
	310	static int
	311	skip_optional_operands (const unsigned char *opindex,
fa452fa6	312	unsigned long insn, ppc_cpu_t dialect)
ea192fa3 PB	313	{
	314	const struct powerpc_operand *operand;
	315
	316	for (; *opindex != 0; opindex++)
	317	{
	318	operand = &powerpc_operands[*opindex];
	319	if ((operand->flags & PPC_OPERAND_NEXT) != 0
	320	\|\| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
	321	&& operand_value_powerpc (operand, insn, dialect) != 0))
	322	return 0;
	323	}
	324
	325	return 1;
	326	}
	327
252b5132 RH	328	/* Print a PowerPC or POWER instruction. */
	329
	330	static int
823bbe9d AM	331	print_insn_powerpc (bfd_vma memaddr,
	332	struct disassemble_info *info,
	333	int bigendian,
fa452fa6	334	ppc_cpu_t dialect)
252b5132 RH	335	{
	336	bfd_byte buffer[4];
	337	int status;
	338	unsigned long insn;
	339	const struct powerpc_opcode *opcode;
	340	const struct powerpc_opcode *opcode_end;
	341	unsigned long op;
70dc4e32	342	ppc_cpu_t dialect_orig = dialect;
252b5132 RH	343
	344	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	345	if (status != 0)
	346	{
	347	(*info->memory_error_func) (status, memaddr, info);
	348	return -1;
	349	}
	350
	351	if (bigendian)
	352	insn = bfd_getb32 (buffer);
	353	else
	354	insn = bfd_getl32 (buffer);
	355
	356	/* Get the major opcode of the instruction. */
	357	op = PPC_OP (insn);
	358
	359	/* Find the first match in the opcode table. We could speed this up
	360	a bit by doing a binary search on the major opcode. */
	361	opcode_end = powerpc_opcodes + powerpc_num_opcodes;
661bd698	362	again:
252b5132 RH	363	for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
	364	{
	365	unsigned long table_op;
	366	const unsigned char *opindex;
	367	const struct powerpc_operand *operand;
	368	int invalid;
	369	int need_comma;
	370	int need_paren;
ea192fa3	371	int skip_optional;
252b5132 RH	372
	373	table_op = PPC_OP (opcode->opcode);
	374	if (op < table_op)
	375	break;
	376	if (op > table_op)
	377	continue;
	378
	379	if ((insn & opcode->mask) != opcode->opcode
21169fcf	380	\|\| (opcode->flags & dialect) == 0
70dc4e32	381	\|\| (opcode->deprecated & dialect_orig) != 0)
252b5132 RH	382	continue;
	383
	384	/* Make two passes over the operands. First see if any of them
	385	have extraction functions, and, if they do, make sure the
	386	instruction is valid. */
	387	invalid = 0;
	388	for (opindex = opcode->operands; *opindex != 0; opindex++)
	389	{
	390	operand = powerpc_operands + *opindex;
	391	if (operand->extract)
802a735e	392	(*operand->extract) (insn, dialect, &invalid);
252b5132 RH	393	}
	394	if (invalid)
	395	continue;
	396
	397	/* The instruction is valid. */
252b5132	398	if (opcode->operands[0] != 0)
fdd12ef3 AM	399	(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
	400	else
	401	(*info->fprintf_func) (info->stream, "%s", opcode->name);
252b5132 RH	402
	403	/* Now extract and print the operands. */
	404	need_comma = 0;
	405	need_paren = 0;
ea192fa3	406	skip_optional = -1;
252b5132 RH	407	for (opindex = opcode->operands; *opindex != 0; opindex++)
	408	{
	409	long value;
	410
	411	operand = powerpc_operands + *opindex;
	412
	413	/* Operands that are marked FAKE are simply ignored. We
	414	already made sure that the extract function considered
	415	the instruction to be valid. */
	416	if ((operand->flags & PPC_OPERAND_FAKE) != 0)
	417	continue;
	418
ea192fa3 PB	419	/* If all of the optional operands have the value zero,
ea192fa3 PB	420	then don't print any of them. */
65b650b4 AM	421	if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
	422	{
	423	if (skip_optional < 0)
	424	skip_optional = skip_optional_operands (opindex, insn,
	425	dialect);
	426	if (skip_optional)
	427	continue;
	428	}
252b5132	429
ea192fa3 PB	430	value = operand_value_powerpc (operand, insn, dialect);
ea192fa3 PB	431
252b5132 RH	432	if (need_comma)
	433	{
	434	(*info->fprintf_func) (info->stream, ",");
	435	need_comma = 0;
	436	}
	437
	438	/* Print the operand as directed by the flags. */
fdd12ef3 AM	439	if ((operand->flags & PPC_OPERAND_GPR) != 0
fdd12ef3 AM	440	\|\| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
252b5132 RH	441	(*info->fprintf_func) (info->stream, "r%ld", value);
	442	else if ((operand->flags & PPC_OPERAND_FPR) != 0)
	443	(*info->fprintf_func) (info->stream, "f%ld", value);
786e2c0f C	444	else if ((operand->flags & PPC_OPERAND_VR) != 0)
786e2c0f C	445	(*info->fprintf_func) (info->stream, "v%ld", value);
9b4e5766 PB	446	else if ((operand->flags & PPC_OPERAND_VSR) != 0)
9b4e5766 PB	447	(*info->fprintf_func) (info->stream, "vs%ld", value);
252b5132 RH	448	else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
	449	(*info->print_address_func) (memaddr + value, info);
	450	else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
	451	(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
081ba1b3 AM	452	else if ((operand->flags & PPC_OPERAND_FSL) != 0)
	453	(*info->fprintf_func) (info->stream, "fsl%ld", value);
	454	else if ((operand->flags & PPC_OPERAND_FCR) != 0)
	455	(*info->fprintf_func) (info->stream, "fcr%ld", value);
	456	else if ((operand->flags & PPC_OPERAND_UDI) != 0)
	457	(*info->fprintf_func) (info->stream, "%ld", value);
70dc4e32 PB	458	else if ((operand->flags & PPC_OPERAND_CR) != 0
70dc4e32 PB	459	&& (dialect & PPC_OPCODE_PPC) != 0)
252b5132	460	{
b84bf58a	461	if (operand->bitm == 7)
0fd3a477	462	(*info->fprintf_func) (info->stream, "cr%ld", value);
252b5132 RH	463	else
	464	{
	465	static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
	466	int cr;
	467	int cc;
	468
	469	cr = value >> 2;
	470	if (cr != 0)
8b4fa155	471	(info->fprintf_func) (info->stream, "4cr%d+", cr);
252b5132	472	cc = value & 3;
8b4fa155	473	(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
252b5132 RH	474	}
252b5132 RH	475	}
70dc4e32 PB	476	else
70dc4e32 PB	477	(*info->fprintf_func) (info->stream, "%ld", value);
252b5132 RH	478
	479	if (need_paren)
	480	{
	481	(*info->fprintf_func) (info->stream, ")");
	482	need_paren = 0;
	483	}
	484
	485	if ((operand->flags & PPC_OPERAND_PARENS) == 0)
	486	need_comma = 1;
	487	else
	488	{
	489	(*info->fprintf_func) (info->stream, "(");
	490	need_paren = 1;
	491	}
	492	}
	493
	494	/* We have found and printed an instruction; return. */
	495	return 4;
	496	}
	497
661bd698 AM	498	if ((dialect & PPC_OPCODE_ANY) != 0)
	499	{
	500	dialect = ~PPC_OPCODE_ANY;
	501	goto again;
	502	}
	503
252b5132 RH	504	/* We could not find a match. */
	505	(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
	506
	507	return 4;
	508	}
07dd56a9 NC	509
07dd56a9 NC	510	void
823bbe9d	511	print_ppc_disassembler_options (FILE *stream)
07dd56a9	512	{
69fe9ce5 AM	513	unsigned int i, col;
	514
	515	fprintf (stream, _("\n\
07dd56a9	516	The following PPC specific disassembler options are supported for use with\n\
69fe9ce5 AM	517	the -M switch:\n"));
	518
	519	for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
	520	{
	521	col += fprintf (stream, " %s,", ppc_opts[i].opt);
	522	if (col > 66)
	523	{
	524	fprintf (stream, "\n");
	525	col = 0;
	526	}
	527	}
	528	fprintf (stream, " 32, 64\n");
07dd56a9	529	}