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[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
6ba045b1 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001
060d22b0 3 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
112, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2102111-1307, USA. */
22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
802a735e
AM		 41static unsigned long insert_bat
42 PARAMS ((unsigned long, long, int, const char **));
43static long extract_bat
44 PARAMS ((unsigned long, int, int *));
45static unsigned long insert_bba
46 PARAMS ((unsigned long, long, int, const char **));
47static long extract_bba
48 PARAMS ((unsigned long, int, int *));
49static unsigned long insert_bd
50 PARAMS ((unsigned long, long, int, const char **));
51static long extract_bd
52 PARAMS ((unsigned long, int, int *));
53static unsigned long insert_bdm
54 PARAMS ((unsigned long, long, int, const char **));
55static long extract_bdm
56 PARAMS ((unsigned long, int, int *));
57static unsigned long insert_bdp
58 PARAMS ((unsigned long, long, int, const char **));
59static long extract_bdp
60 PARAMS ((unsigned long, int, int *));
61static int valid_bo
62 PARAMS ((long, int));
63static unsigned long insert_bo
64 PARAMS ((unsigned long, long, int, const char **));
65static long extract_bo
66 PARAMS ((unsigned long, int, int *));
67static unsigned long insert_boe
68 PARAMS ((unsigned long, long, int, const char **));
69static long extract_boe
70 PARAMS ((unsigned long, int, int *));
71static unsigned long insert_ds
72 PARAMS ((unsigned long, long, int, const char **));
73static long extract_ds
74 PARAMS ((unsigned long, int, int *));
75static unsigned long insert_de
76 PARAMS ((unsigned long, long, int, const char **));
77static long extract_de
78 PARAMS ((unsigned long, int, int *));
79static unsigned long insert_des
80 PARAMS ((unsigned long, long, int, const char **));
81static long extract_des
82 PARAMS ((unsigned long, int, int *));
83static unsigned long insert_li
84 PARAMS ((unsigned long, long, int, const char **));
85static long extract_li
86 PARAMS ((unsigned long, int, int *));
87static unsigned long insert_mbe
88 PARAMS ((unsigned long, long, int, const char **));
89static long extract_mbe
90 PARAMS ((unsigned long, int, int *));
91static unsigned long insert_mb6
92 PARAMS ((unsigned long, long, int, const char **));
93static long extract_mb6
94 PARAMS ((unsigned long, int, int *));
95static unsigned long insert_nb
96 PARAMS ((unsigned long, long, int, const char **));
97static long extract_nb
98 PARAMS ((unsigned long, int, int *));
99static unsigned long insert_nsi
100 PARAMS ((unsigned long, long, int, const char **));
101static long extract_nsi
102 PARAMS ((unsigned long, int, int *));
103static unsigned long insert_ral
104 PARAMS ((unsigned long, long, int, const char **));
105static unsigned long insert_ram
106 PARAMS ((unsigned long, long, int, const char **));
107static unsigned long insert_ras
108 PARAMS ((unsigned long, long, int, const char **));
109static unsigned long insert_rbs
110 PARAMS ((unsigned long, long, int, const char **));
111static long extract_rbs
112 PARAMS ((unsigned long, int, int *));
113static unsigned long insert_sh6
114 PARAMS ((unsigned long, long, int, const char **));
115static long extract_sh6
116 PARAMS ((unsigned long, int, int *));
117static unsigned long insert_spr
118 PARAMS ((unsigned long, long, int, const char **));
119static long extract_spr
120 PARAMS ((unsigned long, int, int *));
121static unsigned long insert_tbr
122 PARAMS ((unsigned long, long, int, const char **));
123static long extract_tbr
124 PARAMS ((unsigned long, int, int *));
252b5132
RH		 125\f
126/* The operands table.
127
128 The fields are bits, shift, insert, extract, flags.
129
130 We used to put parens around the various additions, like the one
131 for BA just below. However, that caused trouble with feeble
132 compilers with a limit on depth of a parenthesized expression, like
133 (reportedly) the compiler in Microsoft Developer Studio 5. So we
134 omit the parens, since the macros are never used in a context where
135 the addition will be ambiguous. */
136
137const struct powerpc_operand powerpc_operands[] =
138{
139 /* The zero index is used to indicate the end of the list of
140 operands. */
141#define UNUSED 0
11b37b7b 142 { 0, 0, 0, 0, 0 },
252b5132
RH		 143
144 /* The BA field in an XL form instruction. */
145#define BA UNUSED + 1
146#define BA_MASK (0x1f << 16)
11b37b7b 147 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 148
149 /* The BA field in an XL form instruction when it must be the same
150 as the BT field in the same instruction. */
151#define BAT BA + 1
11b37b7b 152 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 153
154 /* The BB field in an XL form instruction. */
155#define BB BAT + 1
156#define BB_MASK (0x1f << 11)
11b37b7b 157 { 5, 11, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 158
159 /* The BB field in an XL form instruction when it must be the same
160 as the BA field in the same instruction. */
161#define BBA BB + 1
11b37b7b 162 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 163
164 /* The BD field in a B form instruction. The lower two bits are
165 forced to zero. */
166#define BD BBA + 1
11b37b7b 167 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 168
169 /* The BD field in a B form instruction when absolute addressing is
170 used. */
171#define BDA BD + 1
11b37b7b 172 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 173
174 /* The BD field in a B form instruction when the - modifier is used.
175 This sets the y bit of the BO field appropriately. */
176#define BDM BDA + 1
11b37b7b
AM		 177 { 16, 0, insert_bdm, extract_bdm,
178 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 179
180 /* The BD field in a B form instruction when the - modifier is used
181 and absolute address is used. */
182#define BDMA BDM + 1
11b37b7b
AM		 183 { 16, 0, insert_bdm, extract_bdm,
184 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 185
186 /* The BD field in a B form instruction when the + modifier is used.
187 This sets the y bit of the BO field appropriately. */
188#define BDP BDMA + 1
11b37b7b
AM		 189 { 16, 0, insert_bdp, extract_bdp,
190 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 191
192 /* The BD field in a B form instruction when the + modifier is used
193 and absolute addressing is used. */
194#define BDPA BDP + 1
11b37b7b
AM		 195 { 16, 0, insert_bdp, extract_bdp,
196 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 197
198 /* The BF field in an X or XL form instruction. */
199#define BF BDPA + 1
11b37b7b 200 { 3, 23, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 201
202 /* An optional BF field. This is used for comparison instructions,
203 in which an omitted BF field is taken as zero. */
204#define OBF BF + 1
11b37b7b 205 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 206
207 /* The BFA field in an X or XL form instruction. */
208#define BFA OBF + 1
11b37b7b 209 { 3, 18, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 210
211 /* The BI field in a B form or XL form instruction. */
212#define BI BFA + 1
213#define BI_MASK (0x1f << 16)
11b37b7b 214 { 5, 16, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 215
216 /* The BO field in a B form instruction. Certain values are
217 illegal. */
218#define BO BI + 1
219#define BO_MASK (0x1f << 21)
11b37b7b 220 { 5, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 221
222 /* The BO field in a B form instruction when the + or - modifier is
223 used. This is like the BO field, but it must be even. */
224#define BOE BO + 1
11b37b7b 225 { 5, 21, insert_boe, extract_boe, 0 },
252b5132
RH		 226
227 /* The BT field in an X or XL form instruction. */
228#define BT BOE + 1
11b37b7b 229 { 5, 21, 0, 0, PPC_OPERAND_CR },
252b5132
RH		 230
231 /* The condition register number portion of the BI field in a B form
232 or XL form instruction. This is used for the extended
233 conditional branch mnemonics, which set the lower two bits of the
234 BI field. This field is optional. */
235#define CR BT + 1
11b37b7b 236 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 237
418c1742
MG		 238 /* The CT field in an X form instruction. */
239#define CT CR + 1
1f613cde 240 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
418c1742 241
252b5132
RH		 242 /* The D field in a D form instruction. This is a displacement off
243 a register, and implies that the next operand is a register in
244 parentheses. */
418c1742 245#define D CT + 1
11b37b7b 246 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 247
418c1742
MG		 248 /* The DE field in a DE form instruction. This is like D, but is 12
249 bits only. */
250#define DE D + 1
251 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
252
253 /* The DES field in a DES form instruction. This is like DS, but is 14
254 bits only (12 stored.) */
255#define DES DE + 1
256 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
257
252b5132
RH		 258 /* The DS field in a DS form instruction. This is like D, but the
259 lower two bits are forced to zero. */
418c1742 260#define DS DES + 1
6ba045b1
AM		 261 { 16, 0, insert_ds, extract_ds,
262 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 263
264 /* The E field in a wrteei instruction. */
265#define E DS + 1
11b37b7b 266 { 1, 15, 0, 0, 0 },
252b5132
RH		 267
268 /* The FL1 field in a POWER SC form instruction. */
269#define FL1 E + 1
11b37b7b 270 { 4, 12, 0, 0, 0 },
252b5132
RH		 271
272 /* The FL2 field in a POWER SC form instruction. */
273#define FL2 FL1 + 1
11b37b7b 274 { 3, 2, 0, 0, 0 },
252b5132
RH		 275
276 /* The FLM field in an XFL form instruction. */
277#define FLM FL2 + 1
11b37b7b 278 { 8, 17, 0, 0, 0 },
252b5132
RH		 279
280 /* The FRA field in an X or A form instruction. */
281#define FRA FLM + 1
282#define FRA_MASK (0x1f << 16)
11b37b7b 283 { 5, 16, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 284
285 /* The FRB field in an X or A form instruction. */
286#define FRB FRA + 1
287#define FRB_MASK (0x1f << 11)
11b37b7b 288 { 5, 11, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 289
290 /* The FRC field in an A form instruction. */
291#define FRC FRB + 1
292#define FRC_MASK (0x1f << 6)
11b37b7b 293 { 5, 6, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 294
295 /* The FRS field in an X form instruction or the FRT field in a D, X
296 or A form instruction. */
297#define FRS FRC + 1
298#define FRT FRS
11b37b7b 299 { 5, 21, 0, 0, PPC_OPERAND_FPR },
252b5132
RH		 300
301 /* The FXM field in an XFX instruction. */
302#define FXM FRS + 1
303#define FXM_MASK (0xff << 12)
11b37b7b 304 { 8, 12, 0, 0, 0 },
252b5132
RH		 305
306 /* The L field in a D or X form instruction. */
307#define L FXM + 1
11b37b7b 308 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
252b5132
RH		 309
310 /* The LEV field in a POWER SC form instruction. */
311#define LEV L + 1
11b37b7b 312 { 7, 5, 0, 0, 0 },
252b5132
RH		 313
314 /* The LI field in an I form instruction. The lower two bits are
315 forced to zero. */
316#define LI LEV + 1
11b37b7b 317 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 318
319 /* The LI field in an I form instruction when used as an absolute
320 address. */
321#define LIA LI + 1
11b37b7b 322 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 323
6ba045b1
AM		 324 /* The LS field in an X (sync) form instruction. */
325#define LS LIA + 1
326 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
327
252b5132 328 /* The MB field in an M form instruction. */
6ba045b1 329#define MB LS + 1
252b5132 330#define MB_MASK (0x1f << 6)
11b37b7b 331 { 5, 6, 0, 0, 0 },
252b5132
RH		 332
333 /* The ME field in an M form instruction. */
334#define ME MB + 1
335#define ME_MASK (0x1f << 1)
11b37b7b 336 { 5, 1, 0, 0, 0 },
252b5132
RH		 337
338 /* The MB and ME fields in an M form instruction expressed a single
339 operand which is a bitmask indicating which bits to select. This
340 is a two operand form using PPC_OPERAND_NEXT. See the
341 description in opcode/ppc.h for what this means. */
342#define MBE ME + 1
11b37b7b
AM		 343 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
344 { 32, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 345
346 /* The MB or ME field in an MD or MDS form instruction. The high
347 bit is wrapped to the low end. */
348#define MB6 MBE + 2
349#define ME6 MB6
350#define MB6_MASK (0x3f << 5)
11b37b7b 351 { 6, 5, insert_mb6, extract_mb6, 0 },
252b5132 352
9fa87a06
MG		 353 /* The MO field in an mbar instruction. */
354#define MO MB6 + 1
355 { 5, 21, 0, 0, 0 },
356
252b5132
RH		 357 /* The NB field in an X form instruction. The value 32 is stored as
358 0. */
9fa87a06 359#define NB MO + 1
11b37b7b 360 { 6, 11, insert_nb, extract_nb, 0 },
252b5132
RH		 361
362 /* The NSI field in a D form instruction. This is the same as the
363 SI field, only negated. */
364#define NSI NB + 1
365 { 16, 0, insert_nsi, extract_nsi,
11b37b7b 366 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 367
368 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
369#define RA NSI + 1
370#define RA_MASK (0x1f << 16)
11b37b7b 371 { 5, 16, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 372
373 /* The RA field in a D or X form instruction which is an updating
374 load, which means that the RA field may not be zero and may not
375 equal the RT field. */
376#define RAL RA + 1
11b37b7b 377 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
252b5132
RH		 378
379 /* The RA field in an lmw instruction, which has special value
380 restrictions. */
381#define RAM RAL + 1
11b37b7b 382 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
252b5132
RH		 383
384 /* The RA field in a D or X form instruction which is an updating
385 store or an updating floating point load, which means that the RA
386 field may not be zero. */
387#define RAS RAM + 1
11b37b7b 388 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
252b5132
RH		 389
390 /* The RB field in an X, XO, M, or MDS form instruction. */
391#define RB RAS + 1
392#define RB_MASK (0x1f << 11)
11b37b7b 393 { 5, 11, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 394
395 /* The RB field in an X form instruction when it must be the same as
396 the RS field in the instruction. This is used for extended
397 mnemonics like mr. */
398#define RBS RB + 1
11b37b7b 399 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 400
401 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
402 instruction or the RT field in a D, DS, X, XFX or XO form
403 instruction. */
404#define RS RBS + 1
405#define RT RS
406#define RT_MASK (0x1f << 21)
11b37b7b 407 { 5, 21, 0, 0, PPC_OPERAND_GPR },
252b5132
RH		 408
409 /* The SH field in an X or M form instruction. */
410#define SH RS + 1
411#define SH_MASK (0x1f << 11)
11b37b7b 412 { 5, 11, 0, 0, 0 },
252b5132
RH		 413
414 /* The SH field in an MD form instruction. This is split. */
415#define SH6 SH + 1
416#define SH6_MASK ((0x1f << 11) | (1 << 1))
11b37b7b 417 { 6, 1, insert_sh6, extract_sh6, 0 },
252b5132
RH		 418
419 /* The SI field in a D form instruction. */
420#define SI SH6 + 1
11b37b7b 421 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
252b5132
RH		 422
423 /* The SI field in a D form instruction when we accept a wide range
424 of positive values. */
425#define SISIGNOPT SI + 1
11b37b7b 426 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 427
428 /* The SPR field in an XFX form instruction. This is flipped--the
429 lower 5 bits are stored in the upper 5 and vice- versa. */
430#define SPR SISIGNOPT + 1
431#define SPR_MASK (0x3ff << 11)
11b37b7b 432 { 10, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 433
434 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
435#define SPRBAT SPR + 1
436#define SPRBAT_MASK (0x3 << 17)
11b37b7b 437 { 2, 17, 0, 0, 0 },
252b5132
RH		 438
439 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
440#define SPRG SPRBAT + 1
441#define SPRG_MASK (0x3 << 16)
11b37b7b 442 { 2, 16, 0, 0, 0 },
252b5132
RH		 443
444 /* The SR field in an X form instruction. */
445#define SR SPRG + 1
11b37b7b 446 { 4, 16, 0, 0, 0 },
252b5132 447
f5c120c5
MG		 448 /* The STRM field in an X AltiVec form instruction. */
449#define STRM SR + 1
450#define STRM_MASK (0x3 << 21)
451 { 2, 21, 0, 0, 0 },
452
252b5132 453 /* The SV field in a POWER SC form instruction. */
f5c120c5 454#define SV STRM + 1
11b37b7b 455 { 14, 2, 0, 0, 0 },
252b5132
RH		 456
457 /* The TBR field in an XFX form instruction. This is like the SPR
458 field, but it is optional. */
459#define TBR SV + 1
11b37b7b 460 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 461
462 /* The TO field in a D or X form instruction. */
463#define TO TBR + 1
464#define TO_MASK (0x1f << 21)
11b37b7b 465 { 5, 21, 0, 0, 0 },
252b5132
RH		 466
467 /* The U field in an X form instruction. */
468#define U TO + 1
11b37b7b 469 { 4, 12, 0, 0, 0 },
252b5132
RH		 470
471 /* The UI field in a D form instruction. */
472#define UI U + 1
11b37b7b 473 { 16, 0, 0, 0, 0 },
786e2c0f
C		 474
475 /* The VA field in a VA, VX or VXR form instruction. */
476#define VA UI + 1
477#define VA_MASK (0x1f << 16)
6ba045b1 478 { 5, 16, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 479
480 /* The VB field in a VA, VX or VXR form instruction. */
481#define VB VA + 1
482#define VB_MASK (0x1f << 11)
6ba045b1 483 { 5, 11, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 484
485 /* The VC field in a VA form instruction. */
486#define VC VB + 1
487#define VC_MASK (0x1f << 6)
6ba045b1 488 { 5, 6, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 489
490 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
491#define VD VC + 1
492#define VS VD
493#define VD_MASK (0x1f << 21)
6ba045b1 494 { 5, 21, 0, 0, PPC_OPERAND_VR },
786e2c0f
C		 495
496 /* The SIMM field in a VX form instruction. */
497#define SIMM VD + 1
11b37b7b 498 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
786e2c0f
C		 499
500 /* The UIMM field in a VX form instruction. */
501#define UIMM SIMM + 1
11b37b7b 502 { 5, 16, 0, 0, 0 },
786e2c0f
C		 503
504 /* The SHB field in a VA form instruction. */
505#define SHB UIMM + 1
11b37b7b 506 { 4, 6, 0, 0, 0 },
252b5132
RH		 507};
508
509/* The functions used to insert and extract complicated operands. */
510
511/* The BA field in an XL form instruction when it must be the same as
512 the BT field in the same instruction. This operand is marked FAKE.
513 The insertion function just copies the BT field into the BA field,
514 and the extraction function just checks that the fields are the
515 same. */
516
517/*ARGSUSED*/
518static unsigned long
802a735e 519insert_bat (insn, value, dialect, errmsg)
252b5132 520 unsigned long insn;
9aaaa291 521 long value ATTRIBUTE_UNUSED;
802a735e 522 int dialect ATTRIBUTE_UNUSED;
9aaaa291 523 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 524{
525 return insn | (((insn >> 21) & 0x1f) << 16);
526}
527
528static long
802a735e 529extract_bat (insn, dialect, invalid)
252b5132 530 unsigned long insn;
802a735e 531 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 532 int *invalid;
533{
534 if (invalid != (int *) NULL
535 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
536 *invalid = 1;
537 return 0;
538}
539
540/* The BB field in an XL form instruction when it must be the same as
541 the BA field in the same instruction. This operand is marked FAKE.
542 The insertion function just copies the BA field into the BB field,
543 and the extraction function just checks that the fields are the
544 same. */
545
546/*ARGSUSED*/
547static unsigned long
802a735e 548insert_bba (insn, value, dialect, errmsg)
252b5132 549 unsigned long insn;
9aaaa291 550 long value ATTRIBUTE_UNUSED;
802a735e 551 int dialect ATTRIBUTE_UNUSED;
9aaaa291 552 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 553{
554 return insn | (((insn >> 16) & 0x1f) << 11);
555}
556
557static long
802a735e 558extract_bba (insn, dialect, invalid)
252b5132 559 unsigned long insn;
802a735e 560 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 561 int *invalid;
562{
563 if (invalid != (int *) NULL
564 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
565 *invalid = 1;
566 return 0;
567}
568
569/* The BD field in a B form instruction. The lower two bits are
570 forced to zero. */
571
572/*ARGSUSED*/
573static unsigned long
802a735e 574insert_bd (insn, value, dialect, errmsg)
252b5132
RH		 575 unsigned long insn;
576 long value;
802a735e 577 int dialect ATTRIBUTE_UNUSED;
9aaaa291 578 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 579{
580 return insn | (value & 0xfffc);
581}
582
583/*ARGSUSED*/
584static long
802a735e 585extract_bd (insn, dialect, invalid)
252b5132 586 unsigned long insn;
802a735e 587 int dialect ATTRIBUTE_UNUSED;
9aaaa291 588 int *invalid ATTRIBUTE_UNUSED;
252b5132 589{
802a735e 590 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 591}
592
593/* The BD field in a B form instruction when the - modifier is used.
594 This modifier means that the branch is not expected to be taken.
802a735e
AM		 595 For 32 bit targets we set the y bit of the BO field to 1 if the
596 offset is negative. When extracting, we require that the y bit be
597 1 and that the offset be positive, since if the y bit is 0 we just
598 want to print the normal form of the instruction.
599 64 bit targets use two bits, "a", and "t", instead of the "y" bit.
600 at == 10 => not taken, at == 11 => taken. The t bit is 00001 in
601 BO field, the a bit is 00010 for branch on CR(BI) and 01000 for
602 branch on CTR. */
252b5132
RH		 603
604/*ARGSUSED*/
605static unsigned long
802a735e 606insert_bdm (insn, value, dialect, errmsg)
252b5132
RH		 607 unsigned long insn;
608 long value;
802a735e 609 int dialect;
9aaaa291 610 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 611{
802a735e
AM		 612 if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
613 {
614 if ((value & 0x8000) != 0)
615 insn |= 1 << 21;
616 }
617 else
618 {
619 if ((insn & (0x14 << 21)) == (0x04 << 21))
620 insn |= 0x02 << 21;
621 else if ((insn & (0x14 << 21)) == (0x10 << 21))
622 insn |= 0x08 << 21;
623 }
252b5132
RH		 624 return insn | (value & 0xfffc);
625}
626
627static long
802a735e 628extract_bdm (insn, dialect, invalid)
252b5132 629 unsigned long insn;
802a735e 630 int dialect;
252b5132
RH		 631 int *invalid;
632{
802a735e
AM		 633 if (invalid != (int *) NULL)
634 {
635 if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
636 {
637 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
638 *invalid = 1;
639 }
640 else
641 {
642 if ((insn & (0x17 << 21)) != (0x06 << 21)
643 && (insn & (0x1d << 21)) != (0x18 << 21))
644 *invalid = 1;
645 }
646 }
647 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 648}
649
650/* The BD field in a B form instruction when the + modifier is used.
651 This is like BDM, above, except that the branch is expected to be
652 taken. */
653
654/*ARGSUSED*/
655static unsigned long
802a735e 656insert_bdp (insn, value, dialect, errmsg)
252b5132
RH		 657 unsigned long insn;
658 long value;
802a735e 659 int dialect;
9aaaa291 660 const char **errmsg ATTRIBUTE_UNUSED;
252b5132 661{
802a735e
AM		 662 if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
663 {
664 if ((value & 0x8000) == 0)
665 insn |= 1 << 21;
666 }
667 else
668 {
669 if ((insn & (0x14 << 21)) == (0x04 << 21))
670 insn |= 0x03 << 21;
671 else if ((insn & (0x14 << 21)) == (0x10 << 21))
672 insn |= 0x09 << 21;
673 }
252b5132
RH		 674 return insn | (value & 0xfffc);
675}
676
677static long
802a735e 678extract_bdp (insn, dialect, invalid)
252b5132 679 unsigned long insn;
802a735e 680 int dialect;
252b5132
RH		 681 int *invalid;
682{
802a735e
AM		 683 if (invalid != (int *) NULL)
684 {
685 if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
686 {
687 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
688 *invalid = 1;
689 }
690 else
691 {
692 if ((insn & (0x17 << 21)) != (0x07 << 21)
693 && (insn & (0x1d << 21)) != (0x19 << 21))
694 *invalid = 1;
695 }
696 }
697 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 698}
699
700/* Check for legal values of a BO field. */
701
702static int
802a735e 703valid_bo (value, dialect)
252b5132 704 long value;
802a735e 705 int dialect;
252b5132 706{
802a735e 707 if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64)
252b5132 708 {
802a735e
AM		 709 /* Certain encodings have bits that are required to be zero.
710 These are (z must be zero, y may be anything):
711 001zy
712 011zy
713 1z00y
714 1z01y
715 1z1zz
716 */
717 switch (value & 0x14)
718 {
719 default:
720 case 0:
721 return 1;
722 case 0x4:
723 return (value & 0x2) == 0;
724 case 0x10:
725 return (value & 0x8) == 0;
726 case 0x14:
727 return value == 0x14;
728 }
729 }
730 else
731 {
732 /* Certain encodings have bits that are required to be zero.
733 These are (z must be zero, a & t may be anything):
734 0000z
735 0001z
736 0100z
737 0101z
738 001at
739 011at
740 1a00t
741 1a01t
742 1z1zz
743 */
744 if ((value & 0x14) == 0)
745 return (value & 0x1) == 0;
746 else if ((value & 0x14) == 0x14)
747 return value == 0x14;
748 else
749 return 1;
252b5132
RH		 750 }
751}
752
753/* The BO field in a B form instruction. Warn about attempts to set
754 the field to an illegal value. */
755
756static unsigned long
802a735e 757insert_bo (insn, value, dialect, errmsg)
252b5132
RH		 758 unsigned long insn;
759 long value;
802a735e 760 int dialect;
252b5132
RH		 761 const char **errmsg;
762{
763 if (errmsg != (const char **) NULL
802a735e 764 && ! valid_bo (value, dialect))
252b5132
RH		 765 *errmsg = _("invalid conditional option");
766 return insn | ((value & 0x1f) << 21);
767}
768
769static long
802a735e 770extract_bo (insn, dialect, invalid)
252b5132 771 unsigned long insn;
802a735e 772 int dialect;
252b5132
RH		 773 int *invalid;
774{
775 long value;
776
777 value = (insn >> 21) & 0x1f;
778 if (invalid != (int *) NULL
802a735e 779 && ! valid_bo (value, dialect))
252b5132
RH		 780 *invalid = 1;
781 return value;
782}
783
784/* The BO field in a B form instruction when the + or - modifier is
785 used. This is like the BO field, but it must be even. When
786 extracting it, we force it to be even. */
787
788static unsigned long
802a735e 789insert_boe (insn, value, dialect, errmsg)
252b5132
RH		 790 unsigned long insn;
791 long value;
802a735e 792 int dialect;
252b5132
RH		 793 const char **errmsg;
794{
795 if (errmsg != (const char **) NULL)
796 {
802a735e 797 if (! valid_bo (value, dialect))
252b5132
RH		 798 *errmsg = _("invalid conditional option");
799 else if ((value & 1) != 0)
800 *errmsg = _("attempt to set y bit when using + or - modifier");
801 }
802 return insn | ((value & 0x1f) << 21);
803}
804
805static long
802a735e 806extract_boe (insn, dialect, invalid)
252b5132 807 unsigned long insn;
802a735e 808 int dialect;
252b5132
RH		 809 int *invalid;
810{
811 long value;
812
813 value = (insn >> 21) & 0x1f;
814 if (invalid != (int *) NULL
802a735e 815 && ! valid_bo (value, dialect))
252b5132
RH		 816 *invalid = 1;
817 return value & 0x1e;
818}
819
820/* The DS field in a DS form instruction. This is like D, but the
821 lower two bits are forced to zero. */
822
823/*ARGSUSED*/
824static unsigned long
802a735e 825insert_ds (insn, value, dialect, errmsg)
252b5132
RH		 826 unsigned long insn;
827 long value;
802a735e 828 int dialect ATTRIBUTE_UNUSED;
418c1742 829 const char **errmsg;
252b5132 830{
6ba045b1
AM		 831 if ((value & 3) != 0 && errmsg != NULL)
832 *errmsg = _("offset not a multiple of 4");
252b5132
RH		 833 return insn | (value & 0xfffc);
834}
835
836/*ARGSUSED*/
837static long
802a735e 838extract_ds (insn, dialect, invalid)
252b5132 839 unsigned long insn;
802a735e 840 int dialect ATTRIBUTE_UNUSED;
9aaaa291 841 int *invalid ATTRIBUTE_UNUSED;
252b5132 842{
802a735e 843 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 844}
845
418c1742
MG		 846/* The DE field in a DE form instruction. */
847
848/*ARGSUSED*/
849static unsigned long
802a735e 850insert_de (insn, value, dialect, errmsg)
418c1742
MG		 851 unsigned long insn;
852 long value;
802a735e 853 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 854 const char **errmsg;
855{
856 if ((value > 2047 || value < -2048) && errmsg != NULL)
857 *errmsg = _("offset not between -2048 and 2047");
858 return insn | ((value << 4) & 0xfff0);
859}
860
861/*ARGSUSED*/
862static long
802a735e 863extract_de (insn, dialect, invalid)
418c1742 864 unsigned long insn;
802a735e 865 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 866 int *invalid ATTRIBUTE_UNUSED;
867{
868 return (insn & 0xfff0) >> 4;
869}
870
871/* The DES field in a DES form instruction. */
872
873/*ARGSUSED*/
874static unsigned long
802a735e 875insert_des (insn, value, dialect, errmsg)
418c1742
MG		 876 unsigned long insn;
877 long value;
802a735e 878 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 879 const char **errmsg;
880{
881 if ((value > 8191 || value < -8192) && errmsg != NULL)
882 *errmsg = _("offset not between -8192 and 8191");
883 else if ((value & 3) != 0 && errmsg != NULL)
884 *errmsg = _("offset not a multiple of 4");
885 return insn | ((value << 2) & 0xfff0);
886}
887
888/*ARGSUSED*/
889static long
802a735e 890extract_des (insn, dialect, invalid)
418c1742 891 unsigned long insn;
802a735e 892 int dialect ATTRIBUTE_UNUSED;
418c1742
MG		 893 int *invalid ATTRIBUTE_UNUSED;
894{
802a735e 895 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
418c1742
MG		 896}
897
252b5132
RH		 898/* The LI field in an I form instruction. The lower two bits are
899 forced to zero. */
900
901/*ARGSUSED*/
902static unsigned long
802a735e 903insert_li (insn, value, dialect, errmsg)
252b5132
RH		 904 unsigned long insn;
905 long value;
802a735e 906 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 907 const char **errmsg;
908{
909 if ((value & 3) != 0 && errmsg != (const char **) NULL)
910 *errmsg = _("ignoring least significant bits in branch offset");
911 return insn | (value & 0x3fffffc);
912}
913
914/*ARGSUSED*/
915static long
802a735e 916extract_li (insn, dialect, invalid)
252b5132 917 unsigned long insn;
802a735e 918 int dialect ATTRIBUTE_UNUSED;
9aaaa291 919 int *invalid ATTRIBUTE_UNUSED;
252b5132 920{
802a735e 921 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
252b5132
RH		 922}
923
924/* The MB and ME fields in an M form instruction expressed as a single
925 operand which is itself a bitmask. The extraction function always
926 marks it as invalid, since we never want to recognize an
927 instruction which uses a field of this type. */
928
929static unsigned long
802a735e 930insert_mbe (insn, value, dialect, errmsg)
252b5132
RH		 931 unsigned long insn;
932 long value;
802a735e 933 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 934 const char **errmsg;
935{
936 unsigned long uval, mask;
937 int mb, me, mx, count, last;
938
939 uval = value;
940
941 if (uval == 0)
942 {
943 if (errmsg != (const char **) NULL)
944 *errmsg = _("illegal bitmask");
945 return insn;
946 }
947
948 mb = 0;
949 me = 32;
950 if ((uval & 1) != 0)
951 last = 1;
952 else
953 last = 0;
954 count = 0;
955
956 /* mb: location of last 0->1 transition */
957 /* me: location of last 1->0 transition */
958 /* count: # transitions */
959
3eb9799d 960 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 961 {
962 if ((uval & mask) && !last)
963 {
964 ++count;
965 mb = mx;
966 last = 1;
967 }
968 else if (!(uval & mask) && last)
969 {
970 ++count;
971 me = mx;
972 last = 0;
973 }
974 }
975 if (me == 0)
976 me = 32;
977
978 if (count != 2 && (count != 0 || ! last))
979 {
980 if (errmsg != (const char **) NULL)
981 *errmsg = _("illegal bitmask");
982 }
983
984 return insn | (mb << 6) | ((me - 1) << 1);
985}
986
987static long
802a735e 988extract_mbe (insn, dialect, invalid)
252b5132 989 unsigned long insn;
802a735e 990 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 991 int *invalid;
992{
993 long ret;
994 int mb, me;
995 int i;
996
997 if (invalid != (int *) NULL)
998 *invalid = 1;
999
1000 mb = (insn >> 6) & 0x1f;
1001 me = (insn >> 1) & 0x1f;
1002 if (mb < me + 1)
1003 {
1004 ret = 0;
1005 for (i = mb; i <= me; i++)
1006 ret |= (long) 1 << (31 - i);
1007 }
1008 else if (mb == me + 1)
1009 ret = ~0;
1010 else /* (mb > me + 1) */
1011 {
1012 ret = ~ (long) 0;
1013 for (i = me + 1; i < mb; i++)
1014 ret &= ~ ((long) 1 << (31 - i));
1015 }
1016 return ret;
1017}
1018
1019/* The MB or ME field in an MD or MDS form instruction. The high bit
1020 is wrapped to the low end. */
1021
1022/*ARGSUSED*/
1023static unsigned long
802a735e 1024insert_mb6 (insn, value, dialect, errmsg)
252b5132
RH		 1025 unsigned long insn;
1026 long value;
802a735e 1027 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1028 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1029{
1030 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1031}
1032
1033/*ARGSUSED*/
1034static long
802a735e 1035extract_mb6 (insn, dialect, invalid)
252b5132 1036 unsigned long insn;
802a735e 1037 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1038 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1039{
1040 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1041}
1042
1043/* The NB field in an X form instruction. The value 32 is stored as
1044 0. */
1045
1046static unsigned long
802a735e 1047insert_nb (insn, value, dialect, errmsg)
252b5132
RH		 1048 unsigned long insn;
1049 long value;
802a735e 1050 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1051 const char **errmsg;
1052{
1053 if (value < 0 || value > 32)
1054 *errmsg = _("value out of range");
1055 if (value == 32)
1056 value = 0;
1057 return insn | ((value & 0x1f) << 11);
1058}
1059
1060/*ARGSUSED*/
1061static long
802a735e 1062extract_nb (insn, dialect, invalid)
252b5132 1063 unsigned long insn;
802a735e 1064 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1065 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1066{
1067 long ret;
1068
1069 ret = (insn >> 11) & 0x1f;
1070 if (ret == 0)
1071 ret = 32;
1072 return ret;
1073}
1074
1075/* The NSI field in a D form instruction. This is the same as the SI
1076 field, only negated. The extraction function always marks it as
1077 invalid, since we never want to recognize an instruction which uses
1078 a field of this type. */
1079
1080/*ARGSUSED*/
1081static unsigned long
802a735e 1082insert_nsi (insn, value, dialect, errmsg)
252b5132
RH		 1083 unsigned long insn;
1084 long value;
802a735e 1085 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1086 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1087{
1088 return insn | ((- value) & 0xffff);
1089}
1090
1091static long
802a735e 1092extract_nsi (insn, dialect, invalid)
252b5132 1093 unsigned long insn;
802a735e 1094 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1095 int *invalid;
1096{
1097 if (invalid != (int *) NULL)
1098 *invalid = 1;
802a735e 1099 return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1100}
1101
1102/* The RA field in a D or X form instruction which is an updating
1103 load, which means that the RA field may not be zero and may not
1104 equal the RT field. */
1105
1106static unsigned long
802a735e 1107insert_ral (insn, value, dialect, errmsg)
252b5132
RH		 1108 unsigned long insn;
1109 long value;
802a735e 1110 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1111 const char **errmsg;
1112{
1113 if (value == 0
1114 || (unsigned long) value == ((insn >> 21) & 0x1f))
1115 *errmsg = "invalid register operand when updating";
1116 return insn | ((value & 0x1f) << 16);
1117}
1118
1119/* The RA field in an lmw instruction, which has special value
1120 restrictions. */
1121
1122static unsigned long
802a735e 1123insert_ram (insn, value, dialect, errmsg)
252b5132
RH		 1124 unsigned long insn;
1125 long value;
802a735e 1126 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1127 const char **errmsg;
1128{
1129 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1130 *errmsg = _("index register in load range");
1131 return insn | ((value & 0x1f) << 16);
1132}
1133
1134/* The RA field in a D or X form instruction which is an updating
1135 store or an updating floating point load, which means that the RA
1136 field may not be zero. */
1137
1138static unsigned long
802a735e 1139insert_ras (insn, value, dialect, errmsg)
252b5132
RH		 1140 unsigned long insn;
1141 long value;
802a735e 1142 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1143 const char **errmsg;
1144{
1145 if (value == 0)
1146 *errmsg = _("invalid register operand when updating");
1147 return insn | ((value & 0x1f) << 16);
1148}
1149
1150/* The RB field in an X form instruction when it must be the same as
1151 the RS field in the instruction. This is used for extended
1152 mnemonics like mr. This operand is marked FAKE. The insertion
1153 function just copies the BT field into the BA field, and the
1154 extraction function just checks that the fields are the same. */
1155
1156/*ARGSUSED*/
1157static unsigned long
802a735e 1158insert_rbs (insn, value, dialect, errmsg)
252b5132 1159 unsigned long insn;
9aaaa291 1160 long value ATTRIBUTE_UNUSED;
802a735e 1161 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1162 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1163{
1164 return insn | (((insn >> 21) & 0x1f) << 11);
1165}
1166
1167static long
802a735e 1168extract_rbs (insn, dialect, invalid)
252b5132 1169 unsigned long insn;
802a735e 1170 int dialect ATTRIBUTE_UNUSED;
252b5132
RH		 1171 int *invalid;
1172{
1173 if (invalid != (int *) NULL
1174 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1175 *invalid = 1;
1176 return 0;
1177}
1178
1179/* The SH field in an MD form instruction. This is split. */
1180
1181/*ARGSUSED*/
1182static unsigned long
802a735e 1183insert_sh6 (insn, value, dialect, errmsg)
252b5132
RH		 1184 unsigned long insn;
1185 long value;
802a735e 1186 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1187 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1188{
1189 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1190}
1191
1192/*ARGSUSED*/
1193static long
802a735e 1194extract_sh6 (insn, dialect, invalid)
252b5132 1195 unsigned long insn;
802a735e 1196 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1197 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1198{
1199 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1200}
1201
1202/* The SPR field in an XFX form instruction. This is flipped--the
1203 lower 5 bits are stored in the upper 5 and vice- versa. */
1204
1205static unsigned long
802a735e 1206insert_spr (insn, value, dialect, errmsg)
252b5132
RH		 1207 unsigned long insn;
1208 long value;
802a735e 1209 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1210 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1211{
1212 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1213}
1214
1215static long
802a735e 1216extract_spr (insn, dialect, invalid)
252b5132 1217 unsigned long insn;
802a735e 1218 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1219 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1220{
1221 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1222}
1223
1224/* The TBR field in an XFX instruction. This is just like SPR, but it
1225 is optional. When TBR is omitted, it must be inserted as 268 (the
1226 magic number of the TB register). These functions treat 0
1227 (indicating an omitted optional operand) as 268. This means that
1228 ``mftb 4,0'' is not handled correctly. This does not matter very
1229 much, since the architecture manual does not define mftb as
1230 accepting any values other than 268 or 269. */
1231
1232#define TB (268)
1233
1234static unsigned long
802a735e 1235insert_tbr (insn, value, dialect, errmsg)
252b5132
RH		 1236 unsigned long insn;
1237 long value;
802a735e 1238 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1239 const char **errmsg ATTRIBUTE_UNUSED;
252b5132
RH		 1240{
1241 if (value == 0)
1242 value = TB;
1243 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1244}
1245
1246static long
802a735e 1247extract_tbr (insn, dialect, invalid)
252b5132 1248 unsigned long insn;
802a735e 1249 int dialect ATTRIBUTE_UNUSED;
9aaaa291 1250 int *invalid ATTRIBUTE_UNUSED;
252b5132
RH		 1251{
1252 long ret;
1253
1254 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1255 if (ret == TB)
1256 ret = 0;
1257 return ret;
1258}
1259\f
1260/* Macros used to form opcodes. */
1261
1262/* The main opcode. */
1263#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1264#define OP_MASK OP (0x3f)
1265
1266/* The main opcode combined with a trap code in the TO field of a D
1267 form instruction. Used for extended mnemonics for the trap
1268 instructions. */
1269#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1270#define OPTO_MASK (OP_MASK | TO_MASK)
1271
1272/* The main opcode combined with a comparison size bit in the L field
1273 of a D form or X form instruction. Used for extended mnemonics for
1274 the comparison instructions. */
1275#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1276#define OPL_MASK OPL (0x3f,1)
1277
1278/* An A form instruction. */
1279#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1280#define A_MASK A (0x3f, 0x1f, 1)
1281
1282/* An A_MASK with the FRB field fixed. */
1283#define AFRB_MASK (A_MASK | FRB_MASK)
1284
1285/* An A_MASK with the FRC field fixed. */
1286#define AFRC_MASK (A_MASK | FRC_MASK)
1287
1288/* An A_MASK with the FRA and FRC fields fixed. */
1289#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1290
1291/* A B form instruction. */
1292#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1293#define B_MASK B (0x3f, 1, 1)
1294
1295/* A B form instruction setting the BO field. */
1296#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1297#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1298
1299/* A BBO_MASK with the y bit of the BO field removed. This permits
1300 matching a conditional branch regardless of the setting of the y
802a735e
AM		 1301 bit. Similarly for the 'at' bits used for 64 bit branch hints. */
1302#define Y_MASK (((unsigned long) 1) << 21)
1303#define AT1_MASK (((unsigned long) 3) << 21)
1304#define AT2_MASK (((unsigned long) 9) << 21)
1305#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1306#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1307
1308/* A B form instruction setting the BO field and the condition bits of
1309 the BI field. */
1310#define BBOCB(op, bo, cb, aa, lk) \
1311 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1312#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1313
1314/* A BBOCB_MASK with the y bit of the BO field removed. */
1315#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1316#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1317#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1318
1319/* A BBOYCB_MASK in which the BI field is fixed. */
1320#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1321#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132
RH		 1322
1323/* The main opcode mask with the RA field clear. */
1324#define DRA_MASK (OP_MASK | RA_MASK)
1325
1326/* A DS form instruction. */
1327#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1328#define DS_MASK DSO (0x3f, 3)
1329
418c1742
MG		 1330/* A DE form instruction. */
1331#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1332#define DE_MASK DEO (0x3e, 0xf)
1333
252b5132
RH		 1334/* An M form instruction. */
1335#define M(op, rc) (OP (op) | ((rc) & 1))
1336#define M_MASK M (0x3f, 1)
1337
1338/* An M form instruction with the ME field specified. */
1339#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1340
1341/* An M_MASK with the MB and ME fields fixed. */
1342#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1343
1344/* An M_MASK with the SH and ME fields fixed. */
1345#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1346
1347/* An MD form instruction. */
1348#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1349#define MD_MASK MD (0x3f, 0x7, 1)
1350
1351/* An MD_MASK with the MB field fixed. */
1352#define MDMB_MASK (MD_MASK | MB6_MASK)
1353
1354/* An MD_MASK with the SH field fixed. */
1355#define MDSH_MASK (MD_MASK | SH6_MASK)
1356
1357/* An MDS form instruction. */
1358#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1359#define MDS_MASK MDS (0x3f, 0xf, 1)
1360
1361/* An MDS_MASK with the MB field fixed. */
1362#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1363
1364/* An SC form instruction. */
1365#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1366#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1367
786e2c0f
C		 1368/* An VX form instruction. */
1369#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1370
1371/* The mask for an VX form instruction. */
1372#define VX_MASK VX(0x3f, 0x7ff)
1373
1374/* An VA form instruction. */
2613489e 1375#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f
C		 1376
1377/* The mask for an VA form instruction. */
2613489e 1378#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f
C		 1379
1380/* An VXR form instruction. */
1381#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1382
1383/* The mask for a VXR form instruction. */
1384#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1385
252b5132
RH		 1386/* An X form instruction. */
1387#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1388
1389/* An X form instruction with the RC bit specified. */
1390#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1391
1392/* The mask for an X form instruction. */
1393#define X_MASK XRC (0x3f, 0x3ff, 1)
1394
1395/* An X_MASK with the RA field fixed. */
1396#define XRA_MASK (X_MASK | RA_MASK)
1397
1398/* An X_MASK with the RB field fixed. */
1399#define XRB_MASK (X_MASK | RB_MASK)
1400
1401/* An X_MASK with the RT field fixed. */
1402#define XRT_MASK (X_MASK | RT_MASK)
1403
1404/* An X_MASK with the RA and RB fields fixed. */
1405#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1406
1407/* An X_MASK with the RT and RA fields fixed. */
1408#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1409
1410/* An X form comparison instruction. */
1411#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1412
1413/* The mask for an X form comparison instruction. */
1414#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1415
1416/* The mask for an X form comparison instruction with the L field
1417 fixed. */
1418#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1419
1420/* An X form trap instruction with the TO field specified. */
1421#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1422#define XTO_MASK (X_MASK | TO_MASK)
1423
e0c21649
GK		 1424/* An X form tlb instruction with the SH field specified. */
1425#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1426#define XTLB_MASK (X_MASK | SH_MASK)
1427
6ba045b1
AM		 1428/* An X form sync instruction. */
1429#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1430
1431/* An X form sync instruction with everything filled in except the LS field. */
1432#define XSYNC_MASK (0xff9fffff)
1433
f5c120c5
MG		 1434/* An X form AltiVec dss instruction. */
1435#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1436#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1437
252b5132
RH		 1438/* An XFL form instruction. */
1439#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1440#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1441
1442/* An XL form instruction with the LK field set to 0. */
1443#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1444
1445/* An XL form instruction which uses the LK field. */
1446#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1447
1448/* The mask for an XL form instruction. */
1449#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1450
1451/* An XL form instruction which explicitly sets the BO field. */
1452#define XLO(op, bo, xop, lk) \
1453 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1454#define XLO_MASK (XL_MASK | BO_MASK)
1455
1456/* An XL form instruction which explicitly sets the y bit of the BO
1457 field. */
1458#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1459#define XLYLK_MASK (XL_MASK | Y_MASK)
1460
1461/* An XL form instruction which sets the BO field and the condition
1462 bits of the BI field. */
1463#define XLOCB(op, bo, cb, xop, lk) \
1464 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1465#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1466
1467/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1468#define XLBB_MASK (XL_MASK | BB_MASK)
1469#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1470#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1471
1472/* An XL_MASK with the BO and BB fields fixed. */
1473#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1474
1475/* An XL_MASK with the BO, BI and BB fields fixed. */
1476#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1477
1478/* An XO form instruction. */
1479#define XO(op, xop, oe, rc) \
1480 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1481#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1482
1483/* An XO_MASK with the RB field fixed. */
1484#define XORB_MASK (XO_MASK | RB_MASK)
1485
1486/* An XS form instruction. */
1487#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1488#define XS_MASK XS (0x3f, 0x1ff, 1)
1489
1490/* A mask for the FXM version of an XFX form instruction. */
1491#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1492
1493/* An XFX form instruction with the FXM field filled in. */
1494#define XFXM(op, xop, fxm) \
1495 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1496
1497/* An XFX form instruction with the SPR field filled in. */
1498#define XSPR(op, xop, spr) \
1499 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1500#define XSPR_MASK (X_MASK | SPR_MASK)
1501
1502/* An XFX form instruction with the SPR field filled in except for the
1503 SPRBAT field. */
1504#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1505
1506/* An XFX form instruction with the SPR field filled in except for the
1507 SPRG field. */
1508#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1509
1510/* An X form instruction with everything filled in except the E field. */
1511#define XE_MASK (0xffff7fff)
1512
1513/* The BO encodings used in extended conditional branch mnemonics. */
1514#define BODNZF (0x0)
1515#define BODNZFP (0x1)
1516#define BODZF (0x2)
1517#define BODZFP (0x3)
252b5132
RH		 1518#define BODNZT (0x8)
1519#define BODNZTP (0x9)
1520#define BODZT (0xa)
1521#define BODZTP (0xb)
802a735e
AM		 1522
1523#define BOF (0x4)
1524#define BOFP (0x5)
1525#define BOFM64 (0x6)
1526#define BOFP64 (0x7)
252b5132
RH		 1527#define BOT (0xc)
1528#define BOTP (0xd)
802a735e
AM		 1529#define BOTM64 (0xe)
1530#define BOTP64 (0xf)
1531
252b5132
RH		 1532#define BODNZ (0x10)
1533#define BODNZP (0x11)
1534#define BODZ (0x12)
1535#define BODZP (0x13)
802a735e
AM		 1536#define BODNZM64 (0x18)
1537#define BODNZP64 (0x19)
1538#define BODZM64 (0x1a)
1539#define BODZP64 (0x1b)
1540
252b5132
RH		 1541#define BOU (0x14)
1542
1543/* The BI condition bit encodings used in extended conditional branch
1544 mnemonics. */
1545#define CBLT (0)
1546#define CBGT (1)
1547#define CBEQ (2)
1548#define CBSO (3)
1549
1550/* The TO encodings used in extended trap mnemonics. */
1551#define TOLGT (0x1)
1552#define TOLLT (0x2)
1553#define TOEQ (0x4)
1554#define TOLGE (0x5)
1555#define TOLNL (0x5)
1556#define TOLLE (0x6)
1557#define TOLNG (0x6)
1558#define TOGT (0x8)
1559#define TOGE (0xc)
1560#define TONL (0xc)
1561#define TOLT (0x10)
1562#define TOLE (0x14)
1563#define TONG (0x14)
1564#define TONE (0x18)
1565#define TOU (0x1f)
1566\f
1567/* Smaller names for the flags so each entry in the opcodes table will
1568 fit on a single line. */
1569#undef PPC
1570#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1571#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
802a735e
AM		 1572#define PPCCOM32 PPC_OPCODE_32 | PPCCOM
1573#define PPCCOM64 PPC_OPCODE_64 | PPCCOM
1574#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1575#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
252b5132 1576#define PPCONLY PPC_OPCODE_PPC
418c1742 1577#define PPC403 PPC_OPCODE_403
e0c21649 1578#define PPC405 PPC403
252b5132
RH		 1579#define PPC750 PPC
1580#define PPC860 PPC
1cbbfaf9 1581#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
252b5132
RH		 1582#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1583#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1584#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1585#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1586#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1587#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1588#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1589#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1590#define MFDEC1 PPC_OPCODE_POWER
1591#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
418c1742
MG		 1592#define BOOKE PPC_OPCODE_BOOKE
1593#define BOOKE64 PPC_OPCODE_BOOKE64
252b5132
RH		 1594\f
1595/* The opcode table.
1596
1597 The format of the opcode table is:
1598
1599 NAME OPCODE MASK FLAGS { OPERANDS }
1600
1601 NAME is the name of the instruction.
1602 OPCODE is the instruction opcode.
1603 MASK is the opcode mask; this is used to tell the disassembler
1604 which bits in the actual opcode must match OPCODE.
1605 FLAGS are flags indicated what processors support the instruction.
1606 OPERANDS is the list of operands.
1607
1608 The disassembler reads the table in order and prints the first
1609 instruction which matches, so this table is sorted to put more
1610 specific instructions before more general instructions. It is also
1611 sorted by major opcode. */
1612
1613const struct powerpc_opcode powerpc_opcodes[] = {
1614{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1615{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1616{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1617{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1618{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1619{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1620{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1621{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1622{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1623{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1624{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1625{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1626{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1627{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1628{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1629
1630{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1631{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1632{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1633{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1634{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1635{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1636{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1637{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1638{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1639{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1640{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1641{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1642{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1643{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1644{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1645{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1646{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1647{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1648{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1649{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1650{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1651{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1652{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1653{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1654{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1655{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1656{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1657{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1658{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1659{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649
GK		 1660
1661{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1662{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1663{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1664{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1665{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1666{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1667{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1668{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1669{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1670{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1671{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1672{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1673{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1674{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1675{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1676{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1677{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1678{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1679{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1680{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1681{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1682{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1683{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1684{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1685{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1686{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1687{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1688{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1689{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1690{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1691{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1692{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1693{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1694{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1695{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1696{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1697{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1698{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1699{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1700{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1701{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1702{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1703{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1704{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1705{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1706{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1707{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1708{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1709{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1710{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1711{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1712{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1713{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1714{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1715{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1716{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1717{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1718{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1719{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1720{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1721{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1722{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1723{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1724{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1725{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1726{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1727{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1728{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1729{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1730{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1731{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1732{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1733{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1734{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1735{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1736{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1737{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1738{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1739{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1740{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1741{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1742{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1743{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1744{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
786e2c0f 1745{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 1746{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
786e2c0f
C		 1747{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1748{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1749{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1750{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1751{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1752{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1753{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1754{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1755{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1756{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1757{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1758{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1759{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1760{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1761{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1762{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1763{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1764{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1765{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1766{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1767{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1768{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1769{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1770{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1771{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1772{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1773{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1774{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1775{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1776{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1777{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1778{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1779{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1780{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1781{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1782{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1783{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1784{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1785{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1786{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1787{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1788{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1789{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1790{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1791{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1792{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1793{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1794{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1795{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1796{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1797{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1798{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1799{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1800{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1801{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1802{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1803{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1804{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1805{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1806{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1807{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1808{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1809{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1810{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1811{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1812{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1813{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1814{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1815{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1816{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1817{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1818{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1819{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1820{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1821{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1822{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1823{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1824{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 1825{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1826{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1827{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 1828{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1829{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1830{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1831{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1832{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1833{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1834{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1835{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1836{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1837{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1838{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1839{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1840{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1841{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1842{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
1843{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
1844{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
1845{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
1846{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
1847{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
1848{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
1849{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
1850{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
1851{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
1852{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
1853{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
1854{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
1855{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
1856{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
1857{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
1858{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1859{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
1860{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
1861{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
1862{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
1863{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 1864{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 1865{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1866{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1867{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
1868{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
1869{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
1870{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1871{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
1872{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
1873{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
1874{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
1875{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
1876{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
1877{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
1878{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
1879{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
1880{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
1881{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
1882{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
1883{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
1884{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
1885{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
1886{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
1887{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
1888{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
1889{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
1890{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
1891{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
1892{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
1893{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
1894{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
1895{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
1896{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
1897{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
1898{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
1899{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
1900{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
1901{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132
RH		 1902
1903{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
1904{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
1905
1906{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
1907{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
1908
1909{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
1910
418c1742
MG		 1911{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
1912{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
1913{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
1914{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
1915
252b5132
RH		 1916{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
1917{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
1918{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
1919{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
1920
1921{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
1922{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
1923{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
1924{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
1925
1926{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
1927{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
1928{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
1929
1930{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
1931{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
1932{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
1933
1934{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
1935{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
1936{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
1937{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
1938{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
1939{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
1940
1941{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
1942{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
1943{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
1944{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
1945{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
1946
802a735e
AM		 1947{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1948{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1949{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
1950{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
1951{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1952{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1953{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
1954{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
1955{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1956{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1957{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
1958{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
1959{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1960{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1961{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
1962{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
1963{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
1964{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
1965{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
1966{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
1967{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
1968{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
1969{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
1970{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
1971{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
1972{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
1973{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
1974{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
1975{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1976{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1977{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1978{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1979{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1980{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1981{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1982{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1983{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1984{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1985{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1986{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1987{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1988{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1989{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
1990{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
1991{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
1992{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
1993{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1994{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1995{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
1996{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
1997{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
1998{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
1999{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2000{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2001{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2002{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2003{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2004{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2005{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2006{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2007{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2008{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2009{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2010{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2011{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2012{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2013{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2014{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2015{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2016{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2017{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2018{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2019{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2020{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2021{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2022{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2023{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2024{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2025{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2026{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2027{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2028{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2029{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2030{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2031{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2032{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2033{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2034{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2035{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2036{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2037{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2038{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2039{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2040{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2041{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2042{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2043{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2044{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2045{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2046{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2047{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2048{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2049{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2050{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2051{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2052{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2053{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2054{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2055{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2056{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2057{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2058{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2059{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2060{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2061{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2062{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2063{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2064{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2065{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2066{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2067{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2068{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2069{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2070{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2071{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2072{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2073{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2074{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2075{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2076{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2077{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2078{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2079{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2080{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2081{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2082{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2083{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2084{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2085{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2086{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2087{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2088{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2089{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2090{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2091{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2092{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2093{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2094{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2095{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2096{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2097{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2098{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2099{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2100{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2101{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2102{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2103{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2104{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2105{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2106{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2107{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2108{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2109{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2110{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2111{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2112{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2113{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2114{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2115{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2116{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2117{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2118{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2119{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } },
2120{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2121{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2122{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } },
2123{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2124{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2125{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2126{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2127{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2128{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2129{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2130{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2131{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } },
2132{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2133{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2134{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } },
2135{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2136{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2137{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2138{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2139{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2140{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2141{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2142{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2143{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2144{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2145{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2146{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2147{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2148{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2149{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2150{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2151{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2152{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2153{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2154{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2155{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2156{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2157{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2158{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2159{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2160{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2161{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2162{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2163{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2164{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2165{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2166{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2167{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2168{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2169{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2170{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2171{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2172{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2173{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2174{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2175{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } },
2176{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2177{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2178{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } },
2179{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2180{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2181{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2182{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2183{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2184{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2185{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2186{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2187{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } },
2188{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2189{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2190{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } },
2191{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } },
252b5132 2192{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
802a735e
AM		 2193{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2194{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2195{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2196{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } },
2197{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } },
252b5132 2198{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2199{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2200{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2201{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2202{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2203{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2204{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2205{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2206{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2207{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2208{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2209{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2210{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2211
2212{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2213{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2214{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2215{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2216{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2217
418c1742
MG		 2218{ "b", B(18,0,0), B_MASK, COM, { LI } },
2219{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2220{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2221{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132
RH		 2222
2223{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
2224
2225{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2226{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2227{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2228{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2229{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
802a735e
AM		 2230{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2231{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2232{ "bdnzlr-", XLO(19,BODNZM64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } },
2233{ "bdnzlr+", XLO(19,BODNZP64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } },
252b5132 2234{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
802a735e
AM		 2235{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2236{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2237{ "bdnzlrl-",XLO(19,BODNZM64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } },
2238{ "bdnzlrl+",XLO(19,BODNZP64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } },
252b5132 2239{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
802a735e
AM		 2240{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2241{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2242{ "bdzlr-", XLO(19,BODZM64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } },
2243{ "bdzlr+", XLO(19,BODZP64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } },
252b5132 2244{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
802a735e
AM		 2245{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2246{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } },
2247{ "bdzlrl-", XLO(19,BODZM64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } },
2248{ "bdzlrl+", XLO(19,BODZP64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } },
252b5132 2249{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2250{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2251{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2252{ "bltlr-", XLOCB(19,BOTM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2253{ "bltlr+", XLOCB(19,BOTP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2254{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2255{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2256{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2257{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2258{ "bltlrl-", XLOCB(19,BOTM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2259{ "bltlrl+", XLOCB(19,BOTP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2260{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2261{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2262{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2263{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2264{ "bgtlr-", XLOCB(19,BOTM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2265{ "bgtlr+", XLOCB(19,BOTP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2266{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2267{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2268{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2269{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2270{ "bgtlrl-", XLOCB(19,BOTM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2271{ "bgtlrl+", XLOCB(19,BOTP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2272{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2273{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2274{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2275{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2276{ "beqlr-", XLOCB(19,BOTM64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2277{ "beqlr+", XLOCB(19,BOTP64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2278{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2279{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2280{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2281{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2282{ "beqlrl-", XLOCB(19,BOTM64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2283{ "beqlrl+", XLOCB(19,BOTP64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2284{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2285{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2286{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2287{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2288{ "bsolr-", XLOCB(19,BOTM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2289{ "bsolr+", XLOCB(19,BOTP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2290{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2291{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2292{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2293{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2294{ "bsolrl-", XLOCB(19,BOTM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2295{ "bsolrl+", XLOCB(19,BOTP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2296{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2297{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2298{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2299{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2300{ "bunlr-", XLOCB(19,BOTM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2301{ "bunlr+", XLOCB(19,BOTP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2302{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2303{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2304{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2305{ "bunlrl-", XLOCB(19,BOTM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2306{ "bunlrl+", XLOCB(19,BOTP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2307{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2308{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2309{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2310{ "bgelr-", XLOCB(19,BOFM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2311{ "bgelr+", XLOCB(19,BOFP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2312{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2313{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2314{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2315{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2316{ "bgelrl-", XLOCB(19,BOFM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2317{ "bgelrl+", XLOCB(19,BOFP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2318{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2319{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2320{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2321{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2322{ "bnllr-", XLOCB(19,BOFM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2323{ "bnllr+", XLOCB(19,BOFP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2324{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2325{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2326{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2327{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2328{ "bnllrl-", XLOCB(19,BOFM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2329{ "bnllrl+", XLOCB(19,BOFP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2330{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2331{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2332{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2333{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2334{ "blelr-", XLOCB(19,BOFM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2335{ "blelr+", XLOCB(19,BOFP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2336{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2337{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2338{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2339{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2340{ "blelrl-", XLOCB(19,BOFM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2341{ "blelrl+", XLOCB(19,BOFP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2342{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2343{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2344{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2345{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2346{ "bnglr-", XLOCB(19,BOFM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2347{ "bnglr+", XLOCB(19,BOFP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2348{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2349{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2350{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2351{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2352{ "bnglrl-", XLOCB(19,BOFM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2353{ "bnglrl+", XLOCB(19,BOFP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2354{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2355{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2356{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2357{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2358{ "bnelr-", XLOCB(19,BOFM64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2359{ "bnelr+", XLOCB(19,BOFP64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2360{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2361{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2362{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2363{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2364{ "bnelrl-", XLOCB(19,BOFM64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2365{ "bnelrl+", XLOCB(19,BOFP64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2366{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2367{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2368{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2369{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2370{ "bnslr-", XLOCB(19,BOFM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2371{ "bnslr+", XLOCB(19,BOFP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2372{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2373{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2374{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2375{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2376{ "bnslrl-", XLOCB(19,BOFM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2377{ "bnslrl+", XLOCB(19,BOFP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132
RH		 2378{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2379{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2380{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2381{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2382{ "bnulr-", XLOCB(19,BOFM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2383{ "bnulr+", XLOCB(19,BOFP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2384{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2385{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2386{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2387{ "bnulrl-", XLOCB(19,BOFM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2388{ "bnulrl+", XLOCB(19,BOFP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2389{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2390{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2391{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2392{ "btlr-", XLO(19,BOTM64,16,0), XLBOBB_MASK, PPCCOM64, { BI } },
2393{ "btlr+", XLO(19,BOTP64,16,0), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132
RH		 2394{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2395{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2396{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2397{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2398{ "btlrl-", XLO(19,BOTM64,16,1), XLBOBB_MASK, PPCCOM64, { BI } },
2399{ "btlrl+", XLO(19,BOTP64,16,1), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132
RH		 2400{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2401{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2402{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2403{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2404{ "bflr-", XLO(19,BOFM64,16,0), XLBOBB_MASK, PPCCOM64, { BI } },
2405{ "bflr+", XLO(19,BOFP64,16,0), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132
RH		 2406{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2407{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2408{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2409{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2410{ "bflrl-", XLO(19,BOFM64,16,1), XLBOBB_MASK, PPCCOM64, { BI } },
2411{ "bflrl+", XLO(19,BOFP64,16,1), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132
RH		 2412{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2413{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2414{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2415{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132 2416{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2417{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2418{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132 2419{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2420{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2421{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132 2422{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2423{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2424{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132 2425{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2426{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2427{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132 2428{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2429{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2430{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132 2431{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2432{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
2433{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132 2434{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2435{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
2436{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } },
252b5132
RH		 2437{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2438{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2439{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2440{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2441{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2442{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 2443{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2444{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2445{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2446{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 2447
f509565f
GK		 2448{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2449
252b5132
RH		 2450{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2451{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2452
2453{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
e0c21649 2454{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
9fa87a06 2455{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
252b5132
RH		 2456
2457{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2458
2459{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2460
2461{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2462{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2463
2464{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2465{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2466
2467{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2468
2469{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2470
2471{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2472{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2473
2474{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2475
2476{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2477{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2478
2479{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2480{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2481{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2482{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2483{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2484{ "bltctr-", XLOCB(19,BOTM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2485{ "bltctr+", XLOCB(19,BOTP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2486{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2487{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2488{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2489{ "bltctrl-",XLOCB(19,BOTM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2490{ "bltctrl+",XLOCB(19,BOTP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2491{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2492{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2493{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2494{ "bgtctr-", XLOCB(19,BOTM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2495{ "bgtctr+", XLOCB(19,BOTP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2496{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2497{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2498{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2499{ "bgtctrl-",XLOCB(19,BOTM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2500{ "bgtctrl+",XLOCB(19,BOTP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2501{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2502{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2503{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2504{ "beqctr-", XLOCB(19,BOTM64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2505{ "beqctr+", XLOCB(19,BOTP64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2506{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2507{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2508{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2509{ "beqctrl-",XLOCB(19,BOTM64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2510{ "beqctrl+",XLOCB(19,BOTP64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2511{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2512{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2513{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2514{ "bsoctr-", XLOCB(19,BOTM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2515{ "bsoctr+", XLOCB(19,BOTP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2516{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2517{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2518{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2519{ "bsoctrl-",XLOCB(19,BOTM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2520{ "bsoctrl+",XLOCB(19,BOTP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2521{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2522{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2523{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2524{ "bunctr-", XLOCB(19,BOTM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2525{ "bunctr+", XLOCB(19,BOTP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2526{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2527{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2528{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2529{ "bunctrl-",XLOCB(19,BOTM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2530{ "bunctrl+",XLOCB(19,BOTP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2531{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2532{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2533{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2534{ "bgectr-", XLOCB(19,BOFM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2535{ "bgectr+", XLOCB(19,BOFP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2536{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2537{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2538{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2539{ "bgectrl-",XLOCB(19,BOFM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2540{ "bgectrl+",XLOCB(19,BOFP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2541{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2542{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2543{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2544{ "bnlctr-", XLOCB(19,BOFM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2545{ "bnlctr+", XLOCB(19,BOFP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2546{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2547{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2548{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2549{ "bnlctrl-",XLOCB(19,BOFM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2550{ "bnlctrl+",XLOCB(19,BOFP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2551{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2552{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2553{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2554{ "blectr-", XLOCB(19,BOFM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2555{ "blectr+", XLOCB(19,BOFP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2556{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2557{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2558{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2559{ "blectrl-",XLOCB(19,BOFM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2560{ "blectrl+",XLOCB(19,BOFP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2561{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2562{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2563{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2564{ "bngctr-", XLOCB(19,BOFM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2565{ "bngctr+", XLOCB(19,BOFP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2566{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2567{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2568{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2569{ "bngctrl-",XLOCB(19,BOFM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2570{ "bngctrl+",XLOCB(19,BOFP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2571{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2572{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2573{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2574{ "bnectr-", XLOCB(19,BOFM64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2575{ "bnectr+", XLOCB(19,BOFP64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2576{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2577{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2578{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2579{ "bnectrl-",XLOCB(19,BOFM64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2580{ "bnectrl+",XLOCB(19,BOFP64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2581{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2582{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2583{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2584{ "bnsctr-", XLOCB(19,BOFM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2585{ "bnsctr+", XLOCB(19,BOFP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2586{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2587{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2588{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2589{ "bnsctrl-",XLOCB(19,BOFM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2590{ "bnsctrl+",XLOCB(19,BOFP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2591{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2592{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2593{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } },
2594{ "bnuctr-", XLOCB(19,BOFM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
2595{ "bnuctr+", XLOCB(19,BOFP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2596{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
802a735e
AM		 2597{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2598{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } },
2599{ "bnuctrl-",XLOCB(19,BOFM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
2600{ "bnuctrl+",XLOCB(19,BOFP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } },
252b5132 2601{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2602{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM32, { BI } },
2603{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM32, { BI } },
2604{ "btctr-", XLO(19,BOTM64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
2605{ "btctr+", XLO(19,BOTP64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132 2606{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2607{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM32, { BI } },
2608{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM32, { BI } },
2609{ "btctrl-", XLO(19,BOTM64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
2610{ "btctrl+", XLO(19,BOTP64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132 2611{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2612{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM32, { BI } },
2613{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM32, { BI } },
2614{ "bfctr-", XLO(19,BOFM64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
2615{ "bfctr+", XLO(19,BOFP64,528,0), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132 2616{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
802a735e
AM		 2617{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM32, { BI } },
2618{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM32, { BI } },
2619{ "bfctrl-", XLO(19,BOFM64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
2620{ "bfctrl+", XLO(19,BOFP64,528,1), XLBOBB_MASK, PPCCOM64, { BI } },
252b5132 2621{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2622{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2623{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132 2624{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
d2f75a6f
GK		 2625{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2626{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
252b5132
RH		 2627{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
2628{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2629{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
2630{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 2631
2632{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2633{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2634
2635{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2636{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2637
2638{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2639{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2640{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2641{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2642{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2643{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2644{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2645{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2646
2647{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2648{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2649
418c1742
MG		 2650{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
2651{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
2652{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
2653{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
2654
252b5132
RH		 2655{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2656{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2657{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2658{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2659{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2660{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2661
2662{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
2663{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
2664{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
2665
2666{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
2667{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
2668
2669{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
2670{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
2671
2672{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
2673{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
2674
2675{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
2676{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
2677
2678{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
2679{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
2680
2681{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2682{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2683{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2684{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2685{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2686{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2687
2688{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2689{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2690
2691{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2692{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2693
2694{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2695{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2696
2697{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
2698{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2699{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
2700{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2701
2702{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2703{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2704
2705{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2706{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2707{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2708{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2709
2710{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
2711{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
2712{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
2713{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
2714{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
2715{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
2716{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
2717{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
2718{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
2719{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
2720{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
2721{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
2722{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
2723{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
2724{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
2725{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
2726{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
2727{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
2728{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
2729{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
2730{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
2731{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
2732{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
2733{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
2734{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
2735{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
2736{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
2737{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
2738{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
2739{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
2740{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
2741
2742{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2743{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2744{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2745{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2746{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2747{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
2748{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2749{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2750{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2751{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2752{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2753{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2754
2755{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2756{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2757
2758{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2759{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2760{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2761{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2762{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2763{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2764{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2765{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2766
2767{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2768{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2769
2770{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
2771
2772{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2773
2774{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
2775
418c1742
MG		 2776{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
2777
252b5132
RH		 2778{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
2779{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
2780
2781{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
2782{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
2783{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
2784{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
2785
2786{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
2787{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
2788{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
2789{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
2790
2791{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
2792{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
2793
2794{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
2795{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
2796
2797{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
2798{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
2799
418c1742
MG		 2800{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
2801
2802{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
2803
252b5132
RH		 2804{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2805{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2806{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2807{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2808
2809{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2810{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2811{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2812{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2813{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2814{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2815{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2816{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2817
2818{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
2819
2820{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2821
2822{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
2823{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
2824
418c1742
MG		 2825{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
2826
2827{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
2828
252b5132
RH		 2829{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
2830{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
2831
418c1742
MG		 2832{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
2833{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 2834
2835{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
2836{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
2837{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
2838{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
2839{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
2840{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
2841{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
2842{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
2843{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
2844{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
2845{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
2846{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
2847{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
2848{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
2849{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
2850
2851{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2852{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2853
2854{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2855{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2856
f509565f
GK		 2857{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
2858
252b5132
RH		 2859{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
2860
2861{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
2862
2863{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2864
2865{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
2866
418c1742
MG		 2867{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
2868
2869{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
2870
252b5132
RH		 2871{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
2872{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
2873{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
2874{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
2875
2876{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
2877{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
2878{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
2879{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
2880
f509565f
GK		 2881{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
2882
2dd46b8b 2883{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 2884
2885{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
2886
2887{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
2888{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
2889{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
2890{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
2891
418c1742
MG		 2892{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
2893
2894{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
2895
252b5132 2896{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
9fa87a06 2897{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
252b5132
RH		 2898
2899{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2900{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2901{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2902{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2903{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2904{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2905{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2906{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2907
2908{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2909{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2910{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2911{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2912{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2913{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2914{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2915{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2916
2917{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
2918{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
2919
2920{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
2921
2922{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
2923
2924{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2925
2926{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
2927{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
2928
418c1742
MG		 2929{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
2930
2931{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
2932
252b5132
RH		 2933{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
2934{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
2935
2936{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
2937{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
2938
2939{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
9fa87a06 2940{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
252b5132 2941
f509565f
GK		 2942{ "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } },
2943
252b5132
RH		 2944{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
2945
2946{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
2947{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
2948
2949{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
2950{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
2951
418c1742
MG		 2952{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
2953
252b5132
RH		 2954{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2955{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2956{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2957{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2958{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2959{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2960{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2961{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2962
2963{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2964{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2965{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2966{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2967{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2968{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2969{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2970{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2971
2972{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
2973
2974{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
2975
418c1742 2976{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
252b5132
RH		 2977
2978{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
2979{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
2980
2981{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
2982{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
2983
418c1742
MG		 2984{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
2985
252b5132
RH		 2986{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2987{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2988{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2989{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2990{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2991{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2992{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2993{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2994
2995{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2996{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2997{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2998{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2999
3000{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3001{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3002{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3003{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3004{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3005{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3006{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3007{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3008
3009{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3010{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3011{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3012{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3013{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3014{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3015{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3016{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3017
3018{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3019{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3020
418c1742 3021{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3022
3023{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3024
3025{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3026{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3027
418c1742
MG		 3028{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3029
3030{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3031
9fa87a06
MG		 3032{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3033
0152a4c6
MG		 3034{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3035
252b5132
RH		 3036{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3037{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3038{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3039{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3040
3041{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3042{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3043{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3044{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3045{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3046{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3047{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3048{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3049
418c1742
MG		 3050{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3051
252b5132
RH		 3052{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3053{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3054
418c1742 3055{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3056
3057{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3058
252b5132
RH		 3059{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3060{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3061
418c1742
MG		 3062{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3063
3064{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3065
252b5132
RH		 3066{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
3067{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3068
3069{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3070
3071{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3072
3073{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3074{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3075
418c1742
MG		 3076{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3077
252b5132
RH		 3078{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3079{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3080{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3081{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3082{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3083{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3084{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3085{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3086{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3087{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3088{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3089{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3090{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3091{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3092{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3093{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3094{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3095{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3096{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3097{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3098{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3099{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3100{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3101{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3102{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3103{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3104{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3105{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3106{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3107{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3108{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3109{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3110{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3111{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
e0c21649 3112{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
9fa87a06 3113{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
252b5132
RH		 3114
3115{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3116{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3117{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3118{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3119
3120{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3121{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3122{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3123{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3124{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3125{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3126{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3127{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3128{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3129{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3130{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3131{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3132{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3133{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3134{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3135{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3136{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3137{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3138{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3139{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3140{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3141{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3142{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3143{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3144{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3145{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3146{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3147{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3148{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3149{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3150{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
473d3293 3151{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
e0c21649
GK		 3152{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3153{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3154{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3155{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3156{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3157{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3158{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3159{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3160{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3161{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3162{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3163{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3164{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3165{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3166{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3167{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3168{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3169{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3170{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3171{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3172{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3173{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3174{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3175{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3176{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3177{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3178{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3179{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3180{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3181{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3182{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3183{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3184{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3185{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3186{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3187{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3188{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3189{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3190{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3191{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3192{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3193{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3194{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3195{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
e0c21649
GK		 3196{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3197{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3198{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3199{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3200{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3201{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3202{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3203{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3204{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3205{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3206{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
e0c21649
GK		 3207{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3208{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3209{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3210{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3211{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3212{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3213{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3214{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3215{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3216{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3217{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3218{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3219{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132 3220{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
e0c21649 3221{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3222{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3223{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3224{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3225{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3226{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3227{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3228{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3229{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3230{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3231{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3232{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3233{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3234{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
e0c21649 3235{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3236{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3237{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3238{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3239{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3240{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3241{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3242{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3243{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3244{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3245{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3246{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3247{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3248{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3249{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3250{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3251{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3252
3253{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3254
f5c120c5
MG		 3255{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3256{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3257
252b5132
RH		 3258{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3259
418c1742
MG		 3260{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3261
f5c120c5
MG		 3262{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3263{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3264
e0c21649 3265{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
252b5132
RH		 3266
3267{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3268{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3269{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3270{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3271
3272{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3273{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3274{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3275{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3276
3277{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3278
e0c21649 3279{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } },
252b5132
RH		 3280{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
3281{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
3282
3283{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3284
3285{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3286
418c1742
MG		 3287{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3288
9fa87a06
MG		 3289{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3290
418c1742
MG		 3291{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3292{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3293
3294{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3295{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3296
6ba045b1
AM		 3297{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3298
252b5132
RH		 3299{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3300
3301{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3302
3303{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3304
3305{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3306
3307{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3308
3309{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3310{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3311
3312{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3313{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3314
418c1742
MG		 3315{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3316
252b5132
RH		 3317{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3318
3319{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3320
3321{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3322
418c1742
MG		 3323{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3324
252b5132
RH		 3325{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3326{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3327{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3328{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3329
3330{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3331{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3332{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3333{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3334{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3335{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3336{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3337{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3338{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3339{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3340{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3341{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3342{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
3343{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3344{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3345{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3346{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3347{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3348{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3349{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3350{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3351{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3352{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3353{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3354{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3355{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3356{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3357{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3358{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3359{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3360{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3361{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3362{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
3363{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
e0c21649 3364{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
9fa87a06 3365{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
252b5132 3366
418c1742
MG		 3367{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3368{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3369
252b5132
RH		 3370{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3371{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3372{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3373{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3374
418c1742
MG		 3375{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3376{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3377
252b5132
RH		 3378{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3379{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3380{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3381{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3382
3383{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3384{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3385{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3386{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3387{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3388{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3389{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3390{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3391{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3392{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3393{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3394{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3395{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3396{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3397{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3398{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3399{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3400{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3401{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3402{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3403{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3404{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3405{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3406{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3407{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3408{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3409{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3410{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3411{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3412{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
473d3293 3413{ "mtvrsave",XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
252b5132
RH		 3414{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
3415{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3416{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3417{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3418{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
e0c21649
GK		 3419{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3420{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3421{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3422{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3423{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3424{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3425{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3426{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3427{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3428{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3429{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3430{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3431{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
3432{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
e0c21649
GK		 3433{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
3434{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
3435{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
3436{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
3437{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
3438{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
3439{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
3440{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
3441{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
3442{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3443{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
3444{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
e0c21649 3445{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3446{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
3447{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
3448{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
3449{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
3450{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
3451{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
3452{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
3453{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
3454{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
3455{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
e0c21649 3456{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3457{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
3458{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
3459{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
3460{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
3461{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
3462{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
3463{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
3464{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
3465{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
3466{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
24a7a601
C		 3467{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
3468{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
3469{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
3470{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
3471{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
3472{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
3473{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
3474{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
3475{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
3476{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
3477{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
3478{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
3479{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
3480{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
3481{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
3482{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
3483{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
3484{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
3485{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
252b5132
RH		 3486{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3487
3488{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
3489
3490{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3491{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3492
418c1742
MG		 3493{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
3494
4db3857a 3495{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
252b5132
RH		 3496
3497{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 3498{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 3499{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
3500{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 3501{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 3502{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
3503
3504{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3505{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3506{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3507{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3508
418c1742
MG		 3509{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3510{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3511
252b5132
RH		 3512{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
3513{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
3514{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
3515{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
3516
3517{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
3518
3519{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
3520
418c1742
MG		 3521{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
3522
252b5132
RH		 3523{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
3524
418c1742
MG		 3525{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } },
3526
252b5132
RH		 3527{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
3528
3529{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
3530{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
3531
3532{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
3533{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
3534
3535{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
3536
3537{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
3538{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
3539{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
3540{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
3541
3542{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
3543{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
3544
3545{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
3546{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
3547
3548{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
3549{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
3550
418c1742
MG		 3551{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
3552
3553{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
3554
252b5132
RH		 3555{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
3556
3557{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
3558
418c1742
MG		 3559{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
3560
252b5132
RH		 3561{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
3562
3563{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
3564{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
3565
6ba045b1
AM		 3566{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
3567{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
3568{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132 3569{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
9fa87a06 3570{ "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } },
252b5132
RH		 3571
3572{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
3573
418c1742
MG		 3574{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
3575
252b5132
RH		 3576{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
3577
3578{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
3579
3580{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
3581
418c1742
MG		 3582{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
3583
252b5132
RH		 3584{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
3585
3586{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
3587{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
3588
3589{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
3590{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
3591
3592{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
3593
3594{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
3595{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
3596
3597{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
3598{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
3599
418c1742
MG		 3600{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
3601
3602{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
3603
252b5132
RH		 3604{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
3605
3606{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
3607{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
3608
418c1742
MG		 3609{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
3610
252b5132
RH		 3611{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
3612{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
3613
3614{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
3615
3616{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
3617{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
3618
3619{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
3620{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
3621
418c1742
MG		 3622{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
3623
e0c21649 3624{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
9fa87a06 3625{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
e0c21649 3626
252b5132
RH		 3627{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
3628
3629{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
3630{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
3631
418c1742
MG		 3632{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
3633
3634{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
3635
3636{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
3637{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } },
3638
252b5132
RH		 3639{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
3640
3641{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
3642{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
3643{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
3644{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
3645
3646{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
3647{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
3648
418c1742
MG		 3649{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
3650
3651{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
3652{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
3653
252b5132
RH		 3654{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
3655
f5c120c5
MG		 3656{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
3657{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } },
3658
252b5132
RH		 3659{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
3660{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
3661{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
3662{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
3663
6ba045b1
AM		 3664{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
3665
252b5132 3666{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
9fa87a06 3667{ "mbar", X(31,854), 0xffffffff, BOOKE, { MO } },
252b5132 3668
9fa87a06
MG		 3669{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
3670{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
252b5132 3671
9fa87a06
MG		 3672{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
3673{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } },
418c1742 3674
6ba045b1
AM		 3675{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
3676
252b5132
RH		 3677{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
3678
3679{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
3680{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
3681
3682{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
3683{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
3684
3685{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
3686{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
3687{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
3688{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
3689
418c1742
MG		 3690{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
3691
3692{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
3693
3694{ "tlbre", X(31,946), X_MASK, BOOKE, { RT, RA, SH } },
3695
e0c21649
GK		 3696{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
3697{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
252b5132
RH		 3698
3699{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
3700{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
3701
3702{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
3703{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
3704
418c1742
MG		 3705{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
3706
e0c21649 3707{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
252b5132
RH		 3708
3709{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
e0c21649
GK		 3710
3711{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
3712{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
252b5132
RH		 3713{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
3714
9fa87a06
MG		 3715{ "tlbwe", X(31,978), X_MASK, BOOKE, { RT, RA, SH } },
3716
252b5132
RH		 3717{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
3718
3719{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
3720
3721{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
3722{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
3723
3724{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
3725
418c1742
MG		 3726{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
3727{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
3728
252b5132
RH		 3729{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
3730
3731{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3732{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3733
418c1742
MG		 3734{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
3735
786e2c0f
C		 3736{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
3737{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
3738{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
3739{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
3740{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
3741{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
3742{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
3743{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
3744{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
3745{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
3746{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
3747{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
3748
252b5132
RH		 3749{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
3750{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
3751
3752{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
3753{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
3754
3755{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
3756
3757{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
3758
3759{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
3760{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
3761
3762{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
3763{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
3764
3765{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
3766
3767{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
3768
3769{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
3770
3771{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
3772
3773{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
3774
3775{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
3776
3777{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
3778
3779{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
3780
3781{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
3782{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
3783
3784{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
3785{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
3786
3787{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
3788
3789{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
3790
3791{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
3792
3793{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
3794
3795{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
3796
3797{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
3798
3799{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
3800
3801{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
3802
3803{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
3804
3805{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
3806
418c1742
MG		 3807{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
3808{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
3809{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
3810{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
3811{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
3812{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
3813{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
3814{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
3815{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
3816{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
3817{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
3818{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
3819{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
3820{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
3821
802a735e
AM		 3822{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
3823
3824{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
3825
3826{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
3827
252b5132
RH		 3828{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3829{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3830
3831{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3832{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3833
3834{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3835{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3836
3837{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3838{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3839
3840{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3841{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3842
3843{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3844{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3845
3846{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3847{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3848
3849{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3850{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3851
3852{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3853{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3854
3855{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3856{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3857
3858{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
3859
3860{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
3861
418c1742 3862{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742 3863{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
418c1742
MG		 3864{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
3865{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3866{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
3867{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
3868{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
3869{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
3870{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
3871{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3872{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
3873{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
3874
802a735e
AM		 3875{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
3876
3877{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
3878
252b5132
RH		 3879{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3880
3881{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
3882{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
3883
3884{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3885{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
3886{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3887{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
3888
3889{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3890{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
3891{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3892{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
3893
3894{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3895{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3896{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3897{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3898
3899{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3900{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3901{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3902{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3903
3904{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3905{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3906{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3907{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3908
3909{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3910{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3911
3912{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3913{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3914
3915{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3916{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3917{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3918{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3919
3920{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3921{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3922
3923{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3924{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3925{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3926{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3927
3928{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3929{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3930{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3931{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3932
3933{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3934{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3935{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3936{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3937
3938{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3939{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3940{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3941{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3942
3943{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3944
3945{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
3946{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
3947
3948{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
3949{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
3950
3951{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
3952
3953{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
3954{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
3955
3956{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
3957{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
3958
3959{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3960{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3961
3962{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
3963{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
3964
3965{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
3966{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
3967
3968{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
3969{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
3970
3971{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
3972{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
3973
3974{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
3975{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
3976
3977{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
3978{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
3979
3980{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
3981{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
3982
3983};
3984
3985const int powerpc_num_opcodes =
3986 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3987\f
3988/* The macro table. This is only used by the assembler. */
3989
3990/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3991 when x=0; 32-x when x is between 1 and 31; are negative if x is
3992 negative; and are 32 or more otherwise. This is what you want
3993 when, for instance, you are emulating a right shift by a
3994 rotate-left-and-mask, because the underlying instructions support
3995 shifts of size 0 but not shifts of size 32. By comparison, when
3996 extracting x bits from some word you want to use just 32-x, because
3997 the underlying instructions don't support extracting 0 bits but do
3998 support extracting the whole word (32 bits in this case). */
3999
4000const struct powerpc_macro powerpc_macros[] = {
4001{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4002{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4003{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4004{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4005{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4006{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4007{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4008{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4009{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4010{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4011{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4012{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4013{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4014{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4015{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4016{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4017
4018{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4019{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4020{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
4021{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
4022{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4023{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4024{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4025{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4026{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4027{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4028{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4029{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4030{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4031{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4032{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4033{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4034{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4035{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4036{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4037{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4038{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4039{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4040
4041};
4042
4043const int powerpc_num_macros =
4044 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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