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* readelf.c (do_archive_index): New.
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
ba4e851b 3 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
9b201bb5 6 This file is part of the GNU opcodes library.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
112290ab 18 You should have received a copy of the GNU General Public License
9b201bb5
NC		 19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
c168870a
AM		 41static unsigned long insert_bat (unsigned long, long, int, const char **);
42static long extract_bat (unsigned long, int, int *);
43static unsigned long insert_bba (unsigned long, long, int, const char **);
44static long extract_bba (unsigned long, int, int *);
c168870a
AM		 45static unsigned long insert_bdm (unsigned long, long, int, const char **);
46static long extract_bdm (unsigned long, int, int *);
47static unsigned long insert_bdp (unsigned long, long, int, const char **);
48static long extract_bdp (unsigned long, int, int *);
c168870a
AM		 49static unsigned long insert_bo (unsigned long, long, int, const char **);
50static long extract_bo (unsigned long, int, int *);
51static unsigned long insert_boe (unsigned long, long, int, const char **);
52static long extract_boe (unsigned long, int, int *);
c168870a
AM		 53static unsigned long insert_fxm (unsigned long, long, int, const char **);
54static long extract_fxm (unsigned long, int, int *);
c168870a
AM		 55static unsigned long insert_mbe (unsigned long, long, int, const char **);
56static long extract_mbe (unsigned long, int, int *);
57static unsigned long insert_mb6 (unsigned long, long, int, const char **);
58static long extract_mb6 (unsigned long, int, int *);
c168870a
AM		 59static long extract_nb (unsigned long, int, int *);
60static unsigned long insert_nsi (unsigned long, long, int, const char **);
61static long extract_nsi (unsigned long, int, int *);
62static unsigned long insert_ral (unsigned long, long, int, const char **);
63static unsigned long insert_ram (unsigned long, long, int, const char **);
64static unsigned long insert_raq (unsigned long, long, int, const char **);
65static unsigned long insert_ras (unsigned long, long, int, const char **);
66static unsigned long insert_rbs (unsigned long, long, int, const char **);
67static long extract_rbs (unsigned long, int, int *);
c168870a
AM		 68static unsigned long insert_sh6 (unsigned long, long, int, const char **);
69static long extract_sh6 (unsigned long, int, int *);
70static unsigned long insert_spr (unsigned long, long, int, const char **);
71static long extract_spr (unsigned long, int, int *);
da99ee72
AM		 72static unsigned long insert_sprg (unsigned long, long, int, const char **);
73static long extract_sprg (unsigned long, int, int *);
c168870a
AM		 74static unsigned long insert_tbr (unsigned long, long, int, const char **);
75static long extract_tbr (unsigned long, int, int *);
252b5132
RH		 76\f
77/* The operands table.
78
717bbdf1 79 The fields are bitm, shift, insert, extract, flags.
252b5132
RH		 80
81 We used to put parens around the various additions, like the one
82 for BA just below. However, that caused trouble with feeble
83 compilers with a limit on depth of a parenthesized expression, like
84 (reportedly) the compiler in Microsoft Developer Studio 5. So we
85 omit the parens, since the macros are never used in a context where
86 the addition will be ambiguous. */
87
88const struct powerpc_operand powerpc_operands[] =
89{
90 /* The zero index is used to indicate the end of the list of
91 operands. */
92#define UNUSED 0
bbac1f2a 93 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 94
95 /* The BA field in an XL form instruction. */
96#define BA UNUSED + 1
717bbdf1
AM		 97 /* The BI field in a B form or XL form instruction. */
98#define BI BA
99#define BI_MASK (0x1f << 16)
b84bf58a 100 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 101
102 /* The BA field in an XL form instruction when it must be the same
103 as the BT field in the same instruction. */
104#define BAT BA + 1
b84bf58a 105 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 106
107 /* The BB field in an XL form instruction. */
108#define BB BAT + 1
109#define BB_MASK (0x1f << 11)
b84bf58a 110 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 111
112 /* The BB field in an XL form instruction when it must be the same
113 as the BA field in the same instruction. */
114#define BBA BB + 1
b84bf58a 115 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 116
117 /* The BD field in a B form instruction. The lower two bits are
118 forced to zero. */
119#define BD BBA + 1
b84bf58a 120 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 121
122 /* The BD field in a B form instruction when absolute addressing is
123 used. */
124#define BDA BD + 1
b84bf58a 125 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 126
127 /* The BD field in a B form instruction when the - modifier is used.
128 This sets the y bit of the BO field appropriately. */
129#define BDM BDA + 1
b84bf58a 130 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 131 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 132
133 /* The BD field in a B form instruction when the - modifier is used
134 and absolute address is used. */
135#define BDMA BDM + 1
b84bf58a 136 { 0xfffc, 0, insert_bdm, extract_bdm,
11b37b7b 137 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 138
139 /* The BD field in a B form instruction when the + modifier is used.
140 This sets the y bit of the BO field appropriately. */
141#define BDP BDMA + 1
b84bf58a 142 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 143 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 144
145 /* The BD field in a B form instruction when the + modifier is used
146 and absolute addressing is used. */
147#define BDPA BDP + 1
b84bf58a 148 { 0xfffc, 0, insert_bdp, extract_bdp,
11b37b7b 149 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 150
151 /* The BF field in an X or XL form instruction. */
152#define BF BDPA + 1
717bbdf1
AM		 153 /* The CRFD field in an X form instruction. */
154#define CRFD BF
b84bf58a 155 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132 156
ea192fa3
PB		 157 /* The BF field in an X or XL form instruction. */
158#define BFF BF + 1
159 { 0x7, 23, NULL, NULL, 0 },
160
252b5132
RH		 161 /* An optional BF field. This is used for comparison instructions,
162 in which an omitted BF field is taken as zero. */
ea192fa3 163#define OBF BFF + 1
b84bf58a 164 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 165
166 /* The BFA field in an X or XL form instruction. */
167#define BFA OBF + 1
b84bf58a 168 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132 169
252b5132
RH		 170 /* The BO field in a B form instruction. Certain values are
171 illegal. */
717bbdf1 172#define BO BFA + 1
252b5132 173#define BO_MASK (0x1f << 21)
b84bf58a 174 { 0x1f, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 175
176 /* The BO field in a B form instruction when the + or - modifier is
177 used. This is like the BO field, but it must be even. */
178#define BOE BO + 1
b84bf58a 179 { 0x1e, 21, insert_boe, extract_boe, 0 },
252b5132 180
d0618d1c 181#define BH BOE + 1
b84bf58a 182 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 183
252b5132 184 /* The BT field in an X or XL form instruction. */
d0618d1c 185#define BT BH + 1
b84bf58a 186 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 187
188 /* The condition register number portion of the BI field in a B form
189 or XL form instruction. This is used for the extended
190 conditional branch mnemonics, which set the lower two bits of the
191 BI field. This field is optional. */
192#define CR BT + 1
b84bf58a 193 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 194
23976049
EZ		 195 /* The CRB field in an X form instruction. */
196#define CRB CR + 1
717bbdf1
AM		 197 /* The MB field in an M form instruction. */
198#define MB CRB
199#define MB_MASK (0x1f << 6)
b84bf58a 200 { 0x1f, 6, NULL, NULL, 0 },
23976049 201
23976049 202 /* The CRFS field in an X form instruction. */
717bbdf1 203#define CRFS CRB + 1
b84bf58a 204 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 205
418c1742 206 /* The CT field in an X form instruction. */
23976049 207#define CT CRFS + 1
717bbdf1
AM		 208 /* The MO field in an mbar instruction. */
209#define MO CT
b84bf58a 210 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 211
252b5132
RH		 212 /* The D field in a D form instruction. This is a displacement off
213 a register, and implies that the next operand is a register in
214 parentheses. */
418c1742 215#define D CT + 1
b84bf58a 216 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 217
418c1742
MG		 218 /* The DE field in a DE form instruction. This is like D, but is 12
219 bits only. */
220#define DE D + 1
b84bf58a 221 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
418c1742
MG		 222
223 /* The DES field in a DES form instruction. This is like DS, but is 14
224 bits only (12 stored.) */
225#define DES DE + 1
b84bf58a 226 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
418c1742 227
adadcc0c
AM		 228 /* The DQ field in a DQ form instruction. This is like D, but the
229 lower four bits are forced to zero. */
230#define DQ DES + 1
b84bf58a
AM		 231 { 0xfff0, 0, NULL, NULL,
232 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
adadcc0c 233
252b5132
RH		 234 /* The DS field in a DS form instruction. This is like D, but the
235 lower two bits are forced to zero. */
adadcc0c 236#define DS DQ + 1
b84bf58a
AM		 237 { 0xfffc, 0, NULL, NULL,
238 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 239
240 /* The E field in a wrteei instruction. */
c3d65c1c 241 /* And the W bit in the pair singles instructions. */
252b5132 242#define E DS + 1
c3d65c1c 243#define PSW E
b84bf58a 244 { 0x1, 15, NULL, NULL, 0 },
252b5132
RH		 245
246 /* The FL1 field in a POWER SC form instruction. */
247#define FL1 E + 1
717bbdf1
AM		 248 /* The U field in an X form instruction. */
249#define U FL1
b84bf58a 250 { 0xf, 12, NULL, NULL, 0 },
252b5132
RH		 251
252 /* The FL2 field in a POWER SC form instruction. */
253#define FL2 FL1 + 1
b84bf58a 254 { 0x7, 2, NULL, NULL, 0 },
252b5132
RH		 255
256 /* The FLM field in an XFL form instruction. */
257#define FLM FL2 + 1
b84bf58a 258 { 0xff, 17, NULL, NULL, 0 },
252b5132
RH		 259
260 /* The FRA field in an X or A form instruction. */
261#define FRA FLM + 1
262#define FRA_MASK (0x1f << 16)
b84bf58a 263 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 264
265 /* The FRB field in an X or A form instruction. */
266#define FRB FRA + 1
267#define FRB_MASK (0x1f << 11)
b84bf58a 268 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 269
270 /* The FRC field in an A form instruction. */
271#define FRC FRB + 1
272#define FRC_MASK (0x1f << 6)
b84bf58a 273 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 274
275 /* The FRS field in an X form instruction or the FRT field in a D, X
276 or A form instruction. */
277#define FRS FRC + 1
278#define FRT FRS
b84bf58a 279 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 280
281 /* The FXM field in an XFX instruction. */
282#define FXM FRS + 1
b84bf58a 283 { 0xff, 12, insert_fxm, extract_fxm, 0 },
c168870a
AM		 284
285 /* Power4 version for mfcr. */
286#define FXM4 FXM + 1
b84bf58a 287 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 288
289 /* The L field in a D or X form instruction. */
c168870a 290#define L FXM4 + 1
b84bf58a 291 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132 292
1ed8e1e4
AM		 293 /* The LEV field in a POWER SVC form instruction. */
294#define SVC_LEV L + 1
b84bf58a 295 { 0x7f, 5, NULL, NULL, 0 },
252b5132 296
1ed8e1e4
AM		 297 /* The LEV field in an SC form instruction. */
298#define LEV SVC_LEV + 1
b84bf58a 299 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
1ed8e1e4 300
252b5132
RH		 301 /* The LI field in an I form instruction. The lower two bits are
302 forced to zero. */
303#define LI LEV + 1
b84bf58a 304 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 305
306 /* The LI field in an I form instruction when used as an absolute
307 address. */
308#define LIA LI + 1
b84bf58a 309 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 310
6ba045b1
AM		 311 /* The LS field in an X (sync) form instruction. */
312#define LS LIA + 1
b84bf58a 313 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 314
252b5132 315 /* The ME field in an M form instruction. */
717bbdf1 316#define ME LS + 1
252b5132 317#define ME_MASK (0x1f << 1)
b84bf58a 318 { 0x1f, 1, NULL, NULL, 0 },
252b5132
RH		 319
320 /* The MB and ME fields in an M form instruction expressed a single
321 operand which is a bitmask indicating which bits to select. This
322 is a two operand form using PPC_OPERAND_NEXT. See the
323 description in opcode/ppc.h for what this means. */
324#define MBE ME + 1
b84bf58a 325 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
eb42fac1 326 { -1, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 327
328 /* The MB or ME field in an MD or MDS form instruction. The high
329 bit is wrapped to the low end. */
330#define MB6 MBE + 2
331#define ME6 MB6
332#define MB6_MASK (0x3f << 5)
b84bf58a 333 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
252b5132
RH		 334
335 /* The NB field in an X form instruction. The value 32 is stored as
336 0. */
717bbdf1 337#define NB MB6 + 1
b84bf58a 338 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
252b5132
RH		 339
340 /* The NSI field in a D form instruction. This is the same as the
341 SI field, only negated. */
342#define NSI NB + 1
b84bf58a 343 { 0xffff, 0, insert_nsi, extract_nsi,
11b37b7b 344 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 345
adadcc0c 346 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 347#define RA NSI + 1
252b5132 348#define RA_MASK (0x1f << 16)
b84bf58a 349 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 350
fdd12ef3
AM		 351 /* As above, but 0 in the RA field means zero, not r0. */
352#define RA0 RA + 1
b84bf58a 353 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3
AM		 354
355 /* The RA field in the DQ form lq instruction, which has special
adadcc0c 356 value restrictions. */
fdd12ef3 357#define RAQ RA0 + 1
b84bf58a 358 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 359
252b5132
RH		 360 /* The RA field in a D or X form instruction which is an updating
361 load, which means that the RA field may not be zero and may not
362 equal the RT field. */
adadcc0c 363#define RAL RAQ + 1
b84bf58a 364 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 365
366 /* The RA field in an lmw instruction, which has special value
367 restrictions. */
368#define RAM RAL + 1
b84bf58a 369 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 370
371 /* The RA field in a D or X form instruction which is an updating
372 store or an updating floating point load, which means that the RA
373 field may not be zero. */
374#define RAS RAM + 1
b84bf58a 375 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 376
1f6c9eb0 377 /* The RA field of the tlbwe instruction, which is optional. */
fdd12ef3 378#define RAOPT RAS + 1
b84bf58a 379 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 380
252b5132 381 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 382#define RB RAOPT + 1
252b5132 383#define RB_MASK (0x1f << 11)
b84bf58a 384 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 385
386 /* The RB field in an X form instruction when it must be the same as
387 the RS field in the instruction. This is used for extended
388 mnemonics like mr. */
389#define RBS RB + 1
b84bf58a 390 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 391
392 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
393 instruction or the RT field in a D, DS, X, XFX or XO form
394 instruction. */
395#define RS RBS + 1
396#define RT RS
397#define RT_MASK (0x1f << 21)
b84bf58a 398 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 399
717bbdf1
AM		 400 /* The RS and RT fields of the DS form stq instruction, which have
401 special value restrictions. */
adadcc0c 402#define RSQ RS + 1
717bbdf1 403#define RTQ RSQ
b84bf58a 404 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 405
1f6c9eb0 406 /* The RS field of the tlbwe instruction, which is optional. */
717bbdf1 407#define RSO RSQ + 1
eed0d89a 408#define RTO RSO
b84bf58a 409 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 410
252b5132 411 /* The SH field in an X or M form instruction. */
1f6c9eb0 412#define SH RSO + 1
252b5132 413#define SH_MASK (0x1f << 11)
717bbdf1
AM		 414 /* The other UIMM field in a EVX form instruction. */
415#define EVUIMM SH
b84bf58a 416 { 0x1f, 11, NULL, NULL, 0 },
252b5132
RH		 417
418 /* The SH field in an MD form instruction. This is split. */
419#define SH6 SH + 1
420#define SH6_MASK ((0x1f << 11) | (1 << 1))
b84bf58a 421 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
252b5132 422
1f6c9eb0
ZW		 423 /* The SH field of the tlbwe instruction, which is optional. */
424#define SHO SH6 + 1
b84bf58a 425 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 426
252b5132 427 /* The SI field in a D form instruction. */
1f6c9eb0 428#define SI SHO + 1
b84bf58a 429 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 430
431 /* The SI field in a D form instruction when we accept a wide range
432 of positive values. */
433#define SISIGNOPT SI + 1
b84bf58a 434 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 435
436 /* The SPR field in an XFX form instruction. This is flipped--the
437 lower 5 bits are stored in the upper 5 and vice- versa. */
438#define SPR SISIGNOPT + 1
914749f6 439#define PMR SPR
252b5132 440#define SPR_MASK (0x3ff << 11)
b84bf58a 441 { 0x3ff, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 442
443 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
444#define SPRBAT SPR + 1
445#define SPRBAT_MASK (0x3 << 17)
b84bf58a 446 { 0x3, 17, NULL, NULL, 0 },
252b5132
RH		 447
448 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
449#define SPRG SPRBAT + 1
b84bf58a 450 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 451
452 /* The SR field in an X form instruction. */
453#define SR SPRG + 1
b84bf58a 454 { 0xf, 16, NULL, NULL, 0 },
252b5132 455
f5c120c5
MG		 456 /* The STRM field in an X AltiVec form instruction. */
457#define STRM SR + 1
b84bf58a 458 { 0x3, 21, NULL, NULL, 0 },
f5c120c5 459
252b5132 460 /* The SV field in a POWER SC form instruction. */
f5c120c5 461#define SV STRM + 1
b84bf58a 462 { 0x3fff, 2, NULL, NULL, 0 },
252b5132
RH		 463
464 /* The TBR field in an XFX form instruction. This is like the SPR
465 field, but it is optional. */
466#define TBR SV + 1
b84bf58a 467 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 468
469 /* The TO field in a D or X form instruction. */
470#define TO TBR + 1
471#define TO_MASK (0x1f << 21)
b84bf58a 472 { 0x1f, 21, NULL, NULL, 0 },
252b5132 473
252b5132 474 /* The UI field in a D form instruction. */
717bbdf1 475#define UI TO + 1
b84bf58a 476 { 0xffff, 0, NULL, NULL, 0 },
786e2c0f 477
112290ab 478 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f 479#define VA UI + 1
b84bf58a 480 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 481
112290ab 482 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f 483#define VB VA + 1
b84bf58a 484 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 485
112290ab 486 /* The VC field in a VA form instruction. */
786e2c0f 487#define VC VB + 1
b84bf58a 488 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 489
112290ab 490 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 491#define VD VC + 1
492#define VS VD
b84bf58a 493 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 494
112290ab 495 /* The SIMM field in a VX form instruction. */
786e2c0f 496#define SIMM VD + 1
b84bf58a 497 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 498
0bbdef92 499 /* The UIMM field in a VX form instruction, and TE in Z form. */
786e2c0f 500#define UIMM SIMM + 1
0bbdef92 501#define TE UIMM
b84bf58a 502 { 0x1f, 16, NULL, NULL, 0 },
786e2c0f 503
112290ab 504 /* The SHB field in a VA form instruction. */
786e2c0f 505#define SHB UIMM + 1
b84bf58a 506 { 0xf, 6, NULL, NULL, 0 },
ff3a6ee3 507
112290ab 508 /* The other UIMM field in a half word EVX form instruction. */
717bbdf1 509#define EVUIMM_2 SHB + 1
b84bf58a 510 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
23976049 511
112290ab 512 /* The other UIMM field in a word EVX form instruction. */
23976049 513#define EVUIMM_4 EVUIMM_2 + 1
b84bf58a 514 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
23976049 515
112290ab 516 /* The other UIMM field in a double EVX form instruction. */
23976049 517#define EVUIMM_8 EVUIMM_4 + 1
b84bf58a 518 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
23976049 519
ff3a6ee3 520 /* The WS field. */
23976049 521#define WS EVUIMM_8 + 1
b84bf58a 522 { 0x7, 11, NULL, NULL, 0 },
ff3a6ee3 523
c3d65c1c
BE		 524 /* PowerPC paired singles extensions. */
525 /* W bit in the pair singles instructions for x type instructions. */
526#define PSWM WS + 1
527 { 0x1, 10, 0, 0, 0 },
528
529 /* IDX bits for quantization in the pair singles instructions. */
530#define PSQ PSWM + 1
531 { 0x7, 12, 0, 0, 0 },
532
533 /* IDX bits for quantization in the pair singles x-type instructions. */
534#define PSQM PSQ + 1
535 { 0x7, 7, 0, 0, 0 },
536
537 /* Smaller D field for quantization in the pair singles instructions. */
538#define PSD PSQM + 1
539 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
540
541#define A_L PSD + 1
ea192fa3 542#define W A_L
c3d65c1c 543#define MTMSRD_L W
b84bf58a 544 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 545
c3d65c1c 546#define RMC MTMSRD_L + 1
b84bf58a 547 { 0x3, 9, NULL, NULL, 0 },
702f0fb4
PB		 548
549#define R RMC + 1
b84bf58a 550 { 0x1, 16, NULL, NULL, 0 },
702f0fb4
PB		 551
552#define SP R + 1
b84bf58a 553 { 0x3, 19, NULL, NULL, 0 },
702f0fb4
PB		 554
555#define S SP + 1
b84bf58a 556 { 0x1, 20, NULL, NULL, 0 },
702f0fb4
PB		 557
558 /* SH field starting at bit position 16. */
559#define SH16 S + 1
0bbdef92
AM		 560 /* The DCM and DGM fields in a Z form instruction. */
561#define DCM SH16
562#define DGM DCM
b84bf58a 563 { 0x3f, 10, NULL, NULL, 0 },
702f0fb4 564
702f0fb4 565 /* The EH field in larx instruction. */
717bbdf1 566#define EH SH16 + 1
b84bf58a 567 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
ea192fa3
PB		 568
569 /* The L field in an mtfsf or XFL form instruction. */
570#define XFL_L EH + 1
571 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
252b5132
RH		 572};
573
b84bf58a
AM		 574const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
575 / sizeof (powerpc_operands[0]));
576
252b5132
RH		 577/* The functions used to insert and extract complicated operands. */
578
579/* The BA field in an XL form instruction when it must be the same as
580 the BT field in the same instruction. This operand is marked FAKE.
581 The insertion function just copies the BT field into the BA field,
582 and the extraction function just checks that the fields are the
583 same. */
584
252b5132 585static unsigned long
2fbfdc41
AM		 586insert_bat (unsigned long insn,
587 long value ATTRIBUTE_UNUSED,
588 int dialect ATTRIBUTE_UNUSED,
589 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 590{
591 return insn | (((insn >> 21) & 0x1f) << 16);
592}
593
594static long
2fbfdc41
AM		 595extract_bat (unsigned long insn,
596 int dialect ATTRIBUTE_UNUSED,
597 int *invalid)
252b5132 598{
8427c424 599 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 600 *invalid = 1;
601 return 0;
602}
603
604/* The BB field in an XL form instruction when it must be the same as
605 the BA field in the same instruction. This operand is marked FAKE.
606 The insertion function just copies the BA field into the BB field,
607 and the extraction function just checks that the fields are the
608 same. */
609
252b5132 610static unsigned long
2fbfdc41
AM		 611insert_bba (unsigned long insn,
612 long value ATTRIBUTE_UNUSED,
613 int dialect ATTRIBUTE_UNUSED,
614 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 615{
616 return insn | (((insn >> 16) & 0x1f) << 11);
617}
618
619static long
2fbfdc41
AM		 620extract_bba (unsigned long insn,
621 int dialect ATTRIBUTE_UNUSED,
622 int *invalid)
252b5132 623{
8427c424 624 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 625 *invalid = 1;
626 return 0;
627}
628
252b5132
RH		 629/* The BD field in a B form instruction when the - modifier is used.
630 This modifier means that the branch is not expected to be taken.
94efba12
AM		 631 For chips built to versions of the architecture prior to version 2
632 (ie. not Power4 compatible), we set the y bit of the BO field to 1
633 if the offset is negative. When extracting, we require that the y
634 bit be 1 and that the offset be positive, since if the y bit is 0
635 we just want to print the normal form of the instruction.
636 Power4 compatible targets use two bits, "a", and "t", instead of
637 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
638 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
639 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
ba4e851b
AM		 640 for branch on CTR. We only handle the taken/not-taken hint here.
641 Note that we don't relax the conditions tested here when
642 disassembling with -Many because insns using extract_bdm and
643 extract_bdp always occur in pairs. One or the other will always
644 be valid. */
252b5132 645
252b5132 646static unsigned long
2fbfdc41
AM		 647insert_bdm (unsigned long insn,
648 long value,
649 int dialect,
650 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 651{
94efba12 652 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 653 {
654 if ((value & 0x8000) != 0)
655 insn |= 1 << 21;
656 }
657 else
658 {
659 if ((insn & (0x14 << 21)) == (0x04 << 21))
660 insn |= 0x02 << 21;
661 else if ((insn & (0x14 << 21)) == (0x10 << 21))
662 insn |= 0x08 << 21;
663 }
252b5132
RH		 664 return insn | (value & 0xfffc);
665}
666
667static long
2fbfdc41
AM		 668extract_bdm (unsigned long insn,
669 int dialect,
670 int *invalid)
252b5132 671{
8427c424 672 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 673 {
8427c424
AM		 674 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
675 *invalid = 1;
802a735e 676 }
8427c424
AM		 677 else
678 {
679 if ((insn & (0x17 << 21)) != (0x06 << 21)
680 && (insn & (0x1d << 21)) != (0x18 << 21))
681 *invalid = 1;
682 }
683
802a735e 684 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 685}
686
687/* The BD field in a B form instruction when the + modifier is used.
688 This is like BDM, above, except that the branch is expected to be
689 taken. */
690
252b5132 691static unsigned long
2fbfdc41
AM		 692insert_bdp (unsigned long insn,
693 long value,
694 int dialect,
695 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 696{
94efba12 697 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 698 {
699 if ((value & 0x8000) == 0)
700 insn |= 1 << 21;
701 }
702 else
703 {
704 if ((insn & (0x14 << 21)) == (0x04 << 21))
705 insn |= 0x03 << 21;
706 else if ((insn & (0x14 << 21)) == (0x10 << 21))
707 insn |= 0x09 << 21;
708 }
252b5132
RH		 709 return insn | (value & 0xfffc);
710}
711
712static long
2fbfdc41
AM		 713extract_bdp (unsigned long insn,
714 int dialect,
715 int *invalid)
252b5132 716{
8427c424 717 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 718 {
8427c424
AM		 719 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
720 *invalid = 1;
721 }
722 else
723 {
724 if ((insn & (0x17 << 21)) != (0x07 << 21)
725 && (insn & (0x1d << 21)) != (0x19 << 21))
726 *invalid = 1;
802a735e 727 }
8427c424 728
802a735e 729 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 730}
731
732/* Check for legal values of a BO field. */
733
734static int
ba4e851b 735valid_bo (long value, int dialect, int extract)
252b5132 736{
94efba12 737 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 738 {
ba4e851b 739 int valid;
802a735e
AM		 740 /* Certain encodings have bits that are required to be zero.
741 These are (z must be zero, y may be anything):
742 001zy
743 011zy
744 1z00y
745 1z01y
746 1z1zz
747 */
748 switch (value & 0x14)
749 {
750 default:
751 case 0:
ba4e851b
AM		 752 valid = 1;
753 break;
802a735e 754 case 0x4:
ba4e851b
AM		 755 valid = (value & 0x2) == 0;
756 break;
802a735e 757 case 0x10:
ba4e851b
AM		 758 valid = (value & 0x8) == 0;
759 break;
802a735e 760 case 0x14:
ba4e851b
AM		 761 valid = value == 0x14;
762 break;
802a735e 763 }
ba4e851b
AM		 764 /* When disassembling with -Many, accept power4 encodings too. */
765 if (valid
766 || (dialect & PPC_OPCODE_ANY) == 0
767 || !extract)
768 return valid;
802a735e 769 }
ba4e851b
AM		 770
771 /* Certain encodings have bits that are required to be zero.
772 These are (z must be zero, a & t may be anything):
773 0000z
774 0001z
775 0100z
776 0101z
777 001at
778 011at
779 1a00t
780 1a01t
781 1z1zz
782 */
783 if ((value & 0x14) == 0)
784 return (value & 0x1) == 0;
785 else if ((value & 0x14) == 0x14)
786 return value == 0x14;
802a735e 787 else
ba4e851b 788 return 1;
252b5132
RH		 789}
790
791/* The BO field in a B form instruction. Warn about attempts to set
792 the field to an illegal value. */
793
794static unsigned long
2fbfdc41
AM		 795insert_bo (unsigned long insn,
796 long value,
797 int dialect,
798 const char **errmsg)
252b5132 799{
ba4e851b 800 if (!valid_bo (value, dialect, 0))
252b5132
RH		 801 *errmsg = _("invalid conditional option");
802 return insn | ((value & 0x1f) << 21);
803}
804
805static long
2fbfdc41
AM		 806extract_bo (unsigned long insn,
807 int dialect,
808 int *invalid)
252b5132
RH		 809{
810 long value;
811
812 value = (insn >> 21) & 0x1f;
ba4e851b 813 if (!valid_bo (value, dialect, 1))
252b5132
RH		 814 *invalid = 1;
815 return value;
816}
817
818/* The BO field in a B form instruction when the + or - modifier is
819 used. This is like the BO field, but it must be even. When
820 extracting it, we force it to be even. */
821
822static unsigned long
2fbfdc41
AM		 823insert_boe (unsigned long insn,
824 long value,
825 int dialect,
826 const char **errmsg)
252b5132 827{
ba4e851b 828 if (!valid_bo (value, dialect, 0))
8427c424
AM		 829 *errmsg = _("invalid conditional option");
830 else if ((value & 1) != 0)
831 *errmsg = _("attempt to set y bit when using + or - modifier");
832
252b5132
RH		 833 return insn | ((value & 0x1f) << 21);
834}
835
836static long
2fbfdc41
AM		 837extract_boe (unsigned long insn,
838 int dialect,
839 int *invalid)
252b5132
RH		 840{
841 long value;
842
843 value = (insn >> 21) & 0x1f;
ba4e851b 844 if (!valid_bo (value, dialect, 1))
252b5132
RH		 845 *invalid = 1;
846 return value & 0x1e;
847}
848
2fbfdc41
AM		 849/* FXM mask in mfcr and mtcrf instructions. */
850
851static unsigned long
852insert_fxm (unsigned long insn,
853 long value,
854 int dialect,
855 const char **errmsg)
c168870a 856{
98e69875
AM		 857 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
858 one bit of the mask field is set. */
859 if ((insn & (1 << 20)) != 0)
860 {
861 if (value == 0 || (value & -value) != value)
862 {
863 *errmsg = _("invalid mask field");
864 value = 0;
865 }
866 }
867
c168870a
AM		 868 /* If the optional field on mfcr is missing that means we want to use
869 the old form of the instruction that moves the whole cr. In that
870 case we'll have VALUE zero. There doesn't seem to be a way to
871 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 872 else if (value == 0)
c168870a
AM		 873 ;
874
875 /* If only one bit of the FXM field is set, we can use the new form
661bd698 876 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 877 encoding, this is not backward compatible. Do not generate the
878 new form unless -mpower4 has been given, or -many and the two
879 operand form of mfcr was used. */
880 else if ((value & -value) == value
881 && ((dialect & PPC_OPCODE_POWER4) != 0
882 || ((dialect & PPC_OPCODE_ANY) != 0
883 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 884 insn |= 1 << 20;
885
886 /* Any other value on mfcr is an error. */
887 else if ((insn & (0x3ff << 1)) == 19 << 1)
888 {
8427c424 889 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 890 value = 0;
891 }
892
893 return insn | ((value & 0xff) << 12);
894}
895
2fbfdc41
AM		 896static long
897extract_fxm (unsigned long insn,
98e69875 898 int dialect ATTRIBUTE_UNUSED,
2fbfdc41 899 int *invalid)
c168870a
AM		 900{
901 long mask = (insn >> 12) & 0xff;
902
903 /* Is this a Power4 insn? */
904 if ((insn & (1 << 20)) != 0)
905 {
98e69875
AM		 906 /* Exactly one bit of MASK should be set. */
907 if (mask == 0 || (mask & -mask) != mask)
8427c424 908 *invalid = 1;
c168870a
AM		 909 }
910
911 /* Check that non-power4 form of mfcr has a zero MASK. */
912 else if ((insn & (0x3ff << 1)) == 19 << 1)
913 {
8427c424 914 if (mask != 0)
c168870a
AM		 915 *invalid = 1;
916 }
917
918 return mask;
919}
920
252b5132
RH		 921/* The MB and ME fields in an M form instruction expressed as a single
922 operand which is itself a bitmask. The extraction function always
923 marks it as invalid, since we never want to recognize an
924 instruction which uses a field of this type. */
925
926static unsigned long
2fbfdc41
AM		 927insert_mbe (unsigned long insn,
928 long value,
929 int dialect ATTRIBUTE_UNUSED,
930 const char **errmsg)
252b5132
RH		 931{
932 unsigned long uval, mask;
933 int mb, me, mx, count, last;
934
935 uval = value;
936
937 if (uval == 0)
938 {
8427c424 939 *errmsg = _("illegal bitmask");
252b5132
RH		 940 return insn;
941 }
942
943 mb = 0;
944 me = 32;
945 if ((uval & 1) != 0)
946 last = 1;
947 else
948 last = 0;
949 count = 0;
950
951 /* mb: location of last 0->1 transition */
952 /* me: location of last 1->0 transition */
953 /* count: # transitions */
954
0deb7ac5 955 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 956 {
957 if ((uval & mask) && !last)
958 {
959 ++count;
960 mb = mx;
961 last = 1;
962 }
963 else if (!(uval & mask) && last)
964 {
965 ++count;
966 me = mx;
967 last = 0;
968 }
969 }
970 if (me == 0)
971 me = 32;
972
973 if (count != 2 && (count != 0 || ! last))
8427c424 974 *errmsg = _("illegal bitmask");
252b5132
RH		 975
976 return insn | (mb << 6) | ((me - 1) << 1);
977}
978
979static long
2fbfdc41
AM		 980extract_mbe (unsigned long insn,
981 int dialect ATTRIBUTE_UNUSED,
982 int *invalid)
252b5132
RH		 983{
984 long ret;
985 int mb, me;
986 int i;
987
8427c424 988 *invalid = 1;
252b5132
RH		 989
990 mb = (insn >> 6) & 0x1f;
991 me = (insn >> 1) & 0x1f;
992 if (mb < me + 1)
993 {
994 ret = 0;
995 for (i = mb; i <= me; i++)
0deb7ac5 996 ret |= 1L << (31 - i);
252b5132
RH		 997 }
998 else if (mb == me + 1)
8427c424 999 ret = ~0;
252b5132
RH		 1000 else /* (mb > me + 1) */
1001 {
2fbfdc41 1002 ret = ~0;
252b5132 1003 for (i = me + 1; i < mb; i++)
0deb7ac5 1004 ret &= ~(1L << (31 - i));
252b5132
RH		 1005 }
1006 return ret;
1007}
1008
1009/* The MB or ME field in an MD or MDS form instruction. The high bit
1010 is wrapped to the low end. */
1011
252b5132 1012static unsigned long
2fbfdc41
AM		 1013insert_mb6 (unsigned long insn,
1014 long value,
1015 int dialect ATTRIBUTE_UNUSED,
1016 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1017{
1018 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1019}
1020
252b5132 1021static long
2fbfdc41
AM		 1022extract_mb6 (unsigned long insn,
1023 int dialect ATTRIBUTE_UNUSED,
1024 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1025{
1026 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1027}
1028
1029/* The NB field in an X form instruction. The value 32 is stored as
1030 0. */
1031
252b5132 1032static long
2fbfdc41
AM		 1033extract_nb (unsigned long insn,
1034 int dialect ATTRIBUTE_UNUSED,
1035 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1036{
1037 long ret;
1038
1039 ret = (insn >> 11) & 0x1f;
1040 if (ret == 0)
1041 ret = 32;
1042 return ret;
1043}
1044
1045/* The NSI field in a D form instruction. This is the same as the SI
1046 field, only negated. The extraction function always marks it as
1047 invalid, since we never want to recognize an instruction which uses
1048 a field of this type. */
1049
252b5132 1050static unsigned long
2fbfdc41
AM		 1051insert_nsi (unsigned long insn,
1052 long value,
1053 int dialect ATTRIBUTE_UNUSED,
1054 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1055{
2fbfdc41 1056 return insn | (-value & 0xffff);
252b5132
RH		 1057}
1058
1059static long
2fbfdc41
AM		 1060extract_nsi (unsigned long insn,
1061 int dialect ATTRIBUTE_UNUSED,
1062 int *invalid)
252b5132 1063{
8427c424 1064 *invalid = 1;
2fbfdc41 1065 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1066}
1067
1068/* The RA field in a D or X form instruction which is an updating
1069 load, which means that the RA field may not be zero and may not
1070 equal the RT field. */
1071
1072static unsigned long
2fbfdc41
AM		 1073insert_ral (unsigned long insn,
1074 long value,
1075 int dialect ATTRIBUTE_UNUSED,
1076 const char **errmsg)
252b5132
RH		 1077{
1078 if (value == 0
1079 || (unsigned long) value == ((insn >> 21) & 0x1f))
1080 *errmsg = "invalid register operand when updating";
1081 return insn | ((value & 0x1f) << 16);
1082}
1083
1084/* The RA field in an lmw instruction, which has special value
1085 restrictions. */
1086
1087static unsigned long
2fbfdc41
AM		 1088insert_ram (unsigned long insn,
1089 long value,
1090 int dialect ATTRIBUTE_UNUSED,
1091 const char **errmsg)
252b5132
RH		 1092{
1093 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1094 *errmsg = _("index register in load range");
1095 return insn | ((value & 0x1f) << 16);
1096}
1097
fdd12ef3 1098/* The RA field in the DQ form lq instruction, which has special
8427c424 1099 value restrictions. */
adadcc0c 1100
adadcc0c 1101static unsigned long
2fbfdc41
AM		 1102insert_raq (unsigned long insn,
1103 long value,
1104 int dialect ATTRIBUTE_UNUSED,
1105 const char **errmsg)
adadcc0c
AM		 1106{
1107 long rtvalue = (insn & RT_MASK) >> 21;
1108
8427c424 1109 if (value == rtvalue)
adadcc0c
AM		 1110 *errmsg = _("source and target register operands must be different");
1111 return insn | ((value & 0x1f) << 16);
1112}
1113
252b5132
RH		 1114/* The RA field in a D or X form instruction which is an updating
1115 store or an updating floating point load, which means that the RA
1116 field may not be zero. */
1117
1118static unsigned long
2fbfdc41
AM		 1119insert_ras (unsigned long insn,
1120 long value,
1121 int dialect ATTRIBUTE_UNUSED,
1122 const char **errmsg)
252b5132
RH		 1123{
1124 if (value == 0)
1125 *errmsg = _("invalid register operand when updating");
1126 return insn | ((value & 0x1f) << 16);
1127}
1128
1129/* The RB field in an X form instruction when it must be the same as
1130 the RS field in the instruction. This is used for extended
1131 mnemonics like mr. This operand is marked FAKE. The insertion
1132 function just copies the BT field into the BA field, and the
1133 extraction function just checks that the fields are the same. */
1134
252b5132 1135static unsigned long
2fbfdc41
AM		 1136insert_rbs (unsigned long insn,
1137 long value ATTRIBUTE_UNUSED,
1138 int dialect ATTRIBUTE_UNUSED,
1139 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1140{
1141 return insn | (((insn >> 21) & 0x1f) << 11);
1142}
1143
1144static long
2fbfdc41
AM		 1145extract_rbs (unsigned long insn,
1146 int dialect ATTRIBUTE_UNUSED,
1147 int *invalid)
252b5132 1148{
8427c424 1149 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1150 *invalid = 1;
1151 return 0;
1152}
1153
1154/* The SH field in an MD form instruction. This is split. */
1155
252b5132 1156static unsigned long
2fbfdc41
AM		 1157insert_sh6 (unsigned long insn,
1158 long value,
1159 int dialect ATTRIBUTE_UNUSED,
1160 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1161{
1162 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1163}
1164
252b5132 1165static long
2fbfdc41
AM		 1166extract_sh6 (unsigned long insn,
1167 int dialect ATTRIBUTE_UNUSED,
1168 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1169{
1170 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1171}
1172
1173/* The SPR field in an XFX form instruction. This is flipped--the
1174 lower 5 bits are stored in the upper 5 and vice- versa. */
1175
1176static unsigned long
2fbfdc41
AM		 1177insert_spr (unsigned long insn,
1178 long value,
1179 int dialect ATTRIBUTE_UNUSED,
1180 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1181{
1182 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1183}
1184
1185static long
2fbfdc41
AM		 1186extract_spr (unsigned long insn,
1187 int dialect ATTRIBUTE_UNUSED,
1188 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1189{
1190 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1191}
1192
da99ee72
AM		 1193/* Some dialects have 8 SPRG registers instead of the standard 4. */
1194
1195static unsigned long
1196insert_sprg (unsigned long insn,
1197 long value,
1198 int dialect,
1199 const char **errmsg)
1200{
1201 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1202 as a synonym. If ever a 405 specific dialect is added this
1203 check should use that instead. */
1204 if (value > 7
1205 || (value > 3
1206 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1207 *errmsg = _("invalid sprg number");
1208
1209 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1210 user mode. Anything else must use spr 272..279. */
1211 if (value <= 3 || (insn & 0x100) != 0)
1212 value |= 0x10;
1213
1214 return insn | ((value & 0x17) << 16);
1215}
1216
1217static long
1218extract_sprg (unsigned long insn,
1219 int dialect,
1220 int *invalid)
1221{
1222 unsigned long val = (insn >> 16) & 0x1f;
1223
1224 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1225 If not BOOKE or 405, then both use only 272..275. */
1226 if (val <= 3
1227 || (val < 0x10 && (insn & 0x100) != 0)
1228 || (val - 0x10 > 3
1229 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1230 *invalid = 1;
1231 return val & 7;
1232}
1233
252b5132
RH		 1234/* The TBR field in an XFX instruction. This is just like SPR, but it
1235 is optional. When TBR is omitted, it must be inserted as 268 (the
1236 magic number of the TB register). These functions treat 0
1237 (indicating an omitted optional operand) as 268. This means that
1238 ``mftb 4,0'' is not handled correctly. This does not matter very
1239 much, since the architecture manual does not define mftb as
1240 accepting any values other than 268 or 269. */
1241
1242#define TB (268)
1243
1244static unsigned long
2fbfdc41
AM		 1245insert_tbr (unsigned long insn,
1246 long value,
1247 int dialect ATTRIBUTE_UNUSED,
1248 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1249{
1250 if (value == 0)
1251 value = TB;
1252 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1253}
1254
1255static long
2fbfdc41
AM		 1256extract_tbr (unsigned long insn,
1257 int dialect ATTRIBUTE_UNUSED,
1258 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1259{
1260 long ret;
1261
1262 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1263 if (ret == TB)
1264 ret = 0;
1265 return ret;
1266}
1267\f
1268/* Macros used to form opcodes. */
1269
1270/* The main opcode. */
1271#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1272#define OP_MASK OP (0x3f)
1273
1274/* The main opcode combined with a trap code in the TO field of a D
1275 form instruction. Used for extended mnemonics for the trap
1276 instructions. */
1277#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1278#define OPTO_MASK (OP_MASK | TO_MASK)
1279
1280/* The main opcode combined with a comparison size bit in the L field
1281 of a D form or X form instruction. Used for extended mnemonics for
1282 the comparison instructions. */
1283#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1284#define OPL_MASK OPL (0x3f,1)
1285
1286/* An A form instruction. */
1287#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1288#define A_MASK A (0x3f, 0x1f, 1)
1289
1290/* An A_MASK with the FRB field fixed. */
1291#define AFRB_MASK (A_MASK | FRB_MASK)
1292
1293/* An A_MASK with the FRC field fixed. */
1294#define AFRC_MASK (A_MASK | FRC_MASK)
1295
1296/* An A_MASK with the FRA and FRC fields fixed. */
1297#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1298
702f0fb4
PB		 1299/* An AFRAFRC_MASK, but with L bit clear. */
1300#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1301
252b5132
RH		 1302/* A B form instruction. */
1303#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1304#define B_MASK B (0x3f, 1, 1)
1305
1306/* A B form instruction setting the BO field. */
1307#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1308#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1309
1310/* A BBO_MASK with the y bit of the BO field removed. This permits
1311 matching a conditional branch regardless of the setting of the y
94efba12 1312 bit. Similarly for the 'at' bits used for power4 branch hints. */
802a735e
AM		 1313#define Y_MASK (((unsigned long) 1) << 21)
1314#define AT1_MASK (((unsigned long) 3) << 21)
1315#define AT2_MASK (((unsigned long) 9) << 21)
1316#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1317#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1318
1319/* A B form instruction setting the BO field and the condition bits of
1320 the BI field. */
1321#define BBOCB(op, bo, cb, aa, lk) \
1322 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1323#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1324
1325/* A BBOCB_MASK with the y bit of the BO field removed. */
1326#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1327#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1328#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1329
1330/* A BBOYCB_MASK in which the BI field is fixed. */
1331#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1332#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1333
23976049
EZ		 1334/* An Context form instruction. */
1335#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1336#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1337
1338/* An User Context form instruction. */
1339#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1340#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1341
252b5132
RH		 1342/* The main opcode mask with the RA field clear. */
1343#define DRA_MASK (OP_MASK | RA_MASK)
1344
1345/* A DS form instruction. */
1346#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1347#define DS_MASK DSO (0x3f, 3)
1348
418c1742
MG		 1349/* A DE form instruction. */
1350#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1351#define DE_MASK DEO (0x3e, 0xf)
1352
23976049
EZ		 1353/* An EVSEL form instruction. */
1354#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1355#define EVSEL_MASK EVSEL(0x3f, 0xff)
1356
252b5132
RH		 1357/* An M form instruction. */
1358#define M(op, rc) (OP (op) | ((rc) & 1))
1359#define M_MASK M (0x3f, 1)
1360
1361/* An M form instruction with the ME field specified. */
1362#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1363
1364/* An M_MASK with the MB and ME fields fixed. */
1365#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1366
1367/* An M_MASK with the SH and ME fields fixed. */
1368#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1369
1370/* An MD form instruction. */
1371#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1372#define MD_MASK MD (0x3f, 0x7, 1)
1373
1374/* An MD_MASK with the MB field fixed. */
1375#define MDMB_MASK (MD_MASK | MB6_MASK)
1376
1377/* An MD_MASK with the SH field fixed. */
1378#define MDSH_MASK (MD_MASK | SH6_MASK)
1379
1380/* An MDS form instruction. */
1381#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1382#define MDS_MASK MDS (0x3f, 0xf, 1)
1383
1384/* An MDS_MASK with the MB field fixed. */
1385#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1386
1387/* An SC form instruction. */
1388#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1389#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1390
112290ab 1391/* An VX form instruction. */
786e2c0f
C		 1392#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1393
112290ab 1394/* The mask for an VX form instruction. */
786e2c0f
C		 1395#define VX_MASK VX(0x3f, 0x7ff)
1396
112290ab 1397/* An VA form instruction. */
2613489e 1398#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1399
112290ab 1400/* The mask for an VA form instruction. */
2613489e 1401#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1402
112290ab 1403/* An VXR form instruction. */
786e2c0f
C		 1404#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1405
112290ab 1406/* The mask for a VXR form instruction. */
786e2c0f
C		 1407#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1408
252b5132
RH		 1409/* An X form instruction. */
1410#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1411
702f0fb4
PB		 1412/* A Z form instruction. */
1413#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1414
252b5132
RH		 1415/* An X form instruction with the RC bit specified. */
1416#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1417
702f0fb4
PB		 1418/* A Z form instruction with the RC bit specified. */
1419#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1420
252b5132
RH		 1421/* The mask for an X form instruction. */
1422#define X_MASK XRC (0x3f, 0x3ff, 1)
1423
702f0fb4
PB		 1424/* The mask for a Z form instruction. */
1425#define Z_MASK ZRC (0x3f, 0x1ff, 1)
0bbdef92 1426#define Z2_MASK ZRC (0x3f, 0xff, 1)
702f0fb4 1427
252b5132
RH		 1428/* An X_MASK with the RA field fixed. */
1429#define XRA_MASK (X_MASK | RA_MASK)
1430
ea192fa3
PB		 1431/* An XRA_MASK with the W field clear. */
1432#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1433
252b5132
RH		 1434/* An X_MASK with the RB field fixed. */
1435#define XRB_MASK (X_MASK | RB_MASK)
1436
1437/* An X_MASK with the RT field fixed. */
1438#define XRT_MASK (X_MASK | RT_MASK)
1439
702f0fb4
PB		 1440/* An XRT_MASK mask with the L bits clear. */
1441#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1442
252b5132
RH		 1443/* An X_MASK with the RA and RB fields fixed. */
1444#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1445
112290ab 1446/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1447#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1448
252b5132
RH		 1449/* An X_MASK with the RT and RA fields fixed. */
1450#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1451
98acc1c5
AM		 1452/* An XRTRA_MASK, but with L bit clear. */
1453#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1454
f3806e43
BE		 1455/* An X form instruction with the L bit specified. */
1456#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132
RH		 1457
1458/* The mask for an X form comparison instruction. */
1459#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1460
520ceea4
BE		 1461/* The mask for an X form comparison instruction with the L field
1462 fixed. */
1463#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1464
1465/* An X form trap instruction with the TO field specified. */
1466#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1467#define XTO_MASK (X_MASK | TO_MASK)
1468
e0c21649
GK		 1469/* An X form tlb instruction with the SH field specified. */
1470#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1471#define XTLB_MASK (X_MASK | SH_MASK)
1472
6ba045b1
AM		 1473/* An X form sync instruction. */
1474#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1475
1476/* An X form sync instruction with everything filled in except the LS field. */
1477#define XSYNC_MASK (0xff9fffff)
1478
702f0fb4
PB		 1479/* An X_MASK, but with the EH bit clear. */
1480#define XEH_MASK (X_MASK & ~((unsigned long )1))
1481
f5c120c5
MG		 1482/* An X form AltiVec dss instruction. */
1483#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1484#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1485
252b5132
RH		 1486/* An XFL form instruction. */
1487#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
ea192fa3 1488#define XFL_MASK XFL (0x3f, 0x3ff, 1)
252b5132 1489
23976049
EZ		 1490/* An X form isel instruction. */
1491#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1492#define XISEL_MASK XISEL(0x3f, 0x1f)
1493
252b5132
RH		 1494/* An XL form instruction with the LK field set to 0. */
1495#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1496
1497/* An XL form instruction which uses the LK field. */
1498#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1499
1500/* The mask for an XL form instruction. */
1501#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1502
1503/* An XL form instruction which explicitly sets the BO field. */
1504#define XLO(op, bo, xop, lk) \
1505 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1506#define XLO_MASK (XL_MASK | BO_MASK)
1507
1508/* An XL form instruction which explicitly sets the y bit of the BO
1509 field. */
1510#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1511#define XLYLK_MASK (XL_MASK | Y_MASK)
1512
1513/* An XL form instruction which sets the BO field and the condition
1514 bits of the BI field. */
1515#define XLOCB(op, bo, cb, xop, lk) \
1516 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1517#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1518
1519/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1520#define XLBB_MASK (XL_MASK | BB_MASK)
1521#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1522#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1523
d0618d1c
AM		 1524/* A mask for branch instructions using the BH field. */
1525#define XLBH_MASK (XL_MASK | (0x1c << 11))
1526
252b5132
RH		 1527/* An XL_MASK with the BO and BB fields fixed. */
1528#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1529
1530/* An XL_MASK with the BO, BI and BB fields fixed. */
1531#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1532
1533/* An XO form instruction. */
1534#define XO(op, xop, oe, rc) \
1535 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1536#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1537
1538/* An XO_MASK with the RB field fixed. */
1539#define XORB_MASK (XO_MASK | RB_MASK)
1540
c3d65c1c
BE		 1541/* An XOPS form instruction for paired singles. */
1542#define XOPS(op, xop, rc) \
1543 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1544#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1545
1546
252b5132
RH		 1547/* An XS form instruction. */
1548#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1549#define XS_MASK XS (0x3f, 0x1ff, 1)
1550
1551/* A mask for the FXM version of an XFX form instruction. */
98e69875 1552#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1553
1554/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1555#define XFXM(op, xop, fxm, p4) \
1556 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1557 | ((unsigned long)(p4) << 20))
252b5132
RH		 1558
1559/* An XFX form instruction with the SPR field filled in. */
1560#define XSPR(op, xop, spr) \
1561 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1562#define XSPR_MASK (X_MASK | SPR_MASK)
1563
1564/* An XFX form instruction with the SPR field filled in except for the
1565 SPRBAT field. */
1566#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1567
1568/* An XFX form instruction with the SPR field filled in except for the
1569 SPRG field. */
b84bf58a 1570#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
252b5132
RH		 1571
1572/* An X form instruction with everything filled in except the E field. */
1573#define XE_MASK (0xffff7fff)
1574
23976049
EZ		 1575/* An X form user context instruction. */
1576#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1577#define XUC_MASK XUC(0x3f, 0x1f)
1578
c3d65c1c
BE		 1579/* An XW form instruction. */
1580#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1581/* The mask for a G form instruction. rc not supported at present. */
1582#define XW_MASK XW (0x3f, 0x3f, 0)
1583
252b5132
RH		 1584/* The BO encodings used in extended conditional branch mnemonics. */
1585#define BODNZF (0x0)
1586#define BODNZFP (0x1)
1587#define BODZF (0x2)
1588#define BODZFP (0x3)
252b5132
RH		 1589#define BODNZT (0x8)
1590#define BODNZTP (0x9)
1591#define BODZT (0xa)
1592#define BODZTP (0xb)
802a735e
AM		 1593
1594#define BOF (0x4)
1595#define BOFP (0x5)
94efba12
AM		 1596#define BOFM4 (0x6)
1597#define BOFP4 (0x7)
252b5132
RH		 1598#define BOT (0xc)
1599#define BOTP (0xd)
94efba12
AM		 1600#define BOTM4 (0xe)
1601#define BOTP4 (0xf)
802a735e 1602
252b5132
RH		 1603#define BODNZ (0x10)
1604#define BODNZP (0x11)
1605#define BODZ (0x12)
1606#define BODZP (0x13)
94efba12
AM		 1607#define BODNZM4 (0x18)
1608#define BODNZP4 (0x19)
1609#define BODZM4 (0x1a)
1610#define BODZP4 (0x1b)
802a735e 1611
252b5132
RH		 1612#define BOU (0x14)
1613
1614/* The BI condition bit encodings used in extended conditional branch
1615 mnemonics. */
1616#define CBLT (0)
1617#define CBGT (1)
1618#define CBEQ (2)
1619#define CBSO (3)
1620
1621/* The TO encodings used in extended trap mnemonics. */
1622#define TOLGT (0x1)
1623#define TOLLT (0x2)
1624#define TOEQ (0x4)
1625#define TOLGE (0x5)
1626#define TOLNL (0x5)
1627#define TOLLE (0x6)
1628#define TOLNG (0x6)
1629#define TOGT (0x8)
1630#define TOGE (0xc)
1631#define TONL (0xc)
1632#define TOLT (0x10)
1633#define TOLE (0x14)
1634#define TONG (0x14)
1635#define TONE (0x18)
1636#define TOU (0x1f)
1637\f
1638/* Smaller names for the flags so each entry in the opcodes table will
1639 fit on a single line. */
1640#undef PPC
661bd698
AM		 1641#define PPC PPC_OPCODE_PPC
1642#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
94efba12 1643#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
661bd698 1644#define POWER4 PPC_OPCODE_POWER4
1ed8e1e4 1645#define POWER5 PPC_OPCODE_POWER5
702f0fb4 1646#define POWER6 PPC_OPCODE_POWER6
ede602d7 1647#define CELL PPC_OPCODE_CELL
661bd698
AM		 1648#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1649#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
418c1742 1650#define PPC403 PPC_OPCODE_403
e0c21649 1651#define PPC405 PPC403
7d5b217e 1652#define PPC440 PPC_OPCODE_440
252b5132 1653#define PPC750 PPC
33e8d5ac 1654#define PPC7450 PPC
252b5132 1655#define PPC860 PPC
c3d65c1c 1656#define PPCPS PPC_OPCODE_PPCPS
a404d431 1657#define PPCVEC PPC_OPCODE_ALTIVEC
661bd698
AM		 1658#define POWER PPC_OPCODE_POWER
1659#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1660#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1661#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1662#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1663#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1664#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1665#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
252b5132 1666#define MFDEC1 PPC_OPCODE_POWER
dde1b132 1667#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742
MG		 1668#define BOOKE PPC_OPCODE_BOOKE
1669#define BOOKE64 PPC_OPCODE_BOOKE64
23976049 1670#define CLASSIC PPC_OPCODE_CLASSIC
36ae0db3 1671#define PPCE300 PPC_OPCODE_E300
23976049
EZ		 1672#define PPCSPE PPC_OPCODE_SPE
1673#define PPCISEL PPC_OPCODE_ISEL
1674#define PPCEFS PPC_OPCODE_EFS
1675#define PPCBRLK PPC_OPCODE_BRLOCK
1676#define PPCPMR PPC_OPCODE_PMR
1677#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1678#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1679#define PPCRFMCI PPC_OPCODE_RFMCI
252b5132
RH		 1680\f
1681/* The opcode table.
1682
1683 The format of the opcode table is:
1684
1685 NAME OPCODE MASK FLAGS { OPERANDS }
1686
1687 NAME is the name of the instruction.
1688 OPCODE is the instruction opcode.
1689 MASK is the opcode mask; this is used to tell the disassembler
1690 which bits in the actual opcode must match OPCODE.
1691 FLAGS are flags indicated what processors support the instruction.
1692 OPERANDS is the list of operands.
1693
1694 The disassembler reads the table in order and prints the first
1695 instruction which matches, so this table is sorted to put more
1696 specific instructions before more general instructions. It is also
1697 sorted by major opcode. */
1698
1699const struct powerpc_opcode powerpc_opcodes[] = {
adadcc0c 1700{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
252b5132
RH		 1701{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1702{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1703{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1704{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1705{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1706{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1707{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1708{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1709{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1710{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1711{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1712{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1713{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1714{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1715{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1716
1717{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1718{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1719{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1720{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1721{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1722{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1723{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1724{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1725{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1726{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1727{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1728{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1729{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1730{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1731{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1732{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1733{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1734{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1735{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1736{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1737{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1738{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1739{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1740{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1741{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1742{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1743{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1744{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1745{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1746{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649 1747
c3d65c1c
BE		 1748{ "dcbz_l", X(4,1014), XRT_MASK, PPCPS, { RA, RB } },
1749{ "ps_cmpu0", X(4 ,0), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
1750{ "psq_lx", XW(4,6,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
1751{ "psq_stx", XW(4,7,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
1752{ "ps_sum0", A(4 ,10,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1753{ "ps_sum0.", A(4 ,10,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1754{ "ps_sum1", A(4 ,11,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1755{ "ps_sum1.", A(4 ,11,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1756{ "ps_muls0", A(4 ,12,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
1757{ "ps_muls0.", A(4 ,12,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
1758{ "ps_muls1", A(4 ,13,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
1759{ "ps_muls1.", A(4 ,13,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
1760{ "ps_madds0", A(4 ,14,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1761{ "ps_madds0.", A(4 ,14,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1762{ "ps_madds1", A(4 ,15,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1763{ "ps_madds1.", A(4 ,15,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1764{ "ps_div", A(4,18,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
1765{ "ps_div.", A(4,18,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
1766{ "ps_sub", A(4,20,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
1767{ "ps_sub.", A(4,20,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
1768{ "ps_add", A(4,21,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
1769{ "ps_add.", A(4,21,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
1770{ "ps_sel", A(4,23,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1771{ "ps_sel.", A(4,23,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1772{ "ps_res", A(4,24,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
1773{ "ps_res.", A(4,24,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
1774{ "ps_mul", A(4,25,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
1775{ "ps_mul.", A(4,25,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
1776{ "ps_rsqrte", A(4 ,26,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
1777{ "ps_rsqrte.", A(4 ,26,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
1778{ "ps_madd", A(4,29,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1779{ "ps_madd.", A(4,29,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1780{ "ps_msub", A(4,28,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1781{ "ps_msub.", A(4,28,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1782{ "ps_nmsub", A(4,30,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1783{ "ps_nmsub.", A(4,30,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1784{ "ps_nmadd", A(4,31,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1785{ "ps_nmadd.", A(4,31,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
1786{ "ps_cmpo0", X(4 ,32), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
1787{ "psq_lux", XW(4,38,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
1788{ "psq_stux", XW(4,39,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
1789{ "ps_neg", XRC(4 ,40,0), XRA_MASK, PPCPS, { FRT, FRB } },
1790{ "ps_neg.", XRC(4 ,40,1), XRA_MASK, PPCPS, { FRT, FRB } },
1791{ "ps_cmpu1", X(4 ,64), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
1792{ "ps_mr", XRC(4 ,72,0), XRA_MASK, PPCPS, { FRT, FRB } },
1793{ "ps_mr.", XRC(4 ,72,1), XRA_MASK, PPCPS, { FRT, FRB } },
1794{ "ps_cmpo1", X(4 ,96), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
1795{ "ps_nabs", XRC(4 ,136,0), XRA_MASK, PPCPS, { FRT, FRB } },
1796{ "ps_nabs.", XRC(4 ,136,1), XRA_MASK, PPCPS, { FRT, FRB } },
1797{ "ps_abs", XRC(4,264,0), XRA_MASK, PPCPS, { FRT, FRB } },
1798{ "ps_abs.", XRC(4,264,1), XRA_MASK, PPCPS, { FRT, FRB } },
1799{ "ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
1800{ "ps_merge00.",XOPS(4,528,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
1801{ "ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
1802{ "ps_merge01.",XOPS(4,560,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
1803{ "ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
1804{ "ps_merge10.",XOPS(4,592,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
1805{ "ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
1806{ "ps_merge11.",XOPS(4,624,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
7d5b217e
AM		 1807{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1808{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1809{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1810{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1811{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1812{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1813{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1814{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1815{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1816{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1817{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1818{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1819{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1820{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1821{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1822{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1823{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1824{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1825{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1826{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1827{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1828{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1829{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1830{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1831{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1832{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1833{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1834{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1835{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1836{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1837{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1838{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1839{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1840{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1841{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1842{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1843{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1844{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1845{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1846{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1847{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1848{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1849{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1850{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1851{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1852{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1853{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1854{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1855{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1856{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1857{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1858{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1859{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1860{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1861{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1862{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1863{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1864{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1865{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1866{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1867{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1868{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1869{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1870{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1871{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1872{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1873{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1874{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1875{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
786e2c0f 1891{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 1892{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
12c64a4e
AH		 1893
1894 /* Double-precision opcodes. */
1895 /* Some of these conflict with AltiVec, so move them before, since
1896 PPCVEC includes the PPC_OPCODE_PPC set. */
0e06657a 1897{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
12c64a4e
AH		 1898{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
1899{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
1900{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
1901{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
1902{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
1903{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
1904{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
1905{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1906{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1907{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1908{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1909{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1910{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1911{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
1912{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
1913{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
1914{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
1915{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
1916{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
1917{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
1918{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
1919{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
1920{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
1921{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
1922{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
1923{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
1924{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
1925{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
1926 /* End of double-precision opcodes. */
1927
786e2c0f
C		 1928{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1929{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1930{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1931{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1932{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1933{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1934{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1935{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1936{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1937{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1938{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1939{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1940{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1941{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1942{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1943{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1944{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1945{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1946{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1947{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1948{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1949{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1950{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1951{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1952{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1953{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1954{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1955{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1956{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1957{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1958{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1959{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1960{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1961{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1962{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1963{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1964{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1965{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1966{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1967{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1968{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1969{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1970{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1971{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1972{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1973{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1974{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1975{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1976{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1977{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1978{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
294b41b3 1979{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
786e2c0f
C		 1980{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1981{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1982{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1983{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1984{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1985{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1986{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1987{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1988{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1989{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1990{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1991{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1992{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1993{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1994{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1995{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1996{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1997{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1998{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1999{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2000{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2001{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2002{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2003{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2004{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2005{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 2006{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2007{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2008{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 2009{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2010{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2011{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2012{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2013{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2014{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2015{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2016{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2017{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2018{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2019{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2020{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2021{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2022{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2023{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2024{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2025{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2026{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2027{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2028{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2029{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2030{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2031{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2032{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2033{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2034{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2035{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2036{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2037{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2038{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2039{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2040{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2042{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2043{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2044{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 2045{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 2046{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2047{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2048{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2049{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2050{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2051{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2052{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2053{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2054{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2055{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2056{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2057{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2058{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2059{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2060{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2061{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2062{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2063{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2064{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2065{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2066{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2067{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2068{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2069{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2070{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2071{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2072{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2073{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2074{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2075{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2076{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2077{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2078{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2079{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2080{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2081{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2082{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132 2083
914749f6
AH		 2084{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2085{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2086{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2087{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2088{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2089{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2090{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2091{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2092{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2093{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2094{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2095{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2096{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2097
2098{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2099
2100{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2101{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2102{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2103{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2104{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2105{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2106{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2107{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2108{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2109{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2110
2111{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2112{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2113{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2114{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2115{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2116{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2117{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2118{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2119{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2120{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
fe587977
AH		 2121{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2122{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2123{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2124{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2125
2126{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2127{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2128{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2129{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2130{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6 2131{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
23976049
EZ		 2132
2133{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2134{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2135{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2136{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2137{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2138{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2139{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2140{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2141{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2142{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2143{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2144{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2145{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2146{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2147{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2148{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2149{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2150{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2151{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2152{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2153{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2154{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2155
2156{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2157{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2158{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2159{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2160{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2161{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2162{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2163{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2164{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2165{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2166{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2167{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2168{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2169{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2170
914749f6
AH		 2171{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2172{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2173{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2174{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2175{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2176{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2177{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2178{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2179{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2180{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2181{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2182{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2183{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6
AH		 2184{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2185{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2186{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2187{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2188{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2189{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2190{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2191{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2192{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2193{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2194
2195{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2196{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2197{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2198{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2199{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2200{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2201{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
23976049
EZ		 2202{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2203{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2204{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2205{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2206{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2207{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
914749f6
AH		 2208{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2209{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2210{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2211{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2212{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2213{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2214{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2215{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2216{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2217{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2218
914749f6
AH		 2219{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2220{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2221{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2222{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2223{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2224{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2225{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2226{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2227{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2228{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2229{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2230{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2231{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2232{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2233{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2234{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2235
2236{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2237{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2238{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2239{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2240{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2241{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2242{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2243{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2244{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2245{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2246{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2247{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2248
2249{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2250{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2251{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2252{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2253{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2254{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2255{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2256{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2257{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2258{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2260{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2261
2262{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2263{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2264{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2265{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2266{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2267{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2268
2269{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2270{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2271{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2272{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2273{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2274{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2275
2276{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2277{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2278{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2279{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2280{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2281{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2282{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2283{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2284
914749f6
AH		 2285{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2286{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2287
914749f6 2288{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2289{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2290{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2291{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2292
914749f6 2293{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2294{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2295{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2296{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2297
914749f6
AH		 2298{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2299{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2300{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2301{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2302{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2303{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2304{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2305{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2306
2307{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2308{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2309{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2310{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2311
2312{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2313{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2314{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2315{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2316
2317{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2318{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2319{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2320{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2321
2322{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2323{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2324{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2325{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2326
2327{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2328
2329{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2330{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049 2331
252b5132
RH		 2332{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2333{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2334
2335{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2336{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2337
2338{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2339
418c1742
MG		 2340{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2341{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2342{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2343{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2344
252b5132
RH		 2345{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2346{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
661bd698 2347{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
252b5132
RH		 2348{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2349
2350{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2351{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
661bd698 2352{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
252b5132
RH		 2353{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2354
2355{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2356{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2357{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2358
2359{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2360{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2361{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2362
2363{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2364{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
fdd12ef3
AM		 2365{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2366{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2367{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2368{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
252b5132
RH		 2369
2370{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2371{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
fdd12ef3
AM		 2372{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2373{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2374{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
252b5132 2375
112290ab
NC		 2376{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2377{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2378{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2379{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2380{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2381{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2382{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2383{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2384{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2385{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2386{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2387{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2388{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2389{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2390{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2391{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2392{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2393{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2394{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2395{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2396{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2397{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2398{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2399{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2400{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2401{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2402{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2403{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
802a735e
AM		 2404{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2405{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2406{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2407{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2408{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2409{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2410{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2411{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2412{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2413{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2414{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2415{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2416{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2417{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2418{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2419{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2420{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2421{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2422{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2423{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2424{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2425{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2426{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2427{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2428{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2429{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2430{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2431{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2432{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2433{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2434{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2435{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2436{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2437{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2438{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2439{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2440{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2441{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2442{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2443{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2444{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2445{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2446{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2447{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2448{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2449{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2450{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2451{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2452{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2453{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2454{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2455{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2456{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2457{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2458{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2459{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2460{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2461{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2462{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2463{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2464{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2465{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2466{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2467{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2468{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2469{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2470{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2471{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2472{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2473{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2474{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2475{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2476{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2477{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2478{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2479{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2480{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2481{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2482{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2483{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2484{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2485{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2486{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2487{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2488{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2489{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2490{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2491{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2494{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2495{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2496{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2497{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2500{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2501{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2502{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2503{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2506{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2507{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2508{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2509{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2512{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2513{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2514{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2515{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2518{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2519{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2520{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2521{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2524{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2525{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2526{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2527{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2528{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2529{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2530{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2531{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2532{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2533{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2534{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2535{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2536{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2537{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2538{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2539{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2540{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2541{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2542{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2543{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2544{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2545{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2546{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2547{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
94efba12
AM		 2548{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2549{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2550{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2551{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2552{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2553{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2554{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2555{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2556{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2557{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2558{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2559{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2560{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2561{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2562{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2563{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2564{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2565{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2566{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2567{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2568{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2569{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2570{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2571{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2572{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2573{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2574{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2575{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2576{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2577{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2578{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2579{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2580{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2581{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2582{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2583{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2584{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2585{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2586{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2587{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2588{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2589{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2590{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2591{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2592{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2593{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2594{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2595{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2596{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2597{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2598{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2599{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2600{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2601{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2602{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2603{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
94efba12
AM		 2604{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2605{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2606{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2607{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2608{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2609{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2610{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2611{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2612{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2613{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2614{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2615{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2616{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2617{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2618{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2619{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2620{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2621{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2622{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2623{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2624{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2625{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2626{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2627{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2628{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2629{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2630{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2631{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2632{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2633{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2634{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2635{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2636{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2637{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2638{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2639{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2640
1ed8e1e4
AM		 2641{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2642{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2643{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
252b5132
RH		 2644{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2645{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2646
418c1742
MG		 2647{ "b", B(18,0,0), B_MASK, COM, { LI } },
2648{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2649{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2650{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132 2651
112290ab 2652{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
252b5132
RH		 2653
2654{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2655{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2656{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2657{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2658{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2659{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2660{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2661{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2662{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2663{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2664{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2665{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2666{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2667{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2668{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2669{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2670{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2671{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2672{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2673{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2674{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2675{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2676{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2677{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2678{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2679{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2680{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2681{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2682{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2683{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2684{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2685{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2686{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2687{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2688{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2689{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2690{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2691{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2692{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2693{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2694{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2695{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2696{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2697{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2698{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2699{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2700{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2701{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2702{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2703{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2704{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2705{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2706{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2707{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2708{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2709{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2710{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2711{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2712{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2713{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2714{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2715{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2716{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2717{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2718{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2719{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2720{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2721{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2722{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2723{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2724{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2725{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2726{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2727{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2728{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2729{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2730{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2731{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2732{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2733{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2734{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2735{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2736{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2737{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2738{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2739{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2740{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2741{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2742{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2743{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2744{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2745{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2746{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2747{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2748{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2749{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2750{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2751{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2752{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2753{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2754{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2755{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2756{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2757{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2758{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2759{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2760{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2761{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2762{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2763{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2764{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2765{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2766{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2767{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2768{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2769{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2770{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2771{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2772{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2773{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2774{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2775{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2776{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2777{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2778{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2779{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2780{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2781{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2782{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2783{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2784{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2785{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2786{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2787{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2788{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2789{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2790{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2791{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2792{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2793{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2794{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2795{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2796{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2797{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2798{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2799{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2800{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2801{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2802{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2803{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2804{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2805{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2806{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2807{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2808{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2809{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2810{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2811{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2812{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2813{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2814{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2815{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2816{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2817{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2818{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2819{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2820{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2821{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2822{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2823{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2824{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2825{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2826{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2827{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2828{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2829{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2830{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2831{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2832{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2833{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2834{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2835{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2836{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2837{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2838{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2839{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2840{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2841{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2842{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2843{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2844{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2845{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2846{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2847{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2848{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2849{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2850{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2851{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2852{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2853{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2854{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2855{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2856{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2857{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2858{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2859{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2860{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2861{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2862{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2863{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2864{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2865{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
d2f75a6f
GK		 2866{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2867{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2868{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2869{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
d0618d1c
AM		 2870{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2871{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
252b5132
RH		 2872{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2873{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2874{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2875{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 2876
f509565f
GK		 2877{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2878
252b5132
RH		 2879{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2880{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
112290ab 2881{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
252b5132
RH		 2882
2883{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
823bbe9d 2884{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
252b5132
RH		 2885
2886{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2887
2888{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2889
2890{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2891{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2892
2893{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2894{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2895
2896{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2897
2898{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2899
ede602d7 2900{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
1ed8e1e4 2901
252b5132
RH		 2902{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2903{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2904
702f0fb4
PB		 2905{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
2906
252b5132
RH		 2907{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2908
702f0fb4
PB		 2909{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
2910
252b5132
RH		 2911{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2912{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2913
702f0fb4
PB		 2914{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
2915{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
2916
252b5132
RH		 2917{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2918{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2919{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2920{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2921{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2922{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2923{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2924{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2925{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2926{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2927{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2928{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2929{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2930{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2931{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2932{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2933{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2934{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2935{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2936{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2937{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2938{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2939{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2940{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2941{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2942{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2943{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2944{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2945{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2946{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2947{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2948{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2949{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2950{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2951{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2952{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2953{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2954{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2955{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2956{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2957{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2958{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2959{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2960{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2961{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2962{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2963{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2964{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2965{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2966{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2967{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2968{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2969{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2970{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2971{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2972{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2973{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2974{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2975{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2976{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2977{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2978{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2979{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2980{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2981{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2982{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2983{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2984{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2985{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2986{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2987{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2988{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2989{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2990{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2991{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2992{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2993{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2994{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2995{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2996{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2997{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2998{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2999{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3000{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3001{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3002{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3003{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3004{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3005{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3006{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3007{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3008{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3009{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3010{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3011{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3012{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3013{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3014{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3015{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3016{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3017{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3018{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3019{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3020{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3021{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3022{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3023{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3024{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3025{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3026{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3027{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3028{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3029{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3030{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3031{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3032{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3033{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3034{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3035{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3036{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3037{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3038{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3039{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3040{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3041{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3042{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3043{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3044{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3045{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3046{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3047{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3048{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3049{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3050{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3051{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3052{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3053{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3054{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3055{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3056{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3057{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3058{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
d2f75a6f
GK		 3059{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3060{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
d2f75a6f
GK		 3061{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3062{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
d0618d1c
AM		 3063{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3064{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
252b5132
RH		 3065{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3066{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
b84bf58a
AM		 3067{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
3068{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 3069
3070{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3071{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3072
3073{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3074{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3075
3076{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3077{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3078{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3079{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3080{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3081{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3082{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3083{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3084
3085{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3086{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3087
418c1742
MG		 3088{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3089{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3090{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3091{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3092
252b5132
RH		 3093{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3094{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3095{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3096{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3097{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3098{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3099
3100{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3101{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3102{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3103
3104{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3105{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3106
3107{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3108{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3109
3110{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3111{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3112
3113{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3114{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3115
3116{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3117{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3118
3119{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3120{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3121{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3122{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3123{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3124{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3125
3126{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3127{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3128
3129{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3130{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3131
3132{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3133{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3134
3135{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3136{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3137{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3138{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3139
3140{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3141{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3142
520ceea4
BE		 3143{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3144{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
661bd698 3145{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
520ceea4 3146{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
252b5132
RH		 3147
3148{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3149{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3150{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3151{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3152{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3153{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3154{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3155{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3156{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3157{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3158{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3159{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3160{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3161{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3162{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3163{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3164{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3165{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3166{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3167{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3168{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3169{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3170{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3171{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3172{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3173{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3174{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3175{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3176{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3177{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3178{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3179
3180{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3181{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3182{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3183{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3184{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3185{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3186{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3187{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3188{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3189{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3190{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3191{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3192
3193{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3194{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3195
3196{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3197{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3198{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3199{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3200{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3201{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3202{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3203{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3204
3205{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3206{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3207
dde1b132
NC		 3208{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3209{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3210{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3211{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
23976049 3212
98e69875 3213{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
a9353e60 3214{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
c168870a 3215{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
252b5132 3216
702f0fb4 3217{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
252b5132 3218
fdd12ef3 3219{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
252b5132 3220
36ae0db3 3221{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
823bbe9d 3222{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
418c1742 3223
fdd12ef3 3224{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 3225{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3226
3227{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3228{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3229{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3230{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3231
3232{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3233{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3234{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3235{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3236
3237{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3238{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3239
3240{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3241{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3242
3243{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3244{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3245
418c1742
MG		 3246{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3247
fdd12ef3 3248{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3249
520ceea4
BE		 3250{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3251{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
661bd698 3252{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
520ceea4 3253{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
252b5132
RH		 3254
3255{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3256{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3257{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3258{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3259{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3260{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3261{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3262{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3263
3264{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3265
3266{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3267
3268{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3269{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3270
418c1742
MG		 3271{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3272
3273{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3274
252b5132
RH		 3275{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3276{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3277
418c1742
MG		 3278{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3279{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 3280
3281{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3282{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3283{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3284{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3285{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3286{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3287{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3288{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3289{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3290{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3291{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3292{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3293{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3294{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3295{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3296
3297{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3298{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3299
3300{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3301{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3302
7d5b217e
AM		 3303{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3304{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3305
f509565f
GK		 3306{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3307
252b5132
RH		 3308{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3309
702f0fb4 3310{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
252b5132 3311
702f0fb4 3312{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
717bbdf1 3313{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
252b5132 3314
fdd12ef3 3315{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
252b5132 3316
418c1742
MG		 3317{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3318
fdd12ef3 3319{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3320
252b5132
RH		 3321{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3322{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3323{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3324{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3325
3326{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3327{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3328{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3329{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3330
f509565f
GK		 3331{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3332
2dd46b8b 3333{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 3334
3335{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3336
1ed8e1e4
AM		 3337{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3338
252b5132
RH		 3339{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3340{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3341{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3342{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3343
fdd12ef3 3344{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742
MG		 3345
3346{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3347
823bbe9d 3348{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
252b5132 3349
23976049
EZ		 3350{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3351
252b5132
RH		 3352{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3353{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3354{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3355{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3356{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3357{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3358{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3359{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3360
3361{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3362{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3363{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3364{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3365{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3366{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3367{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3368{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3369
dde1b132 3370{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3371
98e69875
AM		 3372{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3373{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
252b5132
RH		 3374{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3375
3376{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3377
fdd12ef3 3378{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
252b5132 3379
fdd12ef3 3380{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
252b5132 3381
fdd12ef3 3382{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
252b5132
RH		 3383{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3384
fdd12ef3 3385{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3386
fdd12ef3 3387{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3388
252b5132
RH		 3389{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3390{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3391
3392{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3393{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3394
702f0fb4
PB		 3395{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3396
823bbe9d 3397{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
252b5132 3398
23976049 3399{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
dde1b132 3400{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3401
717bbdf1 3402{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
f509565f 3403
252b5132
RH		 3404{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3405
3406{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
fdd12ef3 3407{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132
RH		 3408
3409{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3410{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3411
702f0fb4
PB		 3412{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3413
418c1742
MG		 3414{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3415
252b5132
RH		 3416{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3417{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3418{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3419{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3420{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3421{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3422{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3423{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3424
3425{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3426{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3427{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3428{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3429{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3430{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3431{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3432{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3433
3434{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3435
fdd12ef3 3436{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
252b5132 3437
fdd12ef3 3438{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
252b5132
RH		 3439
3440{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3441{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3442
3443{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3444{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3445
fdd12ef3 3446{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3447
23976049
EZ		 3448{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3449
252b5132
RH		 3450{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3451{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3452{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3453{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3454{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3455{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3456{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3457{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3458
3459{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3460{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3461{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3462{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3463
3464{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3465{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3466{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3467{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3468{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3469{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3470{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3471{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3472
3473{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3474{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3475{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3476{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3477{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3478{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3479{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3480{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3481
dde1b132 3482{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
252b5132
RH		 3483{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3484{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3485
e5d2b64f 3486{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3487
3488{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3489
3490{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3491{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3492
418c1742
MG		 3493{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3494
3495{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3496
9fa87a06
MG		 3497{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3498
252b5132
RH		 3499{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3500{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3501{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3502{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3503
3504{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3505{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3506{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3507{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3508{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3509{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3510{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3511{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3512
5e8cb021 3513{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
c1a34e60 3514
418c1742
MG		 3515{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3516
252b5132
RH		 3517{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3518{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3519
ede602d7 3520{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
252b5132 3521
fdd12ef3 3522{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
252b5132 3523
252b5132
RH		 3524{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3525{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3526
418c1742
MG		 3527{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3528
fdd12ef3 3529{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3530
98acc1c5 3531{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
fdd12ef3 3532{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
252b5132
RH		 3533
3534{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3535
3536{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3537
3538{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3539{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3540
418c1742
MG		 3541{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3542
dde1b132
NC		 3543{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3544{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3545{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3546{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3547{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3548{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3549{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3550{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3551{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3552{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3553{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3554{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3555{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3556{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3557{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3558{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3559{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3560{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3561{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3562{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3563{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3564{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3565{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3566{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3567{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3568{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3569{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3570{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3571{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3572{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3573{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3574{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3575{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
dde1b132 3576{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
823bbe9d 3577{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
252b5132
RH		 3578
3579{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3580{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3581{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3582{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3583
914749f6 3584{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
23976049 3585
dde1b132
NC		 3586{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3587{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3588{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3589{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3590{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
823bbe9d 3591{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
dde1b132
NC		 3592{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3593{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3594{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3595{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3596{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
dde1b132
NC		 3597{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3598{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3599{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3600{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
702f0fb4 3601{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
dde1b132 3602{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3603{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3604{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3605{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3606{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3607{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
dde1b132 3608{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3609{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3610{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3611{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3612{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3613{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3614{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3615{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3616{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3617{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3618{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3619{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3620{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3621{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3622{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3623{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3624{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3625{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3626{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3627{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3628{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3629{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
661bd698 3630{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3631{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
661bd698 3632{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3633{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
661bd698 3634{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
da99ee72 3635{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
dde1b132
NC		 3636{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3637{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3638{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3639{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
da99ee72
AM		 3640{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3641{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3642{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3643{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
dde1b132
NC		 3644{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3645{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3646{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3647{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3648{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3649{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
dde1b132 3650{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3651{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
dde1b132 3652{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3653{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
dde1b132
NC		 3654{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3655{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3656{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
dde1b132 3657{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3658{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
dde1b132 3659{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3660{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
dde1b132 3661{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3662{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
dde1b132 3663{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3664{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
dde1b132 3665{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3666{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
dde1b132 3667{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3668{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
dde1b132 3669{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3670{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
dde1b132 3671{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3672{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
dde1b132 3673{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3674{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3675{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3676{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3677{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3678{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3679{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3680{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3681{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3682{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3683{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3684{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3685{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3686{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3687{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3688{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3689{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3690{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3691{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3692{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
914749f6 3693{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
f0b26da6
AH		 3694{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3695{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3696{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
2f3b8700 3697{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
dde1b132
NC		 3698{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3699{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3700{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3701{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3702{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3703{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3704{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3705{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3706{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
dde1b132 3707{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
1f04b05f 3708{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
dde1b132
NC		 3709{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3710{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
23d59c56 3711{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
dde1b132
NC		 3712{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3713{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3714{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3715{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3716{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3717{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3718{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3719{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3720{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3721{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3722{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3723{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3724{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3725{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3726{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3727{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3728{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3729{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3730{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3731{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3732{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3733{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3734{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3735{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3736{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3737{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3738{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3739{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3740{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3741{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
dde1b132 3742{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3743{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3744{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3745{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3746{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3747{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3748{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3749{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3750{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3751{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3752{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3753{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
dde1b132 3754{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3755{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3756{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3757{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3758{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3759{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3760{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3761{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3762{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3763{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3764{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3765{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3766{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3767{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3768{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3769{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3770{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3771{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3772{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3773{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
252b5132 3774
fdd12ef3 3775{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
252b5132 3776
f5c120c5
MG		 3777{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3778{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3779
fdd12ef3 3780{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
252b5132 3781
fdd12ef3 3782{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3783
f5c120c5
MG		 3784{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3785{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3786
7d5b217e 3787{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132
RH		 3788
3789{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3790{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3791{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3792{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3793
3794{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3795{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3796{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3797{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3798
3799{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3800
252b5132
RH		 3801{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3802
3803{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3804
418c1742
MG		 3805{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3806
9fa87a06
MG		 3807{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3808
23976049
EZ		 3809{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3810
418c1742
MG		 3811{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3812{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3813
3814{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3816
dde1b132 3817{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3818
6ba045b1
AM		 3819{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3820
fdd12ef3 3821{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
252b5132 3822
702f0fb4
PB		 3823{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
3824
252b5132
RH		 3825{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3826
702f0fb4
PB		 3827{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
3828
252b5132
RH		 3829{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3830
3831{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3832
702f0fb4
PB		 3833{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
3834
252b5132
RH		 3835{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3836
3837{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3838{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3839
3840{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3841{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3842
fdd12ef3 3843{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3844
252b5132
RH		 3845{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3846
3847{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3848
3849{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3850
418c1742
MG		 3851{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3852
360b1600
AM		 3853{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
3854{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
3855{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
3856{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
3857{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
3858{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
3859{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
252b5132
RH		 3860{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3861{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3862{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3863{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3864
823bbe9d
AM		 3865{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3866{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3867{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3868{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3869{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3870{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3871{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3872{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3873{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3874{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3875{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3876{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3877{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3878{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3879{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3880{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3881{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3882{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3883{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3884{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3885{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3886{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3887{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3888{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3889{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3890{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3891{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3892{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3893{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3894{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3895{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3896{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3897{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3898{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3899{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
252b5132 3900
418c1742
MG		 3901{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3902{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3903
252b5132
RH		 3904{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3905{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3906{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3907{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3908
418c1742
MG		 3909{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3910{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3911
252b5132
RH		 3912{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3913{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3914{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3915{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3916
dde1b132
NC		 3917{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3918{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3919{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3920{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3921{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3922{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3923{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3924{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3925{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3926{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3927{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3928{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3929{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3930{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
702f0fb4 3931{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
dde1b132 3932{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3933{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
dde1b132
NC		 3934{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3935{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3936{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3937{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3938{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
dde1b132 3939{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3940{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
dde1b132 3941{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
823bbe9d
AM		 3942{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3943{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3944{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3945{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3946{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3947{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3948{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3949{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3950{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3951{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3952{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3953{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3954{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3955{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3956{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3957{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3958{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
dde1b132 3959{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
da99ee72 3960{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
823bbe9d
AM		 3961{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3962{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3963{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3964{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3965{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3966{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3967{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3968{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
dde1b132
NC		 3969{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3970{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3971{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3972{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3973{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3974{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
dde1b132 3975{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3976{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
dde1b132 3977{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3978{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
dde1b132
NC		 3979{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3980{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3981{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
dde1b132 3982{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3983{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
dde1b132 3984{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3985{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
dde1b132 3986{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3987{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
dde1b132 3988{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3989{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
dde1b132 3990{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3991{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
dde1b132 3992{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3993{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
dde1b132 3994{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3995{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
dde1b132 3996{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3997{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
dde1b132 3998{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
823bbe9d 3999{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
dde1b132
NC		 4000{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4001{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4002{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4003{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4004{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4005{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4006{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4007{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4008{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4009{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4010{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4011{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4012{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4013{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4014{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4015{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
42a2f80a 4016{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
dde1b132 4017{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
914749f6 4018{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
f0b26da6
AH		 4019{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4020{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4021{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
2f3b8700 4022{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
dde1b132
NC		 4023{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4024{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4025{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4026{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4027{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4028{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4029{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
823bbe9d
AM		 4030{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4031{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4032{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4033{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4034{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4035{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4036{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4037{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4038{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4039{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4040{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4041{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4042{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4043{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4044{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4045{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4046{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4047{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4048{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4049{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4050{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4051{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4052{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4053{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4054{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4055{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4056{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4057{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4058{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4059{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4060{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4061{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4062{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4063{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4064{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4065{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4066{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4067{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4068{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
dde1b132 4069{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
252b5132
RH		 4070
4071{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4072
4073{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4074{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4075
418c1742
MG		 4076{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4077
7d5b217e 4078{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
252b5132 4079
914749f6 4080{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
23976049
EZ		 4081
4082{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4083
252b5132 4084{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 4085{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4086{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4087{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 4088{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4089{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4090
4091{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4092{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4093{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4094{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4095
418c1742
MG		 4096{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4097{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4098
252b5132
RH		 4099{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4100{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4101{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4102{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4103
dde1b132 4104{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 4105
252b5132
RH		 4106{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4107
4108{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4109
418c1742
MG		 4110{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4111
252b5132
RH		 4112{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4113
23976049 4114{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
dde1b132 4115{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
418c1742 4116
252b5132
RH		 4117{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4118
ede602d7
AM		 4119{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4120
fdd12ef3 4121{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 4122{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4123
fdd12ef3 4124{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 4125{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4126
fdd12ef3 4127{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
252b5132
RH		 4128
4129{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4130{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4131{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4132{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4133
4134{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4135{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4136
4137{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4138{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4139
4140{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4141{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4142
fdd12ef3 4143{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4144
fdd12ef3 4145{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
418c1742 4146
23976049 4147{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
fdd12ef3 4148
252b5132
RH		 4149{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4150
4151{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4152
418c1742
MG		 4153{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4154
252b5132
RH		 4155{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4156
fdd12ef3
AM		 4157{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4158{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
252b5132 4159
661bd698 4160{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
6ba045b1 4161{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
b6be6416 4162{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
6ba045b1 4163{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132
RH		 4164{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4165
fdd12ef3 4166{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
252b5132 4167
fdd12ef3 4168{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
418c1742 4169
702f0fb4
PB		 4170{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4171
252b5132
RH		 4172{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4173
4174{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4175
4176{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4177
418c1742
MG		 4178{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4179
252b5132
RH		 4180{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4181
ede602d7
AM		 4182{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4183
fdd12ef3
AM		 4184{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4185{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132 4186
fdd12ef3
AM		 4187{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4188{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132 4189
fdd12ef3 4190{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
252b5132
RH		 4191
4192{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4193{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4194
4195{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4196{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4197
fdd12ef3 4198{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4199
fdd12ef3
AM		 4200{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4201
252b5132
RH		 4202{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4203
4204{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4205{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4206
418c1742
MG		 4207{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4208
fdd12ef3
AM		 4209{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4210{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
252b5132 4211
fdd12ef3 4212{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
252b5132
RH		 4213
4214{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4215{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4216
4217{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4218{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4219
fdd12ef3
AM		 4220{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4221
702f0fb4
PB		 4222{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4223
33e8d5ac 4224{ "dcba", X(31,758), XRT_MASK, PPC405 | PPC7450 | BOOKE, { RA, RB } },
e0c21649 4225
252b5132
RH		 4226{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4227
4228{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4229{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4230
418c1742
MG		 4231{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4232
4233{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4234
4235{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
dde1b132 4236{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
418c1742 4237
702f0fb4
PB		 4238{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4239
fdd12ef3 4240{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
252b5132
RH		 4241
4242{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4243{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4244{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4245{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4246
4247{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4248{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4249
fdd12ef3 4250{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4251
fdd12ef3
AM		 4252{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4253{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4254
252b5132
RH		 4255{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4256
702f0fb4
PB		 4257{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4258
f5c120c5 4259{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
eb0fdfed 4260{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
f5c120c5 4261
252b5132
RH		 4262{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4263{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4264{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4265{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4266
6ba045b1
AM		 4267{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4268
702f0fb4
PB		 4269{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4270
b6be6416 4271{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
252b5132
RH		 4272{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4273
702f0fb4
PB		 4274{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4275
4276{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4277
eed0d89a
AM		 4278{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4279{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
b20ae55e
AM		 4280{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
4281{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
418c1742 4282
6ba045b1
AM		 4283{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4284
702f0fb4
PB		 4285{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4286
fdd12ef3 4287{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
252b5132
RH		 4288
4289{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4290{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4291
4292{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4293{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4294
4295{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4296{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4297{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4298{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4299
fdd12ef3 4300{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4301
fdd12ef3 4302{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4303
e0c21649
GK		 4304{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4305{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
eed0d89a 4306{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
252b5132 4307
702f0fb4
PB		 4308{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4309
252b5132
RH		 4310{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4311{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4312
4313{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4314{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4315
418c1742
MG		 4316{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4317
7d5b217e 4318{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132 4319
e0c21649
GK		 4320{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4321{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
fdd12ef3 4322{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
823bbe9d 4323{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
252b5132 4324
702f0fb4
PB		 4325{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4326
252b5132
RH		 4327{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4328
fdd12ef3 4329{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
252b5132 4330
dde1b132
NC		 4331{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4332{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
252b5132 4333
7d5b217e 4334{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132 4335
418c1742 4336{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
fdd12ef3 4337{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
418c1742 4338
252b5132
RH		 4339{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4340
702f0fb4
PB		 4341{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4342
f3806e43 4343{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
252b5132
RH		 4344{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4345{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4346
418c1742
MG		 4347{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4348
786e2c0f
C		 4349{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4350{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4351{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4352{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4353{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4354{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4355{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4356{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4357{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4358{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4359{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4360{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4361
ede602d7
AM		 4362/* New load/store left/right index vector instructions that are in the Cell only. */
4363{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4364{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4365{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4366{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4367{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4368{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4369{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4370{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4371
fdd12ef3
AM		 4372{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4373{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132
RH		 4374
4375{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
fdd12ef3 4376{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132 4377
fdd12ef3 4378{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4379
4380{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4381
fdd12ef3
AM		 4382{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4383{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132
RH		 4384
4385{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
fdd12ef3 4386{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132 4387
fdd12ef3 4388{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
252b5132
RH		 4389
4390{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4391
fdd12ef3 4392{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4393
4394{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4395
fdd12ef3 4396{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4397
4398{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4399
fdd12ef3 4400{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
252b5132
RH		 4401
4402{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4403
4404{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
fdd12ef3 4405{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132 4406
fdd12ef3
AM		 4407{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4408{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132 4409
fdd12ef3 4410{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
252b5132
RH		 4411
4412{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4413
fdd12ef3 4414{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
252b5132
RH		 4415
4416{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4417
fdd12ef3 4418{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
252b5132
RH		 4419
4420{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4421
fdd12ef3 4422{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
252b5132
RH		 4423
4424{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4425
adadcc0c
AM		 4426{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4427
fdd12ef3 4428{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
252b5132 4429
c3d65c1c
BE		 4430{ "psq_l", OP(56), OP_MASK, PPCPS, { FRT, PSD, RA, PSW, PSQ } },
4431
fdd12ef3 4432{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
252b5132 4433
c3d65c1c
BE		 4434{ "psq_lu", OP(57), OP_MASK, PPCPS, { FRT, PSD, RA, PSW, PSQ } },
4435
702f0fb4
PB		 4436{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4437
fdd12ef3 4438{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4439{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4440{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4441{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4442{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4443{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4444{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4445{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4446{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742 4447{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
fdd12ef3 4448{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742 4449{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
fdd12ef3 4450{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742
MG		 4451{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4452
fdd12ef3 4453{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
802a735e
AM		 4454
4455{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4456
fdd12ef3
AM		 4457{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4458
702f0fb4
PB		 4459{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4460{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4461
0bbdef92
AM		 4462{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4463{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
702f0fb4 4464
252b5132
RH		 4465{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4466{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4467
4468{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4469{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4470
4471{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4472{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4473
4474{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4475{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4476
702f0fb4
PB		 4477{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4478{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
252b5132
RH		 4479
4480{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4481{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4482
702f0fb4
PB		 4483{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4484{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
1ed8e1e4 4485
252b5132
RH		 4486{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4487{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4488
4489{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4490{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4491
4492{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4493{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4494
4495{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4496{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4497
c3d65c1c
BE		 4498{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
4499{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
4500
702f0fb4
PB		 4501{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4502{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4503
0bbdef92
AM		 4504{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4505{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
702f0fb4
PB		 4506
4507{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4508{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4509
0bbdef92
AM		 4510{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4511{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
702f0fb4
PB		 4512
4513{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4514{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4515
0bbdef92
AM		 4516{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4517{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
702f0fb4
PB		 4518
4519{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4520
4521{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4522{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4523{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4524
0bbdef92
AM		 4525{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4526{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
702f0fb4
PB		 4527
4528{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4529{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4530
4531{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4532{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4533
4534{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4535{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4536
4537{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4538{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4539
4540{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4541{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4542
4543{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4544{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4545
4546{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4547
4548{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4549
4550{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4551{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4552
4553{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4554{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4555
4556{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4557{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4558
4559{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4560{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4561
252b5132
RH		 4562{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4563
4564{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4565
702f0fb4
PB		 4566{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4567
fdd12ef3
AM		 4568{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4569{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4570{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
418c1742 4571{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
fdd12ef3 4572{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
418c1742 4573{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
fdd12ef3 4574{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
418c1742 4575{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
fdd12ef3 4576{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
418c1742 4577{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
fdd12ef3 4578{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
418c1742
MG		 4579{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4580
fdd12ef3 4581{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
802a735e
AM		 4582
4583{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4584
fdd12ef3
AM		 4585{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4586
252b5132
RH		 4587{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4588
702f0fb4
PB		 4589{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4590{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4591
0bbdef92
AM		 4592{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4593{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
702f0fb4
PB		 4594
4595{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4596{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4597
252b5132
RH		 4598{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4599{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4600
4601{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4602{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4603{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4604{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4605
4606{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4607{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4608{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4609{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4610
4611{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4612{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4613{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4614{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4615
4616{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4617{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4618{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4619{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4620
4621{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4622{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4623{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4624{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4625
4626{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4627{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4628
4629{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4630{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4631
702f0fb4
PB		 4632{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4633{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
1ed8e1e4 4634
252b5132
RH		 4635{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4636{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4637{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4638{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4639
702f0fb4
PB		 4640{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4641{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
252b5132
RH		 4642
4643{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4644{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4645{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4646{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4647
4648{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4649{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4650{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4651{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4652
4653{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4654{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4655{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4656{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4657
4658{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4659{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4660{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4661{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4662
4663{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4664
702f0fb4
PB		 4665{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4666{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4667
0bbdef92
AM		 4668{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4669{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
702f0fb4 4670
252b5132
RH		 4671{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4672{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4673
4674{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4675{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4676
4677{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4678
702f0fb4
PB		 4679{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4680{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4681
0bbdef92
AM		 4682{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4683{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
702f0fb4 4684
252b5132
RH		 4685{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4686{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4687
4688{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4689{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4690
702f0fb4
PB		 4691{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4692{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4693
0bbdef92
AM		 4694{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4695{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
702f0fb4
PB		 4696
4697{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4698
ea192fa3
PB		 4699{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4700{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
252b5132
RH		 4701
4702{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4703{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4704
702f0fb4
PB		 4705{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4706{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4707{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4708
0bbdef92
AM		 4709{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4710{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
702f0fb4
PB		 4711
4712{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4713{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4714
252b5132
RH		 4715{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4716{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4717
702f0fb4
PB		 4718{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4719{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4720
4721{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4722{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4723
4724{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4725{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4726
ce7a772b
AM		 4727{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4728{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4729{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4730{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4731{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4732{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4733{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4734{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4735
702f0fb4
PB		 4736{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4737{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4738
4739{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4740{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4741
252b5132
RH		 4742{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4743{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4744
702f0fb4
PB		 4745{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4746
4747{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4748
ea192fa3
PB		 4749{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
4750{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
252b5132 4751
702f0fb4
PB		 4752{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4753{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4754
4755{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4756{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4757
252b5132
RH		 4758{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4759{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4760
4761{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4762{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4763
702f0fb4
PB		 4764{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4765{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4766
252b5132
RH		 4767{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4768{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4769
702f0fb4
PB		 4770{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4771{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4772
252b5132
RH		 4773};
4774
4775const int powerpc_num_opcodes =
4776 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4777\f
4778/* The macro table. This is only used by the assembler. */
4779
4780/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4781 when x=0; 32-x when x is between 1 and 31; are negative if x is
4782 negative; and are 32 or more otherwise. This is what you want
4783 when, for instance, you are emulating a right shift by a
4784 rotate-left-and-mask, because the underlying instructions support
4785 shifts of size 0 but not shifts of size 32. By comparison, when
4786 extracting x bits from some word you want to use just 32-x, because
4787 the underlying instructions don't support extracting 0 bits but do
4788 support extracting the whole word (32 bits in this case). */
4789
4790const struct powerpc_macro powerpc_macros[] = {
4791{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4792{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4793{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4794{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4795{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4796{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4797{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4798{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4799{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4800{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4801{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4802{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4803{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4804{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4805{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4806{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4807
4808{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4809{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
29ef7e54
AM		 4810{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4811{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
252b5132
RH		 4812{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4813{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4814{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4815{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4816{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4817{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4818{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4819{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4820{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4821{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4822{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4823{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4824{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4825{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4826{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4827{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4828{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4829{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
252b5132
RH		 4830};
4831
4832const int powerpc_num_macros =
4833 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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