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* sparc-opc.c: The fcmp v9a instructions take an integer register
[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
CommitLineData
85dcf36d
ILT		 1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21#include <stdio.h>
22#include "ansidecl.h"
23#include "opcode/ppc.h"
24
25/* This file holds the PowerPC opcode table. The opcode table
26 includes almost all of the extended instruction mnemonics. This
27 permits the disassembler to use them, and simplifies the assembler
28 logic, at the cost of increasing the table size. The table is
29 strictly constant data, so the compiler should be able to put it in
30 the .text section.
31
32 This file also holds the operand table. All knowledge about
33 inserting operands into instructions and vice-versa is kept in this
34 file. */
35\f
36/* Local insertion and extraction functions. */
37
38static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
39static long extract_bat PARAMS ((unsigned long, int *));
40static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
41static long extract_bba PARAMS ((unsigned long, int *));
42static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
43static long extract_bd PARAMS ((unsigned long, int *));
44static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
45static long extract_bdm PARAMS ((unsigned long, int *));
46static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
47static long extract_bdp PARAMS ((unsigned long, int *));
48static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
49static long extract_bo PARAMS ((unsigned long, int *));
50static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
51static long extract_boe PARAMS ((unsigned long, int *));
52static unsigned long insert_cr PARAMS ((unsigned long, long, const char **));
53static long extract_cr PARAMS ((unsigned long, int *));
54static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
55static long extract_ds PARAMS ((unsigned long, int *));
56static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
57static long extract_li PARAMS ((unsigned long, int *));
1c214e4c
ILT		 58static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
59static long extract_mbe PARAMS ((unsigned long, int *));
85dcf36d
ILT		 60static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
61static long extract_mb6 PARAMS ((unsigned long, int *));
1c214e4c
ILT		 62static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
63static long extract_nb PARAMS ((unsigned long, int *));
85dcf36d
ILT		 64static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
65static long extract_nsi PARAMS ((unsigned long, int *));
669124ef
ILT		 66static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
67static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
68static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
85dcf36d
ILT		 69static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
70static long extract_rbs PARAMS ((unsigned long, int *));
71static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
72static long extract_sh6 PARAMS ((unsigned long, int *));
73static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
74static long extract_spr PARAMS ((unsigned long, int *));
669124ef
ILT		 75static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
76static long extract_tbr PARAMS ((unsigned long, int *));
85dcf36d
ILT		 77\f
78/* The operands table.
79
80 The fields are bits, shift, signed, insert, extract, flags. */
81
82const struct powerpc_operand powerpc_operands[] =
83{
84 /* The zero index is used to indicate the end of the list of
85 operands. */
86#define UNUSED (0)
749a663d 87 { 0, 0, 0, 0, 0 },
85dcf36d
ILT		 88
89 /* The BA field in an XL form instruction. */
90#define BA (UNUSED + 1)
91#define BA_MASK (0x1f << 16)
749a663d 92 { 5, 16, 0, 0, PPC_OPERAND_CR },
85dcf36d
ILT		 93
94 /* The BA field in an XL form instruction when it must be the same
95 as the BT field in the same instruction. */
96#define BAT (BA + 1)
749a663d 97 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
85dcf36d
ILT		 98
99 /* The BB field in an XL form instruction. */
100#define BB (BAT + 1)
101#define BB_MASK (0x1f << 11)
749a663d 102 { 5, 11, 0, 0, PPC_OPERAND_CR },
85dcf36d
ILT		 103
104 /* The BB field in an XL form instruction when it must be the same
105 as the BA field in the same instruction. */
106#define BBA (BB + 1)
749a663d 107 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
85dcf36d
ILT		 108
109 /* The BD field in a B form instruction. The lower two bits are
110 forced to zero. */
111#define BD (BBA + 1)
749a663d 112 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 113
114 /* The BD field in a B form instruction when absolute addressing is
115 used. */
116#define BDA (BD + 1)
749a663d 117 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 118
119 /* The BD field in a B form instruction when the - modifier is used.
120 This sets the y bit of the BO field appropriately. */
121#define BDM (BDA + 1)
749a663d
ILT		 122 { 16, 0, insert_bdm, extract_bdm,
123 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 124
125 /* The BD field in a B form instruction when the - modifier is used
126 and absolute address is used. */
127#define BDMA (BDM + 1)
749a663d
ILT		 128 { 16, 0, insert_bdm, extract_bdm,
129 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 130
131 /* The BD field in a B form instruction when the + modifier is used.
132 This sets the y bit of the BO field appropriately. */
133#define BDP (BDMA + 1)
749a663d
ILT		 134 { 16, 0, insert_bdp, extract_bdp,
135 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 136
137 /* The BD field in a B form instruction when the + modifier is used
138 and absolute addressing is used. */
139#define BDPA (BDP + 1)
749a663d
ILT		 140 { 16, 0, insert_bdp, extract_bdp,
141 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 142
143 /* The BF field in an X or XL form instruction. */
144#define BF (BDPA + 1)
749a663d 145 { 3, 23, 0, 0, PPC_OPERAND_CR },
85dcf36d
ILT		 146
147 /* An optional BF field. This is used for comparison instructions,
148 in which an omitted BF field is taken as zero. */
149#define OBF (BF + 1)
749a663d 150 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
85dcf36d
ILT		 151
152 /* The BFA field in an X or XL form instruction. */
153#define BFA (OBF + 1)
749a663d 154 { 3, 18, 0, 0, PPC_OPERAND_CR },
85dcf36d
ILT		 155
156 /* The BI field in a B form or XL form instruction. */
157#define BI (BFA + 1)
158#define BI_MASK (0x1f << 16)
749a663d 159 { 5, 16, 0, 0, PPC_OPERAND_CR },
85dcf36d
ILT		 160
161 /* The BO field in a B form instruction. Certain values are
162 illegal. */
163#define BO (BI + 1)
164#define BO_MASK (0x1f << 21)
749a663d 165 { 5, 21, insert_bo, extract_bo, 0 },
85dcf36d
ILT		 166
167 /* The BO field in a B form instruction when the + or - modifier is
168 used. This is like the BO field, but it must be even. */
169#define BOE (BO + 1)
749a663d 170 { 5, 21, insert_boe, extract_boe, 0 },
85dcf36d
ILT		 171
172 /* The BT field in an X or XL form instruction. */
173#define BT (BOE + 1)
749a663d 174 { 5, 21, 0, 0, PPC_OPERAND_CR },
85dcf36d
ILT		 175
176 /* The condition register number portion of the BI field in a B form
177 or XL form instruction. This is used for the extended
178 conditional branch mnemonics, which set the lower two bits of the
179 BI field. This field is optional. */
180#define CR (BT + 1)
749a663d 181 { 5, 16, insert_cr, extract_cr, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
85dcf36d
ILT		 182
183 /* The D field in a D form instruction. This is a displacement off
184 a register, and implies that the next operand is a register in
185 parentheses. */
186#define D (CR + 1)
749a663d 187 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 188
189 /* The DS field in a DS form instruction. This is like D, but the
190 lower two bits are forced to zero. */
191#define DS (D + 1)
749a663d 192 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 193
194 /* The FL1 field in a POWER SC form instruction. */
195#define FL1 (DS + 1)
749a663d 196 { 4, 12, 0, 0, 0 },
85dcf36d
ILT		 197
198 /* The FL2 field in a POWER SC form instruction. */
199#define FL2 (FL1 + 1)
749a663d 200 { 3, 2, 0, 0, 0 },
85dcf36d
ILT		 201
202 /* The FLM field in an XFL form instruction. */
203#define FLM (FL2 + 1)
749a663d 204 { 8, 17, 0, 0, 0 },
85dcf36d
ILT		 205
206 /* The FRA field in an X or A form instruction. */
207#define FRA (FLM + 1)
208#define FRA_MASK (0x1f << 16)
749a663d 209 { 5, 16, 0, 0, PPC_OPERAND_FPR },
85dcf36d
ILT		 210
211 /* The FRB field in an X or A form instruction. */
212#define FRB (FRA + 1)
213#define FRB_MASK (0x1f << 11)
749a663d 214 { 5, 11, 0, 0, PPC_OPERAND_FPR },
85dcf36d
ILT		 215
216 /* The FRC field in an A form instruction. */
217#define FRC (FRB + 1)
218#define FRC_MASK (0x1f << 6)
749a663d 219 { 5, 6, 0, 0, PPC_OPERAND_FPR },
85dcf36d
ILT		 220
221 /* The FRS field in an X form instruction or the FRT field in a D, X
222 or A form instruction. */
223#define FRS (FRC + 1)
224#define FRT (FRS)
749a663d 225 { 5, 21, 0, 0, PPC_OPERAND_FPR },
85dcf36d
ILT		 226
227 /* The FXM field in an XFX instruction. */
228#define FXM (FRS + 1)
669124ef 229#define FXM_MASK (0xff << 12)
749a663d 230 { 8, 12, 0, 0, 0 },
85dcf36d
ILT		 231
232 /* The L field in a D or X form instruction. */
233#define L (FXM + 1)
749a663d 234 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
85dcf36d
ILT		 235
236 /* The LEV field in a POWER SC form instruction. */
237#define LEV (L + 1)
749a663d 238 { 7, 5, 0, 0, 0 },
85dcf36d
ILT		 239
240 /* The LI field in an I form instruction. The lower two bits are
241 forced to zero. */
242#define LI (LEV + 1)
749a663d 243 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 244
245 /* The LI field in an I form instruction when used as an absolute
246 address. */
247#define LIA (LI + 1)
749a663d 248 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 249
250 /* The MB field in an M form instruction. */
251#define MB (LIA + 1)
252#define MB_MASK (0x1f << 6)
749a663d 253 { 5, 6, 0, 0, 0 },
85dcf36d
ILT		 254
255 /* The ME field in an M form instruction. */
256#define ME (MB + 1)
257#define ME_MASK (0x1f << 1)
749a663d 258 { 5, 1, 0, 0, 0 },
85dcf36d 259
1c214e4c
ILT		 260 /* The MB and ME fields in an M form instruction expressed a single
261 operand which is a bitmask indicating which bits to select. This
262 is a two operand form using PPC_OPERAND_NEXT. See the
263 description in opcode/ppc.h for what this means. */
264#define MBE (ME + 1)
749a663d
ILT		 265 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
266 { 32, 0, insert_mbe, extract_mbe, 0 },
1c214e4c 267
85dcf36d
ILT		 268 /* The MB or ME field in an MD or MDS form instruction. The high
269 bit is wrapped to the low end. */
1c214e4c 270#define MB6 (MBE + 2)
85dcf36d
ILT		 271#define ME6 (MB6)
272#define MB6_MASK (0x3f << 5)
749a663d 273 { 6, 5, insert_mb6, extract_mb6, 0 },
85dcf36d 274
1c214e4c
ILT		 275 /* The NB field in an X form instruction. The value 32 is stored as
276 0. */
85dcf36d 277#define NB (MB6 + 1)
749a663d 278 { 6, 11, insert_nb, extract_nb, 0 },
85dcf36d
ILT		 279
280 /* The NSI field in a D form instruction. This is the same as the
281 SI field, only negated. */
282#define NSI (NB + 1)
749a663d
ILT		 283 { 16, 0, insert_nsi, extract_nsi,
284 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
85dcf36d
ILT		 285
286 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
287#define RA (NSI + 1)
288#define RA_MASK (0x1f << 16)
749a663d 289 { 5, 16, 0, 0, PPC_OPERAND_GPR },
85dcf36d 290
669124ef
ILT		 291 /* The RA field in a D or X form instruction which is an updating
292 load, which means that the RA field may not be zero and may not
293 equal the RT field. */
294#define RAL (RA + 1)
295 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
296
297 /* The RA field in an lmw instruction, which has special value
298 restrictions. */
299#define RAM (RAL + 1)
300 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
301
302 /* The RA field in a D or X form instruction which is an updating
303 store or an updating floating point load, which means that the RA
304 field may not be zero. */
305#define RAS (RAM + 1)
306 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
307
85dcf36d 308 /* The RB field in an X, XO, M, or MDS form instruction. */
669124ef 309#define RB (RAS + 1)
85dcf36d 310#define RB_MASK (0x1f << 11)
749a663d 311 { 5, 11, 0, 0, PPC_OPERAND_GPR },
85dcf36d
ILT		 312
313 /* The RB field in an X form instruction when it must be the same as
314 the RS field in the instruction. This is used for extended
315 mnemonics like mr. */
316#define RBS (RB + 1)
749a663d 317 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
85dcf36d
ILT		 318
319 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
320 instruction or the RT field in a D, DS, X, XFX or XO form
321 instruction. */
322#define RS (RBS + 1)
323#define RT (RS)
324#define RT_MASK (0x1f << 21)
749a663d 325 { 5, 21, 0, 0, PPC_OPERAND_GPR },
85dcf36d 326
1c214e4c
ILT		 327 /* The SH field in an X or M form instruction. */
328#define SH (RS + 1)
329#define SH_MASK (0x1f << 11)
749a663d 330 { 5, 11, 0, 0, 0 },
1c214e4c 331
85dcf36d 332 /* The SH field in an MD form instruction. This is split. */
1c214e4c 333#define SH6 (SH + 1)
85dcf36d 334#define SH6_MASK ((0x1f << 11) | (1 << 1))
749a663d 335 { 6, 1, insert_sh6, extract_sh6, 0 },
85dcf36d
ILT		 336
337 /* The SI field in a D form instruction. */
338#define SI (SH6 + 1)
749a663d
ILT		 339 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
340
341 /* The SI field in a D form instruction when we accept a wide range
342 of positive values. */
343#define SISIGNOPT (SI + 1)
344 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
85dcf36d 345
669124ef
ILT		 346 /* The SPR field in an XFX form instruction. This is flipped--the
347 lower 5 bits are stored in the upper 5 and vice- versa. */
749a663d 348#define SPR (SISIGNOPT + 1)
85dcf36d 349#define SPR_MASK (0x3ff << 11)
749a663d 350 { 10, 11, insert_spr, extract_spr, 0 },
85dcf36d 351
669124ef
ILT		 352 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
353#define SPRBAT (SPR + 1)
354#define SPRBAT_MASK (0x3 << 17)
355 { 2, 17, 0, 0, 0 },
356
357 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
358#define SPRG (SPRBAT + 1)
359#define SPRG_MASK (0x3 << 16)
360 { 2, 16, 0, 0, 0 },
361
85dcf36d 362 /* The SR field in an X form instruction. */
669124ef 363#define SR (SPRG + 1)
749a663d 364 { 4, 16, 0, 0, 0 },
85dcf36d
ILT		 365
366 /* The SV field in a POWER SC form instruction. */
367#define SV (SR + 1)
749a663d 368 { 14, 2, 0, 0, 0 },
85dcf36d 369
669124ef
ILT		 370 /* The TBR field in an XFX form instruction. This is like the SPR
371 field, but it is optional. */
372#define TBR (SV + 1)
373 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
374
85dcf36d 375 /* The TO field in a D or X form instruction. */
669124ef 376#define TO (TBR + 1)
85dcf36d 377#define TO_MASK (0x1f << 21)
749a663d 378 { 5, 21, 0, 0, 0 },
85dcf36d
ILT		 379
380 /* The U field in an X form instruction. */
381#define U (TO + 1)
749a663d 382 { 4, 12, 0, 0, 0 },
85dcf36d
ILT		 383
384 /* The UI field in a D form instruction. */
385#define UI (U + 1)
749a663d 386 { 16, 0, 0, 0, 0 },
85dcf36d
ILT		 387};
388
389/* The functions used to insert and extract complicated operands. */
390
391/* The BA field in an XL form instruction when it must be the same as
392 the BT field in the same instruction. This operand is marked FAKE.
393 The insertion function just copies the BT field into the BA field,
394 and the extraction function just checks that the fields are the
395 same. */
396
397/*ARGSUSED*/
398static unsigned long
399insert_bat (insn, value, errmsg)
400 unsigned long insn;
401 long value;
402 const char **errmsg;
403{
404 return insn | (((insn >> 21) & 0x1f) << 16);
405}
406
407static long
408extract_bat (insn, invalid)
409 unsigned long insn;
410 int *invalid;
411{
412 if (invalid != (int *) NULL
413 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
414 *invalid = 1;
415 return 0;
416}
417
418/* The BB field in an XL form instruction when it must be the same as
419 the BA field in the same instruction. This operand is marked FAKE.
420 The insertion function just copies the BA field into the BB field,
421 and the extraction function just checks that the fields are the
422 same. */
423
424/*ARGSUSED*/
425static unsigned long
426insert_bba (insn, value, errmsg)
427 unsigned long insn;
428 long value;
429 const char **errmsg;
430{
431 return insn | (((insn >> 16) & 0x1f) << 11);
432}
433
434static long
435extract_bba (insn, invalid)
436 unsigned long insn;
437 int *invalid;
438{
439 if (invalid != (int *) NULL
440 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
441 *invalid = 1;
442 return 0;
443}
444
445/* The BD field in a B form instruction. The lower two bits are
446 forced to zero. */
447
448/*ARGSUSED*/
449static unsigned long
450insert_bd (insn, value, errmsg)
451 unsigned long insn;
452 long value;
453 const char **errmsg;
454{
455 return insn | (value & 0xfffc);
456}
457
458/*ARGSUSED*/
459static long
460extract_bd (insn, invalid)
461 unsigned long insn;
462 int *invalid;
463{
464 if ((insn & 0x8000) != 0)
465 return (insn & 0xfffc) - 0x10000;
466 else
467 return insn & 0xfffc;
468}
469
470/* The BD field in a B form instruction when the - modifier is used.
471 This modifier means that the branch is not expected to be taken.
472 We must set the y bit of the BO field to 1 if the offset is
473 negative. When extracting, we require that the y bit be 1 and that
474 the offset be positive, since if the y bit is 0 we just want to
475 print the normal form of the instruction. */
476
477/*ARGSUSED*/
478static unsigned long
479insert_bdm (insn, value, errmsg)
480 unsigned long insn;
481 long value;
482 const char **errmsg;
483{
484 if ((value & 0x8000) != 0)
485 insn |= 1 << 21;
486 return insn | (value & 0xfffc);
487}
488
489static long
490extract_bdm (insn, invalid)
491 unsigned long insn;
492 int *invalid;
493{
494 if (invalid != (int *) NULL
495 && ((insn & (1 << 21)) == 0
496 || (insn & (1 << 15) == 0)))
497 *invalid = 1;
498 if ((insn & 0x8000) != 0)
499 return (insn & 0xfffc) - 0x10000;
500 else
501 return insn & 0xfffc;
502}
503
504/* The BD field in a B form instruction when the + modifier is used.
505 This is like BDM, above, except that the branch is expected to be
506 taken. */
507
508/*ARGSUSED*/
509static unsigned long
510insert_bdp (insn, value, errmsg)
511 unsigned long insn;
512 long value;
513 const char **errmsg;
514{
515 if ((value & 0x8000) == 0)
516 insn |= 1 << 21;
517 return insn | (value & 0xfffc);
518}
519
520static long
521extract_bdp (insn, invalid)
522 unsigned long insn;
523 int *invalid;
524{
525 if (invalid != (int *) NULL
526 && ((insn & (1 << 21)) == 0
527 || (insn & (1 << 15)) != 0))
528 *invalid = 1;
529 if ((insn & 0x8000) != 0)
530 return (insn & 0xfffc) - 0x10000;
531 else
532 return insn & 0xfffc;
533}
534
535/* Check for legal values of a BO field. */
536
537static int
538valid_bo (value)
539 long value;
540{
541 /* Certain encodings have bits that are required to be zero. These
542 are (z must be zero, y may be anything):
543 001zy
544 011zy
545 1z00y
546 1z01y
547 1z1zz
548 */
549 switch (value & 0x14)
550 {
551 default:
552 case 0:
553 return 1;
554 case 0x4:
555 return (value & 0x2) == 0;
556 case 0x10:
557 return (value & 0x8) == 0;
558 case 0x14:
559 return value == 0x14;
560 }
561}
562
563/* The BO field in a B form instruction. Warn about attempts to set
564 the field to an illegal value. */
565
566static unsigned long
567insert_bo (insn, value, errmsg)
568 unsigned long insn;
569 long value;
570 const char **errmsg;
571{
572 if (errmsg != (const char **) NULL
573 && ! valid_bo (value))
574 *errmsg = "invalid conditional option";
575 return insn | ((value & 0x1f) << 21);
576}
577
578static long
579extract_bo (insn, invalid)
580 unsigned long insn;
581 int *invalid;
582{
583 long value;
584
585 value = (insn >> 21) & 0x1f;
586 if (invalid != (int *) NULL
587 && ! valid_bo (value))
588 *invalid = 1;
589 return value;
590}
591
592/* The BO field in a B form instruction when the + or - modifier is
593 used. This is like the BO field, but it must be even. When
594 extracting it, we force it to be even. */
595
596static unsigned long
597insert_boe (insn, value, errmsg)
598 unsigned long insn;
599 long value;
600 const char **errmsg;
601{
602 if (errmsg != (const char **) NULL)
603 {
604 if (! valid_bo (value))
605 *errmsg = "invalid conditional option";
606 else if ((value & 1) != 0)
607 *errmsg = "attempt to set y bit when using + or - modifier";
608 }
609 return insn | ((value & 0x1f) << 21);
610}
611
612static long
613extract_boe (insn, invalid)
614 unsigned long insn;
615 int *invalid;
616{
617 long value;
618
619 value = (insn >> 21) & 0x1f;
620 if (invalid != (int *) NULL
621 && ! valid_bo (value))
622 *invalid = 1;
623 return value & 0x1e;
624}
625
626/* The condition register number portion of the BI field in a B form
627 or XL form instruction. This is used for the extended conditional
628 branch mnemonics, which set the lower two bits of the BI field. It
629 is the BI field with the lower two bits ignored. */
630
631/*ARGSUSED*/
632static unsigned long
633insert_cr (insn, value, errmsg)
634 unsigned long insn;
635 long value;
636 const char **errmsg;
637{
638 return insn | ((value & 0x1c) << 16);
639}
640
641/*ARGSUSED*/
642static long
643extract_cr (insn, invalid)
644 unsigned long insn;
645 int *invalid;
646{
647 return (insn >> 16) & 0x1c;
648}
649
650/* The DS field in a DS form instruction. This is like D, but the
651 lower two bits are forced to zero. */
652
653/*ARGSUSED*/
654static unsigned long
655insert_ds (insn, value, errmsg)
656 unsigned long insn;
657 long value;
658 const char **errmsg;
659{
660 return insn | (value & 0xfffc);
661}
662
663/*ARGSUSED*/
664static long
665extract_ds (insn, invalid)
666 unsigned long insn;
667 int *invalid;
668{
669 if ((insn & 0x8000) != 0)
670 return (insn & 0xfffc) - 0x10000;
671 else
672 return insn & 0xfffc;
673}
674
675/* The LI field in an I form instruction. The lower two bits are
676 forced to zero. */
677
678/*ARGSUSED*/
679static unsigned long
680insert_li (insn, value, errmsg)
681 unsigned long insn;
682 long value;
683 const char **errmsg;
684{
685 return insn | (value & 0x3fffffc);
686}
687
688/*ARGSUSED*/
689static long
690extract_li (insn, invalid)
691 unsigned long insn;
692 int *invalid;
693{
694 if ((insn & 0x2000000) != 0)
695 return (insn & 0x3fffffc) - 0x4000000;
696 else
697 return insn & 0x3fffffc;
698}
699
1c214e4c
ILT		 700/* The MB and ME fields in an M form instruction expressed as a single
701 operand which is itself a bitmask. The extraction function always
702 marks it as invalid, since we never want to recognize an
703 instruction which uses a field of this type. */
704
705static unsigned long
706insert_mbe (insn, value, errmsg)
707 unsigned long insn;
708 long value;
709 const char **errmsg;
710{
711 unsigned long uval;
712 int mb, me;
713
714 uval = value;
715
716 if (uval == 0)
717 {
718 if (errmsg != (const char **) NULL)
719 *errmsg = "illegal bitmask";
720 return insn;
721 }
722
723 me = 31;
724 while ((uval & 1) == 0)
725 {
726 uval >>= 1;
727 --me;
728 }
729
730 mb = me;
731 uval >>= 1;
732 while ((uval & 1) != 0)
733 {
734 uval >>= 1;
735 --mb;
736 }
737
738 if (uval != 0)
739 {
740 if (errmsg != (const char **) NULL)
741 *errmsg = "illegal bitmask";
742 }
743
744 return insn | (mb << 6) | (me << 1);
745}
746
747static long
748extract_mbe (insn, invalid)
749 unsigned long insn;
750 int *invalid;
751{
752 long ret;
753 int mb, me;
754 int i;
755
756 if (invalid != (int *) NULL)
757 *invalid = 1;
758
759 ret = 0;
760 mb = (insn >> 6) & 0x1f;
761 me = (insn >> 1) & 0x1f;
762 for (i = mb; i < me; i++)
763 ret |= 1 << (31 - i);
764 return ret;
765}
766
85dcf36d
ILT		 767/* The MB or ME field in an MD or MDS form instruction. The high bit
768 is wrapped to the low end. */
769
770/*ARGSUSED*/
771static unsigned long
772insert_mb6 (insn, value, errmsg)
773 unsigned long insn;
774 long value;
775 const char **errmsg;
776{
777 return insn | ((value & 0x1f) << 6) | (value & 0x20);
778}
779
780/*ARGSUSED*/
781static long
782extract_mb6 (insn, invalid)
783 unsigned long insn;
784 int *invalid;
785{
786 return ((insn >> 6) & 0x1f) | (insn & 0x20);
787}
788
1c214e4c
ILT		 789/* The NB field in an X form instruction. The value 32 is stored as
790 0. */
791
792static unsigned long
793insert_nb (insn, value, errmsg)
794 unsigned long insn;
795 long value;
796 const char **errmsg;
797{
798 if (value < 0 || value > 32)
799 *errmsg = "value out of range";
800 if (value == 32)
801 value = 0;
802 return insn | ((value & 0x1f) << 11);
803}
804
805/*ARGSUSED*/
806static long
807extract_nb (insn, invalid)
808 unsigned long insn;
809 int *invalid;
810{
811 long ret;
812
813 ret = (insn >> 11) & 0x1f;
814 if (ret == 0)
815 ret = 32;
816 return ret;
817}
818
85dcf36d 819/* The NSI field in a D form instruction. This is the same as the SI
1c214e4c 820 field, only negated. The extraction function always marks it as
85dcf36d
ILT		 821 invalid, since we never want to recognize an instruction which uses
822 a field of this type. */
823
824/*ARGSUSED*/
825static unsigned long
826insert_nsi (insn, value, errmsg)
827 unsigned long insn;
828 long value;
829 const char **errmsg;
830{
831 return insn | ((- value) & 0xffff);
832}
833
834static long
835extract_nsi (insn, invalid)
836 unsigned long insn;
837 int *invalid;
838{
839 if (invalid != (int *) NULL)
840 *invalid = 1;
841 if ((insn & 0x8000) != 0)
842 return - ((insn & 0xffff) - 0x10000);
843 else
844 return - (insn & 0xffff);
845}
846
669124ef
ILT		 847/* The RA field in a D or X form instruction which is an updating
848 load, which means that the RA field may not be zero and may not
849 equal the RT field. */
850
851static unsigned long
852insert_ral (insn, value, errmsg)
853 unsigned long insn;
854 long value;
855 const char **errmsg;
856{
857 if (value == 0
858 || value == ((insn >> 21) & 0x1f))
859 *errmsg = "invalid register operand when updating";
860 return insn | ((value & 0x1f) << 16);
861}
862
863/* The RA field in an lmw instruction, which has special value
864 restrictions. */
865
866static unsigned long
867insert_ram (insn, value, errmsg)
868 unsigned long insn;
869 long value;
870 const char **errmsg;
871{
872 if (value >= ((insn >> 21) & 0x1f))
873 *errmsg = "index register in load range";
874 return insn | ((value & 0x1f) << 16);
875}
876
877/* The RA field in a D or X form instruction which is an updating
878 store or an updating floating point load, which means that the RA
879 field may not be zero. */
880
881static unsigned long
882insert_ras (insn, value, errmsg)
883 unsigned long insn;
884 long value;
885 const char **errmsg;
886{
887 if (value == 0)
888 *errmsg = "invalid register operand when updating";
889 return insn | ((value & 0x1f) << 16);
890}
891
85dcf36d
ILT		 892/* The RB field in an X form instruction when it must be the same as
893 the RS field in the instruction. This is used for extended
894 mnemonics like mr. This operand is marked FAKE. The insertion
895 function just copies the BT field into the BA field, and the
896 extraction function just checks that the fields are the same. */
897
898/*ARGSUSED*/
899static unsigned long
900insert_rbs (insn, value, errmsg)
901 unsigned long insn;
902 long value;
903 const char **errmsg;
904{
905 return insn | (((insn >> 21) & 0x1f) << 11);
906}
907
908static long
909extract_rbs (insn, invalid)
910 unsigned long insn;
911 int *invalid;
912{
913 if (invalid != (int *) NULL
914 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
915 *invalid = 1;
916 return 0;
917}
918
919/* The SH field in an MD form instruction. This is split. */
920
921/*ARGSUSED*/
922static unsigned long
923insert_sh6 (insn, value, errmsg)
924 unsigned long insn;
925 long value;
926 const char **errmsg;
927{
928 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
929}
930
931/*ARGSUSED*/
932static long
933extract_sh6 (insn, invalid)
934 unsigned long insn;
935 int *invalid;
936{
937 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
938}
939
669124ef
ILT		 940/* The SPR field in an XFX form instruction. This is flipped--the
941 lower 5 bits are stored in the upper 5 and vice- versa. */
85dcf36d
ILT		 942
943static unsigned long
944insert_spr (insn, value, errmsg)
945 unsigned long insn;
946 long value;
947 const char **errmsg;
948{
949 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
950}
951
952static long
953extract_spr (insn, invalid)
954 unsigned long insn;
955 int *invalid;
956{
957 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
958}
669124ef
ILT		 959
960/* The TBR field in an XFX instruction. This is just like SPR, but it
961 is optional. When TBR is omitted, it must be inserted as 268 (the
962 magic number of the TB register). These functions treat 0
963 (indicating an omitted optional operand) as 268. This means that
964 ``mftb 4,0'' is not handled correctly. This does not matter very
965 much, since the architecture manual does not define mftb as
966 accepting any values other than 268 or 269. */
967
968#define TB (268)
969
970static unsigned long
971insert_tbr (insn, value, errmsg)
972 unsigned long insn;
973 long value;
974 const char **errmsg;
975{
976 if (value == 0)
977 value = TB;
978 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
979}
980
981static long
982extract_tbr (insn, invalid)
983 unsigned long insn;
984 int *invalid;
985{
986 long ret;
987
988 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
989 if (ret == TB)
990 ret = 0;
991 return ret;
992}
85dcf36d
ILT		 993\f
994/* Macros used to form opcodes. */
995
996/* The main opcode. */
997#define OP(x) (((x) & 0x3f) << 26)
998#define OP_MASK OP (0x3f)
999
1000/* The main opcode combined with a trap code in the TO field of a D
1001 form instruction. Used for extended mnemonics for the trap
1002 instructions. */
1003#define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
1004#define OPTO_MASK (OP_MASK | TO_MASK)
1005
1006/* The main opcode combined with a comparison size bit in the L field
1007 of a D form or X form instruction. Used for extended mnemonics for
1008 the comparison instructions. */
1009#define OPL(x,l) (OP (x) | (((l) & 1) << 21))
1010#define OPL_MASK OPL (0x3f,1)
1011
1012/* An A form instruction. */
1013#define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
1014#define A_MASK A (0x3f, 0x1f, 1)
1015
1016/* An A_MASK with the FRB field fixed. */
1017#define AFRB_MASK (A_MASK | FRB_MASK)
1018
1019/* An A_MASK with the FRC field fixed. */
1020#define AFRC_MASK (A_MASK | FRC_MASK)
1021
1022/* An A_MASK with the FRA and FRC fields fixed. */
1023#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1024
1025/* A B form instruction. */
1026#define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
1027#define B_MASK B (0x3f, 1, 1)
1028
1029/* A B form instruction setting the BO field. */
1030#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
1031#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1032
1033/* A BBO_MASK with the y bit of the BO field removed. This permits
1034 matching a conditional branch regardless of the setting of the y
1035 bit. */
1036#define Y_MASK (1 << 21)
1037#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1038
1039/* A B form instruction setting the BO field and the condition bits of
1040 the BI field. */
1041#define BBOCB(op, bo, cb, aa, lk) \
1042 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
1043#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1044
1045/* A BBOCB_MASK with the y bit of the BO field removed. */
1046#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1047
1048/* A BBOYCB_MASK in which the BI field is fixed. */
1049#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1050
1051/* The main opcode mask with the RA field clear. */
1052#define DRA_MASK (OP_MASK | RA_MASK)
1053
1054/* A DS form instruction. */
1055#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1056#define DS_MASK DSO (0x3f, 3)
1057
1058/* An M form instruction. */
1059#define M(op, rc) (OP (op) | ((rc) & 1))
1060#define M_MASK M (0x3f, 1)
1061
1062/* An M form instruction with the ME field specified. */
1063#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
1064
1065/* An M_MASK with the MB and ME fields fixed. */
1066#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1067
1068/* An M_MASK with the SH and ME fields fixed. */
1069#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1070
1071/* An MD form instruction. */
1072#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
1073#define MD_MASK MD (0x3f, 0x7, 1)
1074
1075/* An MD_MASK with the MB field fixed. */
1076#define MDMB_MASK (MD_MASK | MB6_MASK)
1077
1078/* An MD_MASK with the SH field fixed. */
1079#define MDSH_MASK (MD_MASK | SH6_MASK)
1080
1081/* An MDS form instruction. */
1082#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
1083#define MDS_MASK MDS (0x3f, 0xf, 1)
1084
1085/* An MDS_MASK with the MB field fixed. */
1086#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1087
1088/* An SC form instruction. */
1089#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
1c214e4c 1090#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
85dcf36d
ILT		 1091
1092/* An X form instruction. */
1093#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1094
1095/* An X form instruction with the RC bit specified. */
1096#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1097
1098/* The mask for an X form instruction. */
1099#define X_MASK XRC (0x3f, 0x3ff, 1)
1100
1101/* An X_MASK with the RA field fixed. */
1102#define XRA_MASK (X_MASK | RA_MASK)
1103
1104/* An X_MASK with the RB field fixed. */
1105#define XRB_MASK (X_MASK | RB_MASK)
1106
1107/* An X_MASK with the RT field fixed. */
1108#define XRT_MASK (X_MASK | RT_MASK)
1109
1110/* An X_MASK with the RA and RB fields fixed. */
1111#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1112
1113/* An X_MASK with the RT and RA fields fixed. */
1114#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1115
1116/* An X form comparison instruction. */
1117#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
1118
1119/* The mask for an X form comparison instruction. */
1120#define XCMP_MASK (X_MASK | (1 << 22))
1121
1122/* The mask for an X form comparison instruction with the L field
1123 fixed. */
1124#define XCMPL_MASK (XCMP_MASK | (1 << 21))
1125
1126/* An X form trap instruction with the TO field specified. */
1127#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1128#define XTO_MASK (X_MASK | TO_MASK)
1129
1130/* An XFL form instruction. */
1131#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1132#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1133
1134/* An XL form instruction with the LK field set to 0. */
1135#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1136
1137/* An XL form instruction which uses the LK field. */
1138#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1139
1140/* The mask for an XL form instruction. */
1141#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1142
1143/* An XL form instruction which explicitly sets the BO field. */
1144#define XLO(op, bo, xop, lk) \
1145 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1146#define XLO_MASK (XL_MASK | BO_MASK)
1147
1148/* An XL form instruction which explicitly sets the y bit of the BO
1149 field. */
1150#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1151#define XLYLK_MASK (XL_MASK | Y_MASK)
1152
1153/* An XL form instruction which sets the BO field and the condition
1154 bits of the BI field. */
1155#define XLOCB(op, bo, cb, xop, lk) \
1156 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1157#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1158
1159/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1160#define XLBB_MASK (XL_MASK | BB_MASK)
1161#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1162#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1163
1164/* An XL_MASK with the BO and BB fields fixed. */
1165#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1166
1167/* An XL_MASK with the BO, BI and BB fields fixed. */
1168#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1169
1170/* An XO form instruction. */
1171#define XO(op, xop, oe, rc) \
1172 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1173#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1174
1175/* An XO_MASK with the RB field fixed. */
1176#define XORB_MASK (XO_MASK | RB_MASK)
1177
1178/* An XS form instruction. */
1179#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1180#define XS_MASK XS (0x3f, 0x1ff, 1)
1181
669124ef
ILT		 1182/* A mask for the FXM version of an XFX form instruction. */
1183#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1184
1185/* An XFX form instruction with the FXM field filled in. */
1186#define XFXM(op, xop, fxm) \
1187 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1188
85dcf36d
ILT		 1189/* An XFX form instruction with the SPR field filled in. */
1190#define XSPR(op, xop, spr) \
1191 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1192#define XSPR_MASK (X_MASK | SPR_MASK)
1193
669124ef
ILT		 1194/* An XFX form instruction with the SPR field filled in except for the
1195 SPRBAT field. */
1196#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1197
1198/* An XFX form instruction with the SPR field filled in except for the
1199 SPRG field. */
1200#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1201
85dcf36d
ILT		 1202/* The BO encodings used in extended conditional branch mnemonics. */
1203#define BODNZF (0x0)
1204#define BODNZFP (0x1)
1205#define BODZF (0x2)
1206#define BODZFP (0x3)
1207#define BOF (0x4)
1208#define BOFP (0x5)
1209#define BODNZT (0x8)
1210#define BODNZTP (0x9)
1211#define BODZT (0xa)
1212#define BODZTP (0xb)
1213#define BOT (0xc)
1214#define BOTP (0xd)
1215#define BODNZ (0x10)
1216#define BODNZP (0x11)
1217#define BODZ (0x12)
1218#define BODZP (0x13)
1219#define BOU (0x14)
1220
1221/* The BI condition bit encodings used in extended conditional branch
1222 mnemonics. */
1223#define CBLT (0)
1224#define CBGT (1)
1225#define CBEQ (2)
1226#define CBSO (3)
1227
1228/* The TO encodings used in extended trap mnemonics. */
1229#define TOLGT (0x1)
1230#define TOLLT (0x2)
1231#define TOEQ (0x4)
1232#define TOLGE (0x5)
1233#define TOLNL (0x5)
1234#define TOLLE (0x6)
1235#define TOLNG (0x6)
1236#define TOGT (0x8)
1237#define TOGE (0xc)
1238#define TONL (0xc)
1239#define TOLT (0x10)
1240#define TOLE (0x14)
1241#define TONG (0x14)
1242#define TONE (0x18)
1243#define TOU (0x1f)
1244\f
1245/* Smaller names for the flags so each entry in the opcodes table will
1246 fit on a single line. */
1247#define PPC PPC_OPCODE_PPC
1248#define POWER PPC_OPCODE_POWER
54192495 1249#define POWER2 PPC_OPCODE_POWER2
85dcf36d
ILT		 1250#define B32 PPC_OPCODE_32
1251#define B64 PPC_OPCODE_64
54192495 1252#define M601 PPC_OPCODE_601
85dcf36d
ILT		 1253\f
1254/* The opcode table.
1255
1256 The format of the opcode table is:
1257
1258 NAME OPCODE MASK FLAGS { OPERANDS }
1259
1260 NAME is the name of the instruction.
1261 OPCODE is the instruction opcode.
1262 MASK is the opcode mask; this is used to tell the disassembler
1263 which bits in the actual opcode must match OPCODE.
1264 FLAGS are flags indicated what processors support the instruction.
1265 OPERANDS is the list of operands.
1266
1267 The disassembler reads the table in order and prints the first
1268 instruction which matches, so this table is sorted to put more
1269 specific instructions before more general instructions. It is also
1270 sorted by major opcode. */
1271
1272const struct powerpc_opcode powerpc_opcodes[] = {
1273{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1274{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1275{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1276{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1277{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1278{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1279{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1280{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1281{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1282{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1283{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1284{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1285{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1286{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1287{ "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1288
1289{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1290{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1291{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1292{ "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1293{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1294{ "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1295{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1296{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1297{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1298{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1299{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1300{ "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1301{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1302{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1303{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1304{ "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1305{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1306{ "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1307{ "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1308{ "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1309{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1310{ "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1311{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1312{ "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1313{ "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1314{ "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1315{ "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1316{ "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1317{ "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1318{ "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1319
1320{ "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1321{ "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1322
1323{ "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1324{ "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1325
54192495 1326{ "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
85dcf36d
ILT		 1327
1328{ "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1329{ "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1330{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1331{ "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1332
1333{ "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1334{ "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1335{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1336{ "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1337
1338{ "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1339{ "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1340{ "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1341
1342{ "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1343{ "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1344{ "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1345
1346{ "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1347{ "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1348{ "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1c214e4c 1349{ "cal", OP(14), OP_MASK, POWER, { RT, D, RA } },
85dcf36d
ILT		 1350{ "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1351{ "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1352
749a663d
ILT		 1353{ "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
1354{ "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
1355{ "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
1356{ "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
85dcf36d
ILT		 1357{ "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1358
1359{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1360{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
54192495
ILT		 1361{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
1362{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
85dcf36d
ILT		 1363{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1364{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
54192495
ILT		 1365{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
1366{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
85dcf36d
ILT		 1367{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1368{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
54192495
ILT		 1369{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
1370{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
85dcf36d
ILT		 1371{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1372{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
54192495
ILT		 1373{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
1374{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
85dcf36d
ILT		 1375{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1376{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1377{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1378{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1379{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1380{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1381{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1382{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1383{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1384{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1385{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1386{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1387{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1388{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1389{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1390{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1391{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1392{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1393{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1394{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1395{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1396{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1397{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1398{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1399{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1400{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1401{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1402{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1403{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1404{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1405{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1406{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1407{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1408{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1409{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1410{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1411{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1412{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1413{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1414{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1415{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1416{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1417{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1418{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1419{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1420{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1421{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1422{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1423{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1424{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1425{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1426{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1427{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1428{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1429{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1430{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1431{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1432{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1433{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1434{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1435{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1436{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1437{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1438{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1439{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1440{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1441{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1442{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1443{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1444{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1445{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1446{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1447{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1448{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1449{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1450{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1451{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1452{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1453{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1454{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1455{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1456{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1457{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1458{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1459{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1460{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1461{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1462{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1463{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1464{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1465{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1466{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1467{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1468{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1469{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1470{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1471{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1472{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1473{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1474{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1475{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1476{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1477{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1478{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1479{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1480{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1481{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1482{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1483{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1484{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1485{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1486{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1487{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1488{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1489{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1490{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1491{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1492{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1493{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1494{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1495{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1496{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1497{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1498{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1499{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1500{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1501{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1502{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1503{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1504{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1505{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1506{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1507{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1508{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1509{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1510{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1511{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1512{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1513{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1514{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1515{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1516{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1517{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1518{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1519{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1520{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1521{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1522{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1523{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1524{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1525{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1526{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1527{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1528{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1529{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1530{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1531{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1532{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1533{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1534{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1535{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1536{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1537{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1538{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1539{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1540{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1541{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1542{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1543{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1544{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1545{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1546{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1547{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1548{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1549{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1550{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1551{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1552{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1553{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1554{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1555{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1556{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1557{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1558{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1559{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1560{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1561{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1562{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1563{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1564{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1565{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1566{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1567{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1568{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1569{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1570{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1571{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1572{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1573{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1574{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1575{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1576{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1577{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1578{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1579{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1580{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1581{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1582{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1583{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1584{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1585{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1586{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1587{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1588{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1589{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1590{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1591{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1592{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1593{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1594{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1595{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1596{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1597{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1598{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1599{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1600{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1601{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1602{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1603{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1604{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1605{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1606{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1607{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1608{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1609{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1610{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1611{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1612{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1613{ "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1614{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1615{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1616{ "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1617{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1618{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1619{ "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1620{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1621{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1622{ "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1623
1624{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1625{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1626{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1627{ "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1628{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1629
1630{ "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1631{ "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1632{ "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1633{ "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1634
1635{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1636
1637{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1638{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1639{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1640{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1641{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1642{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1643{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1644{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1645{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1646{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1647{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1648{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1649{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1650{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1651{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1652{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1653{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1654{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1655{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1656{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1657{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1658{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1659{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1660{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1661{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1662{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1663{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1664{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1665{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1666{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1667{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1668{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1669{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1670{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1671{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1672{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1673{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1674{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1675{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1676{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1677{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1678{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1679{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1680{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1681{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1682{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1683{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1684{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1685{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1686{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1687{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1688{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1689{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1690{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1691{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1692{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1693{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1694{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1695{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1696{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1697{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1698{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1699{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1700{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1701{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1702{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1703{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1704{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1705{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1706{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1707{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1708{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1709{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1710{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1711{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1712{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1713{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1714{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1715{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1716{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1717{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1718{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1719{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1720{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1721{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1722{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1723{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1724{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1725{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1726{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1727{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1728{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1729{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1730{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1731{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1732{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1733{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1734{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1735{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1736{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1737{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1738{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1739{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1740{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1741{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1742{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1743{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1744{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1745{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1746{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1747{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1748{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1749{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1750{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1751{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1752{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1753{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1754{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1755{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1756{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1757{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1758{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1759{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1760{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1761{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1762{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1763{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1764{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1765{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1766{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1767{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1768{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1769{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1770{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1771{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1772{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1773{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1774{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1775{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1776{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1777{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1778{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1779{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1780{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1781{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1782{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1783{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1784{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1785{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
1786{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
1787{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1788{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1789{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1790{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1791{ "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
1792{ "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
1793
1794{ "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
1795{ "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
1796
1797{ "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
1798
1799{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
1800
1801{ "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
1802
1803{ "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
1804{ "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
1805
1806{ "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
1807{ "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
1808
1809{ "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
1810
1811{ "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
1812
1813{ "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
1814{ "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
1815
1816{ "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
1817
1818{ "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
1819{ "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
1820
1c214e4c
ILT		 1821{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1822{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
85dcf36d
ILT		 1823{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1824{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1825{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1826{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1827{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1828{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1829{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1830{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1831{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1832{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1833{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1834{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1835{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1836{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1837{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1838{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1839{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1840{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1841{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1842{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1843{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1844{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1845{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1846{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1847{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1848{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1849{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1850{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1851{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1852{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1853{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1854{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1855{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1856{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1857{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1858{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1859{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1860{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1861{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1862{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1863{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1864{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1865{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1866{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1867{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1868{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1869{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1870{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1871{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1872{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1873{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1874{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1875{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1876{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1877{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1878{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1879{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1880{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1881{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1882{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1883{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1884{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1885{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1886{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1887{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1888{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1889{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1890{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1891{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1892{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1893{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1894{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1895{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1896{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1897{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
1898{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1899{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1900{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
1901{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1902{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1903{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
1904{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1905{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1906{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
1907{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
1908{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1909{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1910{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
1911{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1912{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1913{ "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
1914{ "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
1915
1c214e4c
ILT		 1916{ "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1917{ "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
85dcf36d 1918
1c214e4c
ILT		 1919{ "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1920{ "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
85dcf36d
ILT		 1921
1922{ "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
1923{ "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
1c214e4c
ILT		 1924{ "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1925{ "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
85dcf36d
ILT		 1926{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
1927{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
1c214e4c
ILT		 1928{ "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1929{ "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
85dcf36d 1930
54192495
ILT		 1931{ "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1932{ "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
85dcf36d
ILT		 1933
1934{ "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
1c214e4c
ILT		 1935{ "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1936{ "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
85dcf36d 1937{ "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
1c214e4c
ILT		 1938{ "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1939{ "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
85dcf36d
ILT		 1940
1941{ "nop", OP(24), 0xffffffff, PPC, { 0 } },
1942{ "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
1943{ "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
1944
1945{ "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
1946{ "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
1947
1948{ "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
1949{ "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
1950
1951{ "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
1952{ "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
1953
1954{ "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
1955{ "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
1956
1957{ "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
1958{ "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
1959
1960{ "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1961{ "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1962{ "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1963{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1964{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1965{ "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1966
1967{ "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1968{ "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1969
1970{ "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1971{ "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1972
1973{ "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1974{ "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1975
1976{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1977{ "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1978{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1979{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1980
1981{ "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1982{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1983
1984{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1985{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
85dcf36d 1986{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
669124ef 1987{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
85dcf36d
ILT		 1988
1989{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
1990{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
1991{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
1992{ "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
1993{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
1994{ "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
1995{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
1996{ "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
1997{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
1998{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
1999{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
2000{ "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
2001{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
2002{ "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
2003{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
2004{ "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
2005{ "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
2006{ "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
2007{ "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
2008{ "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
2009{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
2010{ "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
2011{ "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
2012{ "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
2013{ "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
2014{ "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
2015{ "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
2016{ "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
2017{ "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
2018{ "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
2019{ "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
2020
2021{ "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
2022{ "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
2023{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2024{ "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
2025{ "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
2026{ "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
2027{ "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
2028{ "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
2029{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2030{ "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
2031{ "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
2032{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2033
2034{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2035{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2036
2037{ "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
2038{ "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
2039{ "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
2040{ "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
2041{ "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
2042{ "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
2043{ "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
2044{ "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
2045
2046{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2047{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2048
2049{ "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
2050
2051{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2052
2053{ "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
2054
2055{ "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
2056{ "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
2057
2058{ "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
2059{ "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
2060{ "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
2061{ "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
2062
2063{ "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
2064{ "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
2065{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
2066{ "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
2067
2068{ "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
2069{ "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
2070
2071{ "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2072{ "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2073
54192495
ILT		 2074{ "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
2075{ "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d
ILT		 2076
2077{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
2078{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
85dcf36d 2079{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
669124ef 2080{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
85dcf36d
ILT		 2081
2082{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2083{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2084{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2085{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2086{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2087{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2088{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2089{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2090
669124ef 2091{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
85dcf36d
ILT		 2092
2093{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2094
669124ef 2095{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
85dcf36d
ILT		 2096{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
2097
2098{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
2099{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
2100
2101{ "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2102{ "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2103
2104{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
2105{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
2106{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
2107{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
2108{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
2109{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
2110{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
2111{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
2112{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
2113{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
2114{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
2115{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
2116{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
2117{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
2118{ "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2119
2120{ "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2121{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2122
2123{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2124{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2125
2126{ "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
2127
2128{ "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2129
2130{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2131
2132{ "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2133
2134{ "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
2135{ "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
2136{ "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
2137{ "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
2138
54192495
ILT		 2139{ "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2140{ "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2141{ "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2142{ "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
85dcf36d
ILT		 2143
2144{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2145
669124ef 2146{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
85dcf36d
ILT		 2147
2148{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2149{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2150{ "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2151{ "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2152
2153{ "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
2154{ "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
2155{ "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
2156{ "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
2157{ "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
2158{ "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
2159{ "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
2160{ "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
2161
2162{ "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
2163{ "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
2164{ "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } },
2165{ "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } },
2166{ "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } },
2167{ "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } },
2168{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
2169{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
2170
669124ef
ILT		 2171{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
2172{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
85dcf36d
ILT		 2173
2174{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
2175
2176{ "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
2177
2178{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2179
2180{ "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
2181{ "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
2182
54192495
ILT		 2183{ "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
2184{ "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2185
54192495
ILT		 2186{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
2187{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2188
669124ef 2189{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
85dcf36d 2190
669124ef 2191{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
85dcf36d
ILT		 2192{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
2193
54192495
ILT		 2194{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
2195{ "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
85dcf36d
ILT		 2196
2197{ "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
2198{ "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
2199{ "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } },
2200{ "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } },
2201{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } },
2202{ "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } },
2203{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } },
2204{ "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } },
2205
2206{ "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } },
2207{ "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } },
2208{ "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } },
2209{ "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } },
2210{ "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } },
2211{ "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } },
2212{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } },
2213{ "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } },
2214
2215{ "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
2216
2217{ "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
2218
2219{ "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
2220
54192495
ILT		 2221{ "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
2222{ "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2223
54192495
ILT		 2224{ "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
2225{ "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d
ILT		 2226
2227{ "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
2228{ "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
2229{ "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } },
2230{ "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } },
2231{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } },
2232{ "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } },
2233{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } },
2234{ "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } },
2235
2236{ "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2237{ "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2238{ "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2239{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2240
2241{ "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } },
2242{ "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } },
2243{ "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } },
2244{ "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } },
2245{ "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } },
2246{ "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } },
2247{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } },
2248{ "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } },
2249
2250{ "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } },
2251{ "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } },
2252{ "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } },
2253{ "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } },
2254{ "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } },
2255{ "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } },
2256{ "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } },
2257{ "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } },
2258
2259{ "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } },
2260{ "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } },
2261
2262{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2263
669124ef 2264{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
85dcf36d 2265
54192495
ILT		 2266{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
2267{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
85dcf36d 2268
54192495
ILT		 2269{ "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2270{ "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2271{ "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2272{ "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
85dcf36d
ILT		 2273
2274{ "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
2275{ "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
2276{ "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } },
2277{ "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } },
2278{ "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } },
2279{ "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } },
2280{ "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
2281{ "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
2282
54192495
ILT		 2283{ "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
2284{ "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
85dcf36d
ILT		 2285
2286{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2287
2288{ "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2289
2290{ "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2291{ "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2292
2293{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2294{ "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } },
2295
2296{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2297
669124ef 2298{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
85dcf36d
ILT		 2299
2300{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2301{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2302
54192495
ILT		 2303{ "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2304{ "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2305{ "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2306{ "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
85dcf36d 2307
54192495 2308{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
85dcf36d 2309{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
669124ef
ILT		 2310{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
2311{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
2312{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
85dcf36d
ILT		 2313{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
2314{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
669124ef
ILT		 2315{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2316{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
2317{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
2318{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
2319{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2320{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
2321{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
2322{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
2323{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2324{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
2325{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2326{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2327{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2328{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2329{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2330{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
85dcf36d
ILT		 2331{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2332
2333{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2334
2335{ "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2336
54192495
ILT		 2337{ "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2338{ "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2339{ "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2340{ "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } },
85dcf36d 2341
54192495
ILT		 2342{ "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2343{ "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2344{ "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2345{ "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
85dcf36d
ILT		 2346
2347{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2348
669124ef 2349{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
85dcf36d
ILT		 2350{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2351
669124ef 2352{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
85dcf36d 2353
669124ef 2354{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
85dcf36d
ILT		 2355
2356{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2357
54192495
ILT		 2358{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2359
2360{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2361
2362{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2363
2364{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2365
85dcf36d
ILT		 2366{ "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2367{ "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2368
2369{ "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2370{ "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2371
2372{ "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } },
2373
2374{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2375
669124ef 2376{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
85dcf36d
ILT		 2377
2378{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2379{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2380{ "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2381{ "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2382
2383{ "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2384{ "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2385{ "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2386{ "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2387
2388{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2389{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2390{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2391{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2392
54192495 2393{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } },
85dcf36d
ILT		 2394{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
2395{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
2396{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
669124ef
ILT		 2397{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2398{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
2399{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
2400{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
2401{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
2402{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
2403{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2404{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
2405{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
2406{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
2407{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2408{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
2409{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2410{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2411{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2412{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2413{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2414{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2415{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
85dcf36d
ILT		 2416{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2417
2418{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2419
2420{ "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2421{ "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2422
54192495
ILT		 2423{ "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2424{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2425{ "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2426{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } },
85dcf36d
ILT		 2427
2428{ "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2429{ "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2430{ "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2431{ "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2432
2433{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2434{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2435{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2436{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2437
2438{ "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } },
2439
2440{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2441
2442{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
2443
54192495 2444{ "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } },
85dcf36d
ILT		 2445
2446{ "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2447{ "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2448
2449{ "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2450{ "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2451
2452{ "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2453
2454{ "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2455{ "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2456{ "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2457{ "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2458
54192495
ILT		 2459{ "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
2460{ "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d
ILT		 2461
2462{ "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2463{ "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2464
54192495
ILT		 2465{ "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
2466{ "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d
ILT		 2467
2468{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2469
669124ef 2470{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
85dcf36d
ILT		 2471
2472{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2473
2474{ "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2475{ "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2476
2477{ "sync", X(31,598), 0xffffffff, PPC, { 0 } },
2478{ "dcs", X(31,598), 0xffffffff, POWER, { 0 } },
2479
2480{ "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2481
2482{ "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2483
2484{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
2485
669124ef 2486{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
85dcf36d
ILT		 2487
2488{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
2489
2490{ "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2491{ "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2492
2493{ "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2494{ "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2495
2496{ "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2497
54192495
ILT		 2498{ "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
2499{ "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2500
54192495
ILT		 2501{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
2502{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2503
669124ef 2504{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
85dcf36d 2505
54192495
ILT		 2506{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
2507{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
85dcf36d
ILT		 2508
2509{ "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2510{ "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2511
2512{ "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2513
54192495
ILT		 2514{ "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
2515{ "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2516
54192495
ILT		 2517{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
2518{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2519
669124ef 2520{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
85dcf36d 2521
54192495
ILT		 2522{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
2523{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
85dcf36d
ILT		 2524
2525{ "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2526
2527{ "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2528{ "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2529{ "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2530{ "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2531
2532{ "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2533{ "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2534
2535{ "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2536
2537{ "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2538{ "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2539{ "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2540{ "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2541
2542{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2543
2544{ "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2545
54192495
ILT		 2546{ "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
2547{ "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d 2548
54192495
ILT		 2549{ "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
2550{ "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
85dcf36d
ILT		 2551
2552{ "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
2553{ "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
2554{ "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
2555{ "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
2556
54192495
ILT		 2557{ "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
2558{ "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
85dcf36d
ILT		 2559
2560{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2561{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2562
2563{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2564
2565{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2566
2567{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2568{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2569
2570{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2571{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2572
2573{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
2574{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
2575
669124ef 2576{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
85dcf36d
ILT		 2577{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
2578
2579{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
2580
669124ef 2581{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
85dcf36d
ILT		 2582
2583{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
2584{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
2585
669124ef 2586{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
85dcf36d
ILT		 2587{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
2588
2589{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
2590
669124ef 2591{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
85dcf36d
ILT		 2592
2593{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
2594
669124ef 2595{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
85dcf36d
ILT		 2596
2597{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
2598
669124ef 2599{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
85dcf36d
ILT		 2600
2601{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
2602
669124ef 2603{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
85dcf36d 2604
669124ef 2605{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
85dcf36d
ILT		 2606{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
2607
2608{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
2609{ "stm", OP(47), OP_MASK, POWER, { RS, D, RA } },
2610
2611{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
2612
669124ef 2613{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
85dcf36d
ILT		 2614
2615{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
2616
669124ef 2617{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
85dcf36d
ILT		 2618
2619{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
2620
669124ef 2621{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
85dcf36d
ILT		 2622
2623{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
2624
669124ef 2625{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
85dcf36d 2626
54192495
ILT		 2627{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
2628
2629{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
2630
85dcf36d
ILT		 2631{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
2632
669124ef 2633{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
85dcf36d
ILT		 2634
2635{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
2636
2637{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2638{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2639
2640{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2641{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2642
2643{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2644{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2645
2646{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2647{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2648
2649{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2650{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2651
2652{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2653{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2654
2655{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2656{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2657
2658{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2659{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2660
2661{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2662{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2663
2664{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2665{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2666
54192495
ILT		 2667{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
2668
2669{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
2670
85dcf36d
ILT		 2671{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
2672
669124ef 2673{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
85dcf36d
ILT		 2674
2675{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2676
2677{ "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2678{ "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2679
2680{ "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
54192495 2681{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
85dcf36d 2682{ "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
8c546ded 2683{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
85dcf36d
ILT		 2684
2685{ "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
54192495 2686{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
85dcf36d 2687{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
54192495 2688{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
85dcf36d
ILT		 2689
2690{ "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2691{ "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2692{ "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2693{ "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2694
2695{ "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2696{ "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2697{ "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2698{ "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2699
2700{ "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2701{ "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2702{ "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2703{ "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2704
54192495
ILT		 2705{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2706{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
85dcf36d
ILT		 2707
2708{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2709{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2710
2711{ "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2712{ "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2713{ "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2714{ "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2715
2716{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2717{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2718
2719{ "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2720{ "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2721{ "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2722{ "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2723
2724{ "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2725{ "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2726{ "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2727{ "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2728
2729{ "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2730{ "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2731{ "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2732{ "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2733
2734{ "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2735{ "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2736{ "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2737{ "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2738
2739{ "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2740
2741{ "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } },
2742{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } },
2743
2744{ "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2745{ "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2746
2747{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2748
2749{ "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } },
2750{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } },
2751
2752{ "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2753{ "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2754
2755{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2756{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2757
2758{ "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2759{ "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2760
2761{ "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2762{ "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2763
2764{ "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } },
2765{ "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } },
2766
2767{ "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } },
2768{ "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } },
2769
2770{ "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2771{ "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2772
2773{ "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2774{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2775
2776{ "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2777{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2778
2779};
2780
2781const int powerpc_num_opcodes =
2782 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
1c214e4c
ILT		 2783\f
2784/* The macro table. This is only used by the assembler. */
2785
2786const struct powerpc_macro powerpc_macros[] = {
2787{ "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" },
2788{ "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" },
2789{ "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2790{ "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2791{ "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
2792{ "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2793{ "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" },
2794{ "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" },
2795{ "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" },
2796{ "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" },
2797{ "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" },
2798{ "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" },
2799{ "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" },
2800{ "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" },
2801{ "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" },
2802{ "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" },
2803
2804{ "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" },
2805{ "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" },
2806{ "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2807{ "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2808{ "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2809{ "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2810{ "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2811{ "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2812{ "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" },
2813{ "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" },
2814{ "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" },
2815{ "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" },
2816{ "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" },
2817{ "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" },
2818{ "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" },
2819{ "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" },
2820{ "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" },
2821{ "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" },
2822{ "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" },
2823{ "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" },
2824{ "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2825{ "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2826
2827};
2828
2829const int powerpc_num_macros =
2830 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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