Commit | Line | Data |
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252b5132 | 1 | /* ppc-opc.c -- PowerPC opcode list |
b3adc24a | 2 | Copyright (C) 1994-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
9b201bb5 | 5 | This file is part of the GNU opcodes library. |
252b5132 | 6 | |
9b201bb5 NC |
7 | This library is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
252b5132 | 11 | |
9b201bb5 NC |
12 | It is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
252b5132 | 16 | |
112290ab | 17 | You should have received a copy of the GNU General Public License |
9b201bb5 NC |
18 | along with this file; see the file COPYING. If not, write to the |
19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 | 21 | |
0d8dfecf | 22 | #include "sysdep.h" |
df7b86aa | 23 | #include <stdio.h> |
252b5132 RH |
24 | #include "opcode/ppc.h" |
25 | #include "opintl.h" | |
26 | ||
27 | /* This file holds the PowerPC opcode table. The opcode table | |
28 | includes almost all of the extended instruction mnemonics. This | |
29 | permits the disassembler to use them, and simplifies the assembler | |
30 | logic, at the cost of increasing the table size. The table is | |
31 | strictly constant data, so the compiler should be able to put it in | |
b80c7270 | 32 | the text segment. |
252b5132 RH |
33 | |
34 | This file also holds the operand table. All knowledge about | |
35 | inserting operands into instructions and vice-versa is kept in this | |
36 | file. */ | |
252b5132 | 37 | |
b80c7270 | 38 | /* The functions used to insert and extract complicated operands. */ |
252b5132 | 39 | |
b80c7270 | 40 | /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ |
252b5132 | 41 | |
0f873fd5 PB |
42 | static uint64_t |
43 | insert_arx (uint64_t insn, | |
44 | int64_t value, | |
b80c7270 AM |
45 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
46 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 47 | { |
71553718 AM |
48 | value -= 8; |
49 | if (value < 0 || value >= 16) | |
b80c7270 AM |
50 | { |
51 | *errmsg = _("invalid register"); | |
71553718 | 52 | value = 0xf; |
b80c7270 | 53 | } |
71553718 | 54 | return insn | value; |
b80c7270 | 55 | } |
b9c361e0 | 56 | |
0f873fd5 PB |
57 | static int64_t |
58 | extract_arx (uint64_t insn, | |
b80c7270 AM |
59 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
60 | int *invalid ATTRIBUTE_UNUSED) | |
61 | { | |
62 | return (insn & 0xf) + 8; | |
63 | } | |
b9c361e0 | 64 | |
0f873fd5 PB |
65 | static uint64_t |
66 | insert_ary (uint64_t insn, | |
67 | int64_t value, | |
b80c7270 AM |
68 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
69 | const char **errmsg ATTRIBUTE_UNUSED) | |
70 | { | |
71553718 AM |
71 | value -= 8; |
72 | if (value < 0 || value >= 16) | |
b80c7270 AM |
73 | { |
74 | *errmsg = _("invalid register"); | |
71553718 | 75 | value = 0xf; |
b80c7270 | 76 | } |
71553718 | 77 | return insn | (value << 4); |
b80c7270 | 78 | } |
23976049 | 79 | |
0f873fd5 PB |
80 | static int64_t |
81 | extract_ary (uint64_t insn, | |
b80c7270 AM |
82 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
83 | int *invalid ATTRIBUTE_UNUSED) | |
84 | { | |
85 | return ((insn >> 4) & 0xf) + 8; | |
86 | } | |
418c1742 | 87 | |
0f873fd5 PB |
88 | static uint64_t |
89 | insert_rx (uint64_t insn, | |
90 | int64_t value, | |
b80c7270 AM |
91 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
92 | const char **errmsg) | |
93 | { | |
94 | if (value >= 0 && value < 8) | |
71553718 | 95 | ; |
b80c7270 | 96 | else if (value >= 24 && value <= 31) |
71553718 | 97 | value -= 16; |
b80c7270 AM |
98 | else |
99 | { | |
100 | *errmsg = _("invalid register"); | |
71553718 | 101 | value = 0xf; |
b80c7270 | 102 | } |
71553718 | 103 | return insn | value; |
b80c7270 | 104 | } |
252b5132 | 105 | |
0f873fd5 PB |
106 | static int64_t |
107 | extract_rx (uint64_t insn, | |
b80c7270 AM |
108 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
109 | int *invalid ATTRIBUTE_UNUSED) | |
110 | { | |
0f873fd5 | 111 | int64_t value = insn & 0xf; |
b80c7270 AM |
112 | if (value >= 0 && value < 8) |
113 | return value; | |
114 | else | |
115 | return value + 16; | |
116 | } | |
b9c361e0 | 117 | |
0f873fd5 PB |
118 | static uint64_t |
119 | insert_ry (uint64_t insn, | |
120 | int64_t value, | |
b80c7270 AM |
121 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
122 | const char **errmsg) | |
123 | { | |
124 | if (value >= 0 && value < 8) | |
71553718 | 125 | ; |
b80c7270 | 126 | else if (value >= 24 && value <= 31) |
71553718 | 127 | value -= 16; |
b80c7270 AM |
128 | else |
129 | { | |
130 | *errmsg = _("invalid register"); | |
71553718 | 131 | value = 0xf; |
b80c7270 | 132 | } |
71553718 | 133 | return insn | (value << 4); |
b80c7270 | 134 | } |
a680de9a | 135 | |
0f873fd5 PB |
136 | static int64_t |
137 | extract_ry (uint64_t insn, | |
b80c7270 AM |
138 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
139 | int *invalid ATTRIBUTE_UNUSED) | |
140 | { | |
0f873fd5 | 141 | int64_t value = (insn >> 4) & 0xf; |
b80c7270 AM |
142 | if (value >= 0 && value < 8) |
143 | return value; | |
144 | else | |
145 | return value + 16; | |
146 | } | |
a680de9a | 147 | |
98553ad3 PB |
148 | /* The BA and BB fields in an XL form instruction or the RA and RB fields or |
149 | VRA and VRB fields in a VX form instruction when they must be the same. | |
150 | This is used for extended mnemonics like crclr. The extraction function | |
151 | enforces that the fields are the same. */ | |
adadcc0c | 152 | |
0f873fd5 | 153 | static uint64_t |
98553ad3 PB |
154 | insert_bab (uint64_t insn, |
155 | int64_t value, | |
b80c7270 AM |
156 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
157 | const char **errmsg ATTRIBUTE_UNUSED) | |
158 | { | |
98553ad3 PB |
159 | value &= 0x1f; |
160 | return insn | (value << 16) | (value << 11); | |
b80c7270 | 161 | } |
252b5132 | 162 | |
0f873fd5 | 163 | static int64_t |
98553ad3 | 164 | extract_bab (uint64_t insn, |
b80c7270 AM |
165 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
166 | int *invalid) | |
167 | { | |
98553ad3 PB |
168 | int64_t ba = (insn >> 16) & 0x1f; |
169 | int64_t bb = (insn >> 11) & 0x1f; | |
170 | ||
171 | if (ba != bb) | |
b80c7270 | 172 | *invalid = 1; |
98553ad3 | 173 | return ba; |
b80c7270 | 174 | } |
19a6653c | 175 | |
98553ad3 PB |
176 | /* The BT, BA and BB fields in an XL form instruction when they must all be |
177 | the same. This is used for extended mnemonics like crclr. The extraction | |
178 | function enforces that the fields are the same. */ | |
a680de9a | 179 | |
0f873fd5 | 180 | static uint64_t |
98553ad3 PB |
181 | insert_btab (uint64_t insn, |
182 | int64_t value, | |
183 | ppc_cpu_t dialect, | |
184 | const char **errmsg) | |
b80c7270 | 185 | { |
98553ad3 PB |
186 | value &= 0x1f; |
187 | return (value << 21) | insert_bab (insn, value, dialect, errmsg); | |
b80c7270 | 188 | } |
a680de9a | 189 | |
0f873fd5 | 190 | static int64_t |
98553ad3 PB |
191 | extract_btab (uint64_t insn, |
192 | ppc_cpu_t dialect, | |
b80c7270 AM |
193 | int *invalid) |
194 | { | |
98553ad3 PB |
195 | int64_t bt = (insn >> 21) & 0x1f; |
196 | int64_t bab = extract_bab (insn, dialect, invalid); | |
197 | ||
198 | if (bt != bab) | |
b80c7270 | 199 | *invalid = 1; |
98553ad3 | 200 | return bt; |
b80c7270 | 201 | } |
252b5132 | 202 | |
b80c7270 AM |
203 | /* The BD field in a B form instruction when the - modifier is used. |
204 | This modifier means that the branch is not expected to be taken. | |
205 | For chips built to versions of the architecture prior to version 2 | |
206 | (ie. not Power4 compatible), we set the y bit of the BO field to 1 | |
207 | if the offset is negative. When extracting, we require that the y | |
208 | bit be 1 and that the offset be positive, since if the y bit is 0 | |
209 | we just want to print the normal form of the instruction. | |
210 | Power4 compatible targets use two bits, "a", and "t", instead of | |
211 | the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, | |
212 | "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 | |
213 | in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 | |
214 | for branch on CTR. We only handle the taken/not-taken hint here. | |
215 | Note that we don't relax the conditions tested here when | |
216 | disassembling with -Many because insns using extract_bdm and | |
217 | extract_bdp always occur in pairs. One or the other will always | |
218 | be valid. */ | |
252b5132 | 219 | |
b80c7270 | 220 | #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
252b5132 | 221 | |
0f873fd5 PB |
222 | static uint64_t |
223 | insert_bdm (uint64_t insn, | |
224 | int64_t value, | |
b80c7270 AM |
225 | ppc_cpu_t dialect, |
226 | const char **errmsg ATTRIBUTE_UNUSED) | |
227 | { | |
228 | if ((dialect & ISA_V2) == 0) | |
229 | { | |
230 | if ((value & 0x8000) != 0) | |
231 | insn |= 1 << 21; | |
232 | } | |
233 | else | |
234 | { | |
235 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
236 | insn |= 0x02 << 21; | |
237 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
238 | insn |= 0x08 << 21; | |
239 | } | |
240 | return insn | (value & 0xfffc); | |
241 | } | |
252b5132 | 242 | |
0f873fd5 PB |
243 | static int64_t |
244 | extract_bdm (uint64_t insn, | |
b80c7270 AM |
245 | ppc_cpu_t dialect, |
246 | int *invalid) | |
247 | { | |
248 | if ((dialect & ISA_V2) == 0) | |
249 | { | |
250 | if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) | |
251 | *invalid = 1; | |
252 | } | |
253 | else | |
254 | { | |
255 | if ((insn & (0x17 << 21)) != (0x06 << 21) | |
256 | && (insn & (0x1d << 21)) != (0x18 << 21)) | |
257 | *invalid = 1; | |
258 | } | |
252b5132 | 259 | |
b80c7270 AM |
260 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
261 | } | |
989993d8 | 262 | |
b80c7270 AM |
263 | /* The BD field in a B form instruction when the + modifier is used. |
264 | This is like BDM, above, except that the branch is expected to be | |
265 | taken. */ | |
252b5132 | 266 | |
0f873fd5 PB |
267 | static uint64_t |
268 | insert_bdp (uint64_t insn, | |
269 | int64_t value, | |
b80c7270 AM |
270 | ppc_cpu_t dialect, |
271 | const char **errmsg ATTRIBUTE_UNUSED) | |
272 | { | |
273 | if ((dialect & ISA_V2) == 0) | |
274 | { | |
275 | if ((value & 0x8000) == 0) | |
276 | insn |= 1 << 21; | |
277 | } | |
278 | else | |
279 | { | |
280 | if ((insn & (0x14 << 21)) == (0x04 << 21)) | |
281 | insn |= 0x03 << 21; | |
282 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) | |
283 | insn |= 0x09 << 21; | |
284 | } | |
285 | return insn | (value & 0xfffc); | |
286 | } | |
989993d8 | 287 | |
0f873fd5 PB |
288 | static int64_t |
289 | extract_bdp (uint64_t insn, | |
b80c7270 AM |
290 | ppc_cpu_t dialect, |
291 | int *invalid) | |
292 | { | |
293 | if ((dialect & ISA_V2) == 0) | |
294 | { | |
295 | if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) | |
296 | *invalid = 1; | |
297 | } | |
298 | else | |
299 | { | |
300 | if ((insn & (0x17 << 21)) != (0x07 << 21) | |
301 | && (insn & (0x1d << 21)) != (0x19 << 21)) | |
302 | *invalid = 1; | |
303 | } | |
252b5132 | 304 | |
b80c7270 AM |
305 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
306 | } | |
252b5132 | 307 | |
b80c7270 | 308 | static inline int |
0f873fd5 | 309 | valid_bo_pre_v2 (int64_t value) |
b80c7270 AM |
310 | { |
311 | /* Certain encodings have bits that are required to be zero. | |
312 | These are (z must be zero, y may be anything): | |
313 | 0000y | |
314 | 0001y | |
315 | 001zy | |
316 | 0100y | |
317 | 0101y | |
318 | 011zy | |
319 | 1z00y | |
320 | 1z01y | |
321 | 1z1zz | |
322 | */ | |
323 | if ((value & 0x14) == 0) | |
aae9718e | 324 | /* BO: 0000y, 0001y, 0100y, 0101y. */ |
b80c7270 AM |
325 | return 1; |
326 | else if ((value & 0x14) == 0x4) | |
aae9718e | 327 | /* BO: 001zy, 011zy. */ |
b80c7270 AM |
328 | return (value & 0x2) == 0; |
329 | else if ((value & 0x14) == 0x10) | |
aae9718e | 330 | /* BO: 1z00y, 1z01y. */ |
b80c7270 AM |
331 | return (value & 0x8) == 0; |
332 | else | |
aae9718e | 333 | /* BO: 1z1zz. */ |
b80c7270 AM |
334 | return value == 0x14; |
335 | } | |
989993d8 | 336 | |
b80c7270 | 337 | static inline int |
0f873fd5 | 338 | valid_bo_post_v2 (int64_t value) |
b80c7270 AM |
339 | { |
340 | /* Certain encodings have bits that are required to be zero. | |
341 | These are (z must be zero, a & t may be anything): | |
342 | 0000z | |
343 | 0001z | |
344 | 001at | |
345 | 0100z | |
346 | 0101z | |
347 | 011at | |
348 | 1a00t | |
349 | 1a01t | |
350 | 1z1zz | |
351 | */ | |
352 | if ((value & 0x14) == 0) | |
aae9718e | 353 | /* BO: 0000z, 0001z, 0100z, 0101z. */ |
b80c7270 AM |
354 | return (value & 0x1) == 0; |
355 | else if ((value & 0x14) == 0x14) | |
aae9718e | 356 | /* BO: 1z1zz. */ |
b80c7270 | 357 | return value == 0x14; |
aae9718e PB |
358 | else if ((value & 0x14) == 0x4) |
359 | /* BO: 001at, 011at, with "at" == 0b01 being reserved. */ | |
360 | return (value & 0x3) != 1; | |
361 | else if ((value & 0x14) == 0x10) | |
362 | /* BO: 1a00t, 1a01t, with "at" == 0b01 being reserved. */ | |
363 | return (value & 0x9) != 1; | |
b80c7270 AM |
364 | else |
365 | return 1; | |
366 | } | |
c168870a | 367 | |
b80c7270 | 368 | /* Check for legal values of a BO field. */ |
252b5132 | 369 | |
b80c7270 | 370 | static int |
0f873fd5 | 371 | valid_bo (int64_t value, ppc_cpu_t dialect, int extract) |
b80c7270 AM |
372 | { |
373 | int valid_y = valid_bo_pre_v2 (value); | |
374 | int valid_at = valid_bo_post_v2 (value); | |
b9c361e0 | 375 | |
b80c7270 AM |
376 | /* When disassembling with -Many, accept either encoding on the |
377 | second pass through opcodes. */ | |
378 | if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) | |
379 | return valid_y || valid_at; | |
380 | if ((dialect & ISA_V2) == 0) | |
381 | return valid_y; | |
382 | else | |
383 | return valid_at; | |
384 | } | |
a5721ba2 | 385 | |
b80c7270 AM |
386 | /* The BO field in a B form instruction. Warn about attempts to set |
387 | the field to an illegal value. */ | |
252b5132 | 388 | |
0f873fd5 PB |
389 | static uint64_t |
390 | insert_bo (uint64_t insn, | |
391 | int64_t value, | |
b80c7270 AM |
392 | ppc_cpu_t dialect, |
393 | const char **errmsg) | |
394 | { | |
395 | if (!valid_bo (value, dialect, 0)) | |
396 | *errmsg = _("invalid conditional option"); | |
aae9718e PB |
397 | else if (PPC_OP (insn) == 19 |
398 | && (((insn >> 1) & 0x3ff) == 528) && ! (value & 4)) | |
b80c7270 AM |
399 | *errmsg = _("invalid counter access"); |
400 | return insn | ((value & 0x1f) << 21); | |
401 | } | |
a680de9a | 402 | |
0f873fd5 PB |
403 | static int64_t |
404 | extract_bo (uint64_t insn, | |
b80c7270 AM |
405 | ppc_cpu_t dialect, |
406 | int *invalid) | |
407 | { | |
0f873fd5 | 408 | int64_t value = (insn >> 21) & 0x1f; |
b80c7270 AM |
409 | if (!valid_bo (value, dialect, 1)) |
410 | *invalid = 1; | |
411 | return value; | |
412 | } | |
252b5132 | 413 | |
aae9718e PB |
414 | /* For the given BO value, return a bit mask detailing which bits |
415 | define the branch hints. */ | |
416 | ||
417 | static int64_t | |
418 | get_bo_hint_mask (int64_t bo, ppc_cpu_t dialect) | |
419 | { | |
420 | if ((dialect & ISA_V2) == 0) | |
421 | { | |
422 | if ((bo & 0x14) != 0x14) | |
423 | /* BO: 0000y, 0001y, 001zy, 0100y, 0101y, 011zy, 1z00y, 1z01y . */ | |
424 | return 1; | |
425 | else | |
426 | /* BO: 1z1zz. */ | |
427 | return 0; | |
428 | } | |
429 | else | |
430 | { | |
431 | if ((bo & 0x14) == 0x4) | |
432 | /* BO: 001at, 011at. */ | |
433 | return 0x3; | |
434 | else if ((bo & 0x14) == 0x10) | |
435 | /* BO: 1a00t, 1a01t. */ | |
436 | return 0x9; | |
437 | else | |
438 | /* BO: 0000z, 0001z, 0100z, 0101z, 1z1zz. */ | |
439 | return 0; | |
440 | } | |
441 | } | |
442 | ||
443 | /* The BO field in a B form instruction when the + or - modifier is used. */ | |
1ed8e1e4 | 444 | |
0f873fd5 PB |
445 | static uint64_t |
446 | insert_boe (uint64_t insn, | |
447 | int64_t value, | |
b80c7270 | 448 | ppc_cpu_t dialect, |
aae9718e PB |
449 | const char **errmsg, |
450 | int branch_taken) | |
b80c7270 | 451 | { |
aae9718e PB |
452 | int64_t implied_hint; |
453 | int64_t hint_mask = get_bo_hint_mask (value, dialect); | |
252b5132 | 454 | |
aae9718e PB |
455 | if (branch_taken) |
456 | implied_hint = hint_mask; | |
457 | else | |
458 | implied_hint = hint_mask & ~1; | |
459 | ||
460 | /* The branch hint bit(s) in the BO field must either be zero or exactly | |
461 | match the branch hint bits implied by the '+' or '-' modifier. */ | |
462 | if (implied_hint == 0) | |
463 | *errmsg = _("BO value implies no branch hint, when using + or - modifier"); | |
464 | else if ((value & hint_mask) != 0 | |
465 | && (value & hint_mask) != implied_hint) | |
466 | { | |
467 | if ((dialect & ISA_V2) == 0) | |
468 | *errmsg = _("attempt to set y bit when using + or - modifier"); | |
469 | else | |
470 | *errmsg = _("attempt to set 'at' bits when using + or - modifier"); | |
471 | } | |
472 | ||
473 | value |= implied_hint; | |
474 | ||
475 | return insert_bo (insn, value, dialect, errmsg); | |
b80c7270 | 476 | } |
252b5132 | 477 | |
0f873fd5 PB |
478 | static int64_t |
479 | extract_boe (uint64_t insn, | |
b80c7270 | 480 | ppc_cpu_t dialect, |
aae9718e PB |
481 | int *invalid, |
482 | int branch_taken) | |
b80c7270 | 483 | { |
0f873fd5 | 484 | int64_t value = (insn >> 21) & 0x1f; |
aae9718e PB |
485 | int64_t implied_hint; |
486 | int64_t hint_mask = get_bo_hint_mask (value, dialect); | |
487 | ||
488 | if (branch_taken) | |
489 | implied_hint = hint_mask; | |
490 | else | |
491 | implied_hint = hint_mask & ~1; | |
492 | ||
493 | if (!valid_bo (value, dialect, 1) | |
494 | || implied_hint == 0 | |
495 | || (value & hint_mask) != implied_hint) | |
b80c7270 | 496 | *invalid = 1; |
aae9718e PB |
497 | return value; |
498 | } | |
499 | ||
500 | /* The BO field in a B form instruction when the - modifier is used. */ | |
501 | ||
502 | static uint64_t | |
503 | insert_bom (uint64_t insn, | |
504 | int64_t value, | |
505 | ppc_cpu_t dialect, | |
506 | const char **errmsg) | |
507 | { | |
508 | return insert_boe (insn, value, dialect, errmsg, 0); | |
509 | } | |
510 | ||
511 | static int64_t | |
512 | extract_bom (uint64_t insn, | |
513 | ppc_cpu_t dialect, | |
514 | int *invalid) | |
515 | { | |
516 | return extract_boe (insn, dialect, invalid, 0); | |
517 | } | |
518 | ||
519 | /* The BO field in a B form instruction when the + modifier is used. */ | |
520 | ||
521 | static uint64_t | |
522 | insert_bop (uint64_t insn, | |
523 | int64_t value, | |
524 | ppc_cpu_t dialect, | |
525 | const char **errmsg) | |
526 | { | |
527 | return insert_boe (insn, value, dialect, errmsg, 1); | |
528 | } | |
529 | ||
530 | static int64_t | |
531 | extract_bop (uint64_t insn, | |
532 | ppc_cpu_t dialect, | |
533 | int *invalid) | |
534 | { | |
535 | return extract_boe (insn, dialect, invalid, 1); | |
b80c7270 | 536 | } |
252b5132 | 537 | |
b80c7270 AM |
538 | /* The DCMX field in a X form instruction when the field is split |
539 | into separate DC, DM and DX fields. */ | |
252b5132 | 540 | |
0f873fd5 PB |
541 | static uint64_t |
542 | insert_dcmxs (uint64_t insn, | |
543 | int64_t value, | |
b80c7270 AM |
544 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
545 | const char **errmsg ATTRIBUTE_UNUSED) | |
546 | { | |
547 | return (insn | |
548 | | ((value & 0x1f) << 16) | |
549 | | ((value & 0x20) >> 3) | |
550 | | (value & 0x40)); | |
551 | } | |
252b5132 | 552 | |
0f873fd5 PB |
553 | static int64_t |
554 | extract_dcmxs (uint64_t insn, | |
b80c7270 AM |
555 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
556 | int *invalid ATTRIBUTE_UNUSED) | |
557 | { | |
558 | return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); | |
559 | } | |
252b5132 | 560 | |
b80c7270 AM |
561 | /* The D field in a DX form instruction when the field is split |
562 | into separate D0, D1 and D2 fields. */ | |
989993d8 | 563 | |
0f873fd5 PB |
564 | static uint64_t |
565 | insert_dxd (uint64_t insn, | |
566 | int64_t value, | |
b80c7270 AM |
567 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
568 | const char **errmsg ATTRIBUTE_UNUSED) | |
569 | { | |
570 | return insn | (value & 0xffc1) | ((value & 0x3e) << 15); | |
571 | } | |
e43de63c | 572 | |
0f873fd5 PB |
573 | static int64_t |
574 | extract_dxd (uint64_t insn, | |
b80c7270 AM |
575 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
576 | int *invalid ATTRIBUTE_UNUSED) | |
577 | { | |
0f873fd5 | 578 | uint64_t dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); |
b80c7270 AM |
579 | return (dxd ^ 0x8000) - 0x8000; |
580 | } | |
252b5132 | 581 | |
0f873fd5 PB |
582 | static uint64_t |
583 | insert_dxdn (uint64_t insn, | |
584 | int64_t value, | |
b80c7270 AM |
585 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
586 | const char **errmsg ATTRIBUTE_UNUSED) | |
587 | { | |
588 | return insert_dxd (insn, -value, dialect, errmsg); | |
589 | } | |
252b5132 | 590 | |
0f873fd5 PB |
591 | static int64_t |
592 | extract_dxdn (uint64_t insn, | |
b80c7270 | 593 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
9cf7e568 | 594 | int *invalid) |
b80c7270 AM |
595 | { |
596 | return -extract_dxd (insn, dialect, invalid); | |
597 | } | |
fdd12ef3 | 598 | |
8acf1435 PB |
599 | /* The D field in a 64-bit D form prefix instruction when the field is split |
600 | into separate D0 and D1 fields. */ | |
601 | ||
602 | static uint64_t | |
603 | insert_d34 (uint64_t insn, | |
604 | int64_t value, | |
605 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
606 | const char **errmsg ATTRIBUTE_UNUSED) | |
607 | { | |
608 | return insn | ((value & 0x3ffff0000ULL) << 16) | (value & 0xffff); | |
609 | } | |
610 | ||
611 | static int64_t | |
612 | extract_d34 (uint64_t insn, | |
613 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
614 | int *invalid ATTRIBUTE_UNUSED) | |
615 | { | |
616 | int64_t mask = 1ULL << 33; | |
617 | int64_t value = ((insn >> 16) & 0x3ffff0000ULL) | (insn & 0xffff); | |
618 | value = (value ^ mask) - mask; | |
619 | return value; | |
620 | } | |
621 | ||
622 | /* The NSI34 field in an 8-byte D form prefix instruction. This is the same | |
623 | as the SI34 field, only negated. The extraction function always marks it | |
624 | as invalid, since we never want to recognize an instruction which uses | |
625 | a field of this type. */ | |
626 | ||
627 | static uint64_t | |
628 | insert_nsi34 (uint64_t insn, | |
629 | int64_t value, | |
630 | ppc_cpu_t dialect, | |
631 | const char **errmsg) | |
632 | { | |
633 | return insert_d34 (insn, -value, dialect, errmsg); | |
634 | } | |
635 | ||
636 | static int64_t | |
637 | extract_nsi34 (uint64_t insn, | |
638 | ppc_cpu_t dialect, | |
639 | int *invalid) | |
640 | { | |
641 | int64_t value = extract_d34 (insn, dialect, invalid); | |
642 | *invalid = 1; | |
643 | return -value; | |
644 | } | |
645 | ||
6edbfd3b AM |
646 | /* The split IMM32 field in a vector splat insn. */ |
647 | ||
648 | static uint64_t | |
649 | insert_imm32 (uint64_t insn, | |
650 | int64_t value, | |
651 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
652 | const char **errmsg ATTRIBUTE_UNUSED) | |
653 | { | |
654 | return insn | ((value & 0xffff0000) << 16) | (value & 0xffff); | |
655 | } | |
656 | ||
657 | static int64_t | |
658 | extract_imm32 (uint64_t insn, | |
659 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
660 | int *invalid ATTRIBUTE_UNUSED) | |
661 | { | |
662 | return (insn & 0xffff) | ((insn >> 16) & 0xffff0000); | |
663 | } | |
664 | ||
8acf1435 PB |
665 | /* The R field in an 8-byte prefix instruction when there are restrictions |
666 | between R's value and the RA value (ie, they cannot both be non zero). */ | |
667 | ||
668 | static uint64_t | |
669 | insert_pcrel (uint64_t insn, | |
670 | int64_t value, | |
671 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
672 | const char **errmsg) | |
673 | { | |
674 | value &= 0x1; | |
675 | int64_t ra = (insn >> 16) & 0x1f; | |
676 | if (ra != 0 && value != 0) | |
677 | *errmsg = _("invalid R operand"); | |
678 | ||
679 | return insn | (value << 52); | |
680 | } | |
681 | ||
682 | static int64_t | |
683 | extract_pcrel (uint64_t insn, | |
684 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
685 | int *invalid) | |
686 | { | |
687 | /* If called with *invalid < 0 to return the value for missing | |
688 | operands, *invalid will be the negative count of missing operands | |
689 | including this one. Return a default value of 1 if the PRA0/PRAQ | |
690 | operand was also omitted (ie. *invalid is -2). Return a default | |
691 | value of 0 if the PRA0/PRAQ operand was not omitted | |
692 | (ie. *invalid is -1). */ | |
693 | if (*invalid < 0) | |
694 | return ~ *invalid & 1; | |
695 | ||
696 | int64_t ra = (insn >> 16) & 0x1f; | |
697 | int64_t pcrel = (insn >> 52) & 0x1; | |
698 | if (ra != 0 && pcrel != 0) | |
699 | *invalid = 1; | |
700 | ||
701 | return pcrel; | |
702 | } | |
703 | ||
704 | /* Variant of extract_pcrel that sets invalid for R bit set. The idea | |
705 | is to disassemble "paddi rt,0,offset,1" as "pla rt,offset". */ | |
706 | ||
707 | static int64_t | |
708 | extract_pcrel0 (uint64_t insn, | |
709 | ppc_cpu_t dialect, | |
710 | int *invalid) | |
711 | { | |
712 | int64_t pcrel = extract_pcrel (insn, dialect, invalid); | |
713 | if (pcrel) | |
714 | *invalid = 1; | |
715 | return pcrel; | |
716 | } | |
717 | ||
b80c7270 | 718 | /* FXM mask in mfcr and mtcrf instructions. */ |
adadcc0c | 719 | |
0f873fd5 PB |
720 | static uint64_t |
721 | insert_fxm (uint64_t insn, | |
722 | int64_t value, | |
b80c7270 AM |
723 | ppc_cpu_t dialect, |
724 | const char **errmsg) | |
725 | { | |
726 | /* If we're handling the mfocrf and mtocrf insns ensure that exactly | |
727 | one bit of the mask field is set. */ | |
728 | if ((insn & (1 << 20)) != 0) | |
729 | { | |
730 | if (value == 0 || (value & -value) != value) | |
731 | { | |
732 | *errmsg = _("invalid mask field"); | |
733 | value = 0; | |
734 | } | |
735 | } | |
252b5132 | 736 | |
b80c7270 AM |
737 | /* If only one bit of the FXM field is set, we can use the new form |
738 | of the instruction, which is faster. Unlike the Power4 branch hint | |
739 | encoding, this is not backward compatible. Do not generate the | |
740 | new form unless -mpower4 has been given, or -many and the two | |
741 | operand form of mfcr was used. */ | |
742 | else if (value > 0 | |
743 | && (value & -value) == value | |
744 | && ((dialect & PPC_OPCODE_POWER4) != 0 | |
745 | || ((dialect & PPC_OPCODE_ANY) != 0 | |
746 | && (insn & (0x3ff << 1)) == 19 << 1))) | |
747 | insn |= 1 << 20; | |
252b5132 | 748 | |
b80c7270 AM |
749 | /* Any other value on mfcr is an error. */ |
750 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
751 | { | |
752 | /* A value of -1 means we used the one operand form of | |
753 | mfcr which is valid. */ | |
754 | if (value != -1) | |
755 | *errmsg = _("invalid mfcr mask"); | |
756 | value = 0; | |
757 | } | |
252b5132 | 758 | |
b80c7270 AM |
759 | return insn | ((value & 0xff) << 12); |
760 | } | |
1f6c9eb0 | 761 | |
0f873fd5 PB |
762 | static int64_t |
763 | extract_fxm (uint64_t insn, | |
b80c7270 AM |
764 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
765 | int *invalid) | |
766 | { | |
9cf7e568 AM |
767 | /* Return a value of -1 for a missing optional operand, which is |
768 | used as a flag by insert_fxm. */ | |
769 | if (*invalid < 0) | |
770 | return -1; | |
252b5132 | 771 | |
9cf7e568 | 772 | int64_t mask = (insn >> 12) & 0xff; |
b80c7270 AM |
773 | /* Is this a Power4 insn? */ |
774 | if ((insn & (1 << 20)) != 0) | |
775 | { | |
776 | /* Exactly one bit of MASK should be set. */ | |
777 | if (mask == 0 || (mask & -mask) != mask) | |
778 | *invalid = 1; | |
779 | } | |
252b5132 | 780 | |
b80c7270 AM |
781 | /* Check that non-power4 form of mfcr has a zero MASK. */ |
782 | else if ((insn & (0x3ff << 1)) == 19 << 1) | |
783 | { | |
784 | if (mask != 0) | |
785 | *invalid = 1; | |
786 | else | |
787 | mask = -1; | |
788 | } | |
989993d8 | 789 | |
b80c7270 AM |
790 | return mask; |
791 | } | |
cee62821 | 792 | |
afef4fe9 PB |
793 | /* L field in the paste. instruction. */ |
794 | ||
795 | static uint64_t | |
796 | insert_l1opt (uint64_t insn, | |
797 | int64_t value, | |
798 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
799 | const char **errmsg ATTRIBUTE_UNUSED) | |
800 | { | |
801 | return insn | ((value & 1) << 21); | |
802 | } | |
803 | ||
804 | static int64_t | |
805 | extract_l1opt (uint64_t insn, | |
806 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
807 | int *invalid) | |
808 | { | |
809 | /* Return a value of 1 for a missing optional operand. */ | |
810 | if (*invalid < 0) | |
811 | return 1; | |
812 | ||
813 | return (insn >> 21) & 1; | |
814 | } | |
815 | ||
0f873fd5 PB |
816 | static uint64_t |
817 | insert_li20 (uint64_t insn, | |
818 | int64_t value, | |
b80c7270 AM |
819 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
820 | const char **errmsg ATTRIBUTE_UNUSED) | |
821 | { | |
822 | return (insn | |
823 | | ((value & 0xf0000) >> 5) | |
824 | | ((value & 0x0f800) << 5) | |
825 | | (value & 0x7ff)); | |
826 | } | |
a680de9a | 827 | |
0f873fd5 PB |
828 | static int64_t |
829 | extract_li20 (uint64_t insn, | |
b80c7270 AM |
830 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
831 | int *invalid ATTRIBUTE_UNUSED) | |
832 | { | |
f143cb5f AM |
833 | return ((((insn << 5) & 0xf0000) |
834 | | ((insn >> 5) & 0xf800) | |
835 | | (insn & 0x7ff)) ^ 0x80000) - 0x80000; | |
b80c7270 | 836 | } |
e3c2f928 | 837 | |
b80c7270 AM |
838 | /* The 2-bit L field in a SYNC or WC field in a WAIT instruction. |
839 | For SYNC, some L values are reserved: | |
840 | * Value 3 is reserved on newer server cpus. | |
841 | * Values 2 and 3 are reserved on all other cpus. */ | |
adadcc0c | 842 | |
0f873fd5 PB |
843 | static uint64_t |
844 | insert_ls (uint64_t insn, | |
845 | int64_t value, | |
b80c7270 AM |
846 | ppc_cpu_t dialect, |
847 | const char **errmsg) | |
848 | { | |
849 | /* For SYNC, some L values are illegal. */ | |
850 | if (((insn >> 1) & 0x3ff) == 598) | |
851 | { | |
0f873fd5 | 852 | int64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; |
b80c7270 | 853 | if (value > max_lvalue) |
71553718 | 854 | *errmsg = _("illegal L operand value"); |
b80c7270 | 855 | } |
1f6c9eb0 | 856 | |
b80c7270 AM |
857 | return insn | ((value & 0x3) << 21); |
858 | } | |
b9c361e0 | 859 | |
0f873fd5 PB |
860 | static int64_t |
861 | extract_ls (uint64_t insn, | |
b80c7270 AM |
862 | ppc_cpu_t dialect, |
863 | int *invalid) | |
864 | { | |
9cf7e568 AM |
865 | /* Missing optional operands have a value of zero. */ |
866 | if (*invalid < 0) | |
867 | return 0; | |
b9c361e0 | 868 | |
9cf7e568 | 869 | uint64_t lvalue = (insn >> 21) & 3; |
b80c7270 AM |
870 | if (((insn >> 1) & 0x3ff) == 598) |
871 | { | |
0f873fd5 | 872 | uint64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; |
b80c7270 AM |
873 | if (lvalue > max_lvalue) |
874 | *invalid = 1; | |
875 | } | |
876 | return lvalue; | |
877 | } | |
b9c361e0 | 878 | |
b80c7270 AM |
879 | /* The 4-bit E field in a sync instruction that accepts 2 operands. |
880 | If ESYNC is non-zero, then the L field must be either 0 or 1 and | |
881 | the complement of ESYNC-bit2. */ | |
b9c361e0 | 882 | |
0f873fd5 PB |
883 | static uint64_t |
884 | insert_esync (uint64_t insn, | |
885 | int64_t value, | |
9cf7e568 | 886 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 AM |
887 | const char **errmsg) |
888 | { | |
0f873fd5 | 889 | uint64_t ls = (insn >> 21) & 0x03; |
b9c361e0 | 890 | |
9cf7e568 AM |
891 | if (value != 0 |
892 | && ((~value >> 1) & 0x1) != ls) | |
b80c7270 | 893 | *errmsg = _("incompatible L operand value"); |
b9c361e0 | 894 | |
b80c7270 AM |
895 | return insn | ((value & 0xf) << 16); |
896 | } | |
b9c361e0 | 897 | |
0f873fd5 PB |
898 | static int64_t |
899 | extract_esync (uint64_t insn, | |
9cf7e568 | 900 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 AM |
901 | int *invalid) |
902 | { | |
8acf1435 | 903 | /* Missing optional operands have a value of zero. */ |
9cf7e568 AM |
904 | if (*invalid < 0) |
905 | return 0; | |
b9c361e0 | 906 | |
9cf7e568 AM |
907 | uint64_t ls = (insn >> 21) & 0x3; |
908 | uint64_t value = (insn >> 16) & 0xf; | |
909 | if (value != 0 | |
910 | && ((~value >> 1) & 0x1) != ls) | |
b80c7270 | 911 | *invalid = 1; |
9cf7e568 | 912 | return value; |
b80c7270 | 913 | } |
e3c2f928 | 914 | |
b80c7270 AM |
915 | /* The MB and ME fields in an M form instruction expressed as a single |
916 | operand which is itself a bitmask. The extraction function always | |
917 | marks it as invalid, since we never want to recognize an | |
918 | instruction which uses a field of this type. */ | |
5817ffd1 | 919 | |
0f873fd5 PB |
920 | static uint64_t |
921 | insert_mbe (uint64_t insn, | |
922 | int64_t value, | |
b80c7270 AM |
923 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
924 | const char **errmsg) | |
925 | { | |
0f873fd5 PB |
926 | uint64_t uval, mask; |
927 | long mb, me, mx, count, last; | |
252b5132 | 928 | |
b80c7270 | 929 | uval = value; |
1f6c9eb0 | 930 | |
b80c7270 AM |
931 | if (uval == 0) |
932 | { | |
933 | *errmsg = _("illegal bitmask"); | |
934 | return insn; | |
935 | } | |
252b5132 | 936 | |
b80c7270 AM |
937 | mb = 0; |
938 | me = 32; | |
939 | if ((uval & 1) != 0) | |
940 | last = 1; | |
941 | else | |
942 | last = 0; | |
943 | count = 0; | |
252b5132 | 944 | |
b80c7270 AM |
945 | /* mb: location of last 0->1 transition */ |
946 | /* me: location of last 1->0 transition */ | |
947 | /* count: # transitions */ | |
b9c361e0 | 948 | |
0f873fd5 | 949 | for (mx = 0, mask = (uint64_t) 1 << 31; mx < 32; ++mx, mask >>= 1) |
b80c7270 AM |
950 | { |
951 | if ((uval & mask) && !last) | |
952 | { | |
953 | ++count; | |
954 | mb = mx; | |
955 | last = 1; | |
956 | } | |
957 | else if (!(uval & mask) && last) | |
958 | { | |
959 | ++count; | |
960 | me = mx; | |
961 | last = 0; | |
962 | } | |
963 | } | |
964 | if (me == 0) | |
965 | me = 32; | |
252b5132 | 966 | |
b80c7270 AM |
967 | if (count != 2 && (count != 0 || ! last)) |
968 | *errmsg = _("illegal bitmask"); | |
252b5132 | 969 | |
b80c7270 AM |
970 | return insn | (mb << 6) | ((me - 1) << 1); |
971 | } | |
252b5132 | 972 | |
0f873fd5 PB |
973 | static int64_t |
974 | extract_mbe (uint64_t insn, | |
b80c7270 AM |
975 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
976 | int *invalid) | |
977 | { | |
0f873fd5 PB |
978 | int64_t ret; |
979 | long mb, me; | |
980 | long i; | |
252b5132 | 981 | |
b80c7270 | 982 | *invalid = 1; |
f5c120c5 | 983 | |
b80c7270 AM |
984 | mb = (insn >> 6) & 0x1f; |
985 | me = (insn >> 1) & 0x1f; | |
986 | if (mb < me + 1) | |
987 | { | |
988 | ret = 0; | |
989 | for (i = mb; i <= me; i++) | |
0f873fd5 | 990 | ret |= (uint64_t) 1 << (31 - i); |
b80c7270 AM |
991 | } |
992 | else if (mb == me + 1) | |
993 | ret = ~0; | |
994 | else /* (mb > me + 1) */ | |
995 | { | |
996 | ret = ~0; | |
997 | for (i = me + 1; i < mb; i++) | |
0f873fd5 | 998 | ret &= ~((uint64_t) 1 << (31 - i)); |
b80c7270 AM |
999 | } |
1000 | return ret; | |
1001 | } | |
aea77599 | 1002 | |
b80c7270 AM |
1003 | /* The MB or ME field in an MD or MDS form instruction. The high bit |
1004 | is wrapped to the low end. */ | |
252b5132 | 1005 | |
0f873fd5 PB |
1006 | static uint64_t |
1007 | insert_mb6 (uint64_t insn, | |
1008 | int64_t value, | |
b80c7270 AM |
1009 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1010 | const char **errmsg ATTRIBUTE_UNUSED) | |
1011 | { | |
1012 | return insn | ((value & 0x1f) << 6) | (value & 0x20); | |
1013 | } | |
252b5132 | 1014 | |
0f873fd5 PB |
1015 | static int64_t |
1016 | extract_mb6 (uint64_t insn, | |
b80c7270 AM |
1017 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1018 | int *invalid ATTRIBUTE_UNUSED) | |
1019 | { | |
1020 | return ((insn >> 6) & 0x1f) | (insn & 0x20); | |
1021 | } | |
252b5132 | 1022 | |
b80c7270 AM |
1023 | /* The NB field in an X form instruction. The value 32 is stored as |
1024 | 0. */ | |
786e2c0f | 1025 | |
0f873fd5 PB |
1026 | static int64_t |
1027 | extract_nb (uint64_t insn, | |
b80c7270 AM |
1028 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1029 | int *invalid ATTRIBUTE_UNUSED) | |
1030 | { | |
0f873fd5 | 1031 | int64_t ret; |
a47622ac | 1032 | |
b80c7270 AM |
1033 | ret = (insn >> 11) & 0x1f; |
1034 | if (ret == 0) | |
1035 | ret = 32; | |
1036 | return ret; | |
1037 | } | |
b9c361e0 | 1038 | |
b80c7270 AM |
1039 | /* The NB field in an lswi instruction, which has special value |
1040 | restrictions. The value 32 is stored as 0. */ | |
b9c361e0 | 1041 | |
0f873fd5 PB |
1042 | static uint64_t |
1043 | insert_nbi (uint64_t insn, | |
1044 | int64_t value, | |
b80c7270 AM |
1045 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1046 | const char **errmsg ATTRIBUTE_UNUSED) | |
1047 | { | |
0f873fd5 PB |
1048 | int64_t rtvalue = (insn >> 21) & 0x1f; |
1049 | int64_t ravalue = (insn >> 16) & 0x1f; | |
b9c361e0 | 1050 | |
b80c7270 AM |
1051 | if (value == 0) |
1052 | value = 32; | |
1053 | if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 | |
1054 | : ravalue)) | |
1055 | *errmsg = _("address register in load range"); | |
1056 | return insn | ((value & 0x1f) << 11); | |
1057 | } | |
786e2c0f | 1058 | |
b80c7270 AM |
1059 | /* The NSI field in a D form instruction. This is the same as the SI |
1060 | field, only negated. The extraction function always marks it as | |
1061 | invalid, since we never want to recognize an instruction which uses | |
1062 | a field of this type. */ | |
786e2c0f | 1063 | |
0f873fd5 PB |
1064 | static uint64_t |
1065 | insert_nsi (uint64_t insn, | |
1066 | int64_t value, | |
b80c7270 AM |
1067 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1068 | const char **errmsg ATTRIBUTE_UNUSED) | |
1069 | { | |
1070 | return insn | (-value & 0xffff); | |
1071 | } | |
786e2c0f | 1072 | |
0f873fd5 PB |
1073 | static int64_t |
1074 | extract_nsi (uint64_t insn, | |
b80c7270 AM |
1075 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1076 | int *invalid) | |
1077 | { | |
1078 | *invalid = 1; | |
1079 | return -(((insn & 0xffff) ^ 0x8000) - 0x8000); | |
1080 | } | |
786e2c0f | 1081 | |
b80c7270 AM |
1082 | /* The RA field in a D or X form instruction which is an updating |
1083 | load, which means that the RA field may not be zero and may not | |
1084 | equal the RT field. */ | |
786e2c0f | 1085 | |
0f873fd5 PB |
1086 | static uint64_t |
1087 | insert_ral (uint64_t insn, | |
1088 | int64_t value, | |
b80c7270 AM |
1089 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1090 | const char **errmsg) | |
1091 | { | |
1092 | if (value == 0 | |
0f873fd5 | 1093 | || (uint64_t) value == ((insn >> 21) & 0x1f)) |
b80c7270 AM |
1094 | *errmsg = "invalid register operand when updating"; |
1095 | return insn | ((value & 0x1f) << 16); | |
1096 | } | |
786e2c0f | 1097 | |
0f873fd5 PB |
1098 | static int64_t |
1099 | extract_ral (uint64_t insn, | |
b80c7270 AM |
1100 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1101 | int *invalid) | |
1102 | { | |
0f873fd5 PB |
1103 | int64_t rtvalue = (insn >> 21) & 0x1f; |
1104 | int64_t ravalue = (insn >> 16) & 0x1f; | |
fb048c26 | 1105 | |
b80c7270 AM |
1106 | if (rtvalue == ravalue || ravalue == 0) |
1107 | *invalid = 1; | |
1108 | return ravalue; | |
1109 | } | |
a680de9a | 1110 | |
b80c7270 AM |
1111 | /* The RA field in an lmw instruction, which has special value |
1112 | restrictions. */ | |
c0637f3a | 1113 | |
0f873fd5 PB |
1114 | static uint64_t |
1115 | insert_ram (uint64_t insn, | |
1116 | int64_t value, | |
b80c7270 AM |
1117 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1118 | const char **errmsg) | |
1119 | { | |
0f873fd5 | 1120 | if ((uint64_t) value >= ((insn >> 21) & 0x1f)) |
b80c7270 AM |
1121 | *errmsg = _("index register in load range"); |
1122 | return insn | ((value & 0x1f) << 16); | |
1123 | } | |
c0637f3a | 1124 | |
0f873fd5 PB |
1125 | static int64_t |
1126 | extract_ram (uint64_t insn, | |
b80c7270 AM |
1127 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1128 | int *invalid) | |
1129 | { | |
0f873fd5 PB |
1130 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
1131 | uint64_t ravalue = (insn >> 16) & 0x1f; | |
ff3a6ee3 | 1132 | |
b80c7270 AM |
1133 | if (ravalue >= rtvalue) |
1134 | *invalid = 1; | |
1135 | return ravalue; | |
1136 | } | |
23976049 | 1137 | |
b80c7270 AM |
1138 | /* The RA field in the DQ form lq or an lswx instruction, which have special |
1139 | value restrictions. */ | |
e3c2f928 | 1140 | |
0f873fd5 PB |
1141 | static uint64_t |
1142 | insert_raq (uint64_t insn, | |
1143 | int64_t value, | |
b80c7270 AM |
1144 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1145 | const char **errmsg) | |
1146 | { | |
0f873fd5 | 1147 | int64_t rtvalue = (insn >> 21) & 0x1f; |
23976049 | 1148 | |
b80c7270 AM |
1149 | if (value == rtvalue) |
1150 | *errmsg = _("source and target register operands must be different"); | |
1151 | return insn | ((value & 0x1f) << 16); | |
1152 | } | |
e3c2f928 | 1153 | |
0f873fd5 PB |
1154 | static int64_t |
1155 | extract_raq (uint64_t insn, | |
b80c7270 AM |
1156 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1157 | int *invalid) | |
1158 | { | |
8acf1435 | 1159 | /* Missing optional operands have a value of zero. */ |
9cf7e568 AM |
1160 | if (*invalid < 0) |
1161 | return 0; | |
1162 | ||
0f873fd5 PB |
1163 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
1164 | uint64_t ravalue = (insn >> 16) & 0x1f; | |
b80c7270 AM |
1165 | if (ravalue == rtvalue) |
1166 | *invalid = 1; | |
1167 | return ravalue; | |
1168 | } | |
e3c2f928 | 1169 | |
b80c7270 AM |
1170 | /* The RA field in a D or X form instruction which is an updating |
1171 | store or an updating floating point load, which means that the RA | |
1172 | field may not be zero. */ | |
ff3a6ee3 | 1173 | |
0f873fd5 PB |
1174 | static uint64_t |
1175 | insert_ras (uint64_t insn, | |
1176 | int64_t value, | |
b80c7270 AM |
1177 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1178 | const char **errmsg) | |
1179 | { | |
1180 | if (value == 0) | |
1181 | *errmsg = _("invalid register operand when updating"); | |
1182 | return insn | ((value & 0x1f) << 16); | |
1183 | } | |
c3d65c1c | 1184 | |
0f873fd5 PB |
1185 | static int64_t |
1186 | extract_ras (uint64_t insn, | |
b80c7270 AM |
1187 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1188 | int *invalid) | |
1189 | { | |
0f873fd5 | 1190 | uint64_t ravalue = (insn >> 16) & 0x1f; |
c3d65c1c | 1191 | |
b80c7270 AM |
1192 | if (ravalue == 0) |
1193 | *invalid = 1; | |
1194 | return ravalue; | |
1195 | } | |
c3d65c1c | 1196 | |
98553ad3 PB |
1197 | /* The RS and RB fields in an X form instruction when they must be the same. |
1198 | This is used for extended mnemonics like mr. The extraction function | |
1199 | enforces that the fields are the same. */ | |
c3d65c1c | 1200 | |
0f873fd5 | 1201 | static uint64_t |
98553ad3 PB |
1202 | insert_rsb (uint64_t insn, |
1203 | int64_t value, | |
b80c7270 AM |
1204 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1205 | const char **errmsg ATTRIBUTE_UNUSED) | |
1206 | { | |
98553ad3 PB |
1207 | value &= 0x1f; |
1208 | return insn | (value << 21) | (value << 11); | |
b80c7270 | 1209 | } |
5ae2e65e | 1210 | |
0f873fd5 | 1211 | static int64_t |
98553ad3 | 1212 | extract_rsb (uint64_t insn, |
b80c7270 AM |
1213 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1214 | int *invalid) | |
1215 | { | |
98553ad3 PB |
1216 | int64_t rs = (insn >> 21) & 0x1f; |
1217 | int64_t rb = (insn >> 11) & 0x1f; | |
1218 | ||
1219 | if (rs != rb) | |
b80c7270 | 1220 | *invalid = 1; |
98553ad3 | 1221 | return rs; |
b80c7270 | 1222 | } |
702f0fb4 | 1223 | |
b80c7270 AM |
1224 | /* The RB field in an lswx instruction, which has special value |
1225 | restrictions. */ | |
702f0fb4 | 1226 | |
0f873fd5 PB |
1227 | static uint64_t |
1228 | insert_rbx (uint64_t insn, | |
1229 | int64_t value, | |
b80c7270 AM |
1230 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1231 | const char **errmsg) | |
1232 | { | |
0f873fd5 | 1233 | int64_t rtvalue = (insn >> 21) & 0x1f; |
a680de9a | 1234 | |
b80c7270 AM |
1235 | if (value == rtvalue) |
1236 | *errmsg = _("source and target register operands must be different"); | |
1237 | return insn | ((value & 0x1f) << 11); | |
1238 | } | |
a680de9a | 1239 | |
0f873fd5 PB |
1240 | static int64_t |
1241 | extract_rbx (uint64_t insn, | |
b80c7270 AM |
1242 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1243 | int *invalid) | |
1244 | { | |
0f873fd5 PB |
1245 | uint64_t rtvalue = (insn >> 21) & 0x1f; |
1246 | uint64_t rbvalue = (insn >> 11) & 0x1f; | |
702f0fb4 | 1247 | |
b80c7270 AM |
1248 | if (rbvalue == rtvalue) |
1249 | *invalid = 1; | |
1250 | return rbvalue; | |
1251 | } | |
702f0fb4 | 1252 | |
b80c7270 | 1253 | /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ |
0f873fd5 PB |
1254 | static uint64_t |
1255 | insert_sci8 (uint64_t insn, | |
1256 | int64_t value, | |
b80c7270 AM |
1257 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1258 | const char **errmsg) | |
1259 | { | |
0f873fd5 PB |
1260 | uint64_t fill_scale = 0; |
1261 | uint64_t ui8 = value; | |
c0637f3a | 1262 | |
b80c7270 AM |
1263 | if ((ui8 & 0xffffff00) == 0) |
1264 | ; | |
1265 | else if ((ui8 & 0xffffff00) == 0xffffff00) | |
1266 | fill_scale = 0x400; | |
1267 | else if ((ui8 & 0xffff00ff) == 0) | |
1268 | { | |
1269 | fill_scale = 1 << 8; | |
1270 | ui8 >>= 8; | |
1271 | } | |
1272 | else if ((ui8 & 0xffff00ff) == 0xffff00ff) | |
1273 | { | |
1274 | fill_scale = 0x400 | (1 << 8); | |
1275 | ui8 >>= 8; | |
1276 | } | |
1277 | else if ((ui8 & 0xff00ffff) == 0) | |
1278 | { | |
1279 | fill_scale = 2 << 8; | |
1280 | ui8 >>= 16; | |
1281 | } | |
1282 | else if ((ui8 & 0xff00ffff) == 0xff00ffff) | |
1283 | { | |
1284 | fill_scale = 0x400 | (2 << 8); | |
1285 | ui8 >>= 16; | |
1286 | } | |
1287 | else if ((ui8 & 0x00ffffff) == 0) | |
1288 | { | |
1289 | fill_scale = 3 << 8; | |
1290 | ui8 >>= 24; | |
1291 | } | |
1292 | else if ((ui8 & 0x00ffffff) == 0x00ffffff) | |
1293 | { | |
1294 | fill_scale = 0x400 | (3 << 8); | |
1295 | ui8 >>= 24; | |
1296 | } | |
1297 | else | |
1298 | { | |
1299 | *errmsg = _("illegal immediate value"); | |
1300 | ui8 = 0; | |
1301 | } | |
702f0fb4 | 1302 | |
b80c7270 AM |
1303 | return insn | fill_scale | (ui8 & 0xff); |
1304 | } | |
ea192fa3 | 1305 | |
0f873fd5 PB |
1306 | static int64_t |
1307 | extract_sci8 (uint64_t insn, | |
b80c7270 AM |
1308 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1309 | int *invalid ATTRIBUTE_UNUSED) | |
1310 | { | |
0f873fd5 PB |
1311 | int64_t fill = insn & 0x400; |
1312 | int64_t scale_factor = (insn & 0x300) >> 5; | |
1313 | int64_t value = (insn & 0xff) << scale_factor; | |
081ba1b3 | 1314 | |
b80c7270 | 1315 | if (fill != 0) |
0f873fd5 | 1316 | value |= ~((int64_t) 0xff << scale_factor); |
b80c7270 AM |
1317 | return value; |
1318 | } | |
081ba1b3 | 1319 | |
0f873fd5 PB |
1320 | static uint64_t |
1321 | insert_sci8n (uint64_t insn, | |
1322 | int64_t value, | |
b80c7270 AM |
1323 | ppc_cpu_t dialect, |
1324 | const char **errmsg) | |
1325 | { | |
1326 | return insert_sci8 (insn, -value, dialect, errmsg); | |
1327 | } | |
081ba1b3 | 1328 | |
0f873fd5 PB |
1329 | static int64_t |
1330 | extract_sci8n (uint64_t insn, | |
b80c7270 AM |
1331 | ppc_cpu_t dialect, |
1332 | int *invalid) | |
1333 | { | |
1334 | return -extract_sci8 (insn, dialect, invalid); | |
1335 | } | |
081ba1b3 | 1336 | |
0f873fd5 PB |
1337 | static uint64_t |
1338 | insert_oimm (uint64_t insn, | |
1339 | int64_t value, | |
b80c7270 AM |
1340 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1341 | const char **errmsg ATTRIBUTE_UNUSED) | |
1342 | { | |
1343 | return insn | (((value - 1) & 0x1f) << 4); | |
1344 | } | |
b9c361e0 | 1345 | |
0f873fd5 PB |
1346 | static int64_t |
1347 | extract_oimm (uint64_t insn, | |
b80c7270 AM |
1348 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1349 | int *invalid ATTRIBUTE_UNUSED) | |
1350 | { | |
1351 | return ((insn >> 4) & 0x1f) + 1; | |
1352 | } | |
b9c361e0 | 1353 | |
b80c7270 | 1354 | /* The SH field in an MD form instruction. This is split. */ |
b9c361e0 | 1355 | |
0f873fd5 PB |
1356 | static uint64_t |
1357 | insert_sh6 (uint64_t insn, | |
1358 | int64_t value, | |
b80c7270 AM |
1359 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1360 | const char **errmsg ATTRIBUTE_UNUSED) | |
1361 | { | |
71553718 | 1362 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
b80c7270 | 1363 | } |
9b4e5766 | 1364 | |
0f873fd5 PB |
1365 | static int64_t |
1366 | extract_sh6 (uint64_t insn, | |
b80c7270 AM |
1367 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1368 | int *invalid ATTRIBUTE_UNUSED) | |
1369 | { | |
71553718 | 1370 | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
b80c7270 | 1371 | } |
a680de9a | 1372 | |
b80c7270 AM |
1373 | /* The SPR field in an XFX form instruction. This is flipped--the |
1374 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
9b4e5766 | 1375 | |
0f873fd5 PB |
1376 | static uint64_t |
1377 | insert_spr (uint64_t insn, | |
1378 | int64_t value, | |
b80c7270 AM |
1379 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1380 | const char **errmsg ATTRIBUTE_UNUSED) | |
1381 | { | |
1382 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1383 | } | |
9b4e5766 | 1384 | |
0f873fd5 PB |
1385 | static int64_t |
1386 | extract_spr (uint64_t insn, | |
b80c7270 AM |
1387 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1388 | int *invalid ATTRIBUTE_UNUSED) | |
1389 | { | |
1390 | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); | |
1391 | } | |
9b4e5766 | 1392 | |
fa758a70 AC |
1393 | /* Some dialects have 8 [DI]BAT registers instead of the standard 4. */ |
1394 | #define ALLOW8_BAT (PPC_OPCODE_750) | |
1395 | ||
16065af1 AM |
1396 | static uint64_t |
1397 | insert_sprbat (uint64_t insn, | |
1398 | int64_t value, | |
fa758a70 AC |
1399 | ppc_cpu_t dialect, |
1400 | const char **errmsg) | |
1401 | { | |
71553718 AM |
1402 | if ((uint64_t) value > 7 |
1403 | || ((uint64_t) value > 3 && (dialect & ALLOW8_BAT) == 0)) | |
fa758a70 AC |
1404 | *errmsg = _("invalid bat number"); |
1405 | ||
1406 | /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */ | |
71553718 | 1407 | if ((uint64_t) value > 3) |
fa758a70 AC |
1408 | value = ((value & 3) << 6) | 1; |
1409 | else | |
1410 | value = value << 6; | |
1411 | ||
1412 | return insn | (value << 11); | |
1413 | } | |
1414 | ||
16065af1 AM |
1415 | static int64_t |
1416 | extract_sprbat (uint64_t insn, | |
fa758a70 AC |
1417 | ppc_cpu_t dialect, |
1418 | int *invalid) | |
1419 | { | |
16065af1 | 1420 | uint64_t val = (insn >> 17) & 0x3; |
fa758a70 AC |
1421 | |
1422 | val = val + ((insn >> 9) & 0x4); | |
1423 | if (val > 3 && (dialect & ALLOW8_BAT) == 0) | |
1424 | *invalid = 1; | |
1425 | return val; | |
1426 | } | |
1427 | ||
b80c7270 AM |
1428 | /* Some dialects have 8 SPRG registers instead of the standard 4. */ |
1429 | #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) | |
066be9f7 | 1430 | |
0f873fd5 PB |
1431 | static uint64_t |
1432 | insert_sprg (uint64_t insn, | |
1433 | int64_t value, | |
b80c7270 AM |
1434 | ppc_cpu_t dialect, |
1435 | const char **errmsg) | |
1436 | { | |
71553718 AM |
1437 | if ((uint64_t) value > 7 |
1438 | || ((uint64_t) value > 3 && (dialect & ALLOW8_SPRG) == 0)) | |
b80c7270 | 1439 | *errmsg = _("invalid sprg number"); |
066be9f7 | 1440 | |
b80c7270 AM |
1441 | /* If this is mfsprg4..7 then use spr 260..263 which can be read in |
1442 | user mode. Anything else must use spr 272..279. */ | |
71553718 | 1443 | if ((uint64_t) value <= 3 || (insn & 0x100) != 0) |
b80c7270 | 1444 | value |= 0x10; |
066be9f7 | 1445 | |
b80c7270 AM |
1446 | return insn | ((value & 0x17) << 16); |
1447 | } | |
e0d602ec | 1448 | |
0f873fd5 PB |
1449 | static int64_t |
1450 | extract_sprg (uint64_t insn, | |
b80c7270 AM |
1451 | ppc_cpu_t dialect, |
1452 | int *invalid) | |
1453 | { | |
0f873fd5 | 1454 | uint64_t val = (insn >> 16) & 0x1f; |
4bc0608a | 1455 | |
b80c7270 AM |
1456 | /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 |
1457 | If not BOOKE, 405 or VLE, then both use only 272..275. */ | |
1458 | if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) | |
1459 | || (val - 0x10 > 7 && (insn & 0x100) != 0) | |
1460 | || val <= 3 | |
1461 | || (val & 8) != 0) | |
1462 | *invalid = 1; | |
1463 | return val & 7; | |
1464 | } | |
a680de9a | 1465 | |
b80c7270 AM |
1466 | /* The TBR field in an XFX instruction. This is just like SPR, but it |
1467 | is optional. */ | |
e3c2f928 | 1468 | |
0f873fd5 PB |
1469 | static uint64_t |
1470 | insert_tbr (uint64_t insn, | |
1471 | int64_t value, | |
b80c7270 AM |
1472 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1473 | const char **errmsg) | |
1474 | { | |
1475 | if (value != 268 && value != 269) | |
1476 | *errmsg = _("invalid tbr number"); | |
1477 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
1478 | } | |
252b5132 | 1479 | |
0f873fd5 PB |
1480 | static int64_t |
1481 | extract_tbr (uint64_t insn, | |
b80c7270 AM |
1482 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1483 | int *invalid) | |
1484 | { | |
8acf1435 | 1485 | /* Missing optional operands have a value of 268. */ |
9cf7e568 AM |
1486 | if (*invalid < 0) |
1487 | return 268; | |
1488 | ||
0f873fd5 | 1489 | int64_t ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
b80c7270 AM |
1490 | if (ret != 268 && ret != 269) |
1491 | *invalid = 1; | |
1492 | return ret; | |
1493 | } | |
252b5132 | 1494 | |
b80c7270 | 1495 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
b9c361e0 | 1496 | |
0f873fd5 PB |
1497 | static uint64_t |
1498 | insert_xt6 (uint64_t insn, | |
1499 | int64_t value, | |
b9c361e0 JL |
1500 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1501 | const char **errmsg ATTRIBUTE_UNUSED) | |
1502 | { | |
b80c7270 | 1503 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); |
b9c361e0 JL |
1504 | } |
1505 | ||
0f873fd5 PB |
1506 | static int64_t |
1507 | extract_xt6 (uint64_t insn, | |
b9c361e0 JL |
1508 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1509 | int *invalid ATTRIBUTE_UNUSED) | |
43e65147 | 1510 | { |
b80c7270 | 1511 | return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); |
b9c361e0 JL |
1512 | } |
1513 | ||
b80c7270 | 1514 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
0f873fd5 PB |
1515 | static uint64_t |
1516 | insert_xtq6 (uint64_t insn, | |
1517 | int64_t value, | |
b80c7270 AM |
1518 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1519 | const char **errmsg ATTRIBUTE_UNUSED) | |
1520 | { | |
1521 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); | |
1522 | } | |
1523 | ||
0f873fd5 PB |
1524 | static int64_t |
1525 | extract_xtq6 (uint64_t insn, | |
b80c7270 AM |
1526 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1527 | int *invalid ATTRIBUTE_UNUSED) | |
1528 | { | |
1529 | return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); | |
1530 | } | |
1531 | ||
1532 | /* The XA field in an XX3 form instruction. This is split. */ | |
1533 | ||
0f873fd5 PB |
1534 | static uint64_t |
1535 | insert_xa6 (uint64_t insn, | |
1536 | int64_t value, | |
b9c361e0 JL |
1537 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1538 | const char **errmsg ATTRIBUTE_UNUSED) | |
1539 | { | |
b80c7270 | 1540 | return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); |
b9c361e0 JL |
1541 | } |
1542 | ||
0f873fd5 PB |
1543 | static int64_t |
1544 | extract_xa6 (uint64_t insn, | |
b9c361e0 JL |
1545 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1546 | int *invalid ATTRIBUTE_UNUSED) | |
1547 | { | |
b80c7270 | 1548 | return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); |
b9c361e0 JL |
1549 | } |
1550 | ||
aa3c112f AM |
1551 | /* The XA field in an MMA XX3 form instruction. This is split |
1552 | and must not overlap with the ACC operand. */ | |
1553 | ||
1554 | static uint64_t | |
1555 | insert_xa6a (uint64_t insn, | |
1556 | int64_t value, | |
1557 | ppc_cpu_t dialect, | |
1558 | const char **errmsg) | |
1559 | { | |
1560 | int64_t acc = (insn >> 23) & 0x7; | |
1561 | if ((value >> 2) == acc) | |
1562 | *errmsg = _("VSR overlaps ACC operand"); | |
1563 | return insert_xa6 (insn, value, dialect, errmsg); | |
1564 | } | |
1565 | ||
1566 | static int64_t | |
1567 | extract_xa6a (uint64_t insn, | |
1568 | ppc_cpu_t dialect, | |
1569 | int *invalid) | |
1570 | { | |
1571 | int64_t acc = (insn >> 23) & 0x7; | |
1572 | int64_t value = extract_xa6 (insn, dialect, invalid); | |
1573 | if ((value >> 2) == acc) | |
1574 | *invalid = 1; | |
1575 | return value; | |
1576 | } | |
1577 | ||
b80c7270 AM |
1578 | /* The XB field in an XX3 form instruction. This is split. */ |
1579 | ||
0f873fd5 PB |
1580 | static uint64_t |
1581 | insert_xb6 (uint64_t insn, | |
1582 | int64_t value, | |
b80c7270 AM |
1583 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1584 | const char **errmsg ATTRIBUTE_UNUSED) | |
b9c361e0 | 1585 | { |
b80c7270 | 1586 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
b9c361e0 JL |
1587 | } |
1588 | ||
0f873fd5 PB |
1589 | static int64_t |
1590 | extract_xb6 (uint64_t insn, | |
b80c7270 AM |
1591 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1592 | int *invalid ATTRIBUTE_UNUSED) | |
b9c361e0 | 1593 | { |
b80c7270 | 1594 | return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); |
b9c361e0 JL |
1595 | } |
1596 | ||
aa3c112f AM |
1597 | /* The XB field in an MMA XX3 form instruction. This is split |
1598 | and must not overlap with the ACC operand. */ | |
1599 | ||
1600 | static uint64_t | |
1601 | insert_xb6a (uint64_t insn, | |
1602 | int64_t value, | |
1603 | ppc_cpu_t dialect, | |
1604 | const char **errmsg) | |
1605 | { | |
1606 | int64_t acc = (insn >> 23) & 0x7; | |
1607 | if ((value >> 2) == acc) | |
1608 | *errmsg = _("VSR overlaps ACC operand"); | |
1609 | return insert_xb6 (insn, value, dialect, errmsg); | |
1610 | } | |
1611 | ||
1612 | static int64_t | |
1613 | extract_xb6a (uint64_t insn, | |
1614 | ppc_cpu_t dialect, | |
1615 | int *invalid) | |
1616 | { | |
1617 | int64_t acc = (insn >> 23) & 0x7; | |
1618 | int64_t value = extract_xb6 (insn, dialect, invalid); | |
1619 | if ((value >> 2) == acc) | |
1620 | *invalid = 1; | |
1621 | return value; | |
1622 | } | |
1623 | ||
98553ad3 PB |
1624 | /* The XA and XB fields in an XX3 form instruction when they must be the same. |
1625 | This is used for extended mnemonics like xvmovdp. The extraction function | |
1626 | enforces that the fields are the same. */ | |
b80c7270 | 1627 | |
0f873fd5 | 1628 | static uint64_t |
98553ad3 PB |
1629 | insert_xab6 (uint64_t insn, |
1630 | int64_t value, | |
1631 | ppc_cpu_t dialect, | |
1632 | const char **errmsg) | |
b9c361e0 | 1633 | { |
98553ad3 PB |
1634 | return insert_xa6 (insn, value, dialect, errmsg) |
1635 | | insert_xb6 (insn, value, dialect, errmsg); | |
b9c361e0 JL |
1636 | } |
1637 | ||
0f873fd5 | 1638 | static int64_t |
98553ad3 PB |
1639 | extract_xab6 (uint64_t insn, |
1640 | ppc_cpu_t dialect, | |
b80c7270 | 1641 | int *invalid) |
b9c361e0 | 1642 | { |
98553ad3 PB |
1643 | int64_t xa6 = extract_xa6 (insn, dialect, invalid); |
1644 | int64_t xb6 = extract_xb6 (insn, dialect, invalid); | |
1645 | ||
1646 | if (xa6 != xb6) | |
b80c7270 | 1647 | *invalid = 1; |
98553ad3 | 1648 | return xa6; |
b9c361e0 JL |
1649 | } |
1650 | ||
b80c7270 | 1651 | /* The XC field in an XX4 form instruction. This is split. */ |
252b5132 | 1652 | |
0f873fd5 PB |
1653 | static uint64_t |
1654 | insert_xc6 (uint64_t insn, | |
1655 | int64_t value, | |
fa452fa6 | 1656 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2fbfdc41 | 1657 | const char **errmsg ATTRIBUTE_UNUSED) |
252b5132 | 1658 | { |
b80c7270 | 1659 | return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); |
252b5132 RH |
1660 | } |
1661 | ||
0f873fd5 PB |
1662 | static int64_t |
1663 | extract_xc6 (uint64_t insn, | |
fa452fa6 | 1664 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
b80c7270 | 1665 | int *invalid ATTRIBUTE_UNUSED) |
252b5132 | 1666 | { |
b80c7270 AM |
1667 | return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); |
1668 | } | |
1669 | ||
94ba9882 AM |
1670 | /* The split XTp field in a vector paired insn. */ |
1671 | ||
1672 | static uint64_t | |
1673 | insert_xtp (uint64_t insn, | |
1674 | int64_t value, | |
1675 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1676 | const char **errmsg ATTRIBUTE_UNUSED) | |
1677 | { | |
1678 | return insn | ((value & 0x1e) << 21) | ((value & 0x20) << (21 - 5)); | |
1679 | } | |
1680 | ||
1681 | static int64_t | |
1682 | extract_xtp (uint64_t insn, | |
1683 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1684 | int *invalid ATTRIBUTE_UNUSED) | |
1685 | { | |
1686 | return ((insn >> (21 - 5)) & 0x20) | ((insn >> 21) & 0x1e); | |
1687 | } | |
1688 | ||
6edbfd3b AM |
1689 | /* The split XT field in a vector splat insn. */ |
1690 | ||
1691 | static uint64_t | |
1692 | insert_xts (uint64_t insn, | |
1693 | int64_t value, | |
1694 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1695 | const char **errmsg ATTRIBUTE_UNUSED) | |
1696 | { | |
1697 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) << (16 - 5)); | |
1698 | } | |
1699 | ||
1700 | static int64_t | |
1701 | extract_xts (uint64_t insn, | |
1702 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
1703 | int *invalid ATTRIBUTE_UNUSED) | |
1704 | { | |
1705 | return ((insn >> (16 - 5)) & 0x20) | ((insn >> 21) & 0x1f); | |
1706 | } | |
1707 | ||
0f873fd5 PB |
1708 | static uint64_t |
1709 | insert_dm (uint64_t insn, | |
1710 | int64_t value, | |
b80c7270 AM |
1711 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1712 | const char **errmsg) | |
1713 | { | |
1714 | if (value != 0 && value != 1) | |
1715 | *errmsg = _("invalid constant"); | |
1716 | return insn | (((value) ? 3 : 0) << 8); | |
1717 | } | |
1718 | ||
0f873fd5 PB |
1719 | static int64_t |
1720 | extract_dm (uint64_t insn, | |
b80c7270 AM |
1721 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1722 | int *invalid) | |
1723 | { | |
0f873fd5 | 1724 | int64_t value = (insn >> 8) & 3; |
b80c7270 | 1725 | if (value != 0 && value != 3) |
252b5132 | 1726 | *invalid = 1; |
b80c7270 | 1727 | return (value) ? 1 : 0; |
252b5132 RH |
1728 | } |
1729 | ||
b80c7270 | 1730 | /* The VLESIMM field in an I16A form instruction. This is split. */ |
252b5132 | 1731 | |
0f873fd5 PB |
1732 | static uint64_t |
1733 | insert_vlesi (uint64_t insn, | |
1734 | int64_t value, | |
b80c7270 AM |
1735 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1736 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1737 | { |
b80c7270 | 1738 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
252b5132 RH |
1739 | } |
1740 | ||
0f873fd5 PB |
1741 | static int64_t |
1742 | extract_vlesi (uint64_t insn, | |
b80c7270 AM |
1743 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1744 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1745 | { |
0f873fd5 | 1746 | int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
b80c7270 AM |
1747 | value = (value ^ 0x8000) - 0x8000; |
1748 | return value; | |
252b5132 RH |
1749 | } |
1750 | ||
0f873fd5 PB |
1751 | static uint64_t |
1752 | insert_vlensi (uint64_t insn, | |
1753 | int64_t value, | |
b80c7270 AM |
1754 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1755 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1756 | { |
b80c7270 AM |
1757 | value = -value; |
1758 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); | |
252b5132 | 1759 | } |
0f873fd5 PB |
1760 | static int64_t |
1761 | extract_vlensi (uint64_t insn, | |
b80c7270 | 1762 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
9cf7e568 | 1763 | int *invalid) |
252b5132 | 1764 | { |
0f873fd5 | 1765 | int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
b80c7270 AM |
1766 | value = (value ^ 0x8000) - 0x8000; |
1767 | /* Don't use for disassembly. */ | |
1768 | *invalid = 1; | |
1769 | return -value; | |
252b5132 RH |
1770 | } |
1771 | ||
b80c7270 | 1772 | /* The VLEUIMM field in an I16A form instruction. This is split. */ |
252b5132 | 1773 | |
0f873fd5 PB |
1774 | static uint64_t |
1775 | insert_vleui (uint64_t insn, | |
1776 | int64_t value, | |
b80c7270 AM |
1777 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1778 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 1779 | { |
b80c7270 | 1780 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
252b5132 RH |
1781 | } |
1782 | ||
0f873fd5 PB |
1783 | static int64_t |
1784 | extract_vleui (uint64_t insn, | |
b80c7270 AM |
1785 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1786 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1787 | { |
b80c7270 AM |
1788 | return ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
1789 | } | |
8427c424 | 1790 | |
b80c7270 AM |
1791 | /* The VLEUIMML field in an I16L form instruction. This is split. */ |
1792 | ||
0f873fd5 PB |
1793 | static uint64_t |
1794 | insert_vleil (uint64_t insn, | |
1795 | int64_t value, | |
b80c7270 AM |
1796 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1797 | const char **errmsg ATTRIBUTE_UNUSED) | |
1798 | { | |
1799 | return insn | ((value & 0xf800) << 5) | (value & 0x7ff); | |
252b5132 RH |
1800 | } |
1801 | ||
0f873fd5 PB |
1802 | static int64_t |
1803 | extract_vleil (uint64_t insn, | |
b80c7270 AM |
1804 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1805 | int *invalid ATTRIBUTE_UNUSED) | |
252b5132 | 1806 | { |
b80c7270 | 1807 | return ((insn >> 5) & 0xf800) | (insn & 0x7ff); |
8ebac3aa | 1808 | } |
ba4e851b | 1809 | |
0f873fd5 PB |
1810 | static uint64_t |
1811 | insert_evuimm1_ex0 (uint64_t insn, | |
1812 | int64_t value, | |
74081948 AF |
1813 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1814 | const char **errmsg) | |
1815 | { | |
71553718 AM |
1816 | if (value <= 0 || value > 0x1f) |
1817 | *errmsg = _("UIMM = 00000 is illegal"); | |
1818 | return insn | ((value & 0x1f) << 11); | |
74081948 AF |
1819 | } |
1820 | ||
0f873fd5 PB |
1821 | static int64_t |
1822 | extract_evuimm1_ex0 (uint64_t insn, | |
74081948 AF |
1823 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1824 | int *invalid) | |
1825 | { | |
0f873fd5 | 1826 | int64_t value = ((insn >> 11) & 0x1f); |
74081948 AF |
1827 | if (value == 0) |
1828 | *invalid = 1; | |
1829 | ||
1830 | return value; | |
1831 | } | |
1832 | ||
0f873fd5 PB |
1833 | static uint64_t |
1834 | insert_evuimm2_ex0 (uint64_t insn, | |
1835 | int64_t value, | |
b80c7270 AM |
1836 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1837 | const char **errmsg) | |
8ebac3aa | 1838 | { |
71553718 AM |
1839 | if (value <= 0 || value > 0x3e) |
1840 | *errmsg = _("UIMM = 00000 is illegal"); | |
1841 | return insn | ((value & 0x3e) << 10); | |
252b5132 RH |
1842 | } |
1843 | ||
0f873fd5 PB |
1844 | static int64_t |
1845 | extract_evuimm2_ex0 (uint64_t insn, | |
b80c7270 AM |
1846 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1847 | int *invalid) | |
8ebac3aa | 1848 | { |
0f873fd5 | 1849 | int64_t value = ((insn >> 10) & 0x3e); |
b80c7270 AM |
1850 | if (value == 0) |
1851 | *invalid = 1; | |
8ebac3aa | 1852 | |
b80c7270 | 1853 | return value; |
8ebac3aa AM |
1854 | } |
1855 | ||
0f873fd5 PB |
1856 | static uint64_t |
1857 | insert_evuimm4_ex0 (uint64_t insn, | |
1858 | int64_t value, | |
b80c7270 AM |
1859 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1860 | const char **errmsg) | |
252b5132 | 1861 | { |
71553718 AM |
1862 | if (value <= 0 || value > 0x7c) |
1863 | *errmsg = _("UIMM = 00000 is illegal"); | |
1864 | return insn | ((value & 0x7c) << 9); | |
252b5132 RH |
1865 | } |
1866 | ||
0f873fd5 PB |
1867 | static int64_t |
1868 | extract_evuimm4_ex0 (uint64_t insn, | |
b80c7270 AM |
1869 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1870 | int *invalid) | |
252b5132 | 1871 | { |
0f873fd5 | 1872 | int64_t value = ((insn >> 9) & 0x7c); |
b80c7270 | 1873 | if (value == 0) |
252b5132 | 1874 | *invalid = 1; |
b80c7270 | 1875 | |
252b5132 RH |
1876 | return value; |
1877 | } | |
1878 | ||
0f873fd5 PB |
1879 | static uint64_t |
1880 | insert_evuimm8_ex0 (uint64_t insn, | |
1881 | int64_t value, | |
b80c7270 AM |
1882 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1883 | const char **errmsg) | |
1884 | { | |
71553718 AM |
1885 | if (value <= 0 || value > 0xf8) |
1886 | *errmsg = _("UIMM = 00000 is illegal"); | |
1887 | return insn | ((value & 0xf8) << 8); | |
252b5132 RH |
1888 | } |
1889 | ||
0f873fd5 PB |
1890 | static int64_t |
1891 | extract_evuimm8_ex0 (uint64_t insn, | |
b80c7270 AM |
1892 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1893 | int *invalid) | |
252b5132 | 1894 | { |
0f873fd5 | 1895 | int64_t value = ((insn >> 8) & 0xf8); |
b80c7270 | 1896 | if (value == 0) |
252b5132 | 1897 | *invalid = 1; |
252b5132 | 1898 | |
b80c7270 AM |
1899 | return value; |
1900 | } | |
a680de9a | 1901 | |
0f873fd5 PB |
1902 | static uint64_t |
1903 | insert_evuimm_lt8 (uint64_t insn, | |
1904 | int64_t value, | |
74081948 AF |
1905 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1906 | const char **errmsg) | |
1907 | { | |
71553718 AM |
1908 | if (value < 0 || value > 7) |
1909 | *errmsg = _("UIMM values >7 are illegal"); | |
1910 | return insn | ((value & 0x7) << 11); | |
74081948 AF |
1911 | } |
1912 | ||
0f873fd5 PB |
1913 | static int64_t |
1914 | extract_evuimm_lt8 (uint64_t insn, | |
74081948 AF |
1915 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1916 | int *invalid) | |
1917 | { | |
0f873fd5 | 1918 | int64_t value = ((insn >> 11) & 0x1f); |
74081948 AF |
1919 | if (value > 7) |
1920 | *invalid = 1; | |
1921 | ||
1922 | return value; | |
1923 | } | |
1924 | ||
0f873fd5 PB |
1925 | static uint64_t |
1926 | insert_evuimm_lt16 (uint64_t insn, | |
1927 | int64_t value, | |
b80c7270 AM |
1928 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1929 | const char **errmsg) | |
a680de9a | 1930 | { |
71553718 AM |
1931 | if (value < 0 || value > 15) |
1932 | *errmsg = _("UIMM values >15 are illegal"); | |
1933 | return insn | ((value & 0xf) << 11); | |
a680de9a PB |
1934 | } |
1935 | ||
0f873fd5 PB |
1936 | static int64_t |
1937 | extract_evuimm_lt16 (uint64_t insn, | |
b80c7270 AM |
1938 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1939 | int *invalid) | |
a680de9a | 1940 | { |
0f873fd5 | 1941 | int64_t value = ((insn >> 11) & 0x1f); |
b80c7270 AM |
1942 | if (value > 15) |
1943 | *invalid = 1; | |
a680de9a | 1944 | |
b80c7270 AM |
1945 | return value; |
1946 | } | |
a680de9a | 1947 | |
0f873fd5 PB |
1948 | static uint64_t |
1949 | insert_rD_rS_even (uint64_t insn, | |
1950 | int64_t value, | |
b80c7270 AM |
1951 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1952 | const char **errmsg) | |
a680de9a | 1953 | { |
71553718 AM |
1954 | if ((value & 0x1) != 0) |
1955 | *errmsg = _("GPR odd is illegal"); | |
1956 | return insn | ((value & 0x1e) << 21); | |
a680de9a PB |
1957 | } |
1958 | ||
0f873fd5 PB |
1959 | static int64_t |
1960 | extract_rD_rS_even (uint64_t insn, | |
b80c7270 AM |
1961 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1962 | int *invalid) | |
a680de9a | 1963 | { |
0f873fd5 | 1964 | int64_t value = ((insn >> 21) & 0x1f); |
b80c7270 AM |
1965 | if ((value & 0x1) != 0) |
1966 | *invalid = 1; | |
1967 | ||
1968 | return value; | |
a680de9a PB |
1969 | } |
1970 | ||
0f873fd5 PB |
1971 | static uint64_t |
1972 | insert_off_lsp (uint64_t insn, | |
1973 | int64_t value, | |
b80c7270 AM |
1974 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1975 | const char **errmsg) | |
a680de9a | 1976 | { |
71553718 AM |
1977 | if (value <= 0 || value > 0x3) |
1978 | *errmsg = _("invalid offset"); | |
1979 | return insn | (value & 0x3); | |
a680de9a PB |
1980 | } |
1981 | ||
0f873fd5 PB |
1982 | static int64_t |
1983 | extract_off_lsp (uint64_t insn, | |
b80c7270 AM |
1984 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1985 | int *invalid) | |
a680de9a | 1986 | { |
0f873fd5 | 1987 | int64_t value = (insn & 0x3); |
b80c7270 AM |
1988 | if (value == 0) |
1989 | *invalid = 1; | |
1990 | ||
1991 | return value; | |
a680de9a | 1992 | } |
74081948 | 1993 | |
0f873fd5 PB |
1994 | static uint64_t |
1995 | insert_off_spe2 (uint64_t insn, | |
1996 | int64_t value, | |
74081948 AF |
1997 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1998 | const char **errmsg) | |
1999 | { | |
71553718 AM |
2000 | if (value <= 0 || value > 0x7) |
2001 | *errmsg = _("invalid offset"); | |
2002 | return insn | (value & 0x7); | |
74081948 AF |
2003 | } |
2004 | ||
0f873fd5 PB |
2005 | static int64_t |
2006 | extract_off_spe2 (uint64_t insn, | |
74081948 AF |
2007 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2008 | int *invalid) | |
2009 | { | |
0f873fd5 | 2010 | int64_t value = (insn & 0x7); |
74081948 AF |
2011 | if (value == 0) |
2012 | *invalid = 1; | |
2013 | ||
2014 | return value; | |
2015 | } | |
2016 | ||
0f873fd5 PB |
2017 | static uint64_t |
2018 | insert_Ddd (uint64_t insn, | |
2019 | int64_t value, | |
74081948 AF |
2020 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2021 | const char **errmsg) | |
2022 | { | |
71553718 AM |
2023 | if (value < 0 || value > 0x7) |
2024 | *errmsg = _("invalid Ddd value"); | |
2025 | return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2); | |
74081948 AF |
2026 | } |
2027 | ||
0f873fd5 PB |
2028 | static int64_t |
2029 | extract_Ddd (uint64_t insn, | |
74081948 AF |
2030 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2031 | int *invalid ATTRIBUTE_UNUSED) | |
2032 | { | |
2033 | return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4); | |
2034 | } | |
9cf7e568 AM |
2035 | |
2036 | static uint64_t | |
2037 | insert_sxl (uint64_t insn, | |
2038 | int64_t value, | |
2039 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2040 | const char **errmsg ATTRIBUTE_UNUSED) | |
2041 | { | |
2042 | return insn | ((value & 0x1) << 11); | |
2043 | } | |
2044 | ||
2045 | static int64_t | |
2046 | extract_sxl (uint64_t insn, | |
2047 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
2048 | int *invalid) | |
2049 | { | |
8acf1435 | 2050 | /* Missing optional operands have a value of one. */ |
9cf7e568 AM |
2051 | if (*invalid < 0) |
2052 | return 1; | |
2053 | return (insn >> 11) & 0x1; | |
2054 | } | |
b80c7270 AM |
2055 | \f |
2056 | /* The operands table. | |
a680de9a | 2057 | |
b80c7270 | 2058 | The fields are bitm, shift, insert, extract, flags. |
2fbfdc41 | 2059 | |
b80c7270 AM |
2060 | We used to put parens around the various additions, like the one |
2061 | for BA just below. However, that caused trouble with feeble | |
2062 | compilers with a limit on depth of a parenthesized expression, like | |
2063 | (reportedly) the compiler in Microsoft Developer Studio 5. So we | |
2064 | omit the parens, since the macros are never used in a context where | |
2065 | the addition will be ambiguous. */ | |
2066 | ||
2067 | const struct powerpc_operand powerpc_operands[] = | |
c168870a | 2068 | { |
b80c7270 AM |
2069 | /* The zero index is used to indicate the end of the list of |
2070 | operands. */ | |
2071 | #define UNUSED 0 | |
2072 | { 0, 0, NULL, NULL, 0 }, | |
2073 | ||
2074 | /* The BA field in an XL form instruction. */ | |
2075 | #define BA UNUSED + 1 | |
2076 | /* The BI field in a B form or XL form instruction. */ | |
2077 | #define BI BA | |
2078 | #define BI_MASK (0x1f << 16) | |
2079 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
2080 | ||
98553ad3 PB |
2081 | /* The BT, BA and BB fields in a XL form instruction when they must all |
2082 | be the same. */ | |
2083 | #define BTAB BA + 1 | |
2084 | { 0x1f, 21, insert_btab, extract_btab, PPC_OPERAND_CR_BIT }, | |
b80c7270 AM |
2085 | |
2086 | /* The BB field in an XL form instruction. */ | |
98553ad3 | 2087 | #define BB BTAB + 1 |
b80c7270 AM |
2088 | #define BB_MASK (0x1f << 11) |
2089 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
2090 | ||
98553ad3 PB |
2091 | /* The BA and BB fields in a XL form instruction when they must be |
2092 | the same. */ | |
2093 | #define BAB BB + 1 | |
2094 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_CR_BIT }, | |
2095 | ||
2096 | /* The VRA and VRB fields in a VX form instruction when they must be the same. | |
2097 | This is used for extended mnemonics like vmr. */ | |
2098 | #define VAB BAB + 1 | |
2099 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_VR }, | |
2100 | ||
2101 | /* The RA and RB fields in a VX form instruction when they must be the same. | |
2102 | This is used for extended mnemonics like evmr. */ | |
2103 | #define RAB VAB + 1 | |
2104 | { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_GPR }, | |
b80c7270 AM |
2105 | |
2106 | /* The BD field in a B form instruction. The lower two bits are | |
2107 | forced to zero. */ | |
98553ad3 | 2108 | #define BD RAB + 1 |
b80c7270 AM |
2109 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
2110 | ||
2111 | /* The BD field in a B form instruction when absolute addressing is | |
2112 | used. */ | |
2113 | #define BDA BD + 1 | |
2114 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
2115 | ||
2116 | /* The BD field in a B form instruction when the - modifier is used. | |
2117 | This sets the y bit of the BO field appropriately. */ | |
2118 | #define BDM BDA + 1 | |
2119 | { 0xfffc, 0, insert_bdm, extract_bdm, | |
2120 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
2121 | ||
2122 | /* The BD field in a B form instruction when the - modifier is used | |
2123 | and absolute address is used. */ | |
2124 | #define BDMA BDM + 1 | |
2125 | { 0xfffc, 0, insert_bdm, extract_bdm, | |
2126 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
2127 | ||
2128 | /* The BD field in a B form instruction when the + modifier is used. | |
2129 | This sets the y bit of the BO field appropriately. */ | |
2130 | #define BDP BDMA + 1 | |
2131 | { 0xfffc, 0, insert_bdp, extract_bdp, | |
2132 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
2133 | ||
2134 | /* The BD field in a B form instruction when the + modifier is used | |
2135 | and absolute addressing is used. */ | |
2136 | #define BDPA BDP + 1 | |
2137 | { 0xfffc, 0, insert_bdp, extract_bdp, | |
2138 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
2139 | ||
2140 | /* The BF field in an X or XL form instruction. */ | |
2141 | #define BF BDPA + 1 | |
2142 | /* The CRFD field in an X form instruction. */ | |
2143 | #define CRFD BF | |
2144 | /* The CRD field in an XL form instruction. */ | |
2145 | #define CRD BF | |
2146 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, | |
2147 | ||
2148 | /* The BF field in an X or XL form instruction. */ | |
2149 | #define BFF BF + 1 | |
2150 | { 0x7, 23, NULL, NULL, 0 }, | |
2151 | ||
aa3c112f AM |
2152 | /* The ACC field in a VSX ACC 8LS:D-form instruction. */ |
2153 | #define ACC BFF + 1 | |
2154 | { 0x7, 23, NULL, NULL, PPC_OPERAND_ACC }, | |
2155 | ||
b80c7270 AM |
2156 | /* An optional BF field. This is used for comparison instructions, |
2157 | in which an omitted BF field is taken as zero. */ | |
aa3c112f | 2158 | #define OBF ACC + 1 |
b80c7270 AM |
2159 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
2160 | ||
2161 | /* The BFA field in an X or XL form instruction. */ | |
2162 | #define BFA OBF + 1 | |
2163 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, | |
2164 | ||
2165 | /* The BO field in a B form instruction. Certain values are | |
2166 | illegal. */ | |
2167 | #define BO BFA + 1 | |
2168 | #define BO_MASK (0x1f << 21) | |
2169 | { 0x1f, 21, insert_bo, extract_bo, 0 }, | |
2170 | ||
aae9718e PB |
2171 | /* The BO field in a B form instruction when the - modifier is used. */ |
2172 | #define BOM BO + 1 | |
2173 | { 0x1f, 21, insert_bom, extract_bom, 0 }, | |
2174 | ||
2175 | /* The BO field in a B form instruction when the + modifier is used. */ | |
2176 | #define BOP BOM + 1 | |
2177 | { 0x1f, 21, insert_bop, extract_bop, 0 }, | |
b80c7270 AM |
2178 | |
2179 | /* The RM field in an X form instruction. */ | |
aae9718e | 2180 | #define RM BOP + 1 |
74081948 | 2181 | #define DD RM |
b80c7270 AM |
2182 | { 0x3, 11, NULL, NULL, 0 }, |
2183 | ||
2184 | #define BH RM + 1 | |
2185 | { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
2186 | ||
2187 | /* The BT field in an X or XL form instruction. */ | |
2188 | #define BT BH + 1 | |
2189 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
2190 | ||
96a86c01 AM |
2191 | /* The BT field in a mtfsb0 or mtfsb1 instruction. */ |
2192 | #define BTF BT + 1 | |
2193 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG }, | |
2194 | ||
b80c7270 | 2195 | /* The BI16 field in a BD8 form instruction. */ |
96a86c01 | 2196 | #define BI16 BTF + 1 |
b80c7270 AM |
2197 | { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, |
2198 | ||
2199 | /* The BI32 field in a BD15 form instruction. */ | |
2200 | #define BI32 BI16 + 1 | |
2201 | { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, | |
98e69875 | 2202 | |
b80c7270 AM |
2203 | /* The BO32 field in a BD15 form instruction. */ |
2204 | #define BO32 BI32 + 1 | |
2205 | { 0x3, 20, NULL, NULL, 0 }, | |
c168870a | 2206 | |
b80c7270 AM |
2207 | /* The B8 field in a BD8 form instruction. */ |
2208 | #define B8 BO32 + 1 | |
2209 | { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 2210 | |
b80c7270 AM |
2211 | /* The B15 field in a BD15 form instruction. The lowest bit is |
2212 | forced to zero. */ | |
2213 | #define B15 B8 + 1 | |
2214 | { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 2215 | |
b80c7270 AM |
2216 | /* The B24 field in a BD24 form instruction. The lowest bit is |
2217 | forced to zero. */ | |
2218 | #define B24 B15 + 1 | |
2219 | { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
c168870a | 2220 | |
b80c7270 AM |
2221 | /* The condition register number portion of the BI field in a B form |
2222 | or XL form instruction. This is used for the extended | |
2223 | conditional branch mnemonics, which set the lower two bits of the | |
2224 | BI field. This field is optional. */ | |
2225 | #define CR B24 + 1 | |
2226 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
c168870a | 2227 | |
b80c7270 AM |
2228 | /* The CRB field in an X form instruction. */ |
2229 | #define CRB CR + 1 | |
2230 | /* The MB field in an M form instruction. */ | |
2231 | #define MB CRB | |
2232 | #define MB_MASK (0x1f << 6) | |
2233 | { 0x1f, 6, NULL, NULL, 0 }, | |
c168870a | 2234 | |
b80c7270 AM |
2235 | /* The CRD32 field in an XL form instruction. */ |
2236 | #define CRD32 CRB + 1 | |
2237 | { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, | |
c168870a | 2238 | |
b80c7270 AM |
2239 | /* The CRFS field in an X form instruction. */ |
2240 | #define CRFS CRD32 + 1 | |
2241 | { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, | |
b9c361e0 | 2242 | |
b80c7270 AM |
2243 | #define CRS CRFS + 1 |
2244 | { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2245 | |
b80c7270 AM |
2246 | /* The CT field in an X form instruction. */ |
2247 | #define CT CRS + 1 | |
2248 | /* The MO field in an mbar instruction. */ | |
2249 | #define MO CT | |
2250 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2251 | |
b80c7270 AM |
2252 | /* The D field in a D form instruction. This is a displacement off |
2253 | a register, and implies that the next operand is a register in | |
2254 | parentheses. */ | |
2255 | #define D CT + 1 | |
2256 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
aea77599 | 2257 | |
b80c7270 AM |
2258 | /* The D8 field in a D form instruction. This is a displacement off |
2259 | a register, and implies that the next operand is a register in | |
2260 | parentheses. */ | |
2261 | #define D8 D + 1 | |
2262 | { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
7b934113 | 2263 | |
b80c7270 AM |
2264 | /* The DCMX field in an X form instruction. */ |
2265 | #define DCMX D8 + 1 | |
2266 | { 0x7f, 16, NULL, NULL, 0 }, | |
7b934113 | 2267 | |
b80c7270 AM |
2268 | /* The split DCMX field in an X form instruction. */ |
2269 | #define DCMXS DCMX + 1 | |
2270 | { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, | |
73f07bff | 2271 | |
b80c7270 AM |
2272 | /* The DQ field in a DQ form instruction. This is like D, but the |
2273 | lower four bits are forced to zero. */ | |
2274 | #define DQ DCMXS + 1 | |
2275 | { 0xfff0, 0, NULL, NULL, | |
2276 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, | |
73f07bff | 2277 | |
b80c7270 AM |
2278 | /* The DS field in a DS form instruction. This is like D, but the |
2279 | lower two bits are forced to zero. */ | |
2280 | #define DS DQ + 1 | |
2281 | { 0xfffc, 0, NULL, NULL, | |
2282 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, | |
7b934113 | 2283 | |
8acf1435 PB |
2284 | /* The D field in an 8-byte D form prefix instruction. This is a displacement |
2285 | off a register, and implies that the next operand is a register in | |
2286 | parentheses. */ | |
2287 | #define D34 DS + 1 | |
0e62b37a | 2288 | { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, |
8acf1435 PB |
2289 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
2290 | ||
2291 | /* The SI field in an 8-byte D form prefix instruction. */ | |
2292 | #define SI34 D34 + 1 | |
0e62b37a | 2293 | { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, PPC_OPERAND_SIGNED }, |
8acf1435 PB |
2294 | |
2295 | /* The NSI field in an 8-byte D form prefix instruction. This is the | |
2296 | same as the SI34 field, only negated. */ | |
2297 | #define NSI34 SI34 + 1 | |
0e62b37a | 2298 | { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34, |
8acf1435 PB |
2299 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
2300 | ||
6edbfd3b AM |
2301 | /* The IMM32 field in a vector splat immediate prefix instruction. */ |
2302 | #define IMM32 NSI34 + 1 | |
2303 | { 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0}, | |
2304 | ||
2305 | /* The UIM field in a vector permute extended prefix instruction. */ | |
2306 | #define UIM3 IMM32 + 1 | |
2307 | { 0x7, 32, NULL, NULL, 0}, | |
2308 | ||
ec40e91c AM |
2309 | /* The UIM field in a vector eval prefix instruction. */ |
2310 | #define UIM8 UIM3 + 1 | |
2311 | { 0xff, 32, NULL, NULL, 0}, | |
2312 | ||
6edbfd3b | 2313 | /* The IX field in xxsplti32dx. */ |
ec40e91c | 2314 | #define IX UIM8 + 1 |
6edbfd3b AM |
2315 | { 0x1, 17, NULL, NULL, 0 }, |
2316 | ||
aa3c112f AM |
2317 | /* The PMSK field in GER rank 8 prefix instructions. */ |
2318 | #define PMSK8 IX + 1 | |
2319 | { 0xff, 40, NULL, NULL, 0 }, | |
2320 | ||
2321 | /* The PMSK field in GER rank 4 prefix instructions. */ | |
2322 | #define PMSK4 PMSK8 + 1 | |
2323 | { 0xf, 44, NULL, NULL, 0 }, | |
2324 | ||
2325 | /* The PMSK field in GER rank 2 prefix instructions. */ | |
2326 | #define PMSK2 PMSK4 + 1 | |
2327 | { 0x3, 46, NULL, NULL, 0 }, | |
2328 | ||
2329 | /* The XMSK field in GER prefix instructions. */ | |
2330 | #define XMSK PMSK2 + 1 | |
2331 | { 0xf, 36, NULL, NULL, 0 }, | |
2332 | ||
2333 | /* The YMSK field in GER prefix instructions. */ | |
2334 | #define YMSK XMSK + 1 | |
2335 | { 0xf, 32, NULL, NULL, 0 }, | |
2336 | ||
2337 | /* The YMSK field in 64-bit GER prefix instructions. */ | |
2338 | #define YMSK2 YMSK + 1 | |
2339 | { 0x3, 34, NULL, NULL, 0 }, | |
2340 | ||
b80c7270 AM |
2341 | /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits |
2342 | unsigned imediate */ | |
aa3c112f | 2343 | #define DUIS YMSK2 + 1 |
b80c7270 AM |
2344 | #define BHRBE DUIS |
2345 | { 0x3ff, 11, NULL, NULL, 0 }, | |
aea77599 | 2346 | |
b80c7270 AM |
2347 | /* The split D field in a DX form instruction. */ |
2348 | #define DXD DUIS + 1 | |
2349 | { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, | |
2350 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, | |
7b934113 | 2351 | |
b80c7270 AM |
2352 | /* The split ND field in a DX form instruction. |
2353 | This is the same as the DX field, only negated. */ | |
2354 | #define NDXD DXD + 1 | |
2355 | { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, | |
2356 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, | |
7b934113 | 2357 | |
b80c7270 AM |
2358 | /* The E field in a wrteei instruction. */ |
2359 | /* And the W bit in the pair singles instructions. */ | |
2360 | /* And the ST field in a VX form instruction. */ | |
2361 | #define E NDXD + 1 | |
2362 | #define PSW E | |
2363 | #define ST E | |
2364 | { 0x1, 15, NULL, NULL, 0 }, | |
aea77599 | 2365 | |
b80c7270 AM |
2366 | /* The FL1 field in a POWER SC form instruction. */ |
2367 | #define FL1 E + 1 | |
2368 | /* The U field in an X form instruction. */ | |
2369 | #define U FL1 | |
2370 | { 0xf, 12, NULL, NULL, 0 }, | |
73f07bff | 2371 | |
b80c7270 AM |
2372 | /* The FL2 field in a POWER SC form instruction. */ |
2373 | #define FL2 FL1 + 1 | |
2374 | { 0x7, 2, NULL, NULL, 0 }, | |
73f07bff | 2375 | |
b80c7270 AM |
2376 | /* The FLM field in an XFL form instruction. */ |
2377 | #define FLM FL2 + 1 | |
2378 | { 0xff, 17, NULL, NULL, 0 }, | |
73f07bff | 2379 | |
b80c7270 AM |
2380 | /* The FRA field in an X or A form instruction. */ |
2381 | #define FRA FLM + 1 | |
2382 | #define FRA_MASK (0x1f << 16) | |
2383 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2384 | |
b80c7270 AM |
2385 | /* The FRAp field of DFP instructions. */ |
2386 | #define FRAp FRA + 1 | |
2387 | { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2388 | |
b80c7270 AM |
2389 | /* The FRB field in an X or A form instruction. */ |
2390 | #define FRB FRAp + 1 | |
2391 | #define FRB_MASK (0x1f << 11) | |
2392 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, | |
2393 | ||
2394 | /* The FRBp field of DFP instructions. */ | |
2395 | #define FRBp FRB + 1 | |
2396 | { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2397 | |
b80c7270 AM |
2398 | /* The FRC field in an A form instruction. */ |
2399 | #define FRC FRBp + 1 | |
2400 | #define FRC_MASK (0x1f << 6) | |
2401 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2402 | |
b80c7270 AM |
2403 | /* The FRS field in an X form instruction or the FRT field in a D, X |
2404 | or A form instruction. */ | |
2405 | #define FRS FRC + 1 | |
2406 | #define FRT FRS | |
2407 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2408 | |
b80c7270 AM |
2409 | /* The FRSp field of stfdp or the FRTp field of lfdp and DFP |
2410 | instructions. */ | |
2411 | #define FRSp FRS + 1 | |
2412 | #define FRTp FRSp | |
2413 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, | |
252b5132 | 2414 | |
b80c7270 AM |
2415 | /* The FXM field in an XFX instruction. */ |
2416 | #define FXM FRSp + 1 | |
2417 | { 0xff, 12, insert_fxm, extract_fxm, 0 }, | |
252b5132 | 2418 | |
b80c7270 AM |
2419 | /* Power4 version for mfcr. */ |
2420 | #define FXM4 FXM + 1 | |
9cf7e568 | 2421 | { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, |
252b5132 | 2422 | |
b80c7270 | 2423 | /* The IMM20 field in an LI instruction. */ |
9cf7e568 | 2424 | #define IMM20 FXM4 + 1 |
b80c7270 | 2425 | { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, |
252b5132 | 2426 | |
b80c7270 AM |
2427 | /* The L field in a D or X form instruction. */ |
2428 | #define L IMM20 + 1 | |
2429 | { 0x1, 21, NULL, NULL, 0 }, | |
252b5132 | 2430 | |
b80c7270 AM |
2431 | /* The optional L field in tlbie and tlbiel instructions. */ |
2432 | #define LOPT L + 1 | |
2433 | /* The R field in a HTM X form instruction. */ | |
2434 | #define HTM_R LOPT | |
2435 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2436 | |
afef4fe9 PB |
2437 | /* The optional L field in the paste. instruction. This is similar to LOPT |
2438 | above, but with a default value of 1. */ | |
2439 | #define L1OPT LOPT + 1 | |
2440 | { 0x1, 21, insert_l1opt, extract_l1opt, PPC_OPERAND_OPTIONAL }, | |
2441 | ||
b80c7270 | 2442 | /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ |
afef4fe9 | 2443 | #define L32OPT L1OPT + 1 |
b80c7270 | 2444 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, |
252b5132 | 2445 | |
b80c7270 AM |
2446 | /* The L field in dcbf instruction. */ |
2447 | #define L2OPT L32OPT + 1 | |
2448 | { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2449 | |
b80c7270 AM |
2450 | /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ |
2451 | #define SVC_LEV L2OPT + 1 | |
2452 | { 0x7f, 5, NULL, NULL, 0 }, | |
252b5132 | 2453 | |
b80c7270 AM |
2454 | /* The LEV field in an SC form instruction. */ |
2455 | #define LEV SVC_LEV + 1 | |
2456 | { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2457 | |
b80c7270 AM |
2458 | /* The LI field in an I form instruction. The lower two bits are |
2459 | forced to zero. */ | |
2460 | #define LI LEV + 1 | |
2461 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2462 | |
b80c7270 AM |
2463 | /* The LI field in an I form instruction when used as an absolute |
2464 | address. */ | |
2465 | #define LIA LI + 1 | |
2466 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2467 | |
b80c7270 AM |
2468 | /* The LS or WC field in an X (sync or wait) form instruction. */ |
2469 | #define LS LIA + 1 | |
2470 | #define WC LS | |
2471 | { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2472 | |
b80c7270 AM |
2473 | /* The ME field in an M form instruction. */ |
2474 | #define ME LS + 1 | |
2475 | #define ME_MASK (0x1f << 1) | |
2476 | { 0x1f, 1, NULL, NULL, 0 }, | |
989993d8 | 2477 | |
b80c7270 AM |
2478 | /* The MB and ME fields in an M form instruction expressed a single |
2479 | operand which is a bitmask indicating which bits to select. This | |
2480 | is a two operand form using PPC_OPERAND_NEXT. See the | |
2481 | description in opcode/ppc.h for what this means. */ | |
2482 | #define MBE ME + 1 | |
2483 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, | |
2484 | { -1, 0, insert_mbe, extract_mbe, 0 }, | |
989993d8 | 2485 | |
b80c7270 AM |
2486 | /* The MB or ME field in an MD or MDS form instruction. The high |
2487 | bit is wrapped to the low end. */ | |
2488 | #define MB6 MBE + 2 | |
2489 | #define ME6 MB6 | |
2490 | #define MB6_MASK (0x3f << 5) | |
2491 | { 0x3f, 5, insert_mb6, extract_mb6, 0 }, | |
989993d8 | 2492 | |
b80c7270 AM |
2493 | /* The NB field in an X form instruction. The value 32 is stored as |
2494 | 0. */ | |
2495 | #define NB MB6 + 1 | |
2496 | { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, | |
252b5132 | 2497 | |
b80c7270 AM |
2498 | /* The NBI field in an lswi instruction, which has special value |
2499 | restrictions. The value 32 is stored as 0. */ | |
2500 | #define NBI NB + 1 | |
2501 | { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, | |
252b5132 | 2502 | |
b80c7270 AM |
2503 | /* The NSI field in a D form instruction. This is the same as the |
2504 | SI field, only negated. */ | |
2505 | #define NSI NBI + 1 | |
2506 | { 0xffff, 0, insert_nsi, extract_nsi, | |
2507 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, | |
252b5132 | 2508 | |
b80c7270 AM |
2509 | /* The NSI field in a D form instruction when we accept a wide range |
2510 | of positive values. */ | |
2511 | #define NSISIGNOPT NSI + 1 | |
2512 | { 0xffff, 0, insert_nsi, extract_nsi, | |
2513 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
252b5132 | 2514 | |
b80c7270 AM |
2515 | /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
2516 | #define RA NSISIGNOPT + 1 | |
2517 | #define RA_MASK (0x1f << 16) | |
2518 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, | |
252b5132 | 2519 | |
b80c7270 AM |
2520 | /* As above, but 0 in the RA field means zero, not r0. */ |
2521 | #define RA0 RA + 1 | |
2522 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2523 | |
8acf1435 PB |
2524 | /* Similar to above, but optional. */ |
2525 | #define PRA0 RA0 + 1 | |
2526 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL }, | |
2527 | ||
b80c7270 AM |
2528 | /* The RA field in the DQ form lq or an lswx instruction, which have |
2529 | special value restrictions. */ | |
8acf1435 | 2530 | #define RAQ PRA0 + 1 |
b80c7270 AM |
2531 | #define RAX RAQ |
2532 | { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2533 | |
8acf1435 PB |
2534 | /* Similar to above, but optional. */ |
2535 | #define PRAQ RAQ + 1 | |
2536 | { 0x1f, 16, insert_raq, extract_raq, | |
2537 | PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL }, | |
2538 | ||
2539 | /* The R field in an 8-byte D, DS, DQ or X form prefix instruction. */ | |
2540 | #define PCREL PRAQ + 1 | |
2541 | #define PCREL_MASK (1ULL << 52) | |
2542 | { 0x1, 52, insert_pcrel, extract_pcrel, PPC_OPERAND_OPTIONAL }, | |
2543 | ||
2544 | #define PCREL0 PCREL + 1 | |
2545 | { 0x1, 52, insert_pcrel, extract_pcrel0, PPC_OPERAND_OPTIONAL }, | |
2546 | ||
b80c7270 AM |
2547 | /* The RA field in a D or X form instruction which is an updating |
2548 | load, which means that the RA field may not be zero and may not | |
2549 | equal the RT field. */ | |
8acf1435 | 2550 | #define RAL PCREL0 + 1 |
b80c7270 | 2551 | { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 }, |
252b5132 | 2552 | |
b80c7270 AM |
2553 | /* The RA field in an lmw instruction, which has special value |
2554 | restrictions. */ | |
2555 | #define RAM RAL + 1 | |
2556 | { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 }, | |
252b5132 | 2557 | |
b80c7270 AM |
2558 | /* The RA field in a D or X form instruction which is an updating |
2559 | store or an updating floating point load, which means that the RA | |
2560 | field may not be zero. */ | |
2561 | #define RAS RAM + 1 | |
2562 | { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 }, | |
73f07bff | 2563 | |
b80c7270 AM |
2564 | /* The RA field of the tlbwe, dccci and iccci instructions, |
2565 | which are optional. */ | |
2566 | #define RAOPT RAS + 1 | |
2567 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2568 | |
b80c7270 AM |
2569 | /* The RB field in an X, XO, M, or MDS form instruction. */ |
2570 | #define RB RAOPT + 1 | |
2571 | #define RB_MASK (0x1f << 11) | |
2572 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, | |
adadcc0c | 2573 | |
98553ad3 PB |
2574 | /* The RS and RB fields in an X form instruction when they must be the same. |
2575 | This is used for extended mnemonics like mr. */ | |
2576 | #define RSB RB + 1 | |
2577 | { 0x1f, 11, insert_rsb, extract_rsb, PPC_OPERAND_GPR }, | |
adadcc0c | 2578 | |
b80c7270 AM |
2579 | /* The RB field in an lswx instruction, which has special value |
2580 | restrictions. */ | |
98553ad3 | 2581 | #define RBX RSB + 1 |
b80c7270 | 2582 | { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR }, |
adadcc0c | 2583 | |
b80c7270 AM |
2584 | /* The RB field of the dccci and iccci instructions, which are optional. */ |
2585 | #define RBOPT RBX + 1 | |
2586 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2587 | |
b80c7270 AM |
2588 | /* The RC register field in an maddld, maddhd or maddhdu instruction. */ |
2589 | #define RC RBOPT + 1 | |
2590 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, | |
73f07bff | 2591 | |
b80c7270 AM |
2592 | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
2593 | instruction or the RT field in a D, DS, X, XFX or XO form | |
2594 | instruction. */ | |
2595 | #define RS RC + 1 | |
2596 | #define RT RS | |
2597 | #define RT_MASK (0x1f << 21) | |
2598 | #define RD RS | |
2599 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, | |
252b5132 | 2600 | |
b80c7270 AM |
2601 | #define RD_EVEN RS + 1 |
2602 | #define RS_EVEN RD_EVEN | |
2603 | { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR }, | |
252b5132 | 2604 | |
b80c7270 AM |
2605 | /* The RS and RT fields of the DS form stq and DQ form lq instructions, |
2606 | which have special value restrictions. */ | |
2607 | #define RSQ RS_EVEN + 1 | |
2608 | #define RTQ RSQ | |
2609 | #define Q_MASK (1 << 21) | |
2610 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, | |
73f07bff | 2611 | |
b80c7270 AM |
2612 | /* The RS field of the tlbwe instruction, which is optional. */ |
2613 | #define RSO RSQ + 1 | |
2614 | #define RTO RSO | |
2615 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, | |
73f07bff | 2616 | |
b80c7270 AM |
2617 | /* The RX field of the SE_RR form instruction. */ |
2618 | #define RX RSO + 1 | |
2619 | { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, | |
252b5132 | 2620 | |
b80c7270 AM |
2621 | /* The ARX field of the SE_RR form instruction. */ |
2622 | #define ARX RX + 1 | |
2623 | { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, | |
252b5132 | 2624 | |
b80c7270 AM |
2625 | /* The RY field of the SE_RR form instruction. */ |
2626 | #define RY ARX + 1 | |
2627 | #define RZ RY | |
2628 | { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, | |
252b5132 | 2629 | |
b80c7270 AM |
2630 | /* The ARY field of the SE_RR form instruction. */ |
2631 | #define ARY RY + 1 | |
2632 | { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, | |
989993d8 | 2633 | |
b80c7270 AM |
2634 | /* The SCLSCI8 field in a D form instruction. */ |
2635 | #define SCLSCI8 ARY + 1 | |
2636 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, | |
989993d8 | 2637 | |
b80c7270 AM |
2638 | /* The SCLSCI8N field in a D form instruction. This is the same as the |
2639 | SCLSCI8 field, only negated. */ | |
2640 | #define SCLSCI8N SCLSCI8 + 1 | |
2641 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, | |
2642 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, | |
989993d8 | 2643 | |
b80c7270 AM |
2644 | /* The SD field of the SD4 form instruction. */ |
2645 | #define SE_SD SCLSCI8N + 1 | |
2646 | { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, | |
73f07bff | 2647 | |
b80c7270 AM |
2648 | /* The SD field of the SD4 form instruction, for halfword. */ |
2649 | #define SE_SDH SE_SD + 1 | |
71553718 | 2650 | { 0x1e, 7, NULL, NULL, PPC_OPERAND_PARENS }, |
73f07bff | 2651 | |
b80c7270 AM |
2652 | /* The SD field of the SD4 form instruction, for word. */ |
2653 | #define SE_SDW SE_SDH + 1 | |
71553718 | 2654 | { 0x3c, 6, NULL, NULL, PPC_OPERAND_PARENS }, |
b9c361e0 | 2655 | |
b80c7270 AM |
2656 | /* The SH field in an X or M form instruction. */ |
2657 | #define SH SE_SDW + 1 | |
2658 | #define SH_MASK (0x1f << 11) | |
2659 | /* The other UIMM field in a EVX form instruction. */ | |
2660 | #define EVUIMM SH | |
2661 | /* The FC field in an atomic X form instruction. */ | |
2662 | #define FC SH | |
6edbfd3b | 2663 | #define UIM5 SH |
b80c7270 | 2664 | { 0x1f, 11, NULL, NULL, 0 }, |
b9c361e0 | 2665 | |
74081948 AF |
2666 | #define EVUIMM_LT8 SH + 1 |
2667 | { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 }, | |
2668 | ||
2669 | #define EVUIMM_LT16 EVUIMM_LT8 + 1 | |
b80c7270 | 2670 | { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 }, |
b9c361e0 | 2671 | |
b80c7270 AM |
2672 | /* The SI field in a HTM X form instruction. */ |
2673 | #define HTM_SI EVUIMM_LT16 + 1 | |
2674 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, | |
943d398f | 2675 | |
b80c7270 AM |
2676 | /* The SH field in an MD form instruction. This is split. */ |
2677 | #define SH6 HTM_SI + 1 | |
2678 | #define SH6_MASK ((0x1f << 11) | (1 << 1)) | |
2679 | { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, | |
b9c361e0 | 2680 | |
b80c7270 AM |
2681 | /* The SH field of some variants of the tlbre and tlbwe |
2682 | instructions, and the ELEV field of the e_sc instruction. */ | |
2683 | #define SHO SH6 + 1 | |
2684 | #define ELEV SHO | |
2685 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2686 | |
b80c7270 AM |
2687 | /* The SI field in a D form instruction. */ |
2688 | #define SI SHO + 1 | |
2689 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, | |
b9c361e0 | 2690 | |
b80c7270 AM |
2691 | /* The SI field in a D form instruction when we accept a wide range |
2692 | of positive values. */ | |
2693 | #define SISIGNOPT SI + 1 | |
2694 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
b9c361e0 | 2695 | |
b80c7270 AM |
2696 | /* The SI8 field in a D form instruction. */ |
2697 | #define SI8 SISIGNOPT + 1 | |
2698 | { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, | |
b9c361e0 | 2699 | |
b80c7270 AM |
2700 | /* The SPR field in an XFX form instruction. This is flipped--the |
2701 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
2702 | #define SPR SI8 + 1 | |
2703 | #define PMR SPR | |
2704 | #define TMR SPR | |
2705 | #define SPR_MASK (0x3ff << 11) | |
2706 | { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR }, | |
b9c361e0 | 2707 | |
b80c7270 AM |
2708 | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ |
2709 | #define SPRBAT SPR + 1 | |
fa758a70 AC |
2710 | #define SPRBAT_MASK (0xc1 << 11) |
2711 | { 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR }, | |
2712 | ||
2713 | /* The GQR index number in an XFX form m[ft]gqr instruction. */ | |
2714 | #define SPRGQR SPRBAT + 1 | |
2715 | #define SPRGQR_MASK (0x7 << 16) | |
2716 | { 0x7, 16, NULL, NULL, PPC_OPERAND_GQR }, | |
b9c361e0 | 2717 | |
b80c7270 | 2718 | /* The SPRG register number in an XFX form m[ft]sprg instruction. */ |
fa758a70 | 2719 | #define SPRG SPRGQR + 1 |
b80c7270 | 2720 | { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, |
b9c361e0 | 2721 | |
b80c7270 AM |
2722 | /* The SR field in an X form instruction. */ |
2723 | #define SR SPRG + 1 | |
2724 | /* The 4-bit UIMM field in a VX form instruction. */ | |
2725 | #define UIMM4 SR | |
2726 | { 0xf, 16, NULL, NULL, 0 }, | |
b9c361e0 | 2727 | |
b80c7270 AM |
2728 | /* The STRM field in an X AltiVec form instruction. */ |
2729 | #define STRM SR + 1 | |
2730 | /* The T field in a tlbilx form instruction. */ | |
2731 | #define T STRM | |
2732 | /* The L field in wclr instructions. */ | |
2733 | #define L2 STRM | |
2734 | { 0x3, 21, NULL, NULL, 0 }, | |
252b5132 | 2735 | |
b80c7270 AM |
2736 | /* The ESYNC field in an X (sync) form instruction. */ |
2737 | #define ESYNC STRM + 1 | |
2738 | { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL }, | |
252b5132 | 2739 | |
b80c7270 AM |
2740 | /* The SV field in a POWER SC form instruction. */ |
2741 | #define SV ESYNC + 1 | |
2742 | { 0x3fff, 2, NULL, NULL, 0 }, | |
252b5132 | 2743 | |
b80c7270 AM |
2744 | /* The TBR field in an XFX form instruction. This is like the SPR |
2745 | field, but it is optional. */ | |
2746 | #define TBR SV + 1 | |
2747 | { 0x3ff, 11, insert_tbr, extract_tbr, | |
9cf7e568 | 2748 | PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL }, |
252b5132 | 2749 | |
b80c7270 | 2750 | /* The TO field in a D or X form instruction. */ |
9cf7e568 | 2751 | #define TO TBR + 1 |
b80c7270 AM |
2752 | #define DUI TO |
2753 | #define TO_MASK (0x1f << 21) | |
2754 | { 0x1f, 21, NULL, NULL, 0 }, | |
252b5132 | 2755 | |
b80c7270 AM |
2756 | /* The UI field in a D form instruction. */ |
2757 | #define UI TO + 1 | |
2758 | { 0xffff, 0, NULL, NULL, 0 }, | |
252b5132 | 2759 | |
b80c7270 AM |
2760 | #define UISIGNOPT UI + 1 |
2761 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, | |
da99ee72 | 2762 | |
b80c7270 AM |
2763 | /* The IMM field in an SE_IM5 instruction. */ |
2764 | #define UI5 UISIGNOPT + 1 | |
2765 | { 0x1f, 4, NULL, NULL, 0 }, | |
da99ee72 | 2766 | |
b80c7270 AM |
2767 | /* The OIMM field in an SE_OIM5 instruction. */ |
2768 | #define OIMM5 UI5 + 1 | |
71553718 | 2769 | { 0x1f, 4, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, |
da99ee72 | 2770 | |
b80c7270 AM |
2771 | /* The UI7 field in an SE_LI instruction. */ |
2772 | #define UI7 OIMM5 + 1 | |
2773 | { 0x7f, 4, NULL, NULL, 0 }, | |
da99ee72 | 2774 | |
b80c7270 AM |
2775 | /* The VA field in a VA, VX or VXR form instruction. */ |
2776 | #define VA UI7 + 1 | |
2777 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, | |
da99ee72 | 2778 | |
b80c7270 AM |
2779 | /* The VB field in a VA, VX or VXR form instruction. */ |
2780 | #define VB VA + 1 | |
2781 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, | |
da99ee72 | 2782 | |
b80c7270 AM |
2783 | /* The VC field in a VA form instruction. */ |
2784 | #define VC VB + 1 | |
2785 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, | |
252b5132 | 2786 | |
b80c7270 AM |
2787 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
2788 | #define VD VC + 1 | |
2789 | #define VS VD | |
2790 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, | |
252b5132 | 2791 | |
b80c7270 AM |
2792 | /* The SIMM field in a VX form instruction, and TE in Z form. */ |
2793 | #define SIMM VD + 1 | |
2794 | #define TE SIMM | |
2795 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, | |
252b5132 | 2796 | |
b80c7270 AM |
2797 | /* The UIMM field in a VX form instruction. */ |
2798 | #define UIMM SIMM + 1 | |
2799 | #define DCTL UIMM | |
2800 | { 0x1f, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2801 | |
b80c7270 AM |
2802 | /* The 3-bit UIMM field in a VX form instruction. */ |
2803 | #define UIMM3 UIMM + 1 | |
2804 | { 0x7, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2805 | |
b80c7270 AM |
2806 | /* The 6-bit UIM field in a X form instruction. */ |
2807 | #define UIM6 UIMM3 + 1 | |
2808 | { 0x3f, 16, NULL, NULL, 0 }, | |
9b4e5766 | 2809 | |
b80c7270 AM |
2810 | /* The SIX field in a VX form instruction. */ |
2811 | #define SIX UIM6 + 1 | |
74081948 | 2812 | #define MMMM SIX |
b80c7270 | 2813 | { 0xf, 11, NULL, NULL, 0 }, |
9b4e5766 | 2814 | |
b80c7270 AM |
2815 | /* The PS field in a VX form instruction. */ |
2816 | #define PS SIX + 1 | |
2817 | { 0x1, 9, NULL, NULL, 0 }, | |
a680de9a | 2818 | |
6edbfd3b AM |
2819 | /* The SH field in a vector shift double by bit immediate instruction. */ |
2820 | #define SH3 PS + 1 | |
2821 | { 0x7, 6, NULL, NULL, 0 }, | |
2822 | ||
b80c7270 | 2823 | /* The SHB field in a VA form instruction. */ |
6edbfd3b | 2824 | #define SHB SH3 + 1 |
b80c7270 | 2825 | { 0xf, 6, NULL, NULL, 0 }, |
a680de9a | 2826 | |
b80c7270 | 2827 | /* The other UIMM field in a half word EVX form instruction. */ |
74081948 AF |
2828 | #define EVUIMM_1 SHB + 1 |
2829 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS }, | |
2830 | ||
2831 | #define EVUIMM_1_EX0 EVUIMM_1 + 1 | |
2832 | { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS }, | |
2833 | ||
2834 | #define EVUIMM_2 EVUIMM_1_EX0 + 1 | |
b80c7270 | 2835 | { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
9b4e5766 | 2836 | |
b80c7270 AM |
2837 | #define EVUIMM_2_EX0 EVUIMM_2 + 1 |
2838 | { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2839 | |
b80c7270 AM |
2840 | /* The other UIMM field in a word EVX form instruction. */ |
2841 | #define EVUIMM_4 EVUIMM_2_EX0 + 1 | |
2842 | { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2843 | |
b80c7270 AM |
2844 | #define EVUIMM_4_EX0 EVUIMM_4 + 1 |
2845 | { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2846 | |
b80c7270 AM |
2847 | /* The other UIMM field in a double EVX form instruction. */ |
2848 | #define EVUIMM_8 EVUIMM_4_EX0 + 1 | |
2849 | { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2850 | |
b80c7270 AM |
2851 | #define EVUIMM_8_EX0 EVUIMM_8 + 1 |
2852 | { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS }, | |
9b4e5766 | 2853 | |
b80c7270 AM |
2854 | /* The WS or DRM field in an X form instruction. */ |
2855 | #define WS EVUIMM_8_EX0 + 1 | |
2856 | #define DRM WS | |
74081948 AF |
2857 | /* The NNN field in a VX form instruction for SPE2 */ |
2858 | #define NNN WS | |
b80c7270 | 2859 | { 0x7, 11, NULL, NULL, 0 }, |
9b4e5766 | 2860 | |
b80c7270 AM |
2861 | /* PowerPC paired singles extensions. */ |
2862 | /* W bit in the pair singles instructions for x type instructions. */ | |
2863 | #define PSWM WS + 1 | |
2864 | /* The BO16 field in a BD8 form instruction. */ | |
2865 | #define BO16 PSWM | |
2866 | { 0x1, 10, 0, 0, 0 }, | |
9b4e5766 | 2867 | |
b80c7270 AM |
2868 | /* IDX bits for quantization in the pair singles instructions. */ |
2869 | #define PSQ PSWM + 1 | |
2870 | { 0x7, 12, 0, 0, PPC_OPERAND_GQR }, | |
066be9f7 | 2871 | |
b80c7270 AM |
2872 | /* IDX bits for quantization in the pair singles x-type instructions. */ |
2873 | #define PSQM PSQ + 1 | |
2874 | { 0x7, 7, 0, 0, PPC_OPERAND_GQR }, | |
066be9f7 | 2875 | |
b80c7270 AM |
2876 | /* Smaller D field for quantization in the pair singles instructions. */ |
2877 | #define PSD PSQM + 1 | |
2878 | { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
066be9f7 | 2879 | |
b80c7270 AM |
2880 | /* The L field in an mtmsrd or A form instruction or R or W in an |
2881 | X form. */ | |
2882 | #define A_L PSD + 1 | |
2883 | #define W A_L | |
2884 | #define X_R A_L | |
2885 | { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
066be9f7 | 2886 | |
b80c7270 AM |
2887 | /* The RMC or CY field in a Z23 form instruction. */ |
2888 | #define RMC A_L + 1 | |
2889 | #define CY RMC | |
2890 | { 0x3, 9, NULL, NULL, 0 }, | |
066be9f7 | 2891 | |
b80c7270 | 2892 | #define R RMC + 1 |
fdefed7c | 2893 | #define MP R |
b80c7270 | 2894 | { 0x1, 16, NULL, NULL, 0 }, |
066be9f7 | 2895 | |
b80c7270 AM |
2896 | #define RIC R + 1 |
2897 | { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
7b934113 | 2898 | |
b80c7270 AM |
2899 | #define PRS RIC + 1 |
2900 | { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2901 | |
b80c7270 AM |
2902 | #define SP PRS + 1 |
2903 | { 0x3, 19, NULL, NULL, 0 }, | |
b9c361e0 | 2904 | |
b80c7270 AM |
2905 | #define S SP + 1 |
2906 | { 0x1, 20, NULL, NULL, 0 }, | |
b9c361e0 | 2907 | |
b80c7270 AM |
2908 | /* The S field in a XL form instruction. */ |
2909 | #define SXL S + 1 | |
9cf7e568 | 2910 | { 0x1, 11, insert_sxl, extract_sxl, PPC_OPERAND_OPTIONAL }, |
b80c7270 AM |
2911 | |
2912 | /* SH field starting at bit position 16. */ | |
9cf7e568 | 2913 | #define SH16 SXL + 1 |
b80c7270 AM |
2914 | /* The DCM and DGM fields in a Z form instruction. */ |
2915 | #define DCM SH16 | |
2916 | #define DGM DCM | |
2917 | { 0x3f, 10, NULL, NULL, 0 }, | |
2918 | ||
2919 | /* The EH field in larx instruction. */ | |
2920 | #define EH SH16 + 1 | |
2921 | { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
b9c361e0 | 2922 | |
b80c7270 AM |
2923 | /* The L field in an mtfsf or XFL form instruction. */ |
2924 | /* The A field in a HTM X form instruction. */ | |
2925 | #define XFL_L EH + 1 | |
2926 | #define HTM_A XFL_L | |
2927 | { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, | |
b9c361e0 | 2928 | |
b80c7270 AM |
2929 | /* Xilinx APU related masks and macros */ |
2930 | #define FCRT XFL_L + 1 | |
2931 | #define FCRT_MASK (0x1f << 21) | |
2932 | { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, | |
b9c361e0 | 2933 | |
b80c7270 AM |
2934 | /* Xilinx FSL related masks and macros */ |
2935 | #define FSL FCRT + 1 | |
2936 | #define FSL_MASK (0x1f << 11) | |
2937 | { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, | |
b9c361e0 | 2938 | |
b80c7270 AM |
2939 | /* Xilinx UDI related masks and macros */ |
2940 | #define URT FSL + 1 | |
2941 | { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 2942 | |
b80c7270 AM |
2943 | #define URA URT + 1 |
2944 | { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 2945 | |
b80c7270 AM |
2946 | #define URB URA + 1 |
2947 | { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, | |
b9c361e0 | 2948 | |
b80c7270 AM |
2949 | #define URC URB + 1 |
2950 | { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, | |
e3c2f928 | 2951 | |
b80c7270 AM |
2952 | /* The VLESIMM field in a D form instruction. */ |
2953 | #define VLESIMM URC + 1 | |
2954 | { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, | |
2955 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 2956 | |
b80c7270 AM |
2957 | /* The VLENSIMM field in a D form instruction. */ |
2958 | #define VLENSIMM VLESIMM + 1 | |
2959 | { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, | |
2960 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 2961 | |
b80c7270 AM |
2962 | /* The VLEUIMM field in a D form instruction. */ |
2963 | #define VLEUIMM VLENSIMM + 1 | |
2964 | { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, | |
e3c2f928 | 2965 | |
b80c7270 AM |
2966 | /* The VLEUIMML field in a D form instruction. */ |
2967 | #define VLEUIMML VLEUIMM + 1 | |
2968 | { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, | |
e3c2f928 | 2969 | |
b80c7270 AM |
2970 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is |
2971 | split. */ | |
2972 | #define XS6 VLEUIMML + 1 | |
2973 | #define XT6 XS6 | |
2974 | { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, | |
e3c2f928 | 2975 | |
b80c7270 AM |
2976 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
2977 | #define XSQ6 XT6 + 1 | |
2978 | #define XTQ6 XSQ6 | |
2979 | { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, | |
e3c2f928 | 2980 | |
94ba9882 AM |
2981 | /* The split XTp field in a vector paired instruction. */ |
2982 | #define XTP XSQ6 + 1 | |
2983 | { 0x3e, PPC_OPSHIFT_INV, insert_xtp, extract_xtp, PPC_OPERAND_VSR }, | |
2984 | ||
6edbfd3b AM |
2985 | #define XTS XTP + 1 |
2986 | { 0x3f, PPC_OPSHIFT_INV, insert_xts, extract_xts, PPC_OPERAND_VSR }, | |
2987 | ||
8acf1435 | 2988 | /* The XT field in a plxv instruction. Runs into the OP field. */ |
6edbfd3b | 2989 | #define XTOP XTS + 1 |
8acf1435 PB |
2990 | { 0x3f, 21, NULL, NULL, PPC_OPERAND_VSR }, |
2991 | ||
b80c7270 | 2992 | /* The XA field in an XX3 form instruction. This is split. */ |
8acf1435 | 2993 | #define XA6 XTOP + 1 |
b80c7270 | 2994 | { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, |
e3c2f928 | 2995 | |
aa3c112f AM |
2996 | /* The XA field in an MMA XX3 form instruction. This is split and |
2997 | must not overlap with the ACC operand. */ | |
2998 | #define XA6a XA6 + 1 | |
2999 | { 0x3f, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR }, | |
3000 | ||
3001 | /* The XAp field in an MMA XX3 form instruction. This is split. | |
3002 | This is like XA6a, but must be even. */ | |
3003 | #define XA6ap XA6a + 1 | |
3004 | { 0x3e, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR }, | |
3005 | ||
b80c7270 | 3006 | /* The XB field in an XX2 or XX3 form instruction. This is split. */ |
aa3c112f | 3007 | #define XB6 XA6ap + 1 |
b80c7270 | 3008 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, |
e3c2f928 | 3009 | |
aa3c112f AM |
3010 | /* The XB field in an XX3 form instruction. This is split and |
3011 | must not overlap with the ACC operand. */ | |
3012 | #define XB6a XB6 + 1 | |
3013 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6a, extract_xb6a, PPC_OPERAND_VSR }, | |
3014 | ||
98553ad3 PB |
3015 | /* The XA and XB fields in an XX3 form instruction when they must be the same. |
3016 | This is used in extended mnemonics like xvmovdp. This is split. */ | |
aa3c112f | 3017 | #define XAB6 XB6a + 1 |
98553ad3 | 3018 | { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR }, |
e3c2f928 | 3019 | |
b80c7270 | 3020 | /* The XC field in an XX4 form instruction. This is split. */ |
98553ad3 | 3021 | #define XC6 XAB6 + 1 |
b80c7270 | 3022 | { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, |
e3c2f928 | 3023 | |
b80c7270 AM |
3024 | /* The DM or SHW field in an XX3 form instruction. */ |
3025 | #define DM XC6 + 1 | |
3026 | #define SHW DM | |
3027 | { 0x3, 8, NULL, NULL, 0 }, | |
e3c2f928 | 3028 | |
b80c7270 AM |
3029 | /* The DM field in an extended mnemonic XX3 form instruction. */ |
3030 | #define DMEX DM + 1 | |
3031 | { 0x3, 8, insert_dm, extract_dm, 0 }, | |
e3c2f928 | 3032 | |
b80c7270 AM |
3033 | /* The UIM field in an XX2 form instruction. */ |
3034 | #define UIM DMEX + 1 | |
3035 | /* The 2-bit UIMM field in a VX form instruction. */ | |
3036 | #define UIMM2 UIM | |
3037 | /* The 2-bit L field in a darn instruction. */ | |
3038 | #define LRAND UIM | |
3039 | { 0x3, 16, NULL, NULL, 0 }, | |
e3c2f928 | 3040 | |
b80c7270 AM |
3041 | #define ERAT_T UIM + 1 |
3042 | { 0x7, 21, NULL, NULL, 0 }, | |
e3c2f928 | 3043 | |
b80c7270 AM |
3044 | #define IH ERAT_T + 1 |
3045 | { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
e3c2f928 | 3046 | |
b80c7270 AM |
3047 | /* The 8-bit IMM8 field in a XX1 form instruction. */ |
3048 | #define IMM8 IH + 1 | |
3049 | { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, | |
e3c2f928 | 3050 | |
b80c7270 AM |
3051 | #define VX_OFF IMM8 + 1 |
3052 | { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 }, | |
74081948 AF |
3053 | |
3054 | #define VX_OFF_SPE2 VX_OFF + 1 | |
3055 | { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 }, | |
3056 | ||
3057 | #define BBB VX_OFF_SPE2 + 1 | |
3058 | { 0x7, 13, NULL, NULL, 0 }, | |
3059 | ||
3060 | #define DDD BBB + 1 | |
3061 | #define VX_MASK_DDD (VX_MASK & ~0x1) | |
3062 | { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, | |
3063 | ||
3064 | #define HH DDD + 1 | |
3065 | { 0x3, 13, NULL, NULL, 0 }, | |
b80c7270 AM |
3066 | }; |
3067 | ||
3068 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | |
3069 | / sizeof (powerpc_operands[0])); | |
252b5132 RH |
3070 | \f |
3071 | /* Macros used to form opcodes. */ | |
3072 | ||
3073 | /* The main opcode. */ | |
0f873fd5 | 3074 | #define OP(x) ((((uint64_t)(x)) & 0x3f) << 26) |
252b5132 RH |
3075 | #define OP_MASK OP (0x3f) |
3076 | ||
dd7efa79 PB |
3077 | /* The prefix opcode. */ |
3078 | #define PREFIX_OP (1ULL << 58) | |
3079 | ||
3080 | /* The 2-bit prefix form. */ | |
3081 | #define PREFIX_FORM(x) ((x & 3ULL) << 56) | |
3082 | ||
3083 | #define SUFFIX_MASK ((1ULL << 32) - 1) | |
3084 | #define PREFIX_MASK (SUFFIX_MASK << 32) | |
3085 | ||
8acf1435 PB |
3086 | /* Prefix insn, eight byte load/store form 8LS. */ |
3087 | #define P8LS (PREFIX_OP | PREFIX_FORM (0)) | |
3088 | ||
6edbfd3b AM |
3089 | /* Prefix insn, eight byte register to register form 8RR. */ |
3090 | #define P8RR (PREFIX_OP | PREFIX_FORM (1)) | |
3091 | ||
8acf1435 PB |
3092 | /* Prefix insn, modified load/store form MLS. */ |
3093 | #define PMLS (PREFIX_OP | PREFIX_FORM (2)) | |
3094 | ||
dd7efa79 PB |
3095 | /* Prefix insn, modified register to register form MRR. */ |
3096 | #define PMRR (PREFIX_OP | PREFIX_FORM (3)) | |
3097 | ||
aa3c112f AM |
3098 | /* Prefix insn, modified masked immediate register to register form MMIRR. */ |
3099 | #define PMMIRR (PREFIX_OP | PREFIX_FORM (3) | (9ULL << 52)) | |
3100 | ||
8acf1435 PB |
3101 | /* An 8-byte D form prefix instruction. */ |
3102 | #define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK) | |
3103 | ||
3104 | /* The same as P_D_MASK, but with the RA and PCREL fields specified. */ | |
3105 | #define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK) | |
3106 | ||
aa3c112f AM |
3107 | /* Mask for prefix X form instructions. */ |
3108 | #define P_X_MASK (PREFIX_MASK | X_MASK) | |
3109 | #define P_XX1_MASK (PREFIX_MASK | XX1_MASK) | |
3110 | ||
6edbfd3b AM |
3111 | /* Mask for prefix vector permute insns. */ |
3112 | #define P_XX4_MASK (PREFIX_MASK | XX4_MASK) | |
3113 | #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32)) | |
ec40e91c | 3114 | #define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32)) |
6edbfd3b | 3115 | |
aa3c112f AM |
3116 | /* MMIRR:XX3-form 8-byte outer product instructions. */ |
3117 | #define P_GER_MASK ((-1ULL << 40) | XX3_MASK | (3 << 21) | 1) | |
3118 | #define P_GER2_MASK (P_GER_MASK & ~(3ULL << 46)) | |
3119 | #define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44)) | |
3120 | #define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40)) | |
3121 | #define P_GER64_MASK (P_GER_MASK | (3ULL << 32)) | |
3122 | ||
6edbfd3b AM |
3123 | /* Vector splat immediate op. */ |
3124 | #define VSOP(op, xop) (OP (op) | (xop << 17)) | |
3125 | #define P_VS_MASK ((-1ULL << 48) | VSOP (0x3f, 0xf)) | |
3126 | #define P_VSI_MASK ((-1ULL << 48) | VSOP (0x3f, 0xe)) | |
3127 | ||
252b5132 RH |
3128 | /* The main opcode combined with a trap code in the TO field of a D |
3129 | form instruction. Used for extended mnemonics for the trap | |
3130 | instructions. */ | |
0f873fd5 | 3131 | #define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21)) |
252b5132 RH |
3132 | #define OPTO_MASK (OP_MASK | TO_MASK) |
3133 | ||
3134 | /* The main opcode combined with a comparison size bit in the L field | |
3135 | of a D form or X form instruction. Used for extended mnemonics for | |
3136 | the comparison instructions. */ | |
0f873fd5 | 3137 | #define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21)) |
252b5132 RH |
3138 | #define OPL_MASK OPL (0x3f,1) |
3139 | ||
b9c361e0 JL |
3140 | /* The main opcode combined with an update code in D form instruction. |
3141 | Used for extended mnemonics for VLE memory instructions. */ | |
0f873fd5 | 3142 | #define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8)) |
b9c361e0 JL |
3143 | #define OPVUP_MASK OPVUP (0x3f, 0xff) |
3144 | ||
b80c7270 AM |
3145 | /* The main opcode combined with an update code and the RT fields |
3146 | specified in D form instruction. Used for VLE volatile context | |
3147 | save/restore instructions. */ | |
3148 | #define OPVUPRT(x,vup,rt) \ | |
3149 | (OPVUP (x, vup) \ | |
0f873fd5 | 3150 | | ((((uint64_t)(rt)) & 0x1f) << 21)) |
dfdaec14 AJ |
3151 | #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) |
3152 | ||
252b5132 | 3153 | /* An A form instruction. */ |
b80c7270 AM |
3154 | #define A(op, xop, rc) \ |
3155 | (OP (op) \ | |
0f873fd5 PB |
3156 | | ((((uint64_t)(xop)) & 0x1f) << 1) \ |
3157 | | (((uint64_t)(rc)) & 1)) | |
252b5132 RH |
3158 | #define A_MASK A (0x3f, 0x1f, 1) |
3159 | ||
3160 | /* An A_MASK with the FRB field fixed. */ | |
3161 | #define AFRB_MASK (A_MASK | FRB_MASK) | |
3162 | ||
3163 | /* An A_MASK with the FRC field fixed. */ | |
3164 | #define AFRC_MASK (A_MASK | FRC_MASK) | |
3165 | ||
3166 | /* An A_MASK with the FRA and FRC fields fixed. */ | |
3167 | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) | |
3168 | ||
702f0fb4 | 3169 | /* An AFRAFRC_MASK, but with L bit clear. */ |
0f873fd5 | 3170 | #define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16)) |
702f0fb4 | 3171 | |
252b5132 | 3172 | /* A B form instruction. */ |
b80c7270 AM |
3173 | #define B(op, aa, lk) \ |
3174 | (OP (op) \ | |
0f873fd5 | 3175 | | ((((uint64_t)(aa)) & 1) << 1) \ |
b80c7270 | 3176 | | ((lk) & 1)) |
252b5132 RH |
3177 | #define B_MASK B (0x3f, 1, 1) |
3178 | ||
b9c361e0 | 3179 | /* A BD8 form instruction. This is a 16-bit instruction. */ |
b80c7270 | 3180 | #define BD8(op, aa, lk) \ |
0f873fd5 | 3181 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 AM |
3182 | | (((aa) & 1) << 9) \ |
3183 | | (((lk) & 1) << 8)) | |
b9c361e0 JL |
3184 | #define BD8_MASK BD8 (0x3f, 1, 1) |
3185 | ||
3186 | /* Another BD8 form instruction. This is a 16-bit instruction. */ | |
0f873fd5 | 3187 | #define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11) |
b9c361e0 JL |
3188 | #define BD8IO_MASK BD8IO (0x1f) |
3189 | ||
3190 | /* A BD8 form instruction for simplified mnemonics. */ | |
3191 | #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) | |
3192 | /* A mask that excludes BO32 and BI32. */ | |
3193 | #define EBD8IO1_MASK 0xf800 | |
3194 | /* A mask that includes BO32 and excludes BI32. */ | |
3195 | #define EBD8IO2_MASK 0xfc00 | |
3196 | /* A mask that include BO32 AND BI32. */ | |
3197 | #define EBD8IO3_MASK 0xff00 | |
3198 | ||
3199 | /* A BD15 form instruction. */ | |
b80c7270 AM |
3200 | #define BD15(op, aa, lk) \ |
3201 | (OP (op) \ | |
0f873fd5 | 3202 | | ((((uint64_t)(aa)) & 0xf) << 22) \ |
b80c7270 | 3203 | | ((lk) & 1)) |
b9c361e0 JL |
3204 | #define BD15_MASK BD15 (0x3f, 0xf, 1) |
3205 | ||
3206 | /* A BD15 form instruction for extended conditional branch mnemonics. */ | |
b80c7270 | 3207 | #define EBD15(op, aa, bo, lk) \ |
2480b6fa | 3208 | (((op) & 0x3fu) << 26) \ |
b80c7270 AM |
3209 | | (((aa) & 0xf) << 22) \ |
3210 | | (((bo) & 0x3) << 20) \ | |
3211 | | ((lk) & 1) | |
b9c361e0 JL |
3212 | #define EBD15_MASK 0xfff00001 |
3213 | ||
b80c7270 AM |
3214 | /* A BD15 form instruction for extended conditional branch mnemonics |
3215 | with BI. */ | |
3216 | #define EBD15BI(op, aa, bo, bi, lk) \ | |
2480b6fa | 3217 | ((((op) & 0x3fu) << 26) \ |
b80c7270 AM |
3218 | | (((aa) & 0xf) << 22) \ |
3219 | | (((bo) & 0x3) << 20) \ | |
3220 | | (((bi) & 0x3) << 16) \ | |
3221 | | ((lk) & 1)) | |
3222 | ||
b9c361e0 JL |
3223 | #define EBD15BI_MASK 0xfff30001 |
3224 | ||
3225 | /* A BD24 form instruction. */ | |
b80c7270 AM |
3226 | #define BD24(op, aa, lk) \ |
3227 | (OP (op) \ | |
0f873fd5 | 3228 | | ((((uint64_t)(aa)) & 1) << 25) \ |
b80c7270 | 3229 | | ((lk) & 1)) |
b9c361e0 JL |
3230 | #define BD24_MASK BD24 (0x3f, 1, 1) |
3231 | ||
252b5132 | 3232 | /* A B form instruction setting the BO field. */ |
b80c7270 AM |
3233 | #define BBO(op, bo, aa, lk) \ |
3234 | (B ((op), (aa), (lk)) \ | |
0f873fd5 | 3235 | | ((((uint64_t)(bo)) & 0x1f) << 21)) |
252b5132 RH |
3236 | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
3237 | ||
3238 | /* A BBO_MASK with the y bit of the BO field removed. This permits | |
3239 | matching a conditional branch regardless of the setting of the y | |
94efba12 | 3240 | bit. Similarly for the 'at' bits used for power4 branch hints. */ |
0f873fd5 PB |
3241 | #define Y_MASK (((uint64_t) 1) << 21) |
3242 | #define AT1_MASK (((uint64_t) 3) << 21) | |
3243 | #define AT2_MASK (((uint64_t) 9) << 21) | |
802a735e AM |
3244 | #define BBOY_MASK (BBO_MASK &~ Y_MASK) |
3245 | #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) | |
252b5132 RH |
3246 | |
3247 | /* A B form instruction setting the BO field and the condition bits of | |
3248 | the BI field. */ | |
3249 | #define BBOCB(op, bo, cb, aa, lk) \ | |
0f873fd5 | 3250 | (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16)) |
252b5132 RH |
3251 | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
3252 | ||
3253 | /* A BBOCB_MASK with the y bit of the BO field removed. */ | |
3254 | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) | |
802a735e AM |
3255 | #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
3256 | #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) | |
252b5132 RH |
3257 | |
3258 | /* A BBOYCB_MASK in which the BI field is fixed. */ | |
3259 | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) | |
802a735e | 3260 | #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
252b5132 | 3261 | |
b9c361e0 | 3262 | /* A VLE C form instruction. */ |
0f873fd5 | 3263 | #define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1)) |
b9c361e0 | 3264 | #define C_LK_MASK C_LK(0x7fff, 1) |
0f873fd5 | 3265 | #define C(x) ((((uint64_t)(x)) & 0xffff)) |
b9c361e0 JL |
3266 | #define C_MASK C(0xffff) |
3267 | ||
23976049 | 3268 | /* An Context form instruction. */ |
0f873fd5 | 3269 | #define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7)) |
fdd12ef3 | 3270 | #define CTX_MASK CTX(0x3f, 0x7) |
23976049 EZ |
3271 | |
3272 | /* An User Context form instruction. */ | |
0f873fd5 | 3273 | #define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) |
fdd12ef3 | 3274 | #define UCTX_MASK UCTX(0x3f, 0x1f) |
23976049 | 3275 | |
252b5132 RH |
3276 | /* The main opcode mask with the RA field clear. */ |
3277 | #define DRA_MASK (OP_MASK | RA_MASK) | |
3278 | ||
a680de9a PB |
3279 | /* A DQ form VSX instruction. */ |
3280 | #define DQX(op, xop) (OP (op) | ((xop) & 0x7)) | |
3281 | #define DQX_MASK DQX (0x3f, 7) | |
3282 | ||
94ba9882 AM |
3283 | /* A DQ form VSX vector paired instruction. */ |
3284 | #define DQXP(op, xop) (OP (op) | ((xop) & 0xf)) | |
3285 | #define DQXP_MASK DQXP (0x3f, 0xf) | |
3286 | ||
252b5132 RH |
3287 | /* A DS form instruction. */ |
3288 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) | |
3289 | #define DS_MASK DSO (0x3f, 3) | |
3290 | ||
a680de9a | 3291 | /* An DX form instruction. */ |
0f873fd5 | 3292 | #define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
a680de9a | 3293 | #define DX_MASK DX (0x3f, 0x1f) |
1437d063 PB |
3294 | /* An DX form instruction with the D bits specified. */ |
3295 | #define NODX_MASK (DX_MASK | 0x1fffc1) | |
a680de9a | 3296 | |
23976049 | 3297 | /* An EVSEL form instruction. */ |
0f873fd5 | 3298 | #define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3) |
23976049 EZ |
3299 | #define EVSEL_MASK EVSEL(0x3f, 0xff) |
3300 | ||
b9c361e0 | 3301 | /* An IA16 form instruction. */ |
0f873fd5 | 3302 | #define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
3303 | #define IA16_MASK IA16(0x3f, 0x1f) |
3304 | ||
3305 | /* An I16A form instruction. */ | |
0f873fd5 | 3306 | #define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
3307 | #define I16A_MASK I16A(0x3f, 0x1f) |
3308 | ||
3309 | /* An I16L form instruction. */ | |
0f873fd5 | 3310 | #define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) |
b9c361e0 JL |
3311 | #define I16L_MASK I16L(0x3f, 0x1f) |
3312 | ||
3313 | /* An IM7 form instruction. */ | |
0f873fd5 | 3314 | #define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11) |
b9c361e0 JL |
3315 | #define IM7_MASK IM7(0x1f) |
3316 | ||
252b5132 RH |
3317 | /* An M form instruction. */ |
3318 | #define M(op, rc) (OP (op) | ((rc) & 1)) | |
3319 | #define M_MASK M (0x3f, 1) | |
3320 | ||
b9c361e0 | 3321 | /* An LI20 form instruction. */ |
0f873fd5 | 3322 | #define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15) |
b9c361e0 JL |
3323 | #define LI20_MASK LI20(0x3f, 0x1) |
3324 | ||
252b5132 | 3325 | /* An M form instruction with the ME field specified. */ |
b80c7270 AM |
3326 | #define MME(op, me, rc) \ |
3327 | (M ((op), (rc)) \ | |
0f873fd5 | 3328 | | ((((uint64_t)(me)) & 0x1f) << 1)) |
252b5132 RH |
3329 | |
3330 | /* An M_MASK with the MB and ME fields fixed. */ | |
3331 | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) | |
3332 | ||
3333 | /* An M_MASK with the SH and ME fields fixed. */ | |
3334 | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) | |
3335 | ||
3336 | /* An MD form instruction. */ | |
b80c7270 AM |
3337 | #define MD(op, xop, rc) \ |
3338 | (OP (op) \ | |
0f873fd5 | 3339 | | ((((uint64_t)(xop)) & 0x7) << 2) \ |
b80c7270 | 3340 | | ((rc) & 1)) |
252b5132 RH |
3341 | #define MD_MASK MD (0x3f, 0x7, 1) |
3342 | ||
3343 | /* An MD_MASK with the MB field fixed. */ | |
3344 | #define MDMB_MASK (MD_MASK | MB6_MASK) | |
3345 | ||
3346 | /* An MD_MASK with the SH field fixed. */ | |
3347 | #define MDSH_MASK (MD_MASK | SH6_MASK) | |
3348 | ||
3349 | /* An MDS form instruction. */ | |
b80c7270 AM |
3350 | #define MDS(op, xop, rc) \ |
3351 | (OP (op) \ | |
0f873fd5 | 3352 | | ((((uint64_t)(xop)) & 0xf) << 1) \ |
b80c7270 | 3353 | | ((rc) & 1)) |
252b5132 RH |
3354 | #define MDS_MASK MDS (0x3f, 0xf, 1) |
3355 | ||
3356 | /* An MDS_MASK with the MB field fixed. */ | |
3357 | #define MDSMB_MASK (MDS_MASK | MB6_MASK) | |
3358 | ||
3359 | /* An SC form instruction. */ | |
b80c7270 AM |
3360 | #define SC(op, sa, lk) \ |
3361 | (OP (op) \ | |
0f873fd5 | 3362 | | ((((uint64_t)(sa)) & 1) << 1) \ |
b80c7270 AM |
3363 | | ((lk) & 1)) |
3364 | #define SC_MASK \ | |
3365 | (OP_MASK \ | |
0f873fd5 PB |
3366 | | (((uint64_t) 0x3ff) << 16) \ |
3367 | | (((uint64_t) 1) << 1) \ | |
b80c7270 | 3368 | | 1) |
252b5132 | 3369 | |
b9c361e0 | 3370 | /* An SCI8 form instruction. */ |
0f873fd5 | 3371 | #define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11)) |
b9c361e0 JL |
3372 | #define SCI8_MASK SCI8(0x3f, 0x1f) |
3373 | ||
3374 | /* An SCI8 form instruction. */ | |
b80c7270 AM |
3375 | #define SCI8BF(op, fop, xop) \ |
3376 | (OP (op) \ | |
0f873fd5 | 3377 | | ((((uint64_t)(xop)) & 0x1f) << 11) \ |
b80c7270 | 3378 | | (((fop) & 7) << 23)) |
b9c361e0 JL |
3379 | #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) |
3380 | ||
3381 | /* An SD4 form instruction. This is a 16-bit instruction. */ | |
0f873fd5 | 3382 | #define SD4(op) ((((uint64_t)(op)) & 0xf) << 12) |
b9c361e0 JL |
3383 | #define SD4_MASK SD4(0xf) |
3384 | ||
3385 | /* An SE_IM5 form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 3386 | #define SE_IM5(op, xop) \ |
0f873fd5 | 3387 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 3388 | | (((xop) & 0x1) << 9)) |
b9c361e0 JL |
3389 | #define SE_IM5_MASK SE_IM5(0x3f, 1) |
3390 | ||
3391 | /* An SE_R form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 3392 | #define SE_R(op, xop) \ |
0f873fd5 | 3393 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 3394 | | (((xop) & 0x3f) << 4)) |
b9c361e0 JL |
3395 | #define SE_R_MASK SE_R(0x3f, 0x3f) |
3396 | ||
3397 | /* An SE_RR form instruction. This is a 16-bit instruction. */ | |
b80c7270 | 3398 | #define SE_RR(op, xop) \ |
0f873fd5 | 3399 | (((((uint64_t)(op)) & 0x3f) << 10) \ |
b80c7270 | 3400 | | (((xop) & 0x3) << 8)) |
b9c361e0 JL |
3401 | #define SE_RR_MASK SE_RR(0x3f, 3) |
3402 | ||
3403 | /* A VX form instruction. */ | |
0f873fd5 | 3404 | #define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) |
786e2c0f | 3405 | |
112290ab | 3406 | /* The mask for an VX form instruction. */ |
786e2c0f C |
3407 | #define VX_MASK VX(0x3f, 0x7ff) |
3408 | ||
e3c2f928 | 3409 | /* A VX LSP form instruction. */ |
0f873fd5 | 3410 | #define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff)) |
e3c2f928 AF |
3411 | |
3412 | /* The mask for an VX LSP form instruction. */ | |
3413 | #define VX_LSP_MASK VX_LSP(0x3f, 0xffff) | |
3414 | #define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc) | |
3415 | ||
74081948 AF |
3416 | /* Additional format of VX SPE2 form instruction. */ |
3417 | #define VX_RA_CONST(op, xop, bits11_15) \ | |
3418 | (OP (op) \ | |
0f873fd5 PB |
3419 | | (((uint64_t)(bits11_15) & 0x1f) << 16) \ |
3420 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3421 | #define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f) |
3422 | ||
3423 | #define VX_RB_CONST(op, xop, bits16_20) \ | |
3424 | (OP (op) \ | |
0f873fd5 PB |
3425 | | (((uint64_t)(bits16_20) & 0x1f) << 11) \ |
3426 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3427 | #define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f) |
3428 | ||
3429 | #define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8) | |
3430 | ||
3431 | #define VX_SPE_CRFD(op, xop, bits9_10) \ | |
3432 | (OP (op) \ | |
0f873fd5 PB |
3433 | | (((uint64_t)(bits9_10) & 0x3) << 21) \ |
3434 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3435 | #define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3) |
3436 | ||
3437 | #define VX_SPE2_CLR(op, xop, bit16) \ | |
3438 | (OP (op) \ | |
0f873fd5 PB |
3439 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3440 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3441 | #define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1) |
3442 | ||
3443 | #define VX_SPE2_SPLATB(op, xop, bits19_20) \ | |
3444 | (OP (op) \ | |
0f873fd5 PB |
3445 | | (((uint64_t)(bits19_20) & 0x3) << 11) \ |
3446 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3447 | #define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3) |
3448 | ||
3449 | #define VX_SPE2_OCTET(op, xop, bits16_17) \ | |
3450 | (OP (op) \ | |
0f873fd5 PB |
3451 | | (((uint64_t)(bits16_17) & 0x3) << 14) \ |
3452 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3453 | #define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7) |
3454 | ||
3455 | #define VX_SPE2_DDHH(op, xop, bit16) \ | |
3456 | (OP (op) \ | |
0f873fd5 PB |
3457 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3458 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3459 | #define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1) |
3460 | ||
3461 | #define VX_SPE2_HH(op, xop, bit16, bits19_20) \ | |
3462 | (OP (op) \ | |
0f873fd5 PB |
3463 | | (((uint64_t)(bit16) & 0x1) << 15) \ |
3464 | | (((uint64_t)(bits19_20) & 0x3) << 11) \ | |
3465 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3466 | #define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3) |
3467 | ||
3468 | #define VX_SPE2_EVMAR(op, xop) \ | |
3469 | (OP (op) \ | |
0f873fd5 PB |
3470 | | ((uint64_t)(0x1) << 11) \ |
3471 | | (((uint64_t)(xop)) & 0x7ff)) | |
74081948 AF |
3472 | #define VX_SPE2_EVMAR_MASK \ |
3473 | (VX_SPE2_EVMAR(0x3f, 0x7ff) \ | |
0f873fd5 | 3474 | | ((uint64_t)(0x1) << 11)) |
74081948 | 3475 | |
fb048c26 PB |
3476 | /* A VX_MASK with the VA field fixed. */ |
3477 | #define VXVA_MASK (VX_MASK | (0x1f << 16)) | |
3478 | ||
3479 | /* A VX_MASK with the VB field fixed. */ | |
3480 | #define VXVB_MASK (VX_MASK | (0x1f << 11)) | |
3481 | ||
3482 | /* A VX_MASK with the VA and VB fields fixed. */ | |
3483 | #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) | |
3484 | ||
3485 | /* A VX_MASK with the VD and VA fields fixed. */ | |
3486 | #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) | |
3487 | ||
3488 | /* A VX_MASK with a UIMM4 field. */ | |
3489 | #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) | |
3490 | ||
3491 | /* A VX_MASK with a UIMM3 field. */ | |
3492 | #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) | |
3493 | ||
3494 | /* A VX_MASK with a UIMM2 field. */ | |
3495 | #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) | |
3496 | ||
c0637f3a PB |
3497 | /* A VX_MASK with a PS field. */ |
3498 | #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) | |
3499 | ||
a680de9a | 3500 | /* A VX_MASK with the VA field fixed with a PS field. */ |
fdefed7c AM |
3501 | #define VXVAPS_MASK (VXVA_MASK & ~(0x1 << 9)) |
3502 | ||
3503 | /* A VX_MASK with the VA field fixed with a MP field. */ | |
3504 | #define VXVAM_MASK (VXVA_MASK & ~(0x1 << 16)) | |
a680de9a | 3505 | |
c7d7aea2 AM |
3506 | /* A VX_MASK for instructions using a BF field. */ |
3507 | #define VXBF_MASK (VX_MASK | (3 << 21)) | |
3508 | ||
6edbfd3b AM |
3509 | /* A VX_MASK for instructions with an RC field. */ |
3510 | #define VXRC_MASK (VX_MASK & ~(0x1f << 6)) | |
3511 | ||
3512 | /* A VX_MASK for instructions with a SH field. */ | |
3513 | #define VXSH_MASK (VX_MASK & ~(0x7 << 6)) | |
3514 | ||
b9c361e0 | 3515 | /* A VA form instruction. */ |
0f873fd5 | 3516 | #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f)) |
786e2c0f | 3517 | |
112290ab | 3518 | /* The mask for an VA form instruction. */ |
2613489e | 3519 | #define VXA_MASK VXA(0x3f, 0x3f) |
786e2c0f | 3520 | |
382c72e9 PB |
3521 | /* A VXA_MASK with a SHB field. */ |
3522 | #define VXASHB_MASK (VXA_MASK | (1 << 10)) | |
3523 | ||
b9c361e0 | 3524 | /* A VXR form instruction. */ |
b80c7270 AM |
3525 | #define VXR(op, xop, rc) \ |
3526 | (OP (op) \ | |
0f873fd5 PB |
3527 | | (((uint64_t)(rc) & 1) << 10) \ |
3528 | | (((uint64_t)(xop)) & 0x3ff)) | |
786e2c0f | 3529 | |
112290ab | 3530 | /* The mask for a VXR form instruction. */ |
786e2c0f C |
3531 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
3532 | ||
a680de9a PB |
3533 | /* A VX form instruction with a VA tertiary opcode. */ |
3534 | #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) | |
3535 | ||
0f873fd5 | 3536 | #define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
6fd3a02d PB |
3537 | #define VXASH_MASK VXASH (0x3f, 0x1f) |
3538 | ||
252b5132 | 3539 | /* An X form instruction. */ |
0f873fd5 | 3540 | #define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) |
252b5132 | 3541 | |
a680de9a PB |
3542 | /* A X form instruction for Quad-Precision FP Instructions. */ |
3543 | #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) | |
3544 | ||
b9c361e0 | 3545 | /* An EX form instruction. */ |
0f873fd5 | 3546 | #define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) |
b9c361e0 JL |
3547 | |
3548 | /* The mask for an EX form instruction. */ | |
3549 | #define EX_MASK EX (0x3f, 0x7ff) | |
3550 | ||
066be9f7 | 3551 | /* An XX2 form instruction. */ |
0f873fd5 | 3552 | #define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2)) |
066be9f7 | 3553 | |
a680de9a PB |
3554 | /* A XX2 form instruction with the VA bits specified. */ |
3555 | #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) | |
3556 | ||
9b4e5766 | 3557 | /* An XX3 form instruction. */ |
0f873fd5 | 3558 | #define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3)) |
9b4e5766 | 3559 | |
066be9f7 | 3560 | /* An XX3 form instruction with the RC bit specified. */ |
b80c7270 AM |
3561 | #define XX3RC(op, xop, rc) \ |
3562 | (OP (op) \ | |
0f873fd5 PB |
3563 | | (((uint64_t)(rc) & 1) << 10) \ |
3564 | | ((((uint64_t)(xop)) & 0x7f) << 3)) | |
066be9f7 PB |
3565 | |
3566 | /* An XX4 form instruction. */ | |
0f873fd5 | 3567 | #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4)) |
9b4e5766 | 3568 | |
702f0fb4 | 3569 | /* A Z form instruction. */ |
0f873fd5 | 3570 | #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1)) |
702f0fb4 | 3571 | |
252b5132 RH |
3572 | /* An X form instruction with the RC bit specified. */ |
3573 | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) | |
3574 | ||
a680de9a PB |
3575 | /* A X form instruction for Quad-Precision FP Instructions with RC bit. */ |
3576 | #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) | |
3577 | ||
6fd3a02d | 3578 | /* An X form instruction with the RA bits specified as two ops. */ |
b80c7270 AM |
3579 | #define XMMF(op, xop, mop0, mop1) \ |
3580 | (X ((op), (xop)) \ | |
3581 | | ((mop0) & 3) << 19 \ | |
3582 | | ((mop1) & 7) << 16) | |
6fd3a02d | 3583 | |
702f0fb4 PB |
3584 | /* A Z form instruction with the RC bit specified. */ |
3585 | #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) | |
3586 | ||
252b5132 RH |
3587 | /* The mask for an X form instruction. */ |
3588 | #define X_MASK XRC (0x3f, 0x3ff, 1) | |
3589 | ||
a680de9a PB |
3590 | /* The mask for an X form instruction with the BF bits specified. */ |
3591 | #define XBF_MASK (X_MASK | (3 << 21)) | |
3592 | ||
b80c7270 AM |
3593 | /* An X form wait instruction with everything filled in except the WC |
3594 | field. */ | |
e0d602ec BE |
3595 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
3596 | ||
9b4e5766 PB |
3597 | /* The mask for an XX1 form instruction. */ |
3598 | #define XX1_MASK X (0x3f, 0x3ff) | |
3599 | ||
c0637f3a PB |
3600 | /* An XX1_MASK with the RB field fixed. */ |
3601 | #define XX1RB_MASK (XX1_MASK | RB_MASK) | |
3602 | ||
066be9f7 PB |
3603 | /* The mask for an XX2 form instruction. */ |
3604 | #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) | |
3605 | ||
3606 | /* The mask for an XX2 form instruction with the UIM bits specified. */ | |
3607 | #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) | |
3608 | ||
a680de9a PB |
3609 | /* The mask for an XX2 form instruction with the 4 UIM bits specified. */ |
3610 | #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) | |
3611 | ||
066be9f7 PB |
3612 | /* The mask for an XX2 form instruction with the BF bits specified. */ |
3613 | #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) | |
3614 | ||
b80c7270 AM |
3615 | /* The mask for an XX2 form instruction with the BF and DCMX bits |
3616 | specified. */ | |
a680de9a PB |
3617 | #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) |
3618 | ||
b80c7270 AM |
3619 | /* The mask for an XX2 form instruction with a split DCMX bits |
3620 | specified. */ | |
a680de9a PB |
3621 | #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) |
3622 | ||
9b4e5766 PB |
3623 | /* The mask for an XX3 form instruction. */ |
3624 | #define XX3_MASK XX3 (0x3f, 0xff) | |
3625 | ||
066be9f7 PB |
3626 | /* The mask for an XX3 form instruction with the BF bits specified. */ |
3627 | #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) | |
3628 | ||
b80c7270 AM |
3629 | /* The mask for an XX3 form instruction with the DM or SHW bits |
3630 | specified. */ | |
9b4e5766 | 3631 | #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) |
066be9f7 PB |
3632 | #define XX3SHW_MASK XX3DM_MASK |
3633 | ||
3634 | /* The mask for an XX4 form instruction. */ | |
3635 | #define XX4_MASK XX4 (0x3f, 0x3) | |
3636 | ||
b80c7270 AM |
3637 | /* An X form wait instruction with everything filled in except the WC |
3638 | field. */ | |
066be9f7 | 3639 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
9b4e5766 | 3640 | |
6fd3a02d PB |
3641 | /* The mask for an XMMF form instruction. */ |
3642 | #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) | |
3643 | ||
702f0fb4 PB |
3644 | /* The mask for a Z form instruction. */ |
3645 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) | |
0bbdef92 | 3646 | #define Z2_MASK ZRC (0x3f, 0xff, 1) |
702f0fb4 | 3647 | |
a680de9a | 3648 | /* An X_MASK with the RA/VA field fixed. */ |
252b5132 | 3649 | #define XRA_MASK (X_MASK | RA_MASK) |
a680de9a | 3650 | #define XVA_MASK XRA_MASK |
252b5132 | 3651 | |
a680de9a | 3652 | /* An XRA_MASK with the A_L/W field clear. */ |
0f873fd5 | 3653 | #define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16)) |
a680de9a | 3654 | #define XRLA_MASK XWRA_MASK |
ea192fa3 | 3655 | |
252b5132 RH |
3656 | /* An X_MASK with the RB field fixed. */ |
3657 | #define XRB_MASK (X_MASK | RB_MASK) | |
3658 | ||
3659 | /* An X_MASK with the RT field fixed. */ | |
3660 | #define XRT_MASK (X_MASK | RT_MASK) | |
3661 | ||
702f0fb4 | 3662 | /* An XRT_MASK mask with the L bits clear. */ |
0f873fd5 | 3663 | #define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21)) |
702f0fb4 | 3664 | |
252b5132 RH |
3665 | /* An X_MASK with the RA and RB fields fixed. */ |
3666 | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) | |
3667 | ||
a680de9a PB |
3668 | /* An XBF_MASK with the RA and RB fields fixed. */ |
3669 | #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) | |
3670 | ||
112290ab | 3671 | /* An XRARB_MASK, but with the L bit clear. */ |
0f873fd5 | 3672 | #define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16)) |
5ae2e65e | 3673 | |
a680de9a | 3674 | /* An XRARB_MASK, but with the L bits in a darn instruction clear. */ |
0f873fd5 | 3675 | #define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16)) |
a680de9a | 3676 | |
252b5132 RH |
3677 | /* An X_MASK with the RT and RA fields fixed. */ |
3678 | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) | |
3679 | ||
5817ffd1 PB |
3680 | /* An X_MASK with the RT and RB fields fixed. */ |
3681 | #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) | |
3682 | ||
98acc1c5 | 3683 | /* An XRTRA_MASK, but with L bit clear. */ |
0f873fd5 | 3684 | #define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21)) |
98acc1c5 | 3685 | |
5817ffd1 PB |
3686 | /* An X_MASK with the RT, RA and RB fields fixed. */ |
3687 | #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) | |
3688 | ||
3689 | /* An XRTRARB_MASK, but with L bit clear. */ | |
0f873fd5 | 3690 | #define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21)) |
5817ffd1 PB |
3691 | |
3692 | /* An XRTRARB_MASK, but with A bit clear. */ | |
0f873fd5 | 3693 | #define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25)) |
5817ffd1 PB |
3694 | |
3695 | /* An XRTRARB_MASK, but with BF bits clear. */ | |
0f873fd5 | 3696 | #define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23)) |
5817ffd1 | 3697 | |
f3806e43 | 3698 | /* An X form instruction with the L bit specified. */ |
b80c7270 AM |
3699 | #define XOPL(op, xop, l) \ |
3700 | (X ((op), (xop)) \ | |
0f873fd5 | 3701 | | ((((uint64_t)(l)) & 1) << 21)) |
252b5132 | 3702 | |
e0d602ec | 3703 | /* An X form instruction with the L bits specified. */ |
b80c7270 AM |
3704 | #define XOPL2(op, xop, l) \ |
3705 | (X ((op), (xop)) \ | |
0f873fd5 | 3706 | | ((((uint64_t)(l)) & 3) << 21)) |
e0d602ec | 3707 | |
5817ffd1 | 3708 | /* An X form instruction with the L bit and RC bit specified. */ |
b80c7270 AM |
3709 | #define XRCL(op, xop, l, rc) \ |
3710 | (XRC ((op), (xop), (rc)) \ | |
0f873fd5 | 3711 | | ((((uint64_t)(l)) & 1) << 21)) |
5817ffd1 | 3712 | |
19a6653c | 3713 | /* An X form instruction with RT fields specified */ |
b80c7270 AM |
3714 | #define XRT(op, xop, rt) \ |
3715 | (X ((op), (xop)) \ | |
0f873fd5 | 3716 | | ((((uint64_t)(rt)) & 0x1f) << 21)) |
19a6653c AM |
3717 | |
3718 | /* An X form instruction with RT and RA fields specified */ | |
b80c7270 AM |
3719 | #define XRTRA(op, xop, rt, ra) \ |
3720 | (X ((op), (xop)) \ | |
0f873fd5 PB |
3721 | | ((((uint64_t)(rt)) & 0x1f) << 21) \ |
3722 | | ((((uint64_t)(ra)) & 0x1f) << 16)) | |
19a6653c | 3723 | |
252b5132 | 3724 | /* The mask for an X form comparison instruction. */ |
0f873fd5 | 3725 | #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22)) |
252b5132 | 3726 | |
520ceea4 BE |
3727 | /* The mask for an X form comparison instruction with the L field |
3728 | fixed. */ | |
0f873fd5 | 3729 | #define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21)) |
252b5132 RH |
3730 | |
3731 | /* An X form trap instruction with the TO field specified. */ | |
b80c7270 AM |
3732 | #define XTO(op, xop, to) \ |
3733 | (X ((op), (xop)) \ | |
0f873fd5 | 3734 | | ((((uint64_t)(to)) & 0x1f) << 21)) |
252b5132 RH |
3735 | #define XTO_MASK (X_MASK | TO_MASK) |
3736 | ||
e0c21649 | 3737 | /* An X form tlb instruction with the SH field specified. */ |
b80c7270 AM |
3738 | #define XTLB(op, xop, sh) \ |
3739 | (X ((op), (xop)) \ | |
0f873fd5 | 3740 | | ((((uint64_t)(sh)) & 0x1f) << 11)) |
e0c21649 GK |
3741 | #define XTLB_MASK (X_MASK | SH_MASK) |
3742 | ||
6ba045b1 | 3743 | /* An X form sync instruction. */ |
b80c7270 AM |
3744 | #define XSYNC(op, xop, l) \ |
3745 | (X ((op), (xop)) \ | |
0f873fd5 | 3746 | | ((((uint64_t)(l)) & 3) << 21)) |
6ba045b1 | 3747 | |
b80c7270 AM |
3748 | /* An X form sync instruction with everything filled in except the LS |
3749 | field. */ | |
6ba045b1 AM |
3750 | #define XSYNC_MASK (0xff9fffff) |
3751 | ||
b80c7270 AM |
3752 | /* An X form sync instruction with everything filled in except the L |
3753 | and E fields. */ | |
aea77599 AM |
3754 | #define XSYNCLE_MASK (0xff90ffff) |
3755 | ||
702f0fb4 | 3756 | /* An X_MASK, but with the EH bit clear. */ |
0f873fd5 | 3757 | #define XEH_MASK (X_MASK & ~((uint64_t )1)) |
702f0fb4 | 3758 | |
f5c120c5 | 3759 | /* An X form AltiVec dss instruction. */ |
0f873fd5 | 3760 | #define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25)) |
f5c120c5 MG |
3761 | #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) |
3762 | ||
252b5132 | 3763 | /* An XFL form instruction. */ |
b80c7270 AM |
3764 | #define XFL(op, xop, rc) \ |
3765 | (OP (op) \ | |
0f873fd5 PB |
3766 | | ((((uint64_t)(xop)) & 0x3ff) << 1) \ |
3767 | | (((uint64_t)(rc)) & 1)) | |
ea192fa3 | 3768 | #define XFL_MASK XFL (0x3f, 0x3ff, 1) |
252b5132 | 3769 | |
23976049 | 3770 | /* An X form isel instruction. */ |
0f873fd5 | 3771 | #define XISEL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) |
de866fcc | 3772 | #define XISEL_MASK XISEL(0x3f, 0x1f) |
23976049 | 3773 | |
252b5132 | 3774 | /* An XL form instruction with the LK field set to 0. */ |
0f873fd5 | 3775 | #define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) |
252b5132 RH |
3776 | |
3777 | /* An XL form instruction which uses the LK field. */ | |
3778 | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) | |
3779 | ||
3780 | /* The mask for an XL form instruction. */ | |
3781 | #define XL_MASK XLLK (0x3f, 0x3ff, 1) | |
3782 | ||
c0637f3a PB |
3783 | /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ |
3784 | #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) | |
3785 | ||
252b5132 RH |
3786 | /* An XL form instruction which explicitly sets the BO field. */ |
3787 | #define XLO(op, bo, xop, lk) \ | |
0f873fd5 | 3788 | (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21)) |
252b5132 RH |
3789 | #define XLO_MASK (XL_MASK | BO_MASK) |
3790 | ||
252b5132 RH |
3791 | /* An XL form instruction which sets the BO field and the condition |
3792 | bits of the BI field. */ | |
3793 | #define XLOCB(op, bo, cb, xop, lk) \ | |
0f873fd5 | 3794 | (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16)) |
252b5132 RH |
3795 | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
3796 | ||
aae9718e | 3797 | /* An XL_MASK or XLOCB_MASK with the BB field fixed. */ |
252b5132 | 3798 | #define XLBB_MASK (XL_MASK | BB_MASK) |
252b5132 RH |
3799 | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) |
3800 | ||
d0618d1c | 3801 | /* A mask for branch instructions using the BH field. */ |
66e85460 | 3802 | #define XLBH_MASK (XL_MASK | (BB_MASK & ~(3 << 11))) |
d0618d1c | 3803 | |
252b5132 RH |
3804 | /* An XL_MASK with the BO and BB fields fixed. */ |
3805 | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) | |
3806 | ||
3807 | /* An XL_MASK with the BO, BI and BB fields fixed. */ | |
3808 | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) | |
3809 | ||
e01d869a | 3810 | /* An X form mbar instruction with MO field. */ |
b80c7270 AM |
3811 | #define XMBAR(op, xop, mo) \ |
3812 | (X ((op), (xop)) \ | |
0f873fd5 | 3813 | | ((((uint64_t)(mo)) & 1) << 21)) |
e01d869a | 3814 | |
252b5132 | 3815 | /* An XO form instruction. */ |
b80c7270 AM |
3816 | #define XO(op, xop, oe, rc) \ |
3817 | (OP (op) \ | |
0f873fd5 PB |
3818 | | ((((uint64_t)(xop)) & 0x1ff) << 1) \ |
3819 | | ((((uint64_t)(oe)) & 1) << 10) \ | |
b80c7270 | 3820 | | (((unsigned long)(rc)) & 1)) |
252b5132 RH |
3821 | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
3822 | ||
3823 | /* An XO_MASK with the RB field fixed. */ | |
3824 | #define XORB_MASK (XO_MASK | RB_MASK) | |
3825 | ||
c3d65c1c | 3826 | /* An XOPS form instruction for paired singles. */ |
b80c7270 AM |
3827 | #define XOPS(op, xop, rc) \ |
3828 | (OP (op) \ | |
0f873fd5 PB |
3829 | | ((((uint64_t)(xop)) & 0x3ff) << 1) \ |
3830 | | (((uint64_t)(rc)) & 1)) | |
c3d65c1c BE |
3831 | #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) |
3832 | ||
3833 | ||
252b5132 | 3834 | /* An XS form instruction. */ |
b80c7270 AM |
3835 | #define XS(op, xop, rc) \ |
3836 | (OP (op) \ | |
0f873fd5 PB |
3837 | | ((((uint64_t)(xop)) & 0x1ff) << 2) \ |
3838 | | (((uint64_t)(rc)) & 1)) | |
252b5132 RH |
3839 | #define XS_MASK XS (0x3f, 0x1ff, 1) |
3840 | ||
3841 | /* A mask for the FXM version of an XFX form instruction. */ | |
98e69875 | 3842 | #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) |
252b5132 RH |
3843 | |
3844 | /* An XFX form instruction with the FXM field filled in. */ | |
b80c7270 AM |
3845 | #define XFXM(op, xop, fxm, p4) \ |
3846 | (X ((op), (xop)) \ | |
0f873fd5 PB |
3847 | | ((((uint64_t)(fxm)) & 0xff) << 12) \ |
3848 | | ((uint64_t)(p4) << 20)) | |
252b5132 RH |
3849 | |
3850 | /* An XFX form instruction with the SPR field filled in. */ | |
b80c7270 AM |
3851 | #define XSPR(op, xop, spr) \ |
3852 | (X ((op), (xop)) \ | |
0f873fd5 PB |
3853 | | ((((uint64_t)(spr)) & 0x1f) << 16) \ |
3854 | | ((((uint64_t)(spr)) & 0x3e0) << 6)) | |
252b5132 RH |
3855 | #define XSPR_MASK (X_MASK | SPR_MASK) |
3856 | ||
3857 | /* An XFX form instruction with the SPR field filled in except for the | |
3858 | SPRBAT field. */ | |
3859 | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) | |
3860 | ||
fa758a70 AC |
3861 | /* An XFX form instruction with the SPR field filled in except for the |
3862 | SPRGQR field. */ | |
3863 | #define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK) | |
3864 | ||
252b5132 RH |
3865 | /* An XFX form instruction with the SPR field filled in except for the |
3866 | SPRG field. */ | |
b84bf58a | 3867 | #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) |
252b5132 RH |
3868 | |
3869 | /* An X form instruction with everything filled in except the E field. */ | |
3870 | #define XE_MASK (0xffff7fff) | |
3871 | ||
23976049 | 3872 | /* An X form user context instruction. */ |
0f873fd5 | 3873 | #define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) |
23976049 EZ |
3874 | #define XUC_MASK XUC(0x3f, 0x1f) |
3875 | ||
c3d65c1c | 3876 | /* An XW form instruction. */ |
b80c7270 AM |
3877 | #define XW(op, xop, rc) \ |
3878 | (OP (op) \ | |
0f873fd5 | 3879 | | ((((uint64_t)(xop)) & 0x3f) << 1) \ |
b80c7270 | 3880 | | ((rc) & 1)) |
c3d65c1c BE |
3881 | /* The mask for a G form instruction. rc not supported at present. */ |
3882 | #define XW_MASK XW (0x3f, 0x3f, 0) | |
3883 | ||
081ba1b3 | 3884 | /* An APU form instruction. */ |
b80c7270 AM |
3885 | #define APU(op, xop, rc) \ |
3886 | (OP (op) \ | |
0f873fd5 | 3887 | | (((uint64_t)(xop)) & 0x3ff) << 1 \ |
b80c7270 | 3888 | | ((rc) & 1)) |
081ba1b3 AM |
3889 | |
3890 | /* The mask for an APU form instruction. */ | |
3891 | #define APU_MASK APU (0x3f, 0x3ff, 1) | |
3892 | #define APU_RT_MASK (APU_MASK | RT_MASK) | |
3893 | #define APU_RA_MASK (APU_MASK | RA_MASK) | |
3894 | ||
252b5132 RH |
3895 | /* The BO encodings used in extended conditional branch mnemonics. */ |
3896 | #define BODNZF (0x0) | |
3897 | #define BODNZFP (0x1) | |
3898 | #define BODZF (0x2) | |
3899 | #define BODZFP (0x3) | |
252b5132 RH |
3900 | #define BODNZT (0x8) |
3901 | #define BODNZTP (0x9) | |
3902 | #define BODZT (0xa) | |
3903 | #define BODZTP (0xb) | |
802a735e AM |
3904 | |
3905 | #define BOF (0x4) | |
3906 | #define BOFP (0x5) | |
94efba12 AM |
3907 | #define BOFM4 (0x6) |
3908 | #define BOFP4 (0x7) | |
252b5132 RH |
3909 | #define BOT (0xc) |
3910 | #define BOTP (0xd) | |
94efba12 AM |
3911 | #define BOTM4 (0xe) |
3912 | #define BOTP4 (0xf) | |
802a735e | 3913 | |
252b5132 RH |
3914 | #define BODNZ (0x10) |
3915 | #define BODNZP (0x11) | |
3916 | #define BODZ (0x12) | |
3917 | #define BODZP (0x13) | |
94efba12 AM |
3918 | #define BODNZM4 (0x18) |
3919 | #define BODNZP4 (0x19) | |
3920 | #define BODZM4 (0x1a) | |
3921 | #define BODZP4 (0x1b) | |
802a735e | 3922 | |
252b5132 RH |
3923 | #define BOU (0x14) |
3924 | ||
b9c361e0 JL |
3925 | /* The BO16 encodings used in extended VLE conditional branch mnemonics. */ |
3926 | #define BO16F (0x0) | |
3927 | #define BO16T (0x1) | |
3928 | ||
3929 | /* The BO32 encodings used in extended VLE conditional branch mnemonics. */ | |
3930 | #define BO32F (0x0) | |
3931 | #define BO32T (0x1) | |
3932 | #define BO32DNZ (0x2) | |
3933 | #define BO32DZ (0x3) | |
3934 | ||
252b5132 RH |
3935 | /* The BI condition bit encodings used in extended conditional branch |
3936 | mnemonics. */ | |
3937 | #define CBLT (0) | |
3938 | #define CBGT (1) | |
3939 | #define CBEQ (2) | |
3940 | #define CBSO (3) | |
3941 | ||
3942 | /* The TO encodings used in extended trap mnemonics. */ | |
3943 | #define TOLGT (0x1) | |
3944 | #define TOLLT (0x2) | |
3945 | #define TOEQ (0x4) | |
3946 | #define TOLGE (0x5) | |
3947 | #define TOLNL (0x5) | |
3948 | #define TOLLE (0x6) | |
3949 | #define TOLNG (0x6) | |
3950 | #define TOGT (0x8) | |
3951 | #define TOGE (0xc) | |
3952 | #define TONL (0xc) | |
3953 | #define TOLT (0x10) | |
3954 | #define TOLE (0x14) | |
3955 | #define TONG (0x14) | |
3956 | #define TONE (0x18) | |
3957 | #define TOU (0x1f) | |
3958 | \f | |
3959 | /* Smaller names for the flags so each entry in the opcodes table will | |
3960 | fit on a single line. */ | |
3961 | #undef PPC | |
de866fcc | 3962 | #define PPC PPC_OPCODE_PPC |
661bd698 | 3963 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
661bd698 | 3964 | #define POWER4 PPC_OPCODE_POWER4 |
1ed8e1e4 | 3965 | #define POWER5 PPC_OPCODE_POWER5 |
702f0fb4 | 3966 | #define POWER6 PPC_OPCODE_POWER6 |
066be9f7 | 3967 | #define POWER7 PPC_OPCODE_POWER7 |
5817ffd1 | 3968 | #define POWER8 PPC_OPCODE_POWER8 |
a680de9a | 3969 | #define POWER9 PPC_OPCODE_POWER9 |
7c1f4227 | 3970 | #define POWER10 PPC_OPCODE_POWER10 |
ede602d7 | 3971 | #define CELL PPC_OPCODE_CELL |
bdc70b4a | 3972 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE |
6b069ee7 | 3973 | #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ |
bdc70b4a | 3974 | | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
418c1742 | 3975 | #define PPC403 PPC_OPCODE_403 |
081ba1b3 | 3976 | #define PPC405 PPC_OPCODE_405 |
7d5b217e | 3977 | #define PPC440 PPC_OPCODE_440 |
c8187e15 | 3978 | #define PPC464 PPC440 |
9fe54b1c | 3979 | #define PPC476 PPC_OPCODE_476 |
ef5a96d5 | 3980 | #define PPC750 PPC_OPCODE_750 |
fa758a70 AC |
3981 | #define GEKKO PPC_OPCODE_750 |
3982 | #define BROADWAY PPC_OPCODE_750 | |
ef5a96d5 AM |
3983 | #define PPC7450 PPC_OPCODE_7450 |
3984 | #define PPC860 PPC_OPCODE_860 | |
c3d65c1c | 3985 | #define PPCPS PPC_OPCODE_PPCPS |
a404d431 | 3986 | #define PPCVEC PPC_OPCODE_ALTIVEC |
9a85b496 AM |
3987 | #define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500) |
3988 | #define PPCVEC3 PPC_OPCODE_POWER9 | |
9b4e5766 | 3989 | #define PPCVSX PPC_OPCODE_VSX |
9570835e AM |
3990 | #define PPCVSX2 PPC_OPCODE_POWER8 |
3991 | #define PPCVSX3 PPC_OPCODE_POWER9 | |
aa3c112f | 3992 | #define PPCVSX4 PPC_OPCODE_POWER10 |
de866fcc AM |
3993 | #define POWER PPC_OPCODE_POWER |
3994 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | |
81a0b7e2 | 3995 | #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON |
b80c7270 AM |
3996 | #define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \ |
3997 | | PPC_OPCODE_COMMON) | |
de866fcc | 3998 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
de866fcc | 3999 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 |
661bd698 | 4000 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON |
de866fcc | 4001 | #define MFDEC1 PPC_OPCODE_POWER |
b80c7270 AM |
4002 | #define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \ |
4003 | | PPC_OPCODE_TITAN) | |
418c1742 | 4004 | #define BOOKE PPC_OPCODE_BOOKE |
14b57c7c | 4005 | #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS |
36ae0db3 | 4006 | #define PPCE300 PPC_OPCODE_E300 |
14b57c7c | 4007 | #define PPCSPE PPC_OPCODE_SPE |
74081948 | 4008 | #define PPCSPE2 PPC_OPCODE_SPE2 |
14b57c7c AM |
4009 | #define PPCISEL PPC_OPCODE_ISEL |
4010 | #define PPCEFS PPC_OPCODE_EFS | |
74081948 | 4011 | #define PPCEFS2 PPC_OPCODE_EFS2 |
de866fcc | 4012 | #define PPCBRLK PPC_OPCODE_BRLOCK |
23976049 | 4013 | #define PPCPMR PPC_OPCODE_PMR |
aea77599 | 4014 | #define PPCTMR PPC_OPCODE_TMR |
de866fcc | 4015 | #define PPCCHLK PPC_OPCODE_CACHELCK |
fa758a70 | 4016 | #define PPCRFMCI PPC_OPCODE_RFMCI |
19a6653c | 4017 | #define E500MC PPC_OPCODE_E500MC |
634b50f2 | 4018 | #define PPCA2 PPC_OPCODE_A2 |
43e65147 | 4019 | #define TITAN PPC_OPCODE_TITAN |
62adc510 | 4020 | #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN |
e01d869a | 4021 | #define E500 PPC_OPCODE_E500 |
aea77599 | 4022 | #define E6500 PPC_OPCODE_E6500 |
b9c361e0 | 4023 | #define PPCVLE PPC_OPCODE_VLE |
ef85eab0 | 4024 | #define PPCHTM PPC_OPCODE_POWER8 |
dfdaec14 | 4025 | #define E200Z4 PPC_OPCODE_E200Z4 |
e3c2f928 | 4026 | #define PPCLSP PPC_OPCODE_LSP |
4fff86c5 PB |
4027 | /* The list of embedded processors that use the embedded operand ordering |
4028 | for the 3 operand dcbt and dcbtst instructions. */ | |
4029 | #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ | |
14b57c7c | 4030 | | PPC_OPCODE_A2) |
4fff86c5 PB |
4031 | |
4032 | ||
252b5132 RH |
4033 | \f |
4034 | /* The opcode table. | |
4035 | ||
4036 | The format of the opcode table is: | |
4037 | ||
8ebac3aa | 4038 | NAME OPCODE MASK FLAGS ANTI {OPERANDS} |
252b5132 RH |
4039 | |
4040 | NAME is the name of the instruction. | |
4041 | OPCODE is the instruction opcode. | |
4042 | MASK is the opcode mask; this is used to tell the disassembler | |
4043 | which bits in the actual opcode must match OPCODE. | |
8ebac3aa AM |
4044 | FLAGS are flags indicating which processors support the instruction. |
4045 | ANTI indicates which processors don't support the instruction. | |
252b5132 RH |
4046 | OPERANDS is the list of operands. |
4047 | ||
4048 | The disassembler reads the table in order and prints the first | |
4049 | instruction which matches, so this table is sorted to put more | |
de866fcc AM |
4050 | specific instructions before more general instructions. |
4051 | ||
4052 | This table must be sorted by major opcode. Please try to keep it | |
4053 | vaguely sorted within major opcode too, except of course where | |
4054 | constrained otherwise by disassembler operation. */ | |
252b5132 RH |
4055 | |
4056 | const struct powerpc_opcode powerpc_opcodes[] = { | |
14b57c7c AM |
4057 | {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, |
4058 | {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4059 | {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4060 | {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4061 | {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4062 | {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4063 | {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4064 | {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4065 | {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4066 | {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4067 | {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4068 | {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4069 | {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4070 | {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4071 | {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4072 | {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, | |
4073 | {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, | |
4074 | ||
4075 | {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4076 | {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4077 | {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4078 | {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4079 | {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4080 | {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4081 | {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4082 | {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4083 | {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4084 | {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4085 | {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4086 | {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4087 | {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4088 | {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4089 | {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4090 | {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4091 | {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4092 | {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4093 | {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4094 | {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4095 | {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4096 | {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4097 | {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4098 | {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4099 | {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4100 | {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4101 | {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4102 | {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4103 | {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, | |
4104 | {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, | |
4105 | {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, | |
4106 | {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, | |
4107 | ||
4108 | {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4109 | {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4110 | {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, | |
4111 | {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4112 | {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4113 | {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4114 | {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4115 | {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4116 | {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4117 | {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4118 | {"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4119 | {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, |
4120 | {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
66ef5847 AM |
4121 | {"vstribl", VXVA(4,13,0), VXVA_MASK, POWER10, 0, {VD, VB}}, |
4122 | {"vstribr", VXVA(4,13,1), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4123 | {"vstrihl", VXVA(4,13,2), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4124 | {"vstrihr", VXVA(4,13,3), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
14b57c7c AM |
4125 | {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, |
4126 | {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4127 | {"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4128 | {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
4129 | {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
fdefed7c | 4130 | {"mtvsrbmi", DX (4,10), DX_MASK, POWER10, 0, {VD, DXD}}, |
14b57c7c AM |
4131 | {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
4132 | {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
6edbfd3b | 4133 | {"vsldbi", VX (4, 22), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}}, |
14b57c7c AM |
4134 | {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
4135 | {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
6edbfd3b | 4136 | {"vextdubvlx", VX (4, 24), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c AM |
4137 | {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
4138 | {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
6edbfd3b | 4139 | {"vextdubvrx", VX (4, 25), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c AM |
4140 | {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
4141 | {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
6edbfd3b | 4142 | {"vextduhvlx", VX (4, 26), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4143 | {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
6edbfd3b | 4144 | {"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4145 | {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
6edbfd3b | 4146 | {"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4147 | {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
6edbfd3b | 4148 | {"vextduwvrx", VX (4, 29), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4149 | {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
6edbfd3b | 4150 | {"vextddvlx", VX (4, 30), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c | 4151 | {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
6edbfd3b | 4152 | {"vextddvrx", VX (4, 31), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, |
14b57c7c AM |
4153 | {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
4154 | {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4155 | {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4156 | {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4157 | {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, | |
4158 | {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
c7d7aea2 | 4159 | {"vmsumcud", VXA(4, 23), VXA_MASK, POWER10, 0, {VD, VA, VB, VC}}, |
14b57c7c AM |
4160 | {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
4161 | {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4162 | {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4163 | {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4164 | {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4165 | {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4166 | {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4167 | {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4168 | {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4169 | {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4170 | {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4171 | {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4172 | {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, | |
4173 | {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, | |
4174 | {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4175 | {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4176 | {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, | |
4177 | {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4178 | {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, | |
4179 | {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4180 | {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
4181 | {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4182 | {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
4183 | {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
4184 | {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, | |
4185 | {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, | |
4186 | {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4187 | {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, | |
4188 | {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4189 | {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4190 | {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4191 | {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4192 | {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, | |
4193 | {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4194 | {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4195 | {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4196 | {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4197 | {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4198 | {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4199 | {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, | |
4200 | {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, | |
4201 | {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4202 | {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4203 | {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4204 | {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4205 | {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4206 | {"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4207 | {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4208 | {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4209 | {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4210 | {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4211 | {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, | |
4212 | {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4213 | {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, | |
4214 | {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4215 | {"vinshvlx", VX (4, 79), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4216 | {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
4217 | {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4218 | {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4219 | {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4220 | {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4221 | {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4222 | {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4223 | {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4224 | {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4225 | {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4226 | {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4227 | {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4228 | {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4229 | {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4230 | {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4231 | {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4232 | {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
f4791f1a | 4233 | {"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4234 | {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4235 | {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4236 | {"vinswvlx", VX (4, 143), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4237 | {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
4238 | {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4239 | {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4240 | {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4241 | {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, | |
4242 | {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4243 | {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4244 | {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4245 | {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4246 | {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4247 | {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4248 | {"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
f4791f1a | 4249 | {"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4250 | {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
6edbfd3b | 4251 | {"vinsw", VX (4, 207), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}}, |
14b57c7c AM |
4252 | {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4253 | {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4254 | {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4255 | {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4256 | {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4257 | {"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, |
14b57c7c AM |
4258 | {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4259 | {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4260 | {"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4261 | {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4262 | {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4263 | {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
c7d7aea2 | 4264 | {"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4265 | {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4266 | {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4267 | {"vinsbvrx", VX (4, 271), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4268 | {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
4269 | {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4270 | {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4271 | {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4272 | {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4273 | {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4274 | {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4275 | {"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, |
14b57c7c AM |
4276 | {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4277 | {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4278 | {"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4279 | {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4280 | {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4281 | {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
4282 | {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4283 | {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4284 | {"vinshvrx", VX (4, 335), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4285 | {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
4286 | {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4287 | {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4288 | {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4289 | {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4290 | {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4291 | {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4292 | {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4293 | {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4294 | {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4295 | {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4296 | {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4297 | {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
f4791f1a | 4298 | {"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4299 | {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
66ef5847 | 4300 | {"vclrlb", VX (4, 397), VX_MASK, POWER10, 0, {VD, VA, RB}}, |
14b57c7c | 4301 | {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
6edbfd3b | 4302 | {"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}}, |
14b57c7c AM |
4303 | {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4304 | {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4305 | {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4306 | {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4307 | {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4308 | {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 AM |
4309 | {"vcmpequq", VXR(4, 455,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
4310 | {"vmulosd", VX (4, 456), VX_MASK, POWER10, 0, {VD, VA, VB}}, | |
f4791f1a | 4311 | {"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4312 | {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
f4791f1a | 4313 | {"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
66ef5847 | 4314 | {"vclrrb", VX (4, 461), VX_MASK, POWER10, 0, {VD, VA, RB}}, |
14b57c7c | 4315 | {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
6edbfd3b | 4316 | {"vinsd", VX (4, 463), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}}, |
14b57c7c AM |
4317 | {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4318 | {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4319 | {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4320 | {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4321 | {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4322 | {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4323 | {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, | |
4324 | {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, | |
4325 | {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4326 | {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4327 | {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, | |
4328 | {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4329 | {"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4330 | {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, |
4331 | {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, | |
4332 | {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4333 | {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4334 | {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4335 | {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4336 | {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4337 | {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
c7d7aea2 | 4338 | {"vdiveuq", VX (4, 523), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4339 | {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, |
4340 | {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4341 | {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, | |
4342 | {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4343 | {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4344 | {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4345 | {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4346 | {"vinsblx", VX (4, 527), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4347 | {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4348 | {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4349 | {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, | |
4350 | {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4351 | {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
6edbfd3b | 4352 | {"vsrdbi", VX (4, 534), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}}, |
14b57c7c | 4353 | {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
98553ad3 | 4354 | {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RAB}}, |
14b57c7c | 4355 | {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
98553ad3 | 4356 | {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RAB}}, |
14b57c7c | 4357 | {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
4358 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
4359 | {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4360 | {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4361 | {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4362 | {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4363 | {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4364 | {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4365 | {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4366 | {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4367 | {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4368 | {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4369 | {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, | |
4370 | {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, | |
4371 | {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, | |
4372 | {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4373 | {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4374 | {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4375 | {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4376 | {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4377 | {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4378 | {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4379 | {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4380 | {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4381 | {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, | |
4382 | {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4383 | {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4384 | {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4385 | {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4386 | {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4387 | {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4388 | {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
4389 | {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, | |
4390 | {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4391 | {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4392 | {"vinshlx", VX (4, 591), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4393 | {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
4394 | {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, | |
4395 | {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, | |
4396 | {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4397 | {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4398 | {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 | 4399 | {"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c | 4400 | {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
74081948 | 4401 | {"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
4402 | {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, |
4403 | {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4404 | {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4405 | {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4406 | {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4407 | {"vcmpgtuq", VXR(4, 647,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4408 | {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, |
14b57c7c AM |
4409 | {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4410 | {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
f4791f1a | 4411 | {"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4412 | {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
74081948 | 4413 | {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c | 4414 | {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
f4791f1a | 4415 | {"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4416 | {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
14b57c7c AM |
4417 | {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
4418 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, | |
4419 | {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4420 | {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4421 | {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4422 | {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4423 | {"vinswlx", VX (4, 655), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c | 4424 | {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, |
74081948 | 4425 | {"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4426 | {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, |
4427 | {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4428 | {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4429 | {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
74081948 | 4430 | {"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4431 | {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, |
4432 | {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4433 | {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4434 | {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4435 | {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, | |
4436 | {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, | |
4437 | {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4438 | {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
4439 | {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, | |
74081948 AF |
4440 | {"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, |
4441 | {"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4442 | {"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4443 | {"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4444 | {"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4445 | {"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4446 | {"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4447 | {"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4448 | {"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4449 | {"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4450 | {"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4451 | {"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4452 | {"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4453 | {"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4454 | {"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4455 | {"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4456 | {"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
4457 | {"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, | |
14b57c7c | 4458 | {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
74081948 | 4459 | {"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, |
14b57c7c AM |
4460 | {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
4461 | {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 | 4462 | {"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c | 4463 | {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4464 | {"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c AM |
4465 | {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, |
4466 | {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4467 | {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
4468 | {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
4469 | {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4470 | {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, |
14b57c7c | 4471 | {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
c7d7aea2 | 4472 | {"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4473 | {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
f4791f1a | 4474 | {"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4475 | {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
74081948 | 4476 | {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c | 4477 | {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
f4791f1a | 4478 | {"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4479 | {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, |
14b57c7c AM |
4480 | {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4481 | {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4482 | {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4483 | {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4484 | {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4485 | {"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4486 | {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4487 | {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 4488 | {"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4489 | {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4490 | {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4491 | {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4492 | {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 4493 | {"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4494 | {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4495 | {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4496 | {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4497 | {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4498 | {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, | |
4499 | {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4500 | {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4501 | {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4502 | {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4503 | {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
4504 | {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 AF |
4505 | {"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, |
4506 | {"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
4507 | {"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, | |
4508 | {"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
14b57c7c AM |
4509 | {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, |
4510 | {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
4511 | {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, | |
74081948 | 4512 | {"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, |
14b57c7c AM |
4513 | {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
4514 | {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, | |
74081948 AF |
4515 | {"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, |
4516 | {"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
4517 | {"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, | |
4518 | {"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}}, | |
14b57c7c AM |
4519 | {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4520 | {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4521 | {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4522 | {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 AF |
4523 | {"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4524 | {"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
4525 | {"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, | |
4526 | {"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
4527 | {"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, | |
14b57c7c AM |
4528 | {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4529 | {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4530 | {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 | 4531 | {"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, |
14b57c7c AM |
4532 | {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, |
4533 | {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
4534 | {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, | |
74081948 AF |
4535 | {"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4536 | {"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
14b57c7c | 4537 | {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
74081948 AF |
4538 | {"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, |
4539 | {"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, | |
14b57c7c AM |
4540 | {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
4541 | {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4542 | {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, | |
4543 | {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4544 | {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4545 | {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4546 | {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4547 | {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4548 | {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4549 | {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4550 | {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4551 | {"vsraq", VX (4, 773), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4552 | {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
4553 | {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4554 | {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4555 | {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4556 | {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, | |
4557 | {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4558 | {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
c7d7aea2 | 4559 | {"vdivesq", VX (4, 779), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4560 | {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4561 | {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, | |
4562 | {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4563 | {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, | |
4564 | {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4565 | {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
6edbfd3b | 4566 | {"vinsbrx", VX (4, 783), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4567 | {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, |
4568 | {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4569 | {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4570 | {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4571 | {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4572 | {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4573 | {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4574 | {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4575 | {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4576 | {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4577 | {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4578 | {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4579 | {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4580 | {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4581 | {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4582 | {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4583 | {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4584 | {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4585 | {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4586 | {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4587 | {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, | |
4588 | {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4589 | {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4590 | {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4591 | {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4592 | {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4593 | {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4594 | {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4595 | {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, | |
4596 | {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4597 | {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4598 | {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4599 | {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4600 | {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4601 | {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4602 | {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4603 | {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
4604 | {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, | |
4605 | {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
4606 | {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4607 | {"vinshrx", VX (4, 847), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4608 | {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
4609 | {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, | |
4610 | {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4611 | {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4612 | {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4613 | {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4614 | {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4615 | {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4616 | {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4617 | {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4618 | {"vcmpgtsq", VXR(4, 903,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 4619 | {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
f4791f1a | 4620 | {"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4621 | {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
4622 | {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
f4791f1a | 4623 | {"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4624 | {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, |
4625 | {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, | |
6edbfd3b | 4626 | {"vinswrx", VX (4, 911), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4627 | {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4628 | {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4629 | {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4630 | {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4631 | {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4632 | {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
c7d7aea2 | 4633 | {"vmulesd", VX (4, 968), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
f4791f1a | 4634 | {"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4635 | {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
4636 | {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, | |
f4791f1a | 4637 | {"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4638 | {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
4639 | {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, | |
6edbfd3b | 4640 | {"vinsdrx", VX (4, 975), VX_MASK, POWER10, 0, {VD, RA, RB}}, |
14b57c7c AM |
4641 | {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4642 | {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4643 | {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4644 | {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4645 | {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4646 | {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, | |
4647 | {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4648 | {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4649 | {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4650 | {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4651 | {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4652 | {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
62adc510 AM |
4653 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4654 | {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4655 | {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4656 | {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4657 | {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4658 | {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4659 | {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4660 | {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4661 | {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4662 | {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
66ef5847 AM |
4663 | {"vstribl.", VXVA(4,1037,0), VXVA_MASK, POWER10, 0, {VD, VB}}, |
4664 | {"vstribr.", VXVA(4,1037,1), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4665 | {"vstrihl.", VXVA(4,1037,2), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4666 | {"vstrihr.", VXVA(4,1037,3), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
14b57c7c AM |
4667 | {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4668 | {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4669 | {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4670 | {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4671 | {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4672 | {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4673 | {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4674 | {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4675 | {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4676 | {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4677 | {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4678 | {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4679 | {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4680 | {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4681 | {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4682 | {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, | |
4683 | {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4684 | {"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4685 | {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4686 | {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4687 | {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4688 | {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4689 | {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4690 | {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4691 | {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4692 | {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4693 | {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4694 | {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 | 4695 | {"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4696 | {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4697 | {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4698 | {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4699 | {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4700 | {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4701 | {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4702 | {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4703 | {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4704 | {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4705 | {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4706 | {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4707 | {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4708 | {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4709 | {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4710 | {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
74081948 | 4711 | {"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4712 | {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4713 | {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 | 4714 | {"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4715 | {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4716 | {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4717 | {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4718 | {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4719 | {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4720 | {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4721 | {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4722 | {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4723 | {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4724 | {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4725 | {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
98553ad3 | 4726 | {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VAB}}, |
14b57c7c AM |
4727 | {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4728 | {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4729 | {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4730 | {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4731 | {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4732 | {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4733 | {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4734 | {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4735 | {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4736 | {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4737 | {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4738 | {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4739 | {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4740 | {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4741 | {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4742 | {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4743 | {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4744 | {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4745 | {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4746 | {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 4747 | {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 4748 | {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 4749 | {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
14b57c7c AM |
4750 | {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4751 | {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4752 | {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4753 | {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4754 | {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
4755 | {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, | |
ec40e91c | 4756 | {"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}}, |
14b57c7c AM |
4757 | {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4758 | {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4759 | {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4760 | {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4761 | {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4762 | {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4763 | {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, | |
4764 | {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4765 | {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4766 | {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4767 | {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4768 | {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4769 | {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4770 | {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
98553ad3 | 4771 | {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VAB}}, |
14b57c7c AM |
4772 | {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
4773 | {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
62adc510 AM |
4774 | {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4775 | {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4776 | {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4777 | {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4778 | {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4779 | {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4780 | {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4781 | {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4782 | {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4783 | {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4784 | {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4785 | {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4786 | {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4787 | {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4788 | {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4789 | {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4790 | {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4791 | {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4792 | {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4793 | {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4794 | {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4795 | {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4796 | {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4797 | {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4798 | {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4799 | {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
74081948 AF |
4800 | {"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4801 | {"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4802 | {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4803 | {"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
62adc510 AM |
4804 | {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4805 | {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c | 4806 | {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
74081948 | 4807 | {"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4808 | {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4809 | {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4810 | {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4811 | {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4812 | {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4813 | {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4814 | {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
ec40e91c | 4815 | {"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4816 | {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 4817 | {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4818 | {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4819 | {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4820 | {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4821 | {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4822 | {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4823 | {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4824 | {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4825 | {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4826 | {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
74081948 AF |
4827 | {"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4828 | {"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4829 | {"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4830 | {"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c AM |
4831 | {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4832 | {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4833 | {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4834 | {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4835 | {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4836 | {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4837 | {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4838 | {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4839 | {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4840 | {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, | |
4841 | {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4842 | {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4843 | {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4844 | {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4845 | {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
62adc510 AM |
4846 | {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4847 | {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4848 | {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
4849 | {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4850 | {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4851 | {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4852 | {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4853 | {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
ec40e91c | 4854 | {"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4855 | {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4856 | {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4857 | {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4858 | {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4859 | {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4860 | {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4861 | {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4862 | {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4863 | {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4864 | {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4865 | {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4866 | {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, | |
4867 | {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4868 | {"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4869 | {"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4870 | {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4871 | {"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 4872 | {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
62adc510 AM |
4873 | {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, |
4874 | {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, | |
c7d7aea2 | 4875 | {"vcmpequq.", VXR(4, 455,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4876 | {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4877 | {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, |
4878 | {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4879 | {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4880 | {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4881 | {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c | 4882 | {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
ec40e91c | 4883 | {"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
74081948 | 4884 | {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c | 4885 | {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
74081948 | 4886 | {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
14b57c7c AM |
4887 | {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
4888 | {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4889 | {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4890 | {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4891 | {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
4892 | {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, | |
74081948 AF |
4893 | {"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, |
4894 | {"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4895 | {"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
4896 | {"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, | |
14b57c7c AM |
4897 | {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4898 | {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4899 | {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4900 | {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, | |
4901 | {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, | |
4902 | {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4903 | {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4904 | {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4905 | {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4906 | {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4907 | {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4908 | {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4909 | {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4910 | {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4911 | {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
c7d7aea2 | 4912 | {"vextsd2q", VXVA(4,1538,27), VXVA_MASK, POWER10, 0, {VD, VB}}, |
14b57c7c AM |
4913 | {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
4914 | {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4915 | {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4916 | {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, | |
4917 | {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, | |
4918 | {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4919 | {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4920 | {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c | 4921 | {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
c7d7aea2 | 4922 | {"vmoduq", VX (4,1547), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4923 | {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
4924 | {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
fdefed7c AM |
4925 | |
4926 | {"vexpandbm", VXVA(4,1602,0), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4927 | {"vexpandhm", VXVA(4,1602,1), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4928 | {"vexpandwm", VXVA(4,1602,2), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4929 | {"vexpanddm", VXVA(4,1602,3), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4930 | {"vexpandqm", VXVA(4,1602,4), VXVA_MASK, POWER10, 0, {VD, VB}}, | |
4931 | {"vextractbm", VXVA(4,1602,8), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
4932 | {"vextracthm", VXVA(4,1602,9), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
4933 | {"vextractwm", VXVA(4,1602,10), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
4934 | {"vextractdm", VXVA(4,1602,11), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
4935 | {"vextractqm", VXVA(4,1602,12), VXVA_MASK, POWER10, 0, {RT, VB}}, | |
4936 | {"mtvsrbm", VXVA(4,1602,16), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
4937 | {"mtvsrhm", VXVA(4,1602,17), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
4938 | {"mtvsrwm", VXVA(4,1602,18), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
4939 | {"mtvsrdm", VXVA(4,1602,19), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
4940 | {"mtvsrqm", VXVA(4,1602,20), VXVA_MASK, POWER10, 0, {VD, RB}}, | |
4941 | {"vcntmbb", VXVA(4,1602,24), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
4942 | {"vcntmbh", VXVA(4,1602,26), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
4943 | {"vcntmbw", VXVA(4,1602,28), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
4944 | {"vcntmbd", VXVA(4,1602,30), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, | |
4945 | ||
14b57c7c AM |
4946 | {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, |
4947 | {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4948 | {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4949 | {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4950 | {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4951 | {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
4952 | {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4953 | {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4954 | {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, | |
4955 | {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4956 | {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 4957 | {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
c7d7aea2 | 4958 | {"vcmpgtuq.", VXR(4, 647,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
62adc510 | 4959 | {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 4960 | {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
f4791f1a | 4961 | {"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4962 | {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
4963 | {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
4964 | {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, | |
4965 | {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, | |
4966 | {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 | 4967 | {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 4968 | {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 4969 | {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
f4791f1a | 4970 | {"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4971 | {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
4972 | {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4973 | {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4974 | {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4975 | {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4976 | {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
62adc510 AM |
4977 | {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4978 | {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c | 4979 | {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
c7d7aea2 | 4980 | {"vmodsq", VX (4,1803), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
4981 | {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
4982 | {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4983 | {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4984 | {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4985 | {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4986 | {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4987 | {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, | |
4988 | {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4989 | {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
62adc510 AM |
4990 | {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
4991 | {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, | |
14b57c7c AM |
4992 | {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
4993 | {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4994 | {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4995 | {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
4996 | {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, | |
4997 | {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
4998 | {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
ec40e91c | 4999 | {"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 5000 | {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
62adc510 | 5001 | {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
c7d7aea2 | 5002 | {"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, |
62adc510 | 5003 | {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 5004 | {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
f4791f1a | 5005 | {"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5006 | {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
5007 | {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, | |
5008 | {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5009 | {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5010 | {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
5011 | {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, | |
ec40e91c | 5012 | {"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c | 5013 | {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
62adc510 | 5014 | {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
14b57c7c | 5015 | {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
62adc510 | 5016 | {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, |
f4791f1a | 5017 | {"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}}, |
14b57c7c AM |
5018 | {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
5019 | {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5020 | {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5021 | {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, | |
5022 | {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, | |
5023 | ||
94ba9882 AM |
5024 | {"lxvp", DQXP(6,0), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, |
5025 | {"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, | |
5026 | ||
14b57c7c AM |
5027 | {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, |
5028 | {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5029 | ||
5030 | {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
5031 | {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5032 | ||
5033 | {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, | |
5034 | ||
5035 | {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, | |
5036 | {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, | |
a5721ba2 | 5037 | {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, |
14b57c7c AM |
5038 | {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, |
5039 | ||
5040 | {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, | |
5041 | {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, | |
a5721ba2 | 5042 | {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, |
14b57c7c AM |
5043 | {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, |
5044 | ||
5045 | {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
5046 | {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5047 | {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, | |
5048 | ||
5049 | {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, | |
5050 | {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, | |
5051 | {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, | |
5052 | ||
5053 | {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, | |
5054 | {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, | |
5055 | {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, | |
5056 | {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
5057 | {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, | |
5058 | {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, | |
5059 | ||
5060 | {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, | |
5061 | {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, | |
5062 | {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, | |
5063 | {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, | |
5064 | {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, | |
5065 | ||
5066 | {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5067 | {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5068 | {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, | |
5069 | {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, | |
5070 | {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5071 | {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5072 | {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, | |
5073 | {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, | |
5074 | {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5075 | {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5076 | {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, | |
5077 | {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, | |
5078 | {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5079 | {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5080 | {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, | |
5081 | {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, | |
5082 | {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5083 | {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5084 | {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}}, | |
5085 | {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, | |
5086 | {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, | |
5087 | {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}}, | |
5088 | {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5089 | {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5090 | {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}}, | |
5091 | {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, | |
5092 | {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, | |
5093 | {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}}, | |
5094 | ||
5095 | {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5096 | {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5097 | {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5098 | {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5099 | {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5100 | {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5101 | {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5102 | {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5103 | {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5104 | {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5105 | {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5106 | {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5107 | {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5108 | {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5109 | {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5110 | {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5111 | {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5112 | {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5113 | {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5114 | {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5115 | {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5116 | {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5117 | {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5118 | {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5119 | {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5120 | {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5121 | {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5122 | {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5123 | {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5124 | {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5125 | {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5126 | {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5127 | {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5128 | {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5129 | {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5130 | {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5131 | {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5132 | {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5133 | {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5134 | {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5135 | {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5136 | {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5137 | {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5138 | {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5139 | {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5140 | {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5141 | {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5142 | {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5143 | {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5144 | {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5145 | {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5146 | {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5147 | {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5148 | {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5149 | {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5150 | {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5151 | {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5152 | {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5153 | {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5154 | {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5155 | {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5156 | {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5157 | {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5158 | {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5159 | {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5160 | {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5161 | {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5162 | {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5163 | {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5164 | {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5165 | {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5166 | {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5167 | {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5168 | {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5169 | {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5170 | {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5171 | {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5172 | {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5173 | {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5174 | {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5175 | {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5176 | {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5177 | {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5178 | {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5179 | ||
5180 | {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5181 | {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5182 | {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5183 | {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5184 | {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5185 | {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5186 | {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5187 | {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5188 | {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5189 | {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5190 | {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5191 | {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5192 | {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5193 | {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5194 | {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5195 | {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5196 | {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5197 | {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5198 | {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5199 | {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5200 | {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5201 | {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5202 | {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5203 | {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5204 | {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5205 | {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5206 | {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5207 | {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5208 | {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5209 | {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5210 | {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5211 | {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5212 | {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5213 | {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5214 | {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5215 | {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5216 | {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5217 | {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5218 | {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5219 | {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5220 | {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5221 | {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5222 | {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5223 | {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5224 | {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, | |
5225 | {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, | |
5226 | {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, | |
5227 | {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, | |
5228 | {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5229 | {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5230 | {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5231 | {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5232 | {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5233 | {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5234 | {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5235 | {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5236 | {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, | |
5237 | {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, | |
5238 | {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, | |
5239 | {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, | |
5240 | ||
5241 | {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5242 | {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5243 | {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5244 | {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5245 | {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5246 | {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5247 | {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5248 | {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5249 | {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5250 | {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5251 | {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5252 | {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5253 | {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5254 | {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5255 | {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5256 | {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5257 | {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5258 | {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5259 | {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5260 | {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5261 | {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5262 | {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5263 | {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5264 | {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5265 | ||
5266 | {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5267 | {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5268 | {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5269 | {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5270 | {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5271 | {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5272 | {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5273 | {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5274 | {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5275 | {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5276 | {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5277 | {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5278 | {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5279 | {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5280 | {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5281 | {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5282 | ||
5283 | {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5284 | {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5285 | {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5286 | {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5287 | {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5288 | {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5289 | {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5290 | {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5291 | {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5292 | {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5293 | {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5294 | {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5295 | {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5296 | {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5297 | {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5298 | {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, | |
5299 | {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, | |
5300 | {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5301 | {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5302 | {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5303 | {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5304 | {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, | |
5305 | {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, | |
5306 | {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5307 | ||
5308 | {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5309 | {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5310 | {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5311 | {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5312 | {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, | |
5313 | {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, | |
5314 | {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, | |
5315 | {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, | |
5316 | {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5317 | {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5318 | {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5319 | {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5320 | {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, | |
5321 | {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, | |
5322 | {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, | |
5323 | {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, | |
5324 | ||
aae9718e PB |
5325 | {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDM}}, |
5326 | {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDP}}, | |
14b57c7c | 5327 | {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, |
aae9718e PB |
5328 | {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDM}}, |
5329 | {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDP}}, | |
14b57c7c | 5330 | {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, |
aae9718e PB |
5331 | {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDMA}}, |
5332 | {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDPA}}, | |
14b57c7c | 5333 | {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, |
aae9718e PB |
5334 | {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDMA}}, |
5335 | {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDPA}}, | |
14b57c7c AM |
5336 | {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, |
5337 | ||
5338 | {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, | |
dce75bf9 | 5339 | {"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, |
14b57c7c AM |
5340 | {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, |
5341 | {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, | |
5342 | {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, | |
5343 | {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, | |
5344 | ||
5345 | {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, | |
5346 | {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, | |
5347 | {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, | |
5348 | {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, | |
5349 | ||
5350 | {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, | |
5351 | ||
1437d063 | 5352 | {"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, |
14b57c7c AM |
5353 | {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, |
5354 | {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, | |
5355 | ||
14b57c7c | 5356 | {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
14b57c7c | 5357 | {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 AM |
5358 | {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
5359 | {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
14b57c7c | 5360 | {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 | 5361 | {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
14b57c7c | 5362 | {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
14b57c7c | 5363 | {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 AM |
5364 | {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
5365 | {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, | |
14b57c7c | 5366 | {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
66e85460 | 5367 | {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
14b57c7c AM |
5368 | {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
5369 | {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, | |
5370 | {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, | |
5371 | {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, | |
5372 | {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5373 | {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5374 | {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5375 | {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5376 | {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5377 | {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5378 | {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5379 | {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, | |
5380 | ||
14b57c7c | 5381 | {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5382 | {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5383 | {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5384 | {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5385 | {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5386 | {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5387 | {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5388 | {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5389 | {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5390 | {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5391 | {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5392 | {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5393 | {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5394 | {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5395 | {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5396 | {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5397 | {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5398 | {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5399 | {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5400 | {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5401 | {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5402 | {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5403 | {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5404 | {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5405 | {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5406 | {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5407 | {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5408 | {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5409 | {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5410 | {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5411 | {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5412 | {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5413 | {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5414 | {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5415 | {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5416 | {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5417 | {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5418 | {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5419 | {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5420 | {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5421 | {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5422 | {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5423 | {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5424 | {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5425 | {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5426 | {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5427 | {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5428 | {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5429 | {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5430 | {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5431 | {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5432 | {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5433 | {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5434 | {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5435 | {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5436 | {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5437 | {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5438 | {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5439 | {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5440 | {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5441 | {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5442 | {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5443 | {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5444 | {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5445 | {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5446 | {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5447 | {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5448 | {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5449 | {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5450 | {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5451 | {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5452 | {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5453 | {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5454 | {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5455 | {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5456 | {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5457 | {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5458 | {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5459 | {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5460 | {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5461 | {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5462 | {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
14b57c7c | 5463 | {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5464 | {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5465 | {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5466 | {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5467 | {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5468 | {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5469 | {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5470 | {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5471 | {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5472 | {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5473 | {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5474 | {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5475 | {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5476 | {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5477 | {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5478 | {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5479 | {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5480 | {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5481 | {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5482 | {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5483 | {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5484 | {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5485 | {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5486 | {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5487 | {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5488 | {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5489 | {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5490 | {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5491 | {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5492 | {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5493 | {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5494 | {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5495 | {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
5496 | {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, | |
14b57c7c | 5497 | {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
14b57c7c | 5498 | {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5499 | {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5500 | {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5501 | {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5502 | {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5503 | {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5504 | {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5505 | {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5506 | {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5507 | {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5508 | {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5509 | {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5510 | {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5511 | {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5512 | {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5513 | {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5514 | {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5515 | {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5516 | {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5517 | {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5518 | {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5519 | {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5520 | {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5521 | ||
14b57c7c | 5522 | {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5523 | {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5524 | {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5525 | {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5526 | {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5527 | {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5528 | {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5529 | {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5530 | {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5531 | {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5532 | {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5533 | {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5534 | {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5535 | {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
5536 | {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
14b57c7c | 5537 | {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
14b57c7c | 5538 | {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5539 | {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5540 | {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5541 | {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
14b57c7c AM |
5542 | {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5543 | {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5544 | {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5545 | {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
14b57c7c | 5546 | {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5547 | {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5548 | {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5549 | {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5550 | {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5551 | {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5552 | {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5553 | {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5554 | {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5555 | {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5556 | {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5557 | {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c | 5558 | {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5559 | {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
5560 | {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, | |
14b57c7c | 5561 | {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
14b57c7c | 5562 | {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5563 | {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5564 | {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5565 | {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, | |
14b57c7c AM |
5566 | {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5567 | {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5568 | {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5569 | {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5570 | ||
66e85460 AM |
5571 | {"bclr-", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, |
5572 | {"bclr+", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5573 | {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 AM |
5574 | {"bcr", XLLK(19,16,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
5575 | {"bclrl-", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, | |
5576 | {"bclrl+", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5577 | {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 | 5578 | {"bcrl", XLLK(19,16,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
14b57c7c AM |
5579 | |
5580 | {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, | |
5581 | ||
98553ad3 | 5582 | {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, |
14b57c7c AM |
5583 | {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5584 | {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, | |
5585 | ||
5586 | {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, | |
5587 | {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, | |
5588 | {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, | |
5589 | ||
dce75bf9 | 5590 | {"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, |
14b57c7c AM |
5591 | {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, |
5592 | ||
5593 | {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, | |
5594 | ||
5595 | {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5596 | ||
5597 | {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, | |
5598 | ||
5599 | {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
5600 | {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, | |
5601 | ||
98553ad3 | 5602 | {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, |
14b57c7c AM |
5603 | {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5604 | ||
5605 | {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, | |
5606 | ||
5607 | {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5608 | ||
5609 | {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5610 | ||
5611 | {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, | |
5612 | ||
98553ad3 | 5613 | {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BTAB}}, |
14b57c7c AM |
5614 | {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5615 | ||
5616 | {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, | |
5617 | {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, | |
5618 | ||
5619 | {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5620 | ||
5621 | {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, | |
5622 | ||
5623 | {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5624 | ||
98553ad3 | 5625 | {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BAB}}, |
14b57c7c AM |
5626 | {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
5627 | ||
5628 | {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5629 | {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, | |
5630 | ||
5631 | {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}}, | |
5632 | {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}}, | |
5633 | ||
14b57c7c | 5634 | {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5635 | {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5636 | {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5637 | {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5638 | {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5639 | {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5640 | {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5641 | {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5642 | {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5643 | {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5644 | {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5645 | {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5646 | {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5647 | {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5648 | {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5649 | {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5650 | {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5651 | {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5652 | {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5653 | {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5654 | {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5655 | {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5656 | {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5657 | {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5658 | {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5659 | {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5660 | {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5661 | {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5662 | {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5663 | {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5664 | {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5665 | {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5666 | {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5667 | {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5668 | {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5669 | {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5670 | {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5671 | {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5672 | {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5673 | {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5674 | {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5675 | {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5676 | {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5677 | {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5678 | {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5679 | {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5680 | {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5681 | {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5682 | {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5683 | {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5684 | {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5685 | {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5686 | {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5687 | {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5688 | {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5689 | {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5690 | {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5691 | {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5692 | {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5693 | {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5694 | {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5695 | {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5696 | {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5697 | {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5698 | {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5699 | {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5700 | {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5701 | {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5702 | {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5703 | {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
14b57c7c | 5704 | {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
14b57c7c | 5705 | {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5706 | {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5707 | {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5708 | {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5709 | {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5710 | {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5711 | {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5712 | {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5713 | {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5714 | {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5715 | {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5716 | {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5717 | {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5718 | {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5719 | {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5720 | {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5721 | {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5722 | {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5723 | {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5724 | {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5725 | {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5726 | {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5727 | {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5728 | {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5729 | {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 AM |
5730 | {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
5731 | {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, | |
14b57c7c | 5732 | {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
66e85460 | 5733 | {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
14b57c7c AM |
5734 | {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
5735 | {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5736 | {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5737 | {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5738 | {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5739 | {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5740 | {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5741 | {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5742 | {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5743 | {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5744 | {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5745 | {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5746 | {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5747 | {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5748 | {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5749 | {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5750 | {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5751 | {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5752 | {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5753 | {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, | |
5754 | ||
14b57c7c | 5755 | {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5756 | {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5757 | {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5758 | {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5759 | {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5760 | {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c AM |
5761 | {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5762 | {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5763 | {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5764 | {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
14b57c7c | 5765 | {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
14b57c7c | 5766 | {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 AM |
5767 | {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
5768 | {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, | |
14b57c7c | 5769 | {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
66e85460 | 5770 | {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
14b57c7c AM |
5771 | {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
5772 | {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5773 | {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5774 | {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, | |
5775 | ||
66e85460 AM |
5776 | {"bcctr-", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, |
5777 | {"bcctr+", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5778 | {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 AM |
5779 | {"bcc", XLLK(19,528,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
5780 | {"bcctrl-", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BOM, BI, BH}}, | |
5781 | {"bcctrl+", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5782 | {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
66e85460 | 5783 | {"bccl", XLLK(19,528,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, |
14b57c7c | 5784 | |
aae9718e PB |
5785 | {"bdnztar", XLO(19,BODNZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, |
5786 | {"bdnztarl", XLO(19,BODNZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5787 | {"bdztar", XLO(19,BODZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5788 | {"bdztarl", XLO(19,BODZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5789 | {"btar", XLO(19,BOU,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5790 | {"btarl", XLO(19,BOU,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5791 | {"bdnztar-", XLO(19,BODNZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5792 | {"bdnztarl-", XLO(19,BODNZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5793 | {"bdnztar+", XLO(19,BODNZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5794 | {"bdnztarl+", XLO(19,BODNZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5795 | {"bdztar-", XLO(19,BODZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5796 | {"bdztarl-", XLO(19,BODZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5797 | {"bdztar+", XLO(19,BODZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5798 | {"bdztarl+", XLO(19,BODZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, | |
5799 | ||
5800 | {"bgetar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5801 | {"bnltar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5802 | {"bgetarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5803 | {"bnltarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5804 | {"bletar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5805 | {"bngtar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5806 | {"bletarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5807 | {"bngtarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5808 | {"bnetar", XLOCB(19,BOF,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5809 | {"bnetarl", XLOCB(19,BOF,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5810 | {"bnstar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5811 | {"bnutar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5812 | {"bnstarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5813 | {"bnutarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5814 | {"bgetar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5815 | {"bnltar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5816 | {"bgetarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5817 | {"bnltarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5818 | {"bletar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5819 | {"bngtar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5820 | {"bletarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5821 | {"bngtarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5822 | {"bnetar-", XLOCB(19,BOFM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5823 | {"bnetarl-",XLOCB(19,BOFM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5824 | {"bnstar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5825 | {"bnutar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5826 | {"bnstarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5827 | {"bnutarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5828 | {"bgetar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5829 | {"bnltar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5830 | {"bgetarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5831 | {"bnltarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5832 | {"bletar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5833 | {"bngtar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5834 | {"bletarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5835 | {"bngtarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5836 | {"bnetar+", XLOCB(19,BOFP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5837 | {"bnetarl+",XLOCB(19,BOFP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5838 | {"bnstar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5839 | {"bnutar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5840 | {"bnstarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5841 | {"bnutarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5842 | {"blttar", XLOCB(19,BOT,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5843 | {"blttarl", XLOCB(19,BOT,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5844 | {"bgttar", XLOCB(19,BOT,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5845 | {"bgttarl", XLOCB(19,BOT,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5846 | {"beqtar", XLOCB(19,BOT,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5847 | {"beqtarl", XLOCB(19,BOT,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5848 | {"bsotar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5849 | {"buntar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5850 | {"bsotarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5851 | {"buntarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5852 | {"blttar-", XLOCB(19,BOTM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5853 | {"blttarl-",XLOCB(19,BOTM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5854 | {"bgttar-", XLOCB(19,BOTM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5855 | {"bgttarl-",XLOCB(19,BOTM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5856 | {"beqtar-", XLOCB(19,BOTM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5857 | {"beqtarl-",XLOCB(19,BOTM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5858 | {"bsotar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5859 | {"buntar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5860 | {"bsotarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5861 | {"buntarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5862 | {"blttar+", XLOCB(19,BOTP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5863 | {"blttarl+",XLOCB(19,BOTP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5864 | {"bgttar+", XLOCB(19,BOTP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5865 | {"bgttarl+",XLOCB(19,BOTP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5866 | {"beqtar+", XLOCB(19,BOTP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5867 | {"beqtarl+",XLOCB(19,BOTP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5868 | {"bsotar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5869 | {"buntar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5870 | {"bsotarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5871 | {"buntarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, | |
5872 | ||
5873 | {"bdnzftar", XLO(19,BODNZF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5874 | {"bdnzftarl", XLO(19,BODNZF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5875 | {"bdzftar", XLO(19,BODZF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5876 | {"bdzftarl", XLO(19,BODZF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5877 | ||
5878 | {"bftar", XLO(19,BOF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5879 | {"bftarl", XLO(19,BOF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5880 | {"bftar-", XLO(19,BOFM4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5881 | {"bftarl-", XLO(19,BOFM4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5882 | {"bftar+", XLO(19,BOFP4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5883 | {"bftarl+", XLO(19,BOFP4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5884 | ||
5885 | {"bdnzttar", XLO(19,BODNZT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5886 | {"bdnzttarl", XLO(19,BODNZT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5887 | {"bdzttar", XLO(19,BODZT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5888 | {"bdzttarl", XLO(19,BODZT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5889 | ||
5890 | {"bttar", XLO(19,BOT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5891 | {"bttarl", XLO(19,BOT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5892 | {"bttar-", XLO(19,BOTM4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5893 | {"bttarl-", XLO(19,BOTM4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5894 | {"bttar+", XLO(19,BOTP4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5895 | {"bttarl+", XLO(19,BOTP4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, | |
5896 | ||
66e85460 AM |
5897 | {"bctar-", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BOM, BI, BH}}, |
5898 | {"bctar+", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c | 5899 | {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, |
66e85460 AM |
5900 | {"bctarl-", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BOM, BI, BH}}, |
5901 | {"bctarl+", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BOP, BI, BH}}, | |
14b57c7c AM |
5902 | {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, |
5903 | ||
5904 | {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5905 | {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5906 | ||
5907 | {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5908 | {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5909 | ||
5910 | {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, | |
5911 | {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, | |
5912 | {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5913 | {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5914 | {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, | |
5915 | {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, | |
5916 | {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5917 | {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, | |
5918 | ||
5919 | {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5920 | {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5921 | ||
5922 | {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, | |
5923 | {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5924 | {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5925 | {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, | |
5926 | {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5927 | {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, | |
5928 | ||
5929 | {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
5930 | {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5931 | {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5932 | ||
5933 | {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5934 | {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5935 | ||
5936 | {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, | |
5937 | {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5938 | {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5939 | ||
5940 | {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5941 | {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5942 | ||
5943 | {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5944 | {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5945 | ||
5946 | {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, | |
5947 | {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, | |
5948 | ||
5949 | {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, | |
5950 | {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, | |
5951 | {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5952 | {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, | |
5953 | {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, | |
5954 | {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5955 | ||
5956 | {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, | |
5957 | {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, | |
5958 | ||
5959 | {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5960 | {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5961 | ||
5962 | {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5963 | {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, | |
5964 | ||
5965 | {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, | |
5966 | {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, | |
5967 | {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, | |
5968 | {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, | |
5969 | ||
5970 | {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, | |
5971 | {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, | |
5972 | ||
5973 | {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, | |
5974 | {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, | |
a5721ba2 | 5975 | {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
bdc70b4a | 5976 | {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
1cb0a767 | 5977 | |
14b57c7c AM |
5978 | {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
5979 | {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5980 | {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5981 | {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5982 | {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5983 | {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5984 | {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5985 | {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5986 | {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5987 | {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5988 | {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5989 | {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5990 | {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5991 | {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5992 | {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5993 | {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5994 | {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5995 | {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5996 | {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5997 | {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
5998 | {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
5999 | {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6000 | {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6001 | {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6002 | {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6003 | {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6004 | {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6005 | {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6006 | {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, | |
6007 | {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, | |
6008 | {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, | |
6009 | {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, | |
6010 | {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, | |
6011 | ||
6012 | {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6013 | {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6014 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
6015 | ||
6016 | {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6017 | {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6018 | {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
6019 | {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6020 | {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6021 | {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
6022 | ||
6023 | {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6024 | {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6025 | ||
6026 | {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6027 | {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6028 | {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6029 | {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6030 | ||
6031 | {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6032 | {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6033 | ||
6034 | {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, | |
6035 | ||
9cc4ce88 AM |
6036 | {"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6037 | ||
14b57c7c AM |
6038 | {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
6039 | ||
6040 | {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, | |
6041 | {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, | |
6042 | {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, | |
6043 | {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, | |
6044 | ||
6045 | {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, | |
6046 | {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, | |
6047 | ||
6048 | {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, | |
6049 | ||
6050 | {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, | |
6051 | ||
6052 | {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, | |
6053 | ||
6054 | {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, | |
6055 | {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6056 | ||
6057 | {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
6058 | {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
6059 | {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
6060 | {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
6061 | ||
6062 | {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
6063 | {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
6064 | {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
6065 | {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
6066 | ||
6067 | {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
6068 | {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
6069 | ||
6070 | {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, | |
6071 | {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
6072 | ||
6073 | {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, | |
6074 | {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, | |
6075 | ||
6076 | {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | |
6077 | ||
6078 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, | |
6079 | {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}}, | |
6080 | ||
6081 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | |
6082 | ||
6083 | {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, | |
6084 | {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, | |
a5721ba2 | 6085 | {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
bdc70b4a | 6086 | {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
de866fcc | 6087 | |
14b57c7c AM |
6088 | {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
6089 | {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6090 | {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6091 | |
9cc4ce88 AM |
6092 | {"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6093 | ||
ac8f0f72 | 6094 | {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, |
e67ed0e8 | 6095 | |
14b57c7c | 6096 | {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
de866fcc | 6097 | |
14b57c7c | 6098 | {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
de866fcc | 6099 | |
14b57c7c | 6100 | {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, |
066be9f7 | 6101 | |
14b57c7c | 6102 | {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
c0637f3a | 6103 | |
9cc4ce88 AM |
6104 | {"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6105 | ||
14b57c7c | 6106 | {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
de866fcc | 6107 | |
14b57c7c | 6108 | {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, |
de866fcc | 6109 | |
14b57c7c AM |
6110 | {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6111 | {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
6112 | {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6113 | {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
de866fcc | 6114 | |
14b57c7c AM |
6115 | {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, |
6116 | {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, | |
6117 | {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, | |
6118 | {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, | |
e0d602ec | 6119 | |
14b57c7c | 6120 | {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
066be9f7 | 6121 | |
14b57c7c | 6122 | {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
43e65147 | 6123 | |
14b57c7c | 6124 | {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, |
43e65147 | 6125 | |
14b57c7c AM |
6126 | {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, |
6127 | {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 6128 | |
14b57c7c AM |
6129 | {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
6130 | {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, | |
de866fcc | 6131 | |
ec40e91c AM |
6132 | {"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}}, |
6133 | ||
14b57c7c AM |
6134 | {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6135 | {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
de866fcc | 6136 | |
14b57c7c AM |
6137 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
6138 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, | |
6139 | {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, | |
43e65147 | 6140 | |
14b57c7c | 6141 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
19a6653c | 6142 | |
14b57c7c AM |
6143 | {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, |
6144 | {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6145 | {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6146 | {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6147 | {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6148 | {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6149 | {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6150 | {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6151 | {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6152 | {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6153 | {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6154 | {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6155 | {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6156 | {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6157 | {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, | |
6158 | {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, | |
de866fcc | 6159 | |
14b57c7c AM |
6160 | {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
6161 | {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6162 | {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 6163 | |
14b57c7c AM |
6164 | {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6165 | {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
de866fcc | 6166 | |
62adc510 AM |
6167 | {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, |
6168 | {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, | |
de866fcc | 6169 | |
14b57c7c | 6170 | {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, |
de866fcc | 6171 | |
14b57c7c | 6172 | {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, |
43e65147 | 6173 | |
14b57c7c | 6174 | {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, |
de866fcc | 6175 | |
c7a8dbf9 | 6176 | {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, |
a5721ba2 | 6177 | {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}}, |
de866fcc | 6178 | |
14b57c7c | 6179 | {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, |
43e65147 | 6180 | |
14b57c7c | 6181 | {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
de866fcc | 6182 | |
14b57c7c | 6183 | {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, |
aea77599 | 6184 | |
14b57c7c AM |
6185 | {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
6186 | {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6187 | |
14b57c7c AM |
6188 | {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, |
6189 | {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, | |
de866fcc | 6190 | |
14b57c7c AM |
6191 | {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6192 | {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
de866fcc | 6193 | |
9cc4ce88 AM |
6194 | {"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6195 | ||
ac8f0f72 | 6196 | {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}}, |
aea77599 | 6197 | |
14b57c7c | 6198 | {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, |
de866fcc | 6199 | |
14b57c7c AM |
6200 | {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, |
6201 | {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, | |
6202 | {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, | |
c0637f3a | 6203 | |
14b57c7c | 6204 | {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
066be9f7 | 6205 | |
14b57c7c | 6206 | {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, |
de866fcc | 6207 | |
14b57c7c | 6208 | {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, |
43e65147 | 6209 | |
14b57c7c | 6210 | {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, |
de866fcc | 6211 | |
98553ad3 | 6212 | {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 6213 | {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, |
98553ad3 | 6214 | {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 6215 | {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, |
19a6653c | 6216 | |
14b57c7c | 6217 | {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
43e65147 | 6218 | |
fd486b63 | 6219 | {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
a680de9a | 6220 | |
14b57c7c | 6221 | {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, |
43e65147 | 6222 | |
14b57c7c | 6223 | {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
de866fcc | 6224 | |
14b57c7c AM |
6225 | {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6226 | {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6227 | |
14b57c7c AM |
6228 | {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6229 | {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6230 | {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6231 | {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 6232 | |
14b57c7c AM |
6233 | {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6234 | {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6235 | {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6236 | {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
de866fcc | 6237 | |
14b57c7c | 6238 | {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
c0637f3a | 6239 | |
9cc4ce88 AM |
6240 | {"stxvrbx", X(31,141), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6241 | ||
14b57c7c AM |
6242 | {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
6243 | {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, | |
de866fcc | 6244 | |
14b57c7c AM |
6245 | {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, |
6246 | {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, | |
6247 | {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, | |
de866fcc | 6248 | |
14b57c7c | 6249 | {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, |
de866fcc | 6250 | |
14b57c7c | 6251 | {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, |
c0637f3a | 6252 | |
14b57c7c AM |
6253 | {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
6254 | {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, | |
e0d602ec | 6255 | |
14b57c7c | 6256 | {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
43e65147 | 6257 | |
14b57c7c | 6258 | {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, |
43e65147 | 6259 | |
14b57c7c AM |
6260 | {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
6261 | {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, | |
de866fcc | 6262 | |
14b57c7c AM |
6263 | {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6264 | {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
de866fcc | 6265 | |
14b57c7c AM |
6266 | {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6267 | {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
de866fcc | 6268 | |
14b57c7c | 6269 | {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, |
de866fcc | 6270 | |
3ff0a5ba | 6271 | {"brw", X(31,155), XRB_MASK, POWER10, 0, {RA, RS}}, |
ec40e91c | 6272 | {"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}}, |
3ff0a5ba | 6273 | |
14b57c7c | 6274 | {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 6275 | |
14b57c7c | 6276 | {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 6277 | |
14b57c7c | 6278 | {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, |
43e65147 | 6279 | |
14b57c7c | 6280 | {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
de866fcc | 6281 | |
14b57c7c AM |
6282 | {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6283 | {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
de866fcc | 6284 | |
14b57c7c | 6285 | {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, |
19dfcc89 | 6286 | |
9cc4ce88 AM |
6287 | {"stxvrhx", X(31,173), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6288 | ||
14b57c7c AM |
6289 | {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
6290 | {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, | |
de866fcc | 6291 | |
aa3c112f AM |
6292 | {"xxmfacc", XVA(31,177,0), XRARB_MASK|3<<21, POWER10, 0, {ACC}}, |
6293 | {"xxmtacc", XVA(31,177,1), XRARB_MASK|3<<21, POWER10, 0, {ACC}}, | |
6294 | {"xxsetaccz", XVA(31,177,3), XRARB_MASK|3<<21, POWER10, 0, {ACC}}, | |
6295 | ||
14b57c7c | 6296 | {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, |
de866fcc | 6297 | |
14b57c7c AM |
6298 | {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, |
6299 | {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, | |
6300 | {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
6301 | {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, | |
e0d602ec | 6302 | |
14b57c7c | 6303 | {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, |
de866fcc | 6304 | |
73f07bff | 6305 | {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, |
14b57c7c | 6306 | {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, |
e0d602ec | 6307 | |
14b57c7c AM |
6308 | {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, |
6309 | {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
de866fcc | 6310 | |
14b57c7c AM |
6311 | {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6312 | {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
de866fcc | 6313 | |
14b57c7c | 6314 | {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, |
252b5132 | 6315 | |
3ff0a5ba | 6316 | {"brd", X(31,187), XRB_MASK, POWER10, 0, {RA, RS}}, |
ec40e91c | 6317 | {"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}}, |
3ff0a5ba | 6318 | |
14b57c7c | 6319 | {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, |
a680de9a | 6320 | |
14b57c7c | 6321 | {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
aea77599 | 6322 | |
14b57c7c AM |
6323 | {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6324 | {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 6325 | |
14b57c7c AM |
6326 | {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6327 | {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6328 | {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6329 | {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 6330 | |
14b57c7c AM |
6331 | {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6332 | {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6333 | {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6334 | {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 6335 | |
9cc4ce88 AM |
6336 | {"stxvrwx", X(31,205), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6337 | ||
14b57c7c | 6338 | {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, |
19a6653c | 6339 | |
14b57c7c | 6340 | {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, |
418c1742 | 6341 | |
14b57c7c AM |
6342 | {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
6343 | {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
6344 | {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, | |
6345 | {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, | |
e0d602ec | 6346 | |
14b57c7c | 6347 | {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
e0d602ec | 6348 | |
14b57c7c | 6349 | {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
43e65147 | 6350 | |
14b57c7c | 6351 | {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, |
252b5132 | 6352 | |
14b57c7c AM |
6353 | {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6354 | {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6355 | |
14b57c7c AM |
6356 | {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6357 | {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 6358 | |
3ff0a5ba | 6359 | {"brh", X(31,219), XRB_MASK, POWER10, 0, {RA, RS}}, |
ec40e91c | 6360 | {"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}}, |
3ff0a5ba | 6361 | |
14b57c7c | 6362 | {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
43e65147 | 6363 | |
14b57c7c | 6364 | {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, |
a680de9a | 6365 | |
14b57c7c | 6366 | {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
7d5b217e | 6367 | |
14b57c7c AM |
6368 | {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
6369 | {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
f509565f | 6370 | |
14b57c7c AM |
6371 | {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6372 | {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6373 | {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6374 | {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 6375 | |
14b57c7c AM |
6376 | {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6377 | {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 6378 | |
14b57c7c AM |
6379 | {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
6380 | {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
6381 | {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
6382 | {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 6383 | |
14b57c7c AM |
6384 | {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6385 | {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6386 | {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6387 | {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 6388 | |
9cc4ce88 AM |
6389 | {"stxvrdx", X(31,237), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, |
6390 | ||
14b57c7c AM |
6391 | {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, |
6392 | {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, | |
6393 | {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, | |
bdc70b4a | 6394 | {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, |
418c1742 | 6395 | |
14b57c7c AM |
6396 | {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
6397 | {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, | |
6398 | {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, | |
c0637f3a | 6399 | |
14b57c7c AM |
6400 | {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
6401 | {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, | |
6402 | {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, | |
6403 | {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, | |
4fff86c5 | 6404 | |
14b57c7c | 6405 | {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, |
252b5132 | 6406 | |
14b57c7c AM |
6407 | {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6408 | {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 6409 | |
14b57c7c | 6410 | {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, |
066be9f7 | 6411 | |
14b57c7c | 6412 | {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
19a6653c | 6413 | |
14b57c7c AM |
6414 | {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, |
6415 | {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, | |
252b5132 | 6416 | |
ac8f0f72 | 6417 | {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6418 | |
14b57c7c | 6419 | {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, |
1ed8e1e4 | 6420 | |
ac8f0f72 | 6421 | {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6422 | |
14b57c7c AM |
6423 | {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
6424 | {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6425 | {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 6426 | |
14b57c7c | 6427 | {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, |
a680de9a | 6428 | |
14b57c7c AM |
6429 | {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6430 | {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
6431 | {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
6432 | {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
418c1742 | 6433 | |
14b57c7c | 6434 | {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, |
a680de9a | 6435 | |
14b57c7c AM |
6436 | {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, |
6437 | {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
a680de9a | 6438 | |
14b57c7c | 6439 | {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
19a6653c | 6440 | |
62adc510 | 6441 | {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}}, |
a5721ba2 | 6442 | {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, |
418c1742 | 6443 | |
14b57c7c | 6444 | {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, |
1cb0a767 | 6445 | |
73f07bff | 6446 | {"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, |
c0637f3a | 6447 | |
14b57c7c AM |
6448 | {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, |
6449 | {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, | |
1cb0a767 | 6450 | |
14b57c7c AM |
6451 | {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
6452 | {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, | |
6453 | {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, | |
6454 | {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, | |
4fff86c5 | 6455 | |
14b57c7c | 6456 | {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, |
1cb0a767 | 6457 | |
14b57c7c | 6458 | {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, |
066be9f7 | 6459 | |
14b57c7c AM |
6460 | {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6461 | {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 6462 | |
14b57c7c | 6463 | {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
1cb0a767 | 6464 | |
62adc510 | 6465 | {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}}, |
1cb0a767 | 6466 | |
ac8f0f72 AM |
6467 | {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}}, |
6468 | {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}}, | |
aea77599 | 6469 | |
14b57c7c | 6470 | {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 6471 | |
14b57c7c | 6472 | {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, |
c0637f3a | 6473 | |
14b57c7c AM |
6474 | {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, |
6475 | {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, | |
a5721ba2 | 6476 | {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, |
14b57c7c | 6477 | {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, |
1cb0a767 | 6478 | |
14b57c7c | 6479 | {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, |
a680de9a | 6480 | |
14b57c7c | 6481 | {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
1cb0a767 | 6482 | |
14b57c7c | 6483 | {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, |
1cb0a767 | 6484 | |
14b57c7c | 6485 | {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, |
066be9f7 | 6486 | |
14b57c7c AM |
6487 | {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6488 | {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 6489 | |
14b57c7c | 6490 | {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
1cb0a767 | 6491 | |
14b57c7c AM |
6492 | {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, |
6493 | {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, | |
6494 | {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, | |
6495 | {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, | |
6496 | {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, | |
6497 | {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, | |
6498 | {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, | |
6499 | {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, | |
6500 | {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, | |
6501 | {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, | |
6502 | {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, | |
6503 | {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, | |
6504 | {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, | |
6505 | {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, | |
6506 | {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, | |
6507 | {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, | |
6508 | {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, | |
6509 | {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, | |
6510 | {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, | |
6511 | {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, | |
6512 | {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, | |
6513 | {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, | |
6514 | {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, | |
6515 | {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, | |
6516 | {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, | |
6517 | {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, | |
6518 | {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, | |
6519 | {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, | |
6520 | {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, | |
6521 | {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, | |
6522 | {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, | |
6523 | {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, | |
6524 | {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, | |
6525 | {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, | |
6526 | {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, | |
6527 | {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, | |
1cb0a767 | 6528 | |
ac8f0f72 | 6529 | {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 6530 | |
14b57c7c | 6531 | {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, |
9fe54b1c | 6532 | |
14b57c7c AM |
6533 | {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6534 | {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
1cb0a767 | 6535 | |
14b57c7c | 6536 | {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
066be9f7 | 6537 | |
94ba9882 AM |
6538 | {"lxvpx", X(31,333), XX1_MASK, POWER10, 0, {XTP, RA0, RB}}, |
6539 | ||
14b57c7c | 6540 | {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, |
c03dc33b | 6541 | {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}}, |
1cb0a767 | 6542 | |
14b57c7c AM |
6543 | {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}}, |
6544 | ||
6545 | {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, | |
6546 | {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, | |
6547 | {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, | |
6548 | {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, | |
6549 | {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, | |
6550 | {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, | |
6551 | {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, | |
6552 | {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, | |
6553 | {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, | |
6554 | {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, | |
6555 | {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, | |
bdc70b4a | 6556 | {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, |
14b57c7c AM |
6557 | {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, |
6558 | {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, | |
6559 | {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, | |
6560 | {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, | |
6561 | {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, | |
6562 | {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, | |
6563 | {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, | |
6564 | {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, | |
6565 | {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, | |
6566 | {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, | |
6567 | {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, | |
6568 | {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, | |
6569 | {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, | |
6570 | {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, | |
6571 | {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, | |
6572 | {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, | |
6573 | {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, | |
6574 | {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, | |
6575 | {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, | |
6576 | {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, | |
6577 | {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, | |
6578 | {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, | |
6579 | {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, | |
6580 | {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, | |
6581 | {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, | |
6582 | {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, | |
6583 | {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, | |
6584 | {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, | |
6585 | {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, | |
6586 | {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, | |
6587 | {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, | |
6588 | {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6589 | {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6590 | {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6591 | {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, | |
6592 | {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, | |
6593 | {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, | |
6594 | {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, | |
6595 | {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, | |
6596 | {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, | |
6597 | {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, | |
6598 | {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, | |
6599 | {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, | |
6600 | {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, | |
6601 | {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, | |
6602 | {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, | |
6603 | {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, | |
6604 | {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, | |
6605 | {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, | |
6606 | {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, | |
6607 | {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, | |
6608 | {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, | |
6609 | {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, | |
6610 | {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, | |
6611 | {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, | |
6612 | {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, | |
6613 | {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, | |
6614 | {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, | |
6615 | {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, | |
6616 | {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, | |
6617 | {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, | |
6618 | {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, | |
6619 | {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, | |
6620 | {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, | |
6621 | {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, | |
6622 | {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, | |
6623 | {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, | |
6624 | {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, | |
6625 | {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, | |
6626 | {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, | |
6627 | {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, | |
6628 | {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, | |
6629 | {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, | |
6630 | {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, | |
6631 | {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, | |
6632 | {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, | |
6633 | {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, | |
6634 | {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, | |
6635 | {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, | |
4b94dd2d AM |
6636 | {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, |
6637 | {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0, {RT}}, | |
14b57c7c AM |
6638 | {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, |
6639 | {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, | |
4b94dd2d AM |
6640 | {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
6641 | {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, | |
14b57c7c AM |
6642 | {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
6643 | {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, | |
6644 | {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, | |
6645 | {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, | |
6646 | {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, | |
6647 | {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, | |
6648 | {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, | |
6649 | {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, | |
6650 | {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
6651 | {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
6652 | {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, | |
6653 | {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, | |
6654 | {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, | |
6655 | {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, | |
6656 | {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, | |
bb71536f AM |
6657 | {"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, |
6658 | {"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, | |
6659 | {"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, | |
6660 | {"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, | |
6661 | {"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, | |
6662 | {"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, | |
6663 | {"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, | |
6664 | {"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, | |
6665 | {"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, | |
6666 | {"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, | |
6667 | {"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, | |
6668 | {"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, | |
14b57c7c AM |
6669 | {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, |
6670 | {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, | |
6671 | {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, | |
6672 | {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, | |
6673 | {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, | |
6674 | {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, | |
6675 | {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, | |
6676 | {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, | |
6677 | {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, | |
6678 | {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, | |
6679 | {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, | |
6680 | {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, | |
6681 | {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, | |
6682 | {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, | |
6683 | {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, | |
6684 | {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, | |
6685 | {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, | |
6686 | {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, | |
6687 | {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, | |
6688 | {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, | |
6689 | {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, | |
6690 | {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, | |
6691 | {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, | |
6692 | {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, | |
6693 | {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, | |
6694 | {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, | |
6695 | {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, | |
fa758a70 AC |
6696 | {"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, 0, {RT, SPRGQR}}, |
6697 | {"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, 0, {RT}}, | |
6698 | {"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, 0, {RT}}, | |
6699 | {"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, 0, {RT}}, | |
6700 | {"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, 0, {RT}}, | |
14b57c7c AM |
6701 | {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, |
6702 | {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, | |
6703 | {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, | |
6704 | {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, | |
6705 | {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, | |
6706 | {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, | |
6707 | {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, | |
6708 | {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, | |
6709 | {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, | |
6710 | {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, | |
6711 | {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, | |
6712 | {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, | |
6713 | {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, | |
6714 | {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, | |
6715 | {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, | |
6716 | {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, | |
6717 | {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, | |
6718 | {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, | |
6719 | {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, | |
6720 | {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, | |
6721 | {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, | |
6722 | {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, | |
6723 | {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, | |
6724 | {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, | |
6725 | {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, | |
6726 | {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, | |
6727 | {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, | |
6728 | {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, | |
6729 | {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, | |
6730 | {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, | |
6731 | {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, | |
6732 | {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, | |
6733 | {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, | |
6734 | {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, | |
6735 | {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, | |
6736 | {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, | |
6737 | {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, | |
6738 | {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, | |
6739 | {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, | |
6740 | {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, | |
6741 | {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, | |
6742 | {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, | |
6743 | {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, | |
6744 | {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, | |
fa758a70 AC |
6745 | {"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, 0, {RT}}, |
6746 | {"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, 0, {RT}}, | |
14b57c7c | 6747 | {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, |
fa758a70 AC |
6748 | {"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, 0, {RT}}, |
6749 | {"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, 0, {RT}}, | |
14b57c7c AM |
6750 | {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, |
6751 | {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, | |
6752 | {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, | |
fa758a70 | 6753 | {"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, 0, {RT}}, |
14b57c7c AM |
6754 | {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, |
6755 | {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, | |
6756 | {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, | |
6757 | {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, | |
6758 | {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, | |
6759 | {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, | |
6760 | {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, | |
6761 | {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, | |
6762 | {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, | |
6763 | {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, | |
6764 | {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, | |
6765 | {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, | |
6766 | {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, | |
6767 | {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, | |
6768 | ||
6769 | {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, | |
6770 | ||
6771 | {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, | |
6772 | ||
6773 | {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, | |
6774 | ||
6775 | {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, | |
6776 | ||
6777 | {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, | |
6778 | {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, | |
6779 | ||
6780 | {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6781 | {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
6782 | ||
6783 | {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
6784 | ||
6785 | {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, | |
1cb0a767 | 6786 | |
db76a700 | 6787 | {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
14b57c7c | 6788 | {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, |
db76a700 | 6789 | {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
1cb0a767 | 6790 | |
14b57c7c | 6791 | {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
1cb0a767 | 6792 | |
14b57c7c | 6793 | {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
1cb0a767 | 6794 | |
14b57c7c | 6795 | {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, |
1cb0a767 | 6796 | |
14b57c7c | 6797 | {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
066be9f7 | 6798 | |
4f3e9537 PB |
6799 | {"setbc", X(31,384), XRB_MASK, POWER10, 0, {RT, BI}}, |
6800 | ||
14b57c7c AM |
6801 | {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, |
6802 | {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, | |
1cb0a767 | 6803 | |
ac8f0f72 | 6804 | {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6805 | |
14b57c7c AM |
6806 | {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
6807 | {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
1cb0a767 | 6808 | |
14b57c7c AM |
6809 | {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6810 | {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6811 | {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6812 | {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 6813 | |
14b57c7c AM |
6814 | {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
6815 | {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
a680de9a | 6816 | |
14b57c7c | 6817 | {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
1cb0a767 | 6818 | |
14b57c7c | 6819 | {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, |
1cb0a767 | 6820 | |
14b57c7c | 6821 | {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, |
a680de9a | 6822 | |
14b57c7c | 6823 | {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, |
c0637f3a | 6824 | |
14b57c7c AM |
6825 | {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, |
6826 | {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, | |
e0d602ec | 6827 | |
14b57c7c | 6828 | {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, |
1cb0a767 | 6829 | |
14b57c7c AM |
6830 | {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, |
6831 | {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
1cb0a767 | 6832 | |
14b57c7c | 6833 | {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
1cb0a767 | 6834 | |
4f3e9537 PB |
6835 | {"setbcr", X(31,416), XRB_MASK, POWER10, 0, {RT, BI}}, |
6836 | ||
62adc510 | 6837 | {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}}, |
1cb0a767 | 6838 | |
ac8f0f72 | 6839 | {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 6840 | |
14b57c7c | 6841 | {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
aea77599 | 6842 | |
14b57c7c AM |
6843 | {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6844 | {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6845 | {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
6846 | {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 6847 | |
14b57c7c | 6848 | {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
a680de9a | 6849 | |
14b57c7c | 6850 | {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}}, |
c0637f3a | 6851 | |
14b57c7c | 6852 | {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, |
1cb0a767 | 6853 | |
14b57c7c | 6854 | {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 6855 | |
14b57c7c | 6856 | {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
1cb0a767 | 6857 | |
14b57c7c | 6858 | {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, |
1cb0a767 | 6859 | |
14b57c7c | 6860 | {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}}, |
1cb0a767 | 6861 | |
14b57c7c | 6862 | {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}}, |
aea77599 | 6863 | |
9f6a6cc0 | 6864 | /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for |
14b57c7c AM |
6865 | "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ |
6866 | {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}}, | |
6867 | {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}}, | |
6868 | {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}}, | |
98553ad3 | 6869 | {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c | 6870 | {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, |
98553ad3 | 6871 | {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RSB}}, |
14b57c7c AM |
6872 | {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, |
6873 | ||
4f3e9537 PB |
6874 | {"setnbc", X(31,448), XRB_MASK, POWER10, 0, {RT, BI}}, |
6875 | ||
14b57c7c AM |
6876 | {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, |
6877 | {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, | |
6878 | {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, | |
6879 | {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, | |
6880 | {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, | |
6881 | {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, | |
6882 | {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, | |
6883 | {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, | |
6884 | {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, | |
6885 | {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, | |
6886 | {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, | |
6887 | {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, | |
6888 | {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, | |
6889 | {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, | |
6890 | {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, | |
6891 | {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, | |
6892 | {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, | |
6893 | {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, | |
6894 | {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, | |
6895 | {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, | |
6896 | {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, | |
6897 | {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, | |
6898 | {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, | |
6899 | {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, | |
6900 | {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, | |
6901 | {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, | |
6902 | {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, | |
6903 | {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, | |
6904 | {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, | |
6905 | {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, | |
6906 | {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, | |
6907 | {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, | |
6908 | {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, | |
6909 | {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, | |
6910 | {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, | |
6911 | {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, | |
6912 | ||
ac8f0f72 | 6913 | {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}}, |
14b57c7c | 6914 | |
62adc510 | 6915 | {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
14b57c7c AM |
6916 | {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
6917 | ||
6918 | {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6919 | {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
6920 | ||
6921 | {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6922 | {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
6923 | ||
94ba9882 AM |
6924 | {"stxvpx", X(31,461), XX1_MASK, POWER10, 0, {XTP, RA0, RB}}, |
6925 | ||
14b57c7c | 6926 | {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, |
c03dc33b | 6927 | {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}}, |
14b57c7c AM |
6928 | |
6929 | {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, | |
6930 | ||
6931 | {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, | |
6932 | {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, | |
6933 | {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, | |
6934 | {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, | |
6935 | {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, | |
6936 | {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, | |
6937 | {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, | |
6938 | {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, | |
6939 | {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, | |
6940 | {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, | |
6941 | {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, | |
6942 | {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, | |
6943 | {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, | |
6944 | {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, | |
6945 | {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, | |
6946 | {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, | |
6947 | {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, | |
6948 | {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, | |
6949 | {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, | |
6950 | {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, | |
6951 | {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, | |
6952 | {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, | |
6953 | {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, | |
6954 | {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, | |
6955 | {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, | |
6956 | {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, | |
6957 | {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, | |
6958 | {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, | |
6959 | {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, | |
6960 | {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, | |
6961 | {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, | |
6962 | {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, | |
6963 | {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, | |
6964 | {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, | |
6965 | {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, | |
6966 | {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, | |
6967 | {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, | |
6968 | {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, | |
6969 | {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, | |
6970 | {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, | |
6971 | {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, | |
6972 | {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, | |
6973 | {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, | |
6974 | {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, | |
6975 | {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, | |
6976 | {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, | |
6977 | {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, | |
6978 | {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6979 | {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6980 | {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6981 | {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, | |
6982 | {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, | |
6983 | {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, | |
6984 | {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, | |
6985 | {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, | |
6986 | {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, | |
6987 | {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, | |
6988 | {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, | |
6989 | {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, | |
6990 | {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, | |
6991 | {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, | |
6992 | {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, | |
6993 | {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, | |
6994 | {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, | |
6995 | {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, | |
6996 | {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, | |
6997 | {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, | |
6998 | {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, | |
6999 | {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, | |
7000 | {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, | |
7001 | {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, | |
7002 | {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, | |
7003 | {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, | |
7004 | {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, | |
7005 | {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, | |
7006 | {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, | |
7007 | {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, | |
7008 | {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, | |
7009 | {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, | |
7010 | {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, | |
7011 | {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, | |
7012 | {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, | |
7013 | {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, | |
7014 | {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, | |
7015 | {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, | |
7016 | {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, | |
7017 | {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, | |
7018 | {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, | |
4b94dd2d AM |
7019 | {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, |
7020 | {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0, {RS}}, | |
14b57c7c AM |
7021 | {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, |
7022 | {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, | |
4b94dd2d AM |
7023 | {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
7024 | {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, | |
14b57c7c AM |
7025 | {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
7026 | {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, | |
7027 | {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
7028 | {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
7029 | {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, | |
bb71536f AM |
7030 | {"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}}, |
7031 | {"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}}, | |
7032 | {"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}}, | |
7033 | {"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}}, | |
7034 | {"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}}, | |
7035 | {"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}}, | |
14b57c7c AM |
7036 | {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, |
7037 | {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, | |
7038 | {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, | |
7039 | {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, | |
7040 | {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, | |
7041 | {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, | |
7042 | {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, | |
7043 | {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, | |
fa758a70 AC |
7044 | {"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, 0, {SPRGQR, RS}}, |
7045 | {"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, 0, {RS}}, | |
7046 | {"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, 0, {RS}}, | |
7047 | {"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, 0, {RS}}, | |
7048 | {"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, 0, {RS}}, | |
14b57c7c AM |
7049 | {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, |
7050 | {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, | |
7051 | {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, | |
7052 | {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, | |
7053 | {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, | |
7054 | {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, | |
7055 | {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, | |
7056 | {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, | |
7057 | {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, | |
7058 | {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, | |
7059 | {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, | |
7060 | {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, | |
7061 | {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, | |
7062 | {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, | |
7063 | {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, | |
7064 | {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, | |
7065 | {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, | |
7066 | {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, | |
7067 | {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, | |
7068 | {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, | |
7069 | {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, | |
7070 | {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, | |
7071 | {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, | |
7072 | {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, | |
7073 | {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, | |
7074 | {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, | |
7075 | {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, | |
7076 | {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, | |
7077 | {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, | |
7078 | {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, | |
7079 | {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, | |
7080 | {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, | |
7081 | {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, | |
7082 | {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, | |
7083 | {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, | |
7084 | {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, | |
7085 | {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, | |
7086 | {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, | |
7087 | {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, | |
7088 | {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, | |
fa758a70 AC |
7089 | {"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, 0, {RS}}, |
7090 | {"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, 0, {RS}}, | |
14b57c7c | 7091 | {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, |
fa758a70 AC |
7092 | {"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, 0, {RS}}, |
7093 | {"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, 0, {RS}}, | |
7094 | {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, | |
14b57c7c AM |
7095 | {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, |
7096 | {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, | |
fa758a70 | 7097 | {"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, 0, {RS}}, |
14b57c7c AM |
7098 | {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, |
7099 | {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, | |
7100 | {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, | |
7101 | {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, | |
7102 | {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, | |
7103 | {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, | |
7104 | {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, | |
7105 | {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, | |
7106 | {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, | |
7107 | {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, | |
7108 | {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, | |
7109 | {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, | |
7110 | {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, | |
7111 | {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, | |
7112 | ||
7113 | {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, | |
7114 | ||
7115 | {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, | |
7116 | {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, | |
7117 | ||
4f3e9537 PB |
7118 | {"setnbcr", X(31,480), XRB_MASK, POWER10, 0, {RT, BI}}, |
7119 | ||
14b57c7c AM |
7120 | {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, |
7121 | ||
62adc510 | 7122 | {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}}, |
14b57c7c AM |
7123 | |
7124 | {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, | |
7125 | ||
7126 | {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, | |
7127 | ||
7128 | {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, | |
7129 | {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, | |
7130 | ||
7131 | {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
7132 | {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
7133 | ||
7134 | {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7135 | {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7136 | ||
7137 | {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, | |
7138 | ||
7139 | {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}}, | |
4bc0608a | 7140 | {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, |
1cb0a767 | 7141 | |
14b57c7c | 7142 | {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, |
1cb0a767 | 7143 | |
14b57c7c | 7144 | {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
066be9f7 | 7145 | |
14b57c7c | 7146 | {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, |
1cb0a767 | 7147 | |
14b57c7c | 7148 | {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, |
252b5132 | 7149 | |
dfdaec14 | 7150 | {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 7151 | {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 7152 | |
14b57c7c | 7153 | {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}}, |
252b5132 | 7154 | |
14b57c7c AM |
7155 | {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, |
7156 | {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7157 | |
14b57c7c AM |
7158 | {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7159 | {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7160 | {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
7161 | {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7162 | {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7163 | {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, | |
43e65147 | 7164 | |
14b57c7c AM |
7165 | {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7166 | {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7167 | {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7168 | {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7169 | |
14b57c7c | 7170 | {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
c0637f3a | 7171 | |
14b57c7c | 7172 | {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, |
418c1742 | 7173 | |
14b57c7c | 7174 | {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, |
418c1742 | 7175 | |
14b57c7c AM |
7176 | {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, |
7177 | {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7178 | |
14b57c7c AM |
7179 | {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, |
7180 | {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7181 | |
14b57c7c | 7182 | {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
702f0fb4 | 7183 | |
14b57c7c AM |
7184 | {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
7185 | {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
7186 | {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
7187 | {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
252b5132 | 7188 | |
14b57c7c AM |
7189 | {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7190 | {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
23976049 | 7191 | |
14b57c7c AM |
7192 | {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
7193 | {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, | |
a680de9a | 7194 | |
14b57c7c AM |
7195 | {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
7196 | {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
f509565f | 7197 | |
14b57c7c AM |
7198 | {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7199 | {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7200 | |
dfdaec14 | 7201 | {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 7202 | {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 7203 | |
ac8f0f72 | 7204 | {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7205 | |
14b57c7c | 7206 | {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, |
418c1742 | 7207 | |
14b57c7c AM |
7208 | {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, |
7209 | {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7210 | |
14b57c7c AM |
7211 | {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
7212 | {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
7213 | {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
7214 | {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, | |
252b5132 | 7215 | |
14b57c7c | 7216 | {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, |
252b5132 | 7217 | |
14b57c7c | 7218 | {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 7219 | |
14b57c7c AM |
7220 | {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
7221 | {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, | |
a680de9a | 7222 | |
ec40e91c AM |
7223 | {"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}}, |
7224 | ||
14b57c7c | 7225 | {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, |
a680de9a | 7226 | |
dfdaec14 | 7227 | {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
a8cc8a54 | 7228 | {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, |
19a6653c | 7229 | |
ac8f0f72 | 7230 | {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7231 | |
14b57c7c | 7232 | {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
a680de9a | 7233 | |
14b57c7c | 7234 | {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7235 | |
14b57c7c | 7236 | {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
066be9f7 | 7237 | |
14b57c7c | 7238 | {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, |
252b5132 | 7239 | |
14b57c7c AM |
7240 | {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, |
7241 | {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, | |
252b5132 | 7242 | |
dc302c00 | 7243 | {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, |
e01d869a | 7244 | {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, |
14b57c7c | 7245 | {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, |
fd486b63 PB |
7246 | {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, |
7247 | {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, | |
14b57c7c AM |
7248 | {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, |
7249 | {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, | |
7250 | {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, | |
7251 | {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}}, | |
418c1742 | 7252 | |
14b57c7c | 7253 | {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
23976049 | 7254 | |
066be9f7 | 7255 | {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, |
14b57c7c | 7256 | {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, |
252b5132 | 7257 | |
14b57c7c | 7258 | {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, |
19a6653c | 7259 | |
ac8f0f72 | 7260 | {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7261 | |
14b57c7c | 7262 | {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
a680de9a | 7263 | |
14b57c7c | 7264 | {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7265 | |
14b57c7c AM |
7266 | {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, |
7267 | {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, | |
252b5132 | 7268 | |
14b57c7c AM |
7269 | {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7270 | {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7271 | |
14b57c7c | 7272 | {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, |
252b5132 | 7273 | |
14b57c7c | 7274 | {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, |
252b5132 | 7275 | |
14b57c7c | 7276 | {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
252b5132 | 7277 | |
dfdaec14 | 7278 | {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 7279 | {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 7280 | |
14b57c7c AM |
7281 | {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, |
7282 | {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
23976049 | 7283 | |
14b57c7c | 7284 | {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
c0637f3a | 7285 | |
14b57c7c | 7286 | {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, |
5817ffd1 | 7287 | |
14b57c7c AM |
7288 | {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7289 | {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7290 | {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7291 | {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7292 | |
14b57c7c AM |
7293 | {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7294 | {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7295 | {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7296 | {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7297 | |
14b57c7c | 7298 | {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, |
418c1742 | 7299 | |
14b57c7c | 7300 | {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, |
252b5132 | 7301 | |
14b57c7c AM |
7302 | {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, |
7303 | {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
418c1742 | 7304 | |
14b57c7c AM |
7305 | {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
7306 | {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, | |
252b5132 | 7307 | |
14b57c7c | 7308 | {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
ede602d7 | 7309 | |
14b57c7c AM |
7310 | {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7311 | {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7312 | |
14b57c7c AM |
7313 | {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7314 | {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7315 | |
dfdaec14 | 7316 | {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 7317 | {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 7318 | |
ac8f0f72 | 7319 | {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7320 | |
14b57c7c AM |
7321 | {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, |
7322 | {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7323 | |
14b57c7c AM |
7324 | {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, |
7325 | {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, | |
5817ffd1 | 7326 | |
14b57c7c | 7327 | {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
066be9f7 | 7328 | |
14b57c7c | 7329 | {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 7330 | |
14b57c7c AM |
7331 | {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, |
7332 | {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 7333 | |
dfdaec14 | 7334 | {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
a8cc8a54 | 7335 | {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, |
19a6653c | 7336 | |
ac8f0f72 | 7337 | {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7338 | |
14b57c7c | 7339 | {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
a680de9a | 7340 | |
14b57c7c | 7341 | {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7342 | |
14b57c7c | 7343 | {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
066be9f7 | 7344 | |
14b57c7c | 7345 | {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, |
5817ffd1 | 7346 | |
14b57c7c AM |
7347 | {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7348 | {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7349 | {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7350 | {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 7351 | |
14b57c7c AM |
7352 | {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7353 | {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7354 | {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7355 | {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
fdd12ef3 | 7356 | |
14b57c7c AM |
7357 | {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, |
7358 | {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, | |
252b5132 | 7359 | |
14b57c7c | 7360 | {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
066be9f7 | 7361 | |
14b57c7c | 7362 | {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
252b5132 | 7363 | |
14b57c7c AM |
7364 | {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7365 | {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
418c1742 | 7366 | |
14b57c7c AM |
7367 | {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7368 | {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7369 | |
066be9f7 | 7370 | {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, |
14b57c7c | 7371 | {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, |
252b5132 | 7372 | |
14b57c7c | 7373 | {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, |
19a6653c | 7374 | |
ac8f0f72 | 7375 | {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7376 | |
14b57c7c | 7377 | {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
a680de9a | 7378 | |
14b57c7c | 7379 | {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
081ba1b3 | 7380 | |
14b57c7c AM |
7381 | {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7382 | {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7383 | {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7384 | {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
252b5132 | 7385 | |
14b57c7c AM |
7386 | {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
7387 | {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
252b5132 | 7388 | |
14b57c7c AM |
7389 | {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
7390 | {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
7391 | {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, | |
7392 | {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, | |
418c1742 | 7393 | |
14b57c7c AM |
7394 | {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7395 | {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7396 | {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7397 | {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
702f0fb4 | 7398 | |
14b57c7c AM |
7399 | {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
7400 | {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}}, | |
7401 | {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, | |
5817ffd1 | 7402 | |
14b57c7c | 7403 | {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, |
a680de9a | 7404 | |
14b57c7c AM |
7405 | {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
7406 | {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, | |
252b5132 | 7407 | |
14b57c7c | 7408 | {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
252b5132 | 7409 | |
14b57c7c AM |
7410 | {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, |
7411 | {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 7412 | |
ac8f0f72 | 7413 | {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}}, |
a680de9a | 7414 | |
fd486b63 | 7415 | {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, |
a680de9a | 7416 | |
ac8f0f72 | 7417 | {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}}, |
14b57c7c AM |
7418 | {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, |
7419 | {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
ede602d7 | 7420 | |
14b57c7c AM |
7421 | {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7422 | {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7423 | |
14b57c7c AM |
7424 | {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
7425 | {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
7426 | {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, | |
7427 | {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, | |
252b5132 | 7428 | |
14b57c7c AM |
7429 | {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, |
7430 | {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, | |
a680de9a | 7431 | |
14b57c7c AM |
7432 | {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
7433 | {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
066be9f7 | 7434 | |
14b57c7c | 7435 | {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
5817ffd1 | 7436 | |
14b57c7c | 7437 | {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
252b5132 | 7438 | |
14b57c7c | 7439 | {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 7440 | |
14b57c7c | 7441 | {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, |
252b5132 | 7442 | |
73f07bff | 7443 | {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, |
14b57c7c | 7444 | {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
418c1742 | 7445 | |
14b57c7c AM |
7446 | {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
7447 | {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
7448 | {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, | |
7449 | {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, | |
fdd12ef3 | 7450 | |
14b57c7c AM |
7451 | {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
7452 | {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, | |
252b5132 | 7453 | |
74081948 | 7454 | {"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, |
14b57c7c | 7455 | {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, |
19a6653c | 7456 | |
ac8f0f72 AM |
7457 | {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, |
7458 | {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}}, | |
14b57c7c | 7459 | {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, |
252b5132 | 7460 | |
14b57c7c AM |
7461 | {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
7462 | {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, | |
a680de9a | 7463 | |
14b57c7c | 7464 | {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
5817ffd1 | 7465 | |
14b57c7c | 7466 | {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, |
252b5132 | 7467 | |
14b57c7c | 7468 | {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, |
e0d602ec | 7469 | |
14b57c7c | 7470 | {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 7471 | |
14b57c7c | 7472 | {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, |
252b5132 | 7473 | |
14b57c7c | 7474 | {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
fdd12ef3 | 7475 | |
14b57c7c AM |
7476 | {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, |
7477 | {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, | |
7478 | {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, | |
7479 | {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, | |
702f0fb4 | 7480 | |
14b57c7c AM |
7481 | {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, |
7482 | {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, | |
e0c21649 | 7483 | |
ac8f0f72 | 7484 | {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7485 | |
fd486b63 | 7486 | {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, |
a680de9a | 7487 | |
14b57c7c AM |
7488 | {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7489 | {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7490 | |
14b57c7c | 7491 | {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
a680de9a | 7492 | {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, |
9b4e5766 | 7493 | |
14b57c7c | 7494 | {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
5817ffd1 | 7495 | |
14b57c7c | 7496 | {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, |
e0d602ec | 7497 | |
1224c05d PB |
7498 | {"slbiag", X(31,850), XRLARB_MASK, POWER10, 0, {RS, A_L}}, |
7499 | {"slbiag", X(31,850), XRARB_MASK, POWER9, POWER10, {RS}}, | |
7500 | ||
14b57c7c | 7501 | {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
a680de9a | 7502 | {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
252b5132 | 7503 | |
14b57c7c | 7504 | {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
418c1742 | 7505 | |
9fe54b1c | 7506 | {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, |
14b57c7c AM |
7507 | {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, |
7508 | {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, | |
7509 | {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, | |
418c1742 | 7510 | |
14b57c7c | 7511 | {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, |
418c1742 | 7512 | |
ac8f0f72 | 7513 | {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}}, |
aea77599 | 7514 | |
14b57c7c AM |
7515 | {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
7516 | {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, | |
702f0fb4 | 7517 | |
14b57c7c AM |
7518 | {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
7519 | {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, | |
252b5132 | 7520 | |
14b57c7c | 7521 | {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
a680de9a | 7522 | |
14b57c7c | 7523 | {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
5817ffd1 | 7524 | |
14b57c7c | 7525 | {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, |
a680de9a | 7526 | |
14b57c7c | 7527 | {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
252b5132 | 7528 | |
14b57c7c | 7529 | {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}}, |
a680de9a | 7530 | |
14b57c7c | 7531 | {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, |
066be9f7 | 7532 | |
14b57c7c AM |
7533 | {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, |
7534 | {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, | |
a680de9a | 7535 | |
afef4fe9 PB |
7536 | {"paste.", XRC(31,902,1), XLRT_MASK, POWER10, 0, {RA0, RB, L1OPT}}, |
7537 | {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, POWER10, {RA0, RB}}, | |
a680de9a | 7538 | |
14b57c7c AM |
7539 | {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, |
7540 | {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, | |
252b5132 | 7541 | |
14b57c7c AM |
7542 | {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
7543 | {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7544 | {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7545 | {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 7546 | |
14b57c7c AM |
7547 | {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
7548 | {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
066be9f7 | 7549 | |
14b57c7c | 7550 | {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
5817ffd1 | 7551 | |
14b57c7c AM |
7552 | {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, |
7553 | {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, | |
252b5132 | 7554 | |
14b57c7c | 7555 | {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
a680de9a | 7556 | {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
702f0fb4 | 7557 | |
14b57c7c | 7558 | {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
f5c120c5 | 7559 | |
14b57c7c | 7560 | {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, |
252b5132 | 7561 | |
73f07bff | 7562 | {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, |
14b57c7c | 7563 | {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, |
6ba045b1 | 7564 | |
14b57c7c AM |
7565 | {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7566 | {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
702f0fb4 | 7567 | |
14b57c7c AM |
7568 | {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, |
7569 | {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, | |
252b5132 | 7570 | |
14b57c7c AM |
7571 | {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, |
7572 | {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
7573 | {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, | |
7574 | {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, | |
702f0fb4 | 7575 | |
74081948 | 7576 | {"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, |
14b57c7c | 7577 | {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, |
19a6653c | 7578 | |
ac8f0f72 | 7579 | {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7580 | |
14b57c7c | 7581 | {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, |
a5721ba2 AM |
7582 | {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}}, |
7583 | {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, | |
85d4ac0b | 7584 | |
14b57c7c | 7585 | {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6ba045b1 | 7586 | |
14b57c7c AM |
7587 | {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
7588 | {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7589 | {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
7590 | {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, | |
066be9f7 | 7591 | |
14b57c7c AM |
7592 | {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
7593 | {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, | |
a680de9a | 7594 | |
14b57c7c | 7595 | {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
5817ffd1 | 7596 | |
e0d602ec BE |
7597 | {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, |
7598 | {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, | |
14b57c7c | 7599 | {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, |
702f0fb4 | 7600 | |
14b57c7c | 7601 | {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
252b5132 | 7602 | |
14b57c7c AM |
7603 | {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, |
7604 | {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, | |
51b5d4a8 | 7605 | |
14b57c7c | 7606 | {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, |
252b5132 | 7607 | |
14b57c7c AM |
7608 | {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, |
7609 | {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, | |
252b5132 | 7610 | |
14b57c7c AM |
7611 | {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, |
7612 | {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, | |
252b5132 | 7613 | |
ac8f0f72 | 7614 | {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7615 | |
62adc510 | 7616 | {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
14b57c7c | 7617 | {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
43e65147 | 7618 | |
14b57c7c AM |
7619 | {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
7620 | {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 7621 | |
14b57c7c AM |
7622 | {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
7623 | {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
252b5132 | 7624 | |
14b57c7c | 7625 | {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
a680de9a | 7626 | {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, |
9b4e5766 | 7627 | |
9fe54b1c | 7628 | {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, |
14b57c7c AM |
7629 | {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, |
7630 | {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, | |
7631 | {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, | |
418c1742 | 7632 | |
14b57c7c | 7633 | {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, |
c4e676f1 | 7634 | |
14b57c7c | 7635 | {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
252b5132 | 7636 | |
14b57c7c | 7637 | {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, |
252b5132 | 7638 | |
14b57c7c | 7639 | {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, |
702f0fb4 | 7640 | |
14b57c7c AM |
7641 | {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
7642 | {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, | |
252b5132 | 7643 | |
14b57c7c | 7644 | {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
19a6653c | 7645 | |
ac8f0f72 | 7646 | {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}}, |
aea77599 | 7647 | |
14b57c7c | 7648 | {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, |
252b5132 | 7649 | |
14b57c7c AM |
7650 | {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
7651 | {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, | |
252b5132 | 7652 | |
14b57c7c AM |
7653 | {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
7654 | {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, | |
43e65147 | 7655 | |
14b57c7c AM |
7656 | {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
7657 | {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, | |
418c1742 | 7658 | |
14b57c7c | 7659 | {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
a680de9a | 7660 | |
14b57c7c | 7661 | {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
702f0fb4 | 7662 | |
14b57c7c | 7663 | {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, |
252b5132 | 7664 | |
14b57c7c | 7665 | {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
418c1742 | 7666 | |
14b57c7c AM |
7667 | {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, |
7668 | {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, | |
786e2c0f | 7669 | |
14b57c7c | 7670 | {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
ede602d7 | 7671 | |
14b57c7c | 7672 | {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, |
252b5132 | 7673 | |
14b57c7c AM |
7674 | {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}}, |
7675 | {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}}, | |
7676 | {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}}, | |
252b5132 | 7677 | |
14b57c7c AM |
7678 | {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
7679 | {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, | |
7680 | {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, | |
252b5132 | 7681 | |
14b57c7c AM |
7682 | {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}}, |
7683 | {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}}, | |
7684 | {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}}, | |
7685 | {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}}, | |
252b5132 | 7686 | |
14b57c7c AM |
7687 | {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, |
7688 | {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 7689 | |
14b57c7c AM |
7690 | {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, |
7691 | {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 7692 | |
14b57c7c | 7693 | {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 7694 | |
14b57c7c | 7695 | {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 7696 | |
14b57c7c AM |
7697 | {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
7698 | {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 7699 | |
14b57c7c AM |
7700 | {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, |
7701 | {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 7702 | |
14b57c7c | 7703 | {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
252b5132 | 7704 | |
14b57c7c | 7705 | {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
252b5132 | 7706 | |
14b57c7c | 7707 | {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 7708 | |
14b57c7c | 7709 | {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 7710 | |
14b57c7c | 7711 | {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
252b5132 | 7712 | |
14b57c7c | 7713 | {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
252b5132 | 7714 | |
14b57c7c | 7715 | {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
252b5132 | 7716 | |
14b57c7c | 7717 | {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
252b5132 | 7718 | |
14b57c7c AM |
7719 | {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, |
7720 | {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, | |
252b5132 | 7721 | |
14b57c7c AM |
7722 | {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
7723 | {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, | |
252b5132 | 7724 | |
14b57c7c | 7725 | {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
252b5132 | 7726 | |
14b57c7c | 7727 | {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
252b5132 | 7728 | |
14b57c7c | 7729 | {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
252b5132 | 7730 | |
14b57c7c | 7731 | {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
252b5132 | 7732 | |
14b57c7c | 7733 | {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
adadcc0c | 7734 | |
14b57c7c | 7735 | {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
252b5132 | 7736 | |
14b57c7c | 7737 | {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
c3d65c1c | 7738 | |
14b57c7c | 7739 | {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
252b5132 | 7740 | |
73f07bff | 7741 | {"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, |
14b57c7c AM |
7742 | {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
7743 | {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, | |
418c1742 | 7744 | |
14b57c7c AM |
7745 | {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, |
7746 | {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, | |
73f07bff | 7747 | {"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, |
14b57c7c AM |
7748 | {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
7749 | {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, | |
802a735e | 7750 | |
14b57c7c AM |
7751 | {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, |
7752 | {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, | |
7753 | {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, | |
702f0fb4 | 7754 | |
14b57c7c AM |
7755 | {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
7756 | {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7757 | |
14b57c7c AM |
7758 | {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, |
7759 | {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, | |
252b5132 | 7760 | |
aa3c112f AM |
7761 | {"xvi8ger4pp", XX3(59,2), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7762 | {"xvi8ger4", XX3(59,3), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7763 | ||
14b57c7c AM |
7764 | {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7765 | {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7766 | |
14b57c7c AM |
7767 | {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7768 | {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7769 | |
14b57c7c AM |
7770 | {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
7771 | {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
252b5132 | 7772 | |
14b57c7c AM |
7773 | {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, |
7774 | {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, | |
252b5132 | 7775 | |
14b57c7c AM |
7776 | {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7777 | {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7778 | {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7779 | {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
1ed8e1e4 | 7780 | |
14b57c7c AM |
7781 | {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
7782 | {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, | |
252b5132 | 7783 | |
14b57c7c AM |
7784 | {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
7785 | {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
7786 | {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7787 | {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
252b5132 | 7788 | |
14b57c7c AM |
7789 | {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7790 | {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7791 | |
14b57c7c AM |
7792 | {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7793 | {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 7794 | |
14b57c7c AM |
7795 | {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7796 | {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 7797 | |
14b57c7c AM |
7798 | {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
7799 | {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
702f0fb4 | 7800 | |
14b57c7c AM |
7801 | {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
7802 | {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
702f0fb4 | 7803 | |
14b57c7c AM |
7804 | {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, |
7805 | {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, | |
702f0fb4 | 7806 | |
14b57c7c AM |
7807 | {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
7808 | {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, | |
702f0fb4 | 7809 | |
14b57c7c AM |
7810 | {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, |
7811 | {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, | |
702f0fb4 | 7812 | |
aa3c112f AM |
7813 | {"xvf16ger2pp", XX3(59,18), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7814 | {"xvf16ger2", XX3(59,19), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7815 | ||
14b57c7c AM |
7816 | {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
7817 | {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, | |
702f0fb4 | 7818 | |
14b57c7c AM |
7819 | {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, |
7820 | {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
702f0fb4 | 7821 | |
aa3c112f AM |
7822 | {"xvf32gerpp", XX3(59,26), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7823 | {"xvf32ger", XX3(59,27), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7824 | ||
14b57c7c | 7825 | {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
702f0fb4 | 7826 | |
aa3c112f AM |
7827 | {"xvi4ger8pp", XX3(59,34), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7828 | {"xvi4ger8", XX3(59,35), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7829 | ||
14b57c7c | 7830 | {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
aa3c112f AM |
7831 | |
7832 | {"xvi16ger2spp", XX3(59,42), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7833 | {"xvi16ger2s", XX3(59,43), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7834 | ||
14b57c7c | 7835 | {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, |
aa3c112f AM |
7836 | |
7837 | {"xvbf16ger2pp",XX3(59,50), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7838 | {"xvbf16ger2", XX3(59,51), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7839 | ||
14b57c7c AM |
7840 | {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, |
7841 | ||
7842 | {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
7843 | {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, | |
7844 | ||
aa3c112f AM |
7845 | {"xvf64gerpp", XX3(59,58), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, |
7846 | {"xvf64ger", XX3(59,59), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, | |
7847 | ||
14b57c7c AM |
7848 | {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
7849 | {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7850 | ||
7851 | {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7852 | {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7853 | ||
7854 | {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, | |
7855 | {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, | |
7856 | ||
aa3c112f AM |
7857 | {"xvi16ger2", XX3(59,75), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7858 | ||
7859 | {"xvf16ger2np", XX3(59,82), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7860 | ||
14b57c7c AM |
7861 | {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
7862 | {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7863 | ||
aa3c112f AM |
7864 | {"xvf32gernp", XX3(59,90), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7865 | ||
7866 | {"xvi8ger4spp", XX3(59,99), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7867 | ||
7868 | {"xvi16ger2pp", XX3(59,107), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7869 | ||
7870 | {"xvbf16ger2np",XX3(59,114), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7871 | ||
7872 | {"xvf64gernp", XX3(59,122), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, | |
7873 | ||
14b57c7c AM |
7874 | {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
7875 | {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7876 | ||
7877 | {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7878 | {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7879 | ||
aa3c112f AM |
7880 | {"xvf16ger2pn", XX3(59,146), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7881 | ||
7882 | {"xvf32gerpn", XX3(59,154), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7883 | ||
14b57c7c AM |
7884 | {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
7885 | ||
7886 | {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, | |
7887 | {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, | |
7888 | ||
aa3c112f AM |
7889 | {"xvbf16ger2pn",XX3(59,178), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7890 | ||
7891 | {"xvf64gerpn", XX3(59,186), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, | |
7892 | ||
14b57c7c AM |
7893 | {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
7894 | {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, | |
7895 | ||
7896 | {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7897 | {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
7898 | ||
7899 | {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, | |
7900 | {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, | |
7901 | ||
aa3c112f AM |
7902 | {"xvf16ger2nn", XX3(59,210), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7903 | ||
14b57c7c AM |
7904 | {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
7905 | {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
7906 | ||
7907 | {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7908 | {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, | |
7909 | ||
aa3c112f AM |
7910 | {"xvf32gernn", XX3(59,218), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, |
7911 | ||
7912 | {"xvbf16ger2nn",XX3(59,242), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, | |
7913 | ||
14b57c7c AM |
7914 | {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
7915 | {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
7916 | ||
aa3c112f AM |
7917 | {"xvf64gernn", XX3(59,250), XX3_MASK|3<<21, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, |
7918 | ||
14b57c7c AM |
7919 | {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
7920 | {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7921 | {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, | |
7922 | {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7923 | {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7924 | {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7925 | {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, | |
7926 | {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7927 | {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
98553ad3 | 7928 | {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XAB6, DMEX}}, |
14b57c7c | 7929 | {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
98553ad3 | 7930 | {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
7931 | {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
7932 | {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, | |
7933 | {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7934 | {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
7935 | {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7936 | {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7937 | {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7938 | {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7939 | {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7940 | {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
7941 | {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7942 | {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7943 | {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7944 | {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7945 | {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7946 | {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7947 | {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7948 | {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7949 | {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7950 | {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7951 | {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7952 | {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7953 | {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7954 | {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7955 | {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7956 | {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7957 | {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7958 | {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7959 | {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
7960 | {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7961 | {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7962 | {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7963 | {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
7964 | {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, | |
7965 | {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7966 | {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
7967 | {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7968 | {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7969 | {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7970 | {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7971 | {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7972 | {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7973 | {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7974 | {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7975 | {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7976 | {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7977 | {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7978 | {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7979 | {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7980 | {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7981 | {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7982 | {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7983 | {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7984 | {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, | |
7985 | {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, | |
7986 | {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7987 | {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7988 | {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7989 | {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7990 | {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
7991 | {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7992 | {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7993 | {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
7994 | {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, | |
6edbfd3b | 7995 | {"lxvkq", XVA(60,360,31), XVA_MASK&~1, POWER10, PPCVLE, {XT6, UIM5}}, |
14b57c7c AM |
7996 | {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, |
7997 | {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7998 | {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
7999 | {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
8000 | {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8001 | {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8002 | {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8003 | {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8004 | {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8005 | {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8006 | {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8007 | {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8008 | {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8009 | {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8010 | {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8011 | {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8012 | {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8013 | {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8014 | {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8015 | {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8016 | {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8017 | {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8018 | {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8019 | {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8020 | {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8021 | {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, | |
8022 | {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8023 | {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8024 | {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8025 | {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8026 | {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8027 | {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, | |
8028 | {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8029 | {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8030 | {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8031 | {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8032 | {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8033 | {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8034 | {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8035 | {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8036 | {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8037 | {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8038 | {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8039 | {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8040 | {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8041 | {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, | |
8042 | {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8043 | {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8044 | {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8045 | {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8046 | {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8047 | {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8048 | {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8049 | {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8050 | {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8051 | {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, | |
8052 | {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8053 | {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8054 | {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8055 | {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8056 | {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8057 | {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, | |
8058 | {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, | |
8059 | {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8060 | {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8061 | {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8062 | {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8063 | {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8064 | {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8065 | {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8066 | {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, | |
8067 | {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8068 | {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, | |
8069 | {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8070 | {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8071 | {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8072 | {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8073 | {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8074 | {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8075 | {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8076 | {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8077 | {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8078 | {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
98553ad3 | 8079 | {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
8080 | {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
8081 | {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8082 | {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8083 | {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8084 | {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, | |
8085 | {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8086 | {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8087 | {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8088 | {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8089 | {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8090 | {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8091 | {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8092 | {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
d7e97a76 AM |
8093 | {"xxgenpcvbm", X(60,916), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, |
8094 | {"xxgenpcvhm", X(60,917), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, | |
14b57c7c AM |
8095 | {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, |
8096 | {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8097 | {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8098 | {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8099 | {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
d7e97a76 AM |
8100 | {"xxgenpcvwm", X(60,948), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, |
8101 | {"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, | |
14b57c7c AM |
8102 | {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
8103 | {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
5d57bc3f | 8104 | {"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {OBF, XB6}}, |
14b57c7c AM |
8105 | {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
8106 | {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8107 | {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8108 | {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
aa3c112f AM |
8109 | {"xvcvbf16sp", XX2VA(60,475,16),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}}, |
8110 | {"xvcvspbf16", XX2VA(60,475,17),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}}, | |
14b57c7c AM |
8111 | {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
8112 | {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8113 | {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
8114 | {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, | |
98553ad3 | 8115 | {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XAB6}}, |
14b57c7c AM |
8116 | {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
8117 | {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8118 | {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8119 | {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8120 | {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, | |
8121 | {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, | |
8122 | {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, | |
8123 | {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8124 | {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, | |
8125 | ||
8126 | {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, | |
8127 | {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, | |
8128 | ||
8129 | {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, | |
8130 | {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, | |
8131 | {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, | |
8132 | {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, | |
73f07bff | 8133 | {"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, |
14b57c7c AM |
8134 | {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, |
8135 | {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, | |
8136 | ||
8137 | {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, | |
8138 | {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, | |
73f07bff | 8139 | {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, |
14b57c7c AM |
8140 | |
8141 | {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, | |
8142 | ||
73f07bff AM |
8143 | {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8144 | {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
14b57c7c | 8145 | |
73f07bff AM |
8146 | {"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, |
8147 | {"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, | |
14b57c7c AM |
8148 | |
8149 | {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
8150 | {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
8151 | ||
8152 | {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, | |
8153 | {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, | |
8154 | ||
8155 | {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, | |
8156 | {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, | |
8157 | ||
8158 | {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8159 | {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8160 | ||
8161 | {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8162 | {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8163 | {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8164 | {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8165 | ||
8166 | {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8167 | {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8168 | {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
8169 | {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, | |
8170 | ||
8171 | {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8172 | {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8173 | {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8174 | {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8175 | ||
8176 | {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8177 | {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8178 | {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8179 | {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8180 | ||
8181 | {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8182 | {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8183 | {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, | |
8184 | {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, | |
8185 | ||
8186 | {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, | |
8187 | {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, | |
8188 | ||
8189 | {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8190 | {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8191 | ||
8192 | {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8193 | {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
8194 | {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8195 | {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
1ed8e1e4 | 8196 | |
14b57c7c AM |
8197 | {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
8198 | {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, | |
8199 | {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, | |
8200 | {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, | |
252b5132 | 8201 | |
14b57c7c AM |
8202 | {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
8203 | {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
8204 | {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8205 | {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, | |
252b5132 | 8206 | |
14b57c7c AM |
8207 | {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8208 | {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8209 | {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8210 | {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8211 | |
14b57c7c AM |
8212 | {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8213 | {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8214 | {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8215 | {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8216 | |
14b57c7c AM |
8217 | {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8218 | {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8219 | {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8220 | {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8221 | |
14b57c7c AM |
8222 | {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
8223 | {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8224 | {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, | |
8225 | {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, | |
252b5132 | 8226 | |
14b57c7c | 8227 | {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, |
252b5132 | 8228 | |
73f07bff AM |
8229 | {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8230 | {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 8231 | |
73f07bff AM |
8232 | {"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, |
8233 | {"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, | |
702f0fb4 | 8234 | |
14b57c7c AM |
8235 | {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8236 | {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8237 | |
14b57c7c | 8238 | {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, |
a680de9a | 8239 | |
96a86c01 AM |
8240 | {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BTF}}, |
8241 | {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BTF}}, | |
252b5132 | 8242 | |
14b57c7c AM |
8243 | {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8244 | {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8245 | |
14b57c7c | 8246 | {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, |
252b5132 | 8247 | |
73f07bff AM |
8248 | {"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
8249 | {"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 8250 | |
73f07bff AM |
8251 | {"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, |
8252 | {"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, | |
702f0fb4 | 8253 | |
3b646889 AM |
8254 | {"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8255 | ||
96a86c01 AM |
8256 | {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BTF}}, |
8257 | {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BTF}}, | |
252b5132 | 8258 | |
14b57c7c AM |
8259 | {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8260 | {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8261 | |
73f07bff AM |
8262 | {"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
8263 | {"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, | |
702f0fb4 | 8264 | |
73f07bff AM |
8265 | {"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
8266 | {"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 8267 | |
14b57c7c | 8268 | {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
a680de9a | 8269 | |
14b57c7c | 8270 | {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, |
066be9f7 | 8271 | |
14b57c7c | 8272 | {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
702f0fb4 | 8273 | |
14b57c7c | 8274 | {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 8275 | |
14b57c7c AM |
8276 | {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, |
8277 | {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, | |
8278 | {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, | |
8279 | {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, | |
252b5132 | 8280 | |
14b57c7c AM |
8281 | {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8282 | {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8283 | |
14b57c7c AM |
8284 | {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
8285 | {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8286 | {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
8287 | {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 8288 | |
14b57c7c | 8289 | {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, |
066be9f7 | 8290 | |
14b57c7c | 8291 | {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
a680de9a | 8292 | |
14b57c7c | 8293 | {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 8294 | |
14b57c7c | 8295 | {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, |
3b646889 AM |
8296 | |
8297 | {"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, | |
8298 | ||
14b57c7c | 8299 | {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, |
702f0fb4 | 8300 | |
73f07bff AM |
8301 | {"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
8302 | {"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, | |
702f0fb4 | 8303 | |
3b646889 AM |
8304 | {"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8305 | ||
73f07bff AM |
8306 | {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
8307 | {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, | |
702f0fb4 | 8308 | |
14b57c7c AM |
8309 | {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
8310 | {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, | |
252b5132 | 8311 | |
14b57c7c AM |
8312 | {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
8313 | {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, | |
702f0fb4 | 8314 | |
73f07bff AM |
8315 | {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, |
8316 | {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, | |
702f0fb4 | 8317 | |
14b57c7c AM |
8318 | {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
8319 | {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, | |
702f0fb4 | 8320 | |
14b57c7c AM |
8321 | {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8322 | {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8323 | |
14b57c7c AM |
8324 | {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8325 | {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 8326 | |
14b57c7c AM |
8327 | {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8328 | {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8329 | |
14b57c7c AM |
8330 | {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8331 | {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 8332 | |
14b57c7c AM |
8333 | {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8334 | {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8335 | |
14b57c7c AM |
8336 | {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8337 | {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
a680de9a | 8338 | |
14b57c7c AM |
8339 | {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8340 | {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8341 | |
14b57c7c AM |
8342 | {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
8343 | {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, | |
ce7a772b | 8344 | |
73f07bff AM |
8345 | {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8346 | {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 8347 | |
14b57c7c AM |
8348 | {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8349 | {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8350 | |
73f07bff AM |
8351 | {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
8352 | {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, | |
702f0fb4 | 8353 | |
14b57c7c AM |
8354 | {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
8355 | {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, | |
a680de9a | 8356 | |
14b57c7c AM |
8357 | {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, |
8358 | {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, | |
252b5132 | 8359 | |
6fd3a02d PB |
8360 | {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, |
8361 | {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, | |
8362 | {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, | |
8363 | {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, | |
8364 | {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, | |
8365 | {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, | |
8366 | ||
14b57c7c | 8367 | {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
702f0fb4 | 8368 | |
14b57c7c | 8369 | {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
a680de9a | 8370 | |
14b57c7c AM |
8371 | {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, |
8372 | {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, | |
a680de9a | 8373 | |
3b646889 AM |
8374 | {"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8375 | ||
14b57c7c | 8376 | {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, |
702f0fb4 | 8377 | |
14b57c7c AM |
8378 | {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, |
8379 | {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, | |
8380 | {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, | |
8381 | {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, | |
252b5132 | 8382 | |
3b646889 AM |
8383 | {"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, |
8384 | ||
73f07bff AM |
8385 | {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, |
8386 | {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, | |
702f0fb4 | 8387 | |
73f07bff AM |
8388 | {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
8389 | {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, | |
702f0fb4 | 8390 | |
14b57c7c AM |
8391 | {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8392 | {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8393 | {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8394 | {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8395 | {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8396 | {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8397 | {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
a680de9a | 8398 | |
14b57c7c AM |
8399 | {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
8400 | {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
8401 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
8402 | {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 8403 | |
14b57c7c AM |
8404 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
8405 | {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
8406 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
8407 | {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 8408 | |
73f07bff AM |
8409 | {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, |
8410 | {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, | |
702f0fb4 | 8411 | |
c7d7aea2 | 8412 | {"xscvqpuqz", XVA(63,836,0), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, |
14b57c7c AM |
8413 | {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8414 | {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
c7d7aea2 AM |
8415 | {"xscvuqqp", XVA(63,836,3), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, |
8416 | {"xscvqpsqz", XVA(63,836,8), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, | |
14b57c7c AM |
8417 | {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8418 | {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
c7d7aea2 | 8419 | {"xscvsqqp", XVA(63,836,11), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, |
14b57c7c AM |
8420 | {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
8421 | {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8422 | {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8423 | {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
8424 | {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, | |
a680de9a | 8425 | |
14b57c7c | 8426 | {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
c0637f3a | 8427 | |
14b57c7c AM |
8428 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
8429 | {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
8430 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, | |
8431 | {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, | |
252b5132 | 8432 | |
73f07bff AM |
8433 | {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, |
8434 | {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, | |
702f0fb4 | 8435 | |
14b57c7c | 8436 | {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
a680de9a | 8437 | |
14b57c7c AM |
8438 | {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8439 | {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 8440 | |
14b57c7c AM |
8441 | {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8442 | {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
066be9f7 | 8443 | |
14b57c7c | 8444 | {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
c0637f3a | 8445 | |
14b57c7c AM |
8446 | {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
8447 | {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, | |
c7d7aea2 AM |
8448 | |
8449 | {"dcffixqq", XVA(63,994,0), XVA_MASK, POWER10, PPCVLE, {FRTp, VB}}, | |
8450 | {"dctfixqq", XVA(63,994,1), XVA_MASK, POWER10, PPCVLE, {VD, FRBp}}, | |
252b5132 RH |
8451 | }; |
8452 | ||
2ceb7719 | 8453 | const unsigned int powerpc_num_opcodes = |
252b5132 RH |
8454 | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
8455 | \f | |
dd7efa79 PB |
8456 | /* The opcode table for 8-byte prefix instructions. |
8457 | ||
8458 | The format of this opcode table is the same as the main opcode table. */ | |
8459 | ||
8460 | const struct powerpc_opcode prefix_opcodes[] = { | |
7c1f4227 AM |
8461 | {"pnop", PMRR, PREFIX_MASK, POWER10, 0, {0}}, |
8462 | {"pli", PMLS|OP(14), P_DRAPCREL_MASK, POWER10, 0, {RT, SI34}}, | |
8463 | {"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL0}}, | |
8464 | {"psubi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, NSI34, PCREL0}}, | |
8465 | {"pla", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
6edbfd3b AM |
8466 | {"xxsplti32dx", P8RR|VSOP(32,0), P_VSI_MASK, POWER10, 0, {XTS, IX, IMM32}}, |
8467 | {"xxspltidp", P8RR|VSOP(32,2), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, | |
8468 | {"xxspltiw", P8RR|VSOP(32,3), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, | |
7c1f4227 | 8469 | {"plwz", PMLS|OP(32), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, |
6edbfd3b AM |
8470 | {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, |
8471 | {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, | |
8472 | {"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, | |
8473 | {"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, | |
8474 | {"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}}, | |
ec40e91c | 8475 | {"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}}, |
7c1f4227 AM |
8476 | {"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, |
8477 | {"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
8478 | {"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
8479 | {"plhz", PMLS|OP(40), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
8480 | {"plwa", P8LS|OP(41), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
8481 | {"plxsd", P8LS|OP(42), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}}, | |
8482 | {"plha", PMLS|OP(42), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
8483 | {"plxssp", P8LS|OP(43), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}}, | |
8484 | {"psth", PMLS|OP(44), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
8485 | {"pstxsd", P8LS|OP(46), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}}, | |
8486 | {"pstxssp", P8LS|OP(47), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}}, | |
8487 | {"plfs", PMLS|OP(48), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}}, | |
8488 | {"plxv", P8LS|OP(50), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}}, | |
8489 | {"plfd", PMLS|OP(50), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}}, | |
8490 | {"pstfs", PMLS|OP(52), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}}, | |
8491 | {"pstxv", P8LS|OP(54), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}}, | |
8492 | {"pstfd", PMLS|OP(54), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}}, | |
8493 | {"plq", P8LS|OP(56), P_D_MASK, POWER10, 0, {RTQ, D34, PRAQ, PCREL}}, | |
8494 | {"pld", P8LS|OP(57), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, | |
94ba9882 | 8495 | {"plxvp", P8LS|OP(58), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}}, |
aa3c112f AM |
8496 | {"pmxvi8ger4pp", PMMIRR|XX3(59,2), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, |
8497 | {"pmxvi8ger4", PMMIRR|XX3(59,3), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, | |
8498 | {"pmxvf16ger2pp", PMMIRR|XX3(59,18), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8499 | {"pmxvf16ger2", PMMIRR|XX3(59,19), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8500 | {"pmxvf32gerpp", PMMIRR|XX3(59,26), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8501 | {"pmxvf32ger", PMMIRR|XX3(59,27), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8502 | {"pmxvi4ger8pp", PMMIRR|XX3(59,34), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}}, | |
8503 | {"pmxvi4ger8", PMMIRR|XX3(59,35), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}}, | |
8504 | {"pmxvi16ger2spp",PMMIRR|XX3(59,42), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8505 | {"pmxvi16ger2s", PMMIRR|XX3(59,43), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8506 | {"pmxvbf16ger2pp",PMMIRR|XX3(59,50), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8507 | {"pmxvbf16ger2", PMMIRR|XX3(59,51), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8508 | {"pmxvf64gerpp", PMMIRR|XX3(59,58), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8509 | {"pmxvf64ger", PMMIRR|XX3(59,59), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8510 | {"pmxvi16ger2", PMMIRR|XX3(59,75), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8511 | {"pmxvf16ger2np", PMMIRR|XX3(59,82), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8512 | {"pmxvf32gernp", PMMIRR|XX3(59,90), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8513 | {"pmxvi8ger4spp", PMMIRR|XX3(59,99), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, | |
8514 | {"pmxvi16ger2pp", PMMIRR|XX3(59,107), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8515 | {"pmxvbf16ger2np",PMMIRR|XX3(59,114), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8516 | {"pmxvf64gernp", PMMIRR|XX3(59,122), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8517 | {"pmxvf16ger2pn", PMMIRR|XX3(59,146), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8518 | {"pmxvf32gerpn", PMMIRR|XX3(59,154), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8519 | {"pmxvbf16ger2pn",PMMIRR|XX3(59,178), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8520 | {"pmxvf64gerpn", PMMIRR|XX3(59,186), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
8521 | {"pmxvf16ger2nn", PMMIRR|XX3(59,210), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8522 | {"pmxvf32gernn", PMMIRR|XX3(59,218), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, | |
8523 | {"pmxvbf16ger2nn",PMMIRR|XX3(59,242), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, | |
8524 | {"pmxvf64gernn", PMMIRR|XX3(59,250), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, | |
7c1f4227 AM |
8525 | {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}}, |
8526 | {"pstd", P8LS|OP(61), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, | |
94ba9882 | 8527 | {"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}}, |
dd7efa79 PB |
8528 | }; |
8529 | ||
8530 | const unsigned int prefix_num_opcodes = | |
8531 | sizeof (prefix_opcodes) / sizeof (prefix_opcodes[0]); | |
8532 | \f | |
b9c361e0 JL |
8533 | /* The VLE opcode table. |
8534 | ||
8535 | The format of this opcode table is the same as the main opcode table. */ | |
8536 | ||
8537 | const struct powerpc_opcode vle_opcodes[] = { | |
14b57c7c AM |
8538 | {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, |
8539 | {"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, | |
8540 | {"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, | |
8541 | {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, | |
8542 | {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, | |
8543 | {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, | |
8544 | {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, | |
8545 | {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, | |
8546 | {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, | |
8547 | {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, | |
8548 | {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, | |
a8cc8a54 | 8549 | {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}}, |
14b57c7c AM |
8550 | {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, |
8551 | {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8552 | {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8553 | {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8554 | {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8555 | {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8556 | {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8557 | {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8558 | {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8559 | {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, | |
8560 | {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8561 | {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, | |
8562 | {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, | |
8563 | {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8564 | {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8565 | {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8566 | {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8567 | {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8568 | {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8569 | {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8570 | {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
8571 | ||
e3c2f928 AF |
8572 | /* by major opcode */ |
8573 | {"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8574 | {"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8575 | {"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8576 | {"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8577 | {"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8578 | {"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8579 | {"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8580 | {"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8581 | {"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8582 | {"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8583 | {"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8584 | {"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8585 | {"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8586 | {"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8587 | {"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8588 | {"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8589 | {"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8590 | {"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8591 | {"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8592 | {"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8593 | {"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8594 | {"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8595 | {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8596 | {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8597 | {"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8598 | {"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8599 | {"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8600 | {"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8601 | {"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8602 | {"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8603 | {"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8604 | {"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8605 | {"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8606 | {"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8607 | {"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8608 | {"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8609 | {"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8610 | {"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8611 | {"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8612 | {"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8613 | {"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, | |
8614 | {"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8615 | {"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8616 | {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8617 | {"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8618 | {"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8619 | {"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8620 | {"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8621 | {"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, | |
8622 | {"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, | |
8623 | {"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8624 | {"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8625 | {"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8626 | {"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8627 | {"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8628 | {"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8629 | {"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8630 | {"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8631 | {"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8632 | {"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8633 | {"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8634 | {"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8635 | {"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8636 | {"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8637 | {"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8638 | {"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8639 | {"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8640 | {"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8641 | {"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8642 | {"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8643 | {"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8644 | {"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, | |
8645 | {"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8646 | {"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8647 | {"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8648 | {"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8649 | {"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}}, | |
8650 | {"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8651 | {"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8652 | {"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8653 | {"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8654 | {"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8655 | {"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8656 | {"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8657 | {"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8658 | {"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8659 | {"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8660 | {"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8661 | {"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8662 | {"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8663 | {"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8664 | {"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, | |
8665 | {"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8666 | {"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8667 | {"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8668 | {"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, | |
8669 | {"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8670 | {"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8671 | {"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8672 | {"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8673 | {"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8674 | {"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8675 | {"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8676 | {"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8677 | {"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8678 | {"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8679 | {"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8680 | {"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8681 | {"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8682 | {"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8683 | {"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8684 | {"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8685 | {"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8686 | {"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8687 | {"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8688 | {"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8689 | {"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8690 | {"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8691 | {"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8692 | {"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8693 | {"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8694 | {"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8695 | {"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, | |
8696 | {"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8697 | {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8698 | {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8699 | {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8700 | {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8701 | {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8702 | {"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8703 | {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8704 | {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8705 | {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8706 | {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8707 | {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8708 | {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8709 | {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8710 | {"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8711 | {"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8712 | {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8713 | {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8714 | {"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8715 | {"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8716 | {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8717 | {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8718 | {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8719 | {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8720 | {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8721 | {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8722 | {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8723 | {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8724 | {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8725 | {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8726 | {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8727 | {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8728 | {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8729 | {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8730 | {"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8731 | {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8732 | {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8733 | {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8734 | {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8735 | {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8736 | {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8737 | {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8738 | {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8739 | {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8740 | {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8741 | {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8742 | {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8743 | {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8744 | {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8745 | {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8746 | {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8747 | {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8748 | {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8749 | {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8750 | {"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8751 | {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8752 | {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8753 | {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8754 | {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8755 | {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8756 | {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8757 | {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8758 | {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8759 | {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8760 | {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8761 | {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8762 | {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8763 | {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8764 | {"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8765 | {"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8766 | {"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8767 | {"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8768 | {"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8769 | {"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8770 | {"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8771 | {"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8772 | {"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8773 | {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8774 | {"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8775 | {"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8776 | {"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8777 | {"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8778 | {"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8779 | {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8780 | {"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8781 | {"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8782 | {"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8783 | {"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8784 | {"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8785 | {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8786 | {"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8787 | {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8788 | {"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8789 | {"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8790 | {"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8791 | {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8792 | {"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8793 | {"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8794 | {"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8795 | {"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8796 | {"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8797 | {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8798 | {"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8799 | {"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8800 | {"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8801 | {"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8802 | {"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8803 | {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8804 | {"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8805 | {"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8806 | {"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8807 | {"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8808 | {"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8809 | {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8810 | {"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8811 | {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8812 | {"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8813 | {"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8814 | {"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8815 | {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8816 | {"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8817 | {"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8818 | {"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8819 | {"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8820 | {"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8821 | {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8822 | {"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8823 | {"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8824 | {"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8825 | {"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8826 | {"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8827 | {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8828 | {"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8829 | {"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8830 | {"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8831 | {"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8832 | {"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8833 | {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8834 | {"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8835 | {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8836 | {"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8837 | {"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8838 | {"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8839 | {"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8840 | {"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8841 | {"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8842 | {"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8843 | {"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8844 | {"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8845 | {"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8846 | {"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8847 | {"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8848 | {"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8849 | {"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8850 | {"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8851 | {"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8852 | {"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8853 | {"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8854 | {"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8855 | {"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8856 | {"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8857 | {"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8858 | {"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8859 | {"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8860 | {"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8861 | {"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8862 | {"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8863 | {"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8864 | {"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8865 | {"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8866 | {"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8867 | {"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8868 | {"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8869 | {"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8870 | {"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8871 | {"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8872 | {"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8873 | {"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8874 | {"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8875 | {"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8876 | {"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8877 | {"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8878 | {"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8879 | {"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8880 | {"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8881 | {"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8882 | {"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8883 | {"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8884 | {"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8885 | {"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8886 | {"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8887 | {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8888 | {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8889 | {"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8890 | {"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8891 | {"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8892 | {"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8893 | {"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8894 | {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8895 | {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8896 | {"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8897 | {"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8898 | {"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8899 | {"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8900 | {"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8901 | {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8902 | {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8903 | {"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8904 | {"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8905 | {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8906 | {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8907 | {"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8908 | {"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8909 | {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8910 | {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8911 | {"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8912 | {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8913 | {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8914 | {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8915 | {"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8916 | {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8917 | {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8918 | {"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8919 | {"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8920 | {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8921 | {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8922 | {"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8923 | {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8924 | {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8925 | {"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8926 | {"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8927 | {"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8928 | {"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8929 | {"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8930 | {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8931 | {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8932 | {"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8933 | {"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8934 | {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8935 | {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8936 | {"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8937 | {"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8938 | {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8939 | {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8940 | {"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8941 | {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8942 | {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8943 | {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8944 | {"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8945 | {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8946 | {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8947 | {"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8948 | {"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8949 | {"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8950 | {"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8951 | {"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8952 | {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8953 | {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8954 | {"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8955 | {"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8956 | {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8957 | {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8958 | {"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8959 | {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8960 | {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8961 | {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8962 | {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8963 | {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8964 | {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8965 | {"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8966 | {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8967 | {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8968 | {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8969 | {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8970 | {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8971 | {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8972 | {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
8973 | {"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8974 | {"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8975 | {"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8976 | {"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8977 | {"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8978 | {"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8979 | {"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8980 | {"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8981 | {"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8982 | {"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8983 | {"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8984 | {"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8985 | {"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8986 | {"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8987 | {"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8988 | {"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8989 | {"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8990 | {"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8991 | {"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8992 | {"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8993 | {"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8994 | {"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8995 | {"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8996 | {"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8997 | {"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8998 | {"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
8999 | {"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9000 | {"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9001 | {"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9002 | {"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9003 | {"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9004 | {"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9005 | {"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9006 | {"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9007 | {"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9008 | {"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9009 | {"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9010 | {"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9011 | {"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9012 | {"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9013 | {"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9014 | {"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9015 | {"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9016 | {"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9017 | {"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9018 | {"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9019 | {"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9020 | {"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9021 | {"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9022 | {"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9023 | {"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9024 | {"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9025 | {"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9026 | {"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9027 | {"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9028 | {"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9029 | {"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9030 | {"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9031 | {"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9032 | {"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9033 | {"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9034 | {"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9035 | {"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9036 | {"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9037 | {"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9038 | {"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9039 | {"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9040 | {"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9041 | {"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9042 | {"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9043 | {"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9044 | {"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9045 | {"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9046 | {"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9047 | {"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9048 | {"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9049 | {"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9050 | {"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9051 | {"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9052 | {"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9053 | {"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9054 | {"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9055 | {"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9056 | {"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9057 | {"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9058 | {"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9059 | {"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9060 | {"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9061 | {"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9062 | {"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9063 | {"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9064 | {"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9065 | {"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9066 | {"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9067 | {"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9068 | {"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9069 | {"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9070 | {"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9071 | {"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9072 | {"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9073 | {"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9074 | {"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9075 | {"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9076 | {"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9077 | {"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9078 | {"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9079 | {"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9080 | {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9081 | {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9082 | {"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9083 | {"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9084 | {"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9085 | {"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9086 | {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9087 | {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9088 | {"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9089 | {"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9090 | {"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9091 | {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9092 | {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9093 | {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9094 | {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9095 | {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9096 | {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9097 | {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9098 | {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9099 | {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9100 | {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9101 | {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9102 | {"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9103 | {"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9104 | {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9105 | {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9106 | {"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9107 | {"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9108 | {"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9109 | {"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9110 | {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9111 | {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9112 | {"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9113 | {"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9114 | {"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9115 | {"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9116 | {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9117 | {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9118 | {"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9119 | {"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9120 | {"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9121 | {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9122 | {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9123 | {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9124 | {"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9125 | {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9126 | {"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9127 | {"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9128 | {"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9129 | {"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9130 | {"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9131 | {"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9132 | {"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9133 | {"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9134 | {"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9135 | {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9136 | {"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9137 | {"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9138 | {"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9139 | {"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9140 | {"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9141 | {"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9142 | {"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9143 | {"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9144 | {"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
9145 | {"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9146 | {"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
9147 | {"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9148 | {"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, | |
9149 | {"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9150 | {"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9151 | {"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9152 | {"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9153 | {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9154 | {"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9155 | {"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9156 | {"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9157 | {"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9158 | {"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9159 | {"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9160 | {"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9161 | {"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9162 | {"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9163 | {"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9164 | {"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, | |
9165 | {"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9166 | {"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, | |
9167 | {"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9168 | {"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, | |
9169 | {"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9170 | {"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9171 | {"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9172 | {"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9173 | {"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9174 | {"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
9175 | {"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9176 | {"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
9177 | {"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9178 | {"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, | |
9179 | {"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9180 | {"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, | |
9181 | {"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9182 | {"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, | |
9183 | {"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9184 | {"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9185 | {"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9186 | {"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9187 | {"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9188 | {"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, | |
9189 | {"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9190 | {"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, | |
9191 | {"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9192 | {"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, | |
9193 | {"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9194 | {"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, | |
9195 | {"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9196 | {"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, | |
9197 | {"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9198 | {"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
9199 | {"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9200 | {"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
9201 | {"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9202 | {"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, | |
9203 | {"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9204 | {"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9205 | {"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9206 | {"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9207 | {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9208 | {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9209 | {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9210 | {"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9211 | {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9212 | {"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9213 | {"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9214 | {"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9215 | {"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9216 | {"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9217 | {"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, | |
9218 | {"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, | |
9219 | {"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9220 | {"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9221 | {"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9222 | {"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9223 | {"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9224 | {"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9225 | {"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9226 | {"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9227 | {"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9228 | {"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}}, | |
9229 | {"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9230 | {"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, | |
9231 | {"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9232 | {"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, | |
9233 | {"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9234 | {"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, | |
9235 | {"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, | |
9236 | {"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, | |
9237 | {"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9238 | {"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9239 | {"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9240 | {"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9241 | {"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, | |
9242 | {"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9243 | {"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9244 | {"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, | |
9245 | {"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9246 | {"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, | |
9247 | {"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9248 | {"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9249 | {"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, | |
9250 | {"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, | |
9251 | ||
14b57c7c | 9252 | {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
dfdaec14 | 9253 | {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
14b57c7c | 9254 | {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
dfdaec14 | 9255 | {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
14b57c7c AM |
9256 | {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
9257 | {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
9258 | {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9259 | {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9260 | {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
9261 | {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9262 | {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, | |
9263 | {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9264 | {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9265 | {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, | |
9266 | {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9267 | {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9268 | {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}}, | |
9269 | {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9270 | {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9271 | {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9272 | {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, | |
9273 | {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9274 | {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9275 | {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9276 | {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9277 | {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9278 | {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9279 | {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9280 | {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
9281 | {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, | |
d2e6c9a3 | 9282 | {"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9283 | {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9284 | {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9285 | {"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9286 | {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9287 | {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9288 | {"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9289 | {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9290 | {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9291 | {"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9292 | {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9293 | {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 | 9294 | {"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
dfdaec14 AJ |
9295 | {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9296 | {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
d2e6c9a3 AF |
9297 | {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
9298 | {"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, | |
14b57c7c AM |
9299 | {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, |
9300 | {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9301 | {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, | |
9302 | ||
9303 | {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9304 | {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9305 | {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9306 | {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, | |
9307 | {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9308 | {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9309 | {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9310 | ||
9311 | {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9312 | {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9313 | {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9314 | ||
9315 | {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9316 | {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9317 | {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9318 | {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, | |
9319 | {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9320 | {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9321 | {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9322 | {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, | |
9323 | {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, | |
9324 | ||
9325 | {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9326 | {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9327 | {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9328 | {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, | |
9329 | ||
9330 | {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9331 | {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9332 | {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9333 | {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9334 | {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9335 | {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9336 | {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, | |
9337 | ||
9338 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9339 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9340 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9341 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9342 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, | |
9343 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, | |
9344 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
9345 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, | |
14b57c7c AM |
9346 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
9347 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
14b57c7c AM |
9348 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, |
9349 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
9350 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, | |
9351 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, | |
9352 | {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, | |
9353 | {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, | |
9354 | {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, | |
9355 | {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, | |
9356 | {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, | |
9357 | {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9358 | {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9359 | {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9360 | {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, | |
9361 | {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9362 | {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9363 | {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9364 | {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9365 | {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9366 | {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9367 | {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9368 | {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9369 | {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9370 | {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9371 | {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9372 | {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9373 | {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9374 | {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9375 | {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9376 | {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9377 | {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9378 | {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9379 | {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9380 | {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9381 | {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9382 | {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9383 | {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9384 | {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, | |
9385 | {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, | |
9386 | {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, | |
9387 | ||
9388 | {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9389 | {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9390 | {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9391 | {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, | |
9392 | ||
9393 | {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, | |
a8cc8a54 | 9394 | {"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}}, |
14b57c7c AM |
9395 | {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, |
9396 | {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
9397 | {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
98553ad3 | 9398 | {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BAB}}, |
14b57c7c | 9399 | {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
98553ad3 | 9400 | {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BTAB}}, |
14b57c7c AM |
9401 | {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
9402 | {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, | |
9403 | {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9404 | {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9405 | ||
9406 | {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
9407 | ||
9408 | {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, | |
9409 | {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, | |
9410 | ||
98553ad3 | 9411 | {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BTAB}}, |
14b57c7c AM |
9412 | {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
9413 | ||
9414 | {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9415 | {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9416 | ||
9417 | {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, | |
9418 | ||
98553ad3 | 9419 | {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BAB}}, |
14b57c7c AM |
9420 | {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
9421 | ||
9422 | {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, | |
9423 | ||
9424 | {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9425 | {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, | |
9426 | ||
9427 | {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, | |
9428 | ||
9429 | {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, | |
9430 | ||
9431 | {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, | |
9432 | ||
9433 | {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, | |
9434 | ||
9435 | {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, | |
9436 | ||
9437 | {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, | |
9438 | ||
9439 | {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9440 | {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9441 | {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9442 | {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9443 | {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9444 | {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9445 | {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9446 | {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, | |
9447 | {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9448 | {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9449 | {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9450 | {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9451 | {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, | |
9452 | {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, | |
9453 | {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, | |
9454 | {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, | |
9455 | {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, | |
b9c361e0 JL |
9456 | }; |
9457 | ||
2ceb7719 | 9458 | const unsigned int vle_num_opcodes = |
b9c361e0 JL |
9459 | sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); |
9460 | \f | |
252b5132 RH |
9461 | /* The macro table. This is only used by the assembler. */ |
9462 | ||
9463 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 | |
9464 | when x=0; 32-x when x is between 1 and 31; are negative if x is | |
9465 | negative; and are 32 or more otherwise. This is what you want | |
9466 | when, for instance, you are emulating a right shift by a | |
9467 | rotate-left-and-mask, because the underlying instructions support | |
9468 | shifts of size 0 but not shifts of size 32. By comparison, when | |
9469 | extracting x bits from some word you want to use just 32-x, because | |
9470 | the underlying instructions don't support extracting 0 bits but do | |
9471 | support extracting the whole word (32 bits in this case). */ | |
9472 | ||
9473 | const struct powerpc_macro powerpc_macros[] = { | |
de866fcc AM |
9474 | {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, |
9475 | {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, | |
bdc7fcfe AM |
9476 | {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, |
9477 | {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, | |
de866fcc AM |
9478 | {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, |
9479 | {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, | |
9480 | {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
9481 | {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, | |
9482 | {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, | |
9483 | {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, | |
9484 | {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
9485 | {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, | |
9486 | {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, | |
9487 | {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, | |
9488 | {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, | |
14b57c7c | 9489 | {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, |
de866fcc AM |
9490 | |
9491 | {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, | |
9492 | {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, | |
9493 | {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
9494 | {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
9495 | {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
9496 | {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
9497 | {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
9498 | {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
9499 | {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
9500 | {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
9501 | {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, | |
9502 | {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, | |
9503 | {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, | |
9504 | {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, | |
9505 | {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9506 | {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9507 | {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9508 | {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9509 | {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, | |
9510 | {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, | |
9511 | {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
9512 | {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
a4ebc835 AM |
9513 | |
9514 | {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, | |
9515 | {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, | |
9516 | {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
9517 | {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
9518 | {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, | |
9519 | {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, | |
9520 | {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, | |
9521 | {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, | |
9522 | {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, | |
9523 | {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, | |
9524 | {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, | |
74081948 AF |
9525 | |
9526 | /* old SPE instructions have new names with the same opcodes */ | |
9527 | {"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"}, | |
9528 | {"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"}, | |
9529 | {"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"}, | |
9530 | {"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"}, | |
9531 | {"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"}, | |
9532 | {"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"}, | |
9533 | {"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"}, | |
9534 | {"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"}, | |
9535 | {"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"}, | |
9536 | {"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"}, | |
9537 | {"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"}, | |
9538 | {"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"}, | |
9539 | {"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"}, | |
9540 | {"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"}, | |
9541 | {"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"}, | |
9542 | {"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"}, | |
9543 | {"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"}, | |
9544 | {"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"}, | |
9545 | {"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"}, | |
9546 | {"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"}, | |
9547 | {"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"}, | |
9548 | {"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"}, | |
9549 | {"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"}, | |
9550 | ||
9551 | /* SPE2 instructions which just are mapped to SPE2 */ | |
9552 | {"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"}, | |
9553 | {"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"}, | |
9554 | {"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"}, | |
9555 | {"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"} | |
252b5132 RH |
9556 | }; |
9557 | ||
9558 | const int powerpc_num_macros = | |
9559 | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); | |
74081948 AF |
9560 | |
9561 | /* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */ | |
9562 | const struct powerpc_opcode spe2_opcodes[] = { | |
9563 | {"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9564 | {"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9565 | {"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9566 | {"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9567 | {"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9568 | {"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9569 | {"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9570 | {"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9571 | {"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9572 | {"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9573 | {"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9574 | {"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9575 | {"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9576 | {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9577 | {"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9578 | {"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9579 | {"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9580 | {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9581 | {"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9582 | {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9583 | {"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9584 | {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9585 | {"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9586 | {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9587 | {"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9588 | {"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9589 | {"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9590 | {"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9591 | {"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9592 | {"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9593 | {"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9594 | {"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9595 | {"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9596 | {"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9597 | {"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9598 | {"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9599 | {"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9600 | {"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9601 | {"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9602 | {"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9603 | {"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9604 | {"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9605 | {"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9606 | {"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9607 | {"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9608 | {"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9609 | {"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9610 | {"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9611 | {"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9612 | {"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9613 | {"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9614 | {"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9615 | {"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9616 | {"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9617 | {"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9618 | {"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9619 | {"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9620 | {"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9621 | {"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9622 | {"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9623 | {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9624 | {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9625 | {"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9626 | {"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9627 | {"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9628 | {"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9629 | {"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9630 | {"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9631 | {"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9632 | {"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9633 | {"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9634 | {"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9635 | {"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9636 | {"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9637 | {"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9638 | {"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9639 | {"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9640 | {"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9641 | {"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9642 | {"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9643 | {"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9644 | {"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9645 | {"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9646 | {"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9647 | {"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9648 | {"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9649 | {"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9650 | {"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9651 | {"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9652 | {"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9653 | {"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9654 | {"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9655 | {"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9656 | {"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9657 | {"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9658 | {"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9659 | {"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9660 | {"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9661 | {"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9662 | {"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9663 | {"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9664 | {"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9665 | {"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9666 | {"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9667 | {"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9668 | {"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9669 | {"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9670 | {"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9671 | {"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9672 | {"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9673 | {"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9674 | {"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9675 | {"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9676 | {"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9677 | {"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9678 | {"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9679 | {"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9680 | {"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9681 | {"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9682 | {"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9683 | {"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9684 | {"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9685 | {"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9686 | {"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9687 | {"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9688 | {"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9689 | {"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9690 | {"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9691 | {"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9692 | {"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9693 | {"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9694 | {"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9695 | {"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9696 | {"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9697 | {"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9698 | {"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9699 | {"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9700 | {"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9701 | {"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9702 | {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9703 | {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9704 | {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9705 | {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9706 | {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9707 | {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9708 | {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9709 | {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9710 | {"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9711 | {"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9712 | {"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9713 | {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9714 | {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9715 | {"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9716 | {"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9717 | {"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9718 | {"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9719 | {"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9720 | {"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9721 | {"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9722 | {"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9723 | {"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9724 | {"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9725 | {"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9726 | {"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9727 | {"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9728 | {"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9729 | {"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9730 | {"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9731 | {"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9732 | {"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9733 | {"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9734 | {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9735 | {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9736 | {"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9737 | {"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9738 | {"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9739 | {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9740 | {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9741 | {"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9742 | {"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9743 | {"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9744 | {"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9745 | {"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9746 | {"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9747 | {"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9748 | {"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9749 | {"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9750 | {"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9751 | {"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9752 | {"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9753 | {"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9754 | {"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9755 | {"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9756 | {"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9757 | {"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9758 | {"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9759 | {"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9760 | {"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9761 | {"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9762 | {"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9763 | {"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9764 | {"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9765 | {"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9766 | {"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9767 | {"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9768 | {"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9769 | {"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9770 | {"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9771 | {"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, | |
9772 | {"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, | |
9773 | {"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, | |
9774 | {"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, | |
9775 | {"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9776 | {"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9777 | {"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9778 | {"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9779 | {"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9780 | {"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9781 | {"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9782 | {"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9783 | {"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9784 | {"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9785 | {"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9786 | {"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9787 | {"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9788 | {"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9789 | {"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9790 | {"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9791 | {"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9792 | {"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9793 | {"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9794 | {"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9795 | {"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9796 | {"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9797 | {"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9798 | {"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9799 | {"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9800 | {"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9801 | {"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9802 | {"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9803 | {"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9804 | {"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9805 | {"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9806 | {"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9807 | {"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9808 | {"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9809 | {"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9810 | {"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9811 | {"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9812 | {"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9813 | {"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9814 | {"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9815 | {"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9816 | {"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9817 | {"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9818 | {"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9819 | {"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9820 | {"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9821 | {"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9822 | {"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9823 | {"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9824 | {"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9825 | {"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9826 | {"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9827 | {"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9828 | {"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9829 | {"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9830 | {"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9831 | {"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9832 | {"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9833 | {"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9834 | {"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9835 | {"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9836 | {"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9837 | {"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9838 | {"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9839 | {"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9840 | {"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9841 | {"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9842 | {"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9843 | {"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9844 | {"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9845 | {"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9846 | {"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9847 | {"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9848 | {"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9849 | {"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9850 | {"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9851 | {"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9852 | {"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9853 | {"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9854 | {"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9855 | {"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9856 | {"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9857 | {"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9858 | {"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9859 | {"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
9860 | {"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9861 | {"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9862 | {"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
9863 | {"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9864 | {"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9865 | {"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9866 | {"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9867 | {"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9868 | {"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9869 | {"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9870 | {"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9871 | {"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9872 | {"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9873 | {"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9874 | {"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9875 | {"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9876 | {"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9877 | {"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9878 | {"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9879 | {"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9880 | {"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9881 | {"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9882 | {"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9883 | {"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9884 | {"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9885 | {"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9886 | {"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9887 | {"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9888 | {"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, | |
9889 | {"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9890 | {"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9891 | {"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9892 | {"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9893 | {"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, | |
9894 | {"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9895 | {"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9896 | {"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9897 | {"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9898 | {"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9899 | {"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9900 | {"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9901 | {"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9902 | {"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, | |
9903 | {"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, | |
9904 | {"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}}, | |
9905 | {"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}}, | |
9906 | {"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, | |
9907 | {"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
9908 | {"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
9909 | {"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, | |
9910 | {"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, | |
9911 | {"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9912 | {"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9913 | {"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9914 | {"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9915 | {"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9916 | {"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9917 | {"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}}, | |
9918 | {"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9919 | {"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9920 | {"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9921 | {"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9922 | {"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9923 | {"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9924 | {"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9925 | {"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, | |
9926 | {"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9927 | {"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9928 | {"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9929 | {"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9930 | {"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9931 | {"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9932 | {"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9933 | {"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, | |
9934 | {"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9935 | {"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9936 | {"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
9937 | {"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, | |
9938 | {"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9939 | {"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9940 | {"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
9941 | {"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
9942 | {"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, | |
9943 | {"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9944 | {"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}}, | |
9945 | {"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9946 | {"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}}, | |
9947 | {"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9948 | {"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9949 | {"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9950 | {"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9951 | {"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9952 | {"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}}, | |
9953 | {"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9954 | {"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}}, | |
9955 | {"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9956 | {"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9957 | {"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9958 | {"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9959 | {"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9960 | {"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, | |
9961 | {"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9962 | {"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
9963 | {"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9964 | {"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
9965 | {"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9966 | {"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, | |
9967 | {"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
9968 | {"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}}, | |
9969 | {"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9970 | {"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9971 | {"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9972 | {"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9973 | {"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9974 | {"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9975 | {"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9976 | {"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, | |
9977 | {"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9978 | {"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9979 | {"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9980 | {"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9981 | {"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9982 | {"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9983 | {"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9984 | {"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, | |
9985 | {"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9986 | {"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9987 | {"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9988 | {"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9989 | {"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9990 | {"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9991 | {"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9992 | {"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9993 | {"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9994 | {"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9995 | {"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9996 | {"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9997 | {"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
9998 | {"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
9999 | {"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10000 | {"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}}, | |
10001 | {"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10002 | {"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10003 | {"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10004 | {"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10005 | {"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10006 | {"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10007 | {"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10008 | {"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, | |
10009 | {"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10010 | {"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10011 | {"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10012 | {"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10013 | {"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10014 | {"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, | |
10015 | {"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10016 | {"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10017 | {"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10018 | {"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10019 | {"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10020 | {"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10021 | {"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10022 | {"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10023 | {"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10024 | {"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10025 | {"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10026 | {"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10027 | {"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10028 | {"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, | |
10029 | {"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, | |
10030 | {"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}}, | |
10031 | {"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10032 | {"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10033 | {"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10034 | {"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10035 | {"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10036 | {"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10037 | {"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10038 | {"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10039 | {"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10040 | {"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10041 | {"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10042 | {"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10043 | {"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10044 | {"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10045 | {"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10046 | {"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10047 | {"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10048 | {"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10049 | {"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10050 | {"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10051 | {"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10052 | {"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10053 | {"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10054 | {"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10055 | {"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10056 | {"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10057 | {"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10058 | {"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10059 | {"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10060 | {"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10061 | {"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10062 | {"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10063 | {"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10064 | {"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10065 | {"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10066 | {"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10067 | {"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10068 | {"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10069 | {"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10070 | {"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10071 | {"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10072 | {"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10073 | {"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10074 | {"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10075 | {"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10076 | {"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10077 | {"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10078 | {"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10079 | {"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10080 | {"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10081 | {"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10082 | {"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10083 | {"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10084 | {"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10085 | {"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10086 | {"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10087 | {"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10088 | {"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10089 | {"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10090 | {"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10091 | {"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10092 | {"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10093 | {"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10094 | {"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10095 | {"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10096 | {"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10097 | {"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10098 | {"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10099 | {"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10100 | {"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10101 | {"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10102 | {"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10103 | {"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10104 | {"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10105 | {"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10106 | {"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10107 | {"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10108 | {"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10109 | {"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10110 | {"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10111 | {"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10112 | {"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10113 | {"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10114 | {"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10115 | {"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10116 | {"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10117 | {"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10118 | {"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10119 | {"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10120 | {"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10121 | {"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10122 | {"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10123 | {"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10124 | {"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10125 | {"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}}, | |
10126 | {"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10127 | {"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10128 | {"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10129 | {"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10130 | {"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10131 | {"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10132 | {"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10133 | {"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10134 | {"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10135 | {"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10136 | {"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10137 | {"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10138 | {"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10139 | {"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10140 | {"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10141 | {"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10142 | {"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10143 | {"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10144 | {"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10145 | {"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10146 | {"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10147 | {"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10148 | {"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10149 | {"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, | |
10150 | {"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10151 | {"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10152 | {"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10153 | {"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10154 | {"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10155 | {"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10156 | {"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10157 | {"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10158 | {"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10159 | {"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10160 | {"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10161 | {"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10162 | {"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10163 | {"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10164 | {"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10165 | {"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10166 | {"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10167 | {"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10168 | {"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10169 | {"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10170 | {"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10171 | {"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10172 | {"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10173 | {"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10174 | {"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10175 | {"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10176 | {"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10177 | {"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10178 | {"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10179 | {"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10180 | {"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10181 | {"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10182 | {"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10183 | {"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10184 | {"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10185 | {"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10186 | {"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10187 | {"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10188 | {"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10189 | {"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10190 | {"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10191 | {"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10192 | {"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10193 | {"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10194 | {"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10195 | {"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10196 | {"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10197 | {"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10198 | {"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10199 | {"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10200 | {"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10201 | {"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10202 | {"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10203 | {"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10204 | {"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10205 | {"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10206 | {"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10207 | {"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10208 | {"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10209 | {"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10210 | {"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10211 | {"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10212 | {"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10213 | {"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10214 | {"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10215 | {"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10216 | {"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10217 | {"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10218 | {"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10219 | {"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10220 | {"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10221 | {"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10222 | {"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10223 | {"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10224 | {"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10225 | {"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10226 | {"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10227 | {"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10228 | {"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10229 | {"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10230 | {"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10231 | {"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10232 | {"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10233 | {"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10234 | {"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10235 | {"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10236 | {"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10237 | {"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10238 | {"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10239 | {"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10240 | {"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10241 | {"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10242 | {"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10243 | {"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10244 | {"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10245 | {"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10246 | {"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10247 | {"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10248 | {"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10249 | {"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10250 | {"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10251 | {"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10252 | {"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10253 | {"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10254 | {"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10255 | {"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10256 | {"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10257 | {"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10258 | {"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10259 | {"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10260 | {"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10261 | {"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10262 | {"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10263 | {"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10264 | {"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10265 | {"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10266 | {"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10267 | {"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10268 | {"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10269 | {"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10270 | {"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10271 | {"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10272 | {"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10273 | {"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10274 | {"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10275 | {"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10276 | {"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10277 | {"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10278 | {"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10279 | {"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10280 | {"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10281 | {"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10282 | {"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10283 | {"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10284 | {"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10285 | {"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10286 | {"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10287 | {"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10288 | {"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10289 | {"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10290 | {"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10291 | {"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10292 | {"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10293 | {"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10294 | {"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10295 | {"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10296 | {"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10297 | {"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10298 | {"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10299 | {"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10300 | {"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10301 | {"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10302 | {"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10303 | {"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10304 | {"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10305 | {"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10306 | {"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10307 | {"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10308 | {"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10309 | {"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10310 | {"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10311 | {"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10312 | {"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10313 | {"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10314 | {"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10315 | {"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10316 | {"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10317 | {"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10318 | {"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10319 | {"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10320 | {"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10321 | {"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10322 | {"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10323 | {"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10324 | {"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10325 | {"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10326 | {"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10327 | {"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10328 | {"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10329 | {"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10330 | {"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10331 | {"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10332 | {"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10333 | {"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10334 | {"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10335 | {"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10336 | {"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10337 | {"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10338 | {"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10339 | {"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10340 | {"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10341 | {"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10342 | {"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10343 | {"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10344 | {"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10345 | {"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10346 | {"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, | |
10347 | }; | |
10348 | ||
2ceb7719 | 10349 | const unsigned int spe2_num_opcodes = |
74081948 | 10350 | sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]); |