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[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c
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252b5132 1/* ppc-opc.c -- PowerPC opcode list
5e8cb021
AM		 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Ian Lance Taylor, Cygnus Support
5
112290ab 6 This file is part of GDB, GAS, and the GNU binutils.
252b5132 7
112290ab
NC		 8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
252b5132 12
112290ab
NC		 13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
252b5132 17
112290ab
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
252b5132
RH		 22
23#include <stdio.h>
0d8dfecf 24#include "sysdep.h"
252b5132
RH		 25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38\f
39/* Local insertion and extraction functions. */
40
c168870a
AM		 41static unsigned long insert_bat (unsigned long, long, int, const char **);
42static long extract_bat (unsigned long, int, int *);
43static unsigned long insert_bba (unsigned long, long, int, const char **);
44static long extract_bba (unsigned long, int, int *);
45static unsigned long insert_bd (unsigned long, long, int, const char **);
46static long extract_bd (unsigned long, int, int *);
47static unsigned long insert_bdm (unsigned long, long, int, const char **);
48static long extract_bdm (unsigned long, int, int *);
49static unsigned long insert_bdp (unsigned long, long, int, const char **);
50static long extract_bdp (unsigned long, int, int *);
c168870a
AM		 51static unsigned long insert_bo (unsigned long, long, int, const char **);
52static long extract_bo (unsigned long, int, int *);
53static unsigned long insert_boe (unsigned long, long, int, const char **);
54static long extract_boe (unsigned long, int, int *);
55static unsigned long insert_dq (unsigned long, long, int, const char **);
56static long extract_dq (unsigned long, int, int *);
57static unsigned long insert_ds (unsigned long, long, int, const char **);
58static long extract_ds (unsigned long, int, int *);
59static unsigned long insert_de (unsigned long, long, int, const char **);
60static long extract_de (unsigned long, int, int *);
61static unsigned long insert_des (unsigned long, long, int, const char **);
62static long extract_des (unsigned long, int, int *);
63static unsigned long insert_fxm (unsigned long, long, int, const char **);
64static long extract_fxm (unsigned long, int, int *);
65static unsigned long insert_li (unsigned long, long, int, const char **);
66static long extract_li (unsigned long, int, int *);
67static unsigned long insert_mbe (unsigned long, long, int, const char **);
68static long extract_mbe (unsigned long, int, int *);
69static unsigned long insert_mb6 (unsigned long, long, int, const char **);
70static long extract_mb6 (unsigned long, int, int *);
71static unsigned long insert_nb (unsigned long, long, int, const char **);
72static long extract_nb (unsigned long, int, int *);
73static unsigned long insert_nsi (unsigned long, long, int, const char **);
74static long extract_nsi (unsigned long, int, int *);
75static unsigned long insert_ral (unsigned long, long, int, const char **);
76static unsigned long insert_ram (unsigned long, long, int, const char **);
77static unsigned long insert_raq (unsigned long, long, int, const char **);
78static unsigned long insert_ras (unsigned long, long, int, const char **);
79static unsigned long insert_rbs (unsigned long, long, int, const char **);
80static long extract_rbs (unsigned long, int, int *);
81static unsigned long insert_rsq (unsigned long, long, int, const char **);
82static unsigned long insert_rtq (unsigned long, long, int, const char **);
83static unsigned long insert_sh6 (unsigned long, long, int, const char **);
84static long extract_sh6 (unsigned long, int, int *);
85static unsigned long insert_spr (unsigned long, long, int, const char **);
86static long extract_spr (unsigned long, int, int *);
da99ee72
AM		 87static unsigned long insert_sprg (unsigned long, long, int, const char **);
88static long extract_sprg (unsigned long, int, int *);
c168870a
AM		 89static unsigned long insert_tbr (unsigned long, long, int, const char **);
90static long extract_tbr (unsigned long, int, int *);
91static unsigned long insert_ev2 (unsigned long, long, int, const char **);
92static long extract_ev2 (unsigned long, int, int *);
93static unsigned long insert_ev4 (unsigned long, long, int, const char **);
94static long extract_ev4 (unsigned long, int, int *);
95static unsigned long insert_ev8 (unsigned long, long, int, const char **);
96static long extract_ev8 (unsigned long, int, int *);
252b5132
RH		 97\f
98/* The operands table.
99
100 The fields are bits, shift, insert, extract, flags.
101
102 We used to put parens around the various additions, like the one
103 for BA just below. However, that caused trouble with feeble
104 compilers with a limit on depth of a parenthesized expression, like
105 (reportedly) the compiler in Microsoft Developer Studio 5. So we
106 omit the parens, since the macros are never used in a context where
107 the addition will be ambiguous. */
108
109const struct powerpc_operand powerpc_operands[] =
110{
111 /* The zero index is used to indicate the end of the list of
112 operands. */
113#define UNUSED 0
bbac1f2a 114 { 0, 0, NULL, NULL, 0 },
252b5132
RH		 115
116 /* The BA field in an XL form instruction. */
117#define BA UNUSED + 1
118#define BA_MASK (0x1f << 16)
bbac1f2a 119 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 120
121 /* The BA field in an XL form instruction when it must be the same
122 as the BT field in the same instruction. */
123#define BAT BA + 1
11b37b7b 124 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
252b5132
RH		 125
126 /* The BB field in an XL form instruction. */
127#define BB BAT + 1
128#define BB_MASK (0x1f << 11)
bbac1f2a 129 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 130
131 /* The BB field in an XL form instruction when it must be the same
132 as the BA field in the same instruction. */
133#define BBA BB + 1
11b37b7b 134 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
252b5132
RH		 135
136 /* The BD field in a B form instruction. The lower two bits are
137 forced to zero. */
138#define BD BBA + 1
11b37b7b 139 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 140
141 /* The BD field in a B form instruction when absolute addressing is
142 used. */
143#define BDA BD + 1
11b37b7b 144 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 145
146 /* The BD field in a B form instruction when the - modifier is used.
147 This sets the y bit of the BO field appropriately. */
148#define BDM BDA + 1
11b37b7b
AM		 149 { 16, 0, insert_bdm, extract_bdm,
150 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 151
152 /* The BD field in a B form instruction when the - modifier is used
153 and absolute address is used. */
154#define BDMA BDM + 1
11b37b7b
AM		 155 { 16, 0, insert_bdm, extract_bdm,
156 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 157
158 /* The BD field in a B form instruction when the + modifier is used.
159 This sets the y bit of the BO field appropriately. */
160#define BDP BDMA + 1
11b37b7b
AM		 161 { 16, 0, insert_bdp, extract_bdp,
162 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 163
164 /* The BD field in a B form instruction when the + modifier is used
165 and absolute addressing is used. */
166#define BDPA BDP + 1
11b37b7b
AM		 167 { 16, 0, insert_bdp, extract_bdp,
168 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132
RH		 169
170 /* The BF field in an X or XL form instruction. */
171#define BF BDPA + 1
bbac1f2a 172 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 173
174 /* An optional BF field. This is used for comparison instructions,
175 in which an omitted BF field is taken as zero. */
176#define OBF BF + 1
bbac1f2a 177 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132
RH		 178
179 /* The BFA field in an X or XL form instruction. */
180#define BFA OBF + 1
bbac1f2a 181 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 182
183 /* The BI field in a B form or XL form instruction. */
184#define BI BFA + 1
185#define BI_MASK (0x1f << 16)
bbac1f2a 186 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 187
188 /* The BO field in a B form instruction. Certain values are
189 illegal. */
190#define BO BI + 1
191#define BO_MASK (0x1f << 21)
11b37b7b 192 { 5, 21, insert_bo, extract_bo, 0 },
252b5132
RH		 193
194 /* The BO field in a B form instruction when the + or - modifier is
195 used. This is like the BO field, but it must be even. */
196#define BOE BO + 1
11b37b7b 197 { 5, 21, insert_boe, extract_boe, 0 },
252b5132 198
d0618d1c 199#define BH BOE + 1
bbac1f2a 200 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
d0618d1c 201
252b5132 202 /* The BT field in an X or XL form instruction. */
d0618d1c 203#define BT BH + 1
bbac1f2a 204 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
252b5132
RH		 205
206 /* The condition register number portion of the BI field in a B form
207 or XL form instruction. This is used for the extended
208 conditional branch mnemonics, which set the lower two bits of the
209 BI field. This field is optional. */
210#define CR BT + 1
bbac1f2a 211 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
252b5132 212
23976049
EZ		 213 /* The CRB field in an X form instruction. */
214#define CRB CR + 1
bbac1f2a 215 { 5, 6, NULL, NULL, 0 },
23976049
EZ		 216
217 /* The CRFD field in an X form instruction. */
218#define CRFD CRB + 1
bbac1f2a 219 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
23976049
EZ		 220
221 /* The CRFS field in an X form instruction. */
222#define CRFS CRFD + 1
bbac1f2a 223 { 3, 0, NULL, NULL, PPC_OPERAND_CR },
23976049 224
418c1742 225 /* The CT field in an X form instruction. */
23976049 226#define CT CRFS + 1
bbac1f2a 227 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
418c1742 228
252b5132
RH		 229 /* The D field in a D form instruction. This is a displacement off
230 a register, and implies that the next operand is a register in
231 parentheses. */
418c1742 232#define D CT + 1
bbac1f2a 233 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
252b5132 234
418c1742
MG		 235 /* The DE field in a DE form instruction. This is like D, but is 12
236 bits only. */
237#define DE D + 1
238 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
239
240 /* The DES field in a DES form instruction. This is like DS, but is 14
241 bits only (12 stored.) */
242#define DES DE + 1
243 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
244
adadcc0c
AM		 245 /* The DQ field in a DQ form instruction. This is like D, but the
246 lower four bits are forced to zero. */
247#define DQ DES + 1
248 { 16, 0, insert_dq, extract_dq,
249 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
250
252b5132
RH		 251 /* The DS field in a DS form instruction. This is like D, but the
252 lower two bits are forced to zero. */
adadcc0c 253#define DS DQ + 1
6ba045b1
AM		 254 { 16, 0, insert_ds, extract_ds,
255 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252b5132
RH		 256
257 /* The E field in a wrteei instruction. */
258#define E DS + 1
bbac1f2a 259 { 1, 15, NULL, NULL, 0 },
252b5132
RH		 260
261 /* The FL1 field in a POWER SC form instruction. */
262#define FL1 E + 1
bbac1f2a 263 { 4, 12, NULL, NULL, 0 },
252b5132
RH		 264
265 /* The FL2 field in a POWER SC form instruction. */
266#define FL2 FL1 + 1
bbac1f2a 267 { 3, 2, NULL, NULL, 0 },
252b5132
RH		 268
269 /* The FLM field in an XFL form instruction. */
270#define FLM FL2 + 1
bbac1f2a 271 { 8, 17, NULL, NULL, 0 },
252b5132
RH		 272
273 /* The FRA field in an X or A form instruction. */
274#define FRA FLM + 1
275#define FRA_MASK (0x1f << 16)
bbac1f2a 276 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 277
278 /* The FRB field in an X or A form instruction. */
279#define FRB FRA + 1
280#define FRB_MASK (0x1f << 11)
bbac1f2a 281 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 282
283 /* The FRC field in an A form instruction. */
284#define FRC FRB + 1
285#define FRC_MASK (0x1f << 6)
bbac1f2a 286 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 287
288 /* The FRS field in an X form instruction or the FRT field in a D, X
289 or A form instruction. */
290#define FRS FRC + 1
291#define FRT FRS
bbac1f2a 292 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
252b5132
RH		 293
294 /* The FXM field in an XFX instruction. */
295#define FXM FRS + 1
296#define FXM_MASK (0xff << 12)
c168870a
AM		 297 { 8, 12, insert_fxm, extract_fxm, 0 },
298
299 /* Power4 version for mfcr. */
300#define FXM4 FXM + 1
301 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
252b5132
RH		 302
303 /* The L field in a D or X form instruction. */
c168870a 304#define L FXM4 + 1
e612bb4d 305 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
252b5132
RH		 306
307 /* The LEV field in a POWER SC form instruction. */
308#define LEV L + 1
bbac1f2a 309 { 7, 5, NULL, NULL, 0 },
252b5132
RH		 310
311 /* The LI field in an I form instruction. The lower two bits are
312 forced to zero. */
313#define LI LEV + 1
11b37b7b 314 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
252b5132
RH		 315
316 /* The LI field in an I form instruction when used as an absolute
317 address. */
318#define LIA LI + 1
11b37b7b 319 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
252b5132 320
6ba045b1
AM		 321 /* The LS field in an X (sync) form instruction. */
322#define LS LIA + 1
bbac1f2a 323 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
6ba045b1 324
252b5132 325 /* The MB field in an M form instruction. */
6ba045b1 326#define MB LS + 1
252b5132 327#define MB_MASK (0x1f << 6)
bbac1f2a 328 { 5, 6, NULL, NULL, 0 },
252b5132
RH		 329
330 /* The ME field in an M form instruction. */
331#define ME MB + 1
332#define ME_MASK (0x1f << 1)
bbac1f2a 333 { 5, 1, NULL, NULL, 0 },
252b5132
RH		 334
335 /* The MB and ME fields in an M form instruction expressed a single
336 operand which is a bitmask indicating which bits to select. This
337 is a two operand form using PPC_OPERAND_NEXT. See the
338 description in opcode/ppc.h for what this means. */
339#define MBE ME + 1
bbac1f2a 340 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
11b37b7b 341 { 32, 0, insert_mbe, extract_mbe, 0 },
252b5132
RH		 342
343 /* The MB or ME field in an MD or MDS form instruction. The high
344 bit is wrapped to the low end. */
345#define MB6 MBE + 2
346#define ME6 MB6
347#define MB6_MASK (0x3f << 5)
11b37b7b 348 { 6, 5, insert_mb6, extract_mb6, 0 },
252b5132 349
9fa87a06
MG		 350 /* The MO field in an mbar instruction. */
351#define MO MB6 + 1
bbac1f2a 352 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
9fa87a06 353
252b5132
RH		 354 /* The NB field in an X form instruction. The value 32 is stored as
355 0. */
9fa87a06 356#define NB MO + 1
11b37b7b 357 { 6, 11, insert_nb, extract_nb, 0 },
252b5132
RH		 358
359 /* The NSI field in a D form instruction. This is the same as the
360 SI field, only negated. */
361#define NSI NB + 1
362 { 16, 0, insert_nsi, extract_nsi,
11b37b7b 363 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
252b5132 364
adadcc0c 365 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
914749f6 366#define RA NSI + 1
252b5132 367#define RA_MASK (0x1f << 16)
bbac1f2a 368 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
252b5132 369
fdd12ef3
AM		 370 /* As above, but 0 in the RA field means zero, not r0. */
371#define RA0 RA + 1
bbac1f2a 372 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
fdd12ef3
AM		 373
374 /* The RA field in the DQ form lq instruction, which has special
adadcc0c 375 value restrictions. */
fdd12ef3 376#define RAQ RA0 + 1
bbac1f2a 377 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 378
252b5132
RH		 379 /* The RA field in a D or X form instruction which is an updating
380 load, which means that the RA field may not be zero and may not
381 equal the RT field. */
adadcc0c 382#define RAL RAQ + 1
bbac1f2a 383 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 384
385 /* The RA field in an lmw instruction, which has special value
386 restrictions. */
387#define RAM RAL + 1
bbac1f2a 388 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
252b5132
RH		 389
390 /* The RA field in a D or X form instruction which is an updating
391 store or an updating floating point load, which means that the RA
392 field may not be zero. */
393#define RAS RAM + 1
bbac1f2a 394 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
252b5132 395
1f6c9eb0 396 /* The RA field of the tlbwe instruction, which is optional. */
fdd12ef3 397#define RAOPT RAS + 1
bbac1f2a 398 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 399
252b5132 400 /* The RB field in an X, XO, M, or MDS form instruction. */
fdd12ef3 401#define RB RAOPT + 1
252b5132 402#define RB_MASK (0x1f << 11)
bbac1f2a 403 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
252b5132
RH		 404
405 /* The RB field in an X form instruction when it must be the same as
406 the RS field in the instruction. This is used for extended
407 mnemonics like mr. */
408#define RBS RB + 1
11b37b7b 409 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
252b5132
RH		 410
411 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
412 instruction or the RT field in a D, DS, X, XFX or XO form
413 instruction. */
414#define RS RBS + 1
415#define RT RS
416#define RT_MASK (0x1f << 21)
bbac1f2a 417 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
252b5132 418
fdd12ef3 419 /* The RS field of the DS form stq instruction, which has special
adadcc0c
AM		 420 value restrictions. */
421#define RSQ RS + 1
bbac1f2a 422 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c
AM		 423
424 /* The RT field of the DQ form lq instruction, which has special
425 value restrictions. */
426#define RTQ RSQ + 1
bbac1f2a 427 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
adadcc0c 428
1f6c9eb0
ZW		 429 /* The RS field of the tlbwe instruction, which is optional. */
430#define RSO RTQ + 1
bbac1f2a 431 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
1f6c9eb0 432
252b5132 433 /* The SH field in an X or M form instruction. */
1f6c9eb0 434#define SH RSO + 1
252b5132 435#define SH_MASK (0x1f << 11)
bbac1f2a 436 { 5, 11, NULL, NULL, 0 },
252b5132
RH		 437
438 /* The SH field in an MD form instruction. This is split. */
439#define SH6 SH + 1
440#define SH6_MASK ((0x1f << 11) | (1 << 1))
11b37b7b 441 { 6, 1, insert_sh6, extract_sh6, 0 },
252b5132 442
1f6c9eb0
ZW		 443 /* The SH field of the tlbwe instruction, which is optional. */
444#define SHO SH6 + 1
bbac1f2a 445 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
1f6c9eb0 446
252b5132 447 /* The SI field in a D form instruction. */
1f6c9eb0 448#define SI SHO + 1
bbac1f2a 449 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
252b5132
RH		 450
451 /* The SI field in a D form instruction when we accept a wide range
452 of positive values. */
453#define SISIGNOPT SI + 1
bbac1f2a 454 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
252b5132
RH		 455
456 /* The SPR field in an XFX form instruction. This is flipped--the
457 lower 5 bits are stored in the upper 5 and vice- versa. */
458#define SPR SISIGNOPT + 1
914749f6 459#define PMR SPR
252b5132 460#define SPR_MASK (0x3ff << 11)
11b37b7b 461 { 10, 11, insert_spr, extract_spr, 0 },
252b5132
RH		 462
463 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
464#define SPRBAT SPR + 1
465#define SPRBAT_MASK (0x3 << 17)
bbac1f2a 466 { 2, 17, NULL, NULL, 0 },
252b5132
RH		 467
468 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
469#define SPRG SPRBAT + 1
da99ee72 470 { 5, 16, insert_sprg, extract_sprg, 0 },
252b5132
RH		 471
472 /* The SR field in an X form instruction. */
473#define SR SPRG + 1
bbac1f2a 474 { 4, 16, NULL, NULL, 0 },
252b5132 475
f5c120c5
MG		 476 /* The STRM field in an X AltiVec form instruction. */
477#define STRM SR + 1
478#define STRM_MASK (0x3 << 21)
bbac1f2a 479 { 2, 21, NULL, NULL, 0 },
f5c120c5 480
252b5132 481 /* The SV field in a POWER SC form instruction. */
f5c120c5 482#define SV STRM + 1
bbac1f2a 483 { 14, 2, NULL, NULL, 0 },
252b5132
RH		 484
485 /* The TBR field in an XFX form instruction. This is like the SPR
486 field, but it is optional. */
487#define TBR SV + 1
11b37b7b 488 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
252b5132
RH		 489
490 /* The TO field in a D or X form instruction. */
491#define TO TBR + 1
492#define TO_MASK (0x1f << 21)
bbac1f2a 493 { 5, 21, NULL, NULL, 0 },
252b5132
RH		 494
495 /* The U field in an X form instruction. */
496#define U TO + 1
bbac1f2a 497 { 4, 12, NULL, NULL, 0 },
252b5132
RH		 498
499 /* The UI field in a D form instruction. */
500#define UI U + 1
bbac1f2a 501 { 16, 0, NULL, NULL, 0 },
786e2c0f 502
112290ab 503 /* The VA field in a VA, VX or VXR form instruction. */
786e2c0f
C		 504#define VA UI + 1
505#define VA_MASK (0x1f << 16)
bbac1f2a 506 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 507
112290ab 508 /* The VB field in a VA, VX or VXR form instruction. */
786e2c0f
C		 509#define VB VA + 1
510#define VB_MASK (0x1f << 11)
bbac1f2a 511 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 512
112290ab 513 /* The VC field in a VA form instruction. */
786e2c0f
C		 514#define VC VB + 1
515#define VC_MASK (0x1f << 6)
bbac1f2a 516 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 517
112290ab 518 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
786e2c0f
C		 519#define VD VC + 1
520#define VS VD
521#define VD_MASK (0x1f << 21)
bbac1f2a 522 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
786e2c0f 523
112290ab 524 /* The SIMM field in a VX form instruction. */
786e2c0f 525#define SIMM VD + 1
bbac1f2a 526 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
786e2c0f 527
112290ab 528 /* The UIMM field in a VX form instruction. */
786e2c0f 529#define UIMM SIMM + 1
bbac1f2a 530 { 5, 16, NULL, NULL, 0 },
786e2c0f 531
112290ab 532 /* The SHB field in a VA form instruction. */
786e2c0f 533#define SHB UIMM + 1
bbac1f2a 534 { 4, 6, NULL, NULL, 0 },
ff3a6ee3 535
112290ab 536 /* The other UIMM field in a EVX form instruction. */
23976049 537#define EVUIMM SHB + 1
bbac1f2a 538 { 5, 11, NULL, NULL, 0 },
23976049 539
112290ab 540 /* The other UIMM field in a half word EVX form instruction. */
23976049 541#define EVUIMM_2 EVUIMM + 1
95e172a5 542 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
23976049 543
112290ab 544 /* The other UIMM field in a word EVX form instruction. */
23976049 545#define EVUIMM_4 EVUIMM_2 + 1
95e172a5 546 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
23976049 547
112290ab 548 /* The other UIMM field in a double EVX form instruction. */
23976049 549#define EVUIMM_8 EVUIMM_4 + 1
ced05688 550 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
23976049 551
ff3a6ee3 552 /* The WS field. */
23976049 553#define WS EVUIMM_8 + 1
ff3a6ee3 554#define WS_MASK (0x7 << 11)
bbac1f2a 555 { 3, 11, NULL, NULL, 0 },
ff3a6ee3 556
5ae2e65e
AM		 557 /* The L field in an mtmsrd instruction */
558#define MTMSRD_L WS + 1
bbac1f2a 559 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
5ae2e65e 560
252b5132
RH		 561};
562
563/* The functions used to insert and extract complicated operands. */
564
565/* The BA field in an XL form instruction when it must be the same as
566 the BT field in the same instruction. This operand is marked FAKE.
567 The insertion function just copies the BT field into the BA field,
568 and the extraction function just checks that the fields are the
569 same. */
570
252b5132 571static unsigned long
2fbfdc41
AM		 572insert_bat (unsigned long insn,
573 long value ATTRIBUTE_UNUSED,
574 int dialect ATTRIBUTE_UNUSED,
575 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 576{
577 return insn | (((insn >> 21) & 0x1f) << 16);
578}
579
580static long
2fbfdc41
AM		 581extract_bat (unsigned long insn,
582 int dialect ATTRIBUTE_UNUSED,
583 int *invalid)
252b5132 584{
8427c424 585 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
252b5132
RH		 586 *invalid = 1;
587 return 0;
588}
589
590/* The BB field in an XL form instruction when it must be the same as
591 the BA field in the same instruction. This operand is marked FAKE.
592 The insertion function just copies the BA field into the BB field,
593 and the extraction function just checks that the fields are the
594 same. */
595
252b5132 596static unsigned long
2fbfdc41
AM		 597insert_bba (unsigned long insn,
598 long value ATTRIBUTE_UNUSED,
599 int dialect ATTRIBUTE_UNUSED,
600 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 601{
602 return insn | (((insn >> 16) & 0x1f) << 11);
603}
604
605static long
2fbfdc41
AM		 606extract_bba (unsigned long insn,
607 int dialect ATTRIBUTE_UNUSED,
608 int *invalid)
252b5132 609{
8427c424 610 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 611 *invalid = 1;
612 return 0;
613}
614
615/* The BD field in a B form instruction. The lower two bits are
616 forced to zero. */
617
252b5132 618static unsigned long
2fbfdc41
AM		 619insert_bd (unsigned long insn,
620 long value,
621 int dialect ATTRIBUTE_UNUSED,
622 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 623{
624 return insn | (value & 0xfffc);
625}
626
252b5132 627static long
2fbfdc41
AM		 628extract_bd (unsigned long insn,
629 int dialect ATTRIBUTE_UNUSED,
630 int *invalid ATTRIBUTE_UNUSED)
252b5132 631{
802a735e 632 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 633}
634
635/* The BD field in a B form instruction when the - modifier is used.
636 This modifier means that the branch is not expected to be taken.
94efba12
AM		 637 For chips built to versions of the architecture prior to version 2
638 (ie. not Power4 compatible), we set the y bit of the BO field to 1
639 if the offset is negative. When extracting, we require that the y
640 bit be 1 and that the offset be positive, since if the y bit is 0
641 we just want to print the normal form of the instruction.
642 Power4 compatible targets use two bits, "a", and "t", instead of
643 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
644 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
645 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
646 for branch on CTR. We only handle the taken/not-taken hint here. */
252b5132 647
252b5132 648static unsigned long
2fbfdc41
AM		 649insert_bdm (unsigned long insn,
650 long value,
651 int dialect,
652 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 653{
94efba12 654 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 655 {
656 if ((value & 0x8000) != 0)
657 insn |= 1 << 21;
658 }
659 else
660 {
661 if ((insn & (0x14 << 21)) == (0x04 << 21))
662 insn |= 0x02 << 21;
663 else if ((insn & (0x14 << 21)) == (0x10 << 21))
664 insn |= 0x08 << 21;
665 }
252b5132
RH		 666 return insn | (value & 0xfffc);
667}
668
669static long
2fbfdc41
AM		 670extract_bdm (unsigned long insn,
671 int dialect,
672 int *invalid)
252b5132 673{
8427c424 674 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 675 {
8427c424
AM		 676 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
677 *invalid = 1;
802a735e 678 }
8427c424
AM		 679 else
680 {
681 if ((insn & (0x17 << 21)) != (0x06 << 21)
682 && (insn & (0x1d << 21)) != (0x18 << 21))
683 *invalid = 1;
684 }
685
802a735e 686 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 687}
688
689/* The BD field in a B form instruction when the + modifier is used.
690 This is like BDM, above, except that the branch is expected to be
691 taken. */
692
252b5132 693static unsigned long
2fbfdc41
AM		 694insert_bdp (unsigned long insn,
695 long value,
696 int dialect,
697 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 698{
94efba12 699 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e
AM		 700 {
701 if ((value & 0x8000) == 0)
702 insn |= 1 << 21;
703 }
704 else
705 {
706 if ((insn & (0x14 << 21)) == (0x04 << 21))
707 insn |= 0x03 << 21;
708 else if ((insn & (0x14 << 21)) == (0x10 << 21))
709 insn |= 0x09 << 21;
710 }
252b5132
RH		 711 return insn | (value & 0xfffc);
712}
713
714static long
2fbfdc41
AM		 715extract_bdp (unsigned long insn,
716 int dialect,
717 int *invalid)
252b5132 718{
8427c424 719 if ((dialect & PPC_OPCODE_POWER4) == 0)
802a735e 720 {
8427c424
AM		 721 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
722 *invalid = 1;
723 }
724 else
725 {
726 if ((insn & (0x17 << 21)) != (0x07 << 21)
727 && (insn & (0x1d << 21)) != (0x19 << 21))
728 *invalid = 1;
802a735e 729 }
8427c424 730
802a735e 731 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 732}
733
734/* Check for legal values of a BO field. */
735
736static int
2fbfdc41 737valid_bo (long value, int dialect)
252b5132 738{
94efba12 739 if ((dialect & PPC_OPCODE_POWER4) == 0)
252b5132 740 {
802a735e
AM		 741 /* Certain encodings have bits that are required to be zero.
742 These are (z must be zero, y may be anything):
743 001zy
744 011zy
745 1z00y
746 1z01y
747 1z1zz
748 */
749 switch (value & 0x14)
750 {
751 default:
752 case 0:
753 return 1;
754 case 0x4:
755 return (value & 0x2) == 0;
756 case 0x10:
757 return (value & 0x8) == 0;
758 case 0x14:
759 return value == 0x14;
760 }
761 }
762 else
763 {
764 /* Certain encodings have bits that are required to be zero.
765 These are (z must be zero, a & t may be anything):
766 0000z
767 0001z
768 0100z
769 0101z
770 001at
771 011at
772 1a00t
773 1a01t
774 1z1zz
775 */
776 if ((value & 0x14) == 0)
777 return (value & 0x1) == 0;
778 else if ((value & 0x14) == 0x14)
779 return value == 0x14;
780 else
781 return 1;
252b5132
RH		 782 }
783}
784
785/* The BO field in a B form instruction. Warn about attempts to set
786 the field to an illegal value. */
787
788static unsigned long
2fbfdc41
AM		 789insert_bo (unsigned long insn,
790 long value,
791 int dialect,
792 const char **errmsg)
252b5132 793{
8427c424 794 if (!valid_bo (value, dialect))
252b5132
RH		 795 *errmsg = _("invalid conditional option");
796 return insn | ((value & 0x1f) << 21);
797}
798
799static long
2fbfdc41
AM		 800extract_bo (unsigned long insn,
801 int dialect,
802 int *invalid)
252b5132
RH		 803{
804 long value;
805
806 value = (insn >> 21) & 0x1f;
8427c424 807 if (!valid_bo (value, dialect))
252b5132
RH		 808 *invalid = 1;
809 return value;
810}
811
812/* The BO field in a B form instruction when the + or - modifier is
813 used. This is like the BO field, but it must be even. When
814 extracting it, we force it to be even. */
815
816static unsigned long
2fbfdc41
AM		 817insert_boe (unsigned long insn,
818 long value,
819 int dialect,
820 const char **errmsg)
252b5132 821{
8427c424
AM		 822 if (!valid_bo (value, dialect))
823 *errmsg = _("invalid conditional option");
824 else if ((value & 1) != 0)
825 *errmsg = _("attempt to set y bit when using + or - modifier");
826
252b5132
RH		 827 return insn | ((value & 0x1f) << 21);
828}
829
830static long
2fbfdc41
AM		 831extract_boe (unsigned long insn,
832 int dialect,
833 int *invalid)
252b5132
RH		 834{
835 long value;
836
837 value = (insn >> 21) & 0x1f;
8427c424 838 if (!valid_bo (value, dialect))
252b5132
RH		 839 *invalid = 1;
840 return value & 0x1e;
841}
842
8427c424
AM		 843/* The DQ field in a DQ form instruction. This is like D, but the
844 lower four bits are forced to zero. */
adadcc0c 845
adadcc0c 846static unsigned long
2fbfdc41
AM		 847insert_dq (unsigned long insn,
848 long value,
849 int dialect ATTRIBUTE_UNUSED,
8427c424 850 const char **errmsg)
adadcc0c 851{
8427c424 852 if ((value & 0xf) != 0)
adadcc0c
AM		 853 *errmsg = _("offset not a multiple of 16");
854 return insn | (value & 0xfff0);
855}
856
adadcc0c 857static long
2fbfdc41
AM		 858extract_dq (unsigned long insn,
859 int dialect ATTRIBUTE_UNUSED,
860 int *invalid ATTRIBUTE_UNUSED)
adadcc0c
AM		 861{
862 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
863}
864
23976049 865static unsigned long
2fbfdc41
AM		 866insert_ev2 (unsigned long insn,
867 long value,
868 int dialect ATTRIBUTE_UNUSED,
8427c424 869 const char **errmsg)
23976049 870{
8427c424 871 if ((value & 1) != 0)
23976049 872 *errmsg = _("offset not a multiple of 2");
8427c424 873 if ((value > 62) != 0)
23976049 874 *errmsg = _("offset greater than 62");
914749f6 875 return insn | ((value & 0x3e) << 10);
23976049
EZ		 876}
877
878static long
2fbfdc41
AM		 879extract_ev2 (unsigned long insn,
880 int dialect ATTRIBUTE_UNUSED,
881 int *invalid ATTRIBUTE_UNUSED)
23976049 882{
914749f6 883 return (insn >> 10) & 0x3e;
23976049
EZ		 884}
885
886static unsigned long
2fbfdc41
AM		 887insert_ev4 (unsigned long insn,
888 long value,
889 int dialect ATTRIBUTE_UNUSED,
8427c424 890 const char **errmsg)
23976049 891{
8427c424 892 if ((value & 3) != 0)
23976049 893 *errmsg = _("offset not a multiple of 4");
8427c424 894 if ((value > 124) != 0)
23976049 895 *errmsg = _("offset greater than 124");
914749f6 896 return insn | ((value & 0x7c) << 9);
23976049
EZ		 897}
898
899static long
2fbfdc41
AM		 900extract_ev4 (unsigned long insn,
901 int dialect ATTRIBUTE_UNUSED,
902 int *invalid ATTRIBUTE_UNUSED)
23976049 903{
914749f6 904 return (insn >> 9) & 0x7c;
23976049
EZ		 905}
906
907static unsigned long
2fbfdc41
AM		 908insert_ev8 (unsigned long insn,
909 long value,
910 int dialect ATTRIBUTE_UNUSED,
8427c424 911 const char **errmsg)
23976049 912{
8427c424 913 if ((value & 7) != 0)
23976049 914 *errmsg = _("offset not a multiple of 8");
8427c424 915 if ((value > 248) != 0)
23976049
EZ		 916 *errmsg = _("offset greater than 248");
917 return insn | ((value & 0xf8) << 8);
918}
919
920static long
2fbfdc41
AM		 921extract_ev8 (unsigned long insn,
922 int dialect ATTRIBUTE_UNUSED,
8427c424 923 int *invalid ATTRIBUTE_UNUSED)
23976049
EZ		 924{
925 return (insn >> 8) & 0xf8;
926}
927
252b5132
RH		 928/* The DS field in a DS form instruction. This is like D, but the
929 lower two bits are forced to zero. */
930
252b5132 931static unsigned long
2fbfdc41
AM		 932insert_ds (unsigned long insn,
933 long value,
934 int dialect ATTRIBUTE_UNUSED,
935 const char **errmsg)
252b5132 936{
8427c424 937 if ((value & 3) != 0)
6ba045b1 938 *errmsg = _("offset not a multiple of 4");
252b5132
RH		 939 return insn | (value & 0xfffc);
940}
941
252b5132 942static long
2fbfdc41
AM		 943extract_ds (unsigned long insn,
944 int dialect ATTRIBUTE_UNUSED,
945 int *invalid ATTRIBUTE_UNUSED)
252b5132 946{
802a735e 947 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
252b5132
RH		 948}
949
418c1742
MG		 950/* The DE field in a DE form instruction. */
951
418c1742 952static unsigned long
2fbfdc41
AM		 953insert_de (unsigned long insn,
954 long value,
955 int dialect ATTRIBUTE_UNUSED,
956 const char **errmsg)
418c1742 957{
8427c424 958 if (value > 2047 || value < -2048)
418c1742
MG		 959 *errmsg = _("offset not between -2048 and 2047");
960 return insn | ((value << 4) & 0xfff0);
961}
962
418c1742 963static long
2fbfdc41
AM		 964extract_de (unsigned long insn,
965 int dialect ATTRIBUTE_UNUSED,
966 int *invalid ATTRIBUTE_UNUSED)
418c1742
MG		 967{
968 return (insn & 0xfff0) >> 4;
969}
970
971/* The DES field in a DES form instruction. */
972
418c1742 973static unsigned long
2fbfdc41
AM		 974insert_des (unsigned long insn,
975 long value,
976 int dialect ATTRIBUTE_UNUSED,
977 const char **errmsg)
418c1742 978{
8427c424 979 if (value > 8191 || value < -8192)
418c1742 980 *errmsg = _("offset not between -8192 and 8191");
8427c424 981 else if ((value & 3) != 0)
418c1742
MG		 982 *errmsg = _("offset not a multiple of 4");
983 return insn | ((value << 2) & 0xfff0);
984}
985
418c1742 986static long
2fbfdc41
AM		 987extract_des (unsigned long insn,
988 int dialect ATTRIBUTE_UNUSED,
989 int *invalid ATTRIBUTE_UNUSED)
418c1742 990{
802a735e 991 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
418c1742
MG		 992}
993
2fbfdc41
AM		 994/* FXM mask in mfcr and mtcrf instructions. */
995
996static unsigned long
997insert_fxm (unsigned long insn,
998 long value,
999 int dialect,
1000 const char **errmsg)
c168870a 1001{
98e69875
AM		 1002 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1003 one bit of the mask field is set. */
1004 if ((insn & (1 << 20)) != 0)
1005 {
1006 if (value == 0 || (value & -value) != value)
1007 {
1008 *errmsg = _("invalid mask field");
1009 value = 0;
1010 }
1011 }
1012
c168870a
AM		 1013 /* If the optional field on mfcr is missing that means we want to use
1014 the old form of the instruction that moves the whole cr. In that
1015 case we'll have VALUE zero. There doesn't seem to be a way to
1016 distinguish this from the case where someone writes mfcr %r3,0. */
98e69875 1017 else if (value == 0)
c168870a
AM		 1018 ;
1019
1020 /* If only one bit of the FXM field is set, we can use the new form
661bd698 1021 of the instruction, which is faster. Unlike the Power4 branch hint
a30e9cc4
AM		 1022 encoding, this is not backward compatible. Do not generate the
1023 new form unless -mpower4 has been given, or -many and the two
1024 operand form of mfcr was used. */
1025 else if ((value & -value) == value
1026 && ((dialect & PPC_OPCODE_POWER4) != 0
1027 || ((dialect & PPC_OPCODE_ANY) != 0
1028 && (insn & (0x3ff << 1)) == 19 << 1)))
c168870a
AM		 1029 insn |= 1 << 20;
1030
1031 /* Any other value on mfcr is an error. */
1032 else if ((insn & (0x3ff << 1)) == 19 << 1)
1033 {
8427c424 1034 *errmsg = _("ignoring invalid mfcr mask");
c168870a
AM		 1035 value = 0;
1036 }
1037
1038 return insn | ((value & 0xff) << 12);
1039}
1040
2fbfdc41
AM		 1041static long
1042extract_fxm (unsigned long insn,
98e69875 1043 int dialect ATTRIBUTE_UNUSED,
2fbfdc41 1044 int *invalid)
c168870a
AM		 1045{
1046 long mask = (insn >> 12) & 0xff;
1047
1048 /* Is this a Power4 insn? */
1049 if ((insn & (1 << 20)) != 0)
1050 {
98e69875
AM		 1051 /* Exactly one bit of MASK should be set. */
1052 if (mask == 0 || (mask & -mask) != mask)
8427c424 1053 *invalid = 1;
c168870a
AM		 1054 }
1055
1056 /* Check that non-power4 form of mfcr has a zero MASK. */
1057 else if ((insn & (0x3ff << 1)) == 19 << 1)
1058 {
8427c424 1059 if (mask != 0)
c168870a
AM		 1060 *invalid = 1;
1061 }
1062
1063 return mask;
1064}
1065
252b5132
RH		 1066/* The LI field in an I form instruction. The lower two bits are
1067 forced to zero. */
1068
252b5132 1069static unsigned long
2fbfdc41
AM		 1070insert_li (unsigned long insn,
1071 long value,
1072 int dialect ATTRIBUTE_UNUSED,
1073 const char **errmsg)
252b5132 1074{
8427c424 1075 if ((value & 3) != 0)
252b5132
RH		 1076 *errmsg = _("ignoring least significant bits in branch offset");
1077 return insn | (value & 0x3fffffc);
1078}
1079
252b5132 1080static long
2fbfdc41
AM		 1081extract_li (unsigned long insn,
1082 int dialect ATTRIBUTE_UNUSED,
1083 int *invalid ATTRIBUTE_UNUSED)
252b5132 1084{
802a735e 1085 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
252b5132
RH		 1086}
1087
1088/* The MB and ME fields in an M form instruction expressed as a single
1089 operand which is itself a bitmask. The extraction function always
1090 marks it as invalid, since we never want to recognize an
1091 instruction which uses a field of this type. */
1092
1093static unsigned long
2fbfdc41
AM		 1094insert_mbe (unsigned long insn,
1095 long value,
1096 int dialect ATTRIBUTE_UNUSED,
1097 const char **errmsg)
252b5132
RH		 1098{
1099 unsigned long uval, mask;
1100 int mb, me, mx, count, last;
1101
1102 uval = value;
1103
1104 if (uval == 0)
1105 {
8427c424 1106 *errmsg = _("illegal bitmask");
252b5132
RH		 1107 return insn;
1108 }
1109
1110 mb = 0;
1111 me = 32;
1112 if ((uval & 1) != 0)
1113 last = 1;
1114 else
1115 last = 0;
1116 count = 0;
1117
1118 /* mb: location of last 0->1 transition */
1119 /* me: location of last 1->0 transition */
1120 /* count: # transitions */
1121
0deb7ac5 1122 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
252b5132
RH		 1123 {
1124 if ((uval & mask) && !last)
1125 {
1126 ++count;
1127 mb = mx;
1128 last = 1;
1129 }
1130 else if (!(uval & mask) && last)
1131 {
1132 ++count;
1133 me = mx;
1134 last = 0;
1135 }
1136 }
1137 if (me == 0)
1138 me = 32;
1139
1140 if (count != 2 && (count != 0 || ! last))
8427c424 1141 *errmsg = _("illegal bitmask");
252b5132
RH		 1142
1143 return insn | (mb << 6) | ((me - 1) << 1);
1144}
1145
1146static long
2fbfdc41
AM		 1147extract_mbe (unsigned long insn,
1148 int dialect ATTRIBUTE_UNUSED,
1149 int *invalid)
252b5132
RH		 1150{
1151 long ret;
1152 int mb, me;
1153 int i;
1154
8427c424 1155 *invalid = 1;
252b5132
RH		 1156
1157 mb = (insn >> 6) & 0x1f;
1158 me = (insn >> 1) & 0x1f;
1159 if (mb < me + 1)
1160 {
1161 ret = 0;
1162 for (i = mb; i <= me; i++)
0deb7ac5 1163 ret |= 1L << (31 - i);
252b5132
RH		 1164 }
1165 else if (mb == me + 1)
8427c424 1166 ret = ~0;
252b5132
RH		 1167 else /* (mb > me + 1) */
1168 {
2fbfdc41 1169 ret = ~0;
252b5132 1170 for (i = me + 1; i < mb; i++)
0deb7ac5 1171 ret &= ~(1L << (31 - i));
252b5132
RH		 1172 }
1173 return ret;
1174}
1175
1176/* The MB or ME field in an MD or MDS form instruction. The high bit
1177 is wrapped to the low end. */
1178
252b5132 1179static unsigned long
2fbfdc41
AM		 1180insert_mb6 (unsigned long insn,
1181 long value,
1182 int dialect ATTRIBUTE_UNUSED,
1183 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1184{
1185 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1186}
1187
252b5132 1188static long
2fbfdc41
AM		 1189extract_mb6 (unsigned long insn,
1190 int dialect ATTRIBUTE_UNUSED,
1191 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1192{
1193 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1194}
1195
1196/* The NB field in an X form instruction. The value 32 is stored as
1197 0. */
1198
1199static unsigned long
2fbfdc41
AM		 1200insert_nb (unsigned long insn,
1201 long value,
1202 int dialect ATTRIBUTE_UNUSED,
1203 const char **errmsg)
252b5132
RH		 1204{
1205 if (value < 0 || value > 32)
1206 *errmsg = _("value out of range");
1207 if (value == 32)
1208 value = 0;
1209 return insn | ((value & 0x1f) << 11);
1210}
1211
252b5132 1212static long
2fbfdc41
AM		 1213extract_nb (unsigned long insn,
1214 int dialect ATTRIBUTE_UNUSED,
1215 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1216{
1217 long ret;
1218
1219 ret = (insn >> 11) & 0x1f;
1220 if (ret == 0)
1221 ret = 32;
1222 return ret;
1223}
1224
1225/* The NSI field in a D form instruction. This is the same as the SI
1226 field, only negated. The extraction function always marks it as
1227 invalid, since we never want to recognize an instruction which uses
1228 a field of this type. */
1229
252b5132 1230static unsigned long
2fbfdc41
AM		 1231insert_nsi (unsigned long insn,
1232 long value,
1233 int dialect ATTRIBUTE_UNUSED,
1234 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 1235{
2fbfdc41 1236 return insn | (-value & 0xffff);
252b5132
RH		 1237}
1238
1239static long
2fbfdc41
AM		 1240extract_nsi (unsigned long insn,
1241 int dialect ATTRIBUTE_UNUSED,
1242 int *invalid)
252b5132 1243{
8427c424 1244 *invalid = 1;
2fbfdc41 1245 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
252b5132
RH		 1246}
1247
1248/* The RA field in a D or X form instruction which is an updating
1249 load, which means that the RA field may not be zero and may not
1250 equal the RT field. */
1251
1252static unsigned long
2fbfdc41
AM		 1253insert_ral (unsigned long insn,
1254 long value,
1255 int dialect ATTRIBUTE_UNUSED,
1256 const char **errmsg)
252b5132
RH		 1257{
1258 if (value == 0
1259 || (unsigned long) value == ((insn >> 21) & 0x1f))
1260 *errmsg = "invalid register operand when updating";
1261 return insn | ((value & 0x1f) << 16);
1262}
1263
1264/* The RA field in an lmw instruction, which has special value
1265 restrictions. */
1266
1267static unsigned long
2fbfdc41
AM		 1268insert_ram (unsigned long insn,
1269 long value,
1270 int dialect ATTRIBUTE_UNUSED,
1271 const char **errmsg)
252b5132
RH		 1272{
1273 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1274 *errmsg = _("index register in load range");
1275 return insn | ((value & 0x1f) << 16);
1276}
1277
fdd12ef3 1278/* The RA field in the DQ form lq instruction, which has special
8427c424 1279 value restrictions. */
adadcc0c 1280
adadcc0c 1281static unsigned long
2fbfdc41
AM		 1282insert_raq (unsigned long insn,
1283 long value,
1284 int dialect ATTRIBUTE_UNUSED,
1285 const char **errmsg)
adadcc0c
AM		 1286{
1287 long rtvalue = (insn & RT_MASK) >> 21;
1288
8427c424 1289 if (value == rtvalue)
adadcc0c
AM		 1290 *errmsg = _("source and target register operands must be different");
1291 return insn | ((value & 0x1f) << 16);
1292}
1293
252b5132
RH		 1294/* The RA field in a D or X form instruction which is an updating
1295 store or an updating floating point load, which means that the RA
1296 field may not be zero. */
1297
1298static unsigned long
2fbfdc41
AM		 1299insert_ras (unsigned long insn,
1300 long value,
1301 int dialect ATTRIBUTE_UNUSED,
1302 const char **errmsg)
252b5132
RH		 1303{
1304 if (value == 0)
1305 *errmsg = _("invalid register operand when updating");
1306 return insn | ((value & 0x1f) << 16);
1307}
1308
1309/* The RB field in an X form instruction when it must be the same as
1310 the RS field in the instruction. This is used for extended
1311 mnemonics like mr. This operand is marked FAKE. The insertion
1312 function just copies the BT field into the BA field, and the
1313 extraction function just checks that the fields are the same. */
1314
252b5132 1315static unsigned long
2fbfdc41
AM		 1316insert_rbs (unsigned long insn,
1317 long value ATTRIBUTE_UNUSED,
1318 int dialect ATTRIBUTE_UNUSED,
1319 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1320{
1321 return insn | (((insn >> 21) & 0x1f) << 11);
1322}
1323
1324static long
2fbfdc41
AM		 1325extract_rbs (unsigned long insn,
1326 int dialect ATTRIBUTE_UNUSED,
1327 int *invalid)
252b5132 1328{
8427c424 1329 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
252b5132
RH		 1330 *invalid = 1;
1331 return 0;
1332}
1333
8427c424
AM		 1334/* The RT field of the DQ form lq instruction, which has special
1335 value restrictions. */
adadcc0c 1336
adadcc0c 1337static unsigned long
2fbfdc41
AM		 1338insert_rtq (unsigned long insn,
1339 long value,
1340 int dialect ATTRIBUTE_UNUSED,
1341 const char **errmsg)
adadcc0c 1342{
8427c424 1343 if ((value & 1) != 0)
adadcc0c
AM		 1344 *errmsg = _("target register operand must be even");
1345 return insn | ((value & 0x1f) << 21);
1346}
1347
fdd12ef3 1348/* The RS field of the DS form stq instruction, which has special
8427c424 1349 value restrictions. */
adadcc0c 1350
adadcc0c 1351static unsigned long
2fbfdc41
AM		 1352insert_rsq (unsigned long insn,
1353 long value ATTRIBUTE_UNUSED,
1354 int dialect ATTRIBUTE_UNUSED,
1355 const char **errmsg)
adadcc0c 1356{
8427c424 1357 if ((value & 1) != 0)
adadcc0c
AM		 1358 *errmsg = _("source register operand must be even");
1359 return insn | ((value & 0x1f) << 21);
1360}
1361
252b5132
RH		 1362/* The SH field in an MD form instruction. This is split. */
1363
252b5132 1364static unsigned long
2fbfdc41
AM		 1365insert_sh6 (unsigned long insn,
1366 long value,
1367 int dialect ATTRIBUTE_UNUSED,
1368 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1369{
1370 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1371}
1372
252b5132 1373static long
2fbfdc41
AM		 1374extract_sh6 (unsigned long insn,
1375 int dialect ATTRIBUTE_UNUSED,
1376 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1377{
1378 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1379}
1380
1381/* The SPR field in an XFX form instruction. This is flipped--the
1382 lower 5 bits are stored in the upper 5 and vice- versa. */
1383
1384static unsigned long
2fbfdc41
AM		 1385insert_spr (unsigned long insn,
1386 long value,
1387 int dialect ATTRIBUTE_UNUSED,
1388 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1389{
1390 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1391}
1392
1393static long
2fbfdc41
AM		 1394extract_spr (unsigned long insn,
1395 int dialect ATTRIBUTE_UNUSED,
1396 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1397{
1398 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1399}
1400
da99ee72
AM		 1401/* Some dialects have 8 SPRG registers instead of the standard 4. */
1402
1403static unsigned long
1404insert_sprg (unsigned long insn,
1405 long value,
1406 int dialect,
1407 const char **errmsg)
1408{
1409 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1410 as a synonym. If ever a 405 specific dialect is added this
1411 check should use that instead. */
1412 if (value > 7
1413 || (value > 3
1414 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1415 *errmsg = _("invalid sprg number");
1416
1417 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1418 user mode. Anything else must use spr 272..279. */
1419 if (value <= 3 || (insn & 0x100) != 0)
1420 value |= 0x10;
1421
1422 return insn | ((value & 0x17) << 16);
1423}
1424
1425static long
1426extract_sprg (unsigned long insn,
1427 int dialect,
1428 int *invalid)
1429{
1430 unsigned long val = (insn >> 16) & 0x1f;
1431
1432 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1433 If not BOOKE or 405, then both use only 272..275. */
1434 if (val <= 3
1435 || (val < 0x10 && (insn & 0x100) != 0)
1436 || (val - 0x10 > 3
1437 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1438 *invalid = 1;
1439 return val & 7;
1440}
1441
252b5132
RH		 1442/* The TBR field in an XFX instruction. This is just like SPR, but it
1443 is optional. When TBR is omitted, it must be inserted as 268 (the
1444 magic number of the TB register). These functions treat 0
1445 (indicating an omitted optional operand) as 268. This means that
1446 ``mftb 4,0'' is not handled correctly. This does not matter very
1447 much, since the architecture manual does not define mftb as
1448 accepting any values other than 268 or 269. */
1449
1450#define TB (268)
1451
1452static unsigned long
2fbfdc41
AM		 1453insert_tbr (unsigned long insn,
1454 long value,
1455 int dialect ATTRIBUTE_UNUSED,
1456 const char **errmsg ATTRIBUTE_UNUSED)
252b5132
RH		 1457{
1458 if (value == 0)
1459 value = TB;
1460 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1461}
1462
1463static long
2fbfdc41
AM		 1464extract_tbr (unsigned long insn,
1465 int dialect ATTRIBUTE_UNUSED,
1466 int *invalid ATTRIBUTE_UNUSED)
252b5132
RH		 1467{
1468 long ret;
1469
1470 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1471 if (ret == TB)
1472 ret = 0;
1473 return ret;
1474}
1475\f
1476/* Macros used to form opcodes. */
1477
1478/* The main opcode. */
1479#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1480#define OP_MASK OP (0x3f)
1481
1482/* The main opcode combined with a trap code in the TO field of a D
1483 form instruction. Used for extended mnemonics for the trap
1484 instructions. */
1485#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1486#define OPTO_MASK (OP_MASK | TO_MASK)
1487
1488/* The main opcode combined with a comparison size bit in the L field
1489 of a D form or X form instruction. Used for extended mnemonics for
1490 the comparison instructions. */
1491#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1492#define OPL_MASK OPL (0x3f,1)
1493
1494/* An A form instruction. */
1495#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1496#define A_MASK A (0x3f, 0x1f, 1)
1497
1498/* An A_MASK with the FRB field fixed. */
1499#define AFRB_MASK (A_MASK | FRB_MASK)
1500
1501/* An A_MASK with the FRC field fixed. */
1502#define AFRC_MASK (A_MASK | FRC_MASK)
1503
1504/* An A_MASK with the FRA and FRC fields fixed. */
1505#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1506
1507/* A B form instruction. */
1508#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1509#define B_MASK B (0x3f, 1, 1)
1510
1511/* A B form instruction setting the BO field. */
1512#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1513#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1514
1515/* A BBO_MASK with the y bit of the BO field removed. This permits
1516 matching a conditional branch regardless of the setting of the y
94efba12 1517 bit. Similarly for the 'at' bits used for power4 branch hints. */
802a735e
AM		 1518#define Y_MASK (((unsigned long) 1) << 21)
1519#define AT1_MASK (((unsigned long) 3) << 21)
1520#define AT2_MASK (((unsigned long) 9) << 21)
1521#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1522#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
252b5132
RH		 1523
1524/* A B form instruction setting the BO field and the condition bits of
1525 the BI field. */
1526#define BBOCB(op, bo, cb, aa, lk) \
1527 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1528#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1529
1530/* A BBOCB_MASK with the y bit of the BO field removed. */
1531#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
802a735e
AM		 1532#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1533#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
252b5132
RH		 1534
1535/* A BBOYCB_MASK in which the BI field is fixed. */
1536#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
802a735e 1537#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
252b5132 1538
23976049
EZ		 1539/* An Context form instruction. */
1540#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
fdd12ef3 1541#define CTX_MASK CTX(0x3f, 0x7)
23976049
EZ		 1542
1543/* An User Context form instruction. */
1544#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
fdd12ef3 1545#define UCTX_MASK UCTX(0x3f, 0x1f)
23976049 1546
252b5132
RH		 1547/* The main opcode mask with the RA field clear. */
1548#define DRA_MASK (OP_MASK | RA_MASK)
1549
1550/* A DS form instruction. */
1551#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1552#define DS_MASK DSO (0x3f, 3)
1553
418c1742
MG		 1554/* A DE form instruction. */
1555#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1556#define DE_MASK DEO (0x3e, 0xf)
1557
23976049
EZ		 1558/* An EVSEL form instruction. */
1559#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1560#define EVSEL_MASK EVSEL(0x3f, 0xff)
1561
252b5132
RH		 1562/* An M form instruction. */
1563#define M(op, rc) (OP (op) | ((rc) & 1))
1564#define M_MASK M (0x3f, 1)
1565
1566/* An M form instruction with the ME field specified. */
1567#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1568
1569/* An M_MASK with the MB and ME fields fixed. */
1570#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1571
1572/* An M_MASK with the SH and ME fields fixed. */
1573#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1574
1575/* An MD form instruction. */
1576#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1577#define MD_MASK MD (0x3f, 0x7, 1)
1578
1579/* An MD_MASK with the MB field fixed. */
1580#define MDMB_MASK (MD_MASK | MB6_MASK)
1581
1582/* An MD_MASK with the SH field fixed. */
1583#define MDSH_MASK (MD_MASK | SH6_MASK)
1584
1585/* An MDS form instruction. */
1586#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1587#define MDS_MASK MDS (0x3f, 0xf, 1)
1588
1589/* An MDS_MASK with the MB field fixed. */
1590#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1591
1592/* An SC form instruction. */
1593#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1594#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1595
112290ab 1596/* An VX form instruction. */
786e2c0f
C		 1597#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1598
112290ab 1599/* The mask for an VX form instruction. */
786e2c0f
C		 1600#define VX_MASK VX(0x3f, 0x7ff)
1601
112290ab 1602/* An VA form instruction. */
2613489e 1603#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
786e2c0f 1604
112290ab 1605/* The mask for an VA form instruction. */
2613489e 1606#define VXA_MASK VXA(0x3f, 0x3f)
786e2c0f 1607
112290ab 1608/* An VXR form instruction. */
786e2c0f
C		 1609#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1610
112290ab 1611/* The mask for a VXR form instruction. */
786e2c0f
C		 1612#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1613
252b5132
RH		 1614/* An X form instruction. */
1615#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1616
1617/* An X form instruction with the RC bit specified. */
1618#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1619
1620/* The mask for an X form instruction. */
1621#define X_MASK XRC (0x3f, 0x3ff, 1)
1622
1623/* An X_MASK with the RA field fixed. */
1624#define XRA_MASK (X_MASK | RA_MASK)
1625
1626/* An X_MASK with the RB field fixed. */
1627#define XRB_MASK (X_MASK | RB_MASK)
1628
1629/* An X_MASK with the RT field fixed. */
1630#define XRT_MASK (X_MASK | RT_MASK)
1631
1632/* An X_MASK with the RA and RB fields fixed. */
1633#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1634
112290ab 1635/* An XRARB_MASK, but with the L bit clear. */
5ae2e65e
AM		 1636#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1637
252b5132
RH		 1638/* An X_MASK with the RT and RA fields fixed. */
1639#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1640
98acc1c5
AM		 1641/* An XRTRA_MASK, but with L bit clear. */
1642#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1643
f3806e43
BE		 1644/* An X form instruction with the L bit specified. */
1645#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
252b5132
RH		 1646
1647/* The mask for an X form comparison instruction. */
1648#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1649
520ceea4
BE		 1650/* The mask for an X form comparison instruction with the L field
1651 fixed. */
1652#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
252b5132
RH		 1653
1654/* An X form trap instruction with the TO field specified. */
1655#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1656#define XTO_MASK (X_MASK | TO_MASK)
1657
e0c21649
GK		 1658/* An X form tlb instruction with the SH field specified. */
1659#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1660#define XTLB_MASK (X_MASK | SH_MASK)
1661
6ba045b1
AM		 1662/* An X form sync instruction. */
1663#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1664
1665/* An X form sync instruction with everything filled in except the LS field. */
1666#define XSYNC_MASK (0xff9fffff)
1667
f5c120c5
MG		 1668/* An X form AltiVec dss instruction. */
1669#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1670#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1671
252b5132
RH		 1672/* An XFL form instruction. */
1673#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1674#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1675
23976049
EZ		 1676/* An X form isel instruction. */
1677#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1678#define XISEL_MASK XISEL(0x3f, 0x1f)
1679
252b5132
RH		 1680/* An XL form instruction with the LK field set to 0. */
1681#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1682
1683/* An XL form instruction which uses the LK field. */
1684#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1685
1686/* The mask for an XL form instruction. */
1687#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1688
1689/* An XL form instruction which explicitly sets the BO field. */
1690#define XLO(op, bo, xop, lk) \
1691 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1692#define XLO_MASK (XL_MASK | BO_MASK)
1693
1694/* An XL form instruction which explicitly sets the y bit of the BO
1695 field. */
1696#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1697#define XLYLK_MASK (XL_MASK | Y_MASK)
1698
1699/* An XL form instruction which sets the BO field and the condition
1700 bits of the BI field. */
1701#define XLOCB(op, bo, cb, xop, lk) \
1702 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1703#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1704
1705/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1706#define XLBB_MASK (XL_MASK | BB_MASK)
1707#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1708#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1709
d0618d1c
AM		 1710/* A mask for branch instructions using the BH field. */
1711#define XLBH_MASK (XL_MASK | (0x1c << 11))
1712
252b5132
RH		 1713/* An XL_MASK with the BO and BB fields fixed. */
1714#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1715
1716/* An XL_MASK with the BO, BI and BB fields fixed. */
1717#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1718
1719/* An XO form instruction. */
1720#define XO(op, xop, oe, rc) \
1721 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1722#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1723
1724/* An XO_MASK with the RB field fixed. */
1725#define XORB_MASK (XO_MASK | RB_MASK)
1726
1727/* An XS form instruction. */
1728#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1729#define XS_MASK XS (0x3f, 0x1ff, 1)
1730
1731/* A mask for the FXM version of an XFX form instruction. */
98e69875 1732#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
252b5132
RH		 1733
1734/* An XFX form instruction with the FXM field filled in. */
98e69875
AM		 1735#define XFXM(op, xop, fxm, p4) \
1736 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1737 | ((unsigned long)(p4) << 20))
252b5132
RH		 1738
1739/* An XFX form instruction with the SPR field filled in. */
1740#define XSPR(op, xop, spr) \
1741 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1742#define XSPR_MASK (X_MASK | SPR_MASK)
1743
1744/* An XFX form instruction with the SPR field filled in except for the
1745 SPRBAT field. */
1746#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1747
1748/* An XFX form instruction with the SPR field filled in except for the
1749 SPRG field. */
da99ee72 1750#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
252b5132
RH		 1751
1752/* An X form instruction with everything filled in except the E field. */
1753#define XE_MASK (0xffff7fff)
1754
23976049
EZ		 1755/* An X form user context instruction. */
1756#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1757#define XUC_MASK XUC(0x3f, 0x1f)
1758
252b5132
RH		 1759/* The BO encodings used in extended conditional branch mnemonics. */
1760#define BODNZF (0x0)
1761#define BODNZFP (0x1)
1762#define BODZF (0x2)
1763#define BODZFP (0x3)
252b5132
RH		 1764#define BODNZT (0x8)
1765#define BODNZTP (0x9)
1766#define BODZT (0xa)
1767#define BODZTP (0xb)
802a735e
AM		 1768
1769#define BOF (0x4)
1770#define BOFP (0x5)
94efba12
AM		 1771#define BOFM4 (0x6)
1772#define BOFP4 (0x7)
252b5132
RH		 1773#define BOT (0xc)
1774#define BOTP (0xd)
94efba12
AM		 1775#define BOTM4 (0xe)
1776#define BOTP4 (0xf)
802a735e 1777
252b5132
RH		 1778#define BODNZ (0x10)
1779#define BODNZP (0x11)
1780#define BODZ (0x12)
1781#define BODZP (0x13)
94efba12
AM		 1782#define BODNZM4 (0x18)
1783#define BODNZP4 (0x19)
1784#define BODZM4 (0x1a)
1785#define BODZP4 (0x1b)
802a735e 1786
252b5132
RH		 1787#define BOU (0x14)
1788
1789/* The BI condition bit encodings used in extended conditional branch
1790 mnemonics. */
1791#define CBLT (0)
1792#define CBGT (1)
1793#define CBEQ (2)
1794#define CBSO (3)
1795
1796/* The TO encodings used in extended trap mnemonics. */
1797#define TOLGT (0x1)
1798#define TOLLT (0x2)
1799#define TOEQ (0x4)
1800#define TOLGE (0x5)
1801#define TOLNL (0x5)
1802#define TOLLE (0x6)
1803#define TOLNG (0x6)
1804#define TOGT (0x8)
1805#define TOGE (0xc)
1806#define TONL (0xc)
1807#define TOLT (0x10)
1808#define TOLE (0x14)
1809#define TONG (0x14)
1810#define TONE (0x18)
1811#define TOU (0x1f)
1812\f
1813/* Smaller names for the flags so each entry in the opcodes table will
1814 fit on a single line. */
1815#undef PPC
661bd698
AM		 1816#define PPC PPC_OPCODE_PPC
1817#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
94efba12 1818#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
661bd698
AM		 1819#define POWER4 PPC_OPCODE_POWER4
1820#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1821#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
418c1742 1822#define PPC403 PPC_OPCODE_403
e0c21649 1823#define PPC405 PPC403
7d5b217e 1824#define PPC440 PPC_OPCODE_440
252b5132
RH		 1825#define PPC750 PPC
1826#define PPC860 PPC
a404d431 1827#define PPCVEC PPC_OPCODE_ALTIVEC
661bd698
AM		 1828#define POWER PPC_OPCODE_POWER
1829#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1830#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1831#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1832#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1833#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1834#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1835#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
252b5132 1836#define MFDEC1 PPC_OPCODE_POWER
dde1b132 1837#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
418c1742
MG		 1838#define BOOKE PPC_OPCODE_BOOKE
1839#define BOOKE64 PPC_OPCODE_BOOKE64
23976049
EZ		 1840#define CLASSIC PPC_OPCODE_CLASSIC
1841#define PPCSPE PPC_OPCODE_SPE
1842#define PPCISEL PPC_OPCODE_ISEL
1843#define PPCEFS PPC_OPCODE_EFS
1844#define PPCBRLK PPC_OPCODE_BRLOCK
1845#define PPCPMR PPC_OPCODE_PMR
1846#define PPCCHLK PPC_OPCODE_CACHELCK
dde1b132 1847#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
23976049 1848#define PPCRFMCI PPC_OPCODE_RFMCI
252b5132
RH		 1849\f
1850/* The opcode table.
1851
1852 The format of the opcode table is:
1853
1854 NAME OPCODE MASK FLAGS { OPERANDS }
1855
1856 NAME is the name of the instruction.
1857 OPCODE is the instruction opcode.
1858 MASK is the opcode mask; this is used to tell the disassembler
1859 which bits in the actual opcode must match OPCODE.
1860 FLAGS are flags indicated what processors support the instruction.
1861 OPERANDS is the list of operands.
1862
1863 The disassembler reads the table in order and prints the first
1864 instruction which matches, so this table is sorted to put more
1865 specific instructions before more general instructions. It is also
1866 sorted by major opcode. */
1867
1868const struct powerpc_opcode powerpc_opcodes[] = {
adadcc0c 1869{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
252b5132
RH		 1870{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1871{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1872{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1873{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1874{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1875{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1876{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1877{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1878{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1879{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1880{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1881{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1882{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1883{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1884{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1885
1886{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1887{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1888{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1889{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1890{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1891{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1892{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1893{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1894{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1895{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1896{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1897{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1898{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1899{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1900{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1901{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1902{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1903{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1904{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1905{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1906{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1907{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1908{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1909{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1910{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1911{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1912{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1913{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1914{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1915{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
e0c21649 1916
7d5b217e
AM		 1917{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1918{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1919{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1920{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1921{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1922{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1923{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1924{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1925{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1926{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1927{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1928{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1929{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1953{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1954{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1955{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1956{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1957{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1958{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1959{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1960{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1961{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1962{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1963{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1964{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1965{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1966{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1967{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1968{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1969{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1970{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1971{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1972{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1973{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1974{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1975{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1976{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1977{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1978{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1979{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1980{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1981{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1982{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1983{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1984{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1985{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1986{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1987{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1988{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1991{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1992{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1993{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1994{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1995{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1996{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1997{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1998{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1999{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2000{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
786e2c0f 2001{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
f5c120c5 2002{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
12c64a4e
AH		 2003
2004 /* Double-precision opcodes. */
2005 /* Some of these conflict with AltiVec, so move them before, since
2006 PPCVEC includes the PPC_OPCODE_PPC set. */
0e06657a 2007{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
12c64a4e
AH		 2008{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2009{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2010{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2011{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2012{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2013{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2014{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2015{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2016{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2017{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2018{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2019{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2020{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2021{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2022{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2023{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2024{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2025{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2026{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2027{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2028{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2029{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2030{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2031{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2032{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2033{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2034{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2035{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2036 /* End of double-precision opcodes. */
2037
786e2c0f
C		 2038{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2039{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2040{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2042{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2043{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2044{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2045{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2046{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2047{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2048{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2049{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2050{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2051{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2052{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2053{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2054{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2055{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2056{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2057{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2058{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2059{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2060{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2061{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2062{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2063{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2064{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2065{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2066{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2067{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2068{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2069{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2070{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2071{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2072{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2073{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2074{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2075{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2076{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2077{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2078{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2079{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2080{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2081{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2082{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2083{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2084{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2085{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2086{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2087{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2088{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
294b41b3 2089{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
786e2c0f
C		 2090{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2091{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2092{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2093{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2094{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2095{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2096{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2097{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2098{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2099{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2100{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2101{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2102{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2103{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2104{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2105{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2106{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2107{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2108{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2109{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2110{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2111{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2112{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2113{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2114{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2115{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
d2f75a6f
GK		 2116{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2117{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2118{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
786e2c0f
C		 2119{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2120{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2121{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2122{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2123{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2124{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2125{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2126{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2127{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2128{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2129{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2130{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2131{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2132{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2133{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2134{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2135{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2136{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2137{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2138{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2139{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2140{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2141{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2142{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2143{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2144{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2145{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2146{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2147{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2148{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2149{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2150{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2151{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2152{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2153{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2154{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1da5001c 2155{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
786e2c0f
C		 2156{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2157{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2158{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2159{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2160{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2161{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2162{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2163{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2164{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2165{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2166{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2167{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2168{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2169{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2170{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2171{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2172{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2173{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2174{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2175{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2176{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2177{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2178{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2179{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2180{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2181{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2182{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2183{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2184{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2185{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2186{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2187{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2188{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2189{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2190{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2191{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2192{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
252b5132 2193
914749f6
AH		 2194{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2195{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2196{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2197{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2198{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2199{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2200{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2201{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2202{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2203{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2204{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2205{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2206{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2207
2208{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2209
2210{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2211{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2212{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2213{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2214{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2215{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2216{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2217{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
dde1b132 2218{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
914749f6
AH		 2219{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2220
2221{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2222{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2223{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2224{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2225{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2226{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2227{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2228{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2229{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2230{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
fe587977
AH		 2231{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2232{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2233{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2234{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2235
2236{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2237{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2238{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2239{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2240{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6 2241{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
23976049
EZ		 2242
2243{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2244{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2245{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2246{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2247{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2248{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2249{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2250{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2251{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2252{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2253{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2254{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2255{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2256{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2257{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2258{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2260{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2261{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2262{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2263{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2264{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2265
2266{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2267{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2268{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2269{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2270{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2271{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2272{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2273{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2274{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2275{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2276{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2277{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2278{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2279{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2280
914749f6
AH		 2281{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2282{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2283{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2284{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2285{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2286{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2287{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049
EZ		 2288{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2289{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2290{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2291{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2292{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2293{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
914749f6
AH		 2294{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2295{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2296{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2297{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2298{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2299{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2300{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2301{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2302{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2303{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2304
2305{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2306{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2307{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2308{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2309{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2310{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2311{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
23976049
EZ		 2312{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2313{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2314{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2315{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2316{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2317{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
914749f6
AH		 2318{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2319{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2320{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2321{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2322{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2323{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2324{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2325{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2326{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2327{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2328
914749f6
AH		 2329{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2330{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2331{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2332{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2333{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2334{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2335{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2336{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2337{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2338{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2339{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2340{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2341{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2342{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2343{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2344{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2345
2346{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2347{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2348{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2349{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2350{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2351{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2352{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2353{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2354{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2355{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2356{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2357{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2358
2359{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2360{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2361{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2362{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2363{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2364{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2365{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2366{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2367{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2368{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2369{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2370{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2371
2372{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2373{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2374{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2375{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2376{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2377{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2378
2379{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2380{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2381{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2382{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2383{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2384{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2385
2386{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2387{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2388{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2389{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2390{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2391{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2392{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2393{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2394
914749f6
AH		 2395{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2396{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2397
914749f6 2398{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2399{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2400{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2401{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2402
914749f6 2403{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
914749f6
AH		 2404{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2405{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2406{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2407
914749f6
AH		 2408{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2409{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2410{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2411{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2412{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2413{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2414{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2415{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2416
2417{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2418{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2419{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2420{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2421
2422{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2423{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2424{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2425{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2426
2427{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2428{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2429{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2430{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2431
2432{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2433{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2434{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2435{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2436
2437{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2438
2439{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2440{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
23976049 2441
252b5132
RH		 2442{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2443{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2444
2445{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2446{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2447
2448{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2449
418c1742
MG		 2450{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2451{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2452{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2453{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2454
252b5132
RH		 2455{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2456{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
661bd698 2457{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
252b5132
RH		 2458{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2459
2460{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2461{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
661bd698 2462{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
252b5132
RH		 2463{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2464
2465{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2466{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2467{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2468
2469{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2470{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2471{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2472
2473{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2474{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
fdd12ef3
AM		 2475{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2476{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2477{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2478{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
252b5132
RH		 2479
2480{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2481{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
fdd12ef3
AM		 2482{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2483{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2484{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
252b5132 2485
112290ab
NC		 2486{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2487{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2488{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2489{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2490{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2491{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2492{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2493{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2494{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2495{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2496{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2497{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2498{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2499{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2500{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2501{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2502{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2503{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2504{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2505{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2506{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2507{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2508{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2509{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2510{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2511{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2512{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2513{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
802a735e
AM		 2514{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2515{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2516{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2517{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2518{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2519{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2520{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2521{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2522{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2523{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2524{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2525{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2526{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2527{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2528{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2529{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2530{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2531{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2532{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2533{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2534{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2535{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2536{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2537{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2538{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2539{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2540{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2541{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2542{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2543{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2544{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2545{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2546{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2547{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2548{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2549{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2550{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2551{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2552{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2553{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2554{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2555{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2556{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2557{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2558{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2559{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2560{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2561{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2562{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2563{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2564{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2565{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2566{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2567{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2568{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2569{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2570{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2571{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2572{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2573{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2574{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2575{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2576{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2577{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2578{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2579{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2580{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2581{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2582{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2583{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2584{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2585{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2586{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2587{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2588{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2589{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2590{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2591{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2592{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2593{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2594{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2595{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2596{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2597{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2598{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2599{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2600{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2601{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2602{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2603{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2604{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2605{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2606{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2607{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2608{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2609{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2610{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2611{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2612{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2613{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2614{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2615{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2616{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2617{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2618{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2619{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2620{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2621{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2622{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2623{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2624{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2625{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2626{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2627{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2628{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2629{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2630{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2631{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2632{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2633{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2634{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2635{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2636{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2637{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2638{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2639{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2640{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2641{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2642{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2643{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2644{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2645{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2646{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2647{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2648{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2649{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2650{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2651{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2652{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2653{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2654{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2655{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2656{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2657{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
94efba12
AM		 2658{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2659{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2660{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2661{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2662{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2663{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2664{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2665{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2666{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2667{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2668{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2669{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2670{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2671{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2672{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2673{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2674{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2675{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2676{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2677{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2678{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2679{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2680{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2681{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
802a735e
AM		 2682{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2683{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2684{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2685{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2686{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2687{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2688{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2689{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2690{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2691{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2692{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2693{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2694{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2695{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2696{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2697{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2698{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2699{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2700{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2701{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2702{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2703{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2704{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2705{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2706{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2707{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2708{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2709{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2710{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2711{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2712{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2713{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
94efba12
AM		 2714{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2715{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2716{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2717{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2718{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2719{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2720{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2721{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2722{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2723{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2724{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2725{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2726{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2727{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2728{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2729{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2730{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
252b5132 2731{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
94efba12
AM		 2732{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2733{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2734{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
94efba12
AM		 2735{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2736{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
252b5132 2737{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
d2f75a6f
GK		 2738{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2739{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2740{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2741{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2742{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
252b5132 2743{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
d2f75a6f
GK		 2744{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2745{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132 2746{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
d2f75a6f
GK		 2747{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2748{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
252b5132
RH		 2749{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2750
2751{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2752{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2753{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2754{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2755{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2756
418c1742
MG		 2757{ "b", B(18,0,0), B_MASK, COM, { LI } },
2758{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2759{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2760{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
252b5132 2761
112290ab 2762{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
252b5132
RH		 2763
2764{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2765{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2766{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2767{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2768{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2769{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2770{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2771{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2772{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2773{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2774{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2775{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2776{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2777{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2778{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2779{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2780{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2781{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2782{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2783{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
94efba12 2784{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2785{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
823bbe9d 2786{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
94efba12 2787{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
252b5132 2788{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2789{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2790{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2791{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2792{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2793{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2794{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2795{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2796{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2797{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2798{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2799{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2800{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2801{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2802{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2803{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2804{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2805{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2806{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2807{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2808{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2809{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2810{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2811{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2812{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2813{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2814{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2815{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2816{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2817{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2818{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2819{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2820{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2821{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2822{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2823{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2824{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2825{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2826{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2827{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2828{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2829{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2830{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2831{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2832{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2833{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2834{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2835{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2836{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2837{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2838{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2839{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2840{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2841{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2842{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2843{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2844{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2845{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2846{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2847{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2848{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2849{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2850{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2851{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2852{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2853{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2854{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2855{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2856{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2857{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2858{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2859{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2860{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2861{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2862{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2863{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2864{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2865{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2866{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2867{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2868{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2869{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2870{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2871{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2872{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2873{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2874{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2875{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2876{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2877{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2878{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2879{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2880{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2881{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2882{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2883{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2884{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2885{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2886{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2887{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2888{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2889{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2890{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2891{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2892{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2893{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2894{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2895{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2896{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2897{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2898{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2899{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2900{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2901{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2902{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2903{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2904{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2905{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2906{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2907{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2908{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2909{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2910{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2911{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2912{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2913{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2914{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2915{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2916{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132
RH		 2917{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2918{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2919{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2920{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2921{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2922{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2923{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 2924{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2925{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 2926{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 2927{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 2928{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2929{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2930{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2931{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2932{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2933{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2934{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2935{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2936{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2937{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2938{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2939{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2940{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2941{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2942{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2943{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2944{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2945{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2946{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 2947{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2948{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 2949{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 2950{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
252b5132
RH		 2951{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2952{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2953{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2954{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2955{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2956{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2957{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2958{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2959{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2960{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2961{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2962{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2963{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2964{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2965{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2966{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2967{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2968{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2969{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2970{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2971{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2972{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
252b5132 2973{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12
AM		 2974{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2975{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
d2f75a6f
GK		 2976{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2977{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2978{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2979{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
d0618d1c
AM		 2980{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2981{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
252b5132
RH		 2982{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2983{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 2984{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2985{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
252b5132 2986
f509565f
GK		 2987{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2988
252b5132
RH		 2989{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2990{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
112290ab 2991{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
252b5132
RH		 2992
2993{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
823bbe9d 2994{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
252b5132
RH		 2995
2996{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2997
2998{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2999
3000{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3001{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3002
3003{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3004{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3005
3006{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3007
3008{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3009
3010{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3011{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3012
3013{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3014
3015{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3016{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3017
3018{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3019{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3020{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3021{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3022{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3023{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3024{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3025{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3026{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3027{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3028{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3029{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3030{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3031{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3032{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3033{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3034{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3035{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3036{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3037{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3038{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3039{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3040{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3041{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3042{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3043{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3044{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3045{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3046{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3047{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3048{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3049{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3050{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3051{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3052{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3053{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3054{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3055{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3056{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3057{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3058{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3059{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3060{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3061{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3062{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3063{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3064{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3065{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3066{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3067{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3068{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3069{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3070{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3071{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3072{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3073{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3074{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3075{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3076{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3077{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3078{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3079{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3080{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3081{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3082{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3083{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3084{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3085{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3086{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3087{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3088{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3089{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3090{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3091{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3092{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3093{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3094{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3095{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3096{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3097{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3098{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3099{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3100{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3101{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3102{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3103{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3104{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3105{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3106{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3107{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3108{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3109{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3110{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3111{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3112{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3113{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3114{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3115{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3116{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3117{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3118{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3119{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3120{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3121{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3122{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3123{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3124{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3125{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3126{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3127{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3128{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3129{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3130{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3131{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3132{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3133{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3134{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3135{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
94efba12 3136{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3137{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
823bbe9d 3138{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
94efba12 3139{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
252b5132 3140{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3141{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3142{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3143{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3144{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3145{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3146{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3147{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3148{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3149{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
252b5132 3150{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3151{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3152{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3153{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3154{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
252b5132 3155{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
94efba12 3156{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3157{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
823bbe9d 3158{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
94efba12 3159{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
d2f75a6f
GK		 3160{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3161{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
d2f75a6f
GK		 3162{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3163{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
d0618d1c
AM		 3164{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3165{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
252b5132
RH		 3166{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3167{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
418c1742
MG		 3168{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3169{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
252b5132
RH		 3170
3171{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3172{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3173
3174{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3175{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3176
3177{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3178{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3179{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3180{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3181{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3182{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3183{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3184{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3185
3186{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3187{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3188
418c1742
MG		 3189{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3190{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3191{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3192{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3193
252b5132
RH		 3194{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3195{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3196{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3197{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3198{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3199{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3200
3201{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3202{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3203{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3204
3205{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3206{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3207
3208{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3209{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3210
3211{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3212{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3213
3214{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3215{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3216
3217{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3218{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3219
3220{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3221{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3222{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3223{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3224{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3225{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3226
3227{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3228{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3229
3230{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3231{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3232
3233{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3234{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3235
3236{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3237{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3238{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3239{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3240
3241{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3242{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3243
520ceea4
BE		 3244{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3245{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
661bd698 3246{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
520ceea4 3247{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
252b5132
RH		 3248
3249{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3250{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3251{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3252{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3253{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3254{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3255{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3256{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3257{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3258{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3259{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3260{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3261{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3262{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3263{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3264{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3265{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3266{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3267{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3268{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3269{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3270{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3271{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3272{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3273{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3274{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3275{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3276{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3277{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3278{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3279{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3280
3281{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3282{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3283{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3284{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3285{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3286{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3287{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3288{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3289{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3290{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3291{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3292{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3293
3294{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3295{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3296
3297{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3298{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3299{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3300{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3301{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3302{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3303{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3304{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3305
3306{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3307{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3308
dde1b132
NC		 3309{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3310{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3311{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3312{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
23976049 3313
98e69875 3314{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
c168870a
AM		 3315{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3316{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
252b5132 3317
fdd12ef3 3318{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } },
252b5132 3319
fdd12ef3 3320{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
252b5132 3321
418c1742 3322{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
823bbe9d 3323{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
418c1742 3324
fdd12ef3 3325{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 3326{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3327
3328{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3329{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3330{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3331{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3332
3333{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3334{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3335{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3336{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3337
3338{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3339{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3340
3341{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3342{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3343
3344{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3345{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3346
418c1742
MG		 3347{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3348
fdd12ef3 3349{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3350
520ceea4
BE		 3351{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3352{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
661bd698 3353{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
520ceea4 3354{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
252b5132
RH		 3355
3356{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3357{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3358{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3359{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3360{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3361{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3362{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3363{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3364
3365{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3366
3367{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3368
3369{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3370{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3371
418c1742
MG		 3372{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3373
3374{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3375
252b5132
RH		 3376{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3377{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3378
418c1742
MG		 3379{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3380{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
252b5132
RH		 3381
3382{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3383{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3384{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3385{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3386{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3387{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3388{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3389{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3390{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3391{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3392{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3393{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3394{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3395{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3396{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3397
3398{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3399{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3400
3401{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3402{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3403
7d5b217e
AM		 3404{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3405{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3406
f509565f
GK		 3407{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3408
252b5132
RH		 3409{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3410
fdd12ef3 3411{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } },
252b5132
RH		 3412
3413{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3414
fdd12ef3 3415{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
252b5132 3416
418c1742
MG		 3417{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3418
fdd12ef3 3419{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3420
252b5132
RH		 3421{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3422{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3423{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3424{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3425
3426{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3427{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3428{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3429{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3430
f509565f
GK		 3431{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3432
2dd46b8b 3433{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
252b5132
RH		 3434
3435{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3436
3437{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3438{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3439{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3440{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3441
fdd12ef3 3442{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742
MG		 3443
3444{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3445
823bbe9d 3446{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
252b5132 3447
23976049
EZ		 3448{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3449
252b5132
RH		 3450{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3451{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3452{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3453{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3454{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3455{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3456{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3457{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3458
3459{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3460{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3461{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3462{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3463{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3464{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3465{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3466{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3467
dde1b132 3468{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3469
98e69875
AM		 3470{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3471{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
252b5132
RH		 3472{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3473
3474{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3475
fdd12ef3 3476{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
252b5132 3477
fdd12ef3 3478{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
252b5132 3479
fdd12ef3 3480{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
252b5132
RH		 3481{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3482
fdd12ef3 3483{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3484
fdd12ef3 3485{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3486
252b5132
RH		 3487{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3488{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3489
3490{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3491{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3492
823bbe9d 3493{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
252b5132 3494
23976049 3495{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
dde1b132 3496{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3497
82674a1f 3498{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
f509565f 3499
252b5132
RH		 3500{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3501
3502{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
fdd12ef3 3503{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132
RH		 3504
3505{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3506{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3507
418c1742
MG		 3508{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3509
252b5132
RH		 3510{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3511{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3512{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3513{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3514{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3515{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3516{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3517{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3518
3519{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3520{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3521{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3522{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3523{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3524{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3525{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3526{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3527
3528{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3529
fdd12ef3 3530{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
252b5132 3531
fdd12ef3 3532{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
252b5132
RH		 3533
3534{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3535{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3536
3537{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3538{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3539
fdd12ef3 3540{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3541
23976049
EZ		 3542{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3543
252b5132
RH		 3544{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3545{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3546{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3547{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3548{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3549{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3550{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3551{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3552
3553{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3554{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3555{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3556{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3557
3558{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3559{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3560{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3561{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3562{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3563{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3564{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3565{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3566
3567{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3568{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3569{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3570{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3571{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3572{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3573{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3574{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3575
dde1b132 3576{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
252b5132
RH		 3577{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3578{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3579
e5d2b64f 3580{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
252b5132
RH		 3581
3582{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3583
3584{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3585{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3586
418c1742
MG		 3587{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3588
3589{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3590
9fa87a06
MG		 3591{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3592
252b5132
RH		 3593{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3594{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3595{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3596{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3597
3598{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3599{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3600{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3601{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3602{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3603{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3604{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3605{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3606
5e8cb021 3607{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
c1a34e60 3608
418c1742
MG		 3609{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3610
252b5132
RH		 3611{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3612{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3613
e5d2b64f 3614{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
252b5132 3615
fdd12ef3 3616{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
252b5132 3617
252b5132
RH		 3618{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3619{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3620
418c1742
MG		 3621{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3622
fdd12ef3 3623{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3624
98acc1c5 3625{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
fdd12ef3 3626{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
252b5132
RH		 3627
3628{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3629
3630{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3631
3632{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3633{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3634
418c1742
MG		 3635{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3636
dde1b132
NC		 3637{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3638{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3639{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3640{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3641{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3642{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3643{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3644{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3645{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3646{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3647{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3648{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3649{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
252b5132
RH		 3650{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3651{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3652{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3653{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3654{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3655{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3656{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3657{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3658{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3659{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3660{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3661{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3662{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3663{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3664{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3665{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3666{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3667{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3668{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3669{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
dde1b132 3670{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
823bbe9d 3671{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
252b5132
RH		 3672
3673{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3674{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3675{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3676{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3677
914749f6 3678{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
23976049 3679
dde1b132
NC		 3680{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3681{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3682{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3683{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3684{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
823bbe9d 3685{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
dde1b132
NC		 3686{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3687{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3688{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3689{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3690{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
dde1b132
NC		 3691{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3692{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3693{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3694{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3695{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3696{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3697{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3698{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3699{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3700{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
dde1b132 3701{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3702{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3703{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3704{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3705{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3706{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3707{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3708{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3709{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3710{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3711{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3712{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3713{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3714{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3715{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3716{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3717{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3718{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3719{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3720{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3721{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3722{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
661bd698 3723{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3724{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
661bd698 3725{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3726{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
661bd698 3727{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
da99ee72 3728{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
dde1b132
NC		 3729{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3730{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3731{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3732{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
da99ee72
AM		 3733{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3734{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3735{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3736{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
dde1b132
NC		 3737{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3738{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3739{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3740{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3741{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3742{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
dde1b132 3743{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3744{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
dde1b132 3745{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3746{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
dde1b132
NC		 3747{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3748{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3749{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
dde1b132 3750{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3751{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
dde1b132 3752{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3753{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
dde1b132 3754{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3755{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
dde1b132 3756{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3757{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
dde1b132 3758{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3759{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
dde1b132 3760{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3761{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
dde1b132 3762{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3763{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
dde1b132 3764{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3765{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
dde1b132 3766{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
823bbe9d 3767{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3768{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3769{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3770{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3771{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3772{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3773{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3774{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3775{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3776{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3777{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3778{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3779{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3780{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3781{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3782{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3783{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3784{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3785{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
914749f6 3786{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
f0b26da6
AH		 3787{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3788{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3789{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
2f3b8700 3790{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
dde1b132
NC		 3791{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3792{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3793{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3794{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3795{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3796{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3797{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3798{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3799{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
dde1b132 3800{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
1f04b05f 3801{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
dde1b132
NC		 3802{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3803{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
23d59c56 3804{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
dde1b132
NC		 3805{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3806{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3807{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3808{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3809{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3810{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3811{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3812{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3813{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3814{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3815{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3816{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3817{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3818{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3819{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3820{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3821{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3822{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3823{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3824{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3825{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3826{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3827{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3828{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3829{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3830{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3831{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3832{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3833{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3834{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
dde1b132 3835{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3836{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3837{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
e0c21649 3838{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
252b5132 3839{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
e0c21649 3840{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
252b5132 3841{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
e0c21649 3842{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
252b5132 3843{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
e0c21649 3844{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
252b5132
RH		 3845{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3846{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
dde1b132 3847{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3848{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3849{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3850{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3851{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3852{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3853{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3854{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
dde1b132
NC		 3855{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3856{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3857{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3858{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3859{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3860{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3861{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3862{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3863{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3864{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3865{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3866{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
252b5132 3867
fdd12ef3 3868{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
252b5132 3869
f5c120c5
MG		 3870{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3871{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3872
fdd12ef3 3873{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
252b5132 3874
fdd12ef3 3875{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 3876
f5c120c5
MG		 3877{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3878{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3879
7d5b217e 3880{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132
RH		 3881
3882{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3883{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3884{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3885{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3886
3887{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3888{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3889{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3890{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3891
3892{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3893
252b5132
RH		 3894{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3895
3896{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3897
418c1742
MG		 3898{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3899
9fa87a06
MG		 3900{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3901
23976049
EZ		 3902{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3903
418c1742
MG		 3904{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3905{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3906
3907{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3908{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3909
dde1b132 3910{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 3911
6ba045b1
AM		 3912{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3913
fdd12ef3 3914{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
252b5132
RH		 3915
3916{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3917
3918{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3919
3920{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3921
3922{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3923
3924{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3925{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3926
3927{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3928{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3929
fdd12ef3 3930{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 3931
252b5132
RH		 3932{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3933
3934{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3935
3936{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3937
418c1742
MG		 3938{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3939
252b5132
RH		 3940{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3941{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3942{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3943{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3944
823bbe9d
AM		 3945{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3946{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3947{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3948{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3949{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3950{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3951{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3952{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3953{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3954{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3955{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3956{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3957{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3958{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3959{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3960{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3961{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3962{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3963{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3964{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3965{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3966{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3967{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3968{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3969{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3970{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3971{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3972{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3973{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3974{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3975{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3976{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3977{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3978{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3979{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
252b5132 3980
418c1742
MG		 3981{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3982{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3983
252b5132
RH		 3984{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3985{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3986{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3987{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3988
418c1742
MG		 3989{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3990{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3991
252b5132
RH		 3992{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3993{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3994{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3995{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3996
dde1b132
NC		 3997{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3998{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3999{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4000{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4001{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4002{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4003{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4004{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4005{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4006{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4007{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4008{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4009{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4010{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4011{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4012{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
dde1b132
NC		 4013{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4014{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4015{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4016{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4017{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
dde1b132 4018{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4019{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
dde1b132 4020{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
823bbe9d
AM		 4021{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4022{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4023{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4024{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4025{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4026{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4027{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4028{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4029{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4030{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4031{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4032{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4033{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4034{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4035{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4036{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4037{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
dde1b132 4038{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
da99ee72 4039{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
823bbe9d
AM		 4040{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4041{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4042{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4043{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4044{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4045{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4046{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4047{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
dde1b132
NC		 4048{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4049{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4050{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4051{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4052{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4053{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
dde1b132 4054{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4055{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
dde1b132 4056{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4057{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
dde1b132
NC		 4058{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4059{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4060{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
dde1b132 4061{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4062{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
dde1b132 4063{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4064{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
dde1b132 4065{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4066{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
dde1b132 4067{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4068{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
dde1b132 4069{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4070{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
dde1b132 4071{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4072{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
dde1b132 4073{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4074{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
dde1b132 4075{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4076{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
dde1b132 4077{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
823bbe9d 4078{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
dde1b132
NC		 4079{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4080{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4081{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4082{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4083{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4084{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4085{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4086{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4087{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4088{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4089{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4090{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4091{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4092{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4093{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4094{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
42a2f80a 4095{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
dde1b132 4096{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
914749f6 4097{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
f0b26da6
AH		 4098{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4099{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4100{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
2f3b8700 4101{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
dde1b132
NC		 4102{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4103{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4104{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4105{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4106{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4107{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4108{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
823bbe9d
AM		 4109{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4110{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4111{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4112{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4113{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4114{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4115{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4116{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4117{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4118{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4119{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4120{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4121{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4122{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4123{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4124{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4125{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4126{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4127{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4128{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4129{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4130{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4131{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4132{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4133{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4134{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4135{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4136{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4137{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4138{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4139{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4140{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4141{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4142{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4143{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4144{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4145{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4146{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4147{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
dde1b132 4148{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
252b5132
RH		 4149
4150{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4151
4152{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4153{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4154
418c1742
MG		 4155{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4156
7d5b217e 4157{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
252b5132 4158
914749f6 4159{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
23976049
EZ		 4160
4161{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4162
252b5132 4163{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
418c1742 4164{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4165{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4166{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
418c1742 4167{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
252b5132
RH		 4168{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4169
4170{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4171{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4172{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4173{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4174
418c1742
MG		 4175{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4176{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4177
252b5132
RH		 4178{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4179{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4180{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4181{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4182
dde1b132 4183{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
23976049 4184
252b5132
RH		 4185{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4186
4187{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4188
418c1742
MG		 4189{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4190
252b5132
RH		 4191{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4192
23976049 4193{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
dde1b132 4194{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
418c1742 4195
252b5132
RH		 4196{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4197
fdd12ef3 4198{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 4199{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4200
fdd12ef3 4201{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
252b5132
RH		 4202{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4203
fdd12ef3 4204{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
252b5132
RH		 4205
4206{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4207{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4208{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4209{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4210
4211{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4212{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4213
4214{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4215{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4216
4217{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4218{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4219
fdd12ef3 4220{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4221
fdd12ef3 4222{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
418c1742 4223
23976049 4224{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
fdd12ef3 4225
252b5132
RH		 4226{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4227
4228{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4229
418c1742
MG		 4230{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4231
252b5132
RH		 4232{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4233
fdd12ef3
AM		 4234{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4235{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
252b5132 4236
661bd698 4237{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
6ba045b1 4238{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
b6be6416 4239{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
6ba045b1 4240{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
252b5132
RH		 4241{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4242
fdd12ef3 4243{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
252b5132 4244
fdd12ef3 4245{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
418c1742 4246
252b5132
RH		 4247{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4248
4249{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4250
4251{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4252
418c1742
MG		 4253{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4254
252b5132
RH		 4255{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4256
fdd12ef3
AM		 4257{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4258{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132 4259
fdd12ef3
AM		 4260{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4261{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
252b5132 4262
fdd12ef3 4263{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
252b5132
RH		 4264
4265{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4266{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4267
4268{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4269{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4270
fdd12ef3 4271{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4272
fdd12ef3
AM		 4273{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4274
252b5132
RH		 4275{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4276
4277{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4278{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4279
418c1742
MG		 4280{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4281
fdd12ef3
AM		 4282{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4283{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
252b5132 4284
fdd12ef3 4285{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
252b5132
RH		 4286
4287{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4288{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4289
4290{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4291{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4292
fdd12ef3
AM		 4293{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4294
823bbe9d 4295{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
e0c21649 4296
252b5132
RH		 4297{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4298
4299{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4300{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4301
418c1742
MG		 4302{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4303
4304{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4305
4306{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
dde1b132 4307{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
418c1742 4308
fdd12ef3 4309{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
252b5132
RH		 4310
4311{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4312{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4313{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4314{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4315
4316{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4317{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4318
fdd12ef3 4319{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4320
fdd12ef3
AM		 4321{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4322{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
418c1742 4323
252b5132
RH		 4324{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4325
f5c120c5 4326{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
eb0fdfed 4327{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
f5c120c5 4328
252b5132
RH		 4329{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4330{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4331{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4332{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4333
6ba045b1
AM		 4334{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4335
b6be6416 4336{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
252b5132
RH		 4337{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4338
9fa87a06 4339{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
823bbe9d 4340{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
7d4a12d2 4341{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
823bbe9d 4342{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
dde1b132
NC		 4343{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4344{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
418c1742 4345
6ba045b1
AM		 4346{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4347
fdd12ef3 4348{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
252b5132
RH		 4349
4350{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4351{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4352
4353{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4354{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4355
4356{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4357{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4358{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4359{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4360
fdd12ef3 4361{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4362
fdd12ef3 4363{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
418c1742 4364
e0c21649
GK		 4365{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4366{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
823bbe9d 4367{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
1c7c333e 4368{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
252b5132
RH		 4369
4370{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4371{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4372
4373{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4374{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4375
418c1742
MG		 4376{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4377
7d5b217e 4378{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132 4379
e0c21649
GK		 4380{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4381{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
fdd12ef3 4382{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
823bbe9d 4383{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
252b5132
RH		 4384
4385{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4386
fdd12ef3 4387{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
252b5132 4388
dde1b132
NC		 4389{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4390{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
252b5132 4391
7d5b217e 4392{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
252b5132 4393
418c1742 4394{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
fdd12ef3 4395{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
418c1742 4396
252b5132
RH		 4397{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4398
f3806e43 4399{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
252b5132
RH		 4400{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4401{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4402
418c1742
MG		 4403{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4404
786e2c0f
C		 4405{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4406{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4407{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4408{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4409{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4410{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4411{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4412{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4413{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4414{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4415{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4416{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4417
fdd12ef3
AM		 4418{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4419{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132
RH		 4420
4421{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
fdd12ef3 4422{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132 4423
fdd12ef3 4424{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4425
4426{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4427
fdd12ef3
AM		 4428{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4429{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132
RH		 4430
4431{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
fdd12ef3 4432{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132 4433
fdd12ef3 4434{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
252b5132
RH		 4435
4436{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4437
fdd12ef3 4438{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4439
4440{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4441
fdd12ef3 4442{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
252b5132
RH		 4443
4444{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4445
fdd12ef3 4446{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
252b5132
RH		 4447
4448{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4449
4450{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
fdd12ef3 4451{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
252b5132 4452
fdd12ef3
AM		 4453{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4454{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
252b5132 4455
fdd12ef3 4456{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
252b5132
RH		 4457
4458{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4459
fdd12ef3 4460{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
252b5132
RH		 4461
4462{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4463
fdd12ef3 4464{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
252b5132
RH		 4465
4466{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4467
fdd12ef3 4468{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
252b5132
RH		 4469
4470{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4471
adadcc0c
AM		 4472{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4473
fdd12ef3 4474{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
252b5132 4475
fdd12ef3 4476{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
252b5132 4477
fdd12ef3 4478{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4479{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4480{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4481{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4482{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4483{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4484{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
418c1742 4485{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
fdd12ef3 4486{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742 4487{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
fdd12ef3 4488{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742 4489{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
fdd12ef3 4490{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
418c1742
MG		 4491{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4492
fdd12ef3 4493{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
802a735e
AM		 4494
4495{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4496
fdd12ef3
AM		 4497{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4498
252b5132
RH		 4499{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4500{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4501
4502{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4503{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4504
4505{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4506{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4507
4508{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4509{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4510
4511{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4512{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4513
4514{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4515{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4516
4517{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4518{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4519
4520{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4521{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4522
4523{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4524{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4525
4526{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4527{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4528
4529{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4530
4531{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4532
fdd12ef3
AM		 4533{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4534{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4535{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
418c1742 4536{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
fdd12ef3 4537{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
418c1742 4538{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
fdd12ef3 4539{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
418c1742 4540{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
fdd12ef3 4541{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
418c1742 4542{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
fdd12ef3 4543{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
418c1742
MG		 4544{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4545
fdd12ef3 4546{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
802a735e
AM		 4547
4548{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4549
fdd12ef3
AM		 4550{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4551
252b5132
RH		 4552{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4553
4554{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4555{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4556
4557{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4558{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4559{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4560{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4561
4562{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4563{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4564{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4565{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4566
4567{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4568{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4569{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4570{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4571
4572{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4573{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4574{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4575{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4576
4577{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4578{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4579{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4580{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4581
4582{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4583{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4584
4585{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4586{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4587
4588{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4589{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4590{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4591{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4592
4593{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4594{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4595
4596{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4597{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4598{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4599{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4600
4601{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4602{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4603{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4604{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4605
4606{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4607{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4608{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4609{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4610
4611{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4612{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4613{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4614{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4615
4616{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4617
4618{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4619{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4620
4621{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4622{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4623
4624{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4625
4626{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4627{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4628
4629{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4630{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4631
4632{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4633{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4634
4635{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4636{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4637
4638{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4639{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4640
4641{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4642{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4643
4644{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4645{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4646
4647{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4648{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4649
4650{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4651{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4652
4653{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4654{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4655
4656};
4657
4658const int powerpc_num_opcodes =
4659 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4660\f
4661/* The macro table. This is only used by the assembler. */
4662
4663/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4664 when x=0; 32-x when x is between 1 and 31; are negative if x is
4665 negative; and are 32 or more otherwise. This is what you want
4666 when, for instance, you are emulating a right shift by a
4667 rotate-left-and-mask, because the underlying instructions support
4668 shifts of size 0 but not shifts of size 32. By comparison, when
4669 extracting x bits from some word you want to use just 32-x, because
4670 the underlying instructions don't support extracting 0 bits but do
4671 support extracting the whole word (32 bits in this case). */
4672
4673const struct powerpc_macro powerpc_macros[] = {
4674{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4675{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4676{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4677{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4678{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4679{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4680{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4681{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4682{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4683{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4684{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4685{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4686{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4687{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4688{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4689{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4690
4691{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4692{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
29ef7e54
AM		 4693{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4694{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
252b5132
RH		 4695{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4696{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4697{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4698{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4699{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4700{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4701{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4702{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4703{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4704{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4705{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4706{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4707{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4708{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4709{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4710{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4711{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4712{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
252b5132
RH		 4713};
4714
4715const int powerpc_num_macros =
4716 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
GDB Binutils - Deliverables
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