projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* elf32-m68k.c (elf_m68k_relocate_section): Allow
[deliverable/binutils-gdb.git] / opcodes / rl78-decode.opc
CommitLineData
99c513f6
DD		 1/* -*- c -*- */
2#include <stdio.h>
3#include <stdlib.h>
4#include <string.h>
5
6#include "config.h"
7#include "ansidecl.h"
8#include "opcode/rl78.h"
9
10static int trace = 0;
11
12typedef struct
13{
14 RL78_Opcode_Decoded * rl78;
15 int (* getbyte)(void *);
16 void * ptr;
17 unsigned char * op;
18} LocalData;
19
20#define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__
21#define OP(n,t,r,a) (rl78->op[n].type = t, \
22 rl78->op[n].reg = r, \
23 rl78->op[n].addend = a )
24#define OPX(n,t,r1,r2,a) \
25 (rl78->op[n].type = t, \
26 rl78->op[n].reg = r1, \
27 rl78->op[n].reg2 = r2, \
28 rl78->op[n].addend = a )
29
30#define W() rl78->size = RL78_Word
31
32#define AU ATTRIBUTE_UNUSED
33#define GETBYTE() (ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr))
34#define B ((unsigned long) GETBYTE())
35
36#define SYNTAX(x) rl78->syntax = x
37
38#define UNSUPPORTED() \
39 rl78->syntax = "*unknown*"
40
41#define RB(x) ((x)+RL78_Reg_X)
42#define RW(x) ((x)+RL78_Reg_AX)
43
44#define Fz rl78->flags = RL78_PSW_Z
45#define Fza rl78->flags = RL78_PSW_Z | RL78_PSW_AC
46#define Fzc rl78->flags = RL78_PSW_Z | RL78_PSW_CY
47#define Fzac rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY
48#define Fa rl78->flags = RL78_PSW_AC
49#define Fc rl78->flags = RL78_PSW_CY
50#define Fac rl78->flags = RL78_PSW_AC | RL78_PSW_CY
51
52#define IMMU(bytes) immediate (bytes, 0, ld)
53#define IMMS(bytes) immediate (bytes, 1, ld)
54
55static int
56immediate (int bytes, int sign_extend, LocalData * ld)
57{
58 unsigned long i = 0;
59
60 switch (bytes)
61 {
62 case 1:
63 i |= B;
64 if (sign_extend && (i & 0x80))
65 i -= 0x100;
66 break;
67 case 2:
68 i |= B;
69 i |= B << 8;
70 if (sign_extend && (i & 0x8000))
71 i -= 0x10000;
72 break;
73 case 3:
74 i |= B;
75 i |= B << 8;
76 i |= B << 16;
77 if (sign_extend && (i & 0x800000))
78 i -= 0x1000000;
79 break;
80 default:
81 fprintf (stderr, "Programmer error: immediate() called with invalid byte count %d\n", bytes);
82 abort();
83 }
84 return i;
85}
86
87#define DC(c) OP (0, RL78_Operand_Immediate, 0, c)
88#define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
89#define DRB(r) OP (0, RL78_Operand_Register, RB(r), 0)
90#define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
91#define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a)
92#define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
93#define DE() rl78->op[0].use_es = 1
94#define DB(b) set_bit (rl78->op, b)
95#define DCY() DR(PSW); DB(0)
96#define DPUSH() OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0);
97
98#define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
99#define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
100#define SRB(r) OP (1, RL78_Operand_Register, RB(r), 0)
101#define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
102#define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a)
103#define SM2(r1,r2,a) OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
104#define SE() rl78->op[1].use_es = 1
105#define SB(b) set_bit (rl78->op+1, b)
106#define SCY() SR(PSW); SB(0)
107#define COND(c) rl78->op[1].condition = RL78_Condition_##c
108#define SPOP() OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0);
109
110static void
111set_bit (RL78_Opcode_Operand *op, int bit)
112{
113 op->bit_number = bit;
114 switch (op->type) {
115 case RL78_Operand_Register:
116 op->type = RL78_Operand_Bit;
117 break;
118 case RL78_Operand_Indirect:
119 op->type = RL78_Operand_BitIndirect;
120 break;
121 default:
122 break;
123 }
124}
125
126static int
127saddr (int x)
128{
129 if (x < 0x20)
130 return 0xfff00 + x;
131 return 0xffe00 + x;
132}
133
134static int
135sfr (int x)
136{
137 return 0xfff00 + x;
138}
139
140#define SADDR saddr (IMMU (1))
141#define SFR sfr (IMMU (1))
142
143int
144rl78_decode_opcode (unsigned long pc AU,
145 RL78_Opcode_Decoded * rl78,
146 int (* getbyte)(void *),
147 void * ptr)
148{
149 LocalData lds, * ld = &lds;
150 unsigned char op_buf[20] = {0};
151 unsigned char *op = op_buf;
152 int op0, op1;
153
154 lds.rl78 = rl78;
155 lds.getbyte = getbyte;
156 lds.ptr = ptr;
157 lds.op = op;
158
159 memset (rl78, 0, sizeof (*rl78));
160
161 start_again:
162
163/* Byte registers, not including A. */
164/** VARY rba 000 010 011 100 101 110 111 */
165/* Word registers, not including AX. */
166/** VARY ra 01 10 11 */
167
168/*----------------------------------------------------------------------*/
169/* ES: prefix */
170
171/** 0001 0001 es: */
172 DE(); SE();
173 op ++;
174 pc ++;
175 goto start_again;
176
177/*----------------------------------------------------------------------*/
178
179/** 0000 1111 add %0, %e1%!1 */
180 ID(add); DR(A); SM(None, IMMU(2)); Fzac;
181
182/** 0000 1101 add %0, %e1%1 */
183 ID(add); DR(A); SM(HL, 0); Fzac;
184
185/** 0110 0001 1000 000 add %0, %e1%1 */
186 ID(add); DR(A); SM2(HL, B, 0); Fzac;
187
188/** 0000 1110 add %0, %e1%1 */
189 ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
190
191/** 0110 0001 1000 0010 add %0, %e1%1 */
192 ID(add); DR(A); SM2(HL, C, 0); Fzac;
193
194/** 0000 1100 add %0, #%1 */
195 ID(add); DR(A); SC(IMMU(1)); Fzac;
196
197/** 0110 0001 0000 1rba add %0, %1 */
198 ID(add); DR(A); SRB(rba); Fzac;
199
200/** 0000 1011 add %0, %1 */
201 ID(add); DR(A); SM(None, SADDR); Fzac;
202
203/** 0110 0001 0000 0reg add %0, %1 */
204 ID(add); DRB(reg); SR(A); Fzac;
205
206/** 0000 1010 add %0, #%1 */
207 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
208
209/*----------------------------------------------------------------------*/
210
211/** 0001 1111 addc %0, %e1%!1 */
212 ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
213
214/** 0001 1101 addc %0, %e1%1 */
215 ID(addc); DR(A); SM(HL, 0); Fzac;
216
217/** 0110 0001 1001 0000 addc %0, %e1%1 */
218 ID(addc); DR(A); SM2(HL, B, 0); Fzac;
219
220/** 0110 0001 1001 0010 addc %0, %e1%1 */
221 ID(addc); DR(A); SM2(HL, C, 0); Fzac;
222
223/** 0001 1110 addc %0, %e1%1 */
224 ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
225
226/** 0001 1100 addc %0, #%1 */
227 ID(addc); DR(A); SC(IMMU(1)); Fzac;
228
229/** 0110 0001 0001 1rba addc %0, %1 */
230 ID(addc); DR(A); SRB(rba); Fzac;
231
232/** 0110 0001 0001 0reg addc %0, %1 */
233 ID(addc); DRB(reg); SR(A); Fzac;
234
235/** 0001 1011 addc %0, %1 */
236 ID(addc); DR(A); SM(None, SADDR); Fzac;
237
238/** 0001 1010 addc %0, #%1 */
239 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
240
241/*----------------------------------------------------------------------*/
242
243/** 0000 0010 addw %0, %e1%!1 */
244 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
245
246/** 0110 0001 0000 1001 addw %0, %e1%1 */
247 ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
248
249/** 0000 0100 addw %0, #%1 */
250 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
251
252/** 0000 0rw1 addw %0, %1 */
253 ID(add); W(); DR(AX); SRW(rw); Fzac;
254
255/** 0000 0110 addw %0, %1 */
256 ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
257
258/** 0001 0000 addw %0, #%1 */
259 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
260
261/*----------------------------------------------------------------------*/
262
263/** 0101 1111 and %0, %e1%!1 */
264 ID(and); DR(A); SM(None, IMMU(2)); Fz;
265
266/** 0101 1101 and %0, %e1%1 */
267 ID(and); DR(A); SM(HL, 0); Fz;
268
269/** 0110 0001 1101 0000 and %0, %e1%1 */
270 ID(and); DR(A); SM2(HL, B, 0); Fz;
271
272/** 0101 1110 and %0, %e1%1 */
273 ID(and); DR(A); SM(HL, IMMU(1)); Fz;
274
275/** 0110 0001 1101 0010 and %0, %e1%1 */
276 ID(and); DR(A); SM2(HL, C, 0); Fz;
277
278/** 0101 1100 and %0, #%1 */
279 ID(and); DR(A); SC(IMMU(1)); Fz;
280
281/** 0110 0001 0101 1rba and %0, %1 */
282 ID(and); DR(A); SRB(rba); Fz;
283
284/** 0110 0001 0101 0reg and %0, %1 */
285 ID(and); DRB(reg); SR(A); Fz;
286
287/** 0101 1011 and %0, %1 */
288 ID(and); DR(A); SM(None, SADDR); Fz;
289
290/** 0101 1010 and %0, #%1 */
291 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
292
293/*----------------------------------------------------------------------*/
294
295/** 0111 0001 1bit 0101 and1 cy, %e1%1 */
296 ID(and); DCY(); SM(HL, 0); SB(bit);
297
298/** 0111 0001 1bit 1101 and1 cy, %1 */
299 ID(and); DCY(); SR(A); SB(bit);
300
301/** 0111 0001 0bit 1101 and1 cy, %s1 */
302 ID(and); DCY(); SM(None, SFR); SB(bit);
303
304/** 0111 0001 0bit 0101 and1 cy, %s1 */
305 ID(and); DCY(); SM(None, SADDR); SB(bit);
306
307/*----------------------------------------------------------------------*/
308
309/* Note that the branch insns need to be listed before the shift
310 ones, as "shift count of zero" means "branch insn" */
311
312/** 1101 1100 bc $%a0 */
313 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
314
315/** 1101 1110 bnc $%a0 */
316 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
317
318/** 0110 0001 1100 0011 bh $%a0 */
319 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
320
321/** 0110 0001 1101 0011 bnh $%a0 */
322 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
323
324/** 1101 1101 bz $%a0 */
325 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
326
327/** 1101 1111 bnz $%a0 */
328 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
329
330/*----------------------------------------------------------------------*/
331
332/** 0011 0001 1bit 0101 bf %e1%1, $%a0 */
333 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
334
335/** 0011 0001 0bit 0101 bf %1, $%a0 */
336 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
337
338/** 0011 0001 1bit 0100 bf %s1, $%a0 */
339 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
340
341/** 0011 0001 0bit 0100 bf %s1, $%a0 */
342 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
343
344/*----------------------------------------------------------------------*/
345
346/** 1110 1100 br !%!a0 */
347 ID(branch); DC(IMMU(3));
348
349/** 1110 1101 br %!a0 */
350 ID(branch); DC(IMMU(2));
351
352/** 1110 1110 br $%!a0 */
353 ID(branch); DC(pc+IMMS(2)+3);
354
355/** 1110 1111 br $%a0 */
356 ID(branch); DC(pc+IMMS(1)+2);
357
358/** 0110 0001 1100 1011 br ax */
359 ID(branch); DR(AX);
360
361/*----------------------------------------------------------------------*/
362
363/** 1111 1111 brk1 */
364 ID(break);
365
366/** 0110 0001 1100 1100 brk */
367 ID(break);
368
369/*----------------------------------------------------------------------*/
370
371/** 0011 0001 1bit 0011 bt %e1%1, $%a0 */
372 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
373
374/** 0011 0001 0bit 0011 bt %1, $%a0 */
375 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
376
377/** 0011 0001 1bit 0010 bt %s1, $%a0 */
378 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
379
380/** 0011 0001 0bit 0010 bt %s1, $%a0 */
381 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
382
383/*----------------------------------------------------------------------*/
384
385/** 0011 0001 1bit 0001 btclr %e1%1, $%a0 */
386 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
387
388/** 0011 0001 0bit 0001 btclr %1, $%a0 */
389 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
390
391/** 0011 0001 1bit 0000 btclr %s1, $%a0 */
392 ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
393
394/** 0011 0001 0bit 0000 btclr %s1, $%a0 */
395 ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
396
397/*----------------------------------------------------------------------*/
398
399/** 1111 1100 call !%!a0 */
400 ID(call); DC(IMMU(3));
401
402/** 1111 1101 call %!a0 */
403 ID(call); DC(IMMU(2));
404
405/** 1111 1110 call $%!a0 */
406 ID(call); DC(pc+IMMS(2)+3);
407
408/** 0110 0001 11rg 1010 call %0 */
409 ID(call); DRW(rg);
410
411/** 0110 0001 1nnn 01mm callt [%x0] */
412 ID(call); DM(None, 0x80 + mm*16 + nnn*2);
413
414/*----------------------------------------------------------------------*/
415
416/** 0111 0001 0bit 1000 clr1 %e0%!0 */
417 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
418
419/** 0111 0001 1bit 0011 clr1 %e0%0 */
420 ID(mov); DM(HL, 0); DB(bit); SC(0);
421
422/** 0111 0001 1bit 1011 clr1 %0 */
423 ID(mov); DR(A); DB(bit); SC(0);
424
425/** 0111 0001 1000 1000 clr1 cy */
426 ID(mov); DCY(); SC(0);
427
428/** 0111 0001 0bit 1011 clr1 %s0 */
429 op0 = SFR;
430 ID(mov); DM(None, op0); DB(bit); SC(0);
431 if (op0 == RL78_SFR_PSW && bit == 7)
432 rl78->syntax = "di";
433
434/** 0111 0001 0bit 0011 clr1 %0 */
435 ID(mov); DM(None, SADDR); DB(bit); SC(0);
436
437/*----------------------------------------------------------------------*/
438
439/** 1111 0101 clrb %e0%!0 */
440 ID(mov); DM(None, IMMU(2)); SC(0);
441
442/** 1111 00rg clrb %0 */
443 ID(mov); DRB(rg); SC(0);
444
445/** 1111 0100 clrb %0 */
446 ID(mov); DM(None, SADDR); SC(0);
447
448/*----------------------------------------------------------------------*/
449
450/** 1111 0110 clrw %0 */
451 ID(mov); DR(AX); SC(0);
452
453/** 1111 0111 clrw %0 */
454 ID(mov); DR(BC); SC(0);
455
456/*----------------------------------------------------------------------*/
457
458/** 0100 0000 cmp %e0%!0, #%1 */
459 ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
460
461/** 0100 1010 cmp %0, #%1 */
462 ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
463
464/** 0100 1111 cmp %0, %e1%!1 */
465 ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
466
467/** 0100 1101 cmp %0, %e1%1 */
468 ID(cmp); DR(A); SM(HL, 0); Fzac;
469
470/** 0110 0001 1100 0000 cmp %0, %e1%1 */
471 ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
472
473/** 0110 0001 1100 0010 cmp %0, %e1%1 */
474 ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
475
476/** 0100 1110 cmp %0, %e1%1 */
477 ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
478
479/** 0100 1100 cmp %0, #%1 */
480 ID(cmp); DR(A); SC(IMMU(1)); Fzac;
481
482/** 0110 0001 0100 1rba cmp %0, %1 */
483 ID(cmp); DR(A); SRB(rba); Fzac;
484
485/** 0110 0001 0100 0reg cmp %0, %1 */
486 ID(cmp); DRB(reg); SR(A); Fzac;
487
488/** 0100 1011 cmp %0, %1 */
489 ID(cmp); DR(A); SM(None, SADDR); Fzac;
490
491/*----------------------------------------------------------------------*/
492
493/** 1101 0101 cmp0 %e0%!0 */
494 ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
495
496/** 1101 00rg cmp0 %0 */
497 ID(cmp); DRB(rg); SC(0); Fzac;
498
499/** 1101 0100 cmp0 %0 */
500 ID(cmp); DM(None, SADDR); SC(0); Fzac;
501
502/*----------------------------------------------------------------------*/
503
504/** 0110 0001 1101 1110 cmps %0, %e1%1 */
505 ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
506
507/*----------------------------------------------------------------------*/
508
509/** 0100 0010 cmpw %0, %e1%!1 */
510 ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
511
512/** 0110 0001 0100 1001 cmpw %0, %e1%1 */
513 ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
514
515/** 0100 0100 cmpw %0, #%1 */
516 ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac;
517
518/** 0100 0ra1 cmpw %0, %1 */
519 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
520
521/** 0100 0110 cmpw %0, %1 */
522 ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac;
523
524/*----------------------------------------------------------------------*/
525
526/** 1011 0000 dec %e0%!0 */
527 ID(sub); DM(None, IMMU(2)); SC(1); Fza;
528
529/** 0110 0001 0110 1001 dec %e0%0 */
530 ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
531
532/** 1001 0reg dec %0 */
533 ID(sub); DRB(reg); SC(1); Fza;
534
535/** 1011 0100 dec %0 */
536 ID(sub); DM(None, SADDR); SC(1); Fza;
537
538/*----------------------------------------------------------------------*/
539
540/** 1011 0010 decw %e0%!0 */
541 ID(sub); W(); DM(None, IMMU(2)); SC(1);
542
543/** 0110 0001 1000 1001 decw %e0%0 */
544 ID(sub); W(); DM(HL, IMMU(1)); SC(1);
545
546/** 1011 0rg1 decw %0 */
547 ID(sub); W(); DRW(rg); SC(1);
548
549/** 1011 0110 decw %0 */
550 ID(sub); W(); DM(None, SADDR); SC(1);
551
552/*----------------------------------------------------------------------*/
553
554/** 0110 0001 1110 1101 halt */
555 ID(halt);
556
557/*----------------------------------------------------------------------*/
558
559/** 1010 0000 inc %e0%!0 */
560 ID(add); DM(None, IMMU(2)); SC(1); Fza;
561
562/** 0110 0001 0101 1001 inc %e0%0 */
563 ID(add); DM(HL, IMMU(1)); SC(1); Fza;
564
565/** 1000 0reg inc %0 */
566 ID(add); DRB(reg); SC(1); Fza;
567
568/** 1010 0100 inc %0 */
569 ID(add); DM(None, SADDR); SC(1); Fza;
570
571/*----------------------------------------------------------------------*/
572
573/** 1010 0010 incw %e0%!0 */
574 ID(add); W(); DM(None, IMMU(2)); SC(1);
575
576/** 0110 0001 0111 1001 incw %e0%0 */
577 ID(add); W(); DM(HL, IMMU(1)); SC(1);
578
579/** 1010 0rg1 incw %0 */
580 ID(add); W(); DRW(rg); SC(1);
581
582/** 1010 0110 incw %0 */
583 ID(add); W(); DM(None, SADDR); SC(1);
584
585/*----------------------------------------------------------------------*/
586
587/** 1100 1111 mov %e0%!0, #%1 */
588 ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
589
590/** 1001 1111 mov %e0%!0, %1 */
591 ID(mov); DM(None, IMMU(2)); SR(A);
592
593/** 1001 1001 mov %e0%0,%1 */
594 ID(mov); DM(DE, 0); SR(A);
595
596/** 1100 1010 mov %e0%0, #%1 */
597 ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
598
599/** 1001 1010 mov %e0%0, %1 */
600 ID(mov); DM(DE, IMMU(1)); SR(A);
601
602/** 1001 1011 mov %e0%0,%1 */
603 ID(mov); DM(HL, 0); SR(A);
604
605/** 0110 0001 1101 1001 mov %e0%0, %1 */
606 ID(mov); DM2(HL, B, 0); SR(A);
607
608/** 1100 1100 mov %e0%0, #%1 */
609 ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
610
611/** 1001 1100 mov %e0%0, %1 */
612 ID(mov); DM(HL, IMMU(1)); SR(A);
613
614/** 0110 0001 1111 1001 mov %e0%0, %1 */
615 ID(mov); DM2(HL, C, 0); SR(A);
616
617/** 1100 1000 mov %0, #%1 */
618 ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
619
620/** 1001 1000 mov %0, %1 */
621 ID(mov); DM(SP, IMMU(1)); SR(A);
622
623/** 1000 1111 mov %0, %e1%!1 */
624 ID(mov); DR(A); SM(None, IMMU(2));
625
626/** 1000 1001 mov %0, %e1%1 */
627 ID(mov); DR(A); SM(DE, 0);
628
629/** 1000 1010 mov %0, %e1%1 */
630 ID(mov); DR(A); SM(DE, IMMU(1));
631
632/** 1000 1011 mov %0, %e1%1 */
633 ID(mov); DR(A); SM(HL, 0);
634
635/** 1000 1100 mov %0, %e1%1 */
636 ID(mov); DR(A); SM(HL, IMMU(1));
637
638/** 0110 0001 1100 1001 mov %0, %e1%1 */
639 ID(mov); DR(A); SM2(HL, B, 0);
640
641/** 0110 0001 1110 1001 mov %0, %e1%1 */
642 ID(mov); DR(A); SM2(HL, C, 0);
643
644/** 1000 1000 mov %0, %e1%1 */
645 ID(mov); DR(A); SM(SP, IMMU(1));
646
647/** 0101 0reg mov %0, #%1 */
648 ID(mov); DRB(reg); SC(IMMU(1));
649
650/** 0110 0rba mov %0, %1 */
651 ID(mov); DR(A); SRB(rba);
652
653/** 1000 1110 1111 1101 mov %0, %1 */
654 ID(mov); DR(A); SR(ES);
655
656/** 0000 1001 mov %0, %e1%1 */
657 ID(mov); DR(A); SM(B, IMMU(2));
658
659/** 0100 1001 mov %0, %e1%1 */
660 ID(mov); DR(A); SM(BC, IMMU(2));
661
662/** 0010 1001 mov %0, %e1%1 */
663 ID(mov); DR(A); SM(C, IMMU(2));
664
665/** 1000 1110 mov %0, %s1 */
666 ID(mov); DR(A); SM(None, SFR);
667
668/** 1000 1101 mov %0, %1 */
669 ID(mov); DR(A); SM(None, SADDR);
670
671/** 1110 1001 mov %0, %e1%!1 */
672 ID(mov); DR(B); SM(None, IMMU(2));
673
674/** 0111 0rba mov %0, %1 */
675 ID(mov); DRB(rba); SR(A);
676
677/** 1110 1000 mov %0, %1 */
678 ID(mov); DR(B); SM(None, SADDR);
679
680/** 1111 1001 mov %0, %e1%!1 */
681 ID(mov); DR(C); SM(None, IMMU(2));
682
683/** 1111 1000 mov %0, %1 */
684 ID(mov); DR(C); SM(None, SADDR);
685
686/** 1101 1001 mov %0, %e1%!1 */
687 ID(mov); DR(X); SM(None, IMMU(2));
688
689/** 1101 1000 mov %0, %1 */
690 ID(mov); DR(X); SM(None, SADDR);
691
692/** 1001 1110 1111 1100 mov %0, %1 */
693 ID(mov); DR(CS); SR(A);
694
695/** 0100 0001 mov %0, #%1 */
696 ID(mov); DR(ES); SC(IMMU(1));
697
698/** 1001 1110 1111 1101 mov %0, %1 */
699 ID(mov); DR(ES); SR(A);
700
701/** 0110 0001 1011 1000 mov %0, %1 */
702 ID(mov); DR(ES); SM(None, SADDR);
703
704/** 0001 1001 mov %e0%0, #%1 */
705 ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
706
707/** 0001 1000 mov %e0%0, %1 */
708 ID(mov); DM(B, IMMU(2)); SR(A);
709
710/** 0011 1001 mov %e0%0, #%1 */
711 ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
712
713/** 0100 1000 mov %e0%0, %1 */
714 ID(mov); DM(BC, IMMU(2)); SR(A);
715
716/** 0011 1000 mov %e0%0, #%1 */
717 ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
718
719/** 0010 1000 mov %e0%0, %1 */
720 ID(mov); DM(C, IMMU(2)); SR(A);
721
722/** 1100 1101 mov %0, #%1 */
723 ID(mov); DM(None, SADDR); SC(IMMU(1));
724
725/** 1001 1101 mov %0, %1 */
726 ID(mov); DM(None, SADDR); SR(A);
727
728/** 1100 1110 mov %s0, #%1 */
729 op0 = SFR;
730 op1 = IMMU(1);
731 ID(mov); DM(None, op0); SC(op1);
732 if (op0 == 0xffffb)
733 switch (op1)
734 {
735 case 0x01:
736 rl78->syntax = "mulhu"; ID(mulhu);
737 break;
738 case 0x02:
739 rl78->syntax = "mulh"; ID(mulh);
740 break;
741 case 0x03:
742 rl78->syntax = "divhu"; ID(divhu);
743 break;
744 case 0x04:
745 rl78->syntax = "divwu"; ID(divwu);
746 break;
747 case 0x05:
748 rl78->syntax = "machu"; ID(machu);
749 break;
750 case 0x06:
751 rl78->syntax = "mach"; ID(mach);
752 break;
753 }
754
755/** 1001 1110 mov %0, %1 */
756 ID(mov); DM(None, SFR); SR(A);
757
758/*----------------------------------------------------------------------*/
759
760/** 0111 0001 1bit 0001 mov1 %e0%0, cy */
761 ID(mov); DM(HL, 0); DB(bit); SCY();
762
763/** 0111 0001 1bit 1001 mov1 %e0%0, cy */
764 ID(mov); DR(A); DB(bit); SCY();
765
766/** 0111 0001 1bit 0100 mov1 cy, %e1%1 */
767 ID(mov); DCY(); SM(HL, 0); SB(bit);
768
769/** 0111 0001 1bit 1100 mov1 cy, %e1%1 */
770 ID(mov); DCY(); SR(A); SB(bit);
771
772/** 0111 0001 0bit 0100 mov1 cy, %1 */
773 ID(mov); DCY(); SM(None, SADDR); SB(bit);
774
775/** 0111 0001 0bit 1100 mov1 cy, %s1 */
776 ID(mov); DCY(); SM(None, SFR); SB(bit);
777
778/** 0111 0001 0bit 0001 mov1 %0, cy */
779 ID(mov); DM(None, SADDR); DB(bit); SCY();
780
781/** 0111 0001 0bit 1001 mov1 %s0, cy */
782 ID(mov); DM(None, SFR); DB(bit); SCY();
783
784/*----------------------------------------------------------------------*/
785
786/** 0110 0001 1100 1110 movs %e0%0, %1 */
787 ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
788
789/*----------------------------------------------------------------------*/
790
791/** 1011 1111 movw %e0%!0, %1 */
792 ID(mov); W(); DM(None, IMMU(2)); SR(AX);
793
794/** 1011 1001 movw %e0%0, %1 */
795 ID(mov); W(); DM(DE, 0); SR(AX);
796
797/** 1011 1010 movw %e0%0, %1 */
798 ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
799
800/** 1011 1011 movw %e0%0, %1 */
801 ID(mov); W(); DM(HL, 0); SR(AX);
802
803/** 1011 1100 movw %e0%0, %1 */
804 ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
805
806/** 1011 1000 movw %0, %1 */
807 ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
808
809/** 1010 1111 movw %0, %e1%!1 */
810 ID(mov); W(); DR(AX); SM(None, IMMU(2));
811
812
813/** 1010 1001 movw %0, %e1%1 */
814 ID(mov); W(); DR(AX); SM(DE, 0);
815
816/** 1010 1010 movw %0, %e1%1 */
817 ID(mov); W(); DR(AX); SM(DE, IMMU(1));
818
819/** 1010 1011 movw %0, %e1%1 */
820 ID(mov); W(); DR(AX); SM(HL, 0);
821
822/** 1010 1100 movw %0, %e1%1 */
823 ID(mov); W(); DR(AX); SM(HL, IMMU(1));
824
825/** 1010 1000 movw %0, %1 */
826 ID(mov); W(); DR(AX); SM(SP, IMMU(1));
827
828/** 0011 0rg0 movw %0, #%1 */
829 ID(mov); W(); DRW(rg); SC(IMMU(2));
830
831/** 0001 0ra1 movw %0, %1 */
832 ID(mov); W(); DR(AX); SRW(ra);
833
834/** 0001 0ra0 movw %0, %1 */
835 ID(mov); W(); DRW(ra); SR(AX);
836
837/** 0101 1001 movw %0, %e1%1 */
838 ID(mov); W(); DR(AX); SM(B, IMMU(2));
839
840/** 0110 1001 movw %0, %e1%1 */
841 ID(mov); W(); DR(AX); SM(C, IMMU(2));
842
843/** 0111 1001 movw %0, %e1%1 */
844 ID(mov); W(); DR(AX); SM(BC, IMMU(2));
845
846/** 0101 1000 movw %e0%0, %1 */
847 ID(mov); W(); DM(B, IMMU(2)); SR(AX);
848
849/** 0110 1000 movw %e0%0, %1 */
850 ID(mov); W(); DM(C, IMMU(2)); SR(AX);
851
852/** 0111 1000 movw %e0%0, %1 */
853 ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
854
855/** 1010 1101 movw %0, %1 */
856 ID(mov); W(); DR(AX); SM(None, SADDR);
857
858/** 1010 1110 movw %0, %s1 */
859 ID(mov); W(); DR(AX); SM(None, SFR);
860
861/** 11ra 1011 movw %0, %e1%!1 */
862 ID(mov); W(); DRW(ra); SM(None, IMMU(2));
863
864/** 11ra 1010 movw %0, %1 */
865 ID(mov); W(); DRW(ra); SM(None, SADDR);
866
867/** 1100 1001 movw %0, #%1 */
868 ID(mov); W(); DM(None, SADDR); SC(IMMU(2));
869
870/** 1011 1101 movw %0, %1 */
871 ID(mov); W(); DM(None, SADDR); SR(AX);
872
873/** 1100 1011 movw %0, #%1 */
874 ID(mov); W(); DM(None, SFR); SC(IMMU(2));
875
876/** 1011 1110 movw %0, %1 */
877 ID(mov); W(); DM(None, SFR); SR(AX);
878
879/*----------------------------------------------------------------------*/
880
881/** 1101 0110 mulu x */
882 ID(mulu);
883
884/*----------------------------------------------------------------------*/
885
886/** 0000 0000 nop */
887 ID(nop);
888
889/*----------------------------------------------------------------------*/
890
21abe33a
DD		 891/** 0111 0001 1100 0000 not1 cy */
892 ID(xor); DCY(); SC(1);
893
894/*----------------------------------------------------------------------*/
895
99c513f6
DD		 896/** 1110 0101 oneb %e0%!0 */
897 ID(mov); DM(None, IMMU(2)); SC(1);
898
899/** 1110 00rg oneb %0 */
900 ID(mov); DRB(rg); SC(1);
901
902/** 1110 0100 oneb %0 */
903 ID(mov); DM(None, SADDR); SC(1);
904
905/*----------------------------------------------------------------------*/
906
907/** 1110 0110 onew %0 */
908 ID(mov); DR(AX); SC(1);
909
910/** 1110 0111 onew %0 */
911 ID(mov); DR(BC); SC(1);
912
913/*----------------------------------------------------------------------*/
914
915/** 0110 1111 or %0, %e1%!1 */
916 ID(or); DR(A); SM(None, IMMU(2)); Fz;
917
918/** 0110 1101 or %0, %e1%1 */
919 ID(or); DR(A); SM(HL, 0); Fz;
920
921/** 0110 0001 1110 0000 or %0, %e1%1 */
922 ID(or); DR(A); SM2(HL, B, 0); Fz;
923
924/** 0110 1110 or %0, %e1%1 */
925 ID(or); DR(A); SM(HL, IMMU(1)); Fz;
926
927/** 0110 0001 1110 0010 or %0, %e1%1 */
928 ID(or); DR(A); SM2(HL, C, 0); Fz;
929
930/** 0110 1100 or %0, #%1 */
931 ID(or); DR(A); SC(IMMU(1)); Fz;
932
933/** 0110 0001 0110 1rba or %0, %1 */
934 ID(or); DR(A); SRB(rba); Fz;
935
936/** 0110 0001 0110 0reg or %0, %1 */
937 ID(or); DRB(reg); SR(A); Fz;
938
939/** 0110 1011 or %0, %1 */
940 ID(or); DR(A); SM(None, SADDR); Fz;
941
942/** 0110 1010 or %0, #%1 */
943 ID(or); DM(None, SADDR); SC(IMMU(1)); Fz;
944
945/*----------------------------------------------------------------------*/
946
947/** 0111 0001 1bit 0110 or1 cy, %e1%1 */
948 ID(or); DCY(); SM(HL, 0); SB(bit);
949
950/** 0111 0001 1bit 1110 or1 cy, %1 */
951 ID(or); DCY(); SR(A); SB(bit);
952
953/** 0111 0001 0bit 1110 or1 cy, %s1 */
954 ID(or); DCY(); SM(None, SFR); SB(bit);
955
956/** 0111 0001 0bit 0110 or1 cy, %s1 */
957 ID(or); DCY(); SM(None, SADDR); SB(bit);
958
959/*----------------------------------------------------------------------*/
960
961/** 1100 0rg0 pop %0 */
962 ID(mov); W(); DRW(rg); SPOP();
963
964/** 0110 0001 1100 1101 pop %s0 */
965 ID(mov); W(); DR(PSW); SPOP();
966
967/*----------------------------------------------------------------------*/
968
969/** 1100 0rg1 push %1 */
970 ID(mov); W(); DPUSH(); SRW(rg);
971
972/** 0110 0001 1101 1101 push %s1 */
973 ID(mov); W(); DPUSH(); SR(PSW);
974
975/*----------------------------------------------------------------------*/
976
977/** 1101 0111 ret */
978 ID(ret);
979
980/** 0110 0001 1111 1100 reti */
981 ID(reti);
982
983/** 0110 0001 1110 1100 retb */
984 ID(reti);
985
986/*----------------------------------------------------------------------*/
987
988/** 0110 0001 1110 1011 rol %0, %1 */
989 ID(rol); DR(A); SC(1);
990
991/** 0110 0001 1101 1100 rolc %0, %1 */
992 ID(rolc); DR(A); SC(1);
993
994/** 0110 0001 111r 1110 rolwc %0, %1 */
995 ID(rolc); W(); DRW(r); SC(1);
996
997/** 0110 0001 1101 1011 ror %0, %1 */
998 ID(ror); DR(A); SC(1);
999
1000/** 0110 0001 1111 1011 rorc %0, %1 */
1001 ID(rorc); DR(A); SC(1);
1002
1003/*----------------------------------------------------------------------*/
1004
1005/* Note that the branch insns need to be listed before the shift
1006 ones, as "shift count of zero" means "branch insn" */
1007
1008/** 0011 0001 0cnt 1011 sar %0, %1 */
1009 ID(sar); DR(A); SC(cnt);
1010
1011/** 0011 0001 wcnt 1111 sarw %0, %1 */
1012 ID(sar); W(); DR(AX); SC(wcnt);
1013
1014/*----------------------------------------------------------------------*/
1015
1016/** 0110 0001 11rb 1111 sel rb%1 */
1017 ID(sel); SC(rb);
1018
1019/*----------------------------------------------------------------------*/
1020
1021/** 0111 0001 0bit 0000 set1 %e0%!0 */
1022 ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
1023
1024/** 0111 0001 1bit 0010 set1 %e0%0 */
1025 ID(mov); DM(HL, 0); DB(bit); SC(1);
1026
1027/** 0111 0001 1bit 1010 set1 %0 */
1028 ID(mov); DR(A); DB(bit); SC(1);
1029
1030/** 0111 0001 1000 0000 set1 cy */
1031 ID(mov); DCY(); SC(1);
1032
1033/** 0111 0001 0bit 1010 set1 %s0 */
1034 op0 = SFR;
1035 ID(mov); DM(None, op0); DB(bit); SC(1);
1036 if (op0 == RL78_SFR_PSW && bit == 7)
1037 rl78->syntax = "ei";
1038
1039/** 0111 0001 0bit 0010 set1 %0 */
1040 ID(mov); DM(None, SADDR); DB(bit); SC(1);
1041
1042/*----------------------------------------------------------------------*/
1043
1044/** 0011 0001 0cnt 1001 shl %0, %1 */
1045 ID(shl); DR(A); SC(cnt);
1046
1047/** 0011 0001 0cnt 1000 shl %0, %1 */
1048 ID(shl); DR(B); SC(cnt);
1049
1050/** 0011 0001 0cnt 0111 shl %0, %1 */
1051 ID(shl); DR(C); SC(cnt);
1052
1053/** 0011 0001 wcnt 1101 shlw %0, %1 */
1054 ID(shl); W(); DR(AX); SC(wcnt);
1055
1056/** 0011 0001 wcnt 1100 shlw %0, %1 */
1057 ID(shl); W(); DR(BC); SC(wcnt);
1058
1059/*----------------------------------------------------------------------*/
1060
1061/** 0011 0001 0cnt 1010 shr %0, %1 */
1062 ID(shr); DR(A); SC(cnt);
1063
1064/** 0011 0001 wcnt 1110 shrw %0, %1 */
1065 ID(shr); W(); DR(AX); SC(wcnt);
1066
1067/*----------------------------------------------------------------------*/
1068
1069/** 0110 0001 1100 1000 sk%c1 */
1070 ID(skip); COND(C);
1071
1072/** 0110 0001 1110 0011 sk%c1 */
1073 ID(skip); COND(H);
1074
1075/** 0110 0001 1101 1000 sk%c1 */
1076 ID(skip); COND(NC);
1077
1078/** 0110 0001 1111 0011 sk%c1 */
1079 ID(skip); COND(NH);
1080
1081/** 0110 0001 1111 1000 sk%c1 */
1082 ID(skip); COND(NZ);
1083
1084/** 0110 0001 1110 1000 sk%c1 */
1085 ID(skip); COND(Z);
1086
1087/*----------------------------------------------------------------------*/
1088
1089/** 0110 0001 1111 1101 stop */
1090 ID(stop);
1091
1092/*----------------------------------------------------------------------*/
1093
1094/** 0010 1111 sub %0, %e1%!1 */
1095 ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
1096
1097/** 0010 1101 sub %0, %e1%1 */
1098 ID(sub); DR(A); SM(HL, 0); Fzac;
1099
1100/** 0110 0001 1010 000 sub %0, %e1%1 */
1101 ID(sub); DR(A); SM2(HL, B, 0); Fzac;
1102
1103/** 0010 1110 sub %0, %e1%1 */
1104 ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
1105
1106/** 0110 0001 1010 0010 sub %0, %e1%1 */
1107 ID(sub); DR(A); SM2(HL, C, 0); Fzac;
1108
1109/** 0010 1100 sub %0, #%1 */
1110 ID(sub); DR(A); SC(IMMU(1)); Fzac;
1111
1112/** 0110 0001 0010 1rba sub %0, %1 */
1113 ID(sub); DR(A); SRB(rba); Fzac;
1114
1115/** 0010 1011 sub %0, %1 */
1116 ID(sub); DR(A); SM(None, SADDR); Fzac;
1117
1118/** 0110 0001 0010 0reg sub %0, %1 */
1119 ID(sub); DRB(reg); SR(A); Fzac;
1120
1121/** 0010 1010 sub %0, #%1 */
1122 ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac;
1123
1124/*----------------------------------------------------------------------*/
1125
1126/** 0011 1111 subc %0, %e1%!1 */
1127 ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
1128
1129/** 0011 1101 subc %0, %e1%1 */
1130 ID(subc); DR(A); SM(HL, 0); Fzac;
1131
1132/** 0110 0001 1011 0000 subc %0, %e1%1 */
1133 ID(subc); DR(A); SM2(HL, B, 0); Fzac;
1134
1135/** 0110 0001 1011 0010 subc %0, %e1%1 */
1136 ID(subc); DR(A); SM2(HL, C, 0); Fzac;
1137
1138/** 0011 1110 subc %0, %e1%1 */
1139 ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
1140
1141/** 0011 1100 subc %0, #%1 */
1142 ID(subc); DR(A); SC(IMMU(1)); Fzac;
1143
1144/** 0110 0001 0011 1rba subc %0, %1 */
1145 ID(subc); DR(A); SRB(rba); Fzac;
1146
1147/** 0110 0001 0011 0reg subc %0, %1 */
1148 ID(subc); DRB(reg); SR(A); Fzac;
1149
1150/** 0011 1011 subc %0, %1 */
1151 ID(subc); DR(A); SM(None, SADDR); Fzac;
1152
1153/** 0011 1010 subc %0, #%1 */
1154 ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac;
1155
1156/*----------------------------------------------------------------------*/
1157
1158/** 0010 0010 subw %0, %e1%!1 */
1159 ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
1160
1161/** 0110 0001 0010 1001 subw %0, %e1%1 */
1162 ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
1163
1164/** 0010 0100 subw %0, #%1 */
1165 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac;
1166
1167/** 0010 0rw1 subw %0, %1 */
1168 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1169
1170/** 0010 0110 subw %0, %1 */
1171 ID(sub); W(); DR(AX); SM(None, SADDR); Fzac;
1172
1173/** 0010 0000 subw %0, #%1 */
1174 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
1175
1176/*----------------------------------------------------------------------*/
1177
1178/** 0110 0001 1010 1010 xch %0, %e1%!1 */
1179 ID(xch); DR(A); SM(None, IMMU(2));
1180
1181/** 0110 0001 1010 1110 xch %0, %e1%1 */
1182 ID(xch); DR(A); SM(DE, 0);
1183
1184/** 0110 0001 1010 1111 xch %0, %e1%1 */
1185 ID(xch); DR(A); SM(DE, IMMU(1));
1186
1187/** 0110 0001 1010 1100 xch %0, %e1%1 */
1188 ID(xch); DR(A); SM(HL, 0);
1189
1190/** 0110 0001 1011 1001 xch %0, %e1%1 */
1191 ID(xch); DR(A); SM2(HL, B, 0);
1192
1193/** 0110 0001 1010 1101 xch %0, %e1%1 */
1194 ID(xch); DR(A); SM(HL, IMMU(1));
1195
1196/** 0110 0001 1010 1001 xch %0, %e1%1 */
1197 ID(xch); DR(A); SM2(HL, C, 0);
1198
1199/** 0110 0001 1000 1reg xch %0, %1 */
1200 /* Note: DECW uses reg == X, so this must follow DECW */
1201 ID(xch); DR(A); SRB(reg);
1202
1203/** 0110 0001 1010 1000 xch %0, %1 */
1204 ID(xch); DR(A); SM(None, SADDR);
1205
1206/** 0110 0001 1010 1011 xch %0, %1 */
1207 ID(xch); DR(A); SM(None, SFR);
1208
1209/** 0000 1000 xch a, x */
1210 ID(xch); DR(A); SR(X);
1211
1212/*----------------------------------------------------------------------*/
1213
1214/** 0011 0ra1 xchw %0, %1 */
1215 ID(xch); W(); DR(AX); SRW(ra);
1216
1217/*----------------------------------------------------------------------*/
1218
1219/** 0111 1111 xor %0, %e1%!1 */
1220 ID(xor); DR(A); SM(None, IMMU(2)); Fz;
1221
1222/** 0111 1101 xor %0, %e1%1 */
1223 ID(xor); DR(A); SM(HL, 0); Fz;
1224
1225/** 0110 0001 1111 0000 xor %0, %e1%1 */
1226 ID(xor); DR(A); SM2(HL, B, 0); Fz;
1227
1228/** 0111 1110 xor %0, %e1%1 */
1229 ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
1230
1231/** 0110 0001 1111 0010 xor %0, %e1%1 */
1232 ID(xor); DR(A); SM2(HL, C, 0); Fz;
1233
1234/** 0111 1100 xor %0, #%1 */
1235 ID(xor); DR(A); SC(IMMU(1)); Fz;
1236
1237/** 0110 0001 0111 1rba xor %0, %1 */
1238 ID(xor); DR(A); SRB(rba); Fz;
1239
1240/** 0110 0001 0111 0reg xor %0, %1 */
1241 ID(xor); DRB(reg); SR(A); Fz;
1242
1243/** 0111 1011 xor %0, %1 */
1244 ID(xor); DR(A); SM(None, SADDR); Fz;
1245
1246/** 0111 1010 xor %0, #%1 */
1247 ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz;
1248
1249/*----------------------------------------------------------------------*/
1250
1251/** 0111 0001 1bit 0111 xor1 cy, %e1%1 */
1252 ID(xor); DCY(); SM(HL, 0); SB(bit);
1253
1254/** 0111 0001 1bit 1111 xor1 cy, %1 */
1255 ID(xor); DCY(); SR(A); SB(bit);
1256
1257/** 0111 0001 0bit 1111 xor1 cy, %s1 */
1258 ID(xor); DCY(); SM(None, SFR); SB(bit);
1259
1260/** 0111 0001 0bit 0111 xor1 cy, %s1 */
1261 ID(xor); DCY(); SM(None, SADDR); SB(bit);
1262
1263/*----------------------------------------------------------------------*/
1264
1265/** */
1266
1267 return rl78->n_bytes;
1268}
GDB Binutils - Deliverables
This page took 0.086089 seconds and 4 git commands to generate.