projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 252b5132 | 1 | /* Table of opcodes for the sparc. |
| 060d22b0 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
| 9e8c70f9 | 3 | 2000, 2002, 2004, 2005, 2006, 2007, 2008, 2011 |
| 252b5132 RH |
4 | Free Software Foundation, Inc. |
| 5 | ||
| 9b201bb5 | 6 | This file is part of the GNU opcodes library. |
| 252b5132 | 7 | |
| 9b201bb5 NC |
8 | This library is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by | |
| 10 | the Free Software Foundation; either version 3, or (at your option) | |
| 11 | any later version. | |
| 252b5132 | 12 | |
| 9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
| 14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 16 | License for more details. | |
| 252b5132 | 17 | |
| 47b0e7ad | 18 | You should have received a copy of the GNU General Public License |
| 9b201bb5 NC |
19 | along with this file; see the file COPYING. If not, write to the |
| 20 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
| 21 | MA 02110-1301, USA. */ | |
| 22 | ||
| 252b5132 RH |
23 | |
| 24 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the | |
| 25 | instruction's name rather than the args. This would make gas faster, pinsn | |
| 26 | slower, but would mess up some macros a bit. xoxorich. */ | |
| 27 | ||
| 28 | #include <stdio.h> | |
| 0d8dfecf | 29 | #include "sysdep.h" |
| 252b5132 RH |
30 | #include "opcode/sparc.h" |
| 31 | ||
| 32 | /* Some defines to make life easy. */ | |
| 33 | #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) | |
| 34 | #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) | |
| 35 | #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) | |
| 36 | #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) | |
| 37 | #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) | |
| 38 | #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) | |
| 39 | #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) | |
| 19f7b010 | 40 | #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) |
| 252b5132 RH |
41 | |
| 42 | /* Bit masks of architectures supporting the insn. */ | |
| 43 | ||
| 44 | #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ | |
| 19f7b010 | 45 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
| 47b0e7ad | 46 | /* v6 insns not supported on the sparclet. */ |
| 252b5132 | 47 | #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ |
| 19f7b010 | 48 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
| 252b5132 | 49 | #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ |
| 19f7b010 | 50 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
| 252b5132 RH |
51 | /* Although not all insns are implemented in hardware, sparclite is defined |
| 52 | to be a superset of v8. Unimplemented insns trap and are then theoretically | |
| 53 | implemented in software. | |
| 54 | It's not clear that the same is true for sparclet, although the docs | |
| 55 | suggest it is. Rather than complicating things, the sparclet assembler | |
| 56 | recognizes all v8 insns. */ | |
| 19f7b010 JJ |
57 | #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ |
| 58 | | MASK_V9 | MASK_V9A | MASK_V9B) | |
| 252b5132 RH |
59 | #define sparclet (MASK_SPARCLET) |
| 60 | #define sparclite (MASK_SPARCLITE) | |
| 19f7b010 JJ |
61 | #define v9 (MASK_V9 | MASK_V9A | MASK_V9B) |
| 62 | #define v9a (MASK_V9A | MASK_V9B) | |
| 63 | #define v9b (MASK_V9B) | |
| 47b0e7ad | 64 | /* v6 insns not supported by v9. */ |
| 252b5132 RH |
65 | #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ |
| 66 | | MASK_SPARCLET | MASK_SPARCLITE) | |
| 67 | /* v9a instructions which would appear to be aliases to v9's impdep's | |
| 47b0e7ad | 68 | otherwise. */ |
| 252b5132 RH |
69 | #define v9notv9a (MASK_V9) |
| 70 | ||
| 71 | /* Table of opcode architectures. | |
| 72 | The order is defined in opcode/sparc.h. */ | |
| 73 | ||
| 47b0e7ad NC |
74 | const struct sparc_opcode_arch sparc_opcode_archs[] = |
| 75 | { | |
| 252b5132 RH |
76 | { "v6", MASK_V6 }, |
| 77 | { "v7", MASK_V6 | MASK_V7 }, | |
| 78 | { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, | |
| 79 | { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, | |
| 80 | { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, | |
| 81 | /* ??? Don't some v8 priviledged insns conflict with v9? */ | |
| 82 | { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, | |
| 83 | /* v9 with ultrasparc additions */ | |
| 84 | { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, | |
| 19f7b010 JJ |
85 | /* v9 with cheetah additions */ |
| 86 | { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B }, | |
| 252b5132 RH |
87 | { NULL, 0 } |
| 88 | }; | |
| 89 | ||
| 90 | /* Given NAME, return it's architecture entry. */ | |
| 91 | ||
| 92 | enum sparc_opcode_arch_val | |
| 47b0e7ad | 93 | sparc_opcode_lookup_arch (const char *name) |
| 252b5132 RH |
94 | { |
| 95 | const struct sparc_opcode_arch *p; | |
| 96 | ||
| 97 | for (p = &sparc_opcode_archs[0]; p->name; ++p) | |
| 47b0e7ad NC |
98 | if (strcmp (name, p->name) == 0) |
| 99 | return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); | |
| 252b5132 RH |
100 | |
| 101 | return SPARC_OPCODE_ARCH_BAD; | |
| 102 | } | |
| 103 | \f | |
| 104 | /* Branch condition field. */ | |
| 47b0e7ad | 105 | #define COND(x) (((x) & 0xf) << 25) |
| 252b5132 RH |
106 | |
| 107 | /* v9: Move (MOVcc and FMOVcc) condition field. */ | |
| 47b0e7ad | 108 | #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ |
| 252b5132 RH |
109 | |
| 110 | /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ | |
| 47b0e7ad NC |
111 | #define RCOND(x) (((x) & 0x7) << 10) /* v9 */ |
| 112 | ||
| 113 | #define CONDA (COND (0x8)) | |
| 114 | #define CONDCC (COND (0xd)) | |
| 115 | #define CONDCS (COND (0x5)) | |
| 116 | #define CONDE (COND (0x1)) | |
| 117 | #define CONDG (COND (0xa)) | |
| 118 | #define CONDGE (COND (0xb)) | |
| 119 | #define CONDGU (COND (0xc)) | |
| 120 | #define CONDL (COND (0x3)) | |
| 121 | #define CONDLE (COND (0x2)) | |
| 122 | #define CONDLEU (COND (0x4)) | |
| 123 | #define CONDN (COND (0x0)) | |
| 124 | #define CONDNE (COND (0x9)) | |
| 125 | #define CONDNEG (COND (0x6)) | |
| 126 | #define CONDPOS (COND (0xe)) | |
| 127 | #define CONDVC (COND (0xf)) | |
| 128 | #define CONDVS (COND (0x7)) | |
| 252b5132 RH |
129 | |
| 130 | #define CONDNZ CONDNE | |
| 131 | #define CONDZ CONDE | |
| 132 | #define CONDGEU CONDCC | |
| 133 | #define CONDLU CONDCS | |
| 134 | ||
| 47b0e7ad NC |
135 | #define FCONDA (COND (0x8)) |
| 136 | #define FCONDE (COND (0x9)) | |
| 137 | #define FCONDG (COND (0x6)) | |
| 138 | #define FCONDGE (COND (0xb)) | |
| 139 | #define FCONDL (COND (0x4)) | |
| 140 | #define FCONDLE (COND (0xd)) | |
| 141 | #define FCONDLG (COND (0x2)) | |
| 142 | #define FCONDN (COND (0x0)) | |
| 143 | #define FCONDNE (COND (0x1)) | |
| 144 | #define FCONDO (COND (0xf)) | |
| 145 | #define FCONDU (COND (0x7)) | |
| 146 | #define FCONDUE (COND (0xa)) | |
| 147 | #define FCONDUG (COND (0x5)) | |
| 148 | #define FCONDUGE (COND (0xc)) | |
| 149 | #define FCONDUL (COND (0x3)) | |
| 150 | #define FCONDULE (COND (0xe)) | |
| 252b5132 RH |
151 | |
| 152 | #define FCONDNZ FCONDNE | |
| 153 | #define FCONDZ FCONDE | |
| 154 | ||
| 47b0e7ad NC |
155 | #define ICC (0) /* v9 */ |
| 156 | #define XCC (1 << 12) /* v9 */ | |
| 157 | #define FCC(x) (((x) & 0x3) << 11) /* v9 */ | |
| 158 | #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ | |
| 252b5132 RH |
159 | \f |
| 160 | /* The order of the opcodes in the table is significant: | |
| 47b0e7ad | 161 | |
| 252b5132 RH |
162 | * The assembler requires that all instances of the same mnemonic must |
| 163 | be consecutive. If they aren't, the assembler will bomb at runtime. | |
| 164 | ||
| 47b0e7ad | 165 | * The disassembler should not care about the order of the opcodes. */ |
| 252b5132 RH |
166 | |
| 167 | /* Entries for commutative arithmetic operations. */ | |
| 168 | /* ??? More entries can make use of this. */ | |
| 169 | #define COMMUTEOP(opcode, op3, arch_mask) \ | |
| ec668d69 DM |
170 | { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, 0, arch_mask }, \ |
| 171 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, 0, arch_mask }, \ | |
| 172 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, 0, arch_mask } | |
| 252b5132 RH |
173 | |
| 174 | const struct sparc_opcode sparc_opcodes[] = { | |
| 175 | ||
| ec668d69 DM |
176 | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, v6 }, |
| 177 | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, 0, v6 }, /* ld [rs1+%g0],d */ | |
| 178 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, v6 }, | |
| 179 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, v6 }, | |
| 180 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, 0, v6 }, | |
| 181 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ld [rs1+0],d */ | |
| 182 | { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, v6 }, | |
| 183 | { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, 0, v6 }, /* ld [rs1+%g0],d */ | |
| 184 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, v6 }, | |
| 185 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, 0, v6 }, | |
| 186 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, 0, v6 }, | |
| 187 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, v6 }, /* ld [rs1+0],d */ | |
| 188 | ||
| 189 | { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, v6 }, | |
| 190 | { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+%g0],d */ | |
| 191 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, v6 }, | |
| 192 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, v6 }, | |
| 193 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, v6 }, | |
| 194 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+0],d */ | |
| 195 | ||
| 196 | { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, 0, v6notv9 }, | |
| 197 | { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */ | |
| 198 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, 0, v6notv9 }, | |
| 199 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, 0, v6notv9 }, | |
| 200 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, 0, v6notv9 }, | |
| 201 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, v6notv9 }, /* ld [rs1+0],d */ | |
| 202 | { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, 0, v6notv9 }, | |
| 203 | { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */ | |
| 204 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, 0, v6notv9 }, | |
| 205 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, 0, v6notv9 }, | |
| 206 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, 0, v6notv9 }, | |
| 207 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, v6notv9 }, /* ld [rs1+0],d */ | |
| 252b5132 RH |
208 | |
| 209 | /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the | |
| 210 | 'ld' pseudo-op in v9. */ | |
| ec668d69 DM |
211 | { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, 0, v9 }, |
| 212 | { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+%g0],d */ | |
| 213 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, 0, v9 }, | |
| 214 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, 0, v9 }, | |
| 215 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, v9 }, | |
| 216 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */ | |
| 217 | ||
| 218 | { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 }, | |
| 219 | { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldd [rs1+%g0],d */ | |
| 220 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, 0, v6 }, | |
| 221 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, 0, v6 }, | |
| 222 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, 0, v6 }, | |
| 223 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldd [rs1+0],d */ | |
| 224 | { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, 0, v6 }, | |
| 225 | { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, 0, v6 }, /* ldd [rs1+%g0],d */ | |
| 226 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, 0, v6 }, | |
| 227 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, 0, v6 }, | |
| 228 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, 0, v6 }, | |
| 229 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, 0, v6 }, /* ldd [rs1+0],d */ | |
| 230 | ||
| 231 | { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, 0, v6notv9 }, | |
| 232 | { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */ | |
| 233 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, 0, v6notv9 }, | |
| 234 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, 0, v6notv9 }, | |
| 235 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, 0, v6notv9 }, | |
| 236 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, v6notv9 }, /* ldd [rs1+0],d */ | |
| 237 | ||
| 238 | { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, 0, v9 }, | |
| 239 | { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, 0, v9 }, /* ldd [rs1+%g0],d */ | |
| 240 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, 0, v9 }, | |
| 241 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, 0, v9 }, | |
| 242 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, 0, v9 }, | |
| 243 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, v9 }, /* ldd [rs1+0],d */ | |
| 244 | ||
| 245 | { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 }, | |
| 246 | { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldsb [rs1+%g0],d */ | |
| 247 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, 0, v6 }, | |
| 248 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, 0, v6 }, | |
| 249 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, 0, v6 }, | |
| 250 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldsb [rs1+0],d */ | |
| 251 | ||
| 252 | { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldsh [rs1+%g0],d */ | |
| 253 | { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 }, | |
| 254 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, 0, v6 }, | |
| 255 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, 0, v6 }, | |
| 256 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, 0, v6 }, | |
| 257 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldsh [rs1+0],d */ | |
| 258 | ||
| 259 | { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 }, | |
| 260 | { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldstub [rs1+%g0],d */ | |
| 261 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, 0, v6 }, | |
| 262 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, 0, v6 }, | |
| 263 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, 0, v6 }, | |
| 264 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldstub [rs1+0],d */ | |
| 265 | ||
| 266 | { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, 0, v9 }, | |
| 267 | { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v9 }, /* ldsw [rs1+%g0],d */ | |
| 268 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, 0, v9 }, | |
| 269 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, 0, v9 }, | |
| 270 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, 0, v9 }, | |
| 271 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, v9 }, /* ldsw [rs1+0],d */ | |
| 272 | ||
| 273 | { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 }, | |
| 274 | { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldub [rs1+%g0],d */ | |
| 275 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, 0, v6 }, | |
| 276 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, 0, v6 }, | |
| 277 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, 0, v6 }, | |
| 278 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldub [rs1+0],d */ | |
| 279 | ||
| 280 | { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 }, | |
| 281 | { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* lduh [rs1+%g0],d */ | |
| 282 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, 0, v6 }, | |
| 283 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, 0, v6 }, | |
| 284 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, 0, v6 }, | |
| 285 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* lduh [rs1+0],d */ | |
| 286 | ||
| 287 | { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, 0, v9 }, | |
| 288 | { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v9 }, /* ldx [rs1+%g0],d */ | |
| 289 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, 0, v9 }, | |
| 290 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, 0, v9 }, | |
| 291 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, 0, v9 }, | |
| 292 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, v9 }, /* ldx [rs1+0],d */ | |
| 293 | ||
| 294 | { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, v9 }, | |
| 295 | { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, 0, v9 }, /* ld [rs1+%g0],d */ | |
| 296 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, v9 }, | |
| 297 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, v9 }, | |
| 298 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, 0, v9 }, | |
| 299 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 300 | ||
| 301 | { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, v9b }, | |
| 302 | { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, 0, v9b }, | |
| 303 | { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, v9b }, | |
| 304 | { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, v9b }, | |
| 305 | { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, 0, v9b }, | |
| 306 | { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, v9b }, | |
| 307 | ||
| 308 | { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, v6 }, | |
| 309 | { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* lda [rs1+%g0],d */ | |
| 310 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 311 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 312 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 313 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 314 | { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, 0, v9 }, | |
| 315 | { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, 0, v9 }, /* lda [rs1+%g0],d */ | |
| 316 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, 0, v9 }, | |
| 317 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, 0, v9 }, | |
| 318 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, 0, v9 }, | |
| 319 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 320 | ||
| 321 | { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, v6 }, | |
| 322 | { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* ldda [rs1+%g0],d */ | |
| 323 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 324 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 325 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 326 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 327 | ||
| 328 | { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, 0, v9 }, | |
| 329 | { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, 0, v9 }, /* ldda [rs1+%g0],d */ | |
| 330 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, 0, v9 }, | |
| 331 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, 0, v9 }, | |
| 332 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, 0, v9 }, | |
| 333 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 334 | ||
| 335 | { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, 0, v9 }, | |
| 336 | { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, 0, v9 }, /* ldd [rs1+%g0],d */ | |
| 337 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, 0, v9 }, | |
| 338 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, 0, v9 }, | |
| 339 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, 0, v9 }, | |
| 340 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, v9 }, /* ldd [rs1+0],d */ | |
| 341 | ||
| 342 | { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, 0, v6 }, | |
| 343 | { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* ldsba [rs1+%g0],d */ | |
| 344 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 345 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 346 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 347 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 348 | ||
| 349 | { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, 0, v6 }, | |
| 350 | { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* ldsha [rs1+%g0],d */ | |
| 351 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 352 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 353 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 354 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 355 | ||
| 356 | { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, 0, v6 }, | |
| 357 | { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* ldstuba [rs1+%g0],d */ | |
| 358 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 359 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 360 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 361 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 362 | ||
| 363 | { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, 0, v9 }, | |
| 364 | { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */ | |
| 365 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 366 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 367 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 368 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 369 | ||
| 370 | { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, 0, v6 }, | |
| 371 | { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* lduba [rs1+%g0],d */ | |
| 372 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 373 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 374 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 375 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 376 | ||
| 377 | { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, 0, v6 }, | |
| 378 | { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* lduha [rs1+%g0],d */ | |
| 379 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 380 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 381 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 382 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 383 | ||
| 384 | { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, 0, v9 }, /* lduwa === lda */ | |
| 385 | { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, v9 }, /* lda [rs1+%g0],d */ | |
| 386 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, 0, v9 }, | |
| 387 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, 0, v9 }, | |
| 388 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, v9 }, | |
| 389 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */ | |
| 390 | ||
| 391 | { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, 0, v9 }, | |
| 392 | { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */ | |
| 393 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 394 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 395 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 396 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */ | |
| 397 | ||
| 398 | { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, 0, v6 }, | |
| 399 | { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */ | |
| 400 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, 0, v6 }, | |
| 401 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, 0, v6 }, | |
| 402 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, 0, v6 }, | |
| 403 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, 0, v6 }, /* st d,[rs1+0] */ | |
| 404 | { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, 0, v6 }, | |
| 405 | { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, 0, v6 }, /* st d[rs1+%g0] */ | |
| 406 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, 0, v6 }, | |
| 407 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, 0, v6 }, | |
| 408 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, 0, v6 }, | |
| 409 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, 0, v6 }, /* st d,[rs1+0] */ | |
| 410 | ||
| 411 | { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, 0, v6notv9 }, | |
| 412 | { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */ | |
| 413 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, 0, v6notv9 }, | |
| 414 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, 0, v6notv9 }, | |
| 415 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, 0, v6notv9 }, | |
| 416 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */ | |
| 417 | { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, 0, v6notv9 }, | |
| 418 | { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */ | |
| 419 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, 0, v6notv9 }, | |
| 420 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, 0, v6notv9 }, | |
| 421 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, 0, v6notv9 }, | |
| 422 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */ | |
| 423 | ||
| 424 | { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, 0, v6 }, | |
| 425 | { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */ | |
| 426 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, 0, v6 }, | |
| 427 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, 0, v6 }, | |
| 428 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, 0, v6 }, | |
| 429 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, 0, v6 }, /* st d,[rs1+0] */ | |
| 430 | ||
| 431 | { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v9 }, | |
| 432 | { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */ | |
| 433 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v9 }, | |
| 434 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v9 }, | |
| 435 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v9 }, | |
| 436 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */ | |
| 437 | { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v9 }, | |
| 438 | { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */ | |
| 439 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v9 }, | |
| 440 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v9 }, | |
| 441 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v9 }, | |
| 442 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */ | |
| 443 | { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v9 }, | |
| 444 | { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */ | |
| 445 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v9 }, | |
| 446 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v9 }, | |
| 447 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v9 }, | |
| 448 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */ | |
| 449 | ||
| 450 | { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 }, | |
| 451 | { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+%g0] */ | |
| 452 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v6 }, | |
| 453 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v6 }, | |
| 454 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 }, | |
| 455 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+0] */ | |
| 456 | ||
| 457 | { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, 0, v6 }, | |
| 458 | { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, 0, v6 }, /* sta d,[rs1+%g0] */ | |
| 459 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, 0, v9 }, | |
| 460 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, 0, v9 }, | |
| 461 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 }, | |
| 462 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */ | |
| 463 | ||
| 464 | { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, 0, v9 }, | |
| 465 | { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, 0, v9 }, /* sta d,[rs1+%g0] */ | |
| 466 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, 0, v9 }, | |
| 467 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, 0, v9 }, | |
| 468 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, 0, v9 }, | |
| 469 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */ | |
| 470 | ||
| 471 | { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, v9 }, | |
| 472 | { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */ | |
| 473 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, v9 }, | |
| 474 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, v9 }, | |
| 475 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 }, | |
| 476 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */ | |
| 477 | { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, v9 }, | |
| 478 | { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */ | |
| 479 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, v9 }, | |
| 480 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, v9 }, | |
| 481 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 }, | |
| 482 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */ | |
| 483 | { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, v9 }, | |
| 484 | { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */ | |
| 485 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, v9 }, | |
| 486 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, v9 }, | |
| 487 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 }, | |
| 488 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */ | |
| 489 | ||
| 490 | { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, 0, v6 }, | |
| 491 | { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v6 }, /* stb d,[rs1+%g0] */ | |
| 492 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, 0, v6 }, | |
| 493 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, 0, v6 }, | |
| 494 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, 0, v6 }, | |
| 495 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, v6 }, /* stb d,[rs1+0] */ | |
| 496 | ||
| 497 | { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 }, | |
| 498 | { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */ | |
| 499 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, v6 }, | |
| 500 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, v6 }, | |
| 501 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 }, | |
| 502 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */ | |
| 503 | { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 }, | |
| 504 | { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */ | |
| 505 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, v6 }, | |
| 506 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, v6 }, | |
| 507 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 }, | |
| 508 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */ | |
| 509 | ||
| 510 | { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, 0, v6 }, | |
| 511 | { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, 0, v6 }, /* stba d,[rs1+%g0] */ | |
| 512 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, 0, v9 }, | |
| 513 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, 0, v9 }, | |
| 514 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 }, | |
| 515 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* stb d,[rs1+0] */ | |
| 516 | ||
| 517 | { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, v6 }, | |
| 518 | { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */ | |
| 519 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, v9 }, | |
| 520 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, v9 }, | |
| 521 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 }, | |
| 522 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */ | |
| 523 | { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, v6 }, | |
| 524 | { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */ | |
| 525 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, v9 }, | |
| 526 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, v9 }, | |
| 527 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 }, | |
| 528 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */ | |
| 529 | ||
| 530 | { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, 0, v6 }, | |
| 531 | { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v6 }, /* std d,[rs1+%g0] */ | |
| 532 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, 0, v6 }, | |
| 533 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, 0, v6 }, | |
| 534 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, 0, v6 }, | |
| 535 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, v6 }, /* std d,[rs1+0] */ | |
| 536 | ||
| 537 | { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, 0, v6notv9 }, | |
| 538 | { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
| 539 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, 0, v6notv9 }, | |
| 540 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, 0, v6notv9 }, | |
| 541 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, 0, v6notv9 }, | |
| 542 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */ | |
| 543 | { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, 0, v6 }, | |
| 544 | { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, 0, v6 }, /* std d,[rs1+%g0] */ | |
| 545 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, 0, v6 }, | |
| 546 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, 0, v6 }, | |
| 547 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, 0, v6 }, | |
| 548 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, v6 }, /* std d,[rs1+0] */ | |
| 549 | ||
| 550 | { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, 0, v6notv9 }, | |
| 551 | { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
| 552 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, 0, v6notv9 }, | |
| 553 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, 0, v6notv9 }, | |
| 554 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, 0, v6notv9 }, | |
| 555 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */ | |
| 556 | { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, 0, v6notv9 }, | |
| 557 | { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ | |
| 558 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, 0, v6notv9 }, | |
| 559 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, 0, v6notv9 }, | |
| 560 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, 0, v6notv9 }, | |
| 561 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */ | |
| 562 | ||
| 563 | { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 }, | |
| 564 | { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+%g0] */ | |
| 565 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, 0, v6 }, | |
| 566 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, 0, v6 }, | |
| 567 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 }, | |
| 568 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+0] */ | |
| 569 | ||
| 570 | { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, 0, v6 }, | |
| 571 | { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, 0, v6 }, /* stda d,[rs1+%g0] */ | |
| 572 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, 0, v9 }, | |
| 573 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, 0, v9 }, | |
| 574 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 }, | |
| 575 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */ | |
| 576 | { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, 0, v9 }, | |
| 577 | { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */ | |
| 578 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, 0, v9 }, | |
| 579 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, 0, v9 }, | |
| 580 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, 0, v9 }, | |
| 581 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */ | |
| 582 | ||
| 583 | { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, 0, v6 }, | |
| 584 | { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v6 }, /* sth d,[rs1+%g0] */ | |
| 585 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, 0, v6 }, | |
| 586 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, 0, v6 }, | |
| 587 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, 0, v6 }, | |
| 588 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, v6 }, /* sth d,[rs1+0] */ | |
| 589 | ||
| 590 | { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 }, | |
| 591 | { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */ | |
| 592 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, v6 }, | |
| 593 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, v6 }, | |
| 594 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 }, | |
| 595 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */ | |
| 596 | { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 }, | |
| 597 | { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */ | |
| 598 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, v6 }, | |
| 599 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, v6 }, | |
| 600 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 }, | |
| 601 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */ | |
| 602 | ||
| 603 | { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, 0, v6 }, | |
| 604 | { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, 0, v6 }, /* stha ,[rs1+%g0] */ | |
| 605 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, 0, v9 }, | |
| 606 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, 0, v9 }, | |
| 607 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 }, | |
| 608 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* sth d,[rs1+0] */ | |
| 609 | ||
| 610 | { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, v6 }, | |
| 611 | { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */ | |
| 612 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, v9 }, | |
| 613 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, v9 }, | |
| 614 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 }, | |
| 615 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */ | |
| 616 | { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, v6 }, | |
| 617 | { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */ | |
| 618 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, v9 }, | |
| 619 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, v9 }, | |
| 620 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 }, | |
| 621 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */ | |
| 622 | ||
| 623 | { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, 0, v9 }, | |
| 624 | { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */ | |
| 625 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, 0, v9 }, | |
| 626 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, 0, v9 }, | |
| 627 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, 0, v9 }, | |
| 628 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */ | |
| 629 | ||
| 630 | { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, v9 }, | |
| 631 | { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */ | |
| 632 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, 0, v9 }, | |
| 633 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, 0, v9 }, | |
| 634 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, 0, v9 }, | |
| 635 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */ | |
| 636 | ||
| 637 | { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, 0, v9 }, | |
| 638 | { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, 0, v9 }, /* stxa d,[rs1+%g0] */ | |
| 639 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, 0, v9 }, | |
| 640 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, 0, v9 }, | |
| 641 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 }, | |
| 642 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* stx d,[rs1+0] */ | |
| 643 | ||
| 644 | { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, 0, v9 }, | |
| 645 | { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, 0, v9 }, /* stq [rs1+%g0] */ | |
| 646 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, 0, v9 }, | |
| 647 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, 0, v9 }, | |
| 648 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, 0, v9 }, | |
| 649 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, v9 }, /* stq [rs1+0] */ | |
| 650 | ||
| 651 | { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, 0, v9 }, | |
| 652 | { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, 0, v9 }, /* stqa [rs1+%g0] */ | |
| 653 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, 0, v9 }, | |
| 654 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, 0, v9 }, | |
| 655 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, 0, v9 }, | |
| 656 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, v9 }, /* stqa [rs1+0] */ | |
| 657 | ||
| 658 | { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, 0, v7 }, | |
| 659 | { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v7 }, /* swap [rs1+%g0],d */ | |
| 660 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, 0, v7 }, | |
| 661 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, 0, v7 }, | |
| 662 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, 0, v7 }, | |
| 663 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, v7 }, /* swap [rs1+0],d */ | |
| 664 | ||
| 665 | { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, 0, v7 }, | |
| 666 | { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, 0, v7 }, /* swapa [rs1+%g0],d */ | |
| 667 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, 0, v9 }, | |
| 668 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, 0, v9 }, | |
| 669 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 }, | |
| 670 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* swap [rs1+0],d */ | |
| 671 | ||
| 672 | { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 673 | { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, v6 }, /* restore %g0,%g0,%g0 */ | |
| 674 | { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, v6 }, | |
| 675 | { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, 0, v6 }, /* restore %g0,0,%g0 */ | |
| 676 | ||
| 677 | { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+rs2 */ | |
| 678 | { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1,%g0 */ | |
| 679 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+X */ | |
| 680 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */ | |
| 681 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */ | |
| 682 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, v6 }, /* rett X */ | |
| 683 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+0 */ | |
| 684 | ||
| 685 | { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 686 | { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, v6 }, | |
| 687 | { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, 0, v6 }, /* Sun assembler compatibility */ | |
| 688 | { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, 0, v6 }, | |
| 689 | ||
| 690 | { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %i7+8,%g0 */ | |
| 691 | { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %o7+8,%g0 */ | |
| 692 | ||
| 693 | { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, 0, v6 }, | |
| 694 | { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,d */ | |
| 695 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,d */ | |
| 696 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,d */ | |
| 697 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, 0, v6 }, | |
| 698 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, 0, v6 }, | |
| 699 | ||
| 700 | { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 701 | { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 702 | { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 703 | { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 704 | { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 705 | { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 706 | { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 707 | { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, 0, v9 }, | |
| 708 | { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, 0, v9 }, | |
| 709 | ||
| 710 | { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, 0, v8 }, | |
| 711 | { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, 0, v8 }, /* flush rs1+%g0 */ | |
| 712 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, 0, v8 }, /* flush rs1+0 */ | |
| 713 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, 0, v8 }, /* flush %g0+i */ | |
| 714 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, 0, v8 }, | |
| 715 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, 0, v8 }, | |
| 252b5132 RH |
716 | |
| 717 | /* IFLUSH was renamed to FLUSH in v8. */ | |
| ec668d69 DM |
718 | { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, v6 }, |
| 719 | { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, v6 }, /* flush rs1+%g0 */ | |
| 720 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, v6 }, /* flush rs1+0 */ | |
| 721 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, v6 }, | |
| 722 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, v6 }, | |
| 723 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, v6 }, | |
| 724 | ||
| 725 | { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, 0, v9 }, | |
| 726 | { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, 0, v9 }, /* return rs1+%g0 */ | |
| 727 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, v9 }, /* return rs1+0 */ | |
| 728 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, 0, v9 }, /* return %g0+i */ | |
| 729 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, 0, v9 }, | |
| 730 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, 0, v9 }, | |
| 731 | ||
| 732 | { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, v9 }, | |
| 733 | ||
| 734 | { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, v9 }, | |
| 735 | { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, v8 }, | |
| 736 | ||
| 737 | { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, 0, v9 }, | |
| 738 | { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ | |
| 739 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, 0, v9 }, | |
| 740 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, 0, v9 }, | |
| 741 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, 0, v9 }, | |
| 742 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ | |
| 743 | { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, 0, v9 }, | |
| 744 | { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ | |
| 745 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, 0, v9 }, | |
| 746 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, 0, v9 }, | |
| 747 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, 0, v9 }, | |
| 748 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, v9 }, /* prefetcha [rs1+0],d */ | |
| 749 | ||
| 750 | { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, v6 }, | |
| 751 | { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, v6 }, | |
| 752 | { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, v6 }, | |
| 753 | { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, v6 }, | |
| 754 | { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, v6 }, | |
| 755 | { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, v6 }, | |
| 756 | ||
| 757 | { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, 0, v9 }, | |
| 758 | { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, 0, v9 }, | |
| 759 | { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, 0, v9 }, | |
| 760 | { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, 0, v9 }, | |
| 761 | { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, 0, v9 }, | |
| 762 | { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, 0, v9 }, | |
| 763 | ||
| 764 | { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 765 | { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, 0, v6 }, | |
| 766 | ||
| 767 | { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, 0, sparclite }, | |
| 768 | { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, 0, sparclite }, | |
| 769 | ||
| 770 | { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, 0, sparclet|sparclite }, | |
| 771 | { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, 0, sparclet|sparclite }, | |
| 772 | ||
| 773 | { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, v9 }, | |
| 774 | { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, HWCAP_POPC, v9 }, | |
| 775 | ||
| 776 | { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, 0, v6 }, /* or %g0,%g0,d */ | |
| 777 | { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, 0, v6 }, /* or %g0,0,d */ | |
| 778 | { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v6 }, | |
| 779 | { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+%g0] */ | |
| 780 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v6 }, | |
| 781 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v6 }, | |
| 782 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v6 }, | |
| 783 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+0] */ | |
| 784 | ||
| 785 | { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v6 }, | |
| 786 | { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+%g0] */ | |
| 787 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v6 }, | |
| 788 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v6 }, | |
| 789 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v6 }, | |
| 790 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+0] */ | |
| 791 | ||
| 792 | { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v6 }, | |
| 793 | { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+%g0] */ | |
| 794 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v6 }, | |
| 795 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v6 }, | |
| 796 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v6 }, | |
| 797 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+0] */ | |
| 798 | ||
| 799 | { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v9 }, | |
| 800 | { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+%g0] */ | |
| 801 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v9 }, | |
| 802 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v9 }, | |
| 803 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v9 }, | |
| 804 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+0] */ | |
| 805 | ||
| 806 | { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 807 | { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, 0, v6 }, | |
| 808 | { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, 0, v6 }, | |
| 252b5132 RH |
809 | |
| 810 | /* This is not a commutative instruction. */ | |
| ec668d69 DM |
811 | { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 812 | { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, 0, v6 }, | |
| 252b5132 RH |
813 | |
| 814 | /* This is not a commutative instruction. */ | |
| ec668d69 DM |
815 | { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 816 | { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, 0, v6 }, | |
| 817 | ||
| 818 | { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, 0, v6 }, /* orcc rs1, %g0, %g0 */ | |
| 819 | { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, v6 }, /* orcc %g0, rs2, %g0 */ | |
| 820 | { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, 0, v6 }, /* orcc rs1, 0, %g0 */ | |
| 821 | ||
| 822 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, v8 }, /* wr r,r,%asrX */ | |
| 823 | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, v8 }, /* wr r,i,%asrX */ | |
| 824 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */ | |
| 825 | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */ | |
| 826 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */ | |
| 827 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, 0, v6 }, /* wr r,r,%y */ | |
| 828 | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, 0, v6 }, /* wr r,i,%y */ | |
| 829 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */ | |
| 830 | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */ | |
| 831 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */ | |
| 832 | { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, 0, v6notv9 }, /* wr r,r,%psr */ | |
| 833 | { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, 0, v6notv9 }, /* wr r,i,%psr */ | |
| 834 | { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */ | |
| 835 | { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */ | |
| 836 | { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */ | |
| 837 | { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, 0, v6notv9 }, /* wr r,r,%wim */ | |
| 838 | { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, 0, v6notv9 }, /* wr r,i,%wim */ | |
| 839 | { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */ | |
| 840 | { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */ | |
| 841 | { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */ | |
| 842 | { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, 0, v6notv9 }, /* wr r,r,%tbr */ | |
| 843 | { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, 0, v6notv9 }, /* wr r,i,%tbr */ | |
| 844 | { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */ | |
| 845 | { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */ | |
| 846 | { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */ | |
| 847 | ||
| 848 | { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, v9 }, /* wr r,r,%ccr */ | |
| 849 | { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, 0, v9 }, /* wr r,i,%ccr */ | |
| 850 | { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, v9 }, /* wr r,r,%asi */ | |
| 851 | { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, 0, v9 }, /* wr r,i,%asi */ | |
| 852 | { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, v9 }, /* wr r,r,%fprs */ | |
| 853 | { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, 0, v9 }, /* wr r,i,%fprs */ | |
| 854 | ||
| 855 | { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pcr */ | |
| 856 | { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pcr */ | |
| 857 | { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pic */ | |
| 858 | { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pic */ | |
| 859 | { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%dcr */ | |
| 860 | { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%dcr */ | |
| 861 | { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%gsr */ | |
| 862 | { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%gsr */ | |
| 863 | { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%set_softint */ | |
| 864 | { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%set_softint */ | |
| 865 | { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%clear_softint */ | |
| 866 | { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%clear_softint */ | |
| 867 | { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%softint */ | |
| 868 | { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%softint */ | |
| 869 | { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%tick_cmpr */ | |
| 870 | { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%tick_cmpr */ | |
| 871 | { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick */ | |
| 872 | { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick */ | |
| 873 | { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick_cmpr */ | |
| 874 | { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick_cmpr */ | |
| 875 | { "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */ | |
| 876 | { "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28), "1,i,_", 0, HWCAP_VIS3, v9b }, /* wr r,i,%cps */ | |
| 877 | ||
| 878 | { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, v8 }, /* rd %asrX,r */ | |
| 879 | { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, 0, v6 }, /* rd %y,r */ | |
| 880 | { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, 0, v6notv9 }, /* rd %psr,r */ | |
| 881 | { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, 0, v6notv9 }, /* rd %wim,r */ | |
| 882 | { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, 0, v6notv9 }, /* rd %tbr,r */ | |
| 883 | ||
| 884 | { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, v9 }, /* rd %ccr,r */ | |
| 885 | { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, v9 }, /* rd %asi,r */ | |
| 886 | { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, v9 }, /* rd %tick,r */ | |
| 887 | { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, v9 }, /* rd %pc,r */ | |
| 888 | { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, v9 }, /* rd %fprs,r */ | |
| 889 | ||
| 890 | { "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %pcr,r */ | |
| 891 | { "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %pic,r */ | |
| 892 | { "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %dcr,r */ | |
| 893 | { "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %gsr,r */ | |
| 894 | { "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %softint,r */ | |
| 895 | { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %tick_cmpr,r */ | |
| 896 | { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick,r */ | |
| 897 | { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick_cmpr,r */ | |
| 898 | { "rd", F3(2, 0x28, 0)|RS1(28), F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0), "/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */ | |
| 899 | ||
| 900 | { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, 0, v9 }, /* rdpr %priv,r */ | |
| 901 | { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, 0, v9 }, /* wrpr r1,r2,%priv */ | |
| 902 | { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, 0, v9 }, /* wrpr r1,%priv */ | |
| 903 | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, 0, v9 }, /* wrpr r1,i,%priv */ | |
| 904 | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, 0, v9 }, /* wrpr i,r1,%priv */ | |
| 905 | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, 0, v9 }, /* wrpr i,%priv */ | |
| 906 | ||
| 907 | { "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, 0, v9 }, /* rdhpr %hpriv,r */ | |
| 908 | { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, 0, v9 }, /* wrhpr r1,r2,%hpriv */ | |
| 909 | { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, 0, v9 }, /* wrhpr r1,%hpriv */ | |
| 910 | { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, 0, v9 }, /* wrhpr r1,i,%hpriv */ | |
| 911 | { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, 0, v9 }, /* wrhpr i,r1,%hpriv */ | |
| 912 | { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, 0, v9 }, /* wrhpr i,%hpriv */ | |
| ff3f9d5b | 913 | |
| 252b5132 | 914 | /* ??? This group seems wrong. A three operand move? */ |
| ec668d69 DM |
915 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, 0, v8 }, /* wr r,r,%asrX */ |
| 916 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, 0, v8 }, /* wr r,i,%asrX */ | |
| 917 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, 0, v6 }, /* wr r,r,%y */ | |
| 918 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, 0, v6 }, /* wr r,i,%y */ | |
| 919 | { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, 0, v6notv9 }, /* wr r,r,%psr */ | |
| 920 | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, 0, v6notv9 }, /* wr r,i,%psr */ | |
| 921 | { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, 0, v6notv9 }, /* wr r,r,%wim */ | |
| 922 | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, 0, v6notv9 }, /* wr r,i,%wim */ | |
| 923 | { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, 0, v6notv9 }, /* wr r,r,%tbr */ | |
| 924 | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, 0, v6notv9 }, /* wr r,i,%tbr */ | |
| 925 | ||
| 926 | { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, 0, v8 }, /* rd %asr1,r */ | |
| 927 | { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, 0, v6 }, /* rd %y,r */ | |
| 928 | { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, 0, v6notv9 }, /* rd %psr,r */ | |
| 929 | { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, 0, v6notv9 }, /* rd %wim,r */ | |
| 930 | { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, 0, v6notv9 }, /* rd %tbr,r */ | |
| 931 | ||
| 932 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */ | |
| 933 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */ | |
| 934 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */ | |
| 935 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, 0, v8 }, /* wr rs1,0,%asrX */ | |
| 936 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */ | |
| 937 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */ | |
| 938 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */ | |
| 939 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, 0, v6 }, /* wr rs1,0,%y */ | |
| 940 | { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */ | |
| 941 | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */ | |
| 942 | { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */ | |
| 943 | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%psr */ | |
| 944 | { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */ | |
| 945 | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */ | |
| 946 | { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */ | |
| 947 | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%wim */ | |
| 948 | { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */ | |
| 949 | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */ | |
| 950 | { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */ | |
| 951 | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%tbr */ | |
| 952 | ||
| 953 | { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, 0, v6 }, /* or %g0,rs2,d */ | |
| 954 | { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, 0, v6 }, /* or %g0,i,d */ | |
| 955 | { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, 0, v6 }, /* or rs1,%g0,d */ | |
| 956 | { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, 0, v6 }, /* or rs1,0,d */ | |
| 957 | ||
| 958 | { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 959 | { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, 0, v6 }, | |
| 960 | { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, 0, v6 }, | |
| 961 | ||
| 962 | { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, 0, v6 }, /* or rd,rs2,rd */ | |
| 963 | { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, 0, v6 }, /* or rd,i,rd */ | |
| 252b5132 RH |
964 | |
| 965 | /* This is not a commutative instruction. */ | |
| ec668d69 DM |
966 | { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 967 | { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, 0, v6 }, | |
| 252b5132 RH |
968 | |
| 969 | /* This is not a commutative instruction. */ | |
| ec668d69 DM |
970 | { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 971 | { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, 0, v6 }, | |
| 972 | ||
| 973 | { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, 0, v6 }, /* andn rd,rs2,rd */ | |
| 974 | { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, 0, v6 }, /* andn rd,i,rd */ | |
| 975 | ||
| 976 | { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, 0, v6 }, /* subcc rs1,rs2,%g0 */ | |
| 977 | { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, 0, v6 }, /* subcc rs1,i,%g0 */ | |
| 978 | ||
| 979 | { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 980 | { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, 0, v6 }, | |
| 981 | ||
| 982 | { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 983 | { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, 0, v6 }, | |
| 984 | ||
| 985 | { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 }, | |
| 986 | { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, v6notv9 }, | |
| 987 | { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, v9 }, | |
| 988 | { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, v9 }, | |
| 989 | ||
| 990 | { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 }, | |
| 991 | { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, v6notv9 }, | |
| 992 | { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, v9 }, | |
| 993 | { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, v9 }, | |
| 994 | ||
| 995 | { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 996 | { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, 0, v6 }, | |
| 997 | { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, 0, v6 }, | |
| 998 | ||
| 999 | { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 1000 | { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, 0, v6 }, | |
| 1001 | { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, 0, v6 }, | |
| 1002 | ||
| 1003 | { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* sub rd,1,rd */ | |
| 1004 | { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, 0, v8 }, /* sub rd,imm,rd */ | |
| 1005 | { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* subcc rd,1,rd */ | |
| 1006 | { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, 0, v8 }, /* subcc rd,imm,rd */ | |
| 1007 | { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* add rd,1,rd */ | |
| 1008 | { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, 0, v8 }, /* add rd,imm,rd */ | |
| 1009 | { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* addcc rd,1,rd */ | |
| 1010 | { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, 0, v8 }, /* addcc rd,imm,rd */ | |
| 1011 | ||
| 1012 | { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, v6 }, /* andcc rs1,rs2,%g0 */ | |
| 1013 | { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, v6 }, /* andcc rs1,i,%g0 */ | |
| 1014 | ||
| 1015 | { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, v6 }, /* sub %g0,rs2,rd */ | |
| 1016 | { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, v6 }, /* sub %g0,rd,rd */ | |
| 1017 | ||
| 1018 | { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 1019 | { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, 0, v6 }, | |
| 1020 | { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, 0, v6 }, | |
| 1021 | { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 1022 | { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, 0, v6 }, | |
| 1023 | { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, 0, v6 }, | |
| 1024 | ||
| 1025 | { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 }, | |
| 1026 | { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, v6notv9 }, | |
| 1027 | { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, v6notv9 }, | |
| 1028 | { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, v9 }, | |
| 1029 | { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, v9 }, | |
| 1030 | { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, v9 }, | |
| 1031 | ||
| 1032 | { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 }, | |
| 1033 | { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, v6notv9 }, | |
| 1034 | { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, v6notv9 }, | |
| 1035 | { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, v9 }, | |
| 1036 | { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, v9 }, | |
| 1037 | { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, v9 }, | |
| 1038 | ||
| 1039 | { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 }, | |
| 1040 | { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, HWCAP_MUL32, v8 }, | |
| 1041 | { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, HWCAP_MUL32, v8 }, | |
| 1042 | { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 }, | |
| 1043 | { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, HWCAP_MUL32, v8 }, | |
| 1044 | { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, HWCAP_MUL32, v8 }, | |
| 1045 | { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 }, | |
| 1046 | { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, HWCAP_MUL32, v8 }, | |
| 1047 | { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, HWCAP_MUL32, v8 }, | |
| 1048 | { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 }, | |
| 1049 | { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, HWCAP_MUL32, v8 }, | |
| 1050 | { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, HWCAP_MUL32, v8 }, | |
| 1051 | { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 }, | |
| 1052 | { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, HWCAP_DIV32, v8 }, | |
| 1053 | { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, HWCAP_DIV32, v8 }, | |
| 1054 | { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 }, | |
| 1055 | { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, HWCAP_DIV32, v8 }, | |
| 1056 | { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, HWCAP_DIV32, v8 }, | |
| 1057 | { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 }, | |
| 1058 | { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, HWCAP_DIV32, v8 }, | |
| 1059 | { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, HWCAP_DIV32, v8 }, | |
| 1060 | { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 }, | |
| 1061 | { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, HWCAP_DIV32, v8 }, | |
| 1062 | { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, HWCAP_DIV32, v8 }, | |
| 1063 | ||
| 1064 | { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, 0, v9 }, | |
| 1065 | { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, 0, v9 }, | |
| 1066 | { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, v9 }, | |
| 1067 | { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, v9 }, | |
| 1068 | { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, 0, v9 }, | |
| 1069 | { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, 0, v9 }, | |
| 1070 | ||
| 1071 | { "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, v6 }, | |
| 1072 | { "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, v6 }, | |
| 1073 | ||
| 1074 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%o7 */ | |
| 1075 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, 0, v6 }, | |
| 1076 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%o7 */ | |
| 1077 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, 0, v6 }, | |
| 1078 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%o7 */ | |
| 1079 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, 0, v6 }, | |
| 1080 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%o7 */ | |
| 1081 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, 0, v6 }, | |
| 1082 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%o7 */ | |
| 1083 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, 0, v6 }, | |
| 1084 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%o7 */ | |
| 1085 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, 0, v6 }, | |
| 1086 | ||
| 1087 | { "chkpt", F2(0, 1)|CONDA|ANNUL|(1<<20), F2(~0, ~1)|((~CONDA)&COND(~0)), "G", 0, HWCAP_TRANS, v9b }, | |
| 252b5132 RH |
1088 | |
| 1089 | /* Conditional instructions. | |
| 1090 | ||
| 1091 | Because this part of the table was such a mess earlier, I have | |
| 1092 | macrofied it so that all the branches and traps are generated from | |
| 1093 | a single-line description of each condition value. John Gilmore. */ | |
| 1094 | ||
| 1095 | /* Define branches -- one annulled, one without, etc. */ | |
| 1096 | #define br(opcode, mask, lose, flags) \ | |
| ec668d69 DM |
1097 | { opcode, (mask)|ANNUL, (lose), ",a l", (flags), 0, v6 }, \ |
| 1098 | { opcode, (mask) , (lose)|ANNUL, "l", (flags), 0, v6 } | |
| 252b5132 RH |
1099 | |
| 1100 | #define brx(opcode, mask, lose, flags) /* v9 */ \ | |
| ec668d69 DM |
1101 | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), 0, v9 }, \ |
| 1102 | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), 0, v9 }, \ | |
| 1103 | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), 0, v9 }, \ | |
| 1104 | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, v9 }, \ | |
| 1105 | { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), 0, v9 }, \ | |
| 1106 | { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, v9 }, \ | |
| 1107 | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), 0, v9 }, \ | |
| 1108 | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), 0, v9 }, \ | |
| 1109 | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), 0, v9 }, \ | |
| 1110 | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, v9 }, \ | |
| 1111 | { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), 0, v9 }, \ | |
| 1112 | { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, v9 } | |
| 252b5132 RH |
1113 | |
| 1114 | /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ | |
| 1115 | #define tr(opcode, mask, lose, flags) \ | |
| ec668d69 DM |
1116 | { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), 0, v9 }, /* %g0 + imm */ \ |
| 1117 | { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), 0, v9 }, /* rs1 + imm */ \ | |
| 1118 | { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), 0, v9 }, /* rs1 + rs2 */ \ | |
| 1119 | { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), 0, v9 }, /* rs1 + %g0 */ \ | |
| 1120 | { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, 0, v9 }, /* %g0 + imm */ \ | |
| 1121 | { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, 0, v9 }, /* rs1 + imm */ \ | |
| 1122 | { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, 0, v9 }, /* rs1 + rs2 */ \ | |
| 1123 | { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, 0, v9 }, /* rs1 + %g0 */ \ | |
| 1124 | { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), 0, v6 }, /* %g0 + imm */ \ | |
| 1125 | { opcode, (mask)|IMMED, (lose), "1+i", (flags), 0, v6 }, /* rs1 + imm */ \ | |
| 1126 | { opcode, (mask)|IMMED, (lose), "i+1", (flags), 0, v6 }, /* imm + rs1 */ \ | |
| 1127 | { opcode, (mask), IMMED|(lose), "1+2", (flags), 0, v6 }, /* rs1 + rs2 */ \ | |
| 1128 | { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), 0, v6 } /* rs1 + %g0 */ | |
| 252b5132 RH |
1129 | |
| 1130 | /* v9: We must put `brx' before `br', to ensure that we never match something | |
| 1131 | v9: against an expression unless it is an expression. Otherwise, we end | |
| 1132 | v9: up with undefined symbol tables entries, because they get added, but | |
| 1133 | v9: are not deleted if the pattern fails to match. */ | |
| 1134 | ||
| 1135 | /* Define both branches and traps based on condition mask */ | |
| 1136 | #define cond(bop, top, mask, flags) \ | |
| 1137 | brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ | |
| 1138 | br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ | |
| 1139 | tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) | |
| 1140 | ||
| 1141 | /* Define all the conditions, all the branches, all the traps. */ | |
| 1142 | ||
| 1143 | /* Standard branch, trap mnemonics */ | |
| 1144 | cond ("b", "ta", CONDA, F_UNBR), | |
| 1145 | /* Alternative form (just for assembly, not for disassembly) */ | |
| 1146 | cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), | |
| 1147 | ||
| 1148 | cond ("bcc", "tcc", CONDCC, F_CONDBR), | |
| 1149 | cond ("bcs", "tcs", CONDCS, F_CONDBR), | |
| 1150 | cond ("be", "te", CONDE, F_CONDBR), | |
| 1151 | cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), | |
| 1152 | cond ("bg", "tg", CONDG, F_CONDBR), | |
| 1153 | cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), | |
| 1154 | cond ("bge", "tge", CONDGE, F_CONDBR), | |
| 1155 | cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ | |
| 1156 | cond ("bgu", "tgu", CONDGU, F_CONDBR), | |
| 1157 | cond ("bl", "tl", CONDL, F_CONDBR), | |
| 1158 | cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), | |
| 1159 | cond ("ble", "tle", CONDLE, F_CONDBR), | |
| 1160 | cond ("bleu", "tleu", CONDLEU, F_CONDBR), | |
| 1161 | cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ | |
| 1162 | cond ("bn", "tn", CONDN, F_CONDBR), | |
| 1163 | cond ("bne", "tne", CONDNE, F_CONDBR), | |
| 1164 | cond ("bneg", "tneg", CONDNEG, F_CONDBR), | |
| 1165 | cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ | |
| 1166 | cond ("bpos", "tpos", CONDPOS, F_CONDBR), | |
| 1167 | cond ("bvc", "tvc", CONDVC, F_CONDBR), | |
| 1168 | cond ("bvs", "tvs", CONDVS, F_CONDBR), | |
| 1169 | cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ | |
| 1170 | ||
| 1171 | #undef cond | |
| 1172 | #undef br | |
| 1173 | #undef brr /* v9 */ | |
| 1174 | #undef tr | |
| 1175 | ||
| 1176 | #define brr(opcode, mask, lose, flags) /* v9 */ \ | |
| ec668d69 DM |
1177 | { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), 0, v9 }, \ |
| 1178 | { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), 0, v9 }, \ | |
| 1179 | { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), 0, v9 }, \ | |
| 1180 | { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, v9 }, \ | |
| 1181 | { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), 0, v9 }, \ | |
| 1182 | { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, v9 } | |
| 252b5132 RH |
1183 | |
| 1184 | #define condr(bop, mask, flags) /* v9 */ \ | |
| 1185 | brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ | |
| 1186 | ||
| 1187 | /* v9 */ condr("brnz", 0x5, F_CONDBR), | |
| 1188 | /* v9 */ condr("brz", 0x1, F_CONDBR), | |
| 1189 | /* v9 */ condr("brgez", 0x7, F_CONDBR), | |
| 1190 | /* v9 */ condr("brlz", 0x3, F_CONDBR), | |
| 1191 | /* v9 */ condr("brlez", 0x2, F_CONDBR), | |
| 1192 | /* v9 */ condr("brgz", 0x6, F_CONDBR), | |
| 1193 | ||
| 1194 | #undef condr /* v9 */ | |
| 1195 | #undef brr /* v9 */ | |
| 1196 | ||
| 1197 | #define movr(opcode, mask, flags) /* v9 */ \ | |
| ec668d69 DM |
1198 | { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, v9 }, \ |
| 1199 | { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, v9 } | |
| 252b5132 RH |
1200 | |
| 1201 | #define fmrrs(opcode, mask, lose, flags) /* v9 */ \ | |
| ec668d69 | 1202 | { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, v9 } |
| 252b5132 | 1203 | #define fmrrd(opcode, mask, lose, flags) /* v9 */ \ |
| ec668d69 | 1204 | { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, v9 } |
| 252b5132 | 1205 | #define fmrrq(opcode, mask, lose, flags) /* v9 */ \ |
| ec668d69 | 1206 | { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, v9 } |
| 252b5132 RH |
1207 | |
| 1208 | #define fmovrs(mop, mask, flags) /* v9 */ \ | |
| 1209 | fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ | |
| 1210 | #define fmovrd(mop, mask, flags) /* v9 */ \ | |
| 1211 | fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ | |
| 1212 | #define fmovrq(mop, mask, flags) /* v9 */ \ | |
| 1213 | fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ | |
| 1214 | ||
| 1215 | /* v9 */ movr("movrne", 0x5, 0), | |
| 1216 | /* v9 */ movr("movre", 0x1, 0), | |
| 1217 | /* v9 */ movr("movrgez", 0x7, 0), | |
| 1218 | /* v9 */ movr("movrlz", 0x3, 0), | |
| 1219 | /* v9 */ movr("movrlez", 0x2, 0), | |
| 1220 | /* v9 */ movr("movrgz", 0x6, 0), | |
| 1221 | /* v9 */ movr("movrnz", 0x5, F_ALIAS), | |
| 1222 | /* v9 */ movr("movrz", 0x1, F_ALIAS), | |
| 1223 | ||
| 1224 | /* v9 */ fmovrs("fmovrsne", 0x5, 0), | |
| 1225 | /* v9 */ fmovrs("fmovrse", 0x1, 0), | |
| 1226 | /* v9 */ fmovrs("fmovrsgez", 0x7, 0), | |
| 1227 | /* v9 */ fmovrs("fmovrslz", 0x3, 0), | |
| 1228 | /* v9 */ fmovrs("fmovrslez", 0x2, 0), | |
| 1229 | /* v9 */ fmovrs("fmovrsgz", 0x6, 0), | |
| 1230 | /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), | |
| 1231 | /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), | |
| 1232 | ||
| 1233 | /* v9 */ fmovrd("fmovrdne", 0x5, 0), | |
| 1234 | /* v9 */ fmovrd("fmovrde", 0x1, 0), | |
| 1235 | /* v9 */ fmovrd("fmovrdgez", 0x7, 0), | |
| 1236 | /* v9 */ fmovrd("fmovrdlz", 0x3, 0), | |
| 1237 | /* v9 */ fmovrd("fmovrdlez", 0x2, 0), | |
| 1238 | /* v9 */ fmovrd("fmovrdgz", 0x6, 0), | |
| 1239 | /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), | |
| 1240 | /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), | |
| 1241 | ||
| 1242 | /* v9 */ fmovrq("fmovrqne", 0x5, 0), | |
| 1243 | /* v9 */ fmovrq("fmovrqe", 0x1, 0), | |
| 1244 | /* v9 */ fmovrq("fmovrqgez", 0x7, 0), | |
| 1245 | /* v9 */ fmovrq("fmovrqlz", 0x3, 0), | |
| 1246 | /* v9 */ fmovrq("fmovrqlez", 0x2, 0), | |
| 1247 | /* v9 */ fmovrq("fmovrqgz", 0x6, 0), | |
| 1248 | /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), | |
| 1249 | /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), | |
| 1250 | ||
| 1251 | #undef movr /* v9 */ | |
| 1252 | #undef fmovr /* v9 */ | |
| 1253 | #undef fmrr /* v9 */ | |
| 1254 | ||
| 1255 | #define movicc(opcode, cond, flags) /* v9 */ \ | |
| ec668d69 DM |
1256 | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, v9 }, \ |
| 1257 | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, v9 }, \ | |
| 1258 | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, 0, v9 }, \ | |
| 1259 | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, 0, v9 } | |
| 252b5132 RH |
1260 | |
| 1261 | #define movfcc(opcode, fcond, flags) /* v9 */ \ | |
| ec668d69 DM |
1262 | { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, v9 }, \ |
| 1263 | { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, v9 }, \ | |
| 1264 | { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, v9 }, \ | |
| 1265 | { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, v9 }, \ | |
| 1266 | { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, v9 }, \ | |
| 1267 | { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, v9 }, \ | |
| 1268 | { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, v9 }, \ | |
| 1269 | { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, v9 } | |
| 252b5132 RH |
1270 | |
| 1271 | #define movcc(opcode, cond, fcond, flags) /* v9 */ \ | |
| 1272 | movfcc (opcode, fcond, flags), /* v9 */ \ | |
| 1273 | movicc (opcode, cond, flags) /* v9 */ | |
| 1274 | ||
| 1275 | /* v9 */ movcc ("mova", CONDA, FCONDA, 0), | |
| 1276 | /* v9 */ movicc ("movcc", CONDCC, 0), | |
| 1277 | /* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), | |
| 1278 | /* v9 */ movicc ("movcs", CONDCS, 0), | |
| 1279 | /* v9 */ movicc ("movlu", CONDLU, F_ALIAS), | |
| 1280 | /* v9 */ movcc ("move", CONDE, FCONDE, 0), | |
| 1281 | /* v9 */ movcc ("movg", CONDG, FCONDG, 0), | |
| 1282 | /* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), | |
| 1283 | /* v9 */ movicc ("movgu", CONDGU, 0), | |
| 1284 | /* v9 */ movcc ("movl", CONDL, FCONDL, 0), | |
| 1285 | /* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), | |
| 1286 | /* v9 */ movicc ("movleu", CONDLEU, 0), | |
| 1287 | /* v9 */ movfcc ("movlg", FCONDLG, 0), | |
| 1288 | /* v9 */ movcc ("movn", CONDN, FCONDN, 0), | |
| 1289 | /* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), | |
| 1290 | /* v9 */ movicc ("movneg", CONDNEG, 0), | |
| 1291 | /* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), | |
| 1292 | /* v9 */ movfcc ("movo", FCONDO, 0), | |
| 1293 | /* v9 */ movicc ("movpos", CONDPOS, 0), | |
| 1294 | /* v9 */ movfcc ("movu", FCONDU, 0), | |
| 1295 | /* v9 */ movfcc ("movue", FCONDUE, 0), | |
| 1296 | /* v9 */ movfcc ("movug", FCONDUG, 0), | |
| 1297 | /* v9 */ movfcc ("movuge", FCONDUGE, 0), | |
| 1298 | /* v9 */ movfcc ("movul", FCONDUL, 0), | |
| 1299 | /* v9 */ movfcc ("movule", FCONDULE, 0), | |
| 1300 | /* v9 */ movicc ("movvc", CONDVC, 0), | |
| 1301 | /* v9 */ movicc ("movvs", CONDVS, 0), | |
| 1302 | /* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), | |
| 1303 | ||
| 1304 | #undef movicc /* v9 */ | |
| 1305 | #undef movfcc /* v9 */ | |
| 1306 | #undef movcc /* v9 */ | |
| 1307 | ||
| 1308 | #define FM_SF 1 /* v9 - values for fpsize */ | |
| 1309 | #define FM_DF 2 /* v9 */ | |
| 1310 | #define FM_QF 3 /* v9 */ | |
| 1311 | ||
| b4781d44 | 1312 | #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ |
| ec668d69 DM |
1313 | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, 0, v9 }, \ |
| 1314 | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, 0, v9 } | |
| 252b5132 | 1315 | |
| b4781d44 | 1316 | #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ |
| ec668d69 DM |
1317 | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, v9 }, \ |
| 1318 | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, v9 }, \ | |
| 1319 | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, v9 }, \ | |
| 1320 | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, v9 } | |
| 252b5132 RH |
1321 | |
| 1322 | /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ | |
| b4781d44 | 1323 | #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ |
| ec668d69 DM |
1324 | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, 0, v9 }, \ |
| 1325 | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, v9 }, \ | |
| 1326 | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, 0, v9 }, \ | |
| 1327 | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, v9 }, \ | |
| 1328 | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, v9 }, \ | |
| 1329 | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, v9 } | |
| b4781d44 JJ |
1330 | |
| 1331 | #define fmovicc(suffix, cond, flags) /* v9 */ \ | |
| 1332 | fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ | |
| 1333 | fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ | |
| 1334 | fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) | |
| 1335 | ||
| 1336 | #define fmovfcc(suffix, fcond, flags) /* v9 */ \ | |
| 1337 | fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ | |
| 1338 | fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ | |
| 1339 | fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) | |
| 1340 | ||
| 1341 | #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ | |
| 1342 | fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ | |
| 1343 | fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ | |
| 1344 | fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) | |
| 1345 | ||
| 1346 | /* v9 */ fmovcc ("a", CONDA, FCONDA, 0), | |
| 1347 | /* v9 */ fmovicc ("cc", CONDCC, 0), | |
| 1348 | /* v9 */ fmovicc ("cs", CONDCS, 0), | |
| 1349 | /* v9 */ fmovcc ("e", CONDE, FCONDE, 0), | |
| 1350 | /* v9 */ fmovcc ("g", CONDG, FCONDG, 0), | |
| 1351 | /* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0), | |
| 1352 | /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS), | |
| 1353 | /* v9 */ fmovicc ("gu", CONDGU, 0), | |
| 1354 | /* v9 */ fmovcc ("l", CONDL, FCONDL, 0), | |
| 1355 | /* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0), | |
| 1356 | /* v9 */ fmovicc ("leu", CONDLEU, 0), | |
| 1357 | /* v9 */ fmovfcc ("lg", FCONDLG, 0), | |
| 1358 | /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS), | |
| 1359 | /* v9 */ fmovcc ("n", CONDN, FCONDN, 0), | |
| 1360 | /* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0), | |
| 1361 | /* v9 */ fmovicc ("neg", CONDNEG, 0), | |
| 1362 | /* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS), | |
| 1363 | /* v9 */ fmovfcc ("o", FCONDO, 0), | |
| 1364 | /* v9 */ fmovicc ("pos", CONDPOS, 0), | |
| 1365 | /* v9 */ fmovfcc ("u", FCONDU, 0), | |
| 1366 | /* v9 */ fmovfcc ("ue", FCONDUE, 0), | |
| 1367 | /* v9 */ fmovfcc ("ug", FCONDUG, 0), | |
| 1368 | /* v9 */ fmovfcc ("uge", FCONDUGE, 0), | |
| 1369 | /* v9 */ fmovfcc ("ul", FCONDUL, 0), | |
| 1370 | /* v9 */ fmovfcc ("ule", FCONDULE, 0), | |
| 1371 | /* v9 */ fmovicc ("vc", CONDVC, 0), | |
| 1372 | /* v9 */ fmovicc ("vs", CONDVS, 0), | |
| 1373 | /* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS), | |
| 1374 | ||
| 1375 | #undef fmoviccx /* v9 */ | |
| 1376 | #undef fmovfccx /* v9 */ | |
| 1377 | #undef fmovccx /* v9 */ | |
| 252b5132 RH |
1378 | #undef fmovicc /* v9 */ |
| 1379 | #undef fmovfcc /* v9 */ | |
| 1380 | #undef fmovcc /* v9 */ | |
| 1381 | #undef FM_DF /* v9 */ | |
| 1382 | #undef FM_QF /* v9 */ | |
| 1383 | #undef FM_SF /* v9 */ | |
| 1384 | ||
| 1385 | /* Coprocessor branches. */ | |
| 1386 | #define CBR(opcode, mask, lose, flags, arch) \ | |
| ec668d69 DM |
1387 | { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, 0, arch }, \ |
| 1388 | { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, arch } | |
| 252b5132 RH |
1389 | |
| 1390 | /* Floating point branches. */ | |
| 1391 | #define FBR(opcode, mask, lose, flags) \ | |
| ec668d69 DM |
1392 | { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, 0, v6 }, \ |
| 1393 | { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, v6 } | |
| 252b5132 RH |
1394 | |
| 1395 | /* V9 extended floating point branches. */ | |
| 1396 | #define FBRX(opcode, mask, lose, flags) /* v9 */ \ | |
| ec668d69 DM |
1397 | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ |
| 1398 | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1399 | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1400 | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1401 | { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1402 | { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1403 | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1404 | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1405 | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1406 | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1407 | { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1408 | { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1409 | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1410 | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1411 | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1412 | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1413 | { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1414 | { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1415 | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1416 | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1417 | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1418 | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1419 | { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \ | |
| 1420 | { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, v9 } | |
| 252b5132 RH |
1421 | |
| 1422 | /* v9: We must put `FBRX' before `FBR', to ensure that we never match | |
| 1423 | v9: something against an expression unless it is an expression. Otherwise, | |
| 1424 | v9: we end up with undefined symbol tables entries, because they get added, | |
| 1425 | v9: but are not deleted if the pattern fails to match. */ | |
| 1426 | ||
| 1427 | #define CONDFC(fop, cop, mask, flags) \ | |
| 1428 | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ | |
| 1429 | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ | |
| 1430 | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) | |
| 1431 | ||
| 1432 | #define CONDFCL(fop, cop, mask, flags) \ | |
| 1433 | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ | |
| 1434 | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ | |
| 1435 | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) | |
| 1436 | ||
| 1437 | #define CONDF(fop, mask, flags) \ | |
| 1438 | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ | |
| 1439 | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) | |
| 1440 | ||
| d3c866d1 NC |
1441 | CONDFC ("fb", "cb", 0x8, F_UNBR), |
| 1442 | CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), | |
| 1443 | CONDFC ("fbe", "cb0", 0x9, F_CONDBR), | |
| 1444 | CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), | |
| 1445 | CONDFC ("fbg", "cb2", 0x6, F_CONDBR), | |
| 1446 | CONDFC ("fbge", "cb02", 0xb, F_CONDBR), | |
| 1447 | CONDFC ("fbl", "cb1", 0x4, F_CONDBR), | |
| 1448 | CONDFC ("fble", "cb01", 0xd, F_CONDBR), | |
| 1449 | CONDFC ("fblg", "cb12", 0x2, F_CONDBR), | |
| 1450 | CONDFCL ("fbn", "cbn", 0x0, F_UNBR), | |
| 1451 | CONDFC ("fbne", "cb123", 0x1, F_CONDBR), | |
| 1452 | CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), | |
| 1453 | CONDFC ("fbo", "cb012", 0xf, F_CONDBR), | |
| 1454 | CONDFC ("fbu", "cb3", 0x7, F_CONDBR), | |
| 1455 | CONDFC ("fbue", "cb03", 0xa, F_CONDBR), | |
| 1456 | CONDFC ("fbug", "cb23", 0x5, F_CONDBR), | |
| 1457 | CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), | |
| 1458 | CONDFC ("fbul", "cb13", 0x3, F_CONDBR), | |
| 1459 | CONDFC ("fbule", "cb013", 0xe, F_CONDBR), | |
| 252b5132 RH |
1460 | |
| 1461 | #undef CONDFC | |
| 1462 | #undef CONDFCL | |
| 1463 | #undef CONDF | |
| 1464 | #undef CBR | |
| 1465 | #undef FBR | |
| 1466 | #undef FBRX /* v9 */ | |
| 1467 | ||
| ec668d69 DM |
1468 | { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%g0 */ |
| 1469 | { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%g0 */ | |
| 1470 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%g0 */ | |
| 1471 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%g0 */ | |
| 1472 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%g0 */ | |
| 1473 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%g0 */ | |
| 252b5132 | 1474 | |
| ec668d69 | 1475 | { "nop", F2(0, 4), 0xfeffffff, "", 0, 0, v6 }, /* sethi 0, %g0 */ |
| 252b5132 | 1476 | |
| ec668d69 DM |
1477 | { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v6 }, |
| 1478 | { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 }, | |
| 1479 | { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 }, | |
| 1480 | { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, v9 }, | |
| 252b5132 | 1481 | |
| ec668d69 | 1482 | { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, v6 }, |
| 252b5132 | 1483 | |
| ec668d69 DM |
1484 | { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 1485 | { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, 0, v6 }, | |
| 1486 | { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, 0, v6 }, | |
| 1487 | { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 1488 | { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, 0, v6 }, | |
| 1489 | { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, 0, v6 }, | |
| 252b5132 | 1490 | |
| ec668d69 DM |
1491 | { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 1492 | { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, 0, v6 }, | |
| 1493 | { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 1494 | { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, 0, v6 }, | |
| 252b5132 | 1495 | |
| ec668d69 DM |
1496 | { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, 0, v6notv9 }, |
| 1497 | { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, v9 }, | |
| 252b5132 RH |
1498 | |
| 1499 | /* This *is* a commutative instruction. */ | |
| ec668d69 DM |
1500 | { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 1501 | { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, 0, v6 }, | |
| 1502 | { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, 0, v6 }, | |
| 252b5132 | 1503 | /* This *is* a commutative instruction. */ |
| ec668d69 DM |
1504 | { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, |
| 1505 | { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, 0, v6 }, | |
| 1506 | { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, 0, v6 }, | |
| 1507 | { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 1508 | { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, 0, v6 }, | |
| 1509 | { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, 0, v6 }, | |
| 1510 | { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, 0, v6 }, | |
| 1511 | { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, 0, v6 }, | |
| 1512 | { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, 0, v6 }, | |
| 1513 | ||
| 1514 | { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, v6 }, /* xnor rs1,%0,rd */ | |
| 1515 | { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, v6 }, /* xnor rd,%0,rd */ | |
| 1516 | ||
| 1517 | { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, 0, v6 }, /* xor rd,rs2,rd */ | |
| 1518 | { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, 0, v6 }, /* xor rd,i,rd */ | |
| 252b5132 RH |
1519 | |
| 1520 | /* FPop1 and FPop2 are not instructions. Don't accept them. */ | |
| 1521 | ||
| ec668d69 DM |
1522 | { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, v6 }, |
| 1523 | { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, v6 }, | |
| 1524 | { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, v8 }, | |
| 1525 | ||
| 1526 | { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, v9 }, | |
| 1527 | { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, v9 }, | |
| 1528 | { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, v9 }, | |
| 1529 | ||
| 1530 | { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, v6 }, | |
| 1531 | { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, v6 }, | |
| 1532 | { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, v8 }, | |
| 1533 | ||
| 1534 | { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, v9 }, | |
| 1535 | { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, v9 }, | |
| 1536 | { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, v9 }, | |
| 1537 | ||
| 1538 | { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, v8 }, | |
| 1539 | { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, v6 }, | |
| 1540 | { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, v8 }, | |
| 1541 | { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, v8 }, | |
| 1542 | { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, v6 }, | |
| 1543 | { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, v8 }, | |
| 1544 | ||
| 1545 | { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, v6 }, | |
| 1546 | { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, v8 }, | |
| 1547 | { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1548 | { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, v6 }, | |
| 1549 | { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, v6 }, | |
| 1550 | { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, v8 }, | |
| 1551 | { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1552 | { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, v6 }, | |
| 1553 | ||
| 1554 | { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, v8 }, | |
| 1555 | { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1556 | { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, v8 }, | |
| 1557 | ||
| 1558 | { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, v7 }, | |
| 1559 | { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, v8 }, | |
| 1560 | { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1561 | { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, v7 }, | |
| 1562 | ||
| 1563 | { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, v9 }, | |
| 1564 | { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, v9 }, | |
| 1565 | { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1566 | { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, v6 }, | |
| 1567 | { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, v9 }, | |
| 1568 | { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, v9 }, | |
| 1569 | { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1570 | { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, v6 }, | |
| 1571 | { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, v9 }, | |
| 1572 | { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, v9 }, | |
| 1573 | { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1574 | { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, v6 }, | |
| 1575 | ||
| 1576 | { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, v6 }, | |
| 1577 | { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, v8 }, | |
| 1578 | { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1579 | { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, v6 }, | |
| 1580 | { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, v6 }, | |
| 1581 | { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, v8 }, | |
| 1582 | { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1583 | { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, v6 }, | |
| 252b5132 RH |
1584 | |
| 1585 | #define CMPFCC(x) (((x)&0x3)<<25) | |
| 1586 | ||
| ec668d69 DM |
1587 | { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, 0, v6 }, |
| 1588 | { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, 0, v9 }, | |
| 1589 | { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, 0, v9 }, | |
| 1590 | { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, 0, v9 }, | |
| 1591 | { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, 0, v9 }, | |
| 1592 | { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, 0, v6 }, | |
| 1593 | { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, 0, v9 }, | |
| 1594 | { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, 0, v9 }, | |
| 1595 | { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, 0, v9 }, | |
| 1596 | { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, 0, v9 }, | |
| 1597 | { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, 0, v8 }, | |
| 1598 | { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, 0, v9 }, | |
| 1599 | { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, 0, v9 }, | |
| 1600 | { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, 0, v9 }, | |
| 1601 | { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, 0, v9 }, | |
| 1602 | { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, 0, v8 }, | |
| 1603 | { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, 0, v9 }, | |
| 1604 | { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, 0, v9 }, | |
| 1605 | { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, 0, v9 }, | |
| 1606 | { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, 0, v9 }, | |
| 1607 | { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1608 | { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1609 | { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1610 | { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1611 | { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1612 | { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, v8 }, | |
| 1613 | { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1614 | { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1615 | { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1616 | { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, 0, v9 }, | |
| 1617 | { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, 0, v6 }, | |
| 1618 | { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, 0, v9 }, | |
| 1619 | { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, 0, v9 }, | |
| 1620 | { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, 0, v9 }, | |
| 1621 | { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, 0, v9 }, | |
| 1622 | { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, 0, v6 }, | |
| 1623 | { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, 0, v9 }, | |
| 1624 | { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, 0, v9 }, | |
| 1625 | { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, 0, v9 }, | |
| 1626 | { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, 0, v9 }, | |
| 252b5132 RH |
1627 | |
| 1628 | /* These Extended FPop (FIFO) instructions are new in the Fujitsu | |
| 1629 | MB86934, replacing the CPop instructions from v6 and later | |
| 1630 | processors. */ | |
| 1631 | ||
| ec668d69 DM |
1632 | #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, sparclite } |
| 1633 | #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, 0, sparclite } | |
| 1634 | #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, 0, sparclite } | |
| 252b5132 RH |
1635 | |
| 1636 | EFPOP1_2 ("efitod", 0x0c8, "f,H"), | |
| 1637 | EFPOP1_2 ("efitos", 0x0c4, "f,g"), | |
| 1638 | EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), | |
| 1639 | EFPOP1_2 ("efstoi", 0x0d1, "f,g"), | |
| 1640 | EFPOP1_2 ("efstod", 0x0c9, "f,H"), | |
| 1641 | EFPOP1_2 ("efdtos", 0x0c6, "B,g"), | |
| 1642 | EFPOP1_2 ("efmovs", 0x001, "f,g"), | |
| 1643 | EFPOP1_2 ("efnegs", 0x005, "f,g"), | |
| 1644 | EFPOP1_2 ("efabss", 0x009, "f,g"), | |
| 1645 | EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), | |
| 1646 | EFPOP1_2 ("efsqrts", 0x029, "f,g"), | |
| 1647 | EFPOP1_3 ("efaddd", 0x042, "v,B,H"), | |
| 1648 | EFPOP1_3 ("efadds", 0x041, "e,f,g"), | |
| 1649 | EFPOP1_3 ("efsubd", 0x046, "v,B,H"), | |
| 1650 | EFPOP1_3 ("efsubs", 0x045, "e,f,g"), | |
| 1651 | EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), | |
| 1652 | EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), | |
| 1653 | EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), | |
| 1654 | EFPOP1_3 ("efmuls", 0x049, "e,f,g"), | |
| 1655 | EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), | |
| 1656 | EFPOP2_2 ("efcmpd", 0x052, "v,B"), | |
| 1657 | EFPOP2_2 ("efcmped", 0x056, "v,B"), | |
| 1658 | EFPOP2_2 ("efcmps", 0x051, "e,f"), | |
| 1659 | EFPOP2_2 ("efcmpes", 0x055, "e,f"), | |
| 1660 | ||
| 1661 | #undef EFPOP1_2 | |
| 1662 | #undef EFPOP1_3 | |
| 1663 | #undef EFPOP2_2 | |
| 1664 | ||
| 1665 | /* These are marked F_ALIAS, so that they won't conflict with sparclite insns | |
| 1666 | present. Otherwise, the F_ALIAS flag is ignored. */ | |
| ec668d69 DM |
1667 | { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 }, |
| 1668 | { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 }, | |
| 252b5132 RH |
1669 | |
| 1670 | /* sparclet specific insns */ | |
| 1671 | ||
| 1672 | COMMUTEOP ("umac", 0x3e, sparclet), | |
| 1673 | COMMUTEOP ("smac", 0x3f, sparclet), | |
| 1674 | COMMUTEOP ("umacd", 0x2e, sparclet), | |
| 1675 | COMMUTEOP ("smacd", 0x2f, sparclet), | |
| 1676 | COMMUTEOP ("umuld", 0x09, sparclet), | |
| 1677 | COMMUTEOP ("smuld", 0x0d, sparclet), | |
| 1678 | ||
| ec668d69 DM |
1679 | { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, sparclet }, |
| 1680 | { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, sparclet }, | |
| 252b5132 RH |
1681 | |
| 1682 | /* The manual isn't completely accurate on these insns. The `rs2' field is | |
| 1683 | treated as being 6 bits to account for 6 bit immediates to cpush. It is | |
| 1684 | assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ | |
| 1685 | #define BIT5 (1<<5) | |
| ec668d69 DM |
1686 | { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, sparclet }, |
| 1687 | { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, sparclet }, | |
| 1688 | { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, sparclet }, | |
| 1689 | { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, 0, sparclet }, | |
| 1690 | { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, sparclet }, | |
| 1691 | { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, 0, sparclet }, | |
| 1692 | { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, sparclet }, | |
| 252b5132 RH |
1693 | #undef BIT5 |
| 1694 | ||
| 1695 | /* sparclet coprocessor branch insns */ | |
| 1696 | #define SLCBCC2(opcode, mask, lose) \ | |
| ec668d69 DM |
1697 | { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, 0, sparclet }, \ |
| 1698 | { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, sparclet } | |
| 252b5132 RH |
1699 | #define SLCBCC(opcode, mask) \ |
| 1700 | SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) | |
| 1701 | ||
| 1702 | /* cbn,cba can't be defined here because they're defined elsewhere and GAS | |
| 1703 | requires all mnemonics of the same name to be consecutive. */ | |
| 1704 | /*SLCBCC("cbn", 0), - already defined */ | |
| 1705 | SLCBCC("cbe", 1), | |
| 1706 | SLCBCC("cbf", 2), | |
| 1707 | SLCBCC("cbef", 3), | |
| 1708 | SLCBCC("cbr", 4), | |
| 1709 | SLCBCC("cber", 5), | |
| 1710 | SLCBCC("cbfr", 6), | |
| 1711 | SLCBCC("cbefr", 7), | |
| 1712 | /*SLCBCC("cba", 8), - already defined */ | |
| 1713 | SLCBCC("cbne", 9), | |
| 1714 | SLCBCC("cbnf", 10), | |
| 1715 | SLCBCC("cbnef", 11), | |
| 1716 | SLCBCC("cbnr", 12), | |
| 1717 | SLCBCC("cbner", 13), | |
| 1718 | SLCBCC("cbnfr", 14), | |
| 1719 | SLCBCC("cbnefr", 15), | |
| 1720 | ||
| 1721 | #undef SLCBCC2 | |
| 1722 | #undef SLCBCC | |
| 1723 | ||
| ec668d69 DM |
1724 | { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, v9 }, |
| 1725 | { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, v9 }, | |
| 1726 | { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, v9 }, | |
| 1727 | { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, v9 }, | |
| 252b5132 RH |
1728 | |
| 1729 | /* v9 synthetic insns */ | |
| ec668d69 DM |
1730 | { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, v9 }, /* bn,a,pt %xcc,label */ |
| 1731 | { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* sra rs1,%g0,rd */ | |
| 1732 | { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* sra rd,%g0,rd */ | |
| 1733 | { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* srl rs1,%g0,rd */ | |
| 1734 | { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* srl rd,%g0,rd */ | |
| 1735 | { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */ | |
| 1736 | { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ | |
| 1737 | { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ | |
| 1738 | { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ | |
| 252b5132 RH |
1739 | |
| 1740 | /* Ultrasparc extensions */ | |
| ec668d69 | 1741 | { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, v9a }, |
| 252b5132 RH |
1742 | |
| 1743 | /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ | |
| ec668d69 DM |
1744 | { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, v9a }, |
| 1745 | { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1746 | { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1747 | { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1748 | { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1749 | { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1750 | { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1751 | { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1752 | ||
| 1753 | { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1754 | { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a }, | |
| 1755 | { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a }, | |
| 1756 | { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, v9a }, | |
| 1757 | { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, v9a }, | |
| 252b5132 RH |
1758 | |
| 1759 | /* Note that the mixing of 32/64 bit regs is intentional. */ | |
| ec668d69 DM |
1760 | { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, v9a }, |
| 1761 | { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, v9a }, | |
| 1762 | { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, v9a }, | |
| 1763 | { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1764 | { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1765 | { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, v9a }, | |
| 1766 | { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, v9a }, | |
| 1767 | ||
| 1768 | { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1769 | { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1770 | { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1771 | ||
| 1772 | { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, v9a }, | |
| 1773 | { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, v9a }, | |
| 1774 | { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, v9a }, | |
| 1775 | { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, v9a }, | |
| 1776 | { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, v9a }, | |
| 1777 | { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, v9a }, | |
| 1778 | { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, v9a }, | |
| 1779 | { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, v9a }, | |
| 1780 | { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, v9a }, | |
| 1781 | { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, v9a }, | |
| 1782 | { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, v9a }, | |
| 1783 | { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, v9a }, | |
| 1784 | { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1785 | { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1786 | { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1787 | { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1788 | { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1789 | { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1790 | { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1791 | { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1792 | { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1793 | { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1794 | { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1795 | { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1796 | { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1797 | { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1798 | { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1799 | { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1800 | { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1801 | { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1802 | { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1803 | { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, v9a }, | |
| 1804 | ||
| 1805 | { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1806 | { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1807 | { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1808 | { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1809 | { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1810 | { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1811 | { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1812 | { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, v9a }, | |
| 1813 | ||
| 1814 | { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1815 | { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1816 | { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1817 | { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1818 | { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1819 | { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1820 | ||
| 1821 | { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, v9a }, | |
| 1822 | ||
| 1823 | { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1824 | { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 1825 | { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, v9a }, | |
| 252b5132 | 1826 | |
| 19f7b010 | 1827 | /* Cheetah instructions */ |
| ec668d69 DM |
1828 | { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", HWCAP_VIS2, 0, v9b }, |
| 1829 | { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", HWCAP_VIS2, 0, v9b }, | |
| 1830 | { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", HWCAP_VIS2, 0, v9b }, | |
| 1831 | { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", HWCAP_VIS2, 0, v9b }, | |
| 1832 | { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", HWCAP_VIS2, 0, v9b }, | |
| 1833 | { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", HWCAP_VIS2, 0, v9b }, | |
| 1834 | ||
| 1835 | { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", HWCAP_VIS2, 0, v9b }, | |
| 1836 | { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", HWCAP_VIS2, 0, v9b }, | |
| 1837 | ||
| 1838 | { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", HWCAP_VIS2, 0, v9b }, | |
| 1839 | ||
| 1840 | { "commit", F3(2, 0x3e, 0)|RD(30), F3(~2, ~0x3e, ~0)|RD(~30)|RS1_G0|SIMM13(~0), "", 0, HWCAP_TRANS, v9b }, | |
| 1841 | { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1842 | { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1843 | { "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1844 | { "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1845 | { "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1846 | { "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1847 | { "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1848 | { "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1849 | { "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1850 | { "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1851 | { "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1852 | { "fpmaddx", F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b }, | |
| 1853 | { "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1854 | { "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1855 | { "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b }, | |
| 1856 | { "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1857 | { "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1858 | { "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1859 | { "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1860 | { "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1861 | { "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b }, | |
| 1862 | { "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1863 | { "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1864 | { "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1865 | { "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1866 | { "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1867 | { "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1868 | { "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1869 | { "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b }, | |
| 1870 | { "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, v9b }, | |
| 1871 | { "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, v9b }, | |
| 1872 | { "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT, HWCAP_RANDOM, v9b }, | |
| 1873 | { "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, v9b }, | |
| 1874 | { "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, v9b }, | |
| 1875 | { "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, v9b }, | |
| 1876 | { "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, v9b }, | |
| 1877 | { "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, v9b }, | |
| 1878 | { "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1879 | { "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1880 | { "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1881 | { "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1882 | { "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1883 | { "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1884 | { "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1885 | { "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1886 | { "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, v9b }, | |
| 1887 | { "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1888 | { "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1889 | { "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1890 | { "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1891 | { "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1892 | { "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, v9b }, | |
| 1893 | { "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1894 | { "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, v9b }, | |
| 1895 | { "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1896 | { "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, v9b }, | |
| 1897 | { "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, v9b }, | |
| 1898 | { "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, v9b }, | |
| 1899 | { "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, v9b }, | |
| 1900 | { "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, v9b }, | |
| 1901 | { "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, v9b }, | |
| 1902 | { "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, v9b }, | |
| 1903 | { "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, v9b }, | |
| 1904 | { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, v9b }, | |
| 1905 | { "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, v9b }, | |
| 1906 | { "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, v9b }, | |
| 1907 | { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b }, | |
| 1908 | { "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b }, | |
| 1909 | { "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b }, | |
| 6cda1326 DM |
1910 | {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, v9b }, |
| 1911 | {"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1912 | { "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, v9b }, | |
| 1913 | { "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, v9b }, | |
| 1914 | { "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, v9b }, | |
| 1915 | {"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, v9b }, | |
| 1916 | { "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b }, | |
| 1917 | {"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b }, | |
| 1918 | { "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, v9b }, | |
| 1919 | { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, v9b }, | |
| 1920 | { "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, v9b }, | |
| 1921 | { "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, v9b }, | |
| 1922 | { "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, v9b }, | |
| 1923 | { "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b }, | |
| 1924 | { "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b }, | |
| 1925 | { "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b }, | |
| 1926 | {"aes_eround01", F2(2, 0x19)|OPF_LOW4(0), F2(~2, ~0x19)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1927 | {"aes_eround23", F2(2, 0x19)|OPF_LOW4(1), F2(~2, ~0x19)|OPF_LOW4(~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1928 | {"aes_dround01", F2(2, 0x19)|OPF_LOW4(2), F2(~2, ~0x19)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1929 | {"aes_dround23", F2(2, 0x19)|OPF_LOW4(3), F2(~2, ~0x19)|OPF_LOW4(~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1930 | {"aes_eround01_l",F2(2, 0x19)|OPF_LOW4(4), F2(~2, ~0x19)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1931 | {"aes_eround23_l",F2(2, 0x19)|OPF_LOW4(5), F2(~2, ~0x19)|OPF_LOW4(~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1932 | {"aes_dround01_l",F2(2, 0x19)|OPF_LOW4(6), F2(~2, ~0x19)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1933 | {"aes_dround23_l",F2(2, 0x19)|OPF_LOW4(7), F2(~2, ~0x19)|OPF_LOW4(~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1934 | {"aes_kexpand1", F2(2, 0x19)|OPF_LOW4(8), F2(~2, ~0x19)|OPF_LOW4(~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b }, | |
| 1935 | {"des_round", F2(2, 0x19)|OPF_LOW4(9), F2(~2, ~0x19)|OPF_LOW4(~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b }, | |
| 1936 | {"kasumi_fl_xor", F2(2, 0x19)|OPF_LOW4(10), F2(~2, ~0x19)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b }, | |
| 1937 | {"kasumi_fi_xor", F2(2, 0x19)|OPF_LOW4(11), F2(~2, ~0x19)|OPF_LOW4(~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b }, | |
| 1938 | {"camellia_f", F2(2, 0x19)|OPF_LOW4(12), F2(~2, ~0x19)|OPF_LOW4(~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b }, | |
| ec668d69 DM |
1939 | { "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b }, |
| 1940 | { "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1941 | { "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1942 | { "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1943 | { "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1944 | { "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1945 | { "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, v9b }, | |
| 1946 | { "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, v9b }, | |
| ea783ef3 | 1947 | |
| 252b5132 RH |
1948 | /* More v9 specific insns, these need to come last so they do not clash |
| 1949 | with v9a instructions such as "edge8" which looks like impdep1. */ | |
| 1950 | ||
| 1951 | #define IMPDEP(name, code) \ | |
| ec668d69 DM |
1952 | { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, v9notv9a }, \ |
| 1953 | { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, 0, v9notv9a }, \ | |
| 1954 | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, 0, v9notv9a }, \ | |
| 1955 | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, 0, v9notv9a } | |
| 252b5132 RH |
1956 | |
| 1957 | IMPDEP ("impdep1", 0x36), | |
| 1958 | IMPDEP ("impdep2", 0x37), | |
| 1959 | ||
| 1960 | #undef IMPDEP | |
| 1961 | ||
| 1962 | }; | |
| 1963 | ||
| 1964 | const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); | |
| 1965 | \f | |
| 1966 | /* Utilities for argument parsing. */ | |
| 1967 | ||
| 1968 | typedef struct | |
| 1969 | { | |
| 1970 | int value; | |
| 1971 | const char *name; | |
| 1972 | } arg; | |
| 1973 | ||
| 1974 | /* Look up NAME in TABLE. */ | |
| 1975 | ||
| 252b5132 | 1976 | static int |
| 47b0e7ad | 1977 | lookup_name (const arg *table, const char *name) |
| 252b5132 RH |
1978 | { |
| 1979 | const arg *p; | |
| 1980 | ||
| 1981 | for (p = table; p->name; ++p) | |
| 1982 | if (strcmp (name, p->name) == 0) | |
| 1983 | return p->value; | |
| 1984 | ||
| 1985 | return -1; | |
| 1986 | } | |
| 1987 | ||
| 1988 | /* Look up VALUE in TABLE. */ | |
| 1989 | ||
| 1990 | static const char * | |
| 47b0e7ad | 1991 | lookup_value (const arg *table, int value) |
| 252b5132 RH |
1992 | { |
| 1993 | const arg *p; | |
| 1994 | ||
| 1995 | for (p = table; p->name; ++p) | |
| 1996 | if (value == p->value) | |
| 1997 | return p->name; | |
| 1998 | ||
| 47b0e7ad | 1999 | return NULL; |
| 252b5132 RH |
2000 | } |
| 2001 | \f | |
| 2002 | /* Handle ASI's. */ | |
| 2003 | ||
| 2004 | static arg asi_table[] = | |
| 2005 | { | |
| 2006 | /* These are in the v9 architecture manual. */ | |
| 2007 | /* The shorter versions appear first, they're here because Sun's as has them. | |
| 2008 | Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the | |
| 2009 | UltraSPARC architecture manual). */ | |
| 2010 | { 0x04, "#ASI_N" }, | |
| 2011 | { 0x0c, "#ASI_N_L" }, | |
| 2012 | { 0x10, "#ASI_AIUP" }, | |
| 2013 | { 0x11, "#ASI_AIUS" }, | |
| 2014 | { 0x18, "#ASI_AIUP_L" }, | |
| 2015 | { 0x19, "#ASI_AIUS_L" }, | |
| 2016 | { 0x80, "#ASI_P" }, | |
| 2017 | { 0x81, "#ASI_S" }, | |
| 2018 | { 0x82, "#ASI_PNF" }, | |
| 2019 | { 0x83, "#ASI_SNF" }, | |
| 2020 | { 0x88, "#ASI_P_L" }, | |
| 2021 | { 0x89, "#ASI_S_L" }, | |
| 2022 | { 0x8a, "#ASI_PNF_L" }, | |
| 2023 | { 0x8b, "#ASI_SNF_L" }, | |
| 2024 | { 0x04, "#ASI_NUCLEUS" }, | |
| 2025 | { 0x0c, "#ASI_NUCLEUS_LITTLE" }, | |
| 2026 | { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, | |
| 2027 | { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, | |
| 2028 | { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, | |
| 2029 | { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, | |
| 2030 | { 0x80, "#ASI_PRIMARY" }, | |
| 2031 | { 0x81, "#ASI_SECONDARY" }, | |
| 2032 | { 0x82, "#ASI_PRIMARY_NOFAULT" }, | |
| 2033 | { 0x83, "#ASI_SECONDARY_NOFAULT" }, | |
| 2034 | { 0x88, "#ASI_PRIMARY_LITTLE" }, | |
| 2035 | { 0x89, "#ASI_SECONDARY_LITTLE" }, | |
| 2036 | { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, | |
| 2037 | { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, | |
| 1a6b486f DM |
2038 | /* These are UltraSPARC and Niagara extensions. */ |
| 2039 | { 0x14, "#ASI_PHYS_USE_EC" }, | |
| 2040 | { 0x15, "#ASI_PHYS_BYPASS_EC_E" }, | |
| 2041 | { 0x16, "#ASI_BLK_AIUP_4V" }, | |
| 2042 | { 0x17, "#ASI_BLK_AIUS_4V" }, | |
| 2043 | { 0x1c, "#ASI_PHYS_USE_EC_L" }, | |
| 2044 | { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" }, | |
| 2045 | { 0x1e, "#ASI_BLK_AIUP_L_4V" }, | |
| 2046 | { 0x1f, "#ASI_BLK_AIUS_L_4V" }, | |
| 2047 | { 0x20, "#ASI_SCRATCHPAD" }, | |
| 2048 | { 0x21, "#ASI_MMU" }, | |
| 2049 | { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" }, | |
| 2050 | { 0x24, "#ASI_NUCLEUS_QUAD_LDD" }, | |
| 2051 | { 0x25, "#ASI_QUEUE" }, | |
| 2052 | { 0x26, "#ASI_QUAD_LDD_PHYS_4V" }, | |
| 2053 | { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" }, | |
| 2054 | { 0x30, "#ASI_PCACHE_DATA_STATUS" }, | |
| 2055 | { 0x31, "#ASI_PCACHE_DATA" }, | |
| 2056 | { 0x32, "#ASI_PCACHE_TAG" }, | |
| 2057 | { 0x33, "#ASI_PCACHE_SNOOP_TAG" }, | |
| 2058 | { 0x34, "#ASI_QUAD_LDD_PHYS" }, | |
| 2059 | { 0x38, "#ASI_WCACHE_VALID_BITS" }, | |
| 2060 | { 0x39, "#ASI_WCACHE_DATA" }, | |
| 2061 | { 0x3a, "#ASI_WCACHE_TAG" }, | |
| 2062 | { 0x3b, "#ASI_WCACHE_SNOOP_TAG" }, | |
| 2063 | { 0x3c, "#ASI_QUAD_LDD_PHYS_L" }, | |
| 2064 | { 0x40, "#ASI_SRAM_FAST_INIT" }, | |
| 2065 | { 0x41, "#ASI_CORE_AVAILABLE" }, | |
| 2066 | { 0x41, "#ASI_CORE_ENABLE_STAT" }, | |
| 2067 | { 0x41, "#ASI_CORE_ENABLE" }, | |
| 2068 | { 0x41, "#ASI_XIR_STEERING" }, | |
| 2069 | { 0x41, "#ASI_CORE_RUNNING_RW" }, | |
| 2070 | { 0x41, "#ASI_CORE_RUNNING_W1S" }, | |
| 2071 | { 0x41, "#ASI_CORE_RUNNING_W1C" }, | |
| 2072 | { 0x41, "#ASI_CORE_RUNNING_STAT" }, | |
| 2073 | { 0x41, "#ASI_CMT_ERROR_STEERING" }, | |
| 2074 | { 0x41, "#ASI_DCACHE_INVALIDATE" }, | |
| 2075 | { 0x41, "#ASI_DCACHE_UTAG" }, | |
| 2076 | { 0x41, "#ASI_DCACHE_SNOOP_TAG" }, | |
| 2077 | { 0x42, "#ASI_DCACHE_INVALIDATE" }, | |
| 2078 | { 0x43, "#ASI_DCACHE_UTAG" }, | |
| 2079 | { 0x44, "#ASI_DCACHE_SNOOP_TAG" }, | |
| 2080 | { 0x45, "#ASI_LSU_CONTROL_REG" }, | |
| 2081 | { 0x45, "#ASI_DCU_CONTROL_REG" }, | |
| 2082 | { 0x46, "#ASI_DCACHE_DATA" }, | |
| 2083 | { 0x47, "#ASI_DCACHE_TAG" }, | |
| 2084 | { 0x48, "#ASI_INTR_DISPATCH_STAT" }, | |
| 2085 | { 0x49, "#ASI_INTR_RECEIVE" }, | |
| 2086 | { 0x4a, "#ASI_UPA_CONFIG" }, | |
| 2087 | { 0x4a, "#ASI_JBUS_CONFIG" }, | |
| 2088 | { 0x4a, "#ASI_SAFARI_CONFIG" }, | |
| 2089 | { 0x4a, "#ASI_SAFARI_ADDRESS" }, | |
| 2090 | { 0x4b, "#ASI_ESTATE_ERROR_EN" }, | |
| 2091 | { 0x4c, "#ASI_AFSR" }, | |
| 2092 | { 0x4d, "#ASI_AFAR" }, | |
| 2093 | { 0x4e, "#ASI_EC_TAG_DATA" }, | |
| 2094 | { 0x50, "#ASI_IMMU" }, | |
| 2095 | { 0x51, "#ASI_IMMU_TSB_8KB_PTR" }, | |
| 2096 | { 0x52, "#ASI_IMMU_TSB_16KB_PTR" }, | |
| 2097 | { 0x54, "#ASI_ITLB_DATA_IN" }, | |
| 2098 | { 0x55, "#ASI_ITLB_DATA_ACCESS" }, | |
| 2099 | { 0x56, "#ASI_ITLB_TAG_READ" }, | |
| 2100 | { 0x57, "#ASI_IMMU_DEMAP" }, | |
| 2101 | { 0x58, "#ASI_DMMU" }, | |
| 2102 | { 0x59, "#ASI_DMMU_TSB_8KB_PTR" }, | |
| 2103 | { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" }, | |
| 2104 | { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" }, | |
| 2105 | { 0x5c, "#ASI_DTLB_DATA_IN" }, | |
| 2106 | { 0x5d, "#ASI_DTLB_DATA_ACCESS" }, | |
| 2107 | { 0x5e, "#ASI_DTLB_TAG_READ" }, | |
| 2108 | { 0x5f, "#ASI_DMMU_DEMAP" }, | |
| 2109 | { 0x60, "#ASI_IIU_INST_TRAP" }, | |
| 2110 | { 0x63, "#ASI_INTR_ID" }, | |
| 2111 | { 0x63, "#ASI_CORE_ID" }, | |
| 2112 | { 0x63, "#ASI_CESR_ID" }, | |
| 2113 | { 0x66, "#ASI_IC_INSTR" }, | |
| 2114 | { 0x67, "#ASI_IC_TAG" }, | |
| 2115 | { 0x68, "#ASI_IC_STAG" }, | |
| 2116 | { 0x6e, "#ASI_IC_PRE_DECODE" }, | |
| 2117 | { 0x6f, "#ASI_IC_NEXT_FIELD" }, | |
| 2118 | { 0x6f, "#ASI_BRPRED_ARRAY" }, | |
| 2119 | { 0x70, "#ASI_BLK_AIUP" }, | |
| 2120 | { 0x71, "#ASI_BLK_AIUS" }, | |
| 2121 | { 0x72, "#ASI_MCU_CTRL_REG" }, | |
| 2122 | { 0x74, "#ASI_EC_DATA" }, | |
| 2123 | { 0x75, "#ASI_EC_CTRL" }, | |
| 2124 | { 0x76, "#ASI_EC_W" }, | |
| 2125 | { 0x77, "#ASI_UDB_ERROR_W" }, | |
| 2126 | { 0x77, "#ASI_UDB_CONTROL_W" }, | |
| 2127 | { 0x77, "#ASI_INTR_W" }, | |
| 2128 | { 0x77, "#ASI_INTR_DATAN_W" }, | |
| 2129 | { 0x77, "#ASI_INTR_DISPATCH_W" }, | |
| 2130 | { 0x78, "#ASI_BLK_AIUPL" }, | |
| 2131 | { 0x79, "#ASI_BLK_AIUSL" }, | |
| 2132 | { 0x7e, "#ASI_EC_R" }, | |
| 2133 | { 0x7f, "#ASI_UDBH_ERROR_R" }, | |
| 2134 | { 0x7f, "#ASI_UDBL_ERROR_R" }, | |
| 2135 | { 0x7f, "#ASI_UDBH_CONTROL_R" }, | |
| 2136 | { 0x7f, "#ASI_UDBL_CONTROL_R" }, | |
| 2137 | { 0x7f, "#ASI_INTR_R" }, | |
| 2138 | { 0x7f, "#ASI_INTR_DATAN_R" }, | |
| 2139 | { 0xc0, "#ASI_PST8_P" }, | |
| 2140 | { 0xc1, "#ASI_PST8_S" }, | |
| 2141 | { 0xc2, "#ASI_PST16_P" }, | |
| 2142 | { 0xc3, "#ASI_PST16_S" }, | |
| 2143 | { 0xc4, "#ASI_PST32_P" }, | |
| 2144 | { 0xc5, "#ASI_PST32_S" }, | |
| 2145 | { 0xc8, "#ASI_PST8_PL" }, | |
| 2146 | { 0xc9, "#ASI_PST8_SL" }, | |
| 2147 | { 0xca, "#ASI_PST16_PL" }, | |
| 2148 | { 0xcb, "#ASI_PST16_SL" }, | |
| 2149 | { 0xcc, "#ASI_PST32_PL" }, | |
| 2150 | { 0xcd, "#ASI_PST32_SL" }, | |
| 2151 | { 0xd0, "#ASI_FL8_P" }, | |
| 2152 | { 0xd1, "#ASI_FL8_S" }, | |
| 2153 | { 0xd2, "#ASI_FL16_P" }, | |
| 2154 | { 0xd3, "#ASI_FL16_S" }, | |
| 2155 | { 0xd8, "#ASI_FL8_PL" }, | |
| 2156 | { 0xd9, "#ASI_FL8_SL" }, | |
| 2157 | { 0xda, "#ASI_FL16_PL" }, | |
| 2158 | { 0xdb, "#ASI_FL16_SL" }, | |
| 2159 | { 0xe0, "#ASI_BLK_COMMIT_P", }, | |
| 2160 | { 0xe1, "#ASI_BLK_COMMIT_S", }, | |
| 2161 | { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" }, | |
| 2162 | { 0xf0, "#ASI_BLK_P", }, | |
| 2163 | { 0xf1, "#ASI_BLK_S", }, | |
| 2164 | { 0xf8, "#ASI_BLK_PL", }, | |
| 2165 | { 0xf9, "#ASI_BLK_SL", }, | |
| 252b5132 RH |
2166 | { 0, 0 } |
| 2167 | }; | |
| 2168 | ||
| 2169 | /* Return the value for ASI NAME, or -1 if not found. */ | |
| 2170 | ||
| 2171 | int | |
| 47b0e7ad | 2172 | sparc_encode_asi (const char *name) |
| 252b5132 RH |
2173 | { |
| 2174 | return lookup_name (asi_table, name); | |
| 2175 | } | |
| 2176 | ||
| 2177 | /* Return the name for ASI value VALUE or NULL if not found. */ | |
| 2178 | ||
| 2179 | const char * | |
| 47b0e7ad | 2180 | sparc_decode_asi (int value) |
| 252b5132 RH |
2181 | { |
| 2182 | return lookup_value (asi_table, value); | |
| 2183 | } | |
| 2184 | \f | |
| 2185 | /* Handle membar masks. */ | |
| 2186 | ||
| 2187 | static arg membar_table[] = | |
| 2188 | { | |
| 2189 | { 0x40, "#Sync" }, | |
| 2190 | { 0x20, "#MemIssue" }, | |
| 2191 | { 0x10, "#Lookaside" }, | |
| 2192 | { 0x08, "#StoreStore" }, | |
| 2193 | { 0x04, "#LoadStore" }, | |
| 2194 | { 0x02, "#StoreLoad" }, | |
| 2195 | { 0x01, "#LoadLoad" }, | |
| 2196 | { 0, 0 } | |
| 2197 | }; | |
| 2198 | ||
| 2199 | /* Return the value for membar arg NAME, or -1 if not found. */ | |
| 2200 | ||
| 2201 | int | |
| 47b0e7ad | 2202 | sparc_encode_membar (const char *name) |
| 252b5132 RH |
2203 | { |
| 2204 | return lookup_name (membar_table, name); | |
| 2205 | } | |
| 2206 | ||
| 2207 | /* Return the name for membar value VALUE or NULL if not found. */ | |
| 2208 | ||
| 2209 | const char * | |
| 47b0e7ad | 2210 | sparc_decode_membar (int value) |
| 252b5132 RH |
2211 | { |
| 2212 | return lookup_value (membar_table, value); | |
| 2213 | } | |
| 2214 | \f | |
| 2215 | /* Handle prefetch args. */ | |
| 2216 | ||
| 2217 | static arg prefetch_table[] = | |
| 2218 | { | |
| 2219 | { 0, "#n_reads" }, | |
| 2220 | { 1, "#one_read" }, | |
| 2221 | { 2, "#n_writes" }, | |
| 2222 | { 3, "#one_write" }, | |
| 2223 | { 4, "#page" }, | |
| 19f7b010 | 2224 | { 16, "#invalidate" }, |
| 1a6b486f DM |
2225 | { 17, "#unified", }, |
| 2226 | { 20, "#n_reads_strong", }, | |
| 2227 | { 21, "#one_read_strong", }, | |
| 2228 | { 22, "#n_writes_strong", }, | |
| 2229 | { 23, "#one_write_strong", }, | |
| 252b5132 RH |
2230 | { 0, 0 } |
| 2231 | }; | |
| 2232 | ||
| 2233 | /* Return the value for prefetch arg NAME, or -1 if not found. */ | |
| 2234 | ||
| 2235 | int | |
| 47b0e7ad | 2236 | sparc_encode_prefetch (const char *name) |
| 252b5132 RH |
2237 | { |
| 2238 | return lookup_name (prefetch_table, name); | |
| 2239 | } | |
| 2240 | ||
| 2241 | /* Return the name for prefetch value VALUE or NULL if not found. */ | |
| 2242 | ||
| 2243 | const char * | |
| 47b0e7ad | 2244 | sparc_decode_prefetch (int value) |
| 252b5132 RH |
2245 | { |
| 2246 | return lookup_value (prefetch_table, value); | |
| 2247 | } | |
| 2248 | \f | |
| 2249 | /* Handle sparclet coprocessor registers. */ | |
| 2250 | ||
| 2251 | static arg sparclet_cpreg_table[] = | |
| 2252 | { | |
| 2253 | { 0, "%ccsr" }, | |
| 2254 | { 1, "%ccfr" }, | |
| 2255 | { 2, "%cccrcr" }, | |
| 2256 | { 3, "%ccpr" }, | |
| 2257 | { 4, "%ccsr2" }, | |
| 2258 | { 5, "%cccrr" }, | |
| 2259 | { 6, "%ccrstr" }, | |
| 2260 | { 0, 0 } | |
| 2261 | }; | |
| 2262 | ||
| 2263 | /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ | |
| 2264 | ||
| 2265 | int | |
| 47b0e7ad | 2266 | sparc_encode_sparclet_cpreg (const char *name) |
| 252b5132 RH |
2267 | { |
| 2268 | return lookup_name (sparclet_cpreg_table, name); | |
| 2269 | } | |
| 2270 | ||
| 2271 | /* Return the name for sparclet cpreg value VALUE or NULL if not found. */ | |
| 2272 | ||
| 2273 | const char * | |
| 47b0e7ad | 2274 | sparc_decode_sparclet_cpreg (int value) |
| 252b5132 RH |
2275 | { |
| 2276 | return lookup_value (sparclet_cpreg_table, value); | |
| 2277 | } |