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252b5132 | 1 | /* Disassembly routines for TMS320C30 architecture |
47b0e7ad | 2 | Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
f4321104 NC |
17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
18 | 02110-1301, USA. */ | |
252b5132 RH |
19 | |
20 | #include <errno.h> | |
21 | #include <math.h> | |
6094e721 | 22 | #include "sysdep.h" |
252b5132 RH |
23 | #include "dis-asm.h" |
24 | #include "opcode/tic30.h" | |
25 | ||
26 | #define NORMAL_INSN 1 | |
27 | #define PARALLEL_INSN 2 | |
28 | ||
29 | /* Gets the type of instruction based on the top 2 or 3 bits of the | |
bf830eae | 30 | instruction word. */ |
252b5132 RH |
31 | #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) |
32 | ||
bf830eae | 33 | /* Instruction types. */ |
252b5132 RH |
34 | #define TWO_OPERAND_1 0x00000000 |
35 | #define TWO_OPERAND_2 0x40000000 | |
36 | #define THREE_OPERAND 0x20000000 | |
37 | #define PAR_STORE 0xC0000000 | |
38 | #define MUL_ADDS 0x80000000 | |
39 | #define BRANCHES 0x60000000 | |
40 | ||
bf830eae | 41 | /* Specific instruction id bits. */ |
252b5132 RH |
42 | #define NORMAL_IDEN 0x1F800000 |
43 | #define PAR_STORE_IDEN 0x3E000000 | |
44 | #define MUL_ADD_IDEN 0x2C000000 | |
45 | #define BR_IMM_IDEN 0x1F000000 | |
46 | #define BR_COND_IDEN 0x1C3F0000 | |
47 | ||
bf830eae | 48 | /* Addressing modes. */ |
252b5132 RH |
49 | #define AM_REGISTER 0x00000000 |
50 | #define AM_DIRECT 0x00200000 | |
51 | #define AM_INDIRECT 0x00400000 | |
52 | #define AM_IMM 0x00600000 | |
53 | ||
54 | #define P_FIELD 0x03000000 | |
55 | ||
56 | #define REG_AR0 0x08 | |
57 | #define LDP_INSN 0x08700000 | |
58 | ||
bf830eae | 59 | /* TMS320C30 program counter for current instruction. */ |
252b5132 RH |
60 | static unsigned int _pc; |
61 | ||
62 | struct instruction | |
bf830eae KH |
63 | { |
64 | int type; | |
65 | template *tm; | |
66 | partemplate *ptm; | |
67 | }; | |
252b5132 | 68 | |
47b0e7ad NC |
69 | static int |
70 | get_tic30_instruction (unsigned long insn_word, struct instruction *insn) | |
252b5132 RH |
71 | { |
72 | switch (GET_TYPE (insn_word)) | |
73 | { | |
74 | case TWO_OPERAND_1: | |
75 | case TWO_OPERAND_2: | |
76 | case THREE_OPERAND: | |
77 | insn->type = NORMAL_INSN; | |
78 | { | |
79 | template *current_optab = (template *) tic30_optab; | |
47b0e7ad | 80 | |
252b5132 RH |
81 | for (; current_optab < tic30_optab_end; current_optab++) |
82 | { | |
83 | if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) | |
84 | { | |
85 | if (current_optab->operands == 0) | |
86 | { | |
87 | if (current_optab->base_opcode == insn_word) | |
88 | { | |
89 | insn->tm = current_optab; | |
90 | break; | |
91 | } | |
92 | } | |
93 | else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN)) | |
94 | { | |
95 | insn->tm = current_optab; | |
96 | break; | |
97 | } | |
98 | } | |
99 | } | |
100 | } | |
101 | break; | |
47b0e7ad | 102 | |
252b5132 RH |
103 | case PAR_STORE: |
104 | insn->type = PARALLEL_INSN; | |
105 | { | |
106 | partemplate *current_optab = (partemplate *) tic30_paroptab; | |
47b0e7ad | 107 | |
252b5132 RH |
108 | for (; current_optab < tic30_paroptab_end; current_optab++) |
109 | { | |
110 | if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) | |
111 | { | |
47b0e7ad NC |
112 | if ((current_optab->base_opcode & PAR_STORE_IDEN) |
113 | == (insn_word & PAR_STORE_IDEN)) | |
252b5132 RH |
114 | { |
115 | insn->ptm = current_optab; | |
116 | break; | |
117 | } | |
118 | } | |
119 | } | |
120 | } | |
121 | break; | |
47b0e7ad | 122 | |
252b5132 RH |
123 | case MUL_ADDS: |
124 | insn->type = PARALLEL_INSN; | |
125 | { | |
126 | partemplate *current_optab = (partemplate *) tic30_paroptab; | |
47b0e7ad | 127 | |
252b5132 RH |
128 | for (; current_optab < tic30_paroptab_end; current_optab++) |
129 | { | |
130 | if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) | |
131 | { | |
47b0e7ad NC |
132 | if ((current_optab->base_opcode & MUL_ADD_IDEN) |
133 | == (insn_word & MUL_ADD_IDEN)) | |
252b5132 RH |
134 | { |
135 | insn->ptm = current_optab; | |
136 | break; | |
137 | } | |
138 | } | |
139 | } | |
140 | } | |
141 | break; | |
47b0e7ad | 142 | |
252b5132 RH |
143 | case BRANCHES: |
144 | insn->type = NORMAL_INSN; | |
145 | { | |
146 | template *current_optab = (template *) tic30_optab; | |
47b0e7ad | 147 | |
252b5132 RH |
148 | for (; current_optab < tic30_optab_end; current_optab++) |
149 | { | |
150 | if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) | |
151 | { | |
152 | if (current_optab->operand_types[0] & Imm24) | |
153 | { | |
47b0e7ad NC |
154 | if ((current_optab->base_opcode & BR_IMM_IDEN) |
155 | == (insn_word & BR_IMM_IDEN)) | |
252b5132 RH |
156 | { |
157 | insn->tm = current_optab; | |
158 | break; | |
159 | } | |
160 | } | |
161 | else if (current_optab->operands > 0) | |
162 | { | |
47b0e7ad NC |
163 | if ((current_optab->base_opcode & BR_COND_IDEN) |
164 | == (insn_word & BR_COND_IDEN)) | |
252b5132 RH |
165 | { |
166 | insn->tm = current_optab; | |
167 | break; | |
168 | } | |
169 | } | |
170 | else | |
171 | { | |
47b0e7ad NC |
172 | if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) |
173 | == (insn_word & (BR_COND_IDEN | 0x00800000))) | |
252b5132 RH |
174 | { |
175 | insn->tm = current_optab; | |
176 | break; | |
177 | } | |
178 | } | |
179 | } | |
180 | } | |
181 | } | |
182 | break; | |
183 | default: | |
184 | return 0; | |
185 | } | |
186 | return 1; | |
187 | } | |
188 | ||
47b0e7ad NC |
189 | static int |
190 | get_register_operand (unsigned char fragment, char *buffer) | |
191 | { | |
192 | const reg *current_reg = tic30_regtab; | |
193 | ||
194 | if (buffer == NULL) | |
195 | return 0; | |
196 | for (; current_reg < tic30_regtab_end; current_reg++) | |
197 | { | |
198 | if ((fragment & 0x1F) == current_reg->opcode) | |
199 | { | |
200 | strcpy (buffer, current_reg->name); | |
201 | return 1; | |
202 | } | |
203 | } | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static int | |
208 | get_indirect_operand (unsigned short fragment, | |
209 | int size, | |
210 | char *buffer) | |
211 | { | |
212 | unsigned char mod; | |
213 | unsigned arnum; | |
214 | unsigned char disp; | |
215 | ||
216 | if (buffer == NULL) | |
217 | return 0; | |
218 | /* Determine which bits identify the sections of the indirect | |
219 | operand based on the size in bytes. */ | |
220 | switch (size) | |
221 | { | |
222 | case 1: | |
223 | mod = (fragment & 0x00F8) >> 3; | |
224 | arnum = (fragment & 0x0007); | |
225 | disp = 0; | |
226 | break; | |
227 | case 2: | |
228 | mod = (fragment & 0xF800) >> 11; | |
229 | arnum = (fragment & 0x0700) >> 8; | |
230 | disp = (fragment & 0x00FF); | |
231 | break; | |
232 | default: | |
233 | return 0; | |
234 | } | |
235 | { | |
236 | const ind_addr_type *current_ind = tic30_indaddr_tab; | |
237 | ||
238 | for (; current_ind < tic30_indaddrtab_end; current_ind++) | |
239 | { | |
240 | if (current_ind->modfield == mod) | |
241 | { | |
242 | if (current_ind->displacement == IMPLIED_DISP && size == 2) | |
243 | continue; | |
244 | ||
245 | else | |
246 | { | |
247 | size_t i, len; | |
248 | int bufcnt; | |
249 | ||
250 | len = strlen (current_ind->syntax); | |
251 | for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) | |
252 | { | |
253 | buffer[bufcnt] = current_ind->syntax[i]; | |
254 | if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') | |
255 | buffer[++bufcnt] = arnum + '0'; | |
256 | if (buffer[bufcnt] == '(' | |
257 | && current_ind->displacement == DISP_REQUIRED) | |
258 | { | |
259 | sprintf (&buffer[bufcnt + 1], "%u", disp); | |
260 | bufcnt += strlen (&buffer[bufcnt + 1]); | |
261 | } | |
262 | } | |
263 | buffer[bufcnt + 1] = '\0'; | |
264 | break; | |
265 | } | |
266 | } | |
267 | } | |
268 | } | |
269 | return 1; | |
270 | } | |
271 | ||
272 | static int | |
273 | cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat) | |
274 | { | |
275 | unsigned long exp, sign, mant; | |
276 | union | |
277 | { | |
278 | unsigned long l; | |
279 | float f; | |
280 | } val; | |
281 | ||
282 | if (size == 2) | |
283 | { | |
284 | if ((tmsfloat & 0x0000F000) == 0x00008000) | |
285 | tmsfloat = 0x80000000; | |
286 | else | |
287 | { | |
288 | tmsfloat <<= 16; | |
289 | tmsfloat = (long) tmsfloat >> 4; | |
290 | } | |
291 | } | |
292 | exp = tmsfloat & 0xFF000000; | |
293 | if (exp == 0x80000000) | |
294 | { | |
295 | *ieeefloat = 0.0; | |
296 | return 1; | |
297 | } | |
298 | exp += 0x7F000000; | |
299 | sign = (tmsfloat & 0x00800000) << 8; | |
300 | mant = tmsfloat & 0x007FFFFF; | |
301 | if (exp == 0xFF000000) | |
302 | { | |
303 | if (mant == 0) | |
304 | *ieeefloat = ERANGE; | |
305 | if (sign == 0) | |
306 | *ieeefloat = 1.0 / 0.0; | |
307 | else | |
308 | *ieeefloat = -1.0 / 0.0; | |
309 | return 1; | |
310 | } | |
311 | exp >>= 1; | |
312 | if (sign) | |
313 | { | |
314 | mant = (~mant) & 0x007FFFFF; | |
315 | mant += 1; | |
316 | exp += mant & 0x00800000; | |
317 | exp &= 0x7F800000; | |
318 | mant &= 0x007FFFFF; | |
319 | } | |
320 | if (tmsfloat == 0x80000000) | |
321 | sign = mant = exp = 0; | |
322 | tmsfloat = sign | exp | mant; | |
323 | val.l = tmsfloat; | |
324 | *ieeefloat = val.f; | |
325 | return 1; | |
326 | } | |
327 | ||
328 | static int | |
329 | print_two_operand (disassemble_info *info, | |
330 | unsigned long insn_word, | |
331 | struct instruction *insn) | |
252b5132 RH |
332 | { |
333 | char name[12]; | |
334 | char operand[2][13] = | |
335 | { | |
336 | {0}, | |
47b0e7ad NC |
337 | {0} |
338 | }; | |
252b5132 RH |
339 | float f_number; |
340 | ||
341 | if (insn->tm == NULL) | |
342 | return 0; | |
343 | strcpy (name, insn->tm->name); | |
344 | if (insn->tm->opcode_modifier == AddressMode) | |
345 | { | |
346 | int src_op, dest_op; | |
bf830eae | 347 | /* Determine whether instruction is a store or a normal instruction. */ |
47b0e7ad NC |
348 | if ((insn->tm->operand_types[1] & (Direct | Indirect)) |
349 | == (Direct | Indirect)) | |
252b5132 RH |
350 | { |
351 | src_op = 1; | |
352 | dest_op = 0; | |
353 | } | |
354 | else | |
355 | { | |
356 | src_op = 0; | |
357 | dest_op = 1; | |
358 | } | |
bf830eae | 359 | /* Get the destination register. */ |
252b5132 RH |
360 | if (insn->tm->operands == 2) |
361 | get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); | |
bf830eae | 362 | /* Get the source operand based on addressing mode. */ |
252b5132 RH |
363 | switch (insn_word & AddressMode) |
364 | { | |
365 | case AM_REGISTER: | |
bf830eae | 366 | /* Check for the NOP instruction before getting the operand. */ |
252b5132 RH |
367 | if ((insn->tm->operand_types[0] & NotReq) == 0) |
368 | get_register_operand ((insn_word & 0x0000001F), operand[src_op]); | |
369 | break; | |
370 | case AM_DIRECT: | |
371 | sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF)); | |
372 | break; | |
373 | case AM_INDIRECT: | |
374 | get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); | |
375 | break; | |
376 | case AM_IMM: | |
bf830eae | 377 | /* Get the value of the immediate operand based on variable type. */ |
252b5132 RH |
378 | switch (insn->tm->imm_arg_type) |
379 | { | |
380 | case Imm_Float: | |
381 | cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number); | |
382 | sprintf (operand[src_op], "%2.2f", f_number); | |
383 | break; | |
384 | case Imm_SInt: | |
385 | sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF)); | |
386 | break; | |
387 | case Imm_UInt: | |
388 | sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF)); | |
389 | break; | |
390 | default: | |
391 | return 0; | |
392 | } | |
bf830eae | 393 | /* Handle special case for LDP instruction. */ |
252b5132 RH |
394 | if ((insn_word & 0xFFFFFF00) == LDP_INSN) |
395 | { | |
396 | strcpy (name, "ldp"); | |
397 | sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16); | |
398 | operand[1][0] = '\0'; | |
399 | } | |
400 | } | |
401 | } | |
bf830eae | 402 | /* Handle case for stack and rotate instructions. */ |
252b5132 RH |
403 | else if (insn->tm->operands == 1) |
404 | { | |
405 | if (insn->tm->opcode_modifier == StackOp) | |
47b0e7ad | 406 | get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); |
252b5132 | 407 | } |
bf830eae | 408 | /* Output instruction to stream. */ |
252b5132 RH |
409 | info->fprintf_func (info->stream, " %s %s%c%s", name, |
410 | operand[0][0] ? operand[0] : "", | |
411 | operand[1][0] ? ',' : ' ', | |
412 | operand[1][0] ? operand[1] : ""); | |
413 | return 1; | |
414 | } | |
415 | ||
47b0e7ad NC |
416 | static int |
417 | print_three_operand (disassemble_info *info, | |
418 | unsigned long insn_word, | |
419 | struct instruction *insn) | |
252b5132 RH |
420 | { |
421 | char operand[3][13] = | |
422 | { | |
423 | {0}, | |
424 | {0}, | |
47b0e7ad NC |
425 | {0} |
426 | }; | |
252b5132 RH |
427 | |
428 | if (insn->tm == NULL) | |
429 | return 0; | |
430 | switch (insn_word & AddressMode) | |
431 | { | |
432 | case AM_REGISTER: | |
433 | get_register_operand ((insn_word & 0x000000FF), operand[0]); | |
434 | get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); | |
435 | break; | |
436 | case AM_DIRECT: | |
437 | get_register_operand ((insn_word & 0x000000FF), operand[0]); | |
438 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); | |
439 | break; | |
440 | case AM_INDIRECT: | |
441 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); | |
442 | get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); | |
443 | break; | |
444 | case AM_IMM: | |
445 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); | |
446 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); | |
447 | break; | |
448 | default: | |
449 | return 0; | |
450 | } | |
451 | if (insn->tm->operands == 3) | |
452 | get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]); | |
453 | info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name, | |
454 | operand[0], operand[1], | |
455 | operand[2][0] ? ',' : ' ', | |
456 | operand[2][0] ? operand[2] : ""); | |
457 | return 1; | |
458 | } | |
459 | ||
47b0e7ad NC |
460 | static int |
461 | print_par_insn (disassemble_info *info, | |
462 | unsigned long insn_word, | |
463 | struct instruction *insn) | |
252b5132 RH |
464 | { |
465 | size_t i, len; | |
466 | char *name1, *name2; | |
467 | char operand[2][3][13] = | |
468 | { | |
469 | { | |
470 | {0}, | |
471 | {0}, | |
47b0e7ad NC |
472 | {0} |
473 | }, | |
252b5132 RH |
474 | { |
475 | {0}, | |
476 | {0}, | |
47b0e7ad NC |
477 | {0} |
478 | } | |
479 | }; | |
252b5132 RH |
480 | |
481 | if (insn->ptm == NULL) | |
482 | return 0; | |
483 | /* Parse out the names of each of the parallel instructions from the | |
bf830eae | 484 | q_insn1_insn2 format. */ |
252b5132 RH |
485 | name1 = (char *) strdup (insn->ptm->name + 2); |
486 | name2 = ""; | |
487 | len = strlen (name1); | |
488 | for (i = 0; i < len; i++) | |
489 | { | |
490 | if (name1[i] == '_') | |
491 | { | |
492 | name2 = &name1[i + 1]; | |
493 | name1[i] = '\0'; | |
494 | break; | |
495 | } | |
496 | } | |
bf830eae | 497 | /* Get the operands of the instruction based on the operand order. */ |
252b5132 RH |
498 | switch (insn->ptm->oporder) |
499 | { | |
500 | case OO_4op1: | |
501 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); | |
502 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); | |
503 | get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); | |
504 | get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); | |
505 | break; | |
506 | case OO_4op2: | |
507 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); | |
508 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); | |
509 | get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]); | |
510 | get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); | |
511 | break; | |
512 | case OO_4op3: | |
513 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); | |
514 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); | |
515 | get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); | |
516 | get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]); | |
517 | break; | |
518 | case OO_5op1: | |
519 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); | |
520 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); | |
521 | get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); | |
522 | get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); | |
523 | get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); | |
524 | break; | |
525 | case OO_5op2: | |
526 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); | |
527 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); | |
528 | get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); | |
529 | get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); | |
530 | get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); | |
531 | break; | |
532 | case OO_PField: | |
533 | if (insn_word & 0x00800000) | |
534 | get_register_operand (0x01, operand[0][2]); | |
535 | else | |
536 | get_register_operand (0x00, operand[0][2]); | |
537 | if (insn_word & 0x00400000) | |
538 | get_register_operand (0x03, operand[1][2]); | |
539 | else | |
540 | get_register_operand (0x02, operand[1][2]); | |
541 | switch (insn_word & P_FIELD) | |
542 | { | |
543 | case 0x00000000: | |
544 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); | |
545 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); | |
546 | get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); | |
547 | get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]); | |
548 | break; | |
549 | case 0x01000000: | |
550 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]); | |
551 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); | |
552 | get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); | |
553 | get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); | |
554 | break; | |
555 | case 0x02000000: | |
556 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); | |
557 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); | |
558 | get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]); | |
559 | get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); | |
560 | break; | |
561 | case 0x03000000: | |
562 | get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); | |
563 | get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); | |
564 | get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); | |
565 | get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); | |
566 | break; | |
567 | } | |
568 | break; | |
569 | default: | |
570 | return 0; | |
571 | } | |
572 | info->fprintf_func (info->stream, " %s %s,%s%c%s", name1, | |
573 | operand[0][0], operand[0][1], | |
574 | operand[0][2][0] ? ',' : ' ', | |
575 | operand[0][2][0] ? operand[0][2] : ""); | |
576 | info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2, | |
577 | operand[1][0], operand[1][1], | |
578 | operand[1][2][0] ? ',' : ' ', | |
579 | operand[1][2][0] ? operand[1][2] : ""); | |
580 | free (name1); | |
581 | return 1; | |
582 | } | |
583 | ||
47b0e7ad NC |
584 | static int |
585 | print_branch (disassemble_info *info, | |
586 | unsigned long insn_word, | |
587 | struct instruction *insn) | |
252b5132 RH |
588 | { |
589 | char operand[2][13] = | |
590 | { | |
591 | {0}, | |
47b0e7ad NC |
592 | {0} |
593 | }; | |
252b5132 RH |
594 | unsigned long address; |
595 | int print_label = 0; | |
596 | ||
597 | if (insn->tm == NULL) | |
598 | return 0; | |
bf830eae | 599 | /* Get the operands for 24-bit immediate jumps. */ |
252b5132 RH |
600 | if (insn->tm->operand_types[0] & Imm24) |
601 | { | |
602 | address = insn_word & 0x00FFFFFF; | |
603 | sprintf (operand[0], "0x%lX", address); | |
604 | print_label = 1; | |
605 | } | |
bf830eae | 606 | /* Get the operand for the trap instruction. */ |
252b5132 RH |
607 | else if (insn->tm->operand_types[0] & IVector) |
608 | { | |
609 | address = insn_word & 0x0000001F; | |
610 | sprintf (operand[0], "0x%lX", address); | |
611 | } | |
612 | else | |
613 | { | |
614 | address = insn_word & 0x0000FFFF; | |
bf830eae | 615 | /* Get the operands for the DB instructions. */ |
252b5132 RH |
616 | if (insn->tm->operands == 2) |
617 | { | |
618 | get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); | |
619 | if (insn_word & PCRel) | |
620 | { | |
621 | sprintf (operand[1], "%d", (short) address); | |
622 | print_label = 1; | |
623 | } | |
624 | else | |
625 | get_register_operand (insn_word & 0x0000001F, operand[1]); | |
626 | } | |
bf830eae | 627 | /* Get the operands for the standard branches. */ |
252b5132 RH |
628 | else if (insn->tm->operands == 1) |
629 | { | |
630 | if (insn_word & PCRel) | |
631 | { | |
632 | address = (short) address; | |
633 | sprintf (operand[0], "%ld", address); | |
634 | print_label = 1; | |
635 | } | |
636 | else | |
637 | get_register_operand (insn_word & 0x0000001F, operand[0]); | |
638 | } | |
639 | } | |
640 | info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name, | |
641 | operand[0][0] ? operand[0] : "", | |
642 | operand[1][0] ? ',' : ' ', | |
643 | operand[1][0] ? operand[1] : ""); | |
bf830eae | 644 | /* Print destination of branch in relation to current symbol. */ |
252b5132 RH |
645 | if (print_label && info->symbols) |
646 | { | |
647 | asymbol *sym = *info->symbols; | |
648 | ||
649 | if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) | |
650 | { | |
651 | address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4); | |
bf830eae | 652 | /* Check for delayed instruction, if so adjust destination. */ |
252b5132 RH |
653 | if (insn_word & 0x00200000) |
654 | address += 2; | |
655 | } | |
656 | else | |
657 | { | |
658 | address -= ((sym->section->vma + sym->value) / 4); | |
659 | } | |
660 | if (address == 0) | |
661 | info->fprintf_func (info->stream, " <%s>", sym->name); | |
662 | else | |
663 | info->fprintf_func (info->stream, " <%s %c %d>", sym->name, | |
664 | ((short) address < 0) ? '-' : '+', | |
665 | abs (address)); | |
666 | } | |
667 | return 1; | |
668 | } | |
669 | ||
670 | int | |
47b0e7ad | 671 | print_insn_tic30 (bfd_vma pc, disassemble_info *info) |
252b5132 | 672 | { |
47b0e7ad NC |
673 | unsigned long insn_word; |
674 | struct instruction insn = { 0, NULL, NULL }; | |
675 | bfd_vma bufaddr = pc - info->buffer_vma; | |
252b5132 | 676 | |
47b0e7ad NC |
677 | /* Obtain the current instruction word from the buffer. */ |
678 | insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | | |
679 | (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); | |
680 | _pc = pc / 4; | |
681 | /* Get the instruction refered to by the current instruction word | |
682 | and print it out based on its type. */ | |
683 | if (!get_tic30_instruction (insn_word, &insn)) | |
684 | return -1; | |
685 | switch (GET_TYPE (insn_word)) | |
252b5132 | 686 | { |
47b0e7ad NC |
687 | case TWO_OPERAND_1: |
688 | case TWO_OPERAND_2: | |
689 | if (!print_two_operand (info, insn_word, &insn)) | |
690 | return -1; | |
252b5132 | 691 | break; |
47b0e7ad NC |
692 | case THREE_OPERAND: |
693 | if (!print_three_operand (info, insn_word, &insn)) | |
694 | return -1; | |
695 | break; | |
696 | case PAR_STORE: | |
697 | case MUL_ADDS: | |
698 | if (!print_par_insn (info, insn_word, &insn)) | |
699 | return -1; | |
700 | break; | |
701 | case BRANCHES: | |
702 | if (!print_branch (info, insn_word, &insn)) | |
703 | return -1; | |
252b5132 | 704 | break; |
252b5132 | 705 | } |
47b0e7ad | 706 | return 4; |
252b5132 | 707 | } |