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* tic80.h (struct tic80_opcode): Change "format" field to "flags".
[deliverable/binutils-gdb.git] / opcodes / tic80-opc.c
CommitLineData
6357e7f6
FF		 1/* Opcode table for TI TMS320C80 (MVP).
2 Copyright 1996 Free Software Foundation, Inc.
3
4This file is part of GDB, GAS, and the GNU binutils.
5
6GDB, GAS, and the GNU binutils are free software; you can redistribute
7them and/or modify them under the terms of the GNU General Public
8License as published by the Free Software Foundation; either version
91, or (at your option) any later version.
10
11GDB, GAS, and the GNU binutils are distributed in the hope that they
12will be useful, but WITHOUT ANY WARRANTY; without even the implied
13warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14the GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this file; see the file COPYING. If not, write to the Free
18Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
872dc6f0 20#include <stdio.h>
6357e7f6
FF		 21#include "ansidecl.h"
22#include "opcode/tic80.h"
872dc6f0
FF		 23
24/* This file holds the TMS320C80 (MVP) opcode table. The table is
25 strictly constant data, so the compiler should be able to put it in
26 the .text section.
27
28 This file also holds the operand table. All knowledge about
29 inserting operands into instructions and vice-versa is kept in this
30 file. */
31
32\f
33/* The operands table. The fields are:
34
35 bits, shift, insertion function, extraction function, flags
36 */
37
38const struct tic80_operand tic80_operands[] =
39{
40
41 /* The zero index is used to indicate the end of the list of operands. */
42
43#define UNUSED (0)
44 { 0, 0, 0, 0, 0 },
45
46 /* Short signed immediate value in bits 14-0. */
47
48#define SSI (UNUSED + 1)
49 { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
50
51 /* Short unsigned immediate value in bits 14-0 */
52
53#define SUI (SSI + 1)
54 { 15, 0, NULL, NULL, 0 },
55
56 /* Short unsigned bitfield in bits 14-0. We distinguish this
57 from a regular unsigned immediate value only for the convenience
58 of the disassembler and the user. */
59
60#define SUBF (SUI + 1)
61 { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
62
63 /* Long signed immediate in following 32 bit word */
64
65#define LSI (SUBF + 1)
66 { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
67
68 /* Long unsigned immediate in following 32 bit word */
69
70#define LUI (LSI + 1)
71 { 32, 0, NULL, NULL, 0 },
72
73 /* Long unsigned bitfield in following 32 bit word. We distinguish
74 this from a regular unsigned immediate value only for the
75 convenience of the disassembler and the user. */
76
77#define LUBF (LUI + 1)
78 { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
79
003df617
FF		 80 /* Single precision floating point immediate in following 32 bit
81 word. */
82
83#define SPFI (LUBF + 1)
84 { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
85
872dc6f0
FF		 86 /* Register in bits 4-0 */
87
003df617 88#define REG_0 (SPFI + 1)
872dc6f0
FF		 89 { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
90
91 /* Register in bits 26-22 */
92
50965d0e 93#define REG_22 (REG_0 + 1)
872dc6f0
FF		 94 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
95
96 /* Register in bits 31-27 */
97
50965d0e 98#define REG_DEST (REG_22 + 1)
872dc6f0
FF		 99 { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
100
5fdeceb4 101 /* Short signed PC word offset in bits 14-0 */
1f8c8c60 102
5fdeceb4
FF		 103#define OFF_SS_PC (REG_DEST + 1)
104 { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
1f8c8c60 105
5fdeceb4 106 /* Long signed PC word offset in following 32 bit word */
1f8c8c60 107
5fdeceb4
FF		 108#define OFF_SL_PC (OFF_SS_PC + 1)
109 {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
110
111 /* Short signed base relative byte offset in bits 14-0 */
112
113#define OFF_SS_BR (OFF_SL_PC + 1)
114 { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
115
116 /* Long signed base relative byte offset in following 32 bit word */
117
118#define OFF_SL_BR (OFF_SS_BR + 1)
119 {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
1f8c8c60
FF		 120
121 /* BITNUM in bits 31-27 */
122
5fdeceb4 123#define BITNUM (OFF_SL_BR + 1)
1f8c8c60
FF		 124 { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
125
126 /* Condition code in bits 31-27 */
127
128#define CC (BITNUM + 1)
129 { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
130
131 /* Control register number in bits 14-0 */
132
50965d0e 133#define CR_SI (CC + 1)
1f8c8c60
FF		 134 { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
135
136 /* Control register number in next 32 bit word */
137
50965d0e 138#define CR_LI (CR_SI + 1)
1f8c8c60
FF		 139 { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
140
5fdeceb4
FF		 141 /* A base register in bits 26-22, enclosed in parens */
142
143#define REG_BASE (CR_LI + 1)
144 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
145
50965d0e
FF		 146 /* A base register in bits 26-22, enclosed in parens, with optional ":m"
147 flag in bit 17 (short immediate instructions only) */
937fe722 148
5fdeceb4 149#define REG_BASE_M_SI (REG_BASE + 1)
937fe722
FF		 150 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
151
50965d0e
FF		 152 /* A base register in bits 26-22, enclosed in parens, with optional ":m"
153 flag in bit 15 (long immediate and register instructions only) */
937fe722 154
50965d0e 155#define REG_BASE_M_LI (REG_BASE_M_SI + 1)
937fe722
FF		 156 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
157
50965d0e
FF		 158 /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
159
160#define REG_SCALED (REG_BASE_M_LI + 1)
161 { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
162
163 /* Long signed immediate in following 32 bit word, with optional ":s" modifier
164 flag in bit 11 */
165
166#define LSI_SCALED (REG_SCALED + 1)
167 { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
003df617
FF		 168
169 /* Unsigned immediate in bits 4-0, used only for shift instructions */
170
171#define ROTATE (LSI_SCALED + 1)
172 { 5, 0, NULL, NULL, 0 },
173
174 /* Unsigned immediate in bits 9-5, used only for shift instructions */
175#define ENDMASK (ROTATE + 1)
176 { 5, 5, NULL, NULL, 0 },
177
872dc6f0
FF		 178};
179
180const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
181
182\f
183/* Macros used to generate entries for the opcodes table. */
184
185#define FIXME 0
186
937fe722 187/* Short-Immediate Format Instructions - basic opcode */
872dc6f0
FF		 188#define OP_SI(x) (((x) & 0x7F) << 15)
189#define MASK_SI OP_SI(0x7F)
872dc6f0 190
937fe722 191/* Long-Immediate Format Instructions - basic opcode */
872dc6f0
FF		 192#define OP_LI(x) (((x) & 0x3FF) << 12)
193#define MASK_LI OP_LI(0x3FF)
872dc6f0 194
937fe722 195/* Register Format Instructions - basic opcode */
872dc6f0
FF		 196#define OP_REG(x) OP_LI(x) /* For readability */
197#define MASK_REG MASK_LI /* For readability */
872dc6f0 198
003df617
FF		 199/* The 'n' bit at bit 10 */
200#define n(x) ((x) << 10)
201
202/* The 'i' bit at bit 11 */
203#define i(x) ((x) << 11)
204
937fe722
FF		 205/* The 'F' bit at bit 27 */
206#define F(x) ((x) << 27)
207
50965d0e
FF		 208/* The 'E' bit at bit 27 */
209#define E(x) ((x) << 27)
210
937fe722
FF		 211/* The 'M' bit at bit 15 in register and long immediate opcodes */
212#define M_REG(x) ((x) << 15)
213#define M_LI(x) ((x) << 15)
214
215/* The 'M' bit at bit 17 in short immediate opcodes */
216#define M_SI(x) ((x) << 17)
217
218/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
219#define SZ_REG(x) ((x) << 13)
220#define SZ_LI(x) ((x) << 13)
221
222/* The 'SZ' field at bits 16-15 in short immediate opcodes */
223#define SZ_SI(x) ((x) << 15)
224
225/* The 'D' (direct external memory access) bit at bit 10 in long immediate
226 and register opcodes. */
227#define D(x) ((x) << 10)
228
229/* The 'S' (scale offset by data size) bit at bit 11 in long immediate
230 and register opcodes. */
231#define S(x) ((x) << 11)
232
003df617
FF		 233/* The 'PD' field at bits 10-9 in floating point instructions */
234#define PD(x) ((x) << 9)
235
236/* The 'P2' field at bits 8-7 in floating point instructions */
237#define P2(x) ((x) << 7)
238
239/* The 'P1' field at bits 6-5 in floating point instructions */
240#define P1(x) ((x) << 5)
241
937fe722 242\f
5fdeceb4
FF		 243/* The opcode table. Formatted for better readability on a wide screen. */
244
872dc6f0
FF		 245const struct tic80_opcode tic80_opcodes[] = {
246
1f8c8c60 247 /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this
937fe722 248 specific bit pattern will get disassembled as a nop rather than an rdcr. The
1f8c8c60
FF		 249 mask of all ones ensures that this will happen. */
250
251 {"nop", OP_SI(0x4), ~0, 0, {0} },
252
253 /* The "br" instruction is really "bbz target,r0,31". We put it first so that
254 this specific bit pattern will get disassembled as a br rather than bbz. */
255
5fdeceb4 256 {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} },
50965d0e 257 {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} },
5fdeceb4 258 {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} },
1f8c8c60 259
5fdeceb4 260 {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} },
50965d0e 261 {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} },
5fdeceb4 262 {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} },
1f8c8c60 263
872dc6f0
FF		 264 /* Signed integer ADD */
265
50965d0e 266 {"add", OP_SI(0x58), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
50965d0e 267 {"add", OP_REG(0x3B0), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
5fdeceb4 268 {"add", OP_LI(0x3B1), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
872dc6f0
FF		 269
270 /* Unsigned integer ADD */
271
50965d0e 272 {"addu", OP_SI(0x59), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
50965d0e 273 {"addu", OP_REG(0x3B2), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
5fdeceb4 274 {"addu", OP_LI(0x3B3), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
872dc6f0
FF		 275
276 /* Bitwise AND */
277
50965d0e 278 {"and", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
5fdeceb4
FF		 279 {"and.tt", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
280
50965d0e 281 {"and", OP_REG(0x322), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
5fdeceb4 282 {"and.tt", OP_REG(0x322), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
872dc6f0 283
5fdeceb4 284 {"and", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
50965d0e 285 {"and.tt", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
872dc6f0
FF		 286
287 /* Bitwise AND with ones complement of both sources */
288
50965d0e 289 {"and.ff", OP_SI(0x18), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
50965d0e 290 {"and.ff", OP_REG(0x330), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
5fdeceb4 291 {"and.ff", OP_LI(0x331), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
872dc6f0
FF		 292
293 /* Bitwise AND with ones complement of source 1 */
294
50965d0e 295 {"and.ft", OP_SI(0x14), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
50965d0e 296 {"and.ft", OP_REG(0x328), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
5fdeceb4 297 {"and.ft", OP_LI(0x329), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
872dc6f0
FF		 298
299 /* Bitwise AND with ones complement of source 2 */
300
50965d0e 301 {"and.tf", OP_SI(0x12), MASK_SI, FMT_SI, {SUBF, REG_22, REG_DEST} },
50965d0e 302 {"and.tf", OP_REG(0x324), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
5fdeceb4 303 {"and.tf", OP_LI(0x325), MASK_LI, FMT_LI, {LUBF, REG_22, REG_DEST} },
872dc6f0 304
1f8c8c60
FF		 305 /* Branch Bit One - nonannulled */
306
5fdeceb4 307 {"bbo", OP_SI(0x4A), MASK_SI, FMT_SI, {OFF_SS_PC, REG_22, BITNUM} },
50965d0e 308 {"bbo", OP_REG(0x394), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
5fdeceb4 309 {"bbo", OP_LI(0x395), MASK_LI, FMT_LI, {OFF_SL_PC, REG_22, BITNUM} },
1f8c8c60
FF		 310
311 /* Branch Bit One - annulled */
312
5fdeceb4 313 {"bbo.a", OP_SI(0x4B), MASK_SI, FMT_SI, {OFF_SS_PC, REG_22, BITNUM} },
50965d0e 314 {"bbo.a", OP_REG(0x396), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
5fdeceb4 315 {"bbo.a", OP_LI(0x397), MASK_LI, FMT_LI, {OFF_SL_PC, REG_22, BITNUM} },
1f8c8c60
FF		 316
317 /* Branch Bit Zero - nonannulled */
318
5fdeceb4 319 {"bbz", OP_SI(0x48), MASK_SI, FMT_SI, {OFF_SS_PC, REG_22, BITNUM} },
50965d0e 320 {"bbz", OP_REG(0x390), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
5fdeceb4 321 {"bbz", OP_LI(0x391), MASK_LI, FMT_LI, {OFF_SL_PC, REG_22, BITNUM} },
1f8c8c60
FF		 322
323 /* Branch Bit Zero - annulled */
324
5fdeceb4 325 {"bbz.a", OP_SI(0x49), MASK_SI, FMT_SI, {OFF_SS_PC, REG_22, BITNUM} },
50965d0e 326 {"bbz.a", OP_REG(0x392), MASK_REG, FMT_REG, {REG_0, REG_22, BITNUM} },
5fdeceb4 327 {"bbz.a", OP_LI(0x393), MASK_LI, FMT_LI, {OFF_SL_PC, REG_22, BITNUM} },
1f8c8c60
FF		 328
329 /* Branch Conditional - nonannulled */
330
5fdeceb4 331 {"bcnd", OP_SI(0x4C), MASK_SI, FMT_SI, {OFF_SS_PC, REG_22, CC} },
50965d0e 332 {"bcnd", OP_REG(0x398), MASK_REG, FMT_REG, {REG_0, REG_22, CC} },
5fdeceb4 333 {"bcnd", OP_LI(0x399), MASK_LI, FMT_LI, {OFF_SL_PC, REG_22, CC} },
1f8c8c60
FF		 334
335 /* Branch Conditional - annulled */
336
5fdeceb4 337 {"bcnd.a", OP_SI(0x4D), MASK_SI, FMT_SI, {OFF_SS_PC, REG_22, CC} },
50965d0e 338 {"bcnd.a", OP_REG(0x39A), MASK_REG, FMT_REG, {REG_0, REG_22, CC} },
5fdeceb4 339 {"bcnd.a", OP_LI(0x39B), MASK_LI, FMT_LI, {OFF_SL_PC, REG_22, CC} },
1f8c8c60
FF		 340
341 /* Branch Control Register */
342
50965d0e 343 {"brcr", OP_SI(0x6), MASK_SI, FMT_SI, {CR_SI} },
50965d0e 344 {"brcr", OP_REG(0x30C), MASK_REG, FMT_REG, {REG_0} },
5fdeceb4 345 {"brcr", OP_LI(0x30D), MASK_LI, FMT_LI, {CR_LI} },
1f8c8c60 346
937fe722
FF		 347 /* Branch and save return - nonannulled */
348
5fdeceb4 349 {"bsr", OP_SI(0x40), MASK_SI, FMT_SI, {OFF_SS_PC, REG_DEST} },
50965d0e 350 {"bsr", OP_REG(0x380), MASK_REG, FMT_REG, {REG_0, REG_DEST} },
5fdeceb4 351 {"bsr", OP_LI(0x381), MASK_LI, FMT_LI, {OFF_SL_PC, REG_DEST} },
937fe722
FF		 352
353 /* Branch and save return - annulled */
354
5fdeceb4 355 {"bsr.a", OP_SI(0x41), MASK_SI, FMT_SI, {OFF_SS_PC, REG_DEST} },
50965d0e 356 {"bsr.a", OP_REG(0x382), MASK_REG, FMT_REG, {REG_0, REG_DEST} },
5fdeceb4 357 {"bsr.a", OP_LI(0x383), MASK_LI, FMT_LI, {OFF_SL_PC, REG_DEST} },
937fe722
FF		 358
359 /* Send command */
360
361 {"cmnd", OP_SI(0x2), MASK_SI, FMT_SI, {SUI} },
50965d0e 362 {"cmnd", OP_REG(0x304), MASK_REG, FMT_REG, {REG_0} },
5fdeceb4 363 {"cmnd", OP_LI(0x305), MASK_LI, FMT_LI, {LUI} },
937fe722
FF		 364
365 /* Integer compare */
366
50965d0e 367 {"cmp", OP_SI(0x50), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
50965d0e 368 {"cmp", OP_REG(0x3A0), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
5fdeceb4 369 {"cmp", OP_LI(0x3A1), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
937fe722
FF		 370
371 /* Flush data cache subblock - don't clear subblock preset flag */
372
50965d0e 373 {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI} },
50965d0e 374 {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), FMT_REG, {REG_0, REG_BASE_M_LI} },
5fdeceb4 375 {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), FMT_LI, {LSI, REG_BASE_M_LI} },
937fe722
FF		 376
377 /* Flush data cache subblock - clear subblock preset flag */
378
50965d0e 379 {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI} },
50965d0e 380 {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), FMT_REG, {REG_0, REG_BASE_M_LI} },
5fdeceb4 381 {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), FMT_LI, {LSI, REG_BASE_M_LI} },
50965d0e
FF		 382
383 /* Direct load signed data into register */
384
50965d0e 385 {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 386 {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 387 {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
5fdeceb4 388 {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 389
5fdeceb4
FF		 390 {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
391 {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
392 {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 393 {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e
FF		 394
395 /* Direct load unsigned data into register */
396
50965d0e 397 {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
5fdeceb4 398 {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 399
5fdeceb4 400 {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 401 {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e
FF		 402
403 /* Direct store data into memory */
404
50965d0e 405 {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 406 {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 407 {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
5fdeceb4 408 {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 409
5fdeceb4
FF		 410 {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
411 {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
412 {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e 413 {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
50965d0e
FF		 414
415 /* Emulation stop */
416
417 {"estop", OP_LI(0x3FC), MASK_LI, FMT_LI, {0} },
418
419 /* Emulation trap */
420
421 {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), FMT_SI, {SUI} },
50965d0e 422 {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), FMT_REG, {REG_0} },
5fdeceb4 423 {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), FMT_LI, {LUI} },
003df617
FF		 424
425 /* Floating-point addition */
426
003df617
FF		 427 {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
428 {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
429 {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
430 {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
431 {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
432
5fdeceb4
FF		 433 {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
434 {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
435 {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
436 {"fadd.dsd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
437 {"fadd.ddd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
003df617 438
5fdeceb4 439 /* Floating point compare */
003df617
FF		 440
441 {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
442 {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
443 {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
444 {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
445
5fdeceb4
FF		 446 {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
447 {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
448 {"fcmp.ds", OP_LI(0x3EB) | PD(0) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
449 {"fcmp.dd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
450
003df617
FF		 451 /* Floating point divide */
452
5fdeceb4
FF		 453 {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
454 {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
455 {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
456 {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
457 {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
458
003df617
FF		 459 {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
460 {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
461 {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
462 {"fdiv.dsd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
463 {"fdiv.ddd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
464
5fdeceb4
FF		 465 /* Floating point multiply */
466
467 {"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
468 {"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
469 {"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
470 {"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
471 {"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
472 {"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
473 {"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
474
475 {"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
476 {"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
477 {"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
478 {"fmpy.dsd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
479 {"fmpy.ddd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
480 {"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_22, REG_DEST} },
481 {"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LUI, REG_22, REG_DEST} },
482
483 /* Convert/Round to Minus Infinity */
484
485 {"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
486 {"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
487 {"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
488 {"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
489 {"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
490 {"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
491
492 {"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
493 {"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
494 {"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
495 {"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
496 {"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
497 {"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
498
499 /* Convert/Round to Nearest */
500
501 {"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
502 {"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
503 {"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
504 {"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
505 {"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
506 {"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
507
508 {"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
509 {"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
510 {"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
511 {"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
512 {"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
513 {"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
514
515 /* Convert/Round to Positive Infinity */
516
517 {"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
518 {"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
519 {"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
520 {"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
521 {"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
522 {"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
523
524 {"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
525 {"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
526 {"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
527 {"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
528 {"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
529 {"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
530
531 /* Convert/Round to Zero */
532
533 {"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
534 {"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
535 {"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
536 {"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
537 {"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
538 {"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
539
540 {"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
541 {"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
542 {"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
543 {"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
544 {"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
545 {"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {LSI, REG_DEST} },
546
547 /* Floating point square root */
548
549 {"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
550 {"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
551 {"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_DEST} },
552
553 {"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
554 {"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
555 {"fsqrt.dd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_DEST} },
556
557 /* Floating point subtraction */
558
559 { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
560 { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
561 { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
562 { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
563 { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
564
565 { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
566 { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
567 { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
568 { "fsub.dsd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
569 { "fsub.ddd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
570
571 /* Illegal instructions */
572
573 {"illop0", OP_SI(0x0), MASK_SI, FMT_SI, 0},
574 {"illopF", 0x1FF << 13, 0x1FF << 13, FMT_REG, 0},
575
576 /* Jump and save return */
577
578 {"jsr", OP_SI(0x44), MASK_SI, FMT_SI, {OFF_SS_BR, REG_BASE, REG_DEST} },
579 {"jsr.a", OP_SI(0x45), MASK_SI, FMT_SI, {OFF_SS_BR, REG_BASE, REG_DEST} },
580
581 {"jsr", OP_REG(0x388), MASK_REG, FMT_REG, {REG_0, REG_BASE, REG_DEST} },
582 {"jsr.a", OP_REG(0x38A), MASK_REG, FMT_REG, {REG_0, REG_BASE, REG_DEST} },
583
584 {"jsr", OP_LI(0x389), MASK_LI, FMT_LI, {OFF_SL_BR, REG_BASE, REG_DEST} },
585 {"jsr.a", OP_LI(0x38B), MASK_LI, FMT_LI, {OFF_SL_BR, REG_BASE, REG_DEST} },
586
587 /* Load Signed Data Into Register */
588
589 {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST} },
590 {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST} },
591 {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST} },
592 {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST} },
593
594 {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
595 {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
596 {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
597 {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
598
599 {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
600 {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
601 {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
602 {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
603
604 /* Load Unsigned Data Into Register */
605
606 {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST} },
607 {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST} },
608
609 {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
610 {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
611
612 {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
613 {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
614
615 /* Leftmost one */
616
617 {"lmo", OP_LI(0x3F0), MASK_LI, FMT_LI, {REG_22, REG_DEST} },
618
619 /* Bitwise logical OR */
620
621 {"or.ff", OP_SI(0x1E), MASK_SI, FMT_SI, {SUI, REG_22, REG_DEST} },
622 {"or.ft", OP_SI(0x1D), MASK_SI, FMT_SI, {SUI, REG_22, REG_DEST} },
623 {"or.tf", OP_SI(0x1B), MASK_SI, FMT_SI, {SUI, REG_22, REG_DEST} },
624 {"or.tt", OP_SI(0x17), MASK_SI, FMT_SI, {SUI, REG_22, REG_DEST} },
625
626 {"or.ff", OP_REG(0x33C), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
627 {"or.ft", OP_REG(0x33A), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
628 {"or.tf", OP_REG(0x336), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
629 {"or.tt", OP_REG(0x32E), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
630
631 {"or.ff", OP_LI(0x33D), MASK_LI, FMT_LI, {LUI, REG_22, REG_DEST} },
632 {"or.ft", OP_LI(0x33B), MASK_LI, FMT_LI, {LUI, REG_22, REG_DEST} },
633 {"or.tf", OP_LI(0x337), MASK_LI, FMT_LI, {LUI, REG_22, REG_DEST} },
634 {"or.tt", OP_LI(0x32F), MASK_LI, FMT_LI, {LUI, REG_22, REG_DEST} },
635
636 /* Read Control Register */
637
638 {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), FMT_SI, {CR_SI, REG_DEST} },
639 {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), FMT_REG, {REG_0, REG_DEST} },
640 {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), FMT_LI, {CR_LI, REG_DEST} },
641
642 /* Rightmost one */
643
644 {"rmo", OP_LI(0x3F2), MASK_LI, FMT_LI, {REG_22, REG_DEST} },
645
646 /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
647 They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
648
649 {"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
650 {"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
651 {"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
652 {"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
653 {"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
654 {"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
655 {"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
656 {"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
657 {"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
658 {"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
659 {"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
660
661 {"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
662 {"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
663 {"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
664 {"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
665 {"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
666 {"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
667 {"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
668 {"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
669 {"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
670 {"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
671 {"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
672
673 /* Shift Register Left With Inverted Endmask */
674
675 {"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
676 {"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
677 {"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
678 {"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
679 {"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
680 {"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
681 {"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
682 {"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
683
684 {"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
685 {"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
686 {"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
687 {"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
688 {"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
689 {"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
690 {"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
691 {"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
692
693 /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
694 They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
695
696 {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
697 {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
698 {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
699 {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
700 {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
701 {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
702 {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
703 {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
704 {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
705 {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
706 {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
707 {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
708 {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
709
710 {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
711 {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
712 {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
713 {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
714 {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
715 {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
716 {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
717 {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
718 {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
719 {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
720 {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
721 {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
722 {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
723
724 /* Shift Register Right With Inverted Endmask */
725
726 {"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
727 {"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
728 {"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
729 {"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
730 {"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
731 {"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
732 {"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
733 {"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
734
735 {"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
736 {"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
737 {"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
738 {"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
739 {"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
740 {"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
741 {"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
742 {"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
743
744 /* Store Data into Memory */
745
746 {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST}},
747 {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST}},
748 {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST}},
749 {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), FMT_SI, {SSI, REG_BASE_M_SI, REG_DEST}},
750
751 {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
752 {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
753 {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
754 {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), FMT_REG, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
755
756 {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
757 {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
758 {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
759 {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), FMT_LI, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} },
760
761 /* Signed Integer Subtract */
762
763 {"sub", OP_SI(0x5A), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
764 {"sub", OP_REG(0x3B4), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
765 {"sub", OP_LI(0x3B5), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
766
767 /* Unsigned Integer Subtract */
768
769 {"subu", OP_SI(0x5B), MASK_SI, FMT_SI, {SSI, REG_22, REG_DEST} },
770 {"subu", OP_REG(0x3B6), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
771 {"subu", OP_LI(0x3B7), MASK_LI, FMT_LI, {LSI, REG_22, REG_DEST} },
772
773 /* Swap Control Register */
774
775 {"swcr", OP_SI(0x5), MASK_SI, FMT_SI, {CR_SI, REG_22, REG_DEST} },
776 {"swcr", OP_REG(0x30A), MASK_REG, FMT_REG, {REG_0, REG_22, REG_DEST} },
777 {"swcr", OP_LI(0x30B), MASK_LI, FMT_LI, {CR_LI, REG_22, REG_DEST} },
778
779 /* Trap */
780
781 {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), FMT_SI, {SUI} },
782 {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), FMT_REG, {REG_0} },
783 {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), FMT_LI, {LUI} },
784
785
003df617 786
872dc6f0
FF		 787 {"xnor", OP_LI(0x333), MASK_LI, FMT_LI, FIXME},
788 {"xnor", OP_REG(0x332), MASK_REG, FMT_REG, FIXME},
789 {"xnor", OP_SI(0x19), MASK_SI, FMT_SI, FIXME},
790 {"xor", OP_LI(0x32D), MASK_LI, FMT_LI, FIXME},
791 {"xor", OP_REG(0x32C), MASK_REG, FMT_REG, FIXME},
792 {"xor", OP_SI(0x16), MASK_SI, FMT_SI, FIXME},
793
794};
795
796const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
797
GDB Binutils - Deliverables
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