projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 252b5132 | 1 | /* Assemble V850 instructions. |
| d83c6548 | 2 | Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. |
| 252b5132 RH |
3 | |
| 4 | This program is free software; you can redistribute it and/or modify | |
| 5 | it under the terms of the GNU General Public License as published by | |
| 6 | the Free Software Foundation; either version 2 of the License, or | |
| 7 | (at your option) any later version. | |
| 8 | ||
| 9 | This program is distributed in the hope that it will be useful, | |
| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | GNU General Public License for more details. | |
| 13 | ||
| 14 | You should have received a copy of the GNU General Public License | |
| 15 | along with this program; if not, write to the Free Software | |
| 16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
| 17 | ||
| 0d8dfecf | 18 | #include "sysdep.h" |
| 252b5132 RH |
19 | #include "opcode/v850.h" |
| 20 | #include <stdio.h> | |
| 21 | #include "opintl.h" | |
| 22 | ||
| 23 | /* regular opcode */ | |
| 24 | #define OP(x) ((x & 0x3f) << 5) | |
| 25 | #define OP_MASK OP (0x3f) | |
| 26 | ||
| 27 | /* conditional branch opcode */ | |
| 28 | #define BOP(x) ((0x0b << 7) | (x & 0x0f)) | |
| 29 | #define BOP_MASK ((0x0f << 7) | 0x0f) | |
| 30 | ||
| 31 | /* one-word opcodes */ | |
| 32 | #define one(x) ((unsigned int) (x)) | |
| 33 | ||
| 34 | /* two-word opcodes */ | |
| 35 | #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) | |
| 36 | ||
| fc05c67f NC |
37 | static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **)); |
| 38 | static long unsigned extract_d9 PARAMS ((long unsigned, int *)); | |
| 39 | static long unsigned insert_d22 PARAMS ((long unsigned, long, const char **)); | |
| 40 | static long unsigned extract_d22 PARAMS ((long unsigned, int *)); | |
| 41 | static long unsigned insert_d16_15 PARAMS ((long unsigned, long, const char **)); | |
| 42 | static long unsigned extract_d16_15 PARAMS ((long unsigned, int *)); | |
| 43 | static long unsigned insert_d8_7 PARAMS ((long unsigned, long, const char **)); | |
| 44 | static long unsigned extract_d8_7 PARAMS ((long unsigned, int *)); | |
| 45 | static long unsigned insert_d8_6 PARAMS ((long unsigned, long, const char **)); | |
| 46 | static long unsigned extract_d8_6 PARAMS ((long unsigned, int *)); | |
| 47 | static long unsigned insert_d5_4 PARAMS ((long unsigned, long, const char **)); | |
| 48 | static long unsigned extract_d5_4 PARAMS ((long unsigned, int *)); | |
| 49 | static long unsigned insert_d16_16 PARAMS ((long unsigned, long, const char **)); | |
| 50 | static long unsigned extract_d16_16 PARAMS ((long unsigned, int *)); | |
| 51 | static long unsigned insert_i9 PARAMS ((long unsigned, long, const char **)); | |
| 52 | static long unsigned extract_i9 PARAMS ((long unsigned, int *)); | |
| 53 | static long unsigned insert_u9 PARAMS ((long unsigned, long, const char **)); | |
| 54 | static long unsigned extract_u9 PARAMS ((long unsigned, int *)); | |
| 55 | static long unsigned insert_spe PARAMS ((long unsigned, long, const char **)); | |
| 56 | static long unsigned extract_spe PARAMS ((long unsigned, int *)); | |
| 57 | static long unsigned insert_i5div PARAMS ((long unsigned, long, const char **)); | |
| 58 | static long unsigned extract_i5div PARAMS ((long unsigned, int *)); | |
| 252b5132 RH |
59 | |
| 60 | \f | |
| 61 | /* The functions used to insert and extract complicated operands. */ | |
| 62 | ||
| 63 | /* Note: There is a conspiracy between these functions and | |
| 64 | v850_insert_operand() in gas/config/tc-v850.c. Error messages | |
| 65 | containing the string 'out of range' will be ignored unless a | |
| 66 | specific command line option is given to GAS. */ | |
| 67 | ||
| 68 | static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); | |
| 69 | static const char * out_of_range = N_ ("displacement value is out of range"); | |
| 70 | static const char * not_aligned = N_ ("displacement value is not aligned"); | |
| 71 | ||
| 72 | static const char * immediate_out_of_range = N_ ("immediate value is out of range"); | |
| 73 | ||
| 74 | static unsigned long | |
| 75 | insert_d9 (insn, value, errmsg) | |
| 76 | unsigned long insn; | |
| 77 | long value; | |
| 78 | const char ** errmsg; | |
| 79 | { | |
| 80 | if (value > 0xff || value < -0x100) | |
| 81 | { | |
| 82 | if ((value % 2) != 0) | |
| 83 | * errmsg = _("branch value not in range and to odd offset"); | |
| 84 | else | |
| 85 | * errmsg = _("branch value out of range"); | |
| 86 | } | |
| 87 | else if ((value % 2) != 0) | |
| 88 | * errmsg = _("branch to odd offset"); | |
| 89 | ||
| 90 | return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); | |
| 91 | } | |
| 92 | ||
| 93 | static unsigned long | |
| 94 | extract_d9 (insn, invalid) | |
| 95 | unsigned long insn; | |
| d83c6548 | 96 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
97 | { |
| 98 | unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); | |
| 99 | ||
| 100 | if ((insn & 0x8000) != 0) | |
| 101 | ret -= 0x0200; | |
| 102 | ||
| 103 | return ret; | |
| 104 | } | |
| 105 | ||
| 106 | static unsigned long | |
| 107 | insert_d22 (insn, value, errmsg) | |
| 108 | unsigned long insn; | |
| 109 | long value; | |
| 110 | const char ** errmsg; | |
| 111 | { | |
| 112 | if (value > 0x1fffff || value < -0x200000) | |
| 113 | { | |
| 114 | if ((value % 2) != 0) | |
| 115 | * errmsg = _("branch value not in range and to an odd offset"); | |
| 116 | else | |
| 117 | * errmsg = _("branch value out of range"); | |
| 118 | } | |
| 119 | else if ((value % 2) != 0) | |
| 120 | * errmsg = _("branch to odd offset"); | |
| 121 | ||
| 122 | return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)); | |
| 123 | } | |
| 124 | ||
| 125 | static unsigned long | |
| 126 | extract_d22 (insn, invalid) | |
| 127 | unsigned long insn; | |
| d83c6548 | 128 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
129 | { |
| 130 | signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); | |
| 131 | ||
| 132 | return (unsigned long) ((ret << 10) >> 10); | |
| 133 | } | |
| 134 | ||
| 135 | static unsigned long | |
| 136 | insert_d16_15 (insn, value, errmsg) | |
| 137 | unsigned long insn; | |
| 138 | long value; | |
| 139 | const char ** errmsg; | |
| 140 | { | |
| 141 | if (value > 0x7fff || value < -0x8000) | |
| 142 | { | |
| 143 | if ((value % 2) != 0) | |
| 144 | * errmsg = _(not_valid); | |
| 145 | else | |
| 146 | * errmsg = _(out_of_range); | |
| 147 | } | |
| 148 | else if ((value % 2) != 0) | |
| 149 | * errmsg = _(not_aligned); | |
| 150 | ||
| 151 | return insn | ((value & 0xfffe) << 16); | |
| 152 | } | |
| 153 | ||
| 154 | static unsigned long | |
| 155 | extract_d16_15 (insn, invalid) | |
| 156 | unsigned long insn; | |
| d83c6548 | 157 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
158 | { |
| 159 | signed long ret = (insn & 0xfffe0000); | |
| 160 | ||
| 161 | return ret >> 16; | |
| 162 | } | |
| 163 | ||
| 164 | static unsigned long | |
| 165 | insert_d8_7 (insn, value, errmsg) | |
| 166 | unsigned long insn; | |
| 167 | long value; | |
| 168 | const char ** errmsg; | |
| 169 | { | |
| 170 | if (value > 0xff || value < 0) | |
| 171 | { | |
| 172 | if ((value % 2) != 0) | |
| 173 | * errmsg = _(not_valid); | |
| 174 | else | |
| 175 | * errmsg = _(out_of_range); | |
| 176 | } | |
| 177 | else if ((value % 2) != 0) | |
| 178 | * errmsg = _(not_aligned); | |
| 179 | ||
| 180 | value >>= 1; | |
| 181 | ||
| 182 | return (insn | (value & 0x7f)); | |
| 183 | } | |
| 184 | ||
| 185 | static unsigned long | |
| 186 | extract_d8_7 (insn, invalid) | |
| 187 | unsigned long insn; | |
| d83c6548 | 188 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
189 | { |
| 190 | unsigned long ret = (insn & 0x7f); | |
| 191 | ||
| 192 | return ret << 1; | |
| 193 | } | |
| 194 | ||
| 195 | static unsigned long | |
| 196 | insert_d8_6 (insn, value, errmsg) | |
| 197 | unsigned long insn; | |
| 198 | long value; | |
| 199 | const char ** errmsg; | |
| 200 | { | |
| 201 | if (value > 0xff || value < 0) | |
| 202 | { | |
| 203 | if ((value % 4) != 0) | |
| 204 | *errmsg = _(not_valid); | |
| 205 | else | |
| 206 | * errmsg = _(out_of_range); | |
| 207 | } | |
| 208 | else if ((value % 4) != 0) | |
| 209 | * errmsg = _(not_aligned); | |
| 210 | ||
| 211 | value >>= 1; | |
| 212 | ||
| 213 | return (insn | (value & 0x7e)); | |
| 214 | } | |
| 215 | ||
| 216 | static unsigned long | |
| 217 | extract_d8_6 (insn, invalid) | |
| 218 | unsigned long insn; | |
| d83c6548 | 219 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
220 | { |
| 221 | unsigned long ret = (insn & 0x7e); | |
| 222 | ||
| 223 | return ret << 1; | |
| 224 | } | |
| 225 | ||
| 226 | static unsigned long | |
| 227 | insert_d5_4 (insn, value, errmsg) | |
| 228 | unsigned long insn; | |
| 229 | long value; | |
| 230 | const char ** errmsg; | |
| 231 | { | |
| 232 | if (value > 0x1f || value < 0) | |
| 233 | { | |
| 234 | if (value & 1) | |
| 235 | * errmsg = _(not_valid); | |
| 236 | else | |
| 237 | *errmsg = _(out_of_range); | |
| 238 | } | |
| 239 | else if (value & 1) | |
| 240 | * errmsg = _(not_aligned); | |
| 241 | ||
| 242 | value >>= 1; | |
| 243 | ||
| 244 | return (insn | (value & 0x0f)); | |
| 245 | } | |
| 246 | ||
| 247 | static unsigned long | |
| 248 | extract_d5_4 (insn, invalid) | |
| 249 | unsigned long insn; | |
| d83c6548 | 250 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
251 | { |
| 252 | unsigned long ret = (insn & 0x0f); | |
| 253 | ||
| 254 | return ret << 1; | |
| 255 | } | |
| 256 | ||
| 257 | static unsigned long | |
| 258 | insert_d16_16 (insn, value, errmsg) | |
| 259 | unsigned long insn; | |
| 260 | signed long value; | |
| 261 | const char ** errmsg; | |
| 262 | { | |
| 263 | if (value > 0x7fff || value < -0x8000) | |
| 264 | * errmsg = _(out_of_range); | |
| 265 | ||
| 266 | return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5)); | |
| 267 | } | |
| 268 | ||
| 269 | static unsigned long | |
| 270 | extract_d16_16 (insn, invalid) | |
| 271 | unsigned long insn; | |
| d83c6548 | 272 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
273 | { |
| 274 | signed long ret = insn & 0xfffe0000; | |
| 275 | ||
| 276 | ret >>= 16; | |
| 277 | ||
| 278 | ret |= ((insn & 0x20) >> 5); | |
| 279 | ||
| 280 | return ret; | |
| 281 | } | |
| 282 | ||
| 283 | static unsigned long | |
| 284 | insert_i9 (insn, value, errmsg) | |
| 285 | unsigned long insn; | |
| 286 | signed long value; | |
| 287 | const char ** errmsg; | |
| 288 | { | |
| 289 | if (value > 0xff || value < -0x100) | |
| 290 | * errmsg = _(immediate_out_of_range); | |
| 291 | ||
| 292 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); | |
| 293 | } | |
| 294 | ||
| 295 | static unsigned long | |
| 296 | extract_i9 (insn, invalid) | |
| 297 | unsigned long insn; | |
| d83c6548 | 298 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
299 | { |
| 300 | signed long ret = insn & 0x003c0000; | |
| 301 | ||
| 302 | ret <<= 10; | |
| 303 | ret >>= 23; | |
| 304 | ||
| 305 | ret |= (insn & 0x1f); | |
| 306 | ||
| 307 | return ret; | |
| 308 | } | |
| 309 | ||
| 310 | static unsigned long | |
| fc05c67f | 311 | insert_u9 (insn, v, errmsg) |
| 252b5132 | 312 | unsigned long insn; |
| fc05c67f | 313 | long v; |
| 252b5132 RH |
314 | const char ** errmsg; |
| 315 | { | |
| fc05c67f | 316 | unsigned long value = (unsigned long) v; |
| 252b5132 RH |
317 | if (value > 0x1ff) |
| 318 | * errmsg = _(immediate_out_of_range); | |
| 319 | ||
| 320 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); | |
| 321 | } | |
| 322 | ||
| 323 | static unsigned long | |
| 324 | extract_u9 (insn, invalid) | |
| 325 | unsigned long insn; | |
| d83c6548 | 326 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
327 | { |
| 328 | unsigned long ret = insn & 0x003c0000; | |
| 329 | ||
| 330 | ret >>= 13; | |
| 331 | ||
| 332 | ret |= (insn & 0x1f); | |
| 333 | ||
| 334 | return ret; | |
| 335 | } | |
| 336 | ||
| 337 | static unsigned long | |
| fc05c67f | 338 | insert_spe (insn, v, errmsg) |
| 252b5132 | 339 | unsigned long insn; |
| fc05c67f | 340 | long v; |
| 252b5132 RH |
341 | const char ** errmsg; |
| 342 | { | |
| fc05c67f NC |
343 | unsigned long value = (unsigned long) v; |
| 344 | ||
| 252b5132 RH |
345 | if (value != 3) |
| 346 | * errmsg = _("invalid register for stack adjustment"); | |
| 347 | ||
| 348 | return insn & (~ 0x180000); | |
| 349 | } | |
| 350 | ||
| 351 | static unsigned long | |
| 352 | extract_spe (insn, invalid) | |
| d83c6548 AJ |
353 | unsigned long insn ATTRIBUTE_UNUSED; |
| 354 | int * invalid ATTRIBUTE_UNUSED; | |
| 252b5132 RH |
355 | { |
| 356 | return 3; | |
| 357 | } | |
| 358 | ||
| 359 | static unsigned long | |
| fc05c67f | 360 | insert_i5div (insn, v, errmsg) |
| 252b5132 | 361 | unsigned long insn; |
| fc05c67f | 362 | long v; |
| 252b5132 RH |
363 | const char ** errmsg; |
| 364 | { | |
| fc05c67f NC |
365 | unsigned long value = (unsigned long) v; |
| 366 | ||
| 252b5132 RH |
367 | if (value > 0x1ff) |
| 368 | { | |
| 369 | if (value & 1) | |
| 370 | * errmsg = _("immediate value not in range and not even"); | |
| 371 | else | |
| 372 | * errmsg = _(immediate_out_of_range); | |
| 373 | } | |
| 374 | else if (value & 1) | |
| 375 | * errmsg = _("immediate value must be even"); | |
| 376 | ||
| 377 | value = 32 - value; | |
| 378 | ||
| 379 | return insn | ((value & 0x1e) << 17); | |
| 380 | } | |
| 381 | ||
| 382 | static unsigned long | |
| 383 | extract_i5div (insn, invalid) | |
| 384 | unsigned long insn; | |
| d83c6548 | 385 | int * invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
386 | { |
| 387 | unsigned long ret = insn & 0x3c0000; | |
| 388 | ||
| 389 | ret >>= 17; | |
| 390 | ||
| 391 | ret = 32 - ret; | |
| 392 | ||
| 393 | return ret; | |
| 394 | } | |
| 395 | ||
| 396 | \f | |
| 397 | /* Warning: code in gas/config/tc-v850.c examines the contents of this array. | |
| 398 | If you change any of the values here, be sure to look for side effects in | |
| fc05c67f | 399 | that code. */ |
| 252b5132 RH |
400 | const struct v850_operand v850_operands[] = |
| 401 | { | |
| 402 | #define UNUSED 0 | |
| 403 | { 0, 0, NULL, NULL, 0 }, | |
| 404 | ||
| 405 | /* The R1 field in a format 1, 6, 7, or 9 insn. */ | |
| 406 | #define R1 (UNUSED + 1) | |
| 407 | { 5, 0, NULL, NULL, V850_OPERAND_REG }, | |
| 408 | ||
| 409 | /* As above, but register 0 is not allowed. */ | |
| 410 | #define R1_NOTR0 (R1 + 1) | |
| 411 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, | |
| 412 | ||
| 413 | /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ | |
| 414 | #define R2 (R1_NOTR0 + 1) | |
| 415 | { 5, 11, NULL, NULL, V850_OPERAND_REG }, | |
| 416 | ||
| 417 | /* As above, but register 0 is not allowed. */ | |
| 418 | #define R2_NOTR0 (R2 + 1) | |
| 419 | { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, | |
| 420 | ||
| 421 | /* The imm5 field in a format 2 insn. */ | |
| 422 | #define I5 (R2_NOTR0 + 1) | |
| 423 | { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, | |
| 424 | ||
| 425 | /* The unsigned imm5 field in a format 2 insn. */ | |
| 426 | #define I5U (I5 + 1) | |
| 427 | { 5, 0, NULL, NULL, 0 }, | |
| 428 | ||
| 429 | /* The imm16 field in a format 6 insn. */ | |
| 430 | #define I16 (I5U + 1) | |
| 431 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, | |
| 432 | ||
| 433 | /* The signed disp7 field in a format 4 insn. */ | |
| 434 | #define D7 (I16 + 1) | |
| 435 | { 7, 0, NULL, NULL, 0}, | |
| 436 | ||
| 437 | /* The disp16 field in a format 6 insn. */ | |
| 438 | #define D16_15 (D7 + 1) | |
| 439 | { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, | |
| 440 | ||
| 441 | /* The 3 bit immediate field in format 8 insn. */ | |
| 442 | #define B3 (D16_15 + 1) | |
| 443 | { 3, 11, NULL, NULL, 0 }, | |
| 444 | ||
| 445 | /* The 4 bit condition code in a setf instruction */ | |
| 446 | #define CCCC (B3 + 1) | |
| 447 | { 4, 0, NULL, NULL, V850_OPERAND_CC }, | |
| 448 | ||
| 449 | /* The unsigned DISP8 field in a format 4 insn. */ | |
| 450 | #define D8_7 (CCCC + 1) | |
| 451 | { 7, 0, insert_d8_7, extract_d8_7, 0 }, | |
| 452 | ||
| 453 | /* The unsigned DISP8 field in a format 4 insn. */ | |
| 454 | #define D8_6 (D8_7 + 1) | |
| 455 | { 6, 1, insert_d8_6, extract_d8_6, 0 }, | |
| 456 | ||
| 457 | /* System register operands. */ | |
| 458 | #define SR1 (D8_6 + 1) | |
| 459 | { 5, 0, NULL, NULL, V850_OPERAND_SRG }, | |
| 460 | ||
| 461 | /* EP Register. */ | |
| 462 | #define EP (SR1 + 1) | |
| 463 | { 0, 0, NULL, NULL, V850_OPERAND_EP }, | |
| 464 | ||
| 465 | /* The imm16 field (unsigned) in a format 6 insn. */ | |
| 466 | #define I16U (EP + 1) | |
| 467 | { 16, 16, NULL, NULL, 0}, | |
| 468 | ||
| 469 | /* The R2 field as a system register. */ | |
| 470 | #define SR2 (I16U + 1) | |
| 471 | { 5, 11, NULL, NULL, V850_OPERAND_SRG }, | |
| 472 | ||
| 473 | /* The disp16 field in a format 8 insn. */ | |
| 474 | #define D16 (SR2 + 1) | |
| 475 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, | |
| 476 | ||
| 477 | /* The DISP9 field in a format 3 insn, relaxable. */ | |
| 478 | #define D9_RELAX (D16 + 1) | |
| 479 | { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, | |
| 480 | ||
| 481 | /* The DISP22 field in a format 4 insn, relaxable. | |
| 482 | This _must_ follow D9_RELAX; the assembler assumes that the longer | |
| 483 | version immediately follows the shorter version for relaxing. */ | |
| 484 | #define D22 (D9_RELAX + 1) | |
| 485 | { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, | |
| 486 | ||
| 487 | /* The signed disp4 field in a format 4 insn. */ | |
| 488 | #define D4 (D22 + 1) | |
| 489 | { 4, 0, NULL, NULL, 0}, | |
| 490 | ||
| 491 | /* The unsigned disp5 field in a format 4 insn. */ | |
| 492 | #define D5_4 (D4 + 1) | |
| 493 | { 4, 0, insert_d5_4, extract_d5_4, 0 }, | |
| 494 | ||
| 495 | /* The disp16 field in an format 7 unsigned byte load insn. */ | |
| 496 | #define D16_16 (D5_4 + 1) | |
| 497 | { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, | |
| 498 | ||
| 499 | /* Third register in conditional moves. */ | |
| 500 | #define R3 (D16_16 + 1) | |
| 501 | { 5, 27, NULL, NULL, V850_OPERAND_REG }, | |
| 502 | ||
| 503 | /* Condition code in conditional moves. */ | |
| 504 | #define MOVCC (R3 + 1) | |
| 505 | { 4, 17, NULL, NULL, V850_OPERAND_CC }, | |
| 506 | ||
| 507 | /* The imm9 field in a multiply word. */ | |
| 508 | #define I9 (MOVCC + 1) | |
| 509 | { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, | |
| 510 | ||
| 511 | /* The unsigned imm9 field in a multiply word. */ | |
| 512 | #define U9 (I9 + 1) | |
| 513 | { 9, 0, insert_u9, extract_u9, 0 }, | |
| 514 | ||
| 515 | /* A list of registers in a prepare/dispose instruction. */ | |
| 516 | #define LIST12 (U9 + 1) | |
| 517 | { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, | |
| 518 | ||
| 519 | /* The IMM6 field in a call instruction. */ | |
| 520 | #define I6 (LIST12 + 1) | |
| 521 | { 6, 0, NULL, NULL, 0 }, | |
| 522 | ||
| 523 | /* The 16 bit immediate following a 32 bit instruction. */ | |
| 524 | #define IMM16 (I6 + 1) | |
| 525 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, | |
| 526 | ||
| 527 | /* The 32 bit immediate following a 32 bit instruction. */ | |
| 528 | #define IMM32 (IMM16 + 1) | |
| 529 | { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, | |
| 530 | ||
| 531 | /* The imm5 field in a push/pop instruction. */ | |
| 532 | #define IMM5 (IMM32 + 1) | |
| 533 | { 5, 1, NULL, NULL, 0 }, | |
| 534 | ||
| 535 | /* Reg2 in dispose instruction. */ | |
| 536 | #define R2DISPOSE (IMM5 + 1) | |
| 537 | { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, | |
| 538 | ||
| 539 | /* Stack pointer in prepare instruction. */ | |
| 540 | #define SP (R2DISPOSE + 1) | |
| 541 | { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, | |
| 542 | ||
| 543 | /* The IMM5 field in a divide N step instruction. */ | |
| 544 | #define I5DIV (SP + 1) | |
| 545 | { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, | |
| 546 | ||
| 547 | /* The list of registers in a PUSHMH/POPMH instruction. */ | |
| 548 | #define LIST18_H (I5DIV + 1) | |
| 549 | { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, | |
| 550 | ||
| 551 | /* The list of registers in a PUSHML/POPML instruction. */ | |
| 552 | #define LIST18_L (LIST18_H + 1) | |
| 553 | { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ | |
| 554 | } ; | |
| 555 | ||
| 556 | \f | |
| 557 | /* reg-reg instruction format (Format I) */ | |
| 558 | #define IF1 {R1, R2} | |
| 559 | ||
| 560 | /* imm-reg instruction format (Format II) */ | |
| 561 | #define IF2 {I5, R2} | |
| 562 | ||
| 563 | /* conditional branch instruction format (Format III) */ | |
| 564 | #define IF3 {D9_RELAX} | |
| 565 | ||
| 566 | /* 3 operand instruction (Format VI) */ | |
| 567 | #define IF6 {I16, R1, R2} | |
| 568 | ||
| 569 | /* 3 operand instruction (Format VI) */ | |
| 570 | #define IF6U {I16U, R1, R2} | |
| 571 | ||
| 572 | ||
| 573 | \f | |
| 574 | /* The opcode table. | |
| 575 | ||
| 576 | The format of the opcode table is: | |
| 577 | ||
| 578 | NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR | |
| 579 | ||
| 580 | NAME is the name of the instruction. | |
| 581 | OPCODE is the instruction opcode. | |
| 582 | MASK is the opcode mask; this is used to tell the disassembler | |
| 583 | which bits in the actual opcode must match OPCODE. | |
| 584 | OPERANDS is the list of operands. | |
| 585 | MEMOP specifies which operand (if any) is a memory operand. | |
| 586 | PROCESSORS specifies which CPU(s) support the opcode. | |
| 587 | ||
| 588 | The disassembler reads the table in order and prints the first | |
| 589 | instruction which matches, so this table is sorted to put more | |
| 590 | specific instructions before more general instructions. It is also | |
| 591 | sorted by major opcode. | |
| 592 | ||
| 593 | The table is also sorted by name. This is used by the assembler. | |
| 594 | When parsing an instruction the assembler finds the first occurance | |
| 595 | of the name of the instruciton in this table and then attempts to | |
| 596 | match the instruction's arguments with description of the operands | |
| 597 | associated with the entry it has just found in this table. If the | |
| 598 | match fails the assembler looks at the next entry in this table. | |
| 599 | If that entry has the same name as the previous entry, then it | |
| 600 | tries to match the instruction against that entry and so on. This | |
| 601 | is how the assembler copes with multiple, different formats of the | |
| 602 | same instruction. */ | |
| 603 | ||
| 604 | const struct v850_opcode v850_opcodes[] = | |
| 605 | { | |
| 606 | { "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, | |
| 607 | ||
| 608 | { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, | |
| 609 | ||
| 610 | /* load/store instructions */ | |
| 252b5132 RH |
611 | { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, |
| 612 | ||
| 252b5132 RH |
613 | { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, |
| 614 | ||
| 252b5132 RH |
615 | { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, |
| 616 | { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, | |
| 617 | ||
| 252b5132 RH |
618 | { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, |
| 619 | { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, | |
| 620 | { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, | |
| 621 | { "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL }, | |
| 622 | { "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL }, | |
| 623 | { "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL }, | |
| 624 | ||
| 252b5132 RH |
625 | { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, |
| 626 | { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, | |
| 627 | { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, | |
| 628 | { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, | |
| 629 | { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, | |
| 630 | { "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 }, | |
| 631 | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, | |
| 632 | ||
| 633 | { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL }, | |
| 634 | { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, | |
| 635 | { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, | |
| 636 | { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, | |
| 637 | { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, | |
| 638 | { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, | |
| 639 | { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, | |
| 640 | { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, | |
| 641 | ||
| 642 | /* byte swap/extend instructions */ | |
| 643 | { "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, | |
| 644 | { "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, | |
| 645 | { "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, | |
| 646 | { "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, | |
| 647 | { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 648 | { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 649 | { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 650 | ||
| 651 | /* jump table instructions */ | |
| 652 | { "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, | |
| 653 | { "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, | |
| 654 | { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, | |
| 655 | ||
| 656 | /* arithmetic operation instructions */ | |
| 657 | { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, | |
| 658 | { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 659 | { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 660 | ||
| 661 | { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 662 | { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 663 | { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 664 | { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 665 | ||
| 666 | { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 667 | { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 668 | { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 669 | { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
| 670 | { "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 671 | ||
| 252b5132 RH |
672 | { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, |
| 673 | { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 674 | { "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, | |
| 675 | { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 676 | { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 677 | { "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 678 | { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 679 | { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, | |
| 680 | { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, | |
| 681 | { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 682 | { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 683 | { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 684 | { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 685 | { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 686 | { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 687 | { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, | |
| 688 | ||
| 689 | /* saturated operation instructions */ | |
| 690 | { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 691 | { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 692 | { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 693 | { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 694 | { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
| 695 | ||
| 696 | /* logical operation instructions */ | |
| 697 | { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 698 | { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 699 | { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, | |
| 700 | { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 701 | { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, | |
| 702 | { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 703 | { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, | |
| 704 | { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
| 705 | { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, | |
| 706 | { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
| 707 | { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, | |
| 708 | { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
| 709 | { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, | |
| 710 | { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
| 711 | { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, | |
| 712 | ||
| 713 | /* branch instructions */ | |
| 714 | /* signed integer */ | |
| 715 | { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 716 | { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 717 | { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 718 | { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 719 | /* unsigned integer */ | |
| 720 | { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 721 | { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 722 | { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 723 | { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 724 | /* common */ | |
| 725 | { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 726 | { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 727 | /* others */ | |
| 728 | { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 729 | { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 730 | { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 731 | { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 732 | { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 733 | { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 734 | { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 735 | { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 736 | { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 737 | { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 738 | ||
| 739 | /* Branch macros. | |
| 740 | ||
| 741 | We use the short form in the opcode/mask fields. The assembler | |
| 742 | will twiddle bits as necessary if the long form is needed. */ | |
| 743 | ||
| 744 | /* signed integer */ | |
| 745 | { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 746 | { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 747 | { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 748 | { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 749 | /* unsigned integer */ | |
| 750 | { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 751 | { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 752 | { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 753 | { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 754 | /* common */ | |
| 755 | { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 756 | { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 757 | /* others */ | |
| 758 | { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 759 | { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 760 | { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 761 | { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 762 | { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 763 | { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 764 | { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 765 | { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 766 | { "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 767 | { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
| 768 | ||
| 769 | { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, | |
| 770 | { "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, | |
| 771 | ||
| 772 | /* bit manipulation instructions */ | |
| 773 | { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, | |
| 774 | { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, | |
| 775 | { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, | |
| 776 | { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, | |
| 777 | { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, | |
| 778 | { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, | |
| 779 | { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, | |
| 780 | { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, | |
| 781 | ||
| 782 | /* special instructions */ | |
| 783 | { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
| 784 | { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
| 785 | { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
| 786 | { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
| 787 | { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, | |
| 788 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, | |
| 789 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, | |
| 790 | { 0, 0, 0, {0}, 0, 0 }, | |
| 791 | ||
| 792 | } ; | |
| 793 | ||
| 794 | const int v850_num_opcodes = | |
| 795 | sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); | |
| 796 |