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Add "attn", "lq" and "stq" power4 insns.
[deliverable/binutils-gdb.git] / opcodes / xstormy16-desc.c
CommitLineData
93fbbb04
GK		 1/* CPU data for xstormy16.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
390ff83f 5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
93fbbb04
GK		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "xstormy16-desc.h"
32#include "xstormy16-opc.h"
33#include "opintl.h"
34#include "libiberty.h"
98f70fc4 35#include "xregex.h"
93fbbb04
GK		 36
37/* Attributes. */
38
39static const CGEN_ATTR_ENTRY bool_attr[] =
40{
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44};
45
46static const CGEN_ATTR_ENTRY MACH_attr[] =
47{
48 { "base", MACH_BASE },
49 { "xstormy16", MACH_XSTORMY16 },
50 { "max", MACH_MAX },
51 { 0, 0 }
52};
53
54static const CGEN_ATTR_ENTRY ISA_attr[] =
55{
56 { "xstormy16", ISA_XSTORMY16 },
57 { "max", ISA_MAX },
58 { 0, 0 }
59};
60
61const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
62{
63 { "MACH", & MACH_attr[0], & MACH_attr[0] },
64 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
65 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
66 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
67 { "RESERVED", &bool_attr[0], &bool_attr[0] },
68 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
69 { "SIGNED", &bool_attr[0], &bool_attr[0] },
70 { 0, 0, 0 }
71};
72
73const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
74{
75 { "MACH", & MACH_attr[0], & MACH_attr[0] },
76 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
77 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
78 { "PC", &bool_attr[0], &bool_attr[0] },
79 { "PROFILE", &bool_attr[0], &bool_attr[0] },
80 { 0, 0, 0 }
81};
82
83const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
84{
85 { "MACH", & MACH_attr[0], & MACH_attr[0] },
86 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
89 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
90 { "SIGNED", &bool_attr[0], &bool_attr[0] },
91 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
92 { "RELAX", &bool_attr[0], &bool_attr[0] },
93 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
94 { 0, 0, 0 }
95};
96
97const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
98{
99 { "MACH", & MACH_attr[0], & MACH_attr[0] },
100 { "ALIAS", &bool_attr[0], &bool_attr[0] },
101 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
102 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
103 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
104 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
105 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
106 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
107 { "RELAX", &bool_attr[0], &bool_attr[0] },
108 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
109 { "PBB", &bool_attr[0], &bool_attr[0] },
110 { 0, 0, 0 }
111};
112
113/* Instruction set variants. */
114
115static const CGEN_ISA xstormy16_cgen_isa_table[] = {
116 { "xstormy16", 32, 32, 16, 32 },
117 { 0, 0, 0, 0, 0 }
118};
119
120/* Machine variants. */
121
122static const CGEN_MACH xstormy16_cgen_mach_table[] = {
123 { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
124 { 0, 0, 0, 0 }
125};
126
127static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
128{
129 { "r0", 0, {0, {0}}, 0, 0 },
130 { "r1", 1, {0, {0}}, 0, 0 },
131 { "r2", 2, {0, {0}}, 0, 0 },
132 { "r3", 3, {0, {0}}, 0, 0 },
133 { "r4", 4, {0, {0}}, 0, 0 },
134 { "r5", 5, {0, {0}}, 0, 0 },
135 { "r6", 6, {0, {0}}, 0, 0 },
136 { "r7", 7, {0, {0}}, 0, 0 },
137 { "r8", 8, {0, {0}}, 0, 0 },
138 { "r9", 9, {0, {0}}, 0, 0 },
139 { "r10", 10, {0, {0}}, 0, 0 },
140 { "r11", 11, {0, {0}}, 0, 0 },
141 { "r12", 12, {0, {0}}, 0, 0 },
142 { "r13", 13, {0, {0}}, 0, 0 },
143 { "r14", 14, {0, {0}}, 0, 0 },
144 { "r15", 15, {0, {0}}, 0, 0 },
145 { "psw", 14, {0, {0}}, 0, 0 },
146 { "sp", 15, {0, {0}}, 0, 0 }
147};
148
149CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
150{
151 & xstormy16_cgen_opval_gr_names_entries[0],
152 18,
153 0, 0, 0, 0, ""
154};
155
1951c6f7 156static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
93fbbb04
GK		 157{
158 { "r8", 0, {0, {0}}, 0, 0 },
1951c6f7
MG		 159 { "r9", 1, {0, {0}}, 0, 0 },
160 { "r10", 2, {0, {0}}, 0, 0 },
161 { "r11", 3, {0, {0}}, 0, 0 },
162 { "r12", 4, {0, {0}}, 0, 0 },
163 { "r13", 5, {0, {0}}, 0, 0 },
164 { "r14", 6, {0, {0}}, 0, 0 },
165 { "r15", 7, {0, {0}}, 0, 0 },
166 { "psw", 6, {0, {0}}, 0, 0 },
167 { "sp", 7, {0, {0}}, 0, 0 }
93fbbb04
GK		 168};
169
1951c6f7 170CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
93fbbb04 171{
1951c6f7
MG		 172 & xstormy16_cgen_opval_gr_Rb_names_entries[0],
173 10,
93fbbb04
GK		 174 0, 0, 0, 0, ""
175};
176
177static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
178{
179 { "ge", 0, {0, {0}}, 0, 0 },
180 { "nc", 1, {0, {0}}, 0, 0 },
181 { "lt", 2, {0, {0}}, 0, 0 },
182 { "c", 3, {0, {0}}, 0, 0 },
183 { "gt", 4, {0, {0}}, 0, 0 },
184 { "hi", 5, {0, {0}}, 0, 0 },
185 { "le", 6, {0, {0}}, 0, 0 },
186 { "ls", 7, {0, {0}}, 0, 0 },
187 { "pl", 8, {0, {0}}, 0, 0 },
188 { "nv", 9, {0, {0}}, 0, 0 },
189 { "mi", 10, {0, {0}}, 0, 0 },
190 { "v", 11, {0, {0}}, 0, 0 },
191 { "nz.b", 12, {0, {0}}, 0, 0 },
192 { "nz", 13, {0, {0}}, 0, 0 },
193 { "z.b", 14, {0, {0}}, 0, 0 },
194 { "z", 15, {0, {0}}, 0, 0 }
195};
196
197CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
198{
199 & xstormy16_cgen_opval_h_branchcond_entries[0],
200 16,
201 0, 0, 0, 0, ""
202};
203
204static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
205{
206 { ".b", 0, {0, {0}}, 0, 0 },
207 { ".w", 1, {0, {0}}, 0, 0 },
208 { "", 1, {0, {0}}, 0, 0 }
209};
210
211CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
212{
213 & xstormy16_cgen_opval_h_wordsize_entries[0],
214 3,
215 0, 0, 0, 0, ""
216};
217
218
219/* The hardware table. */
220
221#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
222#define A(a) (1 << CGEN_HW_##a)
223#else
224#define A(a) (1 << CGEN_HW_/**/a)
225#endif
226
227const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
228{
229 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
230 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
231 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
232 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
233 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
234 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
235 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
1951c6f7
MG		 236 { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
237 { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
93fbbb04
GK		 238 { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
239 { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
240 { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
241 { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
242 { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
243 { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
244 { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
245 { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
246 { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } },
247 { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } },
248 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
249};
250
251#undef A
252
253
254/* The instruction field table. */
255
256#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
257#define A(a) (1 << CGEN_IFLD_##a)
258#else
259#define A(a) (1 << CGEN_IFLD_/**/a)
260#endif
261
262const CGEN_IFLD xstormy16_cgen_ifld_table[] =
263{
264 { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
265 { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
266 { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
267 { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } },
268 { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
269 { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
270 { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
271 { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } },
272 { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
273 { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
274 { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
275 { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } },
276 { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
277 { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } },
278 { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
279 { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
280 { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } },
281 { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
282 { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } },
283 { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } },
284 { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } },
285 { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } },
286 { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
287 { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
288 { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
289 { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
290 { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } },
291 { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
292 { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
293 { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
294 { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
295 { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
296 { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
297 { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
298 { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
299 { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
390ff83f 300 { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
93fbbb04
GK		 301 { 0, 0, 0, 0, 0, 0, {0, {0}} }
302};
303
304#undef A
305
306
9a2e995d
GH		 307
308/* multi ifield declarations */
309
310const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
311
312
313/* multi ifield definitions */
314
315const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
316{
390ff83f
DE		 317 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } },
318 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } },
98f70fc4 319 { 0, { (const PTR) 0 } }
9a2e995d
GH		 320};
321
93fbbb04
GK		 322/* The operand table. */
323
324#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
325#define A(a) (1 << CGEN_OPERAND_##a)
326#else
327#define A(a) (1 << CGEN_OPERAND_/**/a)
328#endif
329#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
330#define OPERAND(op) XSTORMY16_OPERAND_##op
331#else
332#define OPERAND(op) XSTORMY16_OPERAND_/**/op
333#endif
334
335const CGEN_OPERAND xstormy16_cgen_operand_table[] =
336{
337/* pc: program counter */
338 { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
390ff83f 339 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
93fbbb04
GK		 340 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
341/* psw-z8: */
342 { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
98f70fc4 343 { 0, { (const PTR) 0 } },
93fbbb04
GK		 344 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
345/* psw-z16: */
346 { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
98f70fc4 347 { 0, { (const PTR) 0 } },
93fbbb04
GK		 348 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
349/* psw-cy: */
350 { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
98f70fc4 351 { 0, { (const PTR) 0 } },
93fbbb04
GK		 352 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
353/* psw-hc: */
354 { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
98f70fc4 355 { 0, { (const PTR) 0 } },
93fbbb04
GK		 356 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
357/* psw-ov: */
358 { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
98f70fc4 359 { 0, { (const PTR) 0 } },
93fbbb04
GK		 360 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
361/* psw-pt: */
362 { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
98f70fc4 363 { 0, { (const PTR) 0 } },
93fbbb04
GK		 364 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
365/* psw-s: */
366 { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
98f70fc4 367 { 0, { (const PTR) 0 } },
93fbbb04
GK		 368 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
369/* Rd: general register destination */
370 { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
390ff83f 371 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
93fbbb04
GK		 372 { 0, { (1<<MACH_BASE) } } },
373/* Rdm: general register destination */
374 { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
390ff83f 375 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
93fbbb04
GK		 376 { 0, { (1<<MACH_BASE) } } },
377/* Rm: general register for memory */
378 { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
390ff83f 379 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
93fbbb04
GK		 380 { 0, { (1<<MACH_BASE) } } },
381/* Rs: general register source */
382 { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
390ff83f 383 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
93fbbb04
GK		 384 { 0, { (1<<MACH_BASE) } } },
385/* Rb: base register */
1951c6f7 386 { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
390ff83f 387 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
93fbbb04
GK		 388 { 0, { (1<<MACH_BASE) } } },
389/* Rbj: base register for jump */
390 { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
390ff83f 391 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
93fbbb04
GK		 392 { 0, { (1<<MACH_BASE) } } },
393/* bcond2: branch condition opcode */
394 { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
390ff83f 395 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
93fbbb04
GK		 396 { 0, { (1<<MACH_BASE) } } },
397/* ws2: word size opcode */
398 { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
390ff83f 399 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
93fbbb04
GK		 400 { 0, { (1<<MACH_BASE) } } },
401/* bcond5: branch condition opcode */
402 { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
390ff83f 403 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
93fbbb04
GK		 404 { 0, { (1<<MACH_BASE) } } },
405/* imm2: 2 bit unsigned immediate */
406 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
390ff83f 407 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
93fbbb04
GK		 408 { 0, { (1<<MACH_BASE) } } },
409/* imm3: 3 bit unsigned immediate */
410 { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
390ff83f 411 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
93fbbb04
GK		 412 { 0, { (1<<MACH_BASE) } } },
413/* imm3b: 3 bit unsigned immediate for bit tests */
414 { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
390ff83f 415 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
93fbbb04
GK		 416 { 0, { (1<<MACH_BASE) } } },
417/* imm4: 4 bit unsigned immediate */
418 { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
390ff83f 419 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
93fbbb04
GK		 420 { 0, { (1<<MACH_BASE) } } },
421/* imm8: 8 bit unsigned immediate */
422 { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
390ff83f 423 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
93fbbb04
GK		 424 { 0, { (1<<MACH_BASE) } } },
425/* imm8small: 8 bit unsigned immediate */
426 { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
390ff83f 427 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
93fbbb04
GK		 428 { 0, { (1<<MACH_BASE) } } },
429/* imm12: 12 bit signed immediate */
430 { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
390ff83f 431 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
93fbbb04
GK		 432 { 0, { (1<<MACH_BASE) } } },
433/* imm16: 16 bit immediate */
434 { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
390ff83f 435 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
93fbbb04
GK		 436 { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
437/* lmem8: 8 bit unsigned immediate low memory */
438 { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
390ff83f 439 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
93fbbb04
GK		 440 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
441/* hmem8: 8 bit unsigned immediate high memory */
442 { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
390ff83f 443 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
93fbbb04
GK		 444 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
445/* rel8-2: 8 bit relative address */
446 { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
390ff83f 447 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
93fbbb04
GK		 448 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
449/* rel8-4: 8 bit relative address */
450 { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
390ff83f 451 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
93fbbb04
GK		 452 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
453/* rel12: 12 bit relative address */
454 { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
390ff83f 455 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
93fbbb04
GK		 456 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
457/* rel12a: 12 bit relative address */
458 { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
390ff83f 459 { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
93fbbb04
GK		 460 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
461/* abs24: 24 bit absolute address */
462 { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
98f70fc4 463 { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
93fbbb04
GK		 464 { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
465/* psw: program status word */
466 { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
98f70fc4 467 { 0, { (const PTR) 0 } },
93fbbb04
GK		 468 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
469/* Rpsw: N0-N3 of the program status word */
470 { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
98f70fc4 471 { 0, { (const PTR) 0 } },
93fbbb04
GK		 472 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
473/* sp: stack pointer */
474 { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
98f70fc4 475 { 0, { (const PTR) 0 } },
93fbbb04
GK		 476 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
477/* R0: R0 */
478 { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
98f70fc4 479 { 0, { (const PTR) 0 } },
93fbbb04
GK		 480 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
481/* R1: R1 */
482 { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
98f70fc4 483 { 0, { (const PTR) 0 } },
93fbbb04
GK		 484 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
485/* R2: R2 */
486 { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
98f70fc4 487 { 0, { (const PTR) 0 } },
93fbbb04
GK		 488 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
489/* R8: R8 */
490 { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
98f70fc4 491 { 0, { (const PTR) 0 } },
93fbbb04 492 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
98f70fc4
AM		 493/* sentinel */
494 { 0, 0, 0, 0, 0,
495 { 0, { (const PTR) 0 } },
496 { 0, { 0 } } }
93fbbb04
GK		 497};
498
499#undef A
500
501
502/* The instruction table. */
503
504#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
505#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
506#define A(a) (1 << CGEN_INSN_##a)
507#else
508#define A(a) (1 << CGEN_INSN_/**/a)
509#endif
510
511static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
512{
513 /* Special null first entry.
514 A `num' value of zero is thus invalid.
515 Also, the special `invalid' insn resides here. */
516 { 0, 0, 0, 0, {0, {0}} },
517/* mov$ws2 $lmem8,#$imm16 */
518 {
519 XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
520 { 0, { (1<<MACH_BASE) } }
521 },
522/* mov$ws2 $hmem8,#$imm16 */
523 {
524 XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
525 { 0, { (1<<MACH_BASE) } }
526 },
527/* mov$ws2 $Rm,$lmem8 */
528 {
529 XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
530 { 0, { (1<<MACH_BASE) } }
531 },
532/* mov$ws2 $Rm,$hmem8 */
533 {
534 XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
535 { 0, { (1<<MACH_BASE) } }
536 },
537/* mov$ws2 $lmem8,$Rm */
538 {
539 XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
540 { 0, { (1<<MACH_BASE) } }
541 },
542/* mov$ws2 $hmem8,$Rm */
543 {
544 XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
545 { 0, { (1<<MACH_BASE) } }
546 },
547/* mov$ws2 $Rdm,($Rs) */
548 {
549 XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
550 { 0, { (1<<MACH_BASE) } }
551 },
552/* mov$ws2 $Rdm,($Rs++) */
553 {
554 XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
555 { 0, { (1<<MACH_BASE) } }
556 },
557/* mov$ws2 $Rdm,(--$Rs) */
558 {
559 XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
560 { 0, { (1<<MACH_BASE) } }
561 },
562/* mov$ws2 ($Rs),$Rdm */
563 {
564 XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
565 { 0, { (1<<MACH_BASE) } }
566 },
567/* mov$ws2 ($Rs++),$Rdm */
568 {
569 XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
570 { 0, { (1<<MACH_BASE) } }
571 },
572/* mov$ws2 (--$Rs),$Rdm */
573 {
574 XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
575 { 0, { (1<<MACH_BASE) } }
576 },
577/* mov$ws2 $Rdm,($Rs,$imm12) */
578 {
579 XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
580 { 0, { (1<<MACH_BASE) } }
581 },
582/* mov$ws2 $Rdm,($Rs++,$imm12) */
583 {
584 XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
585 { 0, { (1<<MACH_BASE) } }
586 },
587/* mov$ws2 $Rdm,(--$Rs,$imm12) */
588 {
589 XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
590 { 0, { (1<<MACH_BASE) } }
591 },
592/* mov$ws2 ($Rs,$imm12),$Rdm */
593 {
594 XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
595 { 0, { (1<<MACH_BASE) } }
596 },
597/* mov$ws2 ($Rs++,$imm12),$Rdm */
598 {
599 XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
600 { 0, { (1<<MACH_BASE) } }
601 },
602/* mov$ws2 (--$Rs,$imm12),$Rdm */
603 {
604 XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
605 { 0, { (1<<MACH_BASE) } }
606 },
607/* mov $Rd,$Rs */
608 {
609 XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
610 { 0, { (1<<MACH_BASE) } }
611 },
612/* mov.w Rx,#$imm8 */
613 {
614 XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
615 { 0, { (1<<MACH_BASE) } }
616 },
617/* mov.w $Rm,#$imm8small */
618 {
619 XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
620 { 0, { (1<<MACH_BASE) } }
621 },
622/* mov.w $Rd,#$imm16 */
623 {
624 XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
625 { 0, { (1<<MACH_BASE) } }
626 },
627/* mov.b $Rd,RxL */
628 {
629 XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
630 { 0, { (1<<MACH_BASE) } }
631 },
632/* mov.b $Rd,RxH */
633 {
634 XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
635 { 0, { (1<<MACH_BASE) } }
636 },
637/* movf$ws2 $Rdm,($Rs) */
638 {
639 XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
640 { 0, { (1<<MACH_BASE) } }
641 },
642/* movf$ws2 $Rdm,($Rs++) */
643 {
644 XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
645 { 0, { (1<<MACH_BASE) } }
646 },
647/* movf$ws2 $Rdm,(--$Rs) */
648 {
649 XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
650 { 0, { (1<<MACH_BASE) } }
651 },
652/* movf$ws2 ($Rs),$Rdm */
653 {
654 XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
655 { 0, { (1<<MACH_BASE) } }
656 },
657/* movf$ws2 ($Rs++),$Rdm */
658 {
659 XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
660 { 0, { (1<<MACH_BASE) } }
661 },
662/* movf$ws2 (--$Rs),$Rdm */
663 {
664 XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
665 { 0, { (1<<MACH_BASE) } }
666 },
667/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
668 {
669 XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
670 { 0, { (1<<MACH_BASE) } }
671 },
672/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
673 {
674 XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
675 { 0, { (1<<MACH_BASE) } }
676 },
677/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
678 {
679 XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
680 { 0, { (1<<MACH_BASE) } }
681 },
682/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
683 {
684 XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
685 { 0, { (1<<MACH_BASE) } }
686 },
687/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
688 {
689 XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
690 { 0, { (1<<MACH_BASE) } }
691 },
692/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
693 {
694 XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
695 { 0, { (1<<MACH_BASE) } }
696 },
697/* mask $Rd,$Rs */
698 {
699 XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
700 { 0, { (1<<MACH_BASE) } }
701 },
702/* mask $Rd,#$imm16 */
703 {
704 XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
705 { 0, { (1<<MACH_BASE) } }
706 },
707/* push $Rd */
708 {
709 XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
710 { 0, { (1<<MACH_BASE) } }
711 },
712/* pop $Rd */
713 {
714 XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
715 { 0, { (1<<MACH_BASE) } }
716 },
717/* swpn $Rd */
718 {
719 XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
720 { 0, { (1<<MACH_BASE) } }
721 },
722/* swpb $Rd */
723 {
724 XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
725 { 0, { (1<<MACH_BASE) } }
726 },
727/* swpw $Rd,$Rs */
728 {
729 XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
730 { 0, { (1<<MACH_BASE) } }
731 },
732/* and $Rd,$Rs */
733 {
734 XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
735 { 0, { (1<<MACH_BASE) } }
736 },
737/* and Rx,#$imm8 */
738 {
739 XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
740 { 0, { (1<<MACH_BASE) } }
741 },
742/* and $Rd,#$imm16 */
743 {
744 XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
745 { 0, { (1<<MACH_BASE) } }
746 },
747/* or $Rd,$Rs */
748 {
749 XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
750 { 0, { (1<<MACH_BASE) } }
751 },
752/* or Rx,#$imm8 */
753 {
754 XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
755 { 0, { (1<<MACH_BASE) } }
756 },
757/* or $Rd,#$imm16 */
758 {
759 XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
760 { 0, { (1<<MACH_BASE) } }
761 },
762/* xor $Rd,$Rs */
763 {
764 XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
765 { 0, { (1<<MACH_BASE) } }
766 },
767/* xor Rx,#$imm8 */
768 {
769 XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
770 { 0, { (1<<MACH_BASE) } }
771 },
772/* xor $Rd,#$imm16 */
773 {
774 XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
775 { 0, { (1<<MACH_BASE) } }
776 },
777/* not $Rd */
778 {
779 XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
780 { 0, { (1<<MACH_BASE) } }
781 },
782/* add $Rd,$Rs */
783 {
784 XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
785 { 0, { (1<<MACH_BASE) } }
786 },
787/* add $Rd,#$imm4 */
788 {
789 XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
790 { 0, { (1<<MACH_BASE) } }
791 },
792/* add Rx,#$imm8 */
793 {
794 XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
795 { 0, { (1<<MACH_BASE) } }
796 },
797/* add $Rd,#$imm16 */
798 {
799 XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
800 { 0, { (1<<MACH_BASE) } }
801 },
802/* adc $Rd,$Rs */
803 {
804 XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
805 { 0, { (1<<MACH_BASE) } }
806 },
807/* adc $Rd,#$imm4 */
808 {
809 XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
810 { 0, { (1<<MACH_BASE) } }
811 },
812/* adc Rx,#$imm8 */
813 {
814 XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
815 { 0, { (1<<MACH_BASE) } }
816 },
817/* adc $Rd,#$imm16 */
818 {
819 XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
820 { 0, { (1<<MACH_BASE) } }
821 },
822/* sub $Rd,$Rs */
823 {
824 XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
825 { 0, { (1<<MACH_BASE) } }
826 },
827/* sub $Rd,#$imm4 */
828 {
829 XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
830 { 0, { (1<<MACH_BASE) } }
831 },
832/* sub Rx,#$imm8 */
833 {
834 XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
835 { 0, { (1<<MACH_BASE) } }
836 },
837/* sub $Rd,#$imm16 */
838 {
839 XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
840 { 0, { (1<<MACH_BASE) } }
841 },
842/* sbc $Rd,$Rs */
843 {
844 XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
845 { 0, { (1<<MACH_BASE) } }
846 },
847/* sbc $Rd,#$imm4 */
848 {
849 XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
850 { 0, { (1<<MACH_BASE) } }
851 },
852/* sbc Rx,#$imm8 */
853 {
854 XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
855 { 0, { (1<<MACH_BASE) } }
856 },
857/* sbc $Rd,#$imm16 */
858 {
859 XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
860 { 0, { (1<<MACH_BASE) } }
861 },
862/* inc $Rd,#$imm2 */
863 {
864 XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
865 { 0, { (1<<MACH_BASE) } }
866 },
867/* dec $Rd,#$imm2 */
868 {
869 XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
870 { 0, { (1<<MACH_BASE) } }
871 },
872/* rrc $Rd,$Rs */
873 {
874 XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
875 { 0, { (1<<MACH_BASE) } }
876 },
877/* rrc $Rd,#$imm4 */
878 {
879 XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
880 { 0, { (1<<MACH_BASE) } }
881 },
882/* rlc $Rd,$Rs */
883 {
884 XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
885 { 0, { (1<<MACH_BASE) } }
886 },
887/* rlc $Rd,#$imm4 */
888 {
889 XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
890 { 0, { (1<<MACH_BASE) } }
891 },
892/* shr $Rd,$Rs */
893 {
894 XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
895 { 0, { (1<<MACH_BASE) } }
896 },
897/* shr $Rd,#$imm4 */
898 {
899 XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
900 { 0, { (1<<MACH_BASE) } }
901 },
902/* shl $Rd,$Rs */
903 {
904 XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
905 { 0, { (1<<MACH_BASE) } }
906 },
907/* shl $Rd,#$imm4 */
908 {
909 XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
910 { 0, { (1<<MACH_BASE) } }
911 },
912/* asr $Rd,$Rs */
913 {
914 XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
915 { 0, { (1<<MACH_BASE) } }
916 },
917/* asr $Rd,#$imm4 */
918 {
919 XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
920 { 0, { (1<<MACH_BASE) } }
921 },
922/* set1 $Rd,#$imm4 */
923 {
924 XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
925 { 0, { (1<<MACH_BASE) } }
926 },
927/* set1 $Rd,$Rs */
928 {
929 XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
930 { 0, { (1<<MACH_BASE) } }
931 },
932/* set1 $lmem8,#$imm3 */
933 {
934 XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
935 { 0, { (1<<MACH_BASE) } }
936 },
937/* set1 $hmem8,#$imm3 */
938 {
939 XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
940 { 0, { (1<<MACH_BASE) } }
941 },
942/* clr1 $Rd,#$imm4 */
943 {
944 XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
945 { 0, { (1<<MACH_BASE) } }
946 },
947/* clr1 $Rd,$Rs */
948 {
949 XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
950 { 0, { (1<<MACH_BASE) } }
951 },
952/* clr1 $lmem8,#$imm3 */
953 {
954 XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
955 { 0, { (1<<MACH_BASE) } }
956 },
957/* clr1 $hmem8,#$imm3 */
958 {
959 XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
960 { 0, { (1<<MACH_BASE) } }
961 },
962/* cbw $Rd */
963 {
964 XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
965 { 0, { (1<<MACH_BASE) } }
966 },
967/* rev $Rd */
968 {
969 XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
970 { 0, { (1<<MACH_BASE) } }
971 },
972/* b$bcond5 $Rd,$Rs,$rel12 */
973 {
974 XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
975 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
976 },
977/* b$bcond5 $Rm,#$imm8,$rel12 */
978 {
979 XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
980 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
981 },
982/* b$bcond2 Rx,#$imm16,${rel8-4} */
983 {
984 XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
985 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
986 },
987/* bn $Rd,#$imm4,$rel12 */
988 {
989 XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
990 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
991 },
992/* bn $Rd,$Rs,$rel12 */
993 {
994 XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
995 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
996 },
997/* bn $lmem8,#$imm3b,$rel12 */
998 {
999 XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
1000 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1001 },
1002/* bn $hmem8,#$imm3b,$rel12 */
1003 {
1004 XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
1005 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1006 },
1007/* bp $Rd,#$imm4,$rel12 */
1008 {
1009 XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
1010 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1011 },
1012/* bp $Rd,$Rs,$rel12 */
1013 {
1014 XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
1015 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1016 },
1017/* bp $lmem8,#$imm3b,$rel12 */
1018 {
1019 XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
1020 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1021 },
1022/* bp $hmem8,#$imm3b,$rel12 */
1023 {
1024 XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
1025 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1026 },
1027/* b$bcond2 ${rel8-2} */
1028 {
1029 XSTORMY16_INSN_BCC, "bcc", "b", 16,
1030 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1031 },
1032/* br $Rd */
1033 {
1034 XSTORMY16_INSN_BGR, "bgr", "br", 16,
1035 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1036 },
1037/* br $rel12a */
1038 {
1039 XSTORMY16_INSN_BR, "br", "br", 16,
1040 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1041 },
1042/* jmp $Rbj,$Rd */
1043 {
1044 XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
1045 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1046 },
1047/* jmpf $abs24 */
1048 {
1049 XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
1050 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1051 },
1052/* callr $Rd */
1053 {
1054 XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
1055 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1056 },
1057/* callr $rel12a */
1058 {
1059 XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
1060 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1061 },
1062/* call $Rbj,$Rd */
1063 {
1064 XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
1065 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1066 },
1067/* callf $abs24 */
1068 {
1069 XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
1070 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1071 },
1072/* icallr $Rd */
1073 {
1074 XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
1075 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1076 },
1077/* icall $Rbj,$Rd */
1078 {
1079 XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
1080 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1081 },
1082/* icallf $abs24 */
1083 {
1084 XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
1085 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1086 },
1087/* iret */
1088 {
1089 XSTORMY16_INSN_IRET, "iret", "iret", 16,
1090 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1091 },
1092/* ret */
1093 {
1094 XSTORMY16_INSN_RET, "ret", "ret", 16,
1095 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1096 },
1097/* mul */
1098 {
1099 XSTORMY16_INSN_MUL, "mul", "mul", 16,
1100 { 0, { (1<<MACH_BASE) } }
1101 },
1102/* div */
1103 {
1104 XSTORMY16_INSN_DIV, "div", "div", 16,
1105 { 0, { (1<<MACH_BASE) } }
1106 },
193eb15d
DD		 1107/* sdiv */
1108 {
1109 XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16,
1110 { 0, { (1<<MACH_BASE) } }
1111 },
1112/* sdivlh */
1113 {
1114 XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16,
1115 { 0, { (1<<MACH_BASE) } }
1116 },
1117/* divlh */
1118 {
1119 XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16,
1120 { 0, { (1<<MACH_BASE) } }
1121 },
390ff83f
DE		 1122/* reset */
1123 {
1124 XSTORMY16_INSN_RESET, "reset", "reset", 16,
1125 { 0, { (1<<MACH_BASE) } }
1126 },
93fbbb04
GK		 1127/* nop */
1128 {
1129 XSTORMY16_INSN_NOP, "nop", "nop", 16,
1130 { 0, { (1<<MACH_BASE) } }
1131 },
1132/* halt */
1133 {
1134 XSTORMY16_INSN_HALT, "halt", "halt", 16,
1135 { 0, { (1<<MACH_BASE) } }
1136 },
1137/* hold */
1138 {
1139 XSTORMY16_INSN_HOLD, "hold", "hold", 16,
1140 { 0, { (1<<MACH_BASE) } }
1141 },
1951c6f7
MG		 1142/* holdx */
1143 {
1144 XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
1145 { 0, { (1<<MACH_BASE) } }
1146 },
93fbbb04
GK		 1147/* brk */
1148 {
1149 XSTORMY16_INSN_BRK, "brk", "brk", 16,
1150 { 0, { (1<<MACH_BASE) } }
1151 },
1152/* --unused-- */
1153 {
1154 XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
1155 { 0, { (1<<MACH_BASE) } }
1156 },
1157};
1158
1159#undef OP
1160#undef A
1161
1162/* Initialize anything needed to be done once, before any cpu_open call. */
1163static void init_tables PARAMS ((void));
1164
1165static void
1166init_tables ()
1167{
1168}
1169
1170static const CGEN_MACH * lookup_mach_via_bfd_name
1171 PARAMS ((const CGEN_MACH *, const char *));
1172static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
1173static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
1174static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1175static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
1176static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1177
1178/* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */
1179
1180static const CGEN_MACH *
1181lookup_mach_via_bfd_name (table, name)
1182 const CGEN_MACH *table;
1183 const char *name;
1184{
1185 while (table->name)
1186 {
1187 if (strcmp (name, table->bfd_name) == 0)
1188 return table;
1189 ++table;
1190 }
1191 abort ();
1192}
1193
1194/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1195
1196static void
1197build_hw_table (cd)
1198 CGEN_CPU_TABLE *cd;
1199{
1200 int i;
1201 int machs = cd->machs;
1202 const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
1203 /* MAX_HW is only an upper bound on the number of selected entries.
1204 However each entry is indexed by it's enum so there can be holes in
1205 the table. */
1206 const CGEN_HW_ENTRY **selected =
1207 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1208
1209 cd->hw_table.init_entries = init;
1210 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1211 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1212 /* ??? For now we just use machs to determine which ones we want. */
1213 for (i = 0; init[i].name != NULL; ++i)
1214 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1215 & machs)
1216 selected[init[i].type] = &init[i];
1217 cd->hw_table.entries = selected;
1218 cd->hw_table.num_entries = MAX_HW;
1219}
1220
1221/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1222
1223static void
1224build_ifield_table (cd)
1225 CGEN_CPU_TABLE *cd;
1226{
1227 cd->ifld_table = & xstormy16_cgen_ifld_table[0];
1228}
1229
1230/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1231
1232static void
1233build_operand_table (cd)
1234 CGEN_CPU_TABLE *cd;
1235{
1236 int i;
1237 int machs = cd->machs;
1238 const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
1239 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1240 However each entry is indexed by it's enum so there can be holes in
1241 the table. */
1242 const CGEN_OPERAND **selected =
1243 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1244
1245 cd->operand_table.init_entries = init;
1246 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1247 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1248 /* ??? For now we just use mach to determine which ones we want. */
1249 for (i = 0; init[i].name != NULL; ++i)
1250 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1251 & machs)
1252 selected[init[i].type] = &init[i];
1253 cd->operand_table.entries = selected;
1254 cd->operand_table.num_entries = MAX_OPERANDS;
1255}
1256
1257/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
1258 ??? This could leave out insns not supported by the specified mach/isa,
1259 but that would cause errors like "foo only supported by bar" to become
1260 "unknown insn", so for now we include all insns and require the app to
1261 do the checking later.
1262 ??? On the other hand, parsing of such insns may require their hardware or
1263 operand elements to be in the table [which they mightn't be]. */
1264
1265static void
1266build_insn_table (cd)
1267 CGEN_CPU_TABLE *cd;
1268{
1269 int i;
1270 const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
1271 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1272
1273 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1274 for (i = 0; i < MAX_INSNS; ++i)
1275 insns[i].base = &ib[i];
1276 cd->insn_table.init_entries = insns;
1277 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1278 cd->insn_table.num_init_entries = MAX_INSNS;
1279}
1280
1281/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */
1282
1283static void
1284xstormy16_cgen_rebuild_tables (cd)
1285 CGEN_CPU_TABLE *cd;
1286{
1287 int i;
1288 unsigned int isas = cd->isas;
1289 unsigned int machs = cd->machs;
1290
1291 cd->int_insn_p = CGEN_INT_INSN_P;
1292
1293 /* Data derived from the isa spec. */
1294#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1295 cd->default_insn_bitsize = UNSET;
1296 cd->base_insn_bitsize = UNSET;
1297 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1298 cd->max_insn_bitsize = 0;
1299 for (i = 0; i < MAX_ISAS; ++i)
1300 if (((1 << i) & isas) != 0)
1301 {
1302 const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
1303
9a2e995d
GH		 1304 /* Default insn sizes of all selected isas must be
1305 equal or we set the result to 0, meaning "unknown". */
93fbbb04
GK		 1306 if (cd->default_insn_bitsize == UNSET)
1307 cd->default_insn_bitsize = isa->default_insn_bitsize;
1308 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1309 ; /* this is ok */
1310 else
1311 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1312
9a2e995d
GH		 1313 /* Base insn sizes of all selected isas must be equal
1314 or we set the result to 0, meaning "unknown". */
93fbbb04
GK		 1315 if (cd->base_insn_bitsize == UNSET)
1316 cd->base_insn_bitsize = isa->base_insn_bitsize;
1317 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1318 ; /* this is ok */
1319 else
1320 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1321
1322 /* Set min,max insn sizes. */
1323 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1324 cd->min_insn_bitsize = isa->min_insn_bitsize;
1325 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1326 cd->max_insn_bitsize = isa->max_insn_bitsize;
1327 }
1328
1329 /* Data derived from the mach spec. */
1330 for (i = 0; i < MAX_MACHS; ++i)
1331 if (((1 << i) & machs) != 0)
1332 {
1333 const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
1334
1335 if (mach->insn_chunk_bitsize != 0)
1336 {
1337 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1338 {
1339 fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1340 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1341 abort ();
1342 }
1343
1344 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1345 }
1346 }
1347
1348 /* Determine which hw elements are used by MACH. */
1349 build_hw_table (cd);
1350
1351 /* Build the ifield table. */
1352 build_ifield_table (cd);
1353
1354 /* Determine which operands are used by MACH/ISA. */
1355 build_operand_table (cd);
1356
1357 /* Build the instruction table. */
1358 build_insn_table (cd);
1359}
1360
1361/* Initialize a cpu table and return a descriptor.
1362 It's much like opening a file, and must be the first function called.
1363 The arguments are a set of (type/value) pairs, terminated with
1364 CGEN_CPU_OPEN_END.
1365
1366 Currently supported values:
1367 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1368 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1369 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1370 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1371 CGEN_CPU_OPEN_END: terminates arguments
1372
1373 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1374 precluded.
1375
1376 ??? We only support ISO C stdargs here, not K&R.
1377 Laziness, plus experiment to see if anything requires K&R - eventually
1378 K&R will no longer be supported - e.g. GDB is currently trying this. */
1379
1380CGEN_CPU_DESC
1381xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1382{
1383 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1384 static int init_p;
1385 unsigned int isas = 0; /* 0 = "unspecified" */
1386 unsigned int machs = 0; /* 0 = "unspecified" */
1387 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1388 va_list ap;
1389
1390 if (! init_p)
1391 {
1392 init_tables ();
1393 init_p = 1;
1394 }
1395
1396 memset (cd, 0, sizeof (*cd));
1397
1398 va_start (ap, arg_type);
1399 while (arg_type != CGEN_CPU_OPEN_END)
1400 {
1401 switch (arg_type)
1402 {
1403 case CGEN_CPU_OPEN_ISAS :
1404 isas = va_arg (ap, unsigned int);
1405 break;
1406 case CGEN_CPU_OPEN_MACHS :
1407 machs = va_arg (ap, unsigned int);
1408 break;
1409 case CGEN_CPU_OPEN_BFDMACH :
1410 {
1411 const char *name = va_arg (ap, const char *);
1412 const CGEN_MACH *mach =
1413 lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
1414
1415 machs |= 1 << mach->num;
1416 break;
1417 }
1418 case CGEN_CPU_OPEN_ENDIAN :
1419 endian = va_arg (ap, enum cgen_endian);
1420 break;
1421 default :
1422 fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
1423 arg_type);
1424 abort (); /* ??? return NULL? */
1425 }
1426 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1427 }
1428 va_end (ap);
1429
1430 /* mach unspecified means "all" */
1431 if (machs == 0)
1432 machs = (1 << MAX_MACHS) - 1;
1433 /* base mach is always selected */
1434 machs |= 1;
1435 /* isa unspecified means "all" */
1436 if (isas == 0)
1437 isas = (1 << MAX_ISAS) - 1;
1438 if (endian == CGEN_ENDIAN_UNKNOWN)
1439 {
1440 /* ??? If target has only one, could have a default. */
1441 fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
1442 abort ();
1443 }
1444
1445 cd->isas = isas;
1446 cd->machs = machs;
1447 cd->endian = endian;
1448 /* FIXME: for the sparc case we can determine insn-endianness statically.
1449 The worry here is where both data and insn endian can be independently
1450 chosen, in which case this function will need another argument.
1451 Actually, will want to allow for more arguments in the future anyway. */
1452 cd->insn_endian = endian;
1453
1454 /* Table (re)builder. */
1455 cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
1456 xstormy16_cgen_rebuild_tables (cd);
1457
1458 /* Default to not allowing signed overflow. */
1459 cd->signed_overflow_ok_p = 0;
1460
1461 return (CGEN_CPU_DESC) cd;
1462}
1463
1464/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1465 MACH_NAME is the bfd name of the mach. */
1466
1467CGEN_CPU_DESC
1468xstormy16_cgen_cpu_open_1 (mach_name, endian)
1469 const char *mach_name;
1470 enum cgen_endian endian;
1471{
1472 return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1473 CGEN_CPU_OPEN_ENDIAN, endian,
1474 CGEN_CPU_OPEN_END);
1475}
1476
1477/* Close a cpu table.
1478 ??? This can live in a machine independent file, but there's currently
1479 no place to put this file (there's no libcgen). libopcodes is the wrong
1480 place as some simulator ports use this but they don't use libopcodes. */
1481
1482void
1483xstormy16_cgen_cpu_close (cd)
1484 CGEN_CPU_DESC cd;
1485{
a978a3e5 1486 unsigned int i;
98f70fc4 1487 const CGEN_INSN *insns;
a978a3e5
NC		 1488
1489 if (cd->macro_insn_table.init_entries)
1490 {
1491 insns = cd->macro_insn_table.init_entries;
1492 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1493 {
1494 if (CGEN_INSN_RX ((insns)))
98f70fc4 1495 regfree (CGEN_INSN_RX (insns));
a978a3e5
NC		 1496 }
1497 }
1498
1499 if (cd->insn_table.init_entries)
1500 {
1501 insns = cd->insn_table.init_entries;
1502 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1503 {
1504 if (CGEN_INSN_RX (insns))
98f70fc4 1505 regfree (CGEN_INSN_RX (insns));
a978a3e5
NC		 1506 }
1507 }
1508
1509
1510
1511 if (cd->macro_insn_table.init_entries)
1512 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1513
93fbbb04
GK		 1514 if (cd->insn_table.init_entries)
1515 free ((CGEN_INSN *) cd->insn_table.init_entries);
a978a3e5 1516
93fbbb04
GK		 1517 if (cd->hw_table.entries)
1518 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
a978a3e5
NC		 1519
1520 if (cd->operand_table.entries)
1521 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1522
93fbbb04
GK		 1523 free (cd);
1524}
1525
GDB Binutils - Deliverables
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