[deliverable/binutils-gdb.git] / opcodes / xstormy16-dis.c

/* Disassembler interface for targets using CGEN. -*- C -*-
   CGEN: Cpu tools GENerator

THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't

Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.

This file is part of the GNU Binutils and GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

/* ??? Eventually more and more of this stuff can go to cpu-independent files.
   Keep that in mind.  */

#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "xstormy16-desc.h"
#include "xstormy16-opc.h"
#include "opintl.h"

/* Default text to print if an instruction isn't recognized.  */
#define UNKNOWN_INSN_MSG _("*unknown*")

static void print_normal
     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
static void print_address
     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
static void print_keyword
     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
static void print_insn_normal
     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
	      bfd_vma, int));
static int print_insn
     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
static int default_print_insn
     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
static int read_insn
     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
	      CGEN_EXTRACT_INFO *, unsigned long *));
\f
/* -- disassembler routines inserted here */


void xstormy16_cgen_print_operand
  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
           void const *, bfd_vma, int));

/* Main entry point for printing operands.
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
   of dis-asm.h on cgen.h.

   This function is basically just a big switch statement.  Earlier versions
   used tables to look up the function to use, but
   - if the table contains both assembler and disassembler functions then
     the disassembler contains much of the assembler and vice-versa,
   - there's a lot of inlining possibilities as things grow,
   - using a switch statement avoids the function call overhead.

   This function could be moved into `print_insn_normal', but keeping it
   separate makes clear the interface between `print_insn_normal' and each of
   the handlers.  */

void
xstormy16_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     CGEN_CPU_DESC cd;
     int opindex;
     PTR xinfo;
     CGEN_FIELDS *fields;
     void const *attrs ATTRIBUTE_UNUSED;
     bfd_vma pc;
     int length;
{
 disassemble_info *info = (disassemble_info *) xinfo;

  switch (opindex)
    {
    case XSTORMY16_OPERAND_RB :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0);
      break;
    case XSTORMY16_OPERAND_RBJ :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0);
      break;
    case XSTORMY16_OPERAND_RD :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0);
      break;
    case XSTORMY16_OPERAND_RDM :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0);
      break;
    case XSTORMY16_OPERAND_RM :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0);
      break;
    case XSTORMY16_OPERAND_RS :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0);
      break;
    case XSTORMY16_OPERAND_ABS24 :
      print_normal (cd, info, fields->f_abs24, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
      break;
    case XSTORMY16_OPERAND_BCOND2 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0);
      break;
    case XSTORMY16_OPERAND_BCOND5 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0);
      break;
    case XSTORMY16_OPERAND_HMEM8 :
      print_normal (cd, info, fields->f_hmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM12 :
      print_normal (cd, info, fields->f_imm12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM16 :
      print_normal (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM2 :
      print_normal (cd, info, fields->f_imm2, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM3 :
      print_normal (cd, info, fields->f_imm3, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM3B :
      print_normal (cd, info, fields->f_imm3b, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM4 :
      print_normal (cd, info, fields->f_imm4, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM8 :
      print_normal (cd, info, fields->f_imm8, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM8SMALL :
      print_normal (cd, info, fields->f_imm8, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_LMEM8 :
      print_normal (cd, info, fields->f_lmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL12 :
      print_normal (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL12A :
      print_normal (cd, info, fields->f_rel12a, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL8_2 :
      print_normal (cd, info, fields->f_rel8_2, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL8_4 :
      print_normal (cd, info, fields->f_rel8_4, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_WS2 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0);
      break;

    default :
      /* xgettext:c-format */
      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
	       opindex);
    abort ();
  }
}

cgen_print_fn * const xstormy16_cgen_print_handlers[] = 
{
  print_insn_normal,
};


void
xstormy16_cgen_init_dis (cd)
     CGEN_CPU_DESC cd;
{
  xstormy16_cgen_init_opcode_table (cd);
  xstormy16_cgen_init_ibld_table (cd);
  cd->print_handlers = & xstormy16_cgen_print_handlers[0];
  cd->print_operand = xstormy16_cgen_print_operand;
}

\f
/* Default print handler.  */

static void
print_normal (cd, dis_info, value, attrs, pc, length)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     PTR dis_info;
     long value;
     unsigned int attrs;
     bfd_vma pc ATTRIBUTE_UNUSED;
     int length ATTRIBUTE_UNUSED;
{
  disassemble_info *info = (disassemble_info *) dis_info;

#ifdef CGEN_PRINT_NORMAL
  CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
#endif

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", value);
}

/* Default address handler.  */

static void
print_address (cd, dis_info, value, attrs, pc, length)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     PTR dis_info;
     bfd_vma value;
     unsigned int attrs;
     bfd_vma pc ATTRIBUTE_UNUSED;
     int length ATTRIBUTE_UNUSED;
{
  disassemble_info *info = (disassemble_info *) dis_info;

#ifdef CGEN_PRINT_ADDRESS
  CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
#endif

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
}

/* Keyword print handler.  */

static void
print_keyword (cd, dis_info, keyword_table, value, attrs)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     PTR dis_info;
     CGEN_KEYWORD *keyword_table;
     long value;
     unsigned int attrs ATTRIBUTE_UNUSED;
{
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_KEYWORD_ENTRY *ke;

  ke = cgen_keyword_lookup_value (keyword_table, value);
  if (ke != NULL)
    (*info->fprintf_func) (info->stream, "%s", ke->name);
  else
    (*info->fprintf_func) (info->stream, "???");
}
\f
/* Default insn printer.

   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
   about disassemble_info.  */

static void
print_insn_normal (cd, dis_info, insn, fields, pc, length)
     CGEN_CPU_DESC cd;
     PTR dis_info;
     const CGEN_INSN *insn;
     CGEN_FIELDS *fields;
     bfd_vma pc;
     int length;
{
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_SYNTAX_CHAR_TYPE *syn;

  CGEN_INIT_PRINT (cd);

  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
    {
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	  continue;
	}
      if (CGEN_SYNTAX_CHAR_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
	  continue;
	}

      /* We have an operand.  */
      xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
				 fields, CGEN_INSN_ATTRS (insn), pc, length);
    }
}
\f
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
   the extract info.
   Returns 0 if all is well, non-zero otherwise.  */

static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
     bfd_vma pc;
     disassemble_info *info;
     char *buf;
     int buflen;
     CGEN_EXTRACT_INFO *ex_info;
     unsigned long *insn_value;
{
  int status = (*info->read_memory_func) (pc, buf, buflen, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  ex_info->dis_info = info;
  ex_info->valid = (1 << buflen) - 1;
  ex_info->insn_bytes = buf;

  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
  return 0;
}

/* Utility to print an insn.
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occurs fetching data (memory_error_func will have
   been called).  */

static int
print_insn (cd, pc, info, buf, buflen)
     CGEN_CPU_DESC cd;
     bfd_vma pc;
     disassemble_info *info;
     char *buf;
     unsigned int buflen;
{
  CGEN_INSN_INT insn_value;
  const CGEN_INSN_LIST *insn_list;
  CGEN_EXTRACT_INFO ex_info;
  int basesize;

  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
  basesize = cd->base_insn_bitsize < buflen * 8 ?
                                     cd->base_insn_bitsize : buflen * 8;
  insn_value = cgen_get_insn_value (cd, buf, basesize);


  /* Fill in ex_info fields like read_insn would.  Don't actually call
     read_insn, since the incoming buffer is already read (and possibly
     modified a la m32r).  */
  ex_info.valid = (1 << buflen) - 1;
  ex_info.dis_info = info;
  ex_info.insn_bytes = buf;

  /* The instructions are stored in hash lists.
     Pick the first one and keep trying until we find the right one.  */

  insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
  while (insn_list != NULL)
    {
      const CGEN_INSN *insn = insn_list->insn;
      CGEN_FIELDS fields;
      int length;
      unsigned long insn_value_cropped;

#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
      /* Supported by this cpu?  */
      if (! xstormy16_cgen_insn_supported (cd, insn))
        {
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	  continue;
        }
#endif

      /* Basic bit mask must be correct.  */
      /* ??? May wish to allow target to defer this check until the extract
	 handler.  */

      /* Base size may exceed this instruction's size.  Extract the
         relevant part from the buffer. */
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
					   info->endian == BFD_ENDIAN_BIG);
      else
	insn_value_cropped = insn_value;

      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	  == CGEN_INSN_BASE_VALUE (insn))
	{
	  /* Printing is handled in two passes.  The first pass parses the
	     machine insn and extracts the fields.  The second pass prints
	     them.  */

	  /* Make sure the entire insn is loaded into insn_value, if it
	     can fit.  */
	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	    {
	      unsigned long full_insn_value;
	      int rc = read_insn (cd, pc, info, buf,
				  CGEN_INSN_BITSIZE (insn) / 8,
				  & ex_info, & full_insn_value);
	      if (rc != 0)
		return rc;
	      length = CGEN_EXTRACT_FN (cd, insn)
		(cd, insn, &ex_info, full_insn_value, &fields, pc);
	    }
	  else
	    length = CGEN_EXTRACT_FN (cd, insn)
	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);

	  /* length < 0 -> error */
	  if (length < 0)
	    return length;
	  if (length > 0)
	    {
	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
	      /* length is in bits, result is in bytes */
	      return length / 8;
	    }
	}

      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
    }

  return 0;
}

/* Default value for CGEN_PRINT_INSN.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occured fetching bytes.  */

#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
#endif

static int
default_print_insn (cd, pc, info)
     CGEN_CPU_DESC cd;
     bfd_vma pc;
     disassemble_info *info;
{
  char buf[CGEN_MAX_INSN_SIZE];
  int buflen;
  int status;

  /* Attempt to read the base part of the insn.  */
  buflen = cd->base_insn_bitsize / 8;
  status = (*info->read_memory_func) (pc, buf, buflen, info);

  /* Try again with the minimum part, if min < base.  */
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
    {
      buflen = cd->min_insn_bitsize / 8;
      status = (*info->read_memory_func) (pc, buf, buflen, info);
    }

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  return print_insn (cd, pc, info, buf, buflen);
}

/* Main entry point.
   Print one instruction from PC on INFO->STREAM.
   Return the size of the instruction (in bytes).  */

typedef struct cpu_desc_list {
  struct cpu_desc_list *next;
  int isa;
  int mach;
  int endian;
  CGEN_CPU_DESC cd;
} cpu_desc_list;

int
print_insn_xstormy16 (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static int prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  int isa,mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
		? CGEN_ENDIAN_BIG
		: CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_xstormy16
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  isa = CGEN_COMPUTE_ISA (info);
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (isa != prev_isa
	  || mach != prev_mach
	  || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
	{
	  if (cl->isa == isa &&
	      cl->mach == mach &&
	      cl->endian == endian)
	    {
	      cd = cl->cd;
	      break;
	    }
	}
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
	abort ();
      mach_name = arch_type->printable_name;

      prev_isa = isa;
      prev_mach = mach;
      prev_endian = endian;
      cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
				 CGEN_CPU_OPEN_BFDMACH, mach_name,
				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
				 CGEN_CPU_OPEN_END);
      if (!cd)
	abort ();

      /* save this away for future reference */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      xstormy16_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}
Commit	Line	Data
93fbbb04 GK	1	/* Disassembler interface for targets using CGEN. -- C --
	2	CGEN: Cpu tools GENerator
	3
	4	THIS FILE IS MACHINE GENERATED WITH CGEN.
	5	- the resultant file is machine generated, cgen-dis.in isn't
	6
98f70fc4 AM	7	Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
98f70fc4 AM	8	Free Software Foundation, Inc.
93fbbb04 GK	9
	10	This file is part of the GNU Binutils and GDB, the GNU debugger.
	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2, or (at your option)
	15	any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; if not, write to the Free Software Foundation, Inc.,
	24	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	25
	26	/* ??? Eventually more and more of this stuff can go to cpu-independent files.
	27	Keep that in mind. */
	28
	29	#include "sysdep.h"
	30	#include <stdio.h>
	31	#include "ansidecl.h"
	32	#include "dis-asm.h"
	33	#include "bfd.h"
	34	#include "symcat.h"
98f70fc4	35	#include "libiberty.h"
93fbbb04 GK	36	#include "xstormy16-desc.h"
	37	#include "xstormy16-opc.h"
	38	#include "opintl.h"
	39
	40	/* Default text to print if an instruction isn't recognized. */
	41	#define UNKNOWN_INSN_MSG _("unknown")
	42
	43	static void print_normal
	44	PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
	45	static void print_address
	46	PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
	47	static void print_keyword
	48	PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
	49	static void print_insn_normal
	50	PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN , CGEN_FIELDS ,
	51	bfd_vma, int));
	52	static int print_insn
	53	PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info , char , unsigned));
	54	static int default_print_insn
	55	PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
	56	static int read_insn
	57	PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info , char , int,
	58	CGEN_EXTRACT_INFO , unsigned long ));
	59	\f
	60	/* -- disassembler routines inserted here */
	61
	62
	63	void xstormy16_cgen_print_operand
	64	PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
	65	void const *, bfd_vma, int));
	66
	67	/* Main entry point for printing operands.
	68	XINFO is a `void ' and not a `disassemble_info ' to not put a requirement
	69	of dis-asm.h on cgen.h.
	70
	71	This function is basically just a big switch statement. Earlier versions
	72	used tables to look up the function to use, but
	73	- if the table contains both assembler and disassembler functions then
	74	the disassembler contains much of the assembler and vice-versa,
	75	- there's a lot of inlining possibilities as things grow,
	76	- using a switch statement avoids the function call overhead.
	77
	78	This function could be moved into `print_insn_normal', but keeping it
	79	separate makes clear the interface between `print_insn_normal' and each of
	80	the handlers. */
	81
	82	void
	83	xstormy16_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
	84	CGEN_CPU_DESC cd;
	85	int opindex;
	86	PTR xinfo;
	87	CGEN_FIELDS *fields;
	88	void const *attrs ATTRIBUTE_UNUSED;
	89	bfd_vma pc;
	90	int length;
	91	{
	92	disassemble_info info = (disassemble_info ) xinfo;
	93
	94	switch (opindex)
	95	{
	96	case XSTORMY16_OPERAND_RB :
1951c6f7	97	print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0);
93fbbb04 GK	98	break;
93fbbb04 GK	99	case XSTORMY16_OPERAND_RBJ :
1951c6f7	100	print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0);
93fbbb04 GK	101	break;
	102	case XSTORMY16_OPERAND_RD :
	103	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0);
	104	break;
	105	case XSTORMY16_OPERAND_RDM :
	106	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0);
	107	break;
	108	case XSTORMY16_OPERAND_RM :
	109	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0);
	110	break;
	111	case XSTORMY16_OPERAND_RS :
	112	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0);
	113	break;
	114	case XSTORMY16_OPERAND_ABS24 :
	115	print_normal (cd, info, fields->f_abs24, 0\|(1<<CGEN_OPERAND_ABS_ADDR)\|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
	116	break;
	117	case XSTORMY16_OPERAND_BCOND2 :
	118	print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0);
	119	break;
	120	case XSTORMY16_OPERAND_BCOND5 :
	121	print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0);
	122	break;
	123	case XSTORMY16_OPERAND_HMEM8 :
	124	print_normal (cd, info, fields->f_hmem8, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	125	break;
	126	case XSTORMY16_OPERAND_IMM12 :
	127	print_normal (cd, info, fields->f_imm12, 0\|(1<<CGEN_OPERAND_SIGNED), pc, length);
	128	break;
	129	case XSTORMY16_OPERAND_IMM16 :
	130	print_normal (cd, info, fields->f_imm16, 0\|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
	131	break;
	132	case XSTORMY16_OPERAND_IMM2 :
	133	print_normal (cd, info, fields->f_imm2, 0, pc, length);
	134	break;
	135	case XSTORMY16_OPERAND_IMM3 :
	136	print_normal (cd, info, fields->f_imm3, 0, pc, length);
	137	break;
	138	case XSTORMY16_OPERAND_IMM3B :
	139	print_normal (cd, info, fields->f_imm3b, 0, pc, length);
	140	break;
	141	case XSTORMY16_OPERAND_IMM4 :
	142	print_normal (cd, info, fields->f_imm4, 0, pc, length);
	143	break;
	144	case XSTORMY16_OPERAND_IMM8 :
	145	print_normal (cd, info, fields->f_imm8, 0, pc, length);
	146	break;
	147	case XSTORMY16_OPERAND_IMM8SMALL :
	148	print_normal (cd, info, fields->f_imm8, 0, pc, length);
	149	break;
	150	case XSTORMY16_OPERAND_LMEM8 :
	151	print_normal (cd, info, fields->f_lmem8, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	152	break;
	153	case XSTORMY16_OPERAND_REL12 :
	154	print_normal (cd, info, fields->f_rel12, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	155	break;
	156	case XSTORMY16_OPERAND_REL12A :
	157	print_normal (cd, info, fields->f_rel12a, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	158	break;
	159	case XSTORMY16_OPERAND_REL8_2 :
	160	print_normal (cd, info, fields->f_rel8_2, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	161	break;
	162	case XSTORMY16_OPERAND_REL8_4 :
	163	print_normal (cd, info, fields->f_rel8_4, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	164	break;
165	case XSTORMY16_OPERAND_WS2 :
166	print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0);
167	break;
168
169	default :
170	/* xgettext:c-format */
171	fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
172	opindex);
173	abort ();
174	}
175	}
176
177	cgen_print_fn * const xstormy16_cgen_print_handlers[] =
178	{
179	print_insn_normal,
180	};
181
182
183	void
184	xstormy16_cgen_init_dis (cd)
185	CGEN_CPU_DESC cd;
186	{
187	xstormy16_cgen_init_opcode_table (cd);
188	xstormy16_cgen_init_ibld_table (cd);
189	cd->print_handlers = & xstormy16_cgen_print_handlers[0];
190	cd->print_operand = xstormy16_cgen_print_operand;
191	}
192
193	\f
194	/* Default print handler. */
195
196	static void
197	print_normal (cd, dis_info, value, attrs, pc, length)
198	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
199	PTR dis_info;
200	long value;
201	unsigned int attrs;
202	bfd_vma pc ATTRIBUTE_UNUSED;
203	int length ATTRIBUTE_UNUSED;
204	{
205	disassemble_info info = (disassemble_info ) dis_info;
206
207	#ifdef CGEN_PRINT_NORMAL
208	CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
209	#endif
210
211	/* Print the operand as directed by the attributes. */
212	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
213	; /* nothing to do */
214	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
215	(*info->fprintf_func) (info->stream, "%ld", value);
216	else
217	(*info->fprintf_func) (info->stream, "0x%lx", value);
218	}
219
220	/* Default address handler. */
221
222	static void
223	print_address (cd, dis_info, value, attrs, pc, length)
224	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
225	PTR dis_info;
226	bfd_vma value;
227	unsigned int attrs;
228	bfd_vma pc ATTRIBUTE_UNUSED;
229	int length ATTRIBUTE_UNUSED;
230	{
231	disassemble_info info = (disassemble_info ) dis_info;
232
233	#ifdef CGEN_PRINT_ADDRESS
234	CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
235	#endif
236
237	/* Print the operand as directed by the attributes. */
238	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
239	; /* nothing to do */
240	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
241	(*info->print_address_func) (value, info);
242	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
243	(*info->print_address_func) (value, info);
244	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
245	(*info->fprintf_func) (info->stream, "%ld", (long) value);
246	else
247	(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
248	}
249
250	/* Keyword print handler. */
251
252	static void
253	print_keyword (cd, dis_info, keyword_table, value, attrs)
254	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
255	PTR dis_info;
256	CGEN_KEYWORD *keyword_table;
257	long value;
258	unsigned int attrs ATTRIBUTE_UNUSED;
259	{
260	disassemble_info info = (disassemble_info ) dis_info;
261	const CGEN_KEYWORD_ENTRY *ke;
262
263	ke = cgen_keyword_lookup_value (keyword_table, value);
264	if (ke != NULL)
265	(*info->fprintf_func) (info->stream, "%s", ke->name);
266	else
267	(*info->fprintf_func) (info->stream, "???");
268	}
269	\f
270	/* Default insn printer.
271
272	DIS_INFO is defined as `PTR' so the disassembler needn't know anything
273	about disassemble_info. */
274
275	static void
276	print_insn_normal (cd, dis_info, insn, fields, pc, length)
277	CGEN_CPU_DESC cd;
278	PTR dis_info;
279	const CGEN_INSN *insn;
280	CGEN_FIELDS *fields;
281	bfd_vma pc;
282	int length;
283	{
284	const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
285	disassemble_info info = (disassemble_info ) dis_info;
286	const CGEN_SYNTAX_CHAR_TYPE *syn;
287
288	CGEN_INIT_PRINT (cd);
289
290	for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
291	{
292	if (CGEN_SYNTAX_MNEMONIC_P (*syn))
293	{
294	(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
295	continue;
296	}
297	if (CGEN_SYNTAX_CHAR_P (*syn))
298	{
299	(info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (syn));
300	continue;
301	}
302
303	/* We have an operand. */
304	xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
305	fields, CGEN_INSN_ATTRS (insn), pc, length);
306	}
307	}
308	\f
309	/* Subroutine of print_insn. Reads an insn into the given buffers and updates
310	the extract info.
311	Returns 0 if all is well, non-zero otherwise. */
312
313	static int
314	read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
315	CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
316	bfd_vma pc;
317	disassemble_info *info;
318	char *buf;
319	int buflen;
320	CGEN_EXTRACT_INFO *ex_info;
321	unsigned long *insn_value;
322	{
323	int status = (*info->read_memory_func) (pc, buf, buflen, info);
324	if (status != 0)
325	{
326	(*info->memory_error_func) (status, pc, info);
327	return -1;
328	}
329
330	ex_info->dis_info = info;
331	ex_info->valid = (1 << buflen) - 1;
332	ex_info->insn_bytes = buf;
333
334	insn_value = bfd_get_bits (buf, buflen 8, info->endian == BFD_ENDIAN_BIG);
335	return 0;
336	}
337
338	/* Utility to print an insn.
339	BUF is the base part of the insn, target byte order, BUFLEN bytes long.
340	The result is the size of the insn in bytes or zero for an unknown insn
341	or -1 if an error occurs fetching data (memory_error_func will have
342	been called). */
343
344	static int
345	print_insn (cd, pc, info, buf, buflen)
346	CGEN_CPU_DESC cd;
347	bfd_vma pc;
348	disassemble_info *info;
349	char *buf;
350	unsigned int buflen;
351	{
352	CGEN_INSN_INT insn_value;
353	const CGEN_INSN_LIST *insn_list;
354	CGEN_EXTRACT_INFO ex_info;
1951c6f7	355	int basesize;
93fbbb04 GK	356
93fbbb04 GK	357	/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
1951c6f7 MG	358	basesize = cd->base_insn_bitsize < buflen * 8 ?
	359	cd->base_insn_bitsize : buflen * 8;
	360	insn_value = cgen_get_insn_value (cd, buf, basesize);
	361
93fbbb04 GK	362
	363	/* Fill in ex_info fields like read_insn would. Don't actually call
	364	read_insn, since the incoming buffer is already read (and possibly
	365	modified a la m32r). */
	366	ex_info.valid = (1 << buflen) - 1;
	367	ex_info.dis_info = info;
	368	ex_info.insn_bytes = buf;
	369
	370	/* The instructions are stored in hash lists.
	371	Pick the first one and keep trying until we find the right one. */
	372
	373	insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
	374	while (insn_list != NULL)
	375	{
	376	const CGEN_INSN *insn = insn_list->insn;
	377	CGEN_FIELDS fields;
	378	int length;
	379	unsigned long insn_value_cropped;
	380
	381	#ifdef CGEN_VALIDATE_INSN_SUPPORTED
	382	/* Not needed as insn shouldn't be in hash lists if not supported. */
	383	/* Supported by this cpu? */
	384	if (! xstormy16_cgen_insn_supported (cd, insn))
	385	{
	386	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	387	continue;
	388	}
	389	#endif
	390
	391	/* Basic bit mask must be correct. */
	392	/* ??? May wish to allow target to defer this check until the extract
	393	handler. */
	394
	395	/* Base size may exceed this instruction's size. Extract the
	396	relevant part from the buffer. */
	397	if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	398	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	399	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
	400	info->endian == BFD_ENDIAN_BIG);
	401	else
	402	insn_value_cropped = insn_value;
	403
	404	if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	405	== CGEN_INSN_BASE_VALUE (insn))
	406	{
	407	/* Printing is handled in two passes. The first pass parses the
	408	machine insn and extracts the fields. The second pass prints
	409	them. */
	410
	411	/* Make sure the entire insn is loaded into insn_value, if it
	412	can fit. */
	413	if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	414	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	415	{
	416	unsigned long full_insn_value;
	417	int rc = read_insn (cd, pc, info, buf,
	418	CGEN_INSN_BITSIZE (insn) / 8,
	419	& ex_info, & full_insn_value);
	420	if (rc != 0)
	421	return rc;
	422	length = CGEN_EXTRACT_FN (cd, insn)
	423	(cd, insn, &ex_info, full_insn_value, &fields, pc);
	424	}
	425	else
426	length = CGEN_EXTRACT_FN (cd, insn)
427	(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
428
429	/* length < 0 -> error */
430	if (length < 0)
431	return length;
432	if (length > 0)
433	{
434	CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
435	/* length is in bits, result is in bytes */
436	return length / 8;
437	}
438	}
439
440	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
441	}
442
443	return 0;
444	}
445
446	/* Default value for CGEN_PRINT_INSN.
447	The result is the size of the insn in bytes or zero for an unknown insn
448	or -1 if an error occured fetching bytes. */
449
450	#ifndef CGEN_PRINT_INSN
451	#define CGEN_PRINT_INSN default_print_insn
452	#endif
453
454	static int
455	default_print_insn (cd, pc, info)
456	CGEN_CPU_DESC cd;
457	bfd_vma pc;
458	disassemble_info *info;
459	{
460	char buf[CGEN_MAX_INSN_SIZE];
461	int buflen;
462	int status;
463
464	/* Attempt to read the base part of the insn. */
465	buflen = cd->base_insn_bitsize / 8;
466	status = (*info->read_memory_func) (pc, buf, buflen, info);
467
468	/* Try again with the minimum part, if min < base. */
469	if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
470	{
471	buflen = cd->min_insn_bitsize / 8;
472	status = (*info->read_memory_func) (pc, buf, buflen, info);
473	}
474
475	if (status != 0)
476	{
477	(*info->memory_error_func) (status, pc, info);
478	return -1;
479	}
480
481	return print_insn (cd, pc, info, buf, buflen);
482	}
483
484	/* Main entry point.
485	Print one instruction from PC on INFO->STREAM.
486	Return the size of the instruction (in bytes). */
487
a978a3e5 NC	488	typedef struct cpu_desc_list {
	489	struct cpu_desc_list *next;
	490	int isa;
	491	int mach;
	492	int endian;
	493	CGEN_CPU_DESC cd;
	494	} cpu_desc_list;
	495
93fbbb04 GK	496	int
	497	print_insn_xstormy16 (pc, info)
	498	bfd_vma pc;
	499	disassemble_info *info;
	500	{
a978a3e5 NC	501	static cpu_desc_list *cd_list = 0;
a978a3e5 NC	502	cpu_desc_list *cl = 0;
93fbbb04 GK	503	static CGEN_CPU_DESC cd = 0;
	504	static int prev_isa;
	505	static int prev_mach;
	506	static int prev_endian;
	507	int length;
	508	int isa,mach;
	509	int endian = (info->endian == BFD_ENDIAN_BIG
	510	? CGEN_ENDIAN_BIG
	511	: CGEN_ENDIAN_LITTLE);
	512	enum bfd_architecture arch;
	513
	514	/* ??? gdb will set mach but leave the architecture as "unknown" */
	515	#ifndef CGEN_BFD_ARCH
	516	#define CGEN_BFD_ARCH bfd_arch_xstormy16
	517	#endif
	518	arch = info->arch;
	519	if (arch == bfd_arch_unknown)
	520	arch = CGEN_BFD_ARCH;
	521
	522	/* There's no standard way to compute the machine or isa number
	523	so we leave it to the target. */
	524	#ifdef CGEN_COMPUTE_MACH
	525	mach = CGEN_COMPUTE_MACH (info);
	526	#else
	527	mach = info->mach;
	528	#endif
	529
	530	#ifdef CGEN_COMPUTE_ISA
	531	isa = CGEN_COMPUTE_ISA (info);
	532	#else
a978a3e5	533	isa = info->insn_sets;
93fbbb04 GK	534	#endif
93fbbb04 GK	535
a978a3e5	536	/* If we've switched cpu's, try to find a handle we've used before */
93fbbb04 GK	537	if (cd
	538	&& (isa != prev_isa
	539	\|\| mach != prev_mach
	540	\|\| endian != prev_endian))
	541	{
93fbbb04	542	cd = 0;
a978a3e5 NC	543	for (cl = cd_list; cl; cl = cl->next)
	544	{
	545	if (cl->isa == isa &&
	546	cl->mach == mach &&
	547	cl->endian == endian)
	548	{
	549	cd = cl->cd;
	550	break;
	551	}
	552	}
	553	}
93fbbb04 GK	554
	555	/* If we haven't initialized yet, initialize the opcode table. */
	556	if (! cd)
	557	{
	558	const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
	559	const char *mach_name;
	560
	561	if (!arch_type)
	562	abort ();
	563	mach_name = arch_type->printable_name;
	564
	565	prev_isa = isa;
	566	prev_mach = mach;
	567	prev_endian = endian;
	568	cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
	569	CGEN_CPU_OPEN_BFDMACH, mach_name,
	570	CGEN_CPU_OPEN_ENDIAN, prev_endian,
	571	CGEN_CPU_OPEN_END);
	572	if (!cd)
	573	abort ();
a978a3e5 NC	574
	575	/* save this away for future reference */
	576	cl = xmalloc (sizeof (struct cpu_desc_list));
	577	cl->cd = cd;
	578	cl->isa = isa;
	579	cl->mach = mach;
	580	cl->endian = endian;
	581	cl->next = cd_list;
	582	cd_list = cl;
	583
93fbbb04 GK	584	xstormy16_cgen_init_dis (cd);
	585	}
	586
	587	/* We try to have as much common code as possible.
	588	But at this point some targets need to take over. */
	589	/* ??? Some targets may need a hook elsewhere. Try to avoid this,
	590	but if not possible try to move this hook elsewhere rather than
	591	have two hooks. */
	592	length = CGEN_PRINT_INSN (cd, pc, info);
	593	if (length > 0)
	594	return length;
	595	if (length < 0)
	596	return -1;
	597
	598	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
	599	return cd->default_insn_bitsize / 8;
	600	}