Commit | Line | Data |
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c906108c | 1 | /* run front end support for arm |
42a4f53d | 2 | Copyright (C) 1995-2019 Free Software Foundation, Inc. |
c906108c | 3 | |
86c735a5 | 4 | This file is part of ARM SIM. |
c906108c | 5 | |
4744ac1b JB |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
4744ac1b JB |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
4744ac1b JB |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
c906108c | 18 | |
86c735a5 NC |
19 | /* This file provides the interface between the simulator and |
20 | run.c and gdb (when the simulator is linked with gdb). | |
c906108c SS |
21 | All simulator interaction should go through this file. */ |
22 | ||
a6ff997c | 23 | #include "config.h" |
c906108c SS |
24 | #include <stdio.h> |
25 | #include <stdarg.h> | |
6d358e86 | 26 | #include <string.h> |
c906108c SS |
27 | #include <bfd.h> |
28 | #include <signal.h> | |
3c25f8c7 AC |
29 | #include "gdb/callback.h" |
30 | #include "gdb/remote-sim.h" | |
49d62f89 MF |
31 | #include "sim-main.h" |
32 | #include "sim-options.h" | |
c906108c SS |
33 | #include "armemu.h" |
34 | #include "dbg_rdi.h" | |
6d358e86 | 35 | #include "ansidecl.h" |
26216b98 | 36 | #include "gdb/sim-arm.h" |
aba6488e | 37 | #include "gdb/signals.h" |
9256caa6 | 38 | #include "libiberty.h" |
8d052926 | 39 | #include "iwmmxt.h" |
851c0536 | 40 | #include "maverick.h" |
74ec5579 | 41 | |
49d62f89 | 42 | /* TODO: This should get pulled from the SIM_DESC. */ |
c906108c SS |
43 | host_callback *sim_callback; |
44 | ||
49d62f89 MF |
45 | /* TODO: This should get merged into sim_cpu. */ |
46 | struct ARMul_State *state; | |
c906108c SS |
47 | |
48 | /* Memory size in bytes. */ | |
49d62f89 | 49 | /* TODO: Memory should be converted to the common memory module. */ |
058f270d | 50 | static int mem_size = (1 << 21); |
c906108c | 51 | |
7a292a7a SS |
52 | int stop_simulator; |
53 | ||
8d052926 NC |
54 | #include "dis-asm.h" |
55 | ||
49d62f89 | 56 | /* TODO: Tracing should be converted to common tracing module. */ |
8d052926 NC |
57 | int trace = 0; |
58 | int disas = 0; | |
59 | int trace_funcs = 0; | |
60 | ||
61 | static struct disassemble_info info; | |
62 | static char opbuf[1000]; | |
63 | ||
64 | static int | |
65 | op_printf (char *buf, char *fmt, ...) | |
66 | { | |
67 | int ret; | |
68 | va_list ap; | |
69 | ||
70 | va_start (ap, fmt); | |
71 | ret = vsprintf (opbuf + strlen (opbuf), fmt, ap); | |
72 | va_end (ap); | |
73 | return ret; | |
74 | } | |
75 | ||
76 | static int | |
77 | sim_dis_read (bfd_vma memaddr ATTRIBUTE_UNUSED, | |
78 | bfd_byte * ptr, | |
79 | unsigned int length, | |
80 | struct disassemble_info * info) | |
81 | { | |
82 | ARMword val = (ARMword) *((ARMword *) info->application_data); | |
83 | ||
84 | while (length--) | |
85 | { | |
86 | * ptr ++ = val & 0xFF; | |
87 | val >>= 8; | |
88 | } | |
89 | return 0; | |
90 | } | |
91 | ||
92 | void | |
93 | print_insn (ARMword instr) | |
94 | { | |
95 | int size; | |
88240b18 | 96 | disassembler_ftype disassemble_fn; |
8d052926 NC |
97 | |
98 | opbuf[0] = 0; | |
99 | info.application_data = & instr; | |
88240b18 YQ |
100 | disassemble_fn = disassembler (bfd_arch_arm, 0, 0, NULL); |
101 | size = disassemble_fn (0, & info); | |
8d052926 NC |
102 | fprintf (stderr, " %*s\n", size, opbuf); |
103 | } | |
104 | ||
dfcd3bfb | 105 | static void |
d68d7e6b | 106 | init (void) |
c906108c SS |
107 | { |
108 | static int done; | |
109 | ||
110 | if (!done) | |
111 | { | |
dfcd3bfb | 112 | ARMul_EmulateInit (); |
c906108c | 113 | state = ARMul_NewState (); |
1ac72f06 | 114 | state->bigendSig = (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? HIGH : LOW); |
dfcd3bfb JM |
115 | ARMul_MemoryInit (state, mem_size); |
116 | ARMul_OSInit (state); | |
58b991b1 | 117 | state->verbose = 0; |
c906108c SS |
118 | done = 1; |
119 | } | |
120 | } | |
121 | ||
dfcd3bfb | 122 | void |
bdca5ee4 TT |
123 | ARMul_ConsolePrint (ARMul_State * state, |
124 | const char * format, | |
125 | ...) | |
c906108c SS |
126 | { |
127 | va_list ap; | |
128 | ||
129 | if (state->verbose) | |
130 | { | |
131 | va_start (ap, format); | |
132 | vprintf (format, ap); | |
133 | va_end (ap); | |
134 | } | |
135 | } | |
136 | ||
c906108c | 137 | int |
d68d7e6b NC |
138 | sim_write (SIM_DESC sd ATTRIBUTE_UNUSED, |
139 | SIM_ADDR addr, | |
140 | const unsigned char * buffer, | |
141 | int size) | |
c906108c SS |
142 | { |
143 | int i; | |
3943c96b | 144 | |
c906108c | 145 | init (); |
3943c96b | 146 | |
c906108c | 147 | for (i = 0; i < size; i++) |
917bca4f | 148 | ARMul_SafeWriteByte (state, addr + i, buffer[i]); |
3943c96b | 149 | |
c906108c SS |
150 | return size; |
151 | } | |
152 | ||
153 | int | |
d68d7e6b NC |
154 | sim_read (SIM_DESC sd ATTRIBUTE_UNUSED, |
155 | SIM_ADDR addr, | |
156 | unsigned char * buffer, | |
157 | int size) | |
c906108c SS |
158 | { |
159 | int i; | |
917bca4f | 160 | |
c906108c | 161 | init (); |
86c735a5 | 162 | |
c906108c | 163 | for (i = 0; i < size; i++) |
917bca4f NC |
164 | buffer[i] = ARMul_SafeReadByte (state, addr + i); |
165 | ||
c906108c SS |
166 | return size; |
167 | } | |
168 | ||
c906108c | 169 | int |
d68d7e6b | 170 | sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED) |
c906108c | 171 | { |
7a292a7a SS |
172 | state->Emulate = STOP; |
173 | stop_simulator = 1; | |
174 | return 1; | |
c906108c SS |
175 | } |
176 | ||
177 | void | |
d68d7e6b NC |
178 | sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED, |
179 | int step, | |
180 | int siggnal ATTRIBUTE_UNUSED) | |
c906108c SS |
181 | { |
182 | state->EndCondition = 0; | |
7a292a7a | 183 | stop_simulator = 0; |
c906108c SS |
184 | |
185 | if (step) | |
186 | { | |
187 | state->Reg[15] = ARMul_DoInstr (state); | |
188 | if (state->EndCondition == 0) | |
189 | state->EndCondition = RDIError_BreakpointReached; | |
190 | } | |
191 | else | |
192 | { | |
dfcd3bfb | 193 | state->NextInstr = RESUME; /* treat as PC change */ |
c906108c SS |
194 | state->Reg[15] = ARMul_DoProg (state); |
195 | } | |
196 | ||
197 | FLUSHPIPE; | |
198 | } | |
199 | ||
200 | SIM_RC | |
d68d7e6b NC |
201 | sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED, |
202 | struct bfd * abfd, | |
2e3d4f4d MF |
203 | char * const *argv, |
204 | char * const *env) | |
c906108c | 205 | { |
dfcd3bfb | 206 | int argvlen = 0; |
1e6b544a | 207 | int mach; |
851c0536 | 208 | char * const *arg; |
c906108c | 209 | |
1ed6c797 WN |
210 | init (); |
211 | ||
c906108c | 212 | if (abfd != NULL) |
8782aa32 WN |
213 | { |
214 | ARMul_SetPC (state, bfd_get_start_address (abfd)); | |
215 | mach = bfd_get_mach (abfd); | |
216 | } | |
c906108c | 217 | else |
8782aa32 WN |
218 | { |
219 | ARMul_SetPC (state, 0); /* ??? */ | |
220 | mach = 0; | |
221 | } | |
1e6b544a | 222 | |
73cb0348 NC |
223 | #ifdef MODET |
224 | if (abfd != NULL && (bfd_get_start_address (abfd) & 1)) | |
225 | SETT; | |
226 | #endif | |
227 | ||
3943c96b NC |
228 | switch (mach) |
229 | { | |
230 | default: | |
86c735a5 NC |
231 | (*sim_callback->printf_filtered) |
232 | (sim_callback, | |
10b57fcb NC |
233 | "Unknown machine type '%d'; please update sim_create_inferior.\n", |
234 | mach); | |
3943c96b NC |
235 | /* fall through */ |
236 | ||
f1129fb8 | 237 | case 0: |
3943c96b | 238 | /* We wouldn't set the machine type with earlier toolchains, so we |
f1129fb8 NC |
239 | explicitly select a processor capable of supporting all ARMs in |
240 | 32bit mode. */ | |
8d052926 NC |
241 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop); |
242 | break; | |
243 | ||
272fcdcd | 244 | case bfd_mach_arm_XScale: |
8207e0f2 | 245 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop); |
272fcdcd NC |
246 | break; |
247 | ||
b0f05691 | 248 | case bfd_mach_arm_iWMMXt2: |
0f026fd0 NC |
249 | case bfd_mach_arm_iWMMXt: |
250 | { | |
251 | extern int SWI_vector_installed; | |
252 | ARMword i; | |
253 | ||
254 | if (! SWI_vector_installed) | |
255 | { | |
256 | /* Intialise the hardware vectors to zero. */ | |
257 | if (! SWI_vector_installed) | |
258 | for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) | |
259 | ARMul_WriteWord (state, i, 0); | |
260 | ||
261 | /* ARM_WriteWord will have detected the write to the SWI vector, | |
262 | but we want SWI_vector_installed to remain at 0 so that thumb | |
263 | mode breakpoints will work. */ | |
264 | SWI_vector_installed = 0; | |
265 | } | |
266 | } | |
267 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop); | |
268 | break; | |
269 | ||
f603c8fe NC |
270 | case bfd_mach_arm_ep9312: |
271 | ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop); | |
272 | break; | |
273 | ||
f1129fb8 | 274 | case bfd_mach_arm_5: |
c17aa318 NC |
275 | if (bfd_family_coff (abfd)) |
276 | { | |
277 | /* This is a special case in order to support COFF based ARM toolchains. | |
278 | The COFF header does not have enough room to store all the different | |
279 | kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default | |
280 | to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5 | |
281 | machine type here, we assume it could be any of the above architectures | |
282 | and so select the most feature-full. */ | |
283 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop); | |
284 | break; | |
285 | } | |
286 | /* Otherwise drop through. */ | |
25180f8a | 287 | |
f1129fb8 NC |
288 | case bfd_mach_arm_5T: |
289 | ARMul_SelectProcessor (state, ARM_v5_Prop); | |
290 | break; | |
3943c96b | 291 | |
f1129fb8 NC |
292 | case bfd_mach_arm_5TE: |
293 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop); | |
294 | break; | |
295 | ||
f1129fb8 NC |
296 | case bfd_mach_arm_4: |
297 | case bfd_mach_arm_4T: | |
298 | ARMul_SelectProcessor (state, ARM_v4_Prop); | |
299 | break; | |
300 | ||
301 | case bfd_mach_arm_3: | |
302 | case bfd_mach_arm_3M: | |
3943c96b NC |
303 | ARMul_SelectProcessor (state, ARM_Lock_Prop); |
304 | break; | |
305 | ||
f1129fb8 NC |
306 | case bfd_mach_arm_2: |
307 | case bfd_mach_arm_2a: | |
3943c96b NC |
308 | ARMul_SelectProcessor (state, ARM_Fix26_Prop); |
309 | break; | |
310 | } | |
311 | ||
8d052926 NC |
312 | memset (& info, 0, sizeof (info)); |
313 | INIT_DISASSEMBLE_INFO (info, stdout, op_printf); | |
314 | info.read_memory_func = sim_dis_read; | |
315 | info.arch = bfd_get_arch (abfd); | |
316 | info.mach = bfd_get_mach (abfd); | |
317 | info.endian_code = BFD_ENDIAN_LITTLE; | |
318 | if (info.mach == 0) | |
319 | info.arch = bfd_arch_arm; | |
320 | disassemble_init_for_target (& info); | |
321 | ||
c906108c SS |
322 | if (argv != NULL) |
323 | { | |
5f7d0a33 NC |
324 | /* Set up the command line by laboriously stringing together |
325 | the environment carefully picked apart by our caller. */ | |
326 | ||
327 | /* Free any old stuff. */ | |
c906108c SS |
328 | if (state->CommandLine != NULL) |
329 | { | |
dfcd3bfb | 330 | free (state->CommandLine); |
c906108c SS |
331 | state->CommandLine = NULL; |
332 | } | |
dfcd3bfb | 333 | |
5f7d0a33 | 334 | /* See how much we need. */ |
c906108c | 335 | for (arg = argv; *arg != NULL; arg++) |
dfcd3bfb JM |
336 | argvlen += strlen (*arg) + 1; |
337 | ||
5f7d0a33 | 338 | /* Allocate it. */ |
dfcd3bfb | 339 | state->CommandLine = malloc (argvlen + 1); |
c906108c SS |
340 | if (state->CommandLine != NULL) |
341 | { | |
342 | arg = argv; | |
dfcd3bfb | 343 | state->CommandLine[0] = '\0'; |
5f7d0a33 | 344 | |
c906108c SS |
345 | for (arg = argv; *arg != NULL; arg++) |
346 | { | |
dfcd3bfb JM |
347 | strcat (state->CommandLine, *arg); |
348 | strcat (state->CommandLine, " "); | |
c906108c SS |
349 | } |
350 | } | |
351 | } | |
352 | ||
353 | if (env != NULL) | |
354 | { | |
5f7d0a33 | 355 | /* Now see if there's a MEMSIZE spec in the environment. */ |
c906108c SS |
356 | while (*env) |
357 | { | |
dfcd3bfb | 358 | if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0) |
c906108c | 359 | { |
c906108c | 360 | char *end_of_num; |
dfcd3bfb | 361 | |
5f7d0a33 | 362 | /* Set up memory limit. */ |
dfcd3bfb JM |
363 | state->MemSize = |
364 | strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0); | |
c906108c SS |
365 | } |
366 | env++; | |
367 | } | |
368 | } | |
369 | ||
370 | return SIM_RC_OK; | |
371 | } | |
372 | ||
dfcd3bfb | 373 | static int |
d68d7e6b | 374 | frommem (struct ARMul_State *state, unsigned char *memory) |
c906108c SS |
375 | { |
376 | if (state->bigendSig == HIGH) | |
86c735a5 NC |
377 | return (memory[0] << 24) | (memory[1] << 16) |
378 | | (memory[2] << 8) | (memory[3] << 0); | |
c906108c | 379 | else |
86c735a5 NC |
380 | return (memory[3] << 24) | (memory[2] << 16) |
381 | | (memory[1] << 8) | (memory[0] << 0); | |
c906108c SS |
382 | } |
383 | ||
c906108c | 384 | static void |
d68d7e6b NC |
385 | tomem (struct ARMul_State *state, |
386 | unsigned char *memory, | |
387 | int val) | |
c906108c SS |
388 | { |
389 | if (state->bigendSig == HIGH) | |
390 | { | |
391 | memory[0] = val >> 24; | |
392 | memory[1] = val >> 16; | |
393 | memory[2] = val >> 8; | |
394 | memory[3] = val >> 0; | |
395 | } | |
396 | else | |
397 | { | |
398 | memory[3] = val >> 24; | |
399 | memory[2] = val >> 16; | |
400 | memory[1] = val >> 8; | |
401 | memory[0] = val >> 0; | |
402 | } | |
403 | } | |
404 | ||
e1211e55 MF |
405 | static int |
406 | arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
c906108c SS |
407 | { |
408 | init (); | |
f1129fb8 | 409 | |
26216b98 | 410 | switch ((enum sim_arm_regs) rn) |
3463c3fb | 411 | { |
26216b98 AC |
412 | case SIM_ARM_R0_REGNUM: |
413 | case SIM_ARM_R1_REGNUM: | |
414 | case SIM_ARM_R2_REGNUM: | |
415 | case SIM_ARM_R3_REGNUM: | |
416 | case SIM_ARM_R4_REGNUM: | |
417 | case SIM_ARM_R5_REGNUM: | |
418 | case SIM_ARM_R6_REGNUM: | |
419 | case SIM_ARM_R7_REGNUM: | |
420 | case SIM_ARM_R8_REGNUM: | |
421 | case SIM_ARM_R9_REGNUM: | |
422 | case SIM_ARM_R10_REGNUM: | |
423 | case SIM_ARM_R11_REGNUM: | |
424 | case SIM_ARM_R12_REGNUM: | |
425 | case SIM_ARM_R13_REGNUM: | |
426 | case SIM_ARM_R14_REGNUM: | |
427 | case SIM_ARM_R15_REGNUM: /* PC */ | |
428 | case SIM_ARM_FP0_REGNUM: | |
429 | case SIM_ARM_FP1_REGNUM: | |
430 | case SIM_ARM_FP2_REGNUM: | |
431 | case SIM_ARM_FP3_REGNUM: | |
432 | case SIM_ARM_FP4_REGNUM: | |
433 | case SIM_ARM_FP5_REGNUM: | |
434 | case SIM_ARM_FP6_REGNUM: | |
435 | case SIM_ARM_FP7_REGNUM: | |
436 | case SIM_ARM_FPS_REGNUM: | |
437 | ARMul_SetReg (state, state->Mode, rn, frommem (state, memory)); | |
438 | break; | |
439 | ||
440 | case SIM_ARM_PS_REGNUM: | |
3463c3fb | 441 | state->Cpsr = frommem (state, memory); |
10b57fcb | 442 | ARMul_CPSRAltered (state); |
26216b98 AC |
443 | break; |
444 | ||
f603c8fe NC |
445 | case SIM_ARM_MAVERIC_COP0R0_REGNUM: |
446 | case SIM_ARM_MAVERIC_COP0R1_REGNUM: | |
447 | case SIM_ARM_MAVERIC_COP0R2_REGNUM: | |
448 | case SIM_ARM_MAVERIC_COP0R3_REGNUM: | |
449 | case SIM_ARM_MAVERIC_COP0R4_REGNUM: | |
450 | case SIM_ARM_MAVERIC_COP0R5_REGNUM: | |
451 | case SIM_ARM_MAVERIC_COP0R6_REGNUM: | |
452 | case SIM_ARM_MAVERIC_COP0R7_REGNUM: | |
453 | case SIM_ARM_MAVERIC_COP0R8_REGNUM: | |
454 | case SIM_ARM_MAVERIC_COP0R9_REGNUM: | |
455 | case SIM_ARM_MAVERIC_COP0R10_REGNUM: | |
456 | case SIM_ARM_MAVERIC_COP0R11_REGNUM: | |
457 | case SIM_ARM_MAVERIC_COP0R12_REGNUM: | |
458 | case SIM_ARM_MAVERIC_COP0R13_REGNUM: | |
459 | case SIM_ARM_MAVERIC_COP0R14_REGNUM: | |
460 | case SIM_ARM_MAVERIC_COP0R15_REGNUM: | |
461 | memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], | |
462 | memory, sizeof (struct maverick_regs)); | |
463 | return sizeof (struct maverick_regs); | |
464 | ||
465 | case SIM_ARM_MAVERIC_DSPSC_REGNUM: | |
466 | memcpy (&DSPsc, memory, sizeof DSPsc); | |
467 | return sizeof DSPsc; | |
468 | ||
0f026fd0 NC |
469 | case SIM_ARM_IWMMXT_COP0R0_REGNUM: |
470 | case SIM_ARM_IWMMXT_COP0R1_REGNUM: | |
471 | case SIM_ARM_IWMMXT_COP0R2_REGNUM: | |
472 | case SIM_ARM_IWMMXT_COP0R3_REGNUM: | |
473 | case SIM_ARM_IWMMXT_COP0R4_REGNUM: | |
474 | case SIM_ARM_IWMMXT_COP0R5_REGNUM: | |
475 | case SIM_ARM_IWMMXT_COP0R6_REGNUM: | |
476 | case SIM_ARM_IWMMXT_COP0R7_REGNUM: | |
477 | case SIM_ARM_IWMMXT_COP0R8_REGNUM: | |
478 | case SIM_ARM_IWMMXT_COP0R9_REGNUM: | |
479 | case SIM_ARM_IWMMXT_COP0R10_REGNUM: | |
480 | case SIM_ARM_IWMMXT_COP0R11_REGNUM: | |
481 | case SIM_ARM_IWMMXT_COP0R12_REGNUM: | |
482 | case SIM_ARM_IWMMXT_COP0R13_REGNUM: | |
483 | case SIM_ARM_IWMMXT_COP0R14_REGNUM: | |
484 | case SIM_ARM_IWMMXT_COP0R15_REGNUM: | |
485 | case SIM_ARM_IWMMXT_COP1R0_REGNUM: | |
486 | case SIM_ARM_IWMMXT_COP1R1_REGNUM: | |
487 | case SIM_ARM_IWMMXT_COP1R2_REGNUM: | |
488 | case SIM_ARM_IWMMXT_COP1R3_REGNUM: | |
489 | case SIM_ARM_IWMMXT_COP1R4_REGNUM: | |
490 | case SIM_ARM_IWMMXT_COP1R5_REGNUM: | |
491 | case SIM_ARM_IWMMXT_COP1R6_REGNUM: | |
492 | case SIM_ARM_IWMMXT_COP1R7_REGNUM: | |
493 | case SIM_ARM_IWMMXT_COP1R8_REGNUM: | |
494 | case SIM_ARM_IWMMXT_COP1R9_REGNUM: | |
495 | case SIM_ARM_IWMMXT_COP1R10_REGNUM: | |
496 | case SIM_ARM_IWMMXT_COP1R11_REGNUM: | |
497 | case SIM_ARM_IWMMXT_COP1R12_REGNUM: | |
498 | case SIM_ARM_IWMMXT_COP1R13_REGNUM: | |
499 | case SIM_ARM_IWMMXT_COP1R14_REGNUM: | |
500 | case SIM_ARM_IWMMXT_COP1R15_REGNUM: | |
501 | return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); | |
3a3d6f65 | 502 | |
26216b98 AC |
503 | default: |
504 | return 0; | |
3463c3fb | 505 | } |
26216b98 | 506 | |
9256caa6 | 507 | return length; |
c906108c SS |
508 | } |
509 | ||
e1211e55 MF |
510 | static int |
511 | arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) | |
c906108c SS |
512 | { |
513 | ARMword regval; | |
9256caa6 | 514 | int len = length; |
c906108c SS |
515 | |
516 | init (); | |
f1129fb8 | 517 | |
26216b98 AC |
518 | switch ((enum sim_arm_regs) rn) |
519 | { | |
520 | case SIM_ARM_R0_REGNUM: | |
521 | case SIM_ARM_R1_REGNUM: | |
522 | case SIM_ARM_R2_REGNUM: | |
523 | case SIM_ARM_R3_REGNUM: | |
524 | case SIM_ARM_R4_REGNUM: | |
525 | case SIM_ARM_R5_REGNUM: | |
526 | case SIM_ARM_R6_REGNUM: | |
527 | case SIM_ARM_R7_REGNUM: | |
528 | case SIM_ARM_R8_REGNUM: | |
529 | case SIM_ARM_R9_REGNUM: | |
530 | case SIM_ARM_R10_REGNUM: | |
531 | case SIM_ARM_R11_REGNUM: | |
532 | case SIM_ARM_R12_REGNUM: | |
533 | case SIM_ARM_R13_REGNUM: | |
534 | case SIM_ARM_R14_REGNUM: | |
535 | case SIM_ARM_R15_REGNUM: /* PC */ | |
536 | regval = ARMul_GetReg (state, state->Mode, rn); | |
537 | break; | |
538 | ||
539 | case SIM_ARM_FP0_REGNUM: | |
540 | case SIM_ARM_FP1_REGNUM: | |
541 | case SIM_ARM_FP2_REGNUM: | |
542 | case SIM_ARM_FP3_REGNUM: | |
543 | case SIM_ARM_FP4_REGNUM: | |
544 | case SIM_ARM_FP5_REGNUM: | |
545 | case SIM_ARM_FP6_REGNUM: | |
546 | case SIM_ARM_FP7_REGNUM: | |
547 | case SIM_ARM_FPS_REGNUM: | |
548 | memset (memory, 0, length); | |
549 | return 0; | |
550 | ||
551 | case SIM_ARM_PS_REGNUM: | |
552 | regval = ARMul_GetCPSR (state); | |
553 | break; | |
554 | ||
f603c8fe NC |
555 | case SIM_ARM_MAVERIC_COP0R0_REGNUM: |
556 | case SIM_ARM_MAVERIC_COP0R1_REGNUM: | |
557 | case SIM_ARM_MAVERIC_COP0R2_REGNUM: | |
558 | case SIM_ARM_MAVERIC_COP0R3_REGNUM: | |
559 | case SIM_ARM_MAVERIC_COP0R4_REGNUM: | |
560 | case SIM_ARM_MAVERIC_COP0R5_REGNUM: | |
561 | case SIM_ARM_MAVERIC_COP0R6_REGNUM: | |
562 | case SIM_ARM_MAVERIC_COP0R7_REGNUM: | |
563 | case SIM_ARM_MAVERIC_COP0R8_REGNUM: | |
564 | case SIM_ARM_MAVERIC_COP0R9_REGNUM: | |
565 | case SIM_ARM_MAVERIC_COP0R10_REGNUM: | |
566 | case SIM_ARM_MAVERIC_COP0R11_REGNUM: | |
567 | case SIM_ARM_MAVERIC_COP0R12_REGNUM: | |
568 | case SIM_ARM_MAVERIC_COP0R13_REGNUM: | |
569 | case SIM_ARM_MAVERIC_COP0R14_REGNUM: | |
570 | case SIM_ARM_MAVERIC_COP0R15_REGNUM: | |
571 | memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], | |
572 | sizeof (struct maverick_regs)); | |
573 | return sizeof (struct maverick_regs); | |
574 | ||
575 | case SIM_ARM_MAVERIC_DSPSC_REGNUM: | |
576 | memcpy (memory, & DSPsc, sizeof DSPsc); | |
577 | return sizeof DSPsc; | |
578 | ||
0f026fd0 NC |
579 | case SIM_ARM_IWMMXT_COP0R0_REGNUM: |
580 | case SIM_ARM_IWMMXT_COP0R1_REGNUM: | |
581 | case SIM_ARM_IWMMXT_COP0R2_REGNUM: | |
582 | case SIM_ARM_IWMMXT_COP0R3_REGNUM: | |
583 | case SIM_ARM_IWMMXT_COP0R4_REGNUM: | |
584 | case SIM_ARM_IWMMXT_COP0R5_REGNUM: | |
585 | case SIM_ARM_IWMMXT_COP0R6_REGNUM: | |
586 | case SIM_ARM_IWMMXT_COP0R7_REGNUM: | |
587 | case SIM_ARM_IWMMXT_COP0R8_REGNUM: | |
588 | case SIM_ARM_IWMMXT_COP0R9_REGNUM: | |
589 | case SIM_ARM_IWMMXT_COP0R10_REGNUM: | |
590 | case SIM_ARM_IWMMXT_COP0R11_REGNUM: | |
591 | case SIM_ARM_IWMMXT_COP0R12_REGNUM: | |
592 | case SIM_ARM_IWMMXT_COP0R13_REGNUM: | |
593 | case SIM_ARM_IWMMXT_COP0R14_REGNUM: | |
594 | case SIM_ARM_IWMMXT_COP0R15_REGNUM: | |
595 | case SIM_ARM_IWMMXT_COP1R0_REGNUM: | |
596 | case SIM_ARM_IWMMXT_COP1R1_REGNUM: | |
597 | case SIM_ARM_IWMMXT_COP1R2_REGNUM: | |
598 | case SIM_ARM_IWMMXT_COP1R3_REGNUM: | |
599 | case SIM_ARM_IWMMXT_COP1R4_REGNUM: | |
600 | case SIM_ARM_IWMMXT_COP1R5_REGNUM: | |
601 | case SIM_ARM_IWMMXT_COP1R6_REGNUM: | |
602 | case SIM_ARM_IWMMXT_COP1R7_REGNUM: | |
603 | case SIM_ARM_IWMMXT_COP1R8_REGNUM: | |
604 | case SIM_ARM_IWMMXT_COP1R9_REGNUM: | |
605 | case SIM_ARM_IWMMXT_COP1R10_REGNUM: | |
606 | case SIM_ARM_IWMMXT_COP1R11_REGNUM: | |
607 | case SIM_ARM_IWMMXT_COP1R12_REGNUM: | |
608 | case SIM_ARM_IWMMXT_COP1R13_REGNUM: | |
609 | case SIM_ARM_IWMMXT_COP1R14_REGNUM: | |
610 | case SIM_ARM_IWMMXT_COP1R15_REGNUM: | |
611 | return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); | |
3a3d6f65 | 612 | |
26216b98 AC |
613 | default: |
614 | return 0; | |
615 | } | |
272fcdcd | 616 | |
9256caa6 | 617 | while (len) |
272fcdcd NC |
618 | { |
619 | tomem (state, memory, regval); | |
620 | ||
9256caa6 | 621 | len -= 4; |
272fcdcd NC |
622 | memory += 4; |
623 | regval = 0; | |
454de2ee | 624 | } |
272fcdcd | 625 | |
9256caa6 | 626 | return length; |
c906108c SS |
627 | } |
628 | ||
de4112fa NC |
629 | typedef struct |
630 | { | |
631 | char * swi_option; | |
632 | unsigned int swi_mask; | |
633 | } swi_options; | |
634 | ||
635 | #define SWI_SWITCH "--swi-support" | |
636 | ||
637 | static swi_options options[] = | |
638 | { | |
639 | { "none", 0 }, | |
640 | { "demon", SWI_MASK_DEMON }, | |
641 | { "angel", SWI_MASK_ANGEL }, | |
642 | { "redboot", SWI_MASK_REDBOOT }, | |
643 | { "all", -1 }, | |
644 | { "NONE", 0 }, | |
645 | { "DEMON", SWI_MASK_DEMON }, | |
646 | { "ANGEL", SWI_MASK_ANGEL }, | |
647 | { "REDBOOT", SWI_MASK_REDBOOT }, | |
648 | { "ALL", -1 } | |
649 | }; | |
650 | ||
651 | ||
49d62f89 | 652 | static int |
d68d7e6b | 653 | sim_target_parse_command_line (int argc, char ** argv) |
de4112fa NC |
654 | { |
655 | int i; | |
656 | ||
657 | for (i = 1; i < argc; i++) | |
658 | { | |
659 | char * ptr = argv[i]; | |
660 | int arg; | |
661 | ||
662 | if ((ptr == NULL) || (* ptr != '-')) | |
663 | break; | |
664 | ||
8d052926 NC |
665 | if (strcmp (ptr, "-t") == 0) |
666 | { | |
667 | trace = 1; | |
668 | continue; | |
669 | } | |
454de2ee | 670 | |
8d052926 NC |
671 | if (strcmp (ptr, "-z") == 0) |
672 | { | |
673 | /* Remove this option from the argv array. */ | |
674 | for (arg = i; arg < argc; arg ++) | |
675 | argv[arg] = argv[arg + 1]; | |
676 | argc --; | |
677 | i --; | |
678 | trace_funcs = 1; | |
679 | continue; | |
680 | } | |
454de2ee | 681 | |
8d052926 NC |
682 | if (strcmp (ptr, "-d") == 0) |
683 | { | |
684 | /* Remove this option from the argv array. */ | |
685 | for (arg = i; arg < argc; arg ++) | |
686 | argv[arg] = argv[arg + 1]; | |
687 | argc --; | |
688 | i --; | |
689 | disas = 1; | |
690 | continue; | |
691 | } | |
692 | ||
de4112fa NC |
693 | if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0) |
694 | continue; | |
695 | ||
696 | if (ptr[sizeof SWI_SWITCH - 1] == 0) | |
697 | { | |
698 | /* Remove this option from the argv array. */ | |
699 | for (arg = i; arg < argc; arg ++) | |
700 | argv[arg] = argv[arg + 1]; | |
701 | argc --; | |
454de2ee | 702 | |
de4112fa NC |
703 | ptr = argv[i]; |
704 | } | |
705 | else | |
706 | ptr += sizeof SWI_SWITCH; | |
707 | ||
708 | swi_mask = 0; | |
454de2ee | 709 | |
de4112fa NC |
710 | while (* ptr) |
711 | { | |
712 | int i; | |
713 | ||
13a590ca | 714 | for (i = ARRAY_SIZE (options); i--;) |
de4112fa NC |
715 | if (strncmp (ptr, options[i].swi_option, |
716 | strlen (options[i].swi_option)) == 0) | |
717 | { | |
718 | swi_mask |= options[i].swi_mask; | |
719 | ptr += strlen (options[i].swi_option); | |
720 | ||
721 | if (* ptr == ',') | |
722 | ++ ptr; | |
723 | ||
724 | break; | |
725 | } | |
726 | ||
727 | if (i < 0) | |
728 | break; | |
729 | } | |
730 | ||
731 | if (* ptr != 0) | |
732 | fprintf (stderr, "Ignoring swi options: %s\n", ptr); | |
454de2ee | 733 | |
de4112fa NC |
734 | /* Remove this option from the argv array. */ |
735 | for (arg = i; arg < argc; arg ++) | |
736 | argv[arg] = argv[arg + 1]; | |
737 | argc --; | |
738 | i --; | |
739 | } | |
740 | return argc; | |
741 | } | |
742 | ||
743 | static void | |
d68d7e6b | 744 | sim_target_parse_arg_array (char ** argv) |
de4112fa | 745 | { |
34fed699 | 746 | sim_target_parse_command_line (countargv (argv), argv); |
de4112fa NC |
747 | } |
748 | ||
27b97b40 MF |
749 | static sim_cia |
750 | arm_pc_get (sim_cpu *cpu) | |
751 | { | |
752 | return PC; | |
753 | } | |
754 | ||
755 | static void | |
756 | arm_pc_set (sim_cpu *cpu, sim_cia pc) | |
757 | { | |
758 | ARMul_SetPC (state, pc); | |
759 | } | |
760 | ||
49d62f89 MF |
761 | static void |
762 | free_state (SIM_DESC sd) | |
de4112fa | 763 | { |
49d62f89 MF |
764 | if (STATE_MODULES (sd) != NULL) |
765 | sim_module_uninstall (sd); | |
766 | sim_cpu_free_all (sd); | |
767 | sim_state_free (sd); | |
de4112fa | 768 | } |
de4112fa | 769 | |
c906108c | 770 | SIM_DESC |
49d62f89 MF |
771 | sim_open (SIM_OPEN_KIND kind, |
772 | host_callback *cb, | |
773 | struct bfd *abfd, | |
2e3d4f4d | 774 | char * const *argv) |
c906108c | 775 | { |
27b97b40 | 776 | int i; |
49d62f89 MF |
777 | SIM_DESC sd = sim_state_alloc (kind, cb); |
778 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
d68d7e6b | 779 | |
49d62f89 MF |
780 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
781 | if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) | |
782 | { | |
783 | free_state (sd); | |
784 | return 0; | |
785 | } | |
d68d7e6b | 786 | |
49d62f89 MF |
787 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
788 | { | |
789 | free_state (sd); | |
790 | return 0; | |
791 | } | |
dfcd3bfb | 792 | |
77cf2ef5 | 793 | /* The parser will print an error message for us, so we silently return. */ |
49d62f89 | 794 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
c906108c | 795 | { |
49d62f89 MF |
796 | free_state (sd); |
797 | return 0; | |
798 | } | |
dfcd3bfb | 799 | |
49d62f89 MF |
800 | /* Check for/establish the a reference program image. */ |
801 | if (sim_analyze_program (sd, | |
802 | (STATE_PROG_ARGV (sd) != NULL | |
803 | ? *STATE_PROG_ARGV (sd) | |
804 | : NULL), abfd) != SIM_RC_OK) | |
805 | { | |
806 | free_state (sd); | |
807 | return 0; | |
808 | } | |
dfcd3bfb | 809 | |
49d62f89 MF |
810 | /* Configure/verify the target byte order and other runtime |
811 | configuration options. */ | |
812 | if (sim_config (sd) != SIM_RC_OK) | |
813 | { | |
814 | sim_module_uninstall (sd); | |
815 | return 0; | |
816 | } | |
dfcd3bfb | 817 | |
49d62f89 MF |
818 | if (sim_post_argv_init (sd) != SIM_RC_OK) |
819 | { | |
820 | /* Uninstall the modules to avoid memory leaks, | |
821 | file descriptor leaks, etc. */ | |
822 | sim_module_uninstall (sd); | |
823 | return 0; | |
824 | } | |
dfcd3bfb | 825 | |
27b97b40 MF |
826 | /* CPU specific initialization. */ |
827 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
828 | { | |
829 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
830 | ||
e1211e55 MF |
831 | CPU_REG_FETCH (cpu) = arm_reg_fetch; |
832 | CPU_REG_STORE (cpu) = arm_reg_store; | |
27b97b40 MF |
833 | CPU_PC_FETCH (cpu) = arm_pc_get; |
834 | CPU_PC_STORE (cpu) = arm_pc_set; | |
835 | } | |
836 | ||
49d62f89 | 837 | sim_callback = cb; |
dfcd3bfb | 838 | |
49d62f89 | 839 | sim_target_parse_arg_array (argv); |
dfcd3bfb | 840 | |
49d62f89 MF |
841 | if (argv[1] != NULL) |
842 | { | |
843 | int i; | |
844 | ||
845 | /* Scan for memory-size switches. */ | |
846 | for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++) | |
847 | if (argv[i][0] == '-' && argv[i][1] == 'm') | |
058f270d AC |
848 | { |
849 | if (argv[i][2] != '\0') | |
49d62f89 | 850 | mem_size = atoi (&argv[i][2]); |
058f270d AC |
851 | else if (argv[i + 1] != NULL) |
852 | { | |
49d62f89 | 853 | mem_size = atoi (argv[i + 1]); |
058f270d AC |
854 | i++; |
855 | } | |
856 | else | |
857 | { | |
858 | sim_callback->printf_filtered (sim_callback, | |
859 | "Missing argument to -m option\n"); | |
860 | return NULL; | |
861 | } | |
058f270d | 862 | } |
c906108c SS |
863 | } |
864 | ||
49d62f89 | 865 | return sd; |
c906108c SS |
866 | } |
867 | ||
c906108c | 868 | void |
d68d7e6b NC |
869 | sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED, |
870 | enum sim_stop *reason, | |
871 | int *sigrc) | |
c906108c | 872 | { |
7a292a7a SS |
873 | if (stop_simulator) |
874 | { | |
875 | *reason = sim_stopped; | |
a493e3e2 | 876 | *sigrc = GDB_SIGNAL_INT; |
7a292a7a SS |
877 | } |
878 | else if (state->EndCondition == 0) | |
c906108c SS |
879 | { |
880 | *reason = sim_exited; | |
881 | *sigrc = state->Reg[0] & 255; | |
882 | } | |
883 | else | |
884 | { | |
885 | *reason = sim_stopped; | |
886 | if (state->EndCondition == RDIError_BreakpointReached) | |
a493e3e2 | 887 | *sigrc = GDB_SIGNAL_TRAP; |
0f026fd0 NC |
888 | else if ( state->EndCondition == RDIError_DataAbort |
889 | || state->EndCondition == RDIError_AddressException) | |
a493e3e2 | 890 | *sigrc = GDB_SIGNAL_BUS; |
c906108c SS |
891 | else |
892 | *sigrc = 0; | |
893 | } | |
894 | } |