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1 | /* Blackfin Core Timer model. |
2 | ||
3 | Copyright (C) 2010-2011 Free Software Foundation, Inc. | |
4 | Contributed by Analog Devices, Inc. | |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_cec.h" | |
26 | #include "dv-bfin_ctimer.h" | |
27 | ||
28 | struct bfin_ctimer | |
29 | { | |
30 | bu32 base; | |
31 | struct hw_event *handler; | |
32 | signed64 timeout; | |
33 | ||
34 | /* Order after here is important -- matches hardware MMR layout. */ | |
35 | bu32 tcntl, tperiod, tscale, tcount; | |
36 | }; | |
37 | #define mmr_base() offsetof(struct bfin_ctimer, tcntl) | |
38 | #define mmr_offset(mmr) (offsetof(struct bfin_ctimer, mmr) - mmr_base()) | |
39 | ||
40 | static const char * const mmr_names[] = { | |
41 | "TCNTL", "TPERIOD", "TSCALE", "TCOUNT", | |
42 | }; | |
43 | #define mmr_name(off) mmr_names[(off) / 4] | |
44 | ||
45 | static bool | |
46 | bfin_ctimer_enabled (struct bfin_ctimer *ctimer) | |
47 | { | |
48 | return (ctimer->tcntl & TMPWR) && (ctimer->tcntl & TMREN); | |
49 | } | |
50 | ||
51 | static bu32 | |
52 | bfin_ctimer_scale (struct bfin_ctimer *ctimer) | |
53 | { | |
54 | /* Only low 8 bits are actually checked. */ | |
55 | return (ctimer->tscale & 0xff) + 1; | |
56 | } | |
57 | ||
58 | static void | |
59 | bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer); | |
60 | ||
61 | static void | |
62 | bfin_ctimer_expire (struct hw *me, void *data) | |
63 | { | |
64 | struct bfin_ctimer *ctimer = data; | |
65 | ||
66 | ctimer->tcntl |= TINT; | |
67 | if (ctimer->tcntl & TAUTORLD) | |
68 | { | |
69 | ctimer->tcount = ctimer->tperiod; | |
70 | bfin_ctimer_schedule (me, ctimer); | |
71 | } | |
72 | else | |
73 | { | |
74 | ctimer->tcount = 0; | |
75 | ctimer->handler = NULL; | |
76 | } | |
77 | ||
78 | hw_port_event (me, IVG_IVTMR, 1); | |
79 | } | |
80 | ||
81 | static void | |
82 | bfin_ctimer_update_count (struct hw *me, struct bfin_ctimer *ctimer) | |
83 | { | |
84 | bu32 scale, ticks; | |
85 | signed64 timeout; | |
86 | ||
87 | /* If the timer was enabled w/out autoreload and has expired, then | |
88 | there's nothing to calculate here. */ | |
89 | if (ctimer->handler == NULL) | |
90 | return; | |
91 | ||
92 | scale = bfin_ctimer_scale (ctimer); | |
93 | timeout = hw_event_remain_time (me, ctimer->handler); | |
94 | ticks = ctimer->timeout - timeout; | |
95 | ctimer->tcount -= (scale * ticks); | |
96 | ctimer->timeout = timeout; | |
97 | } | |
98 | ||
99 | static void | |
100 | bfin_ctimer_deschedule (struct hw *me, struct bfin_ctimer *ctimer) | |
101 | { | |
102 | if (ctimer->handler) | |
103 | { | |
104 | hw_event_queue_deschedule (me, ctimer->handler); | |
105 | ctimer->handler = NULL; | |
106 | } | |
107 | } | |
108 | ||
109 | static void | |
110 | bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer) | |
111 | { | |
112 | bu32 scale = bfin_ctimer_scale (ctimer); | |
113 | ctimer->timeout = (ctimer->tcount / scale) + !!(ctimer->tcount % scale); | |
114 | ctimer->handler = hw_event_queue_schedule (me, ctimer->timeout, | |
115 | bfin_ctimer_expire, | |
116 | ctimer); | |
117 | } | |
118 | ||
119 | static unsigned | |
120 | bfin_ctimer_io_write_buffer (struct hw *me, const void *source, | |
121 | int space, address_word addr, unsigned nr_bytes) | |
122 | { | |
123 | struct bfin_ctimer *ctimer = hw_data (me); | |
124 | bool curr_enabled; | |
125 | bu32 mmr_off; | |
126 | bu32 value; | |
127 | bu32 *valuep; | |
128 | ||
129 | value = dv_load_4 (source); | |
130 | mmr_off = addr - ctimer->base; | |
131 | valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off); | |
132 | ||
133 | HW_TRACE_WRITE (); | |
134 | ||
135 | curr_enabled = bfin_ctimer_enabled (ctimer); | |
136 | switch (mmr_off) | |
137 | { | |
138 | case mmr_offset(tcntl): | |
139 | /* HRM describes TINT as sticky, but it isn't W1C. */ | |
140 | *valuep = value; | |
141 | ||
142 | if (bfin_ctimer_enabled (ctimer) == curr_enabled) | |
143 | { | |
144 | /* Do nothing. */ | |
145 | } | |
146 | else if (curr_enabled) | |
147 | { | |
148 | bfin_ctimer_update_count (me, ctimer); | |
149 | bfin_ctimer_deschedule (me, ctimer); | |
150 | } | |
151 | else | |
152 | bfin_ctimer_schedule (me, ctimer); | |
153 | ||
154 | break; | |
155 | case mmr_offset(tcount): | |
156 | /* HRM says writes are discarded when enabled. */ | |
157 | /* XXX: But hardware seems to be writeable all the time ? */ | |
158 | /* if (!curr_enabled) */ | |
159 | *valuep = value; | |
160 | break; | |
161 | case mmr_offset(tperiod): | |
162 | /* HRM says writes are discarded when enabled. */ | |
163 | /* XXX: But hardware seems to be writeable all the time ? */ | |
164 | /* if (!curr_enabled) */ | |
165 | { | |
166 | /* Writes are mirrored into TCOUNT. */ | |
167 | ctimer->tcount = value; | |
168 | *valuep = value; | |
169 | } | |
170 | break; | |
171 | case mmr_offset(tscale): | |
172 | if (curr_enabled) | |
173 | { | |
174 | bfin_ctimer_update_count (me, ctimer); | |
175 | bfin_ctimer_deschedule (me, ctimer); | |
176 | } | |
177 | *valuep = value; | |
178 | if (curr_enabled) | |
179 | bfin_ctimer_schedule (me, ctimer); | |
180 | break; | |
181 | } | |
182 | ||
183 | return nr_bytes; | |
184 | } | |
185 | ||
186 | static unsigned | |
187 | bfin_ctimer_io_read_buffer (struct hw *me, void *dest, | |
188 | int space, address_word addr, unsigned nr_bytes) | |
189 | { | |
190 | struct bfin_ctimer *ctimer = hw_data (me); | |
191 | bu32 mmr_off; | |
192 | bu32 *valuep; | |
193 | ||
194 | mmr_off = addr - ctimer->base; | |
195 | valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off); | |
196 | ||
197 | HW_TRACE_READ (); | |
198 | ||
199 | switch (mmr_off) | |
200 | { | |
201 | case mmr_offset(tcount): | |
202 | /* Since we're optimizing events here, we need to calculate | |
203 | the new tcount value. */ | |
204 | if (bfin_ctimer_enabled (ctimer)) | |
205 | bfin_ctimer_update_count (me, ctimer); | |
206 | break; | |
207 | } | |
208 | ||
209 | dv_store_4 (dest, *valuep); | |
210 | ||
211 | return nr_bytes; | |
212 | } | |
213 | ||
214 | static const struct hw_port_descriptor bfin_ctimer_ports[] = { | |
215 | { "ivtmr", IVG_IVTMR, 0, output_port, }, | |
216 | { NULL, 0, 0, 0, }, | |
217 | }; | |
218 | ||
219 | static void | |
220 | attach_bfin_ctimer_regs (struct hw *me, struct bfin_ctimer *ctimer) | |
221 | { | |
222 | address_word attach_address; | |
223 | int attach_space; | |
224 | unsigned attach_size; | |
225 | reg_property_spec reg; | |
226 | ||
227 | if (hw_find_property (me, "reg") == NULL) | |
228 | hw_abort (me, "Missing \"reg\" property"); | |
229 | ||
230 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
231 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
232 | ||
233 | hw_unit_address_to_attach_address (hw_parent (me), | |
234 | ®.address, | |
235 | &attach_space, &attach_address, me); | |
236 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
237 | ||
238 | if (attach_size != BFIN_COREMMR_CTIMER_SIZE) | |
239 | hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CTIMER_SIZE); | |
240 | ||
241 | hw_attach_address (hw_parent (me), | |
242 | 0, attach_space, attach_address, attach_size, me); | |
243 | ||
244 | ctimer->base = attach_address; | |
245 | } | |
246 | ||
247 | static void | |
248 | bfin_ctimer_finish (struct hw *me) | |
249 | { | |
250 | struct bfin_ctimer *ctimer; | |
251 | ||
252 | ctimer = HW_ZALLOC (me, struct bfin_ctimer); | |
253 | ||
254 | set_hw_data (me, ctimer); | |
255 | set_hw_io_read_buffer (me, bfin_ctimer_io_read_buffer); | |
256 | set_hw_io_write_buffer (me, bfin_ctimer_io_write_buffer); | |
257 | set_hw_ports (me, bfin_ctimer_ports); | |
258 | ||
259 | attach_bfin_ctimer_regs (me, ctimer); | |
260 | ||
261 | /* Initialize the Core Timer. */ | |
262 | } | |
263 | ||
264 | const struct hw_descriptor dv_bfin_ctimer_descriptor[] = { | |
265 | {"bfin_ctimer", bfin_ctimer_finish,}, | |
266 | {NULL, NULL}, | |
267 | }; |