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ef016f83 MF |
1 | /* Blackfin JTAG model. |
2 | ||
42a4f53d | 3 | Copyright (C) 2010-2019 Free Software Foundation, Inc. |
ef016f83 MF |
4 | Contributed by Analog Devices, Inc. |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_jtag.h" | |
26 | ||
27 | /* XXX: This is mostly a stub. There are more registers, but they're only | |
28 | accessible via the JTAG scan chain and not the MMR interface. */ | |
29 | ||
30 | struct bfin_jtag | |
31 | { | |
32 | bu32 base; | |
33 | ||
34 | /* Order after here is important -- matches hardware MMR layout. */ | |
35 | bu32 dspid; | |
36 | bu32 _pad0; | |
37 | bu32 dbgstat; | |
38 | }; | |
39 | #define mmr_base() offsetof(struct bfin_jtag, dspid) | |
40 | #define mmr_offset(mmr) (offsetof(struct bfin_jtag, mmr) - mmr_base()) | |
41 | ||
990d19fd MF |
42 | static const char * const mmr_names[] = |
43 | { | |
ef016f83 MF |
44 | "DSPID", NULL, "DBGSTAT", |
45 | }; | |
46 | #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") | |
47 | ||
48 | static unsigned | |
49 | bfin_jtag_io_write_buffer (struct hw *me, const void *source, int space, | |
50 | address_word addr, unsigned nr_bytes) | |
51 | { | |
52 | struct bfin_jtag *jtag = hw_data (me); | |
53 | bu32 mmr_off; | |
54 | bu32 value; | |
55 | bu32 *valuep; | |
56 | ||
466b619e MF |
57 | /* Invalid access mode is higher priority than missing register. */ |
58 | if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true)) | |
59 | return 0; | |
60 | ||
ef016f83 MF |
61 | value = dv_load_4 (source); |
62 | mmr_off = addr - jtag->base; | |
63 | valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); | |
64 | ||
65 | HW_TRACE_WRITE (); | |
66 | ||
67 | switch (mmr_off) | |
68 | { | |
69 | case mmr_offset(dbgstat): | |
9922f803 | 70 | dv_w1c_4 (valuep, value, 0xc); |
ef016f83 MF |
71 | break; |
72 | case mmr_offset(dspid): | |
73 | /* Discard writes to these. */ | |
74 | break; | |
75 | default: | |
76 | dv_bfin_mmr_invalid (me, addr, nr_bytes, true); | |
466b619e | 77 | return 0; |
ef016f83 MF |
78 | } |
79 | ||
80 | return nr_bytes; | |
81 | } | |
82 | ||
83 | static unsigned | |
84 | bfin_jtag_io_read_buffer (struct hw *me, void *dest, int space, | |
85 | address_word addr, unsigned nr_bytes) | |
86 | { | |
87 | struct bfin_jtag *jtag = hw_data (me); | |
88 | bu32 mmr_off; | |
89 | bu32 value; | |
90 | bu32 *valuep; | |
91 | ||
466b619e MF |
92 | /* Invalid access mode is higher priority than missing register. */ |
93 | if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false)) | |
94 | return 0; | |
95 | ||
ef016f83 MF |
96 | mmr_off = addr - jtag->base; |
97 | valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); | |
98 | ||
99 | HW_TRACE_READ (); | |
100 | ||
101 | switch (mmr_off) | |
102 | { | |
103 | case mmr_offset(dbgstat): | |
104 | case mmr_offset(dspid): | |
105 | value = *valuep; | |
106 | break; | |
107 | default: | |
466b619e MF |
108 | dv_bfin_mmr_invalid (me, addr, nr_bytes, false); |
109 | return 0; | |
ef016f83 MF |
110 | } |
111 | ||
112 | dv_store_4 (dest, value); | |
113 | ||
114 | return nr_bytes; | |
115 | } | |
116 | ||
117 | static void | |
118 | attach_bfin_jtag_regs (struct hw *me, struct bfin_jtag *jtag) | |
119 | { | |
120 | address_word attach_address; | |
121 | int attach_space; | |
122 | unsigned attach_size; | |
123 | reg_property_spec reg; | |
124 | ||
125 | if (hw_find_property (me, "reg") == NULL) | |
126 | hw_abort (me, "Missing \"reg\" property"); | |
127 | ||
128 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
129 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
130 | ||
131 | hw_unit_address_to_attach_address (hw_parent (me), | |
132 | ®.address, | |
133 | &attach_space, &attach_address, me); | |
134 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
135 | ||
136 | if (attach_size != BFIN_COREMMR_JTAG_SIZE) | |
137 | hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_JTAG_SIZE); | |
138 | ||
139 | hw_attach_address (hw_parent (me), | |
140 | 0, attach_space, attach_address, attach_size, me); | |
141 | ||
142 | jtag->base = attach_address; | |
143 | } | |
144 | ||
145 | static void | |
146 | bfin_jtag_finish (struct hw *me) | |
147 | { | |
148 | struct bfin_jtag *jtag; | |
149 | ||
150 | jtag = HW_ZALLOC (me, struct bfin_jtag); | |
151 | ||
152 | set_hw_data (me, jtag); | |
153 | set_hw_io_read_buffer (me, bfin_jtag_io_read_buffer); | |
154 | set_hw_io_write_buffer (me, bfin_jtag_io_write_buffer); | |
155 | ||
156 | attach_bfin_jtag_regs (me, jtag); | |
157 | ||
158 | /* Initialize the JTAG state. */ | |
159 | jtag->dspid = bfin_model_get_dspid (hw_system (me)); | |
160 | } | |
161 | ||
81d126c3 MF |
162 | const struct hw_descriptor dv_bfin_jtag_descriptor[] = |
163 | { | |
ef016f83 MF |
164 | {"bfin_jtag", bfin_jtag_finish,}, |
165 | {NULL, NULL}, | |
166 | }; |