Commit | Line | Data |
---|---|---|
ef016f83 MF |
1 | /* Blackfin One-Time Programmable Memory (OTP) model |
2 | ||
b811d2c2 | 3 | Copyright (C) 2010-2020 Free Software Foundation, Inc. |
ef016f83 MF |
4 | Contributed by Analog Devices, Inc. |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_otp.h" | |
26 | ||
27 | /* XXX: No public documentation on this interface. This seems to work | |
28 | with the on-chip ROM functions though and was figured out by | |
29 | disassembling & walking that code. */ | |
30 | /* XXX: About only thing that should be done here are CRC fields. And | |
31 | supposedly there is an interrupt that could be generated. */ | |
32 | ||
33 | struct bfin_otp | |
34 | { | |
35 | bu32 base; | |
36 | ||
37 | /* The actual OTP storage -- 0x200 pages, each page is 128bits. | |
38 | While certain pages have predefined and/or secure access, we don't | |
39 | bother trying to implement that coverage. All pages are open for | |
40 | reading & writing. */ | |
41 | bu32 mem[0x200 * 4]; | |
42 | ||
43 | /* Order after here is important -- matches hardware MMR layout. */ | |
44 | bu16 BFIN_MMR_16(control); | |
45 | bu16 BFIN_MMR_16(ben); | |
46 | bu16 BFIN_MMR_16(status); | |
47 | bu32 timing; | |
48 | bu32 _pad0[28]; | |
49 | bu32 data0, data1, data2, data3; | |
50 | }; | |
51 | #define mmr_base() offsetof(struct bfin_otp, control) | |
52 | #define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base()) | |
53 | #define mmr_idx(mmr) (mmr_offset (mmr) / 4) | |
54 | ||
990d19fd MF |
55 | static const char * const mmr_names[] = |
56 | { | |
ef016f83 MF |
57 | "OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING", |
58 | [mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3", | |
59 | }; | |
60 | #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") | |
61 | ||
62 | /* XXX: This probably misbehaves with big endian hosts. */ | |
63 | static void | |
64 | bfin_otp_transfer (struct bfin_otp *otp, void *vdst, void *vsrc) | |
65 | { | |
66 | bu8 *dst = vdst, *src = vsrc; | |
67 | int bidx; | |
68 | for (bidx = 0; bidx < 16; ++bidx) | |
69 | if (otp->ben & (1 << bidx)) | |
70 | dst[bidx] = src[bidx]; | |
71 | } | |
72 | ||
73 | static void | |
74 | bfin_otp_read_page (struct bfin_otp *otp, bu16 page) | |
75 | { | |
76 | bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]); | |
77 | } | |
78 | ||
79 | static void | |
80 | bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2]) | |
81 | { | |
82 | bfin_otp_transfer (otp, &otp->mem[page * 4], val); | |
83 | } | |
84 | static void | |
85 | bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi) | |
86 | { | |
87 | bu64 val[2] = { lo, hi }; | |
88 | bfin_otp_write_page_val (otp, page, val); | |
89 | } | |
90 | static void | |
91 | bfin_otp_write_page (struct bfin_otp *otp, bu16 page) | |
92 | { | |
93 | bfin_otp_write_page_val (otp, page, (void *)&otp->data0); | |
94 | } | |
95 | ||
96 | static unsigned | |
97 | bfin_otp_io_write_buffer (struct hw *me, const void *source, int space, | |
98 | address_word addr, unsigned nr_bytes) | |
99 | { | |
100 | struct bfin_otp *otp = hw_data (me); | |
101 | bu32 mmr_off; | |
102 | bu32 value; | |
103 | bu16 *value16p; | |
104 | bu32 *value32p; | |
105 | void *valuep; | |
106 | ||
466b619e MF |
107 | /* Invalid access mode is higher priority than missing register. */ |
108 | if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true)) | |
109 | return 0; | |
110 | ||
ef016f83 MF |
111 | if (nr_bytes == 4) |
112 | value = dv_load_4 (source); | |
113 | else | |
114 | value = dv_load_2 (source); | |
115 | ||
116 | mmr_off = addr - otp->base; | |
117 | valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off); | |
118 | value16p = valuep; | |
119 | value32p = valuep; | |
120 | ||
121 | HW_TRACE_WRITE (); | |
122 | ||
123 | switch (mmr_off) | |
124 | { | |
125 | case mmr_offset(control): | |
126 | { | |
127 | int page; | |
128 | ||
466b619e MF |
129 | if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true)) |
130 | return 0; | |
ef016f83 MF |
131 | /* XXX: Seems like these bits aren't writable. */ |
132 | *value16p = value & 0x39FF; | |
133 | ||
134 | /* Low bits seem to be the page address. */ | |
135 | page = value & PAGE_ADDR; | |
136 | ||
137 | /* Write operation. */ | |
138 | if (value & DO_WRITE) | |
139 | bfin_otp_write_page (otp, page); | |
140 | ||
141 | /* Read operation. */ | |
142 | if (value & DO_READ) | |
143 | bfin_otp_read_page (otp, page); | |
144 | ||
145 | otp->status |= STATUS_DONE; | |
146 | ||
147 | break; | |
148 | } | |
149 | case mmr_offset(ben): | |
466b619e MF |
150 | if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true)) |
151 | return 0; | |
ef016f83 MF |
152 | /* XXX: All bits seem to be writable. */ |
153 | *value16p = value; | |
154 | break; | |
155 | case mmr_offset(status): | |
466b619e MF |
156 | if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true)) |
157 | return 0; | |
ef016f83 | 158 | /* XXX: All bits seem to be W1C. */ |
9922f803 | 159 | dv_w1c_2 (value16p, value, -1); |
ef016f83 MF |
160 | break; |
161 | case mmr_offset(timing): | |
162 | case mmr_offset(data0): | |
163 | case mmr_offset(data1): | |
164 | case mmr_offset(data2): | |
165 | case mmr_offset(data3): | |
466b619e MF |
166 | if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true)) |
167 | return 0; | |
ef016f83 MF |
168 | *value32p = value; |
169 | break; | |
170 | default: | |
171 | dv_bfin_mmr_invalid (me, addr, nr_bytes, true); | |
466b619e | 172 | return 0; |
ef016f83 MF |
173 | } |
174 | ||
175 | return nr_bytes; | |
176 | } | |
177 | ||
178 | static unsigned | |
179 | bfin_otp_io_read_buffer (struct hw *me, void *dest, int space, | |
180 | address_word addr, unsigned nr_bytes) | |
181 | { | |
182 | struct bfin_otp *otp = hw_data (me); | |
183 | bu32 mmr_off; | |
184 | bu16 *value16p; | |
185 | bu32 *value32p; | |
186 | void *valuep; | |
187 | ||
466b619e MF |
188 | /* Invalid access mode is higher priority than missing register. */ |
189 | if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false)) | |
190 | return 0; | |
191 | ||
ef016f83 MF |
192 | mmr_off = addr - otp->base; |
193 | valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off); | |
194 | value16p = valuep; | |
195 | value32p = valuep; | |
196 | ||
197 | HW_TRACE_READ (); | |
198 | ||
199 | switch (mmr_off) | |
200 | { | |
201 | case mmr_offset(control): | |
202 | case mmr_offset(ben): | |
203 | case mmr_offset(status): | |
466b619e MF |
204 | if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false)) |
205 | return 0; | |
ef016f83 MF |
206 | dv_store_2 (dest, *value16p); |
207 | break; | |
208 | case mmr_offset(timing): | |
209 | case mmr_offset(data0): | |
210 | case mmr_offset(data1): | |
211 | case mmr_offset(data2): | |
212 | case mmr_offset(data3): | |
466b619e MF |
213 | if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false)) |
214 | return 0; | |
ef016f83 MF |
215 | dv_store_4 (dest, *value32p); |
216 | break; | |
217 | default: | |
218 | dv_bfin_mmr_invalid (me, addr, nr_bytes, false); | |
466b619e | 219 | return 0; |
ef016f83 MF |
220 | } |
221 | ||
222 | return nr_bytes; | |
223 | } | |
224 | ||
225 | static void | |
226 | attach_bfin_otp_regs (struct hw *me, struct bfin_otp *otp) | |
227 | { | |
228 | address_word attach_address; | |
229 | int attach_space; | |
230 | unsigned attach_size; | |
231 | reg_property_spec reg; | |
232 | ||
233 | if (hw_find_property (me, "reg") == NULL) | |
234 | hw_abort (me, "Missing \"reg\" property"); | |
235 | ||
236 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
237 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
238 | ||
239 | hw_unit_address_to_attach_address (hw_parent (me), | |
240 | ®.address, | |
241 | &attach_space, &attach_address, me); | |
242 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
243 | ||
244 | if (attach_size != BFIN_MMR_OTP_SIZE) | |
245 | hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE); | |
246 | ||
247 | hw_attach_address (hw_parent (me), | |
248 | 0, attach_space, attach_address, attach_size, me); | |
249 | ||
250 | otp->base = attach_address; | |
251 | } | |
252 | ||
2b12772f MF |
253 | static const struct hw_port_descriptor bfin_otp_ports[] = |
254 | { | |
255 | { "stat", 0, 0, output_port, }, | |
256 | { NULL, 0, 0, 0, }, | |
257 | }; | |
258 | ||
ef016f83 MF |
259 | static void |
260 | bfin_otp_finish (struct hw *me) | |
261 | { | |
262 | char part_str[16]; | |
263 | struct bfin_otp *otp; | |
264 | unsigned int fps03; | |
265 | int type = hw_find_integer_property (me, "type"); | |
266 | ||
267 | otp = HW_ZALLOC (me, struct bfin_otp); | |
268 | ||
269 | set_hw_data (me, otp); | |
270 | set_hw_io_read_buffer (me, bfin_otp_io_read_buffer); | |
271 | set_hw_io_write_buffer (me, bfin_otp_io_write_buffer); | |
2b12772f | 272 | set_hw_ports (me, bfin_otp_ports); |
ef016f83 MF |
273 | |
274 | attach_bfin_otp_regs (me, otp); | |
275 | ||
276 | /* Initialize the OTP. */ | |
277 | otp->ben = 0xFFFF; | |
278 | otp->timing = 0x00001485; | |
279 | ||
280 | /* Semi-random value for unique chip id. */ | |
281 | bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp); | |
282 | ||
283 | memset (part_str, 0, sizeof (part_str)); | |
284 | sprintf (part_str, "ADSP-BF%iX", type); | |
285 | switch (type) | |
286 | { | |
287 | case 512: | |
288 | fps03 = FPS03_BF512; | |
289 | break; | |
290 | case 514: | |
291 | fps03 = FPS03_BF514; | |
292 | break; | |
293 | case 516: | |
294 | fps03 = FPS03_BF516; | |
295 | break; | |
296 | case 518: | |
297 | fps03 = FPS03_BF518; | |
298 | break; | |
299 | case 522: | |
300 | fps03 = FPS03_BF522; | |
301 | break; | |
302 | case 523: | |
303 | fps03 = FPS03_BF523; | |
304 | break; | |
305 | case 524: | |
306 | fps03 = FPS03_BF524; | |
307 | break; | |
308 | case 525: | |
309 | fps03 = FPS03_BF525; | |
310 | break; | |
311 | case 526: | |
312 | fps03 = FPS03_BF526; | |
313 | break; | |
314 | case 527: | |
315 | fps03 = FPS03_BF527; | |
316 | break; | |
317 | default: | |
318 | fps03 = 0; | |
319 | break; | |
320 | } | |
321 | part_str[14] = (fps03 >> 0); | |
322 | part_str[15] = (fps03 >> 8); | |
323 | bfin_otp_write_page_val (otp, FPS03, (void *)part_str); | |
324 | } | |
325 | ||
81d126c3 MF |
326 | const struct hw_descriptor dv_bfin_otp_descriptor[] = |
327 | { | |
ef016f83 MF |
328 | {"bfin_otp", bfin_otp_finish,}, |
329 | {NULL, NULL}, | |
330 | }; |