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ef016f83 MF |
1 | /* Blackfin System Interrupt Controller (SIC) model. |
2 | ||
3 | Copyright (C) 2010-2011 Free Software Foundation, Inc. | |
4 | Contributed by Analog Devices, Inc. | |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_sic.h" | |
26 | #include "dv-bfin_cec.h" | |
27 | ||
28 | struct bfin_sic | |
29 | { | |
30 | /* We assume first element is the base. */ | |
31 | bu32 base; | |
32 | ||
33 | /* Order after here is important -- matches hardware MMR layout. */ | |
34 | bu16 BFIN_MMR_16(swrst); | |
35 | bu16 BFIN_MMR_16(syscr); | |
36 | bu16 BFIN_MMR_16(rvect); /* XXX: BF59x has a 32bit AUX_REVID here. */ | |
37 | union { | |
38 | struct { | |
39 | bu32 imask0; | |
40 | bu32 iar0, iar1, iar2, iar3; | |
41 | bu32 isr0, iwr0; | |
42 | bu32 _pad0[9]; | |
43 | bu32 imask1; | |
44 | bu32 iar4, iar5, iar6, iar7; | |
45 | bu32 isr1, iwr1; | |
46 | } bf52x; | |
47 | struct { | |
48 | bu32 imask; | |
49 | bu32 iar0, iar1, iar2, iar3; | |
50 | bu32 isr, iwr; | |
51 | } bf537; | |
52 | struct { | |
53 | bu32 imask0, imask1, imask2; | |
54 | bu32 isr0, isr1, isr2; | |
55 | bu32 iwr0, iwr1, iwr2; | |
56 | bu32 iar0, iar1, iar2, iar3; | |
57 | bu32 iar4, iar5, iar6, iar7; | |
58 | bu32 iar8, iar9, iar10, iar11; | |
59 | } bf54x; | |
60 | struct { | |
61 | bu32 imask0, imask1; | |
62 | bu32 iar0, iar1, iar2, iar3; | |
63 | bu32 iar4, iar5, iar6, iar7; | |
64 | bu32 isr0, isr1; | |
65 | bu32 iwr0, iwr1; | |
66 | } bf561; | |
67 | }; | |
68 | }; | |
69 | #define mmr_base() offsetof(struct bfin_sic, swrst) | |
70 | #define mmr_offset(mmr) (offsetof(struct bfin_sic, mmr) - mmr_base()) | |
71 | #define mmr_idx(mmr) (mmr_offset (mmr) / 4) | |
72 | ||
990d19fd MF |
73 | static const char * const bf52x_mmr_names[] = |
74 | { | |
ef016f83 MF |
75 | "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IAR0", "SIC_IAR1", |
76 | "SIC_IAR2", "SIC_IAR3", "SIC_ISR0", "SIC_IWR0", | |
77 | [mmr_idx (bf52x.imask1)] = "SIC_IMASK1", "SIC_IAR4", "SIC_IAR5", | |
78 | "SIC_IAR6", "SIC_IAR7", "SIC_ISR1", "SIC_IWR1", | |
79 | }; | |
990d19fd MF |
80 | static const char * const bf537_mmr_names[] = |
81 | { | |
ef016f83 MF |
82 | "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK", "SIC_IAR0", "SIC_IAR1", |
83 | "SIC_IAR2", "SIC_IAR3", "SIC_ISR", "SIC_IWR", | |
84 | }; | |
990d19fd MF |
85 | static const char * const bf54x_mmr_names[] = |
86 | { | |
ef016f83 MF |
87 | "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", "SIC_IMASK2", |
88 | "SIC_ISR0", "SIC_ISR1", "SIC_ISR2", "SIC_IWR0", "SIC_IWR1", "SIC_IWR2", | |
89 | "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3", | |
90 | "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7", | |
91 | "SIC_IAR8", "SIC_IAR9", "SIC_IAR10", "SIC_IAR11", | |
92 | }; | |
990d19fd MF |
93 | static const char * const bf561_mmr_names[] = |
94 | { | |
ef016f83 MF |
95 | "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", |
96 | "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3", | |
97 | "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7", | |
98 | "SIC_ISR0", "SIC_ISR1", "SIC_IWR0", "SIC_IWR1", | |
99 | }; | |
100 | static const char * const *mmr_names; | |
101 | #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") | |
102 | ||
103 | static void | |
104 | bfin_sic_forward_interrupts (struct hw *me, bu32 *isr, bu32 *imask, bu32 *iar) | |
105 | { | |
106 | int my_port; | |
107 | bu32 ipend; | |
108 | ||
109 | /* Process pending and unmasked interrupts. */ | |
110 | ipend = *isr & *imask; | |
111 | ||
112 | /* Usually none are pending unmasked, so avoid bit twiddling. */ | |
113 | if (!ipend) | |
114 | return; | |
115 | ||
116 | for (my_port = 0; my_port < 32; ++my_port) | |
117 | { | |
118 | bu32 iar_idx, iar_off, iar_val; | |
119 | bu32 bit = (1 << my_port); | |
120 | ||
121 | /* This bit isn't pending, so check next one. */ | |
122 | if (!(ipend & bit)) | |
123 | continue; | |
124 | ||
125 | /* The IAR registers map the System input to the Core output. | |
126 | Every 4 bits in the IAR are used to map to IVG{7..15}. */ | |
127 | iar_idx = my_port / 8; | |
128 | iar_off = (my_port % 8) * 4; | |
129 | iar_val = (iar[iar_idx] & (0xf << iar_off)) >> iar_off; | |
130 | hw_port_event (me, IVG7 + iar_val, 1); | |
131 | } | |
132 | } | |
133 | ||
134 | static void | |
135 | bfin_sic_52x_forward_interrupts (struct hw *me, struct bfin_sic *sic) | |
136 | { | |
137 | bfin_sic_forward_interrupts (me, &sic->bf52x.isr0, &sic->bf52x.imask0, &sic->bf52x.iar0); | |
138 | bfin_sic_forward_interrupts (me, &sic->bf52x.isr1, &sic->bf52x.imask1, &sic->bf52x.iar4); | |
139 | } | |
140 | ||
141 | static unsigned | |
142 | bfin_sic_52x_io_write_buffer (struct hw *me, const void *source, int space, | |
143 | address_word addr, unsigned nr_bytes) | |
144 | { | |
145 | struct bfin_sic *sic = hw_data (me); | |
146 | bu32 mmr_off; | |
147 | bu32 value; | |
148 | bu16 *value16p; | |
149 | bu32 *value32p; | |
150 | void *valuep; | |
151 | ||
152 | if (nr_bytes == 4) | |
153 | value = dv_load_4 (source); | |
154 | else | |
155 | value = dv_load_2 (source); | |
156 | ||
157 | mmr_off = addr - sic->base; | |
158 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
159 | value16p = valuep; | |
160 | value32p = valuep; | |
161 | ||
162 | HW_TRACE_WRITE (); | |
163 | ||
164 | /* XXX: Discard all SIC writes for now. */ | |
165 | switch (mmr_off) | |
166 | { | |
167 | case mmr_offset(swrst): | |
168 | /* XXX: This should trigger a software reset ... */ | |
169 | break; | |
170 | case mmr_offset(syscr): | |
171 | /* XXX: what to do ... */ | |
172 | break; | |
173 | case mmr_offset(bf52x.imask0): | |
174 | case mmr_offset(bf52x.imask1): | |
175 | bfin_sic_52x_forward_interrupts (me, sic); | |
176 | *value32p = value; | |
177 | break; | |
178 | case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3): | |
179 | case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7): | |
180 | case mmr_offset(bf52x.iwr0): | |
181 | case mmr_offset(bf52x.iwr1): | |
182 | *value32p = value; | |
183 | break; | |
184 | case mmr_offset(bf52x.isr0): | |
185 | case mmr_offset(bf52x.isr1): | |
186 | /* ISR is read-only. */ | |
187 | break; | |
188 | default: | |
189 | /* XXX: Should discard other writes. */ | |
190 | ; | |
191 | } | |
192 | ||
193 | return nr_bytes; | |
194 | } | |
195 | ||
196 | static unsigned | |
197 | bfin_sic_52x_io_read_buffer (struct hw *me, void *dest, int space, | |
198 | address_word addr, unsigned nr_bytes) | |
199 | { | |
200 | struct bfin_sic *sic = hw_data (me); | |
201 | bu32 mmr_off; | |
202 | bu16 *value16p; | |
203 | bu32 *value32p; | |
204 | void *valuep; | |
205 | ||
206 | mmr_off = addr - sic->base; | |
207 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
208 | value16p = valuep; | |
209 | value32p = valuep; | |
210 | ||
211 | HW_TRACE_READ (); | |
212 | ||
213 | switch (mmr_off) | |
214 | { | |
215 | case mmr_offset(swrst): | |
216 | case mmr_offset(syscr): | |
217 | case mmr_offset(rvect): | |
218 | dv_store_2 (dest, *value16p); | |
219 | break; | |
220 | case mmr_offset(bf52x.imask0): | |
221 | case mmr_offset(bf52x.imask1): | |
222 | case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3): | |
223 | case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7): | |
224 | case mmr_offset(bf52x.iwr0): | |
225 | case mmr_offset(bf52x.iwr1): | |
226 | case mmr_offset(bf52x.isr0): | |
227 | case mmr_offset(bf52x.isr1): | |
228 | dv_store_4 (dest, *value32p); | |
229 | break; | |
230 | default: | |
231 | if (nr_bytes == 2) | |
232 | dv_store_2 (dest, 0); | |
233 | else | |
234 | dv_store_4 (dest, 0); | |
235 | break; | |
236 | } | |
237 | ||
238 | return nr_bytes; | |
239 | } | |
240 | ||
241 | static void | |
242 | bfin_sic_537_forward_interrupts (struct hw *me, struct bfin_sic *sic) | |
243 | { | |
244 | bfin_sic_forward_interrupts (me, &sic->bf537.isr, &sic->bf537.imask, &sic->bf537.iar0); | |
245 | } | |
246 | ||
247 | static unsigned | |
248 | bfin_sic_537_io_write_buffer (struct hw *me, const void *source, int space, | |
249 | address_word addr, unsigned nr_bytes) | |
250 | { | |
251 | struct bfin_sic *sic = hw_data (me); | |
252 | bu32 mmr_off; | |
253 | bu32 value; | |
254 | bu16 *value16p; | |
255 | bu32 *value32p; | |
256 | void *valuep; | |
257 | ||
258 | if (nr_bytes == 4) | |
259 | value = dv_load_4 (source); | |
260 | else | |
261 | value = dv_load_2 (source); | |
262 | ||
263 | mmr_off = addr - sic->base; | |
264 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
265 | value16p = valuep; | |
266 | value32p = valuep; | |
267 | ||
268 | HW_TRACE_WRITE (); | |
269 | ||
270 | /* XXX: Discard all SIC writes for now. */ | |
271 | switch (mmr_off) | |
272 | { | |
273 | case mmr_offset(swrst): | |
274 | /* XXX: This should trigger a software reset ... */ | |
275 | break; | |
276 | case mmr_offset(syscr): | |
277 | /* XXX: what to do ... */ | |
278 | break; | |
279 | case mmr_offset(bf537.imask): | |
280 | bfin_sic_537_forward_interrupts (me, sic); | |
281 | *value32p = value; | |
282 | break; | |
283 | case mmr_offset(bf537.iar0): | |
284 | case mmr_offset(bf537.iar1): | |
285 | case mmr_offset(bf537.iar2): | |
286 | case mmr_offset(bf537.iar3): | |
287 | case mmr_offset(bf537.iwr): | |
288 | *value32p = value; | |
289 | break; | |
290 | case mmr_offset(bf537.isr): | |
291 | /* ISR is read-only. */ | |
292 | break; | |
293 | default: | |
294 | /* XXX: Should discard other writes. */ | |
295 | ; | |
296 | } | |
297 | ||
298 | return nr_bytes; | |
299 | } | |
300 | ||
301 | static unsigned | |
302 | bfin_sic_537_io_read_buffer (struct hw *me, void *dest, int space, | |
303 | address_word addr, unsigned nr_bytes) | |
304 | { | |
305 | struct bfin_sic *sic = hw_data (me); | |
306 | bu32 mmr_off; | |
307 | bu16 *value16p; | |
308 | bu32 *value32p; | |
309 | void *valuep; | |
310 | ||
311 | mmr_off = addr - sic->base; | |
312 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
313 | value16p = valuep; | |
314 | value32p = valuep; | |
315 | ||
316 | HW_TRACE_READ (); | |
317 | ||
318 | switch (mmr_off) | |
319 | { | |
320 | case mmr_offset(swrst): | |
321 | case mmr_offset(syscr): | |
322 | case mmr_offset(rvect): | |
323 | dv_store_2 (dest, *value16p); | |
324 | break; | |
325 | case mmr_offset(bf537.imask): | |
326 | case mmr_offset(bf537.iar0): | |
327 | case mmr_offset(bf537.iar1): | |
328 | case mmr_offset(bf537.iar2): | |
329 | case mmr_offset(bf537.iar3): | |
330 | case mmr_offset(bf537.isr): | |
331 | case mmr_offset(bf537.iwr): | |
332 | dv_store_4 (dest, *value32p); | |
333 | break; | |
334 | default: | |
335 | if (nr_bytes == 2) | |
336 | dv_store_2 (dest, 0); | |
337 | else | |
338 | dv_store_4 (dest, 0); | |
339 | break; | |
340 | } | |
341 | ||
342 | return nr_bytes; | |
343 | } | |
344 | ||
345 | static void | |
346 | bfin_sic_54x_forward_interrupts (struct hw *me, struct bfin_sic *sic) | |
347 | { | |
348 | bfin_sic_forward_interrupts (me, &sic->bf54x.isr0, &sic->bf54x.imask0, &sic->bf54x.iar0); | |
349 | bfin_sic_forward_interrupts (me, &sic->bf54x.isr1, &sic->bf54x.imask1, &sic->bf54x.iar4); | |
350 | bfin_sic_forward_interrupts (me, &sic->bf54x.isr2, &sic->bf54x.imask2, &sic->bf54x.iar8); | |
351 | } | |
352 | ||
353 | static unsigned | |
354 | bfin_sic_54x_io_write_buffer (struct hw *me, const void *source, int space, | |
355 | address_word addr, unsigned nr_bytes) | |
356 | { | |
357 | struct bfin_sic *sic = hw_data (me); | |
358 | bu32 mmr_off; | |
359 | bu32 value; | |
360 | bu16 *value16p; | |
361 | bu32 *value32p; | |
362 | void *valuep; | |
363 | ||
364 | if (nr_bytes == 4) | |
365 | value = dv_load_4 (source); | |
366 | else | |
367 | value = dv_load_2 (source); | |
368 | ||
369 | mmr_off = addr - sic->base; | |
370 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
371 | value16p = valuep; | |
372 | value32p = valuep; | |
373 | ||
374 | HW_TRACE_WRITE (); | |
375 | ||
376 | /* XXX: Discard all SIC writes for now. */ | |
377 | switch (mmr_off) | |
378 | { | |
379 | case mmr_offset(swrst): | |
380 | /* XXX: This should trigger a software reset ... */ | |
381 | break; | |
382 | case mmr_offset(syscr): | |
383 | /* XXX: what to do ... */ | |
384 | break; | |
385 | case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2): | |
386 | bfin_sic_54x_forward_interrupts (me, sic); | |
387 | *value32p = value; | |
388 | break; | |
389 | case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11): | |
390 | case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2): | |
391 | *value32p = value; | |
392 | break; | |
393 | case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2): | |
394 | /* ISR is read-only. */ | |
395 | break; | |
396 | default: | |
397 | /* XXX: Should discard other writes. */ | |
398 | ; | |
399 | } | |
400 | ||
401 | return nr_bytes; | |
402 | } | |
403 | ||
404 | static unsigned | |
405 | bfin_sic_54x_io_read_buffer (struct hw *me, void *dest, int space, | |
406 | address_word addr, unsigned nr_bytes) | |
407 | { | |
408 | struct bfin_sic *sic = hw_data (me); | |
409 | bu32 mmr_off; | |
410 | bu16 *value16p; | |
411 | bu32 *value32p; | |
412 | void *valuep; | |
413 | ||
414 | mmr_off = addr - sic->base; | |
415 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
416 | value16p = valuep; | |
417 | value32p = valuep; | |
418 | ||
419 | HW_TRACE_READ (); | |
420 | ||
421 | switch (mmr_off) | |
422 | { | |
423 | case mmr_offset(swrst): | |
424 | case mmr_offset(syscr): | |
425 | case mmr_offset(rvect): | |
426 | dv_store_2 (dest, *value16p); | |
427 | break; | |
428 | case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2): | |
429 | case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11): | |
430 | case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2): | |
431 | case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2): | |
432 | dv_store_4 (dest, *value32p); | |
433 | break; | |
434 | default: | |
435 | if (nr_bytes == 2) | |
436 | dv_store_2 (dest, 0); | |
437 | else | |
438 | dv_store_4 (dest, 0); | |
439 | break; | |
440 | } | |
441 | ||
442 | return nr_bytes; | |
443 | } | |
444 | ||
445 | static void | |
446 | bfin_sic_561_forward_interrupts (struct hw *me, struct bfin_sic *sic) | |
447 | { | |
448 | bfin_sic_forward_interrupts (me, &sic->bf561.isr0, &sic->bf561.imask0, &sic->bf561.iar0); | |
449 | bfin_sic_forward_interrupts (me, &sic->bf561.isr1, &sic->bf561.imask1, &sic->bf561.iar4); | |
450 | } | |
451 | ||
452 | static unsigned | |
453 | bfin_sic_561_io_write_buffer (struct hw *me, const void *source, int space, | |
454 | address_word addr, unsigned nr_bytes) | |
455 | { | |
456 | struct bfin_sic *sic = hw_data (me); | |
457 | bu32 mmr_off; | |
458 | bu32 value; | |
459 | bu16 *value16p; | |
460 | bu32 *value32p; | |
461 | void *valuep; | |
462 | ||
463 | if (nr_bytes == 4) | |
464 | value = dv_load_4 (source); | |
465 | else | |
466 | value = dv_load_2 (source); | |
467 | ||
468 | mmr_off = addr - sic->base; | |
469 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
470 | value16p = valuep; | |
471 | value32p = valuep; | |
472 | ||
473 | HW_TRACE_WRITE (); | |
474 | ||
475 | /* XXX: Discard all SIC writes for now. */ | |
476 | switch (mmr_off) | |
477 | { | |
478 | case mmr_offset(swrst): | |
479 | /* XXX: This should trigger a software reset ... */ | |
480 | break; | |
481 | case mmr_offset(syscr): | |
482 | /* XXX: what to do ... */ | |
483 | break; | |
484 | case mmr_offset(bf561.imask0): | |
485 | case mmr_offset(bf561.imask1): | |
486 | bfin_sic_561_forward_interrupts (me, sic); | |
487 | *value32p = value; | |
488 | break; | |
489 | case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3): | |
490 | case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7): | |
491 | case mmr_offset(bf561.iwr0): | |
492 | case mmr_offset(bf561.iwr1): | |
493 | *value32p = value; | |
494 | break; | |
495 | case mmr_offset(bf561.isr0): | |
496 | case mmr_offset(bf561.isr1): | |
497 | /* ISR is read-only. */ | |
498 | break; | |
499 | default: | |
500 | /* XXX: Should discard other writes. */ | |
501 | ; | |
502 | } | |
503 | ||
504 | return nr_bytes; | |
505 | } | |
506 | ||
507 | static unsigned | |
508 | bfin_sic_561_io_read_buffer (struct hw *me, void *dest, int space, | |
509 | address_word addr, unsigned nr_bytes) | |
510 | { | |
511 | struct bfin_sic *sic = hw_data (me); | |
512 | bu32 mmr_off; | |
513 | bu16 *value16p; | |
514 | bu32 *value32p; | |
515 | void *valuep; | |
516 | ||
517 | mmr_off = addr - sic->base; | |
518 | valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); | |
519 | value16p = valuep; | |
520 | value32p = valuep; | |
521 | ||
522 | HW_TRACE_READ (); | |
523 | ||
524 | switch (mmr_off) | |
525 | { | |
526 | case mmr_offset(swrst): | |
527 | case mmr_offset(syscr): | |
528 | case mmr_offset(rvect): | |
529 | dv_store_2 (dest, *value16p); | |
530 | break; | |
531 | case mmr_offset(bf561.imask0): | |
532 | case mmr_offset(bf561.imask1): | |
533 | case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3): | |
534 | case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7): | |
535 | case mmr_offset(bf561.iwr0): | |
536 | case mmr_offset(bf561.iwr1): | |
537 | case mmr_offset(bf561.isr0): | |
538 | case mmr_offset(bf561.isr1): | |
539 | dv_store_4 (dest, *value32p); | |
540 | break; | |
541 | default: | |
542 | if (nr_bytes == 2) | |
543 | dv_store_2 (dest, 0); | |
544 | else | |
545 | dv_store_4 (dest, 0); | |
546 | break; | |
547 | } | |
548 | ||
549 | return nr_bytes; | |
550 | } | |
551 | ||
552 | /* XXX: This doesn't handle DMA<->peripheral mappings. */ | |
553 | #define BFIN_SIC_TO_CEC_PORTS \ | |
554 | { "ivg7", IVG7, 0, output_port, }, \ | |
555 | { "ivg8", IVG8, 0, output_port, }, \ | |
556 | { "ivg9", IVG9, 0, output_port, }, \ | |
557 | { "ivg10", IVG10, 0, output_port, }, \ | |
558 | { "ivg11", IVG11, 0, output_port, }, \ | |
559 | { "ivg12", IVG12, 0, output_port, }, \ | |
560 | { "ivg13", IVG13, 0, output_port, }, \ | |
561 | { "ivg14", IVG14, 0, output_port, }, \ | |
562 | { "ivg15", IVG15, 0, output_port, }, | |
563 | ||
990d19fd MF |
564 | static const struct hw_port_descriptor bfin_sic_50x_ports[] = |
565 | { | |
ef016f83 MF |
566 | BFIN_SIC_TO_CEC_PORTS |
567 | /* SIC0 */ | |
568 | { "pll", 0, 0, input_port, }, | |
569 | { "dma_stat", 1, 0, input_port, }, | |
570 | { "ppi@0", 2, 0, input_port, }, | |
571 | { "sport@0_stat", 3, 0, input_port, }, | |
572 | { "sport@1_stat", 4, 0, input_port, }, | |
573 | { "uart2@0_stat", 5, 0, input_port, }, | |
574 | { "uart2@1_stat", 6, 0, input_port, }, | |
575 | { "spi@0", 7, 0, input_port, }, | |
576 | { "spi@1", 8, 0, input_port, }, | |
577 | { "can_stat", 9, 0, input_port, }, | |
578 | { "rsi_int0", 10, 0, input_port, }, | |
579 | /*{ "reserved", 11, 0, input_port, },*/ | |
580 | { "counter@0", 12, 0, input_port, }, | |
581 | { "counter@1", 13, 0, input_port, }, | |
582 | { "dma@0", 14, 0, input_port, }, | |
583 | { "dma@1", 15, 0, input_port, }, | |
584 | { "dma@2", 16, 0, input_port, }, | |
585 | { "dma@3", 17, 0, input_port, }, | |
586 | { "dma@4", 18, 0, input_port, }, | |
587 | { "dma@5", 19, 0, input_port, }, | |
588 | { "dma@6", 20, 0, input_port, }, | |
589 | { "dma@7", 21, 0, input_port, }, | |
590 | { "dma@8", 22, 0, input_port, }, | |
591 | { "dma@9", 23, 0, input_port, }, | |
592 | { "dma@10", 24, 0, input_port, }, | |
593 | { "dma@11", 25, 0, input_port, }, | |
594 | { "can_rx", 26, 0, input_port, }, | |
595 | { "can_tx", 27, 0, input_port, }, | |
596 | { "twi@0", 28, 0, input_port, }, | |
597 | { "portf_irq_a", 29, 0, input_port, }, | |
598 | { "portf_irq_b", 30, 0, input_port, }, | |
599 | /*{ "reserved", 31, 0, input_port, },*/ | |
600 | /* SIC1 */ | |
601 | { "gptimer@0", 100, 0, input_port, }, | |
602 | { "gptimer@1", 101, 0, input_port, }, | |
603 | { "gptimer@2", 102, 0, input_port, }, | |
604 | { "gptimer@3", 103, 0, input_port, }, | |
605 | { "gptimer@4", 104, 0, input_port, }, | |
606 | { "gptimer@5", 105, 0, input_port, }, | |
607 | { "gptimer@6", 106, 0, input_port, }, | |
608 | { "gptimer@7", 107, 0, input_port, }, | |
609 | { "portg_irq_a", 108, 0, input_port, }, | |
610 | { "portg_irq_b", 109, 0, input_port, }, | |
611 | { "mdma@0", 110, 0, input_port, }, | |
612 | { "mdma@1", 111, 0, input_port, }, | |
613 | { "wdog", 112, 0, input_port, }, | |
614 | { "porth_irq_a", 113, 0, input_port, }, | |
615 | { "porth_irq_b", 114, 0, input_port, }, | |
616 | { "acm_stat", 115, 0, input_port, }, | |
617 | { "acm_int", 116, 0, input_port, }, | |
618 | /*{ "reserved", 117, 0, input_port, },*/ | |
619 | /*{ "reserved", 118, 0, input_port, },*/ | |
620 | { "pwm@0_trip", 119, 0, input_port, }, | |
621 | { "pwm@0_sync", 120, 0, input_port, }, | |
622 | { "pwm@1_trip", 121, 0, input_port, }, | |
623 | { "pwm@1_sync", 122, 0, input_port, }, | |
624 | { "rsi_int1", 123, 0, input_port, }, | |
625 | { NULL, 0, 0, 0, }, | |
626 | }; | |
627 | ||
990d19fd MF |
628 | static const struct hw_port_descriptor bfin_sic_51x_ports[] = |
629 | { | |
ef016f83 MF |
630 | BFIN_SIC_TO_CEC_PORTS |
631 | /* SIC0 */ | |
632 | { "pll", 0, 0, input_port, }, | |
633 | { "dma_stat", 1, 0, input_port, }, | |
634 | { "dmar0_block", 2, 0, input_port, }, | |
635 | { "dmar1_block", 3, 0, input_port, }, | |
636 | { "dmar0_over", 4, 0, input_port, }, | |
637 | { "dmar1_over", 5, 0, input_port, }, | |
638 | { "ppi@0", 6, 0, input_port, }, | |
639 | { "emac_stat", 7, 0, input_port, }, | |
640 | { "sport@0_stat", 8, 0, input_port, }, | |
641 | { "sport@1_stat", 9, 0, input_port, }, | |
642 | { "ptp_err", 10, 0, input_port, }, | |
643 | /*{ "reserved", 11, 0, input_port, },*/ | |
644 | { "uart@0_stat", 12, 0, input_port, }, | |
645 | { "uart@1_stat", 13, 0, input_port, }, | |
646 | { "rtc", 14, 0, input_port, }, | |
647 | { "dma@0", 15, 0, input_port, }, | |
648 | { "dma@3", 16, 0, input_port, }, | |
649 | { "dma@4", 17, 0, input_port, }, | |
650 | { "dma@5", 18, 0, input_port, }, | |
651 | { "dma@6", 19, 0, input_port, }, | |
652 | { "twi@0", 20, 0, input_port, }, | |
653 | { "dma@7", 21, 0, input_port, }, | |
654 | { "dma@8", 22, 0, input_port, }, | |
655 | { "dma@9", 23, 0, input_port, }, | |
656 | { "dma@10", 24, 0, input_port, }, | |
657 | { "dma@11", 25, 0, input_port, }, | |
658 | { "otp", 26, 0, input_port, }, | |
659 | { "counter", 27, 0, input_port, }, | |
660 | { "dma@1", 28, 0, input_port, }, | |
661 | { "porth_irq_a", 29, 0, input_port, }, | |
662 | { "dma@2", 30, 0, input_port, }, | |
663 | { "porth_irq_b", 31, 0, input_port, }, | |
664 | /* SIC1 */ | |
665 | { "gptimer@0", 100, 0, input_port, }, | |
666 | { "gptimer@1", 101, 0, input_port, }, | |
667 | { "gptimer@2", 102, 0, input_port, }, | |
668 | { "gptimer@3", 103, 0, input_port, }, | |
669 | { "gptimer@4", 104, 0, input_port, }, | |
670 | { "gptimer@5", 105, 0, input_port, }, | |
671 | { "gptimer@6", 106, 0, input_port, }, | |
672 | { "gptimer@7", 107, 0, input_port, }, | |
673 | { "portg_irq_a", 108, 0, input_port, }, | |
674 | { "portg_irq_b", 109, 0, input_port, }, | |
675 | { "mdma@0", 110, 0, input_port, }, | |
676 | { "mdma@1", 111, 0, input_port, }, | |
677 | { "wdog", 112, 0, input_port, }, | |
678 | { "portf_irq_a", 113, 0, input_port, }, | |
679 | { "portf_irq_b", 114, 0, input_port, }, | |
680 | { "spi@0", 115, 0, input_port, }, | |
681 | { "spi@1", 116, 0, input_port, }, | |
682 | /*{ "reserved", 117, 0, input_port, },*/ | |
683 | /*{ "reserved", 118, 0, input_port, },*/ | |
684 | { "rsi_int0", 119, 0, input_port, }, | |
685 | { "rsi_int1", 120, 0, input_port, }, | |
686 | { "pwm_trip", 121, 0, input_port, }, | |
687 | { "pwm_sync", 122, 0, input_port, }, | |
688 | { "ptp_stat", 123, 0, input_port, }, | |
689 | { NULL, 0, 0, 0, }, | |
690 | }; | |
691 | ||
990d19fd MF |
692 | static const struct hw_port_descriptor bfin_sic_52x_ports[] = |
693 | { | |
ef016f83 MF |
694 | BFIN_SIC_TO_CEC_PORTS |
695 | /* SIC0 */ | |
696 | { "pll", 0, 0, input_port, }, | |
697 | { "dma_stat", 1, 0, input_port, }, | |
698 | { "dmar0_block", 2, 0, input_port, }, | |
699 | { "dmar1_block", 3, 0, input_port, }, | |
700 | { "dmar0_over", 4, 0, input_port, }, | |
701 | { "dmar1_over", 5, 0, input_port, }, | |
702 | { "ppi@0", 6, 0, input_port, }, | |
703 | { "emac_stat", 7, 0, input_port, }, | |
704 | { "sport@0_stat", 8, 0, input_port, }, | |
705 | { "sport@1_stat", 9, 0, input_port, }, | |
706 | /*{ "reserved", 10, 0, input_port, },*/ | |
707 | /*{ "reserved", 11, 0, input_port, },*/ | |
708 | { "uart@0_stat", 12, 0, input_port, }, | |
709 | { "uart@1_stat", 13, 0, input_port, }, | |
710 | { "rtc", 14, 0, input_port, }, | |
711 | { "dma@0", 15, 0, input_port, }, | |
712 | { "dma@3", 16, 0, input_port, }, | |
713 | { "dma@4", 17, 0, input_port, }, | |
714 | { "dma@5", 18, 0, input_port, }, | |
715 | { "dma@6", 19, 0, input_port, }, | |
716 | { "twi@0", 20, 0, input_port, }, | |
717 | { "dma@7", 21, 0, input_port, }, | |
718 | { "dma@8", 22, 0, input_port, }, | |
719 | { "dma@9", 23, 0, input_port, }, | |
720 | { "dma@10", 24, 0, input_port, }, | |
721 | { "dma@11", 25, 0, input_port, }, | |
722 | { "otp", 26, 0, input_port, }, | |
723 | { "counter", 27, 0, input_port, }, | |
724 | { "dma@1", 28, 0, input_port, }, | |
725 | { "porth_irq_a", 29, 0, input_port, }, | |
726 | { "dma@2", 30, 0, input_port, }, | |
727 | { "porth_irq_b", 31, 0, input_port, }, | |
728 | /* SIC1 */ | |
729 | { "gptimer@0", 100, 0, input_port, }, | |
730 | { "gptimer@1", 101, 0, input_port, }, | |
731 | { "gptimer@2", 102, 0, input_port, }, | |
732 | { "gptimer@3", 103, 0, input_port, }, | |
733 | { "gptimer@4", 104, 0, input_port, }, | |
734 | { "gptimer@5", 105, 0, input_port, }, | |
735 | { "gptimer@6", 106, 0, input_port, }, | |
736 | { "gptimer@7", 107, 0, input_port, }, | |
737 | { "portg_irq_a", 108, 0, input_port, }, | |
738 | { "portg_irq_b", 109, 0, input_port, }, | |
739 | { "mdma@0", 110, 0, input_port, }, | |
740 | { "mdma@1", 111, 0, input_port, }, | |
741 | { "wdog", 112, 0, input_port, }, | |
742 | { "portf_irq_a", 113, 0, input_port, }, | |
743 | { "portf_irq_b", 114, 0, input_port, }, | |
744 | { "spi@0", 115, 0, input_port, }, | |
745 | { "nfc_stat", 116, 0, input_port, }, | |
746 | { "hostdp_stat", 117, 0, input_port, }, | |
747 | { "hostdp_done", 118, 0, input_port, }, | |
748 | { "usb_int0", 120, 0, input_port, }, | |
749 | { "usb_int1", 121, 0, input_port, }, | |
750 | { "usb_int2", 122, 0, input_port, }, | |
751 | { NULL, 0, 0, 0, }, | |
752 | }; | |
753 | ||
754 | static void | |
755 | bfin_sic_52x_port_event (struct hw *me, int my_port, struct hw *source, | |
756 | int source_port, int level) | |
757 | { | |
758 | struct bfin_sic *sic = hw_data (me); | |
759 | bu32 idx = my_port / 100; | |
760 | bu32 bit = (1 << (my_port & 0x1f)); | |
761 | ||
762 | /* SIC only exists to forward interrupts from the system to the CEC. */ | |
763 | switch (idx) | |
764 | { | |
765 | case 0: sic->bf52x.isr0 |= bit; break; | |
766 | case 1: sic->bf52x.isr1 |= bit; break; | |
767 | } | |
768 | ||
769 | /* XXX: Handle SIC wakeup source ? | |
770 | if (sic->bf52x.iwr0 & bit) | |
771 | What to do ?; | |
772 | if (sic->bf52x.iwr1 & bit) | |
773 | What to do ?; | |
774 | */ | |
775 | ||
776 | bfin_sic_52x_forward_interrupts (me, sic); | |
777 | } | |
778 | ||
990d19fd MF |
779 | static const struct hw_port_descriptor bfin_sic_533_ports[] = |
780 | { | |
ef016f83 MF |
781 | BFIN_SIC_TO_CEC_PORTS |
782 | { "pll", 0, 0, input_port, }, | |
783 | { "dma_stat", 1, 0, input_port, }, | |
784 | { "ppi@0", 2, 0, input_port, }, | |
785 | { "sport@0_stat", 3, 0, input_port, }, | |
786 | { "sport@1_stat", 4, 0, input_port, }, | |
787 | { "spi@0", 5, 0, input_port, }, | |
788 | { "uart@0_stat", 6, 0, input_port, }, | |
789 | { "rtc", 7, 0, input_port, }, | |
790 | { "dma@0", 8, 0, input_port, }, | |
791 | { "dma@1", 9, 0, input_port, }, | |
792 | { "dma@2", 10, 0, input_port, }, | |
793 | { "dma@3", 11, 0, input_port, }, | |
794 | { "dma@4", 12, 0, input_port, }, | |
795 | { "dma@5", 13, 0, input_port, }, | |
796 | { "dma@6", 14, 0, input_port, }, | |
797 | { "dma@7", 15, 0, input_port, }, | |
798 | { "gptimer@0", 16, 0, input_port, }, | |
799 | { "gptimer@1", 17, 0, input_port, }, | |
800 | { "gptimer@2", 18, 0, input_port, }, | |
801 | { "portf_irq_a", 19, 0, input_port, }, | |
802 | { "portf_irq_b", 20, 0, input_port, }, | |
803 | { "mdma@0", 21, 0, input_port, }, | |
804 | { "mdma@1", 22, 0, input_port, }, | |
805 | { "wdog", 23, 0, input_port, }, | |
806 | { NULL, 0, 0, 0, }, | |
807 | }; | |
808 | ||
809 | static void | |
810 | bfin_sic_533_port_event (struct hw *me, int my_port, struct hw *source, | |
811 | int source_port, int level) | |
812 | { | |
813 | struct bfin_sic *sic = hw_data (me); | |
814 | bu32 bit = (1 << my_port); | |
815 | ||
816 | /* SIC only exists to forward interrupts from the system to the CEC. */ | |
817 | sic->bf537.isr |= bit; | |
818 | ||
819 | /* XXX: Handle SIC wakeup source ? | |
820 | if (sic->bf537.iwr & bit) | |
821 | What to do ?; | |
822 | */ | |
823 | ||
824 | bfin_sic_537_forward_interrupts (me, sic); | |
825 | } | |
826 | ||
990d19fd MF |
827 | static const struct hw_port_descriptor bfin_sic_537_ports[] = |
828 | { | |
ef016f83 MF |
829 | BFIN_SIC_TO_CEC_PORTS |
830 | { "pll", 0, 0, input_port, }, | |
831 | { "dma_stat", 10, 0, input_port, }, | |
832 | { "dmar0_block", 11, 0, input_port, }, | |
833 | { "dmar1_block", 12, 0, input_port, }, | |
834 | { "dmar0_over", 13, 0, input_port, }, | |
835 | { "dmar1_over", 14, 0, input_port, }, | |
836 | { "can_stat", 20, 0, input_port, }, | |
837 | { "emac_stat", 21, 0, input_port, }, | |
838 | { "sport@0_stat", 22, 0, input_port, }, | |
839 | { "sport@1_stat", 23, 0, input_port, }, | |
840 | { "ppi@0", 24, 0, input_port, }, | |
841 | { "spi@0", 25, 0, input_port, }, | |
842 | { "uart@0_stat", 26, 0, input_port, }, | |
843 | { "uart@1_stat", 27, 0, input_port, }, | |
844 | { "rtc", 30, 0, input_port, }, | |
845 | { "dma@0", 40, 0, input_port, }, | |
846 | { "dma@3", 50, 0, input_port, }, | |
847 | { "dma@4", 60, 0, input_port, }, | |
848 | { "dma@5", 70, 0, input_port, }, | |
849 | { "dma@6", 80, 0, input_port, }, | |
850 | { "twi@0", 90, 0, input_port, }, | |
851 | { "dma@7", 100, 0, input_port, }, | |
852 | { "dma@8", 110, 0, input_port, }, | |
853 | { "dma@9", 120, 0, input_port, }, | |
854 | { "dma@10", 130, 0, input_port, }, | |
855 | { "dma@11", 140, 0, input_port, }, | |
856 | { "can_rx", 150, 0, input_port, }, | |
857 | { "can_tx", 160, 0, input_port, }, | |
858 | { "dma@1", 170, 0, input_port, }, | |
859 | { "porth_irq_a", 171, 0, input_port, }, | |
860 | { "dma@2", 180, 0, input_port, }, | |
861 | { "porth_irq_b", 181, 0, input_port, }, | |
862 | { "gptimer@0", 190, 0, input_port, }, | |
863 | { "gptimer@1", 200, 0, input_port, }, | |
864 | { "gptimer@2", 210, 0, input_port, }, | |
865 | { "gptimer@3", 220, 0, input_port, }, | |
866 | { "gptimer@4", 230, 0, input_port, }, | |
867 | { "gptimer@5", 240, 0, input_port, }, | |
868 | { "gptimer@6", 250, 0, input_port, }, | |
869 | { "gptimer@7", 260, 0, input_port, }, | |
870 | { "portf_irq_a", 270, 0, input_port, }, | |
871 | { "portg_irq_a", 271, 0, input_port, }, | |
872 | { "portg_irq_b", 280, 0, input_port, }, | |
873 | { "mdma@0", 290, 0, input_port, }, | |
874 | { "mdma@1", 300, 0, input_port, }, | |
875 | { "wdog", 310, 0, input_port, }, | |
876 | { "portf_irq_b", 311, 0, input_port, }, | |
877 | { NULL, 0, 0, 0, }, | |
878 | }; | |
879 | ||
880 | static void | |
881 | bfin_sic_537_port_event (struct hw *me, int my_port, struct hw *source, | |
882 | int source_port, int level) | |
883 | { | |
884 | struct bfin_sic *sic = hw_data (me); | |
885 | bu32 bit = (1 << (my_port / 10)); | |
886 | ||
887 | /* SIC only exists to forward interrupts from the system to the CEC. */ | |
888 | sic->bf537.isr |= bit; | |
889 | ||
890 | /* XXX: Handle SIC wakeup source ? | |
891 | if (sic->bf537.iwr & bit) | |
892 | What to do ?; | |
893 | */ | |
894 | ||
895 | bfin_sic_537_forward_interrupts (me, sic); | |
896 | } | |
897 | ||
990d19fd MF |
898 | static const struct hw_port_descriptor bfin_sic_538_ports[] = |
899 | { | |
ef016f83 MF |
900 | BFIN_SIC_TO_CEC_PORTS |
901 | /* SIC0 */ | |
902 | { "pll", 0, 0, input_port, }, | |
903 | { "dmac@0_stat", 1, 0, input_port, }, | |
904 | { "ppi@0", 2, 0, input_port, }, | |
905 | { "sport@0_stat", 3, 0, input_port, }, | |
906 | { "sport@1_stat", 4, 0, input_port, }, | |
907 | { "spi@0", 5, 0, input_port, }, | |
908 | { "uart@0_stat", 6, 0, input_port, }, | |
909 | { "rtc", 7, 0, input_port, }, | |
910 | { "dma@0", 8, 0, input_port, }, | |
911 | { "dma@1", 9, 0, input_port, }, | |
912 | { "dma@2", 10, 0, input_port, }, | |
913 | { "dma@3", 11, 0, input_port, }, | |
914 | { "dma@4", 12, 0, input_port, }, | |
915 | { "dma@5", 13, 0, input_port, }, | |
916 | { "dma@6", 14, 0, input_port, }, | |
917 | { "dma@7", 15, 0, input_port, }, | |
918 | { "gptimer@0", 16, 0, input_port, }, | |
919 | { "gptimer@1", 17, 0, input_port, }, | |
920 | { "gptimer@2", 18, 0, input_port, }, | |
921 | { "portf_irq_a", 19, 0, input_port, }, | |
922 | { "portf_irq_b", 20, 0, input_port, }, | |
923 | { "mdma@0", 21, 0, input_port, }, | |
924 | { "mdma@1", 22, 0, input_port, }, | |
925 | { "wdog", 23, 0, input_port, }, | |
926 | { "dmac@1_stat", 24, 0, input_port, }, | |
927 | { "sport@2_stat", 25, 0, input_port, }, | |
928 | { "sport@3_stat", 26, 0, input_port, }, | |
929 | /*{ "reserved", 27, 0, input_port, },*/ | |
930 | { "spi@1", 28, 0, input_port, }, | |
931 | { "spi@2", 29, 0, input_port, }, | |
932 | { "uart@1_stat", 30, 0, input_port, }, | |
933 | { "uart@2_stat", 31, 0, input_port, }, | |
934 | /* SIC1 */ | |
935 | { "can_stat", 100, 0, input_port, }, | |
936 | { "dma@8", 101, 0, input_port, }, | |
937 | { "dma@9", 102, 0, input_port, }, | |
938 | { "dma@10", 103, 0, input_port, }, | |
939 | { "dma@11", 104, 0, input_port, }, | |
940 | { "dma@12", 105, 0, input_port, }, | |
941 | { "dma@13", 106, 0, input_port, }, | |
942 | { "dma@14", 107, 0, input_port, }, | |
943 | { "dma@15", 108, 0, input_port, }, | |
944 | { "dma@16", 109, 0, input_port, }, | |
945 | { "dma@17", 110, 0, input_port, }, | |
946 | { "dma@18", 111, 0, input_port, }, | |
947 | { "dma@19", 112, 0, input_port, }, | |
948 | { "twi@0", 113, 0, input_port, }, | |
949 | { "twi@1", 114, 0, input_port, }, | |
950 | { "can_rx", 115, 0, input_port, }, | |
951 | { "can_tx", 116, 0, input_port, }, | |
952 | { "mdma@2", 117, 0, input_port, }, | |
953 | { "mdma@3", 118, 0, input_port, }, | |
954 | { NULL, 0, 0, 0, }, | |
955 | }; | |
956 | ||
990d19fd MF |
957 | static const struct hw_port_descriptor bfin_sic_54x_ports[] = |
958 | { | |
ef016f83 MF |
959 | BFIN_SIC_TO_CEC_PORTS |
960 | /* SIC0 */ | |
961 | { "pll", 0, 0, input_port, }, | |
962 | { "dmac@0_stat", 1, 0, input_port, }, | |
963 | { "eppi@0", 2, 0, input_port, }, | |
964 | { "sport@0_stat", 3, 0, input_port, }, | |
965 | { "sport@1_stat", 4, 0, input_port, }, | |
966 | { "spi@0", 5, 0, input_port, }, | |
967 | { "uart2@0_stat", 6, 0, input_port, }, | |
968 | { "rtc", 7, 0, input_port, }, | |
969 | { "dma@12", 8, 0, input_port, }, | |
970 | { "dma@0", 9, 0, input_port, }, | |
971 | { "dma@1", 10, 0, input_port, }, | |
972 | { "dma@2", 11, 0, input_port, }, | |
973 | { "dma@3", 12, 0, input_port, }, | |
974 | { "dma@4", 13, 0, input_port, }, | |
975 | { "dma@6", 14, 0, input_port, }, | |
976 | { "dma@7", 15, 0, input_port, }, | |
977 | { "gptimer@8", 16, 0, input_port, }, | |
978 | { "gptimer@9", 17, 0, input_port, }, | |
979 | { "gptimer@10", 18, 0, input_port, }, | |
980 | { "pint@0", 19, 0, input_port, }, | |
981 | { "pint@1", 20, 0, input_port, }, | |
982 | { "mdma@0", 21, 0, input_port, }, | |
983 | { "mdma@1", 22, 0, input_port, }, | |
984 | { "wdog", 23, 0, input_port, }, | |
985 | { "dmac@1_stat", 24, 0, input_port, }, | |
986 | { "sport@2_stat", 25, 0, input_port, }, | |
987 | { "sport@3_stat", 26, 0, input_port, }, | |
988 | { "mxvr", 27, 0, input_port, }, | |
989 | { "spi@1", 28, 0, input_port, }, | |
990 | { "spi@2", 29, 0, input_port, }, | |
991 | { "uart2@1_stat", 30, 0, input_port, }, | |
992 | { "uart2@2_stat", 31, 0, input_port, }, | |
993 | /* SIC1 */ | |
994 | { "can@0_stat", 32, 0, input_port, }, | |
995 | { "dma@18", 33, 0, input_port, }, | |
996 | { "dma@19", 34, 0, input_port, }, | |
997 | { "dma@20", 35, 0, input_port, }, | |
998 | { "dma@21", 36, 0, input_port, }, | |
999 | { "dma@13", 37, 0, input_port, }, | |
1000 | { "dma@14", 38, 0, input_port, }, | |
1001 | { "dma@5", 39, 0, input_port, }, | |
1002 | { "dma@23", 40, 0, input_port, }, | |
1003 | { "dma@8", 41, 0, input_port, }, | |
1004 | { "dma@9", 42, 0, input_port, }, | |
1005 | { "dma@10", 43, 0, input_port, }, | |
1006 | { "dma@11", 44, 0, input_port, }, | |
1007 | { "twi@0", 45, 0, input_port, }, | |
1008 | { "twi@1", 46, 0, input_port, }, | |
1009 | { "can@0_rx", 47, 0, input_port, }, | |
1010 | { "can@0_tx", 48, 0, input_port, }, | |
1011 | { "mdma@2", 49, 0, input_port, }, | |
1012 | { "mdma@3", 50, 0, input_port, }, | |
1013 | { "mxvr_stat", 51, 0, input_port, }, | |
1014 | { "mxvr_message", 52, 0, input_port, }, | |
1015 | { "mxvr_packet", 53, 0, input_port, }, | |
1016 | { "eppi@1", 54, 0, input_port, }, | |
1017 | { "eppi@2", 55, 0, input_port, }, | |
1018 | { "uart2@3_stat", 56, 0, input_port, }, | |
1019 | { "hostdp", 57, 0, input_port, }, | |
1020 | /*{ "reserved", 58, 0, input_port, },*/ | |
1021 | { "pixc_stat", 59, 0, input_port, }, | |
1022 | { "nfc", 60, 0, input_port, }, | |
1023 | { "atapi", 61, 0, input_port, }, | |
1024 | { "can@1_stat", 62, 0, input_port, }, | |
1025 | { "dmar", 63, 0, input_port, }, | |
1026 | /* SIC2 */ | |
1027 | { "dma@15", 64, 0, input_port, }, | |
1028 | { "dma@16", 65, 0, input_port, }, | |
1029 | { "dma@17", 66, 0, input_port, }, | |
1030 | { "dma@22", 67, 0, input_port, }, | |
1031 | { "counter", 68, 0, input_port, }, | |
1032 | { "key", 69, 0, input_port, }, | |
1033 | { "can@1_rx", 70, 0, input_port, }, | |
1034 | { "can@1_tx", 71, 0, input_port, }, | |
1035 | { "sdh_mask0", 72, 0, input_port, }, | |
1036 | { "sdh_mask1", 73, 0, input_port, }, | |
1037 | /*{ "reserved", 74, 0, input_port, },*/ | |
1038 | { "usb_int0", 75, 0, input_port, }, | |
1039 | { "usb_int1", 76, 0, input_port, }, | |
1040 | { "usb_int2", 77, 0, input_port, }, | |
1041 | { "usb_dma", 78, 0, input_port, }, | |
1042 | { "otpsec", 79, 0, input_port, }, | |
1043 | /*{ "reserved", 80, 0, input_port, },*/ | |
1044 | /*{ "reserved", 81, 0, input_port, },*/ | |
1045 | /*{ "reserved", 82, 0, input_port, },*/ | |
1046 | /*{ "reserved", 83, 0, input_port, },*/ | |
1047 | /*{ "reserved", 84, 0, input_port, },*/ | |
1048 | /*{ "reserved", 85, 0, input_port, },*/ | |
1049 | { "gptimer@0", 86, 0, input_port, }, | |
1050 | { "gptimer@1", 87, 0, input_port, }, | |
1051 | { "gptimer@2", 88, 0, input_port, }, | |
1052 | { "gptimer@3", 89, 0, input_port, }, | |
1053 | { "gptimer@4", 90, 0, input_port, }, | |
1054 | { "gptimer@5", 91, 0, input_port, }, | |
1055 | { "gptimer@6", 92, 0, input_port, }, | |
1056 | { "gptimer@7", 93, 0, input_port, }, | |
1057 | { "pint2", 94, 0, input_port, }, | |
1058 | { "pint3", 95, 0, input_port, }, | |
1059 | { NULL, 0, 0, 0, }, | |
1060 | }; | |
1061 | ||
1062 | static void | |
1063 | bfin_sic_54x_port_event (struct hw *me, int my_port, struct hw *source, | |
1064 | int source_port, int level) | |
1065 | { | |
1066 | struct bfin_sic *sic = hw_data (me); | |
1067 | bu32 idx = my_port / 100; | |
1068 | bu32 bit = (1 << (my_port & 0x1f)); | |
1069 | ||
1070 | /* SIC only exists to forward interrupts from the system to the CEC. */ | |
1071 | switch (idx) | |
1072 | { | |
1073 | case 0: sic->bf54x.isr0 |= bit; break; | |
1074 | case 1: sic->bf54x.isr1 |= bit; break; | |
1075 | case 2: sic->bf54x.isr2 |= bit; break; | |
1076 | } | |
1077 | ||
1078 | /* XXX: Handle SIC wakeup source ? | |
1079 | if (sic->bf54x.iwr0 & bit) | |
1080 | What to do ?; | |
1081 | if (sic->bf54x.iwr1 & bit) | |
1082 | What to do ?; | |
1083 | if (sic->bf54x.iwr2 & bit) | |
1084 | What to do ?; | |
1085 | */ | |
1086 | ||
1087 | bfin_sic_54x_forward_interrupts (me, sic); | |
1088 | } | |
1089 | ||
990d19fd MF |
1090 | static const struct hw_port_descriptor bfin_sic_561_ports[] = |
1091 | { | |
ef016f83 MF |
1092 | BFIN_SIC_TO_CEC_PORTS |
1093 | /* SIC0 */ | |
1094 | { "pll", 0, 0, input_port, }, | |
1095 | { "dmac@0_stat", 1, 0, input_port, }, | |
1096 | { "dmac@1_stat", 2, 0, input_port, }, | |
1097 | { "imdma_stat", 3, 0, input_port, }, | |
1098 | { "ppi@0", 4, 0, input_port, }, | |
1099 | { "ppi@1", 5, 0, input_port, }, | |
1100 | { "sport@0_stat", 6, 0, input_port, }, | |
1101 | { "sport@1_stat", 7, 0, input_port, }, | |
1102 | { "spi@0", 8, 0, input_port, }, | |
1103 | { "uart@0_stat", 9, 0, input_port, }, | |
1104 | /*{ "reserved", 10, 0, input_port, },*/ | |
1105 | { "dma@12", 11, 0, input_port, }, | |
1106 | { "dma@13", 12, 0, input_port, }, | |
1107 | { "dma@14", 13, 0, input_port, }, | |
1108 | { "dma@15", 14, 0, input_port, }, | |
1109 | { "dma@16", 15, 0, input_port, }, | |
1110 | { "dma@17", 16, 0, input_port, }, | |
1111 | { "dma@18", 17, 0, input_port, }, | |
1112 | { "dma@19", 18, 0, input_port, }, | |
1113 | { "dma@20", 19, 0, input_port, }, | |
1114 | { "dma@21", 20, 0, input_port, }, | |
1115 | { "dma@22", 21, 0, input_port, }, | |
1116 | { "dma@23", 22, 0, input_port, }, | |
1117 | { "dma@0", 23, 0, input_port, }, | |
1118 | { "dma@1", 24, 0, input_port, }, | |
1119 | { "dma@2", 25, 0, input_port, }, | |
1120 | { "dma@3", 26, 0, input_port, }, | |
1121 | { "dma@4", 27, 0, input_port, }, | |
1122 | { "dma@5", 28, 0, input_port, }, | |
1123 | { "dma@6", 29, 0, input_port, }, | |
1124 | { "dma@7", 30, 0, input_port, }, | |
1125 | { "dma@8", 31, 0, input_port, }, | |
1126 | /* SIC1 */ | |
1127 | { "dma@9", 100, 0, input_port, }, | |
1128 | { "dma@10", 101, 0, input_port, }, | |
1129 | { "dma@11", 102, 0, input_port, }, | |
1130 | { "gptimer@0", 103, 0, input_port, }, | |
1131 | { "gptimer@1", 104, 0, input_port, }, | |
1132 | { "gptimer@2", 105, 0, input_port, }, | |
1133 | { "gptimer@3", 106, 0, input_port, }, | |
1134 | { "gptimer@4", 107, 0, input_port, }, | |
1135 | { "gptimer@5", 108, 0, input_port, }, | |
1136 | { "gptimer@6", 109, 0, input_port, }, | |
1137 | { "gptimer@7", 110, 0, input_port, }, | |
1138 | { "gptimer@8", 111, 0, input_port, }, | |
1139 | { "gptimer@9", 112, 0, input_port, }, | |
1140 | { "gptimer@10", 113, 0, input_port, }, | |
1141 | { "gptimer@11", 114, 0, input_port, }, | |
1142 | { "portf_irq_a", 115, 0, input_port, }, | |
1143 | { "portf_irq_b", 116, 0, input_port, }, | |
1144 | { "portg_irq_a", 117, 0, input_port, }, | |
1145 | { "portg_irq_b", 118, 0, input_port, }, | |
1146 | { "porth_irq_a", 119, 0, input_port, }, | |
1147 | { "porth_irq_b", 120, 0, input_port, }, | |
1148 | { "mdma@0", 121, 0, input_port, }, | |
1149 | { "mdma@1", 122, 0, input_port, }, | |
1150 | { "mdma@2", 123, 0, input_port, }, | |
1151 | { "mdma@3", 124, 0, input_port, }, | |
1152 | { "imdma@0", 125, 0, input_port, }, | |
1153 | { "imdma@1", 126, 0, input_port, }, | |
1154 | { "wdog", 127, 0, input_port, }, | |
1155 | /*{ "reserved", 128, 0, input_port, },*/ | |
1156 | /*{ "reserved", 129, 0, input_port, },*/ | |
1157 | { "sup_irq_0", 130, 0, input_port, }, | |
1158 | { "sup_irq_1", 131, 0, input_port, }, | |
1159 | { NULL, 0, 0, 0, }, | |
1160 | }; | |
1161 | ||
1162 | static void | |
1163 | bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source, | |
1164 | int source_port, int level) | |
1165 | { | |
1166 | struct bfin_sic *sic = hw_data (me); | |
1167 | bu32 idx = my_port / 100; | |
1168 | bu32 bit = (1 << (my_port & 0x1f)); | |
1169 | ||
1170 | /* SIC only exists to forward interrupts from the system to the CEC. */ | |
1171 | switch (idx) | |
1172 | { | |
1173 | case 0: sic->bf561.isr0 |= bit; break; | |
1174 | case 1: sic->bf561.isr1 |= bit; break; | |
1175 | } | |
1176 | ||
1177 | /* XXX: Handle SIC wakeup source ? | |
1178 | if (sic->bf561.iwr0 & bit) | |
1179 | What to do ?; | |
1180 | if (sic->bf561.iwr1 & bit) | |
1181 | What to do ?; | |
1182 | */ | |
1183 | ||
1184 | bfin_sic_561_forward_interrupts (me, sic); | |
1185 | } | |
1186 | ||
990d19fd MF |
1187 | static const struct hw_port_descriptor bfin_sic_59x_ports[] = |
1188 | { | |
ef016f83 MF |
1189 | BFIN_SIC_TO_CEC_PORTS |
1190 | { "pll", 0, 0, input_port, }, | |
1191 | { "dma_stat", 1, 0, input_port, }, | |
1192 | { "ppi@0", 2, 0, input_port, }, | |
1193 | { "sport@0_stat", 3, 0, input_port, }, | |
1194 | { "sport@1_stat", 4, 0, input_port, }, | |
1195 | { "spi@0", 5, 0, input_port, }, | |
1196 | { "spi@1", 6, 0, input_port, }, | |
1197 | { "uart@0_stat", 7, 0, input_port, }, | |
1198 | { "dma@0", 8, 0, input_port, }, | |
1199 | { "dma@1", 9, 0, input_port, }, | |
1200 | { "dma@2", 10, 0, input_port, }, | |
1201 | { "dma@3", 11, 0, input_port, }, | |
1202 | { "dma@4", 12, 0, input_port, }, | |
1203 | { "dma@5", 13, 0, input_port, }, | |
1204 | { "dma@6", 14, 0, input_port, }, | |
1205 | { "dma@7", 15, 0, input_port, }, | |
1206 | { "dma@8", 16, 0, input_port, }, | |
1207 | { "portf_irq_a", 17, 0, input_port, }, | |
1208 | { "portf_irq_b", 18, 0, input_port, }, | |
1209 | { "gptimer@0", 19, 0, input_port, }, | |
1210 | { "gptimer@1", 20, 0, input_port, }, | |
1211 | { "gptimer@2", 21, 0, input_port, }, | |
1212 | { "portg_irq_a", 22, 0, input_port, }, | |
1213 | { "portg_irq_b", 23, 0, input_port, }, | |
1214 | { "twi@0", 24, 0, input_port, }, | |
1215 | /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */ | |
1216 | { "dma@9", 25, 0, input_port, }, | |
1217 | { "dma@10", 26, 0, input_port, }, | |
1218 | { "dma@11", 27, 0, input_port, }, | |
1219 | { "dma@12", 28, 0, input_port, }, | |
1220 | /*{ "reserved", 25, 0, input_port, },*/ | |
1221 | /*{ "reserved", 26, 0, input_port, },*/ | |
1222 | /*{ "reserved", 27, 0, input_port, },*/ | |
1223 | /*{ "reserved", 28, 0, input_port, },*/ | |
1224 | { "mdma@0", 29, 0, input_port, }, | |
1225 | { "mdma@1", 30, 0, input_port, }, | |
1226 | { "wdog", 31, 0, input_port, }, | |
1227 | { NULL, 0, 0, 0, }, | |
1228 | }; | |
1229 | ||
1230 | static void | |
1231 | attach_bfin_sic_regs (struct hw *me, struct bfin_sic *sic) | |
1232 | { | |
1233 | address_word attach_address; | |
1234 | int attach_space; | |
1235 | unsigned attach_size; | |
1236 | reg_property_spec reg; | |
1237 | ||
1238 | if (hw_find_property (me, "reg") == NULL) | |
1239 | hw_abort (me, "Missing \"reg\" property"); | |
1240 | ||
1241 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
1242 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
1243 | ||
1244 | hw_unit_address_to_attach_address (hw_parent (me), | |
1245 | ®.address, | |
1246 | &attach_space, &attach_address, me); | |
1247 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
1248 | ||
1249 | if (attach_size != BFIN_MMR_SIC_SIZE) | |
1250 | hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SIC_SIZE); | |
1251 | ||
1252 | hw_attach_address (hw_parent (me), | |
1253 | 0, attach_space, attach_address, attach_size, me); | |
1254 | ||
1255 | sic->base = attach_address; | |
1256 | } | |
1257 | ||
1258 | static void | |
1259 | bfin_sic_finish (struct hw *me) | |
1260 | { | |
1261 | struct bfin_sic *sic; | |
1262 | ||
1263 | sic = HW_ZALLOC (me, struct bfin_sic); | |
1264 | ||
1265 | set_hw_data (me, sic); | |
1266 | attach_bfin_sic_regs (me, sic); | |
1267 | ||
1268 | switch (hw_find_integer_property (me, "type")) | |
1269 | { | |
1270 | case 500 ... 509: | |
1271 | set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); | |
1272 | set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); | |
1273 | set_hw_ports (me, bfin_sic_50x_ports); | |
1274 | set_hw_port_event (me, bfin_sic_52x_port_event); | |
1275 | mmr_names = bf52x_mmr_names; | |
1276 | ||
1277 | /* Initialize the SIC. */ | |
1278 | sic->bf52x.imask0 = sic->bf52x.imask1 = 0; | |
1279 | sic->bf52x.isr0 = sic->bf52x.isr1 = 0; | |
1280 | sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; | |
1281 | sic->bf52x.iar0 = 0x00000000; | |
1282 | sic->bf52x.iar1 = 0x22111000; | |
1283 | sic->bf52x.iar2 = 0x33332222; | |
1284 | sic->bf52x.iar3 = 0x44444433; | |
1285 | sic->bf52x.iar4 = 0x55555555; | |
1286 | sic->bf52x.iar5 = 0x06666655; | |
1287 | sic->bf52x.iar6 = 0x33333003; | |
1288 | sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ | |
1289 | break; | |
1290 | case 510 ... 519: | |
1291 | set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); | |
1292 | set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); | |
1293 | set_hw_ports (me, bfin_sic_51x_ports); | |
1294 | set_hw_port_event (me, bfin_sic_52x_port_event); | |
1295 | mmr_names = bf52x_mmr_names; | |
1296 | ||
1297 | /* Initialize the SIC. */ | |
1298 | sic->bf52x.imask0 = sic->bf52x.imask1 = 0; | |
1299 | sic->bf52x.isr0 = sic->bf52x.isr1 = 0; | |
1300 | sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; | |
1301 | sic->bf52x.iar0 = 0x00000000; | |
1302 | sic->bf52x.iar1 = 0x11000000; | |
1303 | sic->bf52x.iar2 = 0x33332222; | |
1304 | sic->bf52x.iar3 = 0x44444433; | |
1305 | sic->bf52x.iar4 = 0x55555555; | |
1306 | sic->bf52x.iar5 = 0x06666655; | |
1307 | sic->bf52x.iar6 = 0x33333000; | |
1308 | sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ | |
1309 | break; | |
1310 | case 522 ... 527: | |
1311 | set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); | |
1312 | set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); | |
1313 | set_hw_ports (me, bfin_sic_52x_ports); | |
1314 | set_hw_port_event (me, bfin_sic_52x_port_event); | |
1315 | mmr_names = bf52x_mmr_names; | |
1316 | ||
1317 | /* Initialize the SIC. */ | |
1318 | sic->bf52x.imask0 = sic->bf52x.imask1 = 0; | |
1319 | sic->bf52x.isr0 = sic->bf52x.isr1 = 0; | |
1320 | sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; | |
1321 | sic->bf52x.iar0 = 0x00000000; | |
1322 | sic->bf52x.iar1 = 0x11000000; | |
1323 | sic->bf52x.iar2 = 0x33332222; | |
1324 | sic->bf52x.iar3 = 0x44444433; | |
1325 | sic->bf52x.iar4 = 0x55555555; | |
1326 | sic->bf52x.iar5 = 0x06666655; | |
1327 | sic->bf52x.iar6 = 0x33333000; | |
1328 | sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ | |
1329 | break; | |
1330 | case 531 ... 533: | |
1331 | set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer); | |
1332 | set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer); | |
1333 | set_hw_ports (me, bfin_sic_533_ports); | |
1334 | set_hw_port_event (me, bfin_sic_533_port_event); | |
1335 | mmr_names = bf537_mmr_names; | |
1336 | ||
1337 | /* Initialize the SIC. */ | |
1338 | sic->bf537.imask = 0; | |
1339 | sic->bf537.isr = 0; | |
1340 | sic->bf537.iwr = 0xFFFFFFFF; | |
1341 | sic->bf537.iar0 = 0x10000000; | |
1342 | sic->bf537.iar1 = 0x33322221; | |
1343 | sic->bf537.iar2 = 0x66655444; | |
1344 | sic->bf537.iar3 = 0; /* XXX: fix this */ | |
1345 | break; | |
1346 | case 534: | |
1347 | case 536: | |
1348 | case 537: | |
1349 | set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer); | |
1350 | set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer); | |
1351 | set_hw_ports (me, bfin_sic_537_ports); | |
1352 | set_hw_port_event (me, bfin_sic_537_port_event); | |
1353 | mmr_names = bf537_mmr_names; | |
1354 | ||
1355 | /* Initialize the SIC. */ | |
1356 | sic->bf537.imask = 0; | |
1357 | sic->bf537.isr = 0; | |
1358 | sic->bf537.iwr = 0xFFFFFFFF; | |
1359 | sic->bf537.iar0 = 0x22211000; | |
1360 | sic->bf537.iar1 = 0x43333332; | |
1361 | sic->bf537.iar2 = 0x55555444; | |
1362 | sic->bf537.iar3 = 0x66655555; | |
1363 | break; | |
1364 | case 538 ... 539: | |
1365 | set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); | |
1366 | set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); | |
1367 | set_hw_ports (me, bfin_sic_538_ports); | |
1368 | set_hw_port_event (me, bfin_sic_52x_port_event); | |
1369 | mmr_names = bf52x_mmr_names; | |
1370 | ||
1371 | /* Initialize the SIC. */ | |
1372 | sic->bf52x.imask0 = sic->bf52x.imask1 = 0; | |
1373 | sic->bf52x.isr0 = sic->bf52x.isr1 = 0; | |
1374 | sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; | |
1375 | sic->bf52x.iar0 = 0x10000000; | |
1376 | sic->bf52x.iar1 = 0x33322221; | |
1377 | sic->bf52x.iar2 = 0x66655444; | |
1378 | sic->bf52x.iar3 = 0x00000000; | |
1379 | sic->bf52x.iar4 = 0x32222220; | |
1380 | sic->bf52x.iar5 = 0x44433333; | |
1381 | sic->bf52x.iar6 = 0x00444664; | |
1382 | sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ | |
1383 | break; | |
1384 | case 540 ... 549: | |
1385 | set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer); | |
1386 | set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer); | |
1387 | set_hw_ports (me, bfin_sic_54x_ports); | |
1388 | set_hw_port_event (me, bfin_sic_54x_port_event); | |
1389 | mmr_names = bf54x_mmr_names; | |
1390 | ||
1391 | /* Initialize the SIC. */ | |
1392 | sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0; | |
1393 | sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0; | |
1394 | sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr1 = 0xFFFFFFFF; | |
1395 | sic->bf54x.iar0 = 0x10000000; | |
1396 | sic->bf54x.iar1 = 0x33322221; | |
1397 | sic->bf54x.iar2 = 0x66655444; | |
1398 | sic->bf54x.iar3 = 0x00000000; | |
1399 | sic->bf54x.iar4 = 0x32222220; | |
1400 | sic->bf54x.iar5 = 0x44433333; | |
1401 | sic->bf54x.iar6 = 0x00444664; | |
1402 | sic->bf54x.iar7 = 0x00000000; | |
1403 | sic->bf54x.iar8 = 0x44111111; | |
1404 | sic->bf54x.iar9 = 0x44444444; | |
1405 | sic->bf54x.iar10 = 0x44444444; | |
1406 | sic->bf54x.iar11 = 0x55444444; | |
1407 | break; | |
1408 | case 561: | |
1409 | set_hw_io_read_buffer (me, bfin_sic_561_io_read_buffer); | |
1410 | set_hw_io_write_buffer (me, bfin_sic_561_io_write_buffer); | |
1411 | set_hw_ports (me, bfin_sic_561_ports); | |
1412 | set_hw_port_event (me, bfin_sic_561_port_event); | |
1413 | mmr_names = bf561_mmr_names; | |
1414 | ||
1415 | /* Initialize the SIC. */ | |
1416 | sic->bf561.imask0 = sic->bf561.imask1 = 0; | |
1417 | sic->bf561.isr0 = sic->bf561.isr1 = 0; | |
1418 | sic->bf561.iwr0 = sic->bf561.iwr1 = 0xFFFFFFFF; | |
1419 | sic->bf561.iar0 = 0x00000000; | |
1420 | sic->bf561.iar1 = 0x11111000; | |
1421 | sic->bf561.iar2 = 0x21111111; | |
1422 | sic->bf561.iar3 = 0x22222222; | |
1423 | sic->bf561.iar4 = 0x33333222; | |
1424 | sic->bf561.iar5 = 0x43333333; | |
1425 | sic->bf561.iar6 = 0x21144444; | |
1426 | sic->bf561.iar7 = 0x00006552; | |
1427 | break; | |
1428 | case 590 ... 599: | |
1429 | set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer); | |
1430 | set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer); | |
1431 | set_hw_ports (me, bfin_sic_59x_ports); | |
1432 | set_hw_port_event (me, bfin_sic_533_port_event); | |
1433 | mmr_names = bf537_mmr_names; | |
1434 | ||
1435 | /* Initialize the SIC. */ | |
1436 | sic->bf537.imask = 0; | |
1437 | sic->bf537.isr = 0; | |
1438 | sic->bf537.iwr = 0xFFFFFFFF; | |
1439 | sic->bf537.iar0 = 0x00000000; | |
1440 | sic->bf537.iar1 = 0x33322221; | |
1441 | sic->bf537.iar2 = 0x55444443; | |
1442 | sic->bf537.iar3 = 0x66600005; | |
1443 | break; | |
1444 | default: | |
1445 | hw_abort (me, "no support for SIC on this Blackfin model yet"); | |
1446 | } | |
1447 | } | |
1448 | ||
81d126c3 MF |
1449 | const struct hw_descriptor dv_bfin_sic_descriptor[] = |
1450 | { | |
ef016f83 MF |
1451 | {"bfin_sic", bfin_sic_finish,}, |
1452 | {NULL, NULL}, | |
1453 | }; |