[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_trace.c

/* Blackfin Trace (TBUF) model.

   Copyright (C) 2010-2020 Free Software Foundation, Inc.
   Contributed by Analog Devices, Inc.

   This file is part of simulators.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "sim-main.h"
#include "devices.h"
#include "dv-bfin_cec.h"
#include "dv-bfin_trace.h"

/* Note: The circular buffering here might look a little buggy wrt mid-reads
         and consuming the top entry, but this is simulating hardware behavior.
         The hardware is simple, dumb, and fast.  Don't write dumb Blackfin
         software and you won't have a problem.  */

/* The hardware is limited to 16 entries and defines TBUFCTL.  Let's extend it ;).  */
#ifndef SIM_BFIN_TRACE_DEPTH
#define SIM_BFIN_TRACE_DEPTH 6
#endif
#define SIM_BFIN_TRACE_LEN (1 << SIM_BFIN_TRACE_DEPTH)
#define SIM_BFIN_TRACE_LEN_MASK (SIM_BFIN_TRACE_LEN - 1)

struct bfin_trace_entry
{
  bu32 src, dst;
};
struct bfin_trace
{
  bu32 base;
  struct bfin_trace_entry buffer[SIM_BFIN_TRACE_LEN];
  int top, bottom;
  bool mid;

  /* Order after here is important -- matches hardware MMR layout.  */
  bu32 tbufctl, tbufstat;
  char _pad[0x100 - 0x8];
  bu32 tbuf;
};
#define mmr_base()      offsetof(struct bfin_trace, tbufctl)
#define mmr_offset(mmr) (offsetof(struct bfin_trace, mmr) - mmr_base())

static const char * const mmr_names[] =
{
  "TBUFCTL", "TBUFSTAT", [mmr_offset (tbuf) / 4] = "TBUF",
};
#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")

/* Ugh, circular buffers.  */
#define TBUF_LEN(t) ((t)->top - (t)->bottom)
#define TBUF_IDX(i) ((i) & SIM_BFIN_TRACE_LEN_MASK)
/* TOP is the next slot to fill.  */
#define TBUF_TOP(t) (&(t)->buffer[TBUF_IDX ((t)->top)])
/* LAST is the latest valid slot.  */
#define TBUF_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 1)])
/* LAST_LAST is the second-to-last valid slot.  */
#define TBUF_LAST_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 2)])

static unsigned
bfin_trace_io_write_buffer (struct hw *me, const void *source,
			    int space, address_word addr, unsigned nr_bytes)
{
  struct bfin_trace *trace = hw_data (me);
  bu32 mmr_off;
  bu32 value;

  /* Invalid access mode is higher priority than missing register.  */
  if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
    return 0;

  value = dv_load_4 (source);
  mmr_off = addr - trace->base;

  HW_TRACE_WRITE ();

  switch (mmr_off)
    {
    case mmr_offset(tbufctl):
      trace->tbufctl = value;
      break;
    case mmr_offset(tbufstat):
    case mmr_offset(tbuf):
      /* Discard writes to these.  */
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
      return 0;
    }

  return nr_bytes;
}

static unsigned
bfin_trace_io_read_buffer (struct hw *me, void *dest,
			   int space, address_word addr, unsigned nr_bytes)
{
  struct bfin_trace *trace = hw_data (me);
  bu32 mmr_off;
  bu32 value;

  /* Invalid access mode is higher priority than missing register.  */
  if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
    return 0;

  mmr_off = addr - trace->base;

  HW_TRACE_READ ();

  switch (mmr_off)
    {
    case mmr_offset(tbufctl):
      value = trace->tbufctl;
      break;
    case mmr_offset(tbufstat):
      /* Hardware is limited to 16 entries, so to stay compatible with
         software, limit the value to 16.  For software algorithms that
         keep reading while (TBUFSTAT != 0), they'll get all of it.  */
      value = min (TBUF_LEN (trace), 16);
      break;
    case mmr_offset(tbuf):
      {
	struct bfin_trace_entry *e;

	if (TBUF_LEN (trace) == 0)
	  {
	    value = 0;
	    break;
	  }

	e = TBUF_LAST (trace);
	if (trace->mid)
	  {
	    value = e->src;
	    --trace->top;
	  }
	else
	  value = e->dst;
	trace->mid = !trace->mid;

	break;
      }
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
      return 0;
    }

  dv_store_4 (dest, value);

  return nr_bytes;
}

static void
attach_bfin_trace_regs (struct hw *me, struct bfin_trace *trace)
{
  address_word attach_address;
  int attach_space;
  unsigned attach_size;
  reg_property_spec reg;

  if (hw_find_property (me, "reg") == NULL)
    hw_abort (me, "Missing \"reg\" property");

  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
    hw_abort (me, "\"reg\" property must contain three addr/size entries");

  hw_unit_address_to_attach_address (hw_parent (me),
				     &reg.address,
				     &attach_space, &attach_address, me);
  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);

  if (attach_size != BFIN_COREMMR_TRACE_SIZE)
    hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_TRACE_SIZE);

  hw_attach_address (hw_parent (me),
		     0, attach_space, attach_address, attach_size, me);

  trace->base = attach_address;
}

static void
bfin_trace_finish (struct hw *me)
{
  struct bfin_trace *trace;

  trace = HW_ZALLOC (me, struct bfin_trace);

  set_hw_data (me, trace);
  set_hw_io_read_buffer (me, bfin_trace_io_read_buffer);
  set_hw_io_write_buffer (me, bfin_trace_io_write_buffer);

  attach_bfin_trace_regs (me, trace);
}

const struct hw_descriptor dv_bfin_trace_descriptor[] =
{
  {"bfin_trace", bfin_trace_finish,},
  {NULL, NULL},
};

#define TRACE_STATE(cpu) DV_STATE_CACHED (cpu, trace)

/* This is not re-entrant, but neither is the cpu state, so this shouldn't
   be a big deal ...  */
void bfin_trace_queue (SIM_CPU *cpu, bu32 src_pc, bu32 dst_pc, int hwloop)
{
  struct bfin_trace *trace = TRACE_STATE (cpu);
  struct bfin_trace_entry *e;
  int len, ivg;

  /* Only queue if powered.  */
  if (!(trace->tbufctl & TBUFPWR))
    return;

  /* Only queue if enabled.  */
  if (!(trace->tbufctl & TBUFEN))
    return;

  /* Ignore hardware loops.
     XXX: This is what the hardware does, but an option to ignore
     could be useful for debugging ...  */
  if (hwloop >= 0)
    return;

  /* Only queue if at right level.  */
  ivg = cec_get_ivg (cpu);
  if (ivg == IVG_RST)
    /* XXX: This is what the hardware does, but an option to ignore
            could be useful for debugging ...  */
    return;
  if (ivg <= IVG_EVX && (trace->tbufctl & TBUFOVF))
    /* XXX: This is what the hardware does, but an option to ignore
            could be useful for debugging ... just don't throw an
            exception when full and in EVT{0..3}.  */
    return;

  /* Are we full ?  */
  len = TBUF_LEN (trace);
  if (len == SIM_BFIN_TRACE_LEN)
    {
      if (trace->tbufctl & TBUFOVF)
	{
	  cec_exception (cpu, VEC_OVFLOW);
	  return;
	}

      /* Overwrite next entry.  */
      ++trace->bottom;
    }

  /* One level compression.  */
  if (len >= 1 && (trace->tbufctl & TBUFCMPLP))
    {
      e = TBUF_LAST (trace);
      if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1))
	{
	  /* Hardware sets LSB when level is compressed.  */
	  e->dst |= 1;
	  return;
	}
    }

  /* Two level compression.  */
  if (len >= 2 && (trace->tbufctl & TBUFCMPLP_DOUBLE))
    {
      e = TBUF_LAST_LAST (trace);
      if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1))
	{
	  /* Hardware sets LSB when level is compressed.  */
	  e->src |= 1;
	  return;
	}
    }

  e = TBUF_TOP (trace);
  e->dst = dst_pc;
  e->src = src_pc;
  ++trace->top;
}
Commit	Line	Data
ef016f83 MF	1	/* Blackfin Trace (TBUF) model.
ef016f83 MF	2
b811d2c2	3	Copyright (C) 2010-2020 Free Software Foundation, Inc.
ef016f83 MF	4	Contributed by Analog Devices, Inc.
	5
	6	This file is part of simulators.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
	21	#include "config.h"
	22
	23	#include "sim-main.h"
	24	#include "devices.h"
	25	#include "dv-bfin_cec.h"
	26	#include "dv-bfin_trace.h"
	27
	28	/* Note: The circular buffering here might look a little buggy wrt mid-reads
	29	and consuming the top entry, but this is simulating hardware behavior.
	30	The hardware is simple, dumb, and fast. Don't write dumb Blackfin
	31	software and you won't have a problem. */
	32
	33	/* The hardware is limited to 16 entries and defines TBUFCTL. Let's extend it ;). */
	34	#ifndef SIM_BFIN_TRACE_DEPTH
	35	#define SIM_BFIN_TRACE_DEPTH 6
	36	#endif
	37	#define SIM_BFIN_TRACE_LEN (1 << SIM_BFIN_TRACE_DEPTH)
	38	#define SIM_BFIN_TRACE_LEN_MASK (SIM_BFIN_TRACE_LEN - 1)
	39
	40	struct bfin_trace_entry
	41	{
	42	bu32 src, dst;
	43	};
	44	struct bfin_trace
	45	{
	46	bu32 base;
	47	struct bfin_trace_entry buffer[SIM_BFIN_TRACE_LEN];
	48	int top, bottom;
	49	bool mid;
	50
	51	/* Order after here is important -- matches hardware MMR layout. */
	52	bu32 tbufctl, tbufstat;
	53	char _pad[0x100 - 0x8];
	54	bu32 tbuf;
	55	};
	56	#define mmr_base() offsetof(struct bfin_trace, tbufctl)
	57	#define mmr_offset(mmr) (offsetof(struct bfin_trace, mmr) - mmr_base())
	58
990d19fd MF	59	static const char * const mmr_names[] =
990d19fd MF	60	{
ef016f83 MF	61	"TBUFCTL", "TBUFSTAT", [mmr_offset (tbuf) / 4] = "TBUF",
	62	};
	63	#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
	64
	65	/* Ugh, circular buffers. */
	66	#define TBUF_LEN(t) ((t)->top - (t)->bottom)
	67	#define TBUF_IDX(i) ((i) & SIM_BFIN_TRACE_LEN_MASK)
	68	/* TOP is the next slot to fill. */
	69	#define TBUF_TOP(t) (&(t)->buffer[TBUF_IDX ((t)->top)])
	70	/* LAST is the latest valid slot. */
	71	#define TBUF_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 1)])
	72	/* LAST_LAST is the second-to-last valid slot. */
	73	#define TBUF_LAST_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 2)])
	74
	75	static unsigned
	76	bfin_trace_io_write_buffer (struct hw me, const void source,
	77	int space, address_word addr, unsigned nr_bytes)
	78	{
	79	struct bfin_trace *trace = hw_data (me);
	80	bu32 mmr_off;
	81	bu32 value;
	82
466b619e MF	83	/* Invalid access mode is higher priority than missing register. */
	84	if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
	85	return 0;
	86
ef016f83 MF	87	value = dv_load_4 (source);
	88	mmr_off = addr - trace->base;
	89
	90	HW_TRACE_WRITE ();
	91
	92	switch (mmr_off)
	93	{
	94	case mmr_offset(tbufctl):
	95	trace->tbufctl = value;
	96	break;
	97	case mmr_offset(tbufstat):
	98	case mmr_offset(tbuf):
	99	/* Discard writes to these. */
	100	break;
	101	default:
	102	dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
466b619e	103	return 0;
ef016f83 MF	104	}
	105
	106	return nr_bytes;
	107	}
	108
	109	static unsigned
	110	bfin_trace_io_read_buffer (struct hw me, void dest,
	111	int space, address_word addr, unsigned nr_bytes)
	112	{
	113	struct bfin_trace *trace = hw_data (me);
	114	bu32 mmr_off;
	115	bu32 value;
	116
466b619e MF	117	/* Invalid access mode is higher priority than missing register. */
	118	if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
	119	return 0;
	120
ef016f83 MF	121	mmr_off = addr - trace->base;
	122
	123	HW_TRACE_READ ();
	124
	125	switch (mmr_off)
	126	{
	127	case mmr_offset(tbufctl):
	128	value = trace->tbufctl;
	129	break;
	130	case mmr_offset(tbufstat):
	131	/* Hardware is limited to 16 entries, so to stay compatible with
	132	software, limit the value to 16. For software algorithms that
	133	keep reading while (TBUFSTAT != 0), they'll get all of it. */
bc273e17	134	value = min (TBUF_LEN (trace), 16);
ef016f83 MF	135	break;
	136	case mmr_offset(tbuf):
	137	{
	138	struct bfin_trace_entry *e;
	139
	140	if (TBUF_LEN (trace) == 0)
	141	{
	142	value = 0;
	143	break;
	144	}
	145
	146	e = TBUF_LAST (trace);
	147	if (trace->mid)
	148	{
	149	value = e->src;
	150	--trace->top;
	151	}
	152	else
	153	value = e->dst;
	154	trace->mid = !trace->mid;
	155
	156	break;
	157	}
	158	default:
466b619e MF	159	dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
466b619e MF	160	return 0;
ef016f83 MF	161	}
	162
	163	dv_store_4 (dest, value);
	164
	165	return nr_bytes;
	166	}
	167
	168	static void
	169	attach_bfin_trace_regs (struct hw me, struct bfin_trace trace)
	170	{
	171	address_word attach_address;
	172	int attach_space;
	173	unsigned attach_size;
	174	reg_property_spec reg;
	175
	176	if (hw_find_property (me, "reg") == NULL)
	177	hw_abort (me, "Missing \"reg\" property");
	178
	179	if (!hw_find_reg_array_property (me, "reg", 0, &reg))
	180	hw_abort (me, "\"reg\" property must contain three addr/size entries");
	181
	182	hw_unit_address_to_attach_address (hw_parent (me),
	183	&reg.address,
	184	&attach_space, &attach_address, me);
	185	hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
	186
	187	if (attach_size != BFIN_COREMMR_TRACE_SIZE)
	188	hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_TRACE_SIZE);
	189
	190	hw_attach_address (hw_parent (me),
	191	0, attach_space, attach_address, attach_size, me);
	192
	193	trace->base = attach_address;
	194	}
	195
	196	static void
	197	bfin_trace_finish (struct hw *me)
	198	{
	199	struct bfin_trace *trace;
	200
	201	trace = HW_ZALLOC (me, struct bfin_trace);
	202
	203	set_hw_data (me, trace);
	204	set_hw_io_read_buffer (me, bfin_trace_io_read_buffer);
	205	set_hw_io_write_buffer (me, bfin_trace_io_write_buffer);
	206
	207	attach_bfin_trace_regs (me, trace);
	208	}
	209
81d126c3 MF	210	const struct hw_descriptor dv_bfin_trace_descriptor[] =
81d126c3 MF	211	{
ef016f83 MF	212	{"bfin_trace", bfin_trace_finish,},
	213	{NULL, NULL},
	214	};
	215
	216	#define TRACE_STATE(cpu) DV_STATE_CACHED (cpu, trace)
	217
	218	/* This is not re-entrant, but neither is the cpu state, so this shouldn't
	219	be a big deal ... */
	220	void bfin_trace_queue (SIM_CPU *cpu, bu32 src_pc, bu32 dst_pc, int hwloop)
	221	{
	222	struct bfin_trace *trace = TRACE_STATE (cpu);
	223	struct bfin_trace_entry *e;
	224	int len, ivg;
	225
	226	/* Only queue if powered. */
	227	if (!(trace->tbufctl & TBUFPWR))
	228	return;
	229
	230	/* Only queue if enabled. */
	231	if (!(trace->tbufctl & TBUFEN))
	232	return;
	233
	234	/* Ignore hardware loops.
	235	XXX: This is what the hardware does, but an option to ignore
	236	could be useful for debugging ... */
	237	if (hwloop >= 0)
	238	return;
	239
	240	/* Only queue if at right level. */
	241	ivg = cec_get_ivg (cpu);
	242	if (ivg == IVG_RST)
	243	/* XXX: This is what the hardware does, but an option to ignore
	244	could be useful for debugging ... */
	245	return;
	246	if (ivg <= IVG_EVX && (trace->tbufctl & TBUFOVF))
	247	/* XXX: This is what the hardware does, but an option to ignore
	248	could be useful for debugging ... just don't throw an
	249	exception when full and in EVT{0..3}. */
	250	return;
	251
	252	/* Are we full ? */
	253	len = TBUF_LEN (trace);
	254	if (len == SIM_BFIN_TRACE_LEN)
	255	{
	256	if (trace->tbufctl & TBUFOVF)
	257	{
	258	cec_exception (cpu, VEC_OVFLOW);
	259	return;
	260	}
	261
	262	/* Overwrite next entry. */
	263	++trace->bottom;
	264	}
	265
	266	/* One level compression. */
	267	if (len >= 1 && (trace->tbufctl & TBUFCMPLP))
	268	{
	269	e = TBUF_LAST (trace);
	270	if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1))
	271	{
	272	/* Hardware sets LSB when level is compressed. */
	273	e->dst \|= 1;
	274	return;
	275	}
276	}
277
278	/* Two level compression. */
279	if (len >= 2 && (trace->tbufctl & TBUFCMPLP_DOUBLE))
280	{
281	e = TBUF_LAST_LAST (trace);
282	if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1))
283	{
284	/* Hardware sets LSB when level is compressed. */
285	e->src \|= 1;
286	return;
287	}
288	}
289
290	e = TBUF_TOP (trace);
291	e->dst = dst_pc;
292	e->src = src_pc;
293	++trace->top;
294	}