sim: trace: add a basic cpu register class
[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_uart.c
CommitLineData
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1/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
2 For "old style" UARTs on BF53x/etc... parts.
3
32d0add0 4 Copyright (C) 2010-2015 Free Software Foundation, Inc.
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5 Contributed by Analog Devices, Inc.
6
7 This file is part of simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "config.h"
23
24#include "sim-main.h"
25#include "dv-sockser.h"
26#include "devices.h"
27#include "dv-bfin_uart.h"
28
29/* XXX: Should we bother emulating the TX/RX FIFOs ? */
30
31/* Internal state needs to be the same as bfin_uart2. */
32struct bfin_uart
33{
34 /* This top portion matches common dv_bfin struct. */
35 bu32 base;
36 struct hw *dma_master;
37 bool acked;
38
39 struct hw_event *handler;
40 char saved_byte;
41 int saved_count;
42
43 /* This is aliased to DLH. */
44 bu16 ier;
45 /* These are aliased to DLL. */
46 bu16 thr, rbr;
47
48 /* Order after here is important -- matches hardware MMR layout. */
49 bu16 BFIN_MMR_16(dll);
50 bu16 BFIN_MMR_16(dlh);
51 bu16 BFIN_MMR_16(iir);
52 bu16 BFIN_MMR_16(lcr);
53 bu16 BFIN_MMR_16(mcr);
54 bu16 BFIN_MMR_16(lsr);
55 bu16 BFIN_MMR_16(msr);
56 bu16 BFIN_MMR_16(scr);
57 bu16 _pad0[2];
58 bu16 BFIN_MMR_16(gctl);
59};
60#define mmr_base() offsetof(struct bfin_uart, dll)
61#define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base())
62
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63static const char * const mmr_names[] =
64{
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65 "UART_RBR/UART_THR", "UART_IER", "UART_IIR", "UART_LCR", "UART_MCR",
66 "UART_LSR", "UART_MSR", "UART_SCR", "<INV>", "UART_GCTL",
67};
68static const char *mmr_name (struct bfin_uart *uart, bu32 idx)
69{
70 if (uart->lcr & DLAB)
71 if (idx < 2)
72 return idx == 0 ? "UART_DLL" : "UART_DLH";
73 return mmr_names[idx];
74}
75#define mmr_name(off) mmr_name (uart, (off) / 4)
76
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77static void
78bfin_uart_poll (struct hw *me, void *data)
79{
80 struct bfin_uart *uart = data;
81 bu16 lsr;
82
83 uart->handler = NULL;
84
85 lsr = bfin_uart_get_status (me);
86 if (lsr & DR)
87 hw_port_event (me, DV_PORT_RX, 1);
88
89 bfin_uart_reschedule (me);
90}
91
92void
93bfin_uart_reschedule (struct hw *me)
94{
95 struct bfin_uart *uart = hw_data (me);
96
97 if (uart->ier & ERBFI)
98 {
99 if (!uart->handler)
100 uart->handler = hw_event_queue_schedule (me, 10000,
101 bfin_uart_poll, uart);
102 }
103 else
104 {
105 if (uart->handler)
106 {
107 hw_event_queue_deschedule (me, uart->handler);
108 uart->handler = NULL;
109 }
110 }
111}
112
113bu16
28fe96b7 114bfin_uart_write_byte (struct hw *me, bu16 thr, bu16 mcr)
ef016f83 115{
28fe96b7 116 struct bfin_uart *uart = hw_data (me);
ef016f83 117 unsigned char ch = thr;
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118
119 if (mcr & LOOP_ENA)
120 {
121 /* XXX: This probably doesn't work exactly right with
122 external FIFOs ... */
123 uart->saved_byte = thr;
124 uart->saved_count = 1;
125 }
126
ef016f83 127 bfin_uart_write_buffer (me, &ch, 1);
28fe96b7 128
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129 return thr;
130}
131
132static unsigned
133bfin_uart_io_write_buffer (struct hw *me, const void *source,
134 int space, address_word addr, unsigned nr_bytes)
135{
136 struct bfin_uart *uart = hw_data (me);
137 bu32 mmr_off;
138 bu32 value;
139 bu16 *valuep;
140
141 value = dv_load_2 (source);
142 mmr_off = addr - uart->base;
143 valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
144
145 HW_TRACE_WRITE ();
146
147 dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
148
149 /* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
150 switch (mmr_off)
151 {
152 case mmr_offset(dll):
153 if (uart->lcr & DLAB)
154 uart->dll = value;
155 else
156 {
28fe96b7 157 uart->thr = bfin_uart_write_byte (me, value, uart->mcr);
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158
159 if (uart->ier & ETBEI)
160 hw_port_event (me, DV_PORT_TX, 1);
161 }
162 break;
163 case mmr_offset(dlh):
164 if (uart->lcr & DLAB)
165 uart->dlh = value;
166 else
167 {
168 uart->ier = value;
169 bfin_uart_reschedule (me);
170 }
171 break;
172 case mmr_offset(iir):
173 case mmr_offset(lsr):
174 /* XXX: Writes are ignored ? */
175 break;
176 case mmr_offset(lcr):
177 case mmr_offset(mcr):
178 case mmr_offset(scr):
179 case mmr_offset(gctl):
180 *valuep = value;
181 break;
182 default:
183 dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
184 break;
185 }
186
187 return nr_bytes;
188}
189
190/* Switch between socket and stdin on the fly. */
191bu16
28fe96b7 192bfin_uart_get_next_byte (struct hw *me, bu16 rbr, bu16 mcr, bool *fresh)
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193{
194 SIM_DESC sd = hw_system (me);
195 struct bfin_uart *uart = hw_data (me);
196 int status = dv_sockser_status (sd);
197 bool _fresh;
198
199 /* NB: The "uart" here may only use interal state. */
200
201 if (!fresh)
202 fresh = &_fresh;
203
204 *fresh = false;
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205
206 if (uart->saved_count > 0)
ef016f83 207 {
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208 *fresh = true;
209 rbr = uart->saved_byte;
210 --uart->saved_count;
211 }
212 else if (mcr & LOOP_ENA)
213 {
214 /* RX is disconnected, so only return local data. */
215 }
216 else if (status & DV_SOCKSER_DISCONNECTED)
217 {
218 char byte;
219 int ret = sim_io_poll_read (sd, 0/*STDIN*/, &byte, 1);
220
221 if (ret > 0)
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222 {
223 *fresh = true;
28fe96b7 224 rbr = byte;
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225 }
226 }
227 else
228 rbr = dv_sockser_read (sd);
229
230 return rbr;
231}
232
233bu16
234bfin_uart_get_status (struct hw *me)
235{
236 SIM_DESC sd = hw_system (me);
237 struct bfin_uart *uart = hw_data (me);
238 int status = dv_sockser_status (sd);
239 bu16 lsr = 0;
240
241 if (status & DV_SOCKSER_DISCONNECTED)
242 {
243 if (uart->saved_count <= 0)
244 uart->saved_count = sim_io_poll_read (sd, 0/*STDIN*/,
245 &uart->saved_byte, 1);
246 lsr |= TEMT | THRE | (uart->saved_count > 0 ? DR : 0);
247 }
248 else
249 lsr |= (status & DV_SOCKSER_INPUT_EMPTY ? 0 : DR) |
28fe96b7 250 (status & DV_SOCKSER_OUTPUT_EMPTY ? TEMT | THRE : 0);
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251
252 return lsr;
253}
254
255static unsigned
256bfin_uart_io_read_buffer (struct hw *me, void *dest,
257 int space, address_word addr, unsigned nr_bytes)
258{
259 struct bfin_uart *uart = hw_data (me);
260 bu32 mmr_off;
261 bu16 *valuep;
262
263 mmr_off = addr - uart->base;
264 valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
265
266 HW_TRACE_READ ();
267
268 dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
269
270 switch (mmr_off)
271 {
272 case mmr_offset(dll):
273 if (uart->lcr & DLAB)
274 dv_store_2 (dest, uart->dll);
275 else
276 {
28fe96b7 277 uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, uart->mcr, NULL);
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278 dv_store_2 (dest, uart->rbr);
279 }
280 break;
281 case mmr_offset(dlh):
282 if (uart->lcr & DLAB)
283 dv_store_2 (dest, uart->dlh);
284 else
285 dv_store_2 (dest, uart->ier);
286 break;
287 case mmr_offset(lsr):
288 /* XXX: Reads are destructive on most parts, but not all ... */
289 uart->lsr |= bfin_uart_get_status (me);
290 dv_store_2 (dest, *valuep);
291 uart->lsr = 0;
292 break;
293 case mmr_offset(iir):
294 /* XXX: Reads are destructive ... */
295 case mmr_offset(lcr):
296 case mmr_offset(mcr):
297 case mmr_offset(scr):
298 case mmr_offset(gctl):
299 dv_store_2 (dest, *valuep);
300 break;
301 default:
302 dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
303 break;
304 }
305
306 return nr_bytes;
307}
308
309unsigned
310bfin_uart_read_buffer (struct hw *me, unsigned char *buffer, unsigned nr_bytes)
311{
312 SIM_DESC sd = hw_system (me);
313 struct bfin_uart *uart = hw_data (me);
314 int status = dv_sockser_status (sd);
315 unsigned i = 0;
316
317 if (status & DV_SOCKSER_DISCONNECTED)
318 {
319 int ret;
320
321 while (uart->saved_count > 0 && i < nr_bytes)
322 {
323 buffer[i++] = uart->saved_byte;
324 --uart->saved_count;
325 }
326
327 ret = sim_io_poll_read (sd, 0/*STDIN*/, (char *) buffer, nr_bytes - i);
328 if (ret > 0)
329 i += ret;
330 }
331 else
332 buffer[i++] = dv_sockser_read (sd);
333
334 return i;
335}
336
337static unsigned
338bfin_uart_dma_read_buffer (struct hw *me, void *dest, int space,
339 unsigned_word addr, unsigned nr_bytes)
340{
341 HW_TRACE_DMA_READ ();
342 return bfin_uart_read_buffer (me, dest, nr_bytes);
343}
344
345unsigned
346bfin_uart_write_buffer (struct hw *me, const unsigned char *buffer,
347 unsigned nr_bytes)
348{
349 SIM_DESC sd = hw_system (me);
350 int status = dv_sockser_status (sd);
351
352 if (status & DV_SOCKSER_DISCONNECTED)
353 {
354 sim_io_write_stdout (sd, (const char *) buffer, nr_bytes);
355 sim_io_flush_stdout (sd);
356 }
357 else
358 {
359 /* Normalize errors to a value of 0. */
360 int ret = dv_sockser_write_buffer (sd, buffer, nr_bytes);
361 nr_bytes = CLAMP (ret, 0, nr_bytes);
362 }
363
364 return nr_bytes;
365}
366
367static unsigned
368bfin_uart_dma_write_buffer (struct hw *me, const void *source,
369 int space, unsigned_word addr,
370 unsigned nr_bytes,
371 int violate_read_only_section)
372{
373 struct bfin_uart *uart = hw_data (me);
374 unsigned ret;
375
376 HW_TRACE_DMA_WRITE ();
377
378 ret = bfin_uart_write_buffer (me, source, nr_bytes);
379
380 if (ret == nr_bytes && (uart->ier & ETBEI))
381 hw_port_event (me, DV_PORT_TX, 1);
382
383 return ret;
384}
385
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386static const struct hw_port_descriptor bfin_uart_ports[] =
387{
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388 { "tx", DV_PORT_TX, 0, output_port, },
389 { "rx", DV_PORT_RX, 0, output_port, },
390 { "stat", DV_PORT_STAT, 0, output_port, },
391 { NULL, 0, 0, 0, },
392};
393
394static void
395attach_bfin_uart_regs (struct hw *me, struct bfin_uart *uart)
396{
397 address_word attach_address;
398 int attach_space;
399 unsigned attach_size;
400 reg_property_spec reg;
401
402 if (hw_find_property (me, "reg") == NULL)
403 hw_abort (me, "Missing \"reg\" property");
404
405 if (!hw_find_reg_array_property (me, "reg", 0, &reg))
406 hw_abort (me, "\"reg\" property must contain three addr/size entries");
407
408 hw_unit_address_to_attach_address (hw_parent (me),
409 &reg.address,
410 &attach_space, &attach_address, me);
411 hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
412
413 if (attach_size != BFIN_MMR_UART_SIZE)
414 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_UART_SIZE);
415
416 hw_attach_address (hw_parent (me),
417 0, attach_space, attach_address, attach_size, me);
418
419 uart->base = attach_address;
420}
421
422static void
423bfin_uart_finish (struct hw *me)
424{
425 struct bfin_uart *uart;
426
427 uart = HW_ZALLOC (me, struct bfin_uart);
428
429 set_hw_data (me, uart);
430 set_hw_io_read_buffer (me, bfin_uart_io_read_buffer);
431 set_hw_io_write_buffer (me, bfin_uart_io_write_buffer);
432 set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer);
433 set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer);
434 set_hw_ports (me, bfin_uart_ports);
435
436 attach_bfin_uart_regs (me, uart);
437
438 /* Initialize the UART. */
439 uart->dll = 0x0001;
440 uart->iir = 0x0001;
441 uart->lsr = 0x0060;
442}
443
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444const struct hw_descriptor dv_bfin_uart_descriptor[] =
445{
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446 {"bfin_uart", bfin_uart_finish,},
447 {NULL, NULL},
448};
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