projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| ef016f83 MF |
1 | /* Simulator for Analog Devices Blackfin processors. |
| 2 | ||
| 88b9d363 | 3 | Copyright (C) 2005-2022 Free Software Foundation, Inc. |
| ef016f83 MF |
4 | Contributed by Analog Devices, Inc. |
| 5 | ||
| 6 | This file is part of simulators. | |
| 7 | ||
| 8 | This program is free software; you can redistribute it and/or modify | |
| 9 | it under the terms of the GNU General Public License as published by | |
| 10 | the Free Software Foundation; either version 3 of the License, or | |
| 11 | (at your option) any later version. | |
| 12 | ||
| 13 | This program is distributed in the hope that it will be useful, | |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | GNU General Public License for more details. | |
| 17 | ||
| 18 | You should have received a copy of the GNU General Public License | |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
| 20 | ||
| 21 | #ifndef _BFIN_MACHS_H_ | |
| 22 | #define _BFIN_MACHS_H_ | |
| 23 | ||
| ef016f83 MF |
24 | #define CPU_MODEL_NUM(cpu) MODEL_NUM (CPU_MODEL (cpu)) |
| 25 | ||
| 26 | /* XXX: Some of this probably belongs in CPU_MODEL. */ | |
| 27 | struct bfin_board_data { | |
| 28 | unsigned int sirev, sirev_valid; | |
| 29 | const char *hw_file; | |
| 30 | }; | |
| 31 | ||
| 32 | void bfin_model_cpu_init (SIM_DESC, SIM_CPU *); | |
| 33 | bu32 bfin_model_get_chipid (SIM_DESC); | |
| 34 | bu32 bfin_model_get_dspid (SIM_DESC); | |
| 1c636da0 | 35 | extern const SIM_MACH * const bfin_sim_machs[]; |
| ef016f83 | 36 | |
| f2db709f MF |
37 | #define BFIN_COREMMR_CEC_BASE 0xFFE02100 |
| 38 | #define BFIN_COREMMR_CEC_SIZE (4 * 5) | |
| 39 | #define BFIN_COREMMR_CTIMER_BASE 0xFFE03000 | |
| 40 | #define BFIN_COREMMR_CTIMER_SIZE (4 * 4) | |
| 41 | #define BFIN_COREMMR_EVT_BASE 0xFFE02000 | |
| 42 | #define BFIN_COREMMR_EVT_SIZE (4 * 16) | |
| 43 | #define BFIN_COREMMR_JTAG_BASE 0xFFE05000 | |
| 44 | #define BFIN_COREMMR_JTAG_SIZE (4 * 3) | |
| 45 | #define BFIN_COREMMR_MMU_BASE 0xFFE00000 | |
| 46 | #define BFIN_COREMMR_MMU_SIZE 0x2000 | |
| 47 | #define BFIN_COREMMR_PFMON_BASE 0xFFE08000 | |
| 48 | #define BFIN_COREMMR_PFMON_SIZE 0x108 | |
| 49 | #define BFIN_COREMMR_TRACE_BASE 0xFFE06000 | |
| 50 | #define BFIN_COREMMR_TRACE_SIZE (4 * 65) | |
| 51 | #define BFIN_COREMMR_WP_BASE 0xFFE07000 | |
| 52 | #define BFIN_COREMMR_WP_SIZE 0x204 | |
| 53 | ||
| 54 | #define BFIN_MMR_DMA_SIZE (4 * 16) | |
| 55 | #define BFIN_MMR_DMAC0_BASE 0xFFC00C00 | |
| 56 | #define BFIN_MMR_DMAC1_BASE 0xFFC01C00 | |
| 57 | #define BFIN_MMR_EBIU_AMC_SIZE (4 * 3) | |
| 58 | #define BF50X_MMR_EBIU_AMC_SIZE 0x28 | |
| 59 | #define BF54X_MMR_EBIU_AMC_SIZE (4 * 7) | |
| 60 | #define BFIN_MMR_EBIU_DDRC_SIZE 0xb0 | |
| 61 | #define BFIN_MMR_EBIU_SDC_SIZE (4 * 4) | |
| 62 | #define BFIN_MMR_EMAC_BASE 0xFFC03000 | |
| 63 | #define BFIN_MMR_EMAC_SIZE 0x200 | |
| 64 | #define BFIN_MMR_EPPI_SIZE 0x40 | |
| 65 | #define BFIN_MMR_GPIO_SIZE (17 * 4) | |
| 07c5891d | 66 | #define BFIN_MMR_GPIO2_SIZE (8 * 4) |
| f2db709f MF |
67 | #define BFIN_MMR_GPTIMER_SIZE (4 * 4) |
| 68 | #define BFIN_MMR_NFC_SIZE 0x50 | |
| 69 | /* XXX: Not exactly true; it's two sets of 4 regs near each other: | |
| 70 | 0xFFC03600 0x10 - Control | |
| 71 | 0xFFC03680 0x10 - Data */ | |
| 72 | #define BFIN_MMR_OTP_SIZE 0xa0 | |
| 050396e5 | 73 | #define BFIN_MMR_PINT_SIZE 0x28 |
| f2db709f MF |
74 | #define BFIN_MMR_PLL_BASE 0xFFC00000 |
| 75 | #define BFIN_MMR_PLL_SIZE (4 * 6) | |
| 76 | #define BFIN_MMR_PPI_SIZE (4 * 5) | |
| 77 | #define BFIN_MMR_RTC_SIZE (4 * 6) | |
| 78 | #define BFIN_MMR_SIC_BASE 0xFFC00100 | |
| 79 | #define BFIN_MMR_SIC_SIZE 0x100 | |
| 80 | #define BFIN_MMR_SPI_SIZE (4 * 7) | |
| 81 | #define BFIN_MMR_TWI_SIZE 0x90 | |
| 82 | #define BFIN_MMR_WDOG_SIZE (4 * 3) | |
| 83 | #define BFIN_MMR_UART_SIZE 0x30 | |
| 84 | #define BFIN_MMR_UART2_SIZE 0x30 | |
| 85 | ||
| ef016f83 | 86 | #endif |