projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
import gdb-1999-10-25 snapshot
[deliverable/binutils-gdb.git] / sim / common / cgen-par.c
CommitLineData
d4f3574e
SS		 1/* Simulator parallel routines for CGEN simulators (and maybe others).
2 Copyright (C) 1999 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
4
5This file is part of the GNU instruction set simulator.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License along
18with this program; if not, write to the Free Software Foundation, Inc.,
1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include "sim-main.h"
22#include "cgen-mem.h"
23#include "cgen-par.h"
24
25/* Functions required by the cgen interface. These functions add various
26 kinds of writes to the write queue. */
c2c6d25f
JM		 27void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value)
28{
29 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
30 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
31 element->kind = CGEN_BI_WRITE;
e514a9d6 32 element->insn_address = CPU_PC_GET (cpu);
c2c6d25f
JM		 33 element->kinds.bi_write.target = target;
34 element->kinds.bi_write.value = value;
35}
36
d4f3574e
SS		 37void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
38{
39 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
40 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
41 element->kind = CGEN_QI_WRITE;
e514a9d6 42 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 43 element->kinds.qi_write.target = target;
44 element->kinds.qi_write.value = value;
45}
46
47void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
48{
49 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
50 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
51 element->kind = CGEN_SI_WRITE;
e514a9d6 52 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 53 element->kinds.si_write.target = target;
54 element->kinds.si_write.value = value;
55}
56
57void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
58{
59 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
60 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
61 element->kind = CGEN_SF_WRITE;
e514a9d6 62 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 63 element->kinds.sf_write.target = target;
64 element->kinds.sf_write.value = value;
65}
66
67void sim_queue_pc_write (SIM_CPU *cpu, USI value)
68{
69 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
70 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
71 element->kind = CGEN_PC_WRITE;
e514a9d6 72 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 73 element->kinds.pc_write.value = value;
74}
75
2df3850c
JM		 76void sim_queue_fn_hi_write (
77 SIM_CPU *cpu,
78 void (*write_function)(SIM_CPU *cpu, UINT, UHI),
79 UINT regno,
80 UHI value
81)
82{
83 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
84 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
85 element->kind = CGEN_FN_HI_WRITE;
e514a9d6 86 element->insn_address = CPU_PC_GET (cpu);
2df3850c
JM		 87 element->kinds.fn_hi_write.function = write_function;
88 element->kinds.fn_hi_write.regno = regno;
89 element->kinds.fn_hi_write.value = value;
90}
91
d4f3574e
SS		 92void sim_queue_fn_si_write (
93 SIM_CPU *cpu,
94 void (*write_function)(SIM_CPU *cpu, UINT, USI),
95 UINT regno,
96 SI value
97)
98{
99 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
100 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
101 element->kind = CGEN_FN_SI_WRITE;
e514a9d6 102 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 103 element->kinds.fn_si_write.function = write_function;
104 element->kinds.fn_si_write.regno = regno;
105 element->kinds.fn_si_write.value = value;
106}
107
108void sim_queue_fn_di_write (
109 SIM_CPU *cpu,
110 void (*write_function)(SIM_CPU *cpu, UINT, DI),
111 UINT regno,
112 DI value
113)
114{
115 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
116 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
117 element->kind = CGEN_FN_DI_WRITE;
e514a9d6 118 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 119 element->kinds.fn_di_write.function = write_function;
120 element->kinds.fn_di_write.regno = regno;
121 element->kinds.fn_di_write.value = value;
122}
123
124void sim_queue_fn_df_write (
125 SIM_CPU *cpu,
126 void (*write_function)(SIM_CPU *cpu, UINT, DI),
127 UINT regno,
128 DF value
129)
130{
131 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
132 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
133 element->kind = CGEN_FN_DF_WRITE;
e514a9d6 134 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 135 element->kinds.fn_df_write.function = write_function;
136 element->kinds.fn_df_write.regno = regno;
137 element->kinds.fn_df_write.value = value;
138}
139
e514a9d6
JM		 140void sim_queue_fn_pc_write (
141 SIM_CPU *cpu,
142 void (*write_function)(SIM_CPU *cpu, USI),
143 USI value
144)
145{
146 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
147 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
148 element->kind = CGEN_FN_PC_WRITE;
149 element->insn_address = CPU_PC_GET (cpu);
150 element->kinds.fn_pc_write.function = write_function;
151 element->kinds.fn_pc_write.value = value;
152}
153
d4f3574e
SS		 154void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
155{
156 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
157 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
158 element->kind = CGEN_MEM_QI_WRITE;
e514a9d6 159 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 160 element->kinds.mem_qi_write.address = address;
161 element->kinds.mem_qi_write.value = value;
162}
163
164void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
165{
166 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
167 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
168 element->kind = CGEN_MEM_HI_WRITE;
e514a9d6 169 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 170 element->kinds.mem_hi_write.address = address;
171 element->kinds.mem_hi_write.value = value;
172}
173
174void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
175{
176 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
177 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
178 element->kind = CGEN_MEM_SI_WRITE;
e514a9d6 179 element->insn_address = CPU_PC_GET (cpu);
d4f3574e
SS		 180 element->kinds.mem_si_write.address = address;
181 element->kinds.mem_si_write.value = value;
182}
183
917317f4
JM		 184void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
185{
186 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
187 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
188 element->kind = CGEN_MEM_DI_WRITE;
e514a9d6 189 element->insn_address = CPU_PC_GET (cpu);
917317f4
JM		 190 element->kinds.mem_di_write.address = address;
191 element->kinds.mem_di_write.value = value;
192}
193
194void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
195{
196 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
197 CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
198 element->kind = CGEN_MEM_DF_WRITE;
e514a9d6 199 element->insn_address = CPU_PC_GET (cpu);
917317f4
JM		 200 element->kinds.mem_df_write.address = address;
201 element->kinds.mem_df_write.value = value;
202}
203
d4f3574e
SS		 204/* Execute a write stored on the write queue. */
205void
206cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
207{
208 IADDR pc;
209 switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
210 {
c2c6d25f
JM		 211 case CGEN_BI_WRITE:
212 *item->kinds.bi_write.target = item->kinds.bi_write.value;
213 break;
d4f3574e
SS		 214 case CGEN_QI_WRITE:
215 *item->kinds.qi_write.target = item->kinds.qi_write.value;
216 break;
217 case CGEN_SI_WRITE:
218 *item->kinds.si_write.target = item->kinds.si_write.value;
219 break;
220 case CGEN_SF_WRITE:
221 *item->kinds.sf_write.target = item->kinds.sf_write.value;
222 break;
223 case CGEN_PC_WRITE:
224 CPU_PC_SET (cpu, item->kinds.pc_write.value);
225 break;
2df3850c
JM		 226 case CGEN_FN_HI_WRITE:
227 item->kinds.fn_hi_write.function (cpu,
228 item->kinds.fn_hi_write.regno,
229 item->kinds.fn_hi_write.value);
230 break;
d4f3574e
SS		 231 case CGEN_FN_SI_WRITE:
232 item->kinds.fn_si_write.function (cpu,
233 item->kinds.fn_si_write.regno,
234 item->kinds.fn_si_write.value);
235 break;
236 case CGEN_FN_DI_WRITE:
237 item->kinds.fn_di_write.function (cpu,
238 item->kinds.fn_di_write.regno,
239 item->kinds.fn_di_write.value);
240 break;
241 case CGEN_FN_DF_WRITE:
242 item->kinds.fn_df_write.function (cpu,
243 item->kinds.fn_df_write.regno,
244 item->kinds.fn_df_write.value);
245 break;
e514a9d6
JM		 246 case CGEN_FN_PC_WRITE:
247 item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value);
248 break;
d4f3574e 249 case CGEN_MEM_QI_WRITE:
e514a9d6 250 pc = item->insn_address;
d4f3574e
SS		 251 SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
252 item->kinds.mem_qi_write.value);
253 break;
254 case CGEN_MEM_HI_WRITE:
e514a9d6 255 pc = item->insn_address;
d4f3574e
SS		 256 SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
257 item->kinds.mem_hi_write.value);
258 break;
259 case CGEN_MEM_SI_WRITE:
e514a9d6 260 pc = item->insn_address;
d4f3574e
SS		 261 SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
262 item->kinds.mem_si_write.value);
263 break;
917317f4 264 case CGEN_MEM_DI_WRITE:
e514a9d6 265 pc = item->insn_address;
917317f4
JM		 266 SETMEMDI (cpu, pc, item->kinds.mem_di_write.address,
267 item->kinds.mem_di_write.value);
268 break;
269 case CGEN_MEM_DF_WRITE:
e514a9d6 270 pc = item->insn_address;
917317f4
JM		 271 SETMEMDF (cpu, pc, item->kinds.mem_df_write.address,
272 item->kinds.mem_df_write.value);
273 break;
d4f3574e
SS		 274 default:
275 break; /* FIXME: for now....print message later. */
276 }
277}
278
279/* Utilities for the write queue. */
280CGEN_WRITE_QUEUE_ELEMENT *
281cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
282{
283 abort (); /* FIXME: for now....print message later. */
284 return 0;
285}
GDB Binutils - Deliverables
This page took 0.03713 seconds and 4 git commands to generate.