[deliverable/binutils-gdb.git] / sim / cr16 / cr16_sim.h

/* Simulation code for the CR16 processor.
   Copyright (C) 2008-2020 Free Software Foundation, Inc.
   Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>

   This file is part of GDB, the GNU debugger.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program. If not, see <http://www.gnu.org/licenses/>.  */


#include "config.h"
#include <stdio.h>
#include <ctype.h>
#include <limits.h>
#include "ansidecl.h"
#include "gdb/callback.h"
#include "opcode/cr16.h"
#include "bfd.h"

#define DEBUG_TRACE		0x00000001
#define DEBUG_VALUES		0x00000002
#define DEBUG_LINE_NUMBER	0x00000004
#define DEBUG_MEMSIZE		0x00000008
#define DEBUG_INSTRUCTION	0x00000010
#define DEBUG_TRAP		0x00000020
#define DEBUG_MEMORY		0x00000040

#ifndef	DEBUG
#define	DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
#endif

extern int cr16_debug;

#include "gdb/remote-sim.h"
#include "sim-config.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef signed8 int8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

/* FIXME: CR16 defines */
typedef uint16 reg_t;
typedef uint32 creg_t;

struct simops 
{
  char mnimonic[12];
  uint32 size;
  uint32 mask;
  uint32 opcode;
  int format;
  char fname[12];
  void (*func)(SIM_DESC, SIM_CPU *);
  int numops;
  operand_desc operands[4];
};

enum _ins_type
{
   INS_UNKNOWN,			/* unknown instruction */
   INS_NO_TYPE_INS,
   INS_ARITH_INS,
   INS_LD_STOR_INS,
   INS_BRANCH_INS,
   INS_ARITH_BYTE_INS,
   INS_SHIFT_INS,
   INS_BRANCH_NEQ_INS,
   INS_STOR_IMM_INS, 
   INS_CSTBIT_INS, 
   INS_MAX
};

extern unsigned long ins_type_counters[ (int)INS_MAX ];

enum {
  SP_IDX = 15,
};

/* Write-back slots */
union slot_data {
  unsigned_1 _1;
  unsigned_2 _2;
  unsigned_4 _4;
};
struct slot {
  void *dest;
  int size;
  union slot_data data;
  union slot_data mask;
};
enum {
 NR_SLOTS = 16
};
#define SLOT (State.slot)
#define SLOT_NR (State.slot_nr)
#define SLOT_PEND_MASK(DEST, MSK, VAL) \
  do \
    { \
      SLOT[SLOT_NR].dest = &(DEST); \
      SLOT[SLOT_NR].size = sizeof (DEST); \
      switch (sizeof (DEST)) \
        { \
        case 1: \
          SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
          SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
          break; \
        case 2: \
          SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
          SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
          break; \
        case 4: \
          SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
          SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
          break; \
        } \
      SLOT_NR = (SLOT_NR + 1); \
    } \
  while (0)
#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
#define SLOT_DISCARD() (SLOT_NR = 0)
#define SLOT_FLUSH() \
  do \
    { \
      int i; \
      for (i = 0; i < SLOT_NR; i++) \
	{ \
	  switch (SLOT[i].size) \
	    { \
	    case 1: \
	      *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
	      *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
	      break; \
	    case 2: \
	      *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
	      *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
	      break; \
	    case 4: \
	      *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
	      *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
	      break; \
	    } \
        } \
      SLOT_NR = 0; \
    } \
  while (0)
#define SLOT_DUMP() \
  do \
    { \
      int i; \
      for (i = 0; i < SLOT_NR; i++) \
	{ \
	  switch (SLOT[i].size) \
	    { \
	    case 1: \
              printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._1, \
                      (unsigned) SLOT[i].data._1); \
	      break; \
	    case 2: \
              printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._2, \
                      (unsigned) SLOT[i].data._2); \
	      break; \
	    case 4: \
              printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._4, \
                      (unsigned) SLOT[i].data._4); \
	      break; \
	    case 8: \
              printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) (SLOT[i].mask._8 >> 32),  \
                      (unsigned) SLOT[i].mask._8, \
                      (unsigned) (SLOT[i].data._8 >> 32),  \
                      (unsigned) SLOT[i].data._8); \
	      break; \
	    } \
        } \
    } \
  while (0)

struct _state
{
  creg_t regs[16];		/* general-purpose registers */
#define GPR(N) (State.regs[(N)] + 0)
#define SET_GPR(N,VAL) (State.regs[(N)] = (VAL))

#define GPR32(N) \
     (N < 12) ? \
     ((((uint16) State.regs[(N) + 1]) << 16) | (uint16) State.regs[(N)]) \
     : GPR (N) 

#define SET_GPR32(N,VAL) do { \
     if (N < 11)  \
       { SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \
     else { if ( N == 11) \
             { SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \
	       SET_GPR (N, ((VAL) & 0xffff));} \
            else SET_GPR (N, (VAL));} \
    } while (0)

  creg_t cregs[16];		/* control registers */
#define CREG(N) (State.cregs[(N)] + 0)
#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)

  reg_t sp[2];                  /* holding area for SPI(0)/SPU(1) */
#define HELD_SP(N) (State.sp[(N)] + 0)
#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))

  /* writeback info */
  struct slot slot[NR_SLOTS];
  int slot_nr;

  /* trace data */
  struct {
    uint16 psw;
  } trace;

  int	pc_changed;

  /* NOTE: everything below this line is not reset by
     sim_create_inferior() */

  enum _ins_type ins_type;

} State;


extern uint32 OP[4];
extern uint32 sign_flag;
extern struct simops Simops[];

enum
{
  PC_CR   = 0,
  BDS_CR  = 1,
  BSR_CR  = 2,
  DCR_CR  = 3,
  CAR0_CR = 5,
  CAR1_CR = 7,
  CFG_CR  = 9,
  PSR_CR  = 10,
  INTBASE_CR = 11,
  ISP_CR = 13,
  USP_CR = 15
};

enum
{
  PSR_I_BIT = 0x0800,
  PSR_P_BIT = 0x0400,
  PSR_E_BIT = 0x0200,
  PSR_N_BIT = 0x0080,
  PSR_Z_BIT = 0x0040,
  PSR_F_BIT = 0x0020,
  PSR_U_BIT = 0x0008,
  PSR_L_BIT = 0x0004,
  PSR_T_BIT = 0x0002,
  PSR_C_BIT = 0x0001
};

#define PSR CREG (PSR_CR)
#define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
#define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
#define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)

#define PSR_SM ((PSR & PSR_SM_BIT) != 0)
#define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))

#define PSR_I ((PSR & PSR_I_BIT) != 0)
#define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL))

#define PSR_DB ((PSR & PSR_DB_BIT) != 0)
#define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL))

#define PSR_P ((PSR & PSR_P_BIT) != 0)
#define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL))

#define PSR_E ((PSR & PSR_E_BIT) != 0)
#define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL))

#define PSR_N ((PSR & PSR_N_BIT) != 0)
#define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL))

#define PSR_Z ((PSR & PSR_Z_BIT) != 0)
#define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL))

#define PSR_F ((PSR & PSR_F_BIT) != 0)
#define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL))

#define PSR_U ((PSR & PSR_U_BIT) != 0)
#define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL))

#define PSR_L ((PSR & PSR_L_BIT) != 0)
#define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL))

#define PSR_T ((PSR & PSR_T_BIT) != 0)
#define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL))

#define PSR_C ((PSR & PSR_C_BIT) != 0)
#define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL))

/* See simopsc.:move_to_cr() for registers that can not be read-from
   or assigned-to directly */

#define PC	CREG (PC_CR)
#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
//#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL))

#define BPSR	CREG (BPSR_CR)
#define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL))

#define BPC	CREG (BPC_CR)
#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))

#define DPSR	CREG (DPSR_CR)
#define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL))

#define DPC	CREG (DPC_CR)
#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))

#define RPT_C	CREG (RPT_C_CR)
#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))

#define RPT_S	CREG (RPT_S_CR)
#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))

#define RPT_E	CREG (RPT_E_CR)
#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))

#define MOD_S	CREG (MOD_S_CR)
#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))

#define MOD_E	CREG (MOD_E_CR)
#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))

#define IBA	CREG (IBA_CR)
#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))


#define SIG_CR16_STOP	-1
#define SIG_CR16_EXIT	-2
#define SIG_CR16_BUS    -3
#define SIG_CR16_IAD    -4

/* TODO: Resolve conflicts with common headers.  */
#undef SEXT8
#undef SEXT16
#undef SEXT32

#define SEXT3(x)	((((x)&0x7)^(~3))+4)	

/* sign-extend a 4-bit number */
#define SEXT4(x)	((((x)&0xf)^(~7))+8)	

/* sign-extend an 8-bit number */
#define SEXT8(x)	((((x)&0xff)^(~0x7f))+0x80)

/* sign-extend a 16-bit number */
#define SEXT16(x)	((((x)&0xffff)^(~0x7fff))+0x8000)

/* sign-extend a 24-bit number */
#define SEXT24(x)	((((x)&0xffffff)^(~0x7fffff))+0x800000)

/* sign-extend a 32-bit number */
#define SEXT32(x)	((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)

#define SB(addr, data)		sim_core_write_1 (cpu, PC, read_map, addr, data)
#define RB(addr)		sim_core_read_1 (cpu, PC, read_map, addr)
#define SW(addr, data)		sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
#define RW(addr)		sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
#define SLW(addr, data)		sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)

/* Yes, this is as whacked as it looks.  The sim currently reads little endian
   for 16 bits, but then merge them like big endian to get 32 bits.  */
static inline uint32 get_longword (SIM_CPU *cpu, address_word addr)
{
  return (RW (addr) << 16) | RW (addr + 2);
}
#define RLW(addr)		get_longword (cpu, addr)

#define JMP(x)			do { SET_PC (x); State.pc_changed = 1; } while (0)

#define RIE_VECTOR_START  0xffc2
#define AE_VECTOR_START   0xffc3
#define TRAP_VECTOR_START 0xffc4	/* vector for trap 0 */
#define DBT_VECTOR_START  0xffd4
#define SDBT_VECTOR_START 0xffd5

#define INT_VECTOR_START   0xFFFE00 /*maskable interrupt - mapped to ICU */
#define NMI_VECTOR_START   0xFFFF00 /*non-maskable interrupt;for observability*/
#define ISE_VECTOR_START   0xFFFC00 /*in-system emulation trap */
#define ADBG_VECTOR_START  0xFFFC02 /*alternate debug trap */
#define ATRC_VECTOR_START  0xFFFC0C /*alternate trace trap */
#define ABPT_VECTOR_START  0xFFFC0E /*alternate break point trap */


/* Scedule a store of VAL into cr[CR].  MASK indicates the bits in
   cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
   (VAL & ~MASK)).  In addition, unless PSR_HW_P, a VAL intended for
   PSR is masked for zero bits. */

extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p);

#ifndef SIGTRAP
#define SIGTRAP 5
#endif
/* Special purpose trap  */
#define TRAP_BREAKPOINT 8
Commit	Line	Data
fee8ec00	1	/* Simulation code for the CR16 processor.
b811d2c2	2	Copyright (C) 2008-2020 Free Software Foundation, Inc.
fee8ec00 SR	3	Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
dc3cf14f	9	the Free Software Foundation; either version 3, or (at your option)
fee8ec00 SR	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
8e26b0f4 SR	17	You should have received a copy of the GNU General Public License
	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	19
fee8ec00 SR	20
	21	#include "config.h"
	22	#include <stdio.h>
	23	#include <ctype.h>
	24	#include <limits.h>
	25	#include "ansidecl.h"
	26	#include "gdb/callback.h"
	27	#include "opcode/cr16.h"
	28	#include "bfd.h"
	29
	30	#define DEBUG_TRACE 0x00000001
	31	#define DEBUG_VALUES 0x00000002
	32	#define DEBUG_LINE_NUMBER 0x00000004
	33	#define DEBUG_MEMSIZE 0x00000008
	34	#define DEBUG_INSTRUCTION 0x00000010
	35	#define DEBUG_TRAP 0x00000020
	36	#define DEBUG_MEMORY 0x00000040
	37
	38	#ifndef DEBUG
	39	#define DEBUG (DEBUG_TRACE \| DEBUG_VALUES \| DEBUG_LINE_NUMBER)
	40	#endif
	41
	42	extern int cr16_debug;
	43
	44	#include "gdb/remote-sim.h"
	45	#include "sim-config.h"
	46	#include "sim-types.h"
	47
	48	typedef unsigned8 uint8;
	49	typedef signed8 int8;
	50	typedef unsigned16 uint16;
	51	typedef signed16 int16;
	52	typedef unsigned32 uint32;
	53	typedef signed32 int32;
	54	typedef unsigned64 uint64;
	55	typedef signed64 int64;
	56
	57	/* FIXME: CR16 defines */
	58	typedef uint16 reg_t;
	59	typedef uint32 creg_t;
	60
	61	struct simops
	62	{
8e26b0f4 SR	63	char mnimonic[12];
	64	uint32 size;
	65	uint32 mask;
	66	uint32 opcode;
fee8ec00	67	int format;
8e26b0f4	68	char fname[12];
267b3b8e	69	void (func)(SIM_DESC, SIM_CPU );
fee8ec00	70	int numops;
8e26b0f4	71	operand_desc operands[4];
fee8ec00 SR	72	};
	73
	74	enum _ins_type
	75	{
	76	INS_UNKNOWN, /* unknown instruction */
	77	INS_NO_TYPE_INS,
	78	INS_ARITH_INS,
	79	INS_LD_STOR_INS,
	80	INS_BRANCH_INS,
	81	INS_ARITH_BYTE_INS,
	82	INS_SHIFT_INS,
	83	INS_BRANCH_NEQ_INS,
	84	INS_STOR_IMM_INS,
	85	INS_CSTBIT_INS,
	86	INS_MAX
	87	};
	88
	89	extern unsigned long ins_type_counters[ (int)INS_MAX ];
	90
	91	enum {
	92	SP_IDX = 15,
	93	};
	94
	95	/* Write-back slots */
	96	union slot_data {
	97	unsigned_1 _1;
	98	unsigned_2 _2;
	99	unsigned_4 _4;
	100	};
	101	struct slot {
	102	void *dest;
	103	int size;
	104	union slot_data data;
	105	union slot_data mask;
	106	};
	107	enum {
	108	NR_SLOTS = 16
	109	};
	110	#define SLOT (State.slot)
	111	#define SLOT_NR (State.slot_nr)
	112	#define SLOT_PEND_MASK(DEST, MSK, VAL) \
	113	do \
	114	{ \
	115	SLOT[SLOT_NR].dest = &(DEST); \
	116	SLOT[SLOT_NR].size = sizeof (DEST); \
	117	switch (sizeof (DEST)) \
	118	{ \
	119	case 1: \
	120	SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
	121	SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
	122	break; \
	123	case 2: \
	124	SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
	125	SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
	126	break; \
	127	case 4: \
	128	SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
	129	SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
	130	break; \
	131	} \
	132	SLOT_NR = (SLOT_NR + 1); \
	133	} \
	134	while (0)
	135	#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
136	#define SLOT_DISCARD() (SLOT_NR = 0)
137	#define SLOT_FLUSH() \
138	do \
139	{ \
140	int i; \
141	for (i = 0; i < SLOT_NR; i++) \
142	{ \
143	switch (SLOT[i].size) \
144	{ \
145	case 1: \
146	(unsigned_1) SLOT[i].dest &= SLOT[i].mask._1; \
147	(unsigned_1) SLOT[i].dest \|= SLOT[i].data._1; \
148	break; \
149	case 2: \
150	(unsigned_2) SLOT[i].dest &= SLOT[i].mask._2; \
151	(unsigned_2) SLOT[i].dest \|= SLOT[i].data._2; \
152	break; \
153	case 4: \
154	(unsigned_4) SLOT[i].dest &= SLOT[i].mask._4; \
155	(unsigned_4) SLOT[i].dest \|= SLOT[i].data._4; \
156	break; \
157	} \
158	} \
159	SLOT_NR = 0; \
160	} \
161	while (0)
162	#define SLOT_DUMP() \
163	do \
164	{ \
165	int i; \
166	for (i = 0; i < SLOT_NR; i++) \
167	{ \
168	switch (SLOT[i].size) \
169	{ \
170	case 1: \
171	printf ("SLOT %d *0x%08lx & 0x%02x \| 0x%02x\n", i, \
172	(long) SLOT[i].dest, \
173	(unsigned) SLOT[i].mask._1, \
174	(unsigned) SLOT[i].data._1); \
175	break; \
176	case 2: \
177	printf ("SLOT %d *0x%08lx & 0x%04x \| 0x%04x\n", i, \
178	(long) SLOT[i].dest, \
179	(unsigned) SLOT[i].mask._2, \
180	(unsigned) SLOT[i].data._2); \
181	break; \
182	case 4: \
183	printf ("SLOT %d *0x%08lx & 0x%08x \| 0x%08x\n", i, \
184	(long) SLOT[i].dest, \
185	(unsigned) SLOT[i].mask._4, \
186	(unsigned) SLOT[i].data._4); \
187	break; \
188	case 8: \
189	printf ("SLOT %d *0x%08lx & 0x%08x%08x \| 0x%08x%08x\n", i, \
190	(long) SLOT[i].dest, \
191	(unsigned) (SLOT[i].mask._8 >> 32), \
192	(unsigned) SLOT[i].mask._8, \
193	(unsigned) (SLOT[i].data._8 >> 32), \
194	(unsigned) SLOT[i].data._8); \
195	break; \
196	} \
197	} \
198	} \
199	while (0)
200
fee8ec00 SR	201	struct _state
	202	{
	203	creg_t regs[16]; /* general-purpose registers */
	204	#define GPR(N) (State.regs[(N)] + 0)
	205	#define SET_GPR(N,VAL) (State.regs[(N)] = (VAL))
	206
	207	#define GPR32(N) \
	208	(N < 12) ? \
	209	((((uint16) State.regs[(N) + 1]) << 16) \| (uint16) State.regs[(N)]) \
	210	: GPR (N)
	211
	212	#define SET_GPR32(N,VAL) do { \
	213	if (N < 11) \
	214	{ SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \
	215	else { if ( N == 11) \
	216	{ SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)\|((VAL) >> 16)); \
	217	SET_GPR (N, ((VAL) & 0xffff));} \
	218	else SET_GPR (N, (VAL));} \
	219	} while (0)
	220
	221	creg_t cregs[16]; /* control registers */
	222	#define CREG(N) (State.cregs[(N)] + 0)
267b3b8e MF	223	#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
267b3b8e MF	224	#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
fee8ec00 SR	225
	226	reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
	227	#define HELD_SP(N) (State.sp[(N)] + 0)
	228	#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
	229
	230	/* writeback info */
	231	struct slot slot[NR_SLOTS];
	232	int slot_nr;
	233
	234	/* trace data */
	235	struct {
	236	uint16 psw;
	237	} trace;
	238
fee8ec00 SR	239	int pc_changed;
	240
	241	/* NOTE: everything below this line is not reset by
	242	sim_create_inferior() */
	243
fee8ec00 SR	244	enum _ins_type ins_type;
	245
	246	} State;
	247
	248
fee8ec00 SR	249	extern uint32 OP[4];
	250	extern uint32 sign_flag;
	251	extern struct simops Simops[];
fee8ec00 SR	252
	253	enum
	254	{
	255	PC_CR = 0,
	256	BDS_CR = 1,
	257	BSR_CR = 2,
	258	DCR_CR = 3,
	259	CAR0_CR = 5,
	260	CAR1_CR = 7,
	261	CFG_CR = 9,
	262	PSR_CR = 10,
	263	INTBASE_CR = 11,
	264	ISP_CR = 13,
	265	USP_CR = 15
	266	};
	267
	268	enum
	269	{
	270	PSR_I_BIT = 0x0800,
	271	PSR_P_BIT = 0x0400,
	272	PSR_E_BIT = 0x0200,
8e26b0f4	273	PSR_N_BIT = 0x0080,
fee8ec00 SR	274	PSR_Z_BIT = 0x0040,
fee8ec00 SR	275	PSR_F_BIT = 0x0020,
8e26b0f4	276	PSR_U_BIT = 0x0008,
fee8ec00 SR	277	PSR_L_BIT = 0x0004,
fee8ec00 SR	278	PSR_T_BIT = 0x0002,
8e26b0f4	279	PSR_C_BIT = 0x0001
fee8ec00 SR	280	};
	281
	282	#define PSR CREG (PSR_CR)
	283	#define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
	284	#define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
267b3b8e	285	#define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
fee8ec00 SR	286
	287	#define PSR_SM ((PSR & PSR_SM_BIT) != 0)
	288	#define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))
	289
	290	#define PSR_I ((PSR & PSR_I_BIT) != 0)
	291	#define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL))
	292
	293	#define PSR_DB ((PSR & PSR_DB_BIT) != 0)
	294	#define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL))
	295
	296	#define PSR_P ((PSR & PSR_P_BIT) != 0)
	297	#define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL))
	298
	299	#define PSR_E ((PSR & PSR_E_BIT) != 0)
	300	#define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL))
	301
	302	#define PSR_N ((PSR & PSR_N_BIT) != 0)
	303	#define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL))
	304
	305	#define PSR_Z ((PSR & PSR_Z_BIT) != 0)
	306	#define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL))
	307
	308	#define PSR_F ((PSR & PSR_F_BIT) != 0)
	309	#define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL))
	310
	311	#define PSR_U ((PSR & PSR_U_BIT) != 0)
	312	#define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL))
	313
	314	#define PSR_L ((PSR & PSR_L_BIT) != 0)
	315	#define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL))
	316
	317	#define PSR_T ((PSR & PSR_T_BIT) != 0)
	318	#define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL))
	319
	320	#define PSR_C ((PSR & PSR_C_BIT) != 0)
	321	#define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL))
	322
	323	/* See simopsc.:move_to_cr() for registers that can not be read-from
	324	or assigned-to directly */
	325
	326	#define PC CREG (PC_CR)
	327	#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
	328	//#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL))
	329
	330	#define BPSR CREG (BPSR_CR)
	331	#define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL))
	332
	333	#define BPC CREG (BPC_CR)
	334	#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
	335
	336	#define DPSR CREG (DPSR_CR)
	337	#define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL))
	338
	339	#define DPC CREG (DPC_CR)
	340	#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
	341
	342	#define RPT_C CREG (RPT_C_CR)
	343	#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
	344
	345	#define RPT_S CREG (RPT_S_CR)
	346	#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
	347
	348	#define RPT_E CREG (RPT_E_CR)
	349	#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
350
351	#define MOD_S CREG (MOD_S_CR)
352	#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
353
354	#define MOD_E CREG (MOD_E_CR)
355	#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
356
357	#define IBA CREG (IBA_CR)
358	#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
359
360
361	#define SIG_CR16_STOP -1
362	#define SIG_CR16_EXIT -2
363	#define SIG_CR16_BUS -3
364	#define SIG_CR16_IAD -4
365
247ac9ee MF	366	/* TODO: Resolve conflicts with common headers. */
	367	#undef SEXT8
	368	#undef SEXT16
	369	#undef SEXT32
	370
fee8ec00 SR	371	#define SEXT3(x) ((((x)&0x7)^(~3))+4)
	372
	373	/* sign-extend a 4-bit number */
	374	#define SEXT4(x) ((((x)&0xf)^(~7))+8)
	375
	376	/* sign-extend an 8-bit number */
	377	#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
	378
	379	/* sign-extend a 16-bit number */
	380	#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
	381
	382	/* sign-extend a 24-bit number */
	383	#define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000)
	384
	385	/* sign-extend a 32-bit number */
	386	#define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
	387
761e171a MF	388	#define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data)
	389	#define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr)
	390	#define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
	391	#define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
	392	#define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
fee8ec00	393
761e171a MF	394	/* Yes, this is as whacked as it looks. The sim currently reads little endian
	395	for 16 bits, but then merge them like big endian to get 32 bits. */
	396	static inline uint32 get_longword (SIM_CPU *cpu, address_word addr)
	397	{
	398	return (RW (addr) << 16) \| RW (addr + 2);
	399	}
	400	#define RLW(addr) get_longword (cpu, addr)
fee8ec00 SR	401
	402	#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
	403
	404	#define RIE_VECTOR_START 0xffc2
	405	#define AE_VECTOR_START 0xffc3
	406	#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
	407	#define DBT_VECTOR_START 0xffd4
	408	#define SDBT_VECTOR_START 0xffd5
	409
	410	#define INT_VECTOR_START 0xFFFE00 /maskable interrupt - mapped to ICU /
	411	#define NMI_VECTOR_START 0xFFFF00 /non-maskable interrupt;for observability/
	412	#define ISE_VECTOR_START 0xFFFC00 /in-system emulation trap /
	413	#define ADBG_VECTOR_START 0xFFFC02 /alternate debug trap /
	414	#define ATRC_VECTOR_START 0xFFFC0C /alternate trace trap /
	415	#define ABPT_VECTOR_START 0xFFFC0E /alternate break point trap /
	416
	417
	418	/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
	419	cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) \|
	420	(VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for
	421	PSR is masked for zero bits. */
	422
267b3b8e	423	extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p);
5a06d7c4 MF	424
	425	#ifndef SIGTRAP
	426	#define SIGTRAP 5
	427	#endif
	428	/* Special purpose trap */
	429	#define TRAP_BREAKPOINT 8