Update copyright year range in all GDB files.
[deliverable/binutils-gdb.git] / sim / cris / Makefile.in
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1# Makefile template for Configure for the CRIS simulator, based on a mix
2# of the ones for m32r and i960.
3#
b811d2c2 4# Copyright (C) 2004-2020 Free Software Foundation, Inc.
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5# Contributed by Axis Communications.
6#
7# This program is free software; you can redistribute it and/or modify
8# it under the terms of the GNU General Public License as published by
4744ac1b 9# the Free Software Foundation; either version 3 of the License, or
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10# (at your option) any later version.
11#
12# This program is distributed in the hope that it will be useful,
13# but WITHOUT ANY WARRANTY; without even the implied warranty of
14# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15# GNU General Public License for more details.
16#
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17# You should have received a copy of the GNU General Public License
18# along with this program. If not, see <http://www.gnu.org/licenses/>.
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19
20## COMMON_PRE_CONFIG_FRAG
21
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22CRISV10F_OBJS = crisv10f.o cpuv10.o decodev10.o modelv10.o mloopv10f.o
23CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o modelv32.o mloopv32f.o
f6bcefef 24
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25SIM_OBJS = \
26 $(SIM_NEW_COMMON_OBJS) \
f6bcefef 27 cgen-utils.o cgen-trace.o cgen-scache.o \
797eee42 28 cgen-run.o \
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29 sim-if.o arch.o \
30 $(CRISV10F_OBJS) \
31 $(CRISV32F_OBJS) \
34cf5112 32 traps.o \
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33 cris-desc.o
34
35# Extra headers included by sim-main.h.
36# FIXME: $(srccom)/cgen-ops.h should be in CGEN_INCLUDE_DEPS.
37SIM_EXTRA_DEPS = \
38 $(CGEN_INCLUDE_DEPS) $(srccom)/cgen-ops.h \
39 arch.h cpuall.h cris-sim.h cris-desc.h
40
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41SIM_EXTRA_CLEAN = cris-clean
42
43# This selects the cris newlib/libgloss syscall definitions.
44NL_TARGET = -DNL_TARGET_cris
45
46## COMMON_POST_CONFIG_FRAG
47
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48arch = cris
49
50sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(sim-core_h) $(sim-options_h)
51
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52# Needs CPU-specific knowledge.
53dv-cris.o: dv-cris.c $(SIM_MAIN_DEPS) $(sim-core_h)
54
55# This is the same rule as dv-core.o etc.
56dv-rv.o: dv-rv.c $(hw_main_headers) $(sim_main_headers)
57
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58arch.o: arch.c $(SIM_MAIN_DEPS)
59
60traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS) $(sim-options_h)
61devices.o: devices.c $(SIM_MAIN_DEPS)
62
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63# rvdummy is just used for testing. It does nothing if
64# --enable-sim-hardware isn't active.
65
66all: rvdummy$(EXEEXT)
67
68check: rvdummy$(EXEEXT)
69
70rvdummy$(EXEEXT): rvdummy.o $(EXTRA_LIBDEPS)
71 $(CC) $(ALL_CFLAGS) -o rvdummy$(EXEEXT) rvdummy.o $(EXTRA_LIBS)
72
1b393626 73rvdummy.o: rvdummy.c config.h $(remote_sim_h) $(callback_h)
aad3b3cb 74
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75# CRISV10 objs
76
77CRISV10F_INCLUDE_DEPS = \
78 $(CGEN_MAIN_CPU_DEPS) \
79 cpuv10.h decodev10.h engv10.h
80
81crisv10f.o: crisv10f.c cris-tmpl.c $(CRISV10F_INCLUDE_DEPS)
82
83# FIXME: What is mono and what does "Use of `mono' is wip" mean (other
84# than the apparent; some "mono" feature is work in progress)?
85mloopv10f.c engv10.h: stamp-v10fmloop
86stamp-v10fmloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
086c6838 87 $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
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88 -mono -no-fast -pbb -switch semcrisv10f-switch.c \
89 -cpu crisv10f -infile $(srcdir)/mloop.in
90 $(SHELL) $(srcroot)/move-if-change eng.hin engv10.h
91 $(SHELL) $(srcroot)/move-if-change mloop.cin mloopv10f.c
92 touch stamp-v10fmloop
93mloopv10f.o: mloopv10f.c semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
94
95cpuv10.o: cpuv10.c $(CRISV10F_INCLUDE_DEPS)
96decodev10.o: decodev10.c $(CRISV10F_INCLUDE_DEPS)
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97modelv10.o: modelv10.c $(CRISV10F_INCLUDE_DEPS)
98
99# CRISV32 objs
100
101CRISV32F_INCLUDE_DEPS = \
102 $(CGEN_MAIN_CPU_DEPS) \
103 cpuv32.h decodev32.h engv32.h
104
105crisv32f.o: crisv32f.c cris-tmpl.c $(CRISV32F_INCLUDE_DEPS)
106
107# FIXME: What is mono and what does "Use of `mono' is wip" mean (other
108# than the apparent; some "mono" feature is work in progress)?
109mloopv32f.c engv32.h: stamp-v32fmloop
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110# We depend on stamp-v10fmloop to get serialization to avoid
111# racing with it for the same temporary file-names when "make -j".
112stamp-v32fmloop: stamp-v10fmloop $(srcdir)/../common/genmloop.sh mloop.in Makefile
086c6838 113 $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
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114 -mono -no-fast -pbb -switch semcrisv32f-switch.c \
115 -cpu crisv32f -infile $(srcdir)/mloop.in
116 $(SHELL) $(srcroot)/move-if-change eng.hin engv32.h
117 $(SHELL) $(srcroot)/move-if-change mloop.cin mloopv32f.c
118 touch stamp-v32fmloop
119mloopv32f.o: mloopv32f.c semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
120
121cpuv32.o: cpuv32.c $(CRISV32F_INCLUDE_DEPS)
122decodev32.o: decodev32.c $(CRISV32F_INCLUDE_DEPS)
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123modelv32.o: modelv32.c $(CRISV32F_INCLUDE_DEPS)
124
125cris-clean:
126 for v in 10 32; do \
127 rm -f mloopv$${v}f.c engv$${v}.h stamp-v$${v}fmloop; \
128 rm -f stamp-v$${v}fcpu; \
129 done
130 -rm -f stamp-arch stamp-desc
131 -rm -f tmp-*
132
133# cgen support, enable with --enable-cgen-maint
134CGEN_MAINT = ; @true
135# The following line is commented in or out depending upon --enable-cgen-maint.
136@CGEN_MAINT@CGEN_MAINT =
137
138# Useful when making CGEN-generated files manually, without --enable-cgen-maint.
139stamps: stamp-v10fmloop stamp-v32fmloop stamp-arch stamp-v10fcpu stamp-v32fcpu stamp-desc
140
23ebf378 141stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CPU_DIR)/cris.cpu Makefile
f6bcefef 142 $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=crisv10,crisv32 \
23ebf378 143 archfile=$(CPU_DIR)/cris.cpu \
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144 FLAGS="with-scache with-profile=fn"
145 touch stamp-arch
146arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
147
cce0efb5 148# The sed-hack is supposed to be temporary, until we get CGEN to emit it.
23ebf378 149stamp-v10fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/cris.cpu Makefile
f6bcefef 150 $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
23ebf378 151 archfile=$(CPU_DIR)/cris.cpu \
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152 cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
153 $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv10-switch.c $(srcdir)/semcrisv10f-switch.c
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154 sed -ne 'p; s/^\(#include "sim-assert.h"\)$$/#include "cgen-ops.h"/p' < $(srcdir)/decodev10.c > decodev10.c.tmp
155 mv decodev10.c.tmp $(srcdir)/decodev10.c
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156 touch stamp-v10fcpu
157cpuv10.h cpuv10.c semcrisv10f-switch.c modelv10.c decodev10.c decodev10.h: $(CGEN_MAINT) stamp-v10fcpu
158
23ebf378 159stamp-v32fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/cris.cpu Makefile
f6bcefef 160 $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
23ebf378 161 archfile=$(CPU_DIR)/cris.cpu \
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162 cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
163 $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv32-switch.c $(srcdir)/semcrisv32f-switch.c
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164 sed -ne 'p; s/^\(#include "sim-assert.h"\)$$/#include "cgen-ops.h"/p' < $(srcdir)/decodev32.c > decodev32.c.tmp
165 mv decodev32.c.tmp $(srcdir)/decodev32.c
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166 touch stamp-v32fcpu
167cpuv32.h cpuv32.c semcrisv32f-switch.c modelv32.c decodev32.c decodev32.h: $(CGEN_MAINT) stamp-v32fcpu
168
23ebf378 169stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) $(CPU_DIR)/cris.cpu Makefile
f6bcefef 170 $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
23ebf378 171 archfile=$(CPU_DIR)/cris.cpu \
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172 cpu=cris mach=all
173 touch stamp-desc
174cris-desc.c cris-desc.h cris-opc.h: $(CGEN_MAINT) stamp-desc
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