Commit | Line | Data |
---|---|---|
fd435e9f MM |
1 | #include "config.h" |
2 | ||
4f425a32 | 3 | #include <signal.h> |
63a91cfb MM |
4 | #include <errno.h> |
5 | #include <sys/types.h> | |
6 | #include <sys/stat.h> | |
fd435e9f | 7 | #ifdef HAVE_UNISTD_H |
63a91cfb | 8 | #include <unistd.h> |
fd435e9f | 9 | #endif |
63a91cfb | 10 | |
2934d1c9 MH |
11 | #include "d10v_sim.h" |
12 | #include "simops.h" | |
8719be26 | 13 | #include "sys/syscall.h" |
2934d1c9 | 14 | |
c422ecc7 MH |
15 | extern char *strrchr (); |
16 | ||
87178dbd MM |
17 | enum op_types { |
18 | OP_VOID, | |
19 | OP_REG, | |
20 | OP_REG_OUTPUT, | |
21 | OP_DREG, | |
22 | OP_DREG_OUTPUT, | |
23 | OP_ACCUM, | |
24 | OP_ACCUM_OUTPUT, | |
25 | OP_ACCUM_REVERSE, | |
26 | OP_CR, | |
27 | OP_CR_OUTPUT, | |
28 | OP_CR_REVERSE, | |
29 | OP_FLAG, | |
60fc5b72 | 30 | OP_FLAG_OUTPUT, |
87178dbd | 31 | OP_CONSTANT16, |
a18cb100 | 32 | OP_CONSTANT8, |
87178dbd MM |
33 | OP_CONSTANT3, |
34 | OP_CONSTANT4, | |
35 | OP_MEMREF, | |
36 | OP_MEMREF2, | |
37 | OP_POSTDEC, | |
38 | OP_POSTINC, | |
a18cb100 | 39 | OP_PREDEC, |
8831cb01 MM |
40 | OP_R0, |
41 | OP_R1, | |
a18cb100 | 42 | OP_R2, |
8831cb01 | 43 | OP_R0R1 |
87178dbd MM |
44 | }; |
45 | ||
bc6df23d AC |
46 | |
47 | void | |
48 | move_to_cr (int cr, reg_t val) | |
49 | { | |
50 | switch (cr) | |
51 | { | |
52 | case PSW_CR: | |
ac9a7d8a | 53 | State.sp[State.SM] = State.regs[SP_IDX]; /* save old SP */ |
bc6df23d AC |
54 | State.SM = (val & PSW_SM_BIT) != 0; |
55 | State.EA = (val & PSW_EA_BIT) != 0; | |
56 | State.DB = (val & PSW_DB_BIT) != 0; | |
57 | State.DM = (val & PSW_DM_BIT) != 0; | |
58 | State.IE = (val & PSW_IE_BIT) != 0; | |
59 | State.RP = (val & PSW_RP_BIT) != 0; | |
60 | State.MD = (val & PSW_MD_BIT) != 0; | |
61 | State.FX = (val & PSW_FX_BIT) != 0; | |
62 | State.ST = (val & PSW_ST_BIT) != 0; | |
63 | State.F0 = (val & PSW_F0_BIT) != 0; | |
64 | State.F1 = (val & PSW_F1_BIT) != 0; | |
65 | State.C = (val & PSW_C_BIT) != 0; | |
ac9a7d8a | 66 | State.regs[SP_IDX] = State.sp[State.SM]; /* restore new SP */ |
bc6df23d AC |
67 | if (State.ST && !State.FX) |
68 | { | |
69 | (*d10v_callback->printf_filtered) | |
70 | (d10v_callback, | |
71 | "ERROR at PC 0x%x: ST can only be set when FX is set.\n", | |
72 | PC<<2); | |
73 | State.exception = SIGILL; | |
74 | } | |
19431a02 | 75 | State.cregs[cr] = (val & ~0x4032); |
bc6df23d AC |
76 | break; |
77 | case BPSW_CR: | |
19431a02 AC |
78 | case DPSW_CR: |
79 | State.cregs[cr] = (val & ~0x4032); | |
bc6df23d AC |
80 | break; |
81 | case MOD_S_CR: | |
82 | case MOD_E_CR: | |
83 | State.cregs[cr] = (val & ~0x1); | |
84 | break; | |
85 | default: | |
86 | State.cregs[cr] = val; | |
87 | break; | |
88 | } | |
89 | } | |
90 | ||
91 | reg_t | |
92 | move_from_cr (int cr) | |
93 | { | |
94 | reg_t val = 0; | |
95 | switch (cr) | |
96 | { | |
97 | case PSW_CR: | |
98 | if (State.SM) val |= PSW_SM_BIT; | |
99 | if (State.EA) val |= PSW_EA_BIT; | |
100 | if (State.DB) val |= PSW_DB_BIT; | |
101 | if (State.DM) val |= PSW_DM_BIT; | |
102 | if (State.IE) val |= PSW_IE_BIT; | |
103 | if (State.RP) val |= PSW_RP_BIT; | |
104 | if (State.MD) val |= PSW_MD_BIT; | |
105 | if (State.FX) val |= PSW_FX_BIT; | |
106 | if (State.ST) val |= PSW_ST_BIT; | |
107 | if (State.F0) val |= PSW_F0_BIT; | |
108 | if (State.F1) val |= PSW_F1_BIT; | |
109 | if (State.C) val |= PSW_C_BIT; | |
110 | break; | |
111 | default: | |
112 | val = State.cregs[cr]; | |
113 | break; | |
114 | } | |
115 | return val; | |
116 | } | |
117 | ||
118 | ||
7eebfc62 | 119 | #ifdef DEBUG |
a49a15ad MM |
120 | static void trace_input_func PARAMS ((char *name, |
121 | enum op_types in1, | |
122 | enum op_types in2, | |
123 | enum op_types in3)); | |
87178dbd | 124 | |
a49a15ad MM |
125 | #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0) |
126 | ||
127 | static void trace_output_func PARAMS ((enum op_types result)); | |
128 | ||
129 | #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0) | |
130 | ||
87178dbd | 131 | #ifndef SIZE_INSTRUCTION |
a49a15ad | 132 | #define SIZE_INSTRUCTION 8 |
87178dbd MM |
133 | #endif |
134 | ||
135 | #ifndef SIZE_OPERANDS | |
a49a15ad | 136 | #define SIZE_OPERANDS 18 |
87178dbd MM |
137 | #endif |
138 | ||
139 | #ifndef SIZE_VALUES | |
140 | #define SIZE_VALUES 13 | |
141 | #endif | |
142 | ||
a49a15ad MM |
143 | #ifndef SIZE_LOCATION |
144 | #define SIZE_LOCATION 20 | |
145 | #endif | |
146 | ||
891513ee MM |
147 | #ifndef SIZE_PC |
148 | #define SIZE_PC 6 | |
149 | #endif | |
150 | ||
151 | #ifndef SIZE_LINE_NUMBER | |
152 | #define SIZE_LINE_NUMBER 4 | |
153 | #endif | |
154 | ||
87178dbd | 155 | static void |
a49a15ad | 156 | trace_input_func (name, in1, in2, in3) |
87178dbd MM |
157 | char *name; |
158 | enum op_types in1; | |
159 | enum op_types in2; | |
160 | enum op_types in3; | |
161 | { | |
162 | char *comma; | |
163 | enum op_types in[3]; | |
164 | int i; | |
a49a15ad | 165 | char buf[1024]; |
87178dbd MM |
166 | char *p; |
167 | long tmp; | |
168 | char *type; | |
a49a15ad MM |
169 | const char *filename; |
170 | const char *functionname; | |
171 | unsigned int linenumber; | |
172 | bfd_vma byte_pc; | |
87178dbd | 173 | |
7eebfc62 MM |
174 | if ((d10v_debug & DEBUG_TRACE) == 0) |
175 | return; | |
176 | ||
87178dbd MM |
177 | switch (State.ins_type) |
178 | { | |
179 | default: | |
180 | case INS_UNKNOWN: type = " ?"; break; | |
181 | case INS_LEFT: type = " L"; break; | |
182 | case INS_RIGHT: type = " R"; break; | |
183 | case INS_LEFT_PARALLEL: type = "*L"; break; | |
184 | case INS_RIGHT_PARALLEL: type = "*R"; break; | |
c422ecc7 MH |
185 | case INS_LEFT_COND_TEST: type = "?L"; break; |
186 | case INS_RIGHT_COND_TEST: type = "?R"; break; | |
187 | case INS_LEFT_COND_EXE: type = "&L"; break; | |
188 | case INS_RIGHT_COND_EXE: type = "&R"; break; | |
87178dbd MM |
189 | case INS_LONG: type = " B"; break; |
190 | } | |
191 | ||
a49a15ad MM |
192 | if ((d10v_debug & DEBUG_LINE_NUMBER) == 0) |
193 | (*d10v_callback->printf_filtered) (d10v_callback, | |
f061ddf6 | 194 | "0x%.*x %s: %-*s ", |
891513ee MM |
195 | SIZE_PC, (unsigned)PC, |
196 | type, | |
a49a15ad MM |
197 | SIZE_INSTRUCTION, name); |
198 | ||
199 | else | |
200 | { | |
891513ee | 201 | buf[0] = '\0'; |
b30cdd35 | 202 | byte_pc = decode_pc (); |
a49a15ad MM |
203 | if (text && byte_pc >= text_start && byte_pc < text_end) |
204 | { | |
205 | filename = (const char *)0; | |
206 | functionname = (const char *)0; | |
207 | linenumber = 0; | |
b83093ff | 208 | if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start, |
a49a15ad MM |
209 | &filename, &functionname, &linenumber)) |
210 | { | |
211 | p = buf; | |
212 | if (linenumber) | |
213 | { | |
891513ee | 214 | sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); |
a49a15ad MM |
215 | p += strlen (p); |
216 | } | |
891513ee MM |
217 | else |
218 | { | |
219 | sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); | |
220 | p += SIZE_LINE_NUMBER+2; | |
221 | } | |
a49a15ad MM |
222 | |
223 | if (functionname) | |
224 | { | |
225 | sprintf (p, "%s ", functionname); | |
226 | p += strlen (p); | |
227 | } | |
228 | else if (filename) | |
229 | { | |
c422ecc7 | 230 | char *q = strrchr (filename, '/'); |
a49a15ad MM |
231 | sprintf (p, "%s ", (q) ? q+1 : filename); |
232 | p += strlen (p); | |
233 | } | |
234 | ||
235 | if (*p == ' ') | |
236 | *p = '\0'; | |
237 | } | |
238 | } | |
239 | ||
240 | (*d10v_callback->printf_filtered) (d10v_callback, | |
f061ddf6 | 241 | "0x%.*x %s: %-*.*s %-*s ", |
891513ee MM |
242 | SIZE_PC, (unsigned)PC, |
243 | type, | |
a49a15ad MM |
244 | SIZE_LOCATION, SIZE_LOCATION, buf, |
245 | SIZE_INSTRUCTION, name); | |
246 | } | |
87178dbd MM |
247 | |
248 | in[0] = in1; | |
249 | in[1] = in2; | |
250 | in[2] = in3; | |
251 | comma = ""; | |
252 | p = buf; | |
253 | for (i = 0; i < 3; i++) | |
254 | { | |
255 | switch (in[i]) | |
256 | { | |
257 | case OP_VOID: | |
8831cb01 MM |
258 | case OP_R0: |
259 | case OP_R1: | |
a18cb100 | 260 | case OP_R2: |
8831cb01 | 261 | case OP_R0R1: |
87178dbd MM |
262 | break; |
263 | ||
264 | case OP_REG: | |
265 | case OP_REG_OUTPUT: | |
266 | case OP_DREG: | |
267 | case OP_DREG_OUTPUT: | |
268 | sprintf (p, "%sr%d", comma, OP[i]); | |
269 | p += strlen (p); | |
270 | comma = ","; | |
271 | break; | |
272 | ||
273 | case OP_CR: | |
274 | case OP_CR_OUTPUT: | |
275 | case OP_CR_REVERSE: | |
276 | sprintf (p, "%scr%d", comma, OP[i]); | |
277 | p += strlen (p); | |
278 | comma = ","; | |
279 | break; | |
280 | ||
281 | case OP_ACCUM: | |
282 | case OP_ACCUM_OUTPUT: | |
283 | case OP_ACCUM_REVERSE: | |
284 | sprintf (p, "%sa%d", comma, OP[i]); | |
285 | p += strlen (p); | |
286 | comma = ","; | |
287 | break; | |
288 | ||
289 | case OP_CONSTANT16: | |
290 | sprintf (p, "%s%d", comma, OP[i]); | |
291 | p += strlen (p); | |
292 | comma = ","; | |
293 | break; | |
294 | ||
a18cb100 MM |
295 | case OP_CONSTANT8: |
296 | sprintf (p, "%s%d", comma, SEXT8(OP[i])); | |
297 | p += strlen (p); | |
298 | comma = ","; | |
299 | break; | |
300 | ||
87178dbd MM |
301 | case OP_CONSTANT4: |
302 | sprintf (p, "%s%d", comma, SEXT4(OP[i])); | |
303 | p += strlen (p); | |
304 | comma = ","; | |
305 | break; | |
306 | ||
307 | case OP_CONSTANT3: | |
308 | sprintf (p, "%s%d", comma, SEXT3(OP[i])); | |
309 | p += strlen (p); | |
310 | comma = ","; | |
311 | break; | |
312 | ||
313 | case OP_MEMREF: | |
314 | sprintf (p, "%s@r%d", comma, OP[i]); | |
315 | p += strlen (p); | |
316 | comma = ","; | |
317 | break; | |
318 | ||
319 | case OP_MEMREF2: | |
320 | sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); | |
321 | p += strlen (p); | |
322 | comma = ","; | |
323 | break; | |
324 | ||
325 | case OP_POSTINC: | |
326 | sprintf (p, "%s@r%d+", comma, OP[i]); | |
327 | p += strlen (p); | |
328 | comma = ","; | |
329 | break; | |
330 | ||
331 | case OP_POSTDEC: | |
332 | sprintf (p, "%s@r%d-", comma, OP[i]); | |
333 | p += strlen (p); | |
334 | comma = ","; | |
335 | break; | |
336 | ||
337 | case OP_PREDEC: | |
338 | sprintf (p, "%s@-r%d", comma, OP[i]); | |
339 | p += strlen (p); | |
340 | comma = ","; | |
341 | break; | |
342 | ||
343 | case OP_FLAG: | |
60fc5b72 | 344 | case OP_FLAG_OUTPUT: |
87178dbd MM |
345 | if (OP[i] == 0) |
346 | sprintf (p, "%sf0", comma); | |
347 | ||
348 | else if (OP[i] == 1) | |
349 | sprintf (p, "%sf1", comma); | |
350 | ||
351 | else | |
60fc5b72 | 352 | sprintf (p, "%sc", comma); |
87178dbd MM |
353 | |
354 | p += strlen (p); | |
355 | comma = ","; | |
356 | break; | |
357 | } | |
358 | } | |
359 | ||
7eebfc62 MM |
360 | if ((d10v_debug & DEBUG_VALUES) == 0) |
361 | { | |
362 | *p++ = '\n'; | |
363 | *p = '\0'; | |
364 | (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf); | |
365 | } | |
366 | else | |
367 | { | |
368 | *p = '\0'; | |
369 | (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf); | |
87178dbd | 370 | |
7eebfc62 MM |
371 | p = buf; |
372 | for (i = 0; i < 3; i++) | |
373 | { | |
374 | buf[0] = '\0'; | |
375 | switch (in[i]) | |
376 | { | |
377 | case OP_VOID: | |
378 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, ""); | |
379 | break; | |
380 | ||
381 | case OP_REG_OUTPUT: | |
382 | case OP_DREG_OUTPUT: | |
383 | case OP_CR_OUTPUT: | |
384 | case OP_ACCUM_OUTPUT: | |
60fc5b72 | 385 | case OP_FLAG_OUTPUT: |
7eebfc62 MM |
386 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---"); |
387 | break; | |
388 | ||
389 | case OP_REG: | |
390 | case OP_MEMREF: | |
391 | case OP_POSTDEC: | |
392 | case OP_POSTINC: | |
393 | case OP_PREDEC: | |
394 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
395 | (uint16)State.regs[OP[i]]); | |
396 | break; | |
397 | ||
398 | case OP_DREG: | |
399 | tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1])); | |
400 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); | |
401 | break; | |
402 | ||
403 | case OP_CR: | |
404 | case OP_CR_REVERSE: | |
405 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
406 | (uint16)State.cregs[OP[i]]); | |
407 | break; | |
408 | ||
409 | case OP_ACCUM: | |
410 | case OP_ACCUM_REVERSE: | |
411 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "", | |
412 | ((int)(State.a[OP[i]] >> 32) & 0xff), | |
413 | ((unsigned long)State.a[OP[i]]) & 0xffffffff); | |
414 | break; | |
415 | ||
416 | case OP_CONSTANT16: | |
417 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
418 | (uint16)OP[i]); | |
419 | break; | |
420 | ||
421 | case OP_CONSTANT4: | |
422 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
423 | (uint16)SEXT4(OP[i])); | |
424 | break; | |
425 | ||
a18cb100 MM |
426 | case OP_CONSTANT8: |
427 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
428 | (uint16)SEXT8(OP[i])); | |
429 | break; | |
430 | ||
7eebfc62 MM |
431 | case OP_CONSTANT3: |
432 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
433 | (uint16)SEXT3(OP[i])); | |
434 | break; | |
435 | ||
436 | case OP_FLAG: | |
437 | if (OP[i] == 0) | |
438 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "", | |
439 | State.F0 != 0); | |
440 | ||
441 | else if (OP[i] == 1) | |
442 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "", | |
443 | State.F1 != 0); | |
444 | ||
445 | else | |
446 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "", | |
447 | State.C != 0); | |
448 | ||
449 | break; | |
450 | ||
451 | case OP_MEMREF2: | |
452 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
453 | (uint16)OP[i]); | |
454 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
455 | (uint16)State.regs[OP[++i]]); | |
456 | break; | |
a18cb100 | 457 | |
8831cb01 | 458 | case OP_R0: |
a18cb100 | 459 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", |
8831cb01 | 460 | (uint16)State.regs[0]); |
a18cb100 MM |
461 | break; |
462 | ||
8831cb01 | 463 | case OP_R1: |
a18cb100 | 464 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", |
8831cb01 | 465 | (uint16)State.regs[1]); |
a18cb100 | 466 | break; |
8918b3a7 | 467 | |
8831cb01 | 468 | case OP_R2: |
8918b3a7 | 469 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", |
8831cb01 | 470 | (uint16)State.regs[2]); |
8918b3a7 | 471 | break; |
c422ecc7 | 472 | |
8831cb01 | 473 | case OP_R0R1: |
c422ecc7 | 474 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", |
8831cb01 | 475 | (uint16)State.regs[0]); |
c422ecc7 | 476 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", |
8831cb01 | 477 | (uint16)State.regs[1]); |
c422ecc7 MH |
478 | i++; |
479 | break; | |
7eebfc62 MM |
480 | } |
481 | } | |
482 | } | |
fd435e9f MM |
483 | |
484 | (*d10v_callback->flush_stdout) (d10v_callback); | |
7eebfc62 | 485 | } |
87178dbd | 486 | |
7eebfc62 | 487 | static void |
a49a15ad | 488 | trace_output_func (result) |
7eebfc62 MM |
489 | enum op_types result; |
490 | { | |
491 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
87178dbd | 492 | { |
7eebfc62 | 493 | long tmp; |
87178dbd | 494 | |
7eebfc62 MM |
495 | switch (result) |
496 | { | |
497 | default: | |
498 | putchar ('\n'); | |
87178dbd MM |
499 | break; |
500 | ||
501 | case OP_REG: | |
7eebfc62 MM |
502 | case OP_REG_OUTPUT: |
503 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
504 | (uint16)State.regs[OP[0]], | |
505 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
506 | break; |
507 | ||
508 | case OP_DREG: | |
7eebfc62 MM |
509 | case OP_DREG_OUTPUT: |
510 | tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1])); | |
511 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp, | |
512 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
513 | break; |
514 | ||
515 | case OP_CR: | |
7eebfc62 MM |
516 | case OP_CR_OUTPUT: |
517 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
518 | (uint16)State.cregs[OP[0]], | |
519 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
520 | break; |
521 | ||
7eebfc62 MM |
522 | case OP_CR_REVERSE: |
523 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
524 | (uint16)State.cregs[OP[1]], | |
525 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
526 | break; |
527 | ||
7eebfc62 MM |
528 | case OP_ACCUM: |
529 | case OP_ACCUM_OUTPUT: | |
069398aa | 530 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", |
7eebfc62 MM |
531 | ((int)(State.a[OP[0]] >> 32) & 0xff), |
532 | ((unsigned long)State.a[OP[0]]) & 0xffffffff, | |
533 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
534 | break; |
535 | ||
7eebfc62 | 536 | case OP_ACCUM_REVERSE: |
069398aa | 537 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", |
7eebfc62 MM |
538 | ((int)(State.a[OP[1]] >> 32) & 0xff), |
539 | ((unsigned long)State.a[OP[1]]) & 0xffffffff, | |
540 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd MM |
541 | break; |
542 | ||
543 | case OP_FLAG: | |
60fc5b72 | 544 | case OP_FLAG_OUTPUT: |
7eebfc62 MM |
545 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "", |
546 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
87178dbd | 547 | break; |
8918b3a7 | 548 | |
8831cb01 | 549 | case OP_R0: |
8918b3a7 | 550 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", |
8831cb01 | 551 | (uint16)State.regs[0], |
8918b3a7 MM |
552 | State.F0 != 0, State.F1 != 0, State.C != 0); |
553 | break; | |
554 | ||
8831cb01 | 555 | case OP_R0R1: |
8918b3a7 | 556 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", |
8831cb01 | 557 | (uint16)State.regs[0], (uint16)State.regs[1], |
8918b3a7 MM |
558 | State.F0 != 0, State.F1 != 0, State.C != 0); |
559 | break; | |
87178dbd MM |
560 | } |
561 | } | |
fd435e9f MM |
562 | |
563 | (*d10v_callback->flush_stdout) (d10v_callback); | |
87178dbd MM |
564 | } |
565 | ||
566 | #else | |
567 | #define trace_input(NAME, IN1, IN2, IN3) | |
568 | #define trace_output(RESULT) | |
569 | #endif | |
2934d1c9 MH |
570 | |
571 | /* abs */ | |
572 | void | |
573 | OP_4607 () | |
574 | { | |
87178dbd | 575 | trace_input ("abs", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 MH |
576 | State.F1 = State.F0; |
577 | if ((int16)(State.regs[OP[0]]) < 0) | |
578 | { | |
579 | State.regs[OP[0]] = -(int16)(State.regs[OP[0]]); | |
580 | State.F0 = 1; | |
581 | } | |
582 | else | |
583 | State.F0 = 0; | |
87178dbd | 584 | trace_output (OP_REG); |
2934d1c9 MH |
585 | } |
586 | ||
587 | /* abs */ | |
588 | void | |
589 | OP_5607 () | |
590 | { | |
591 | int64 tmp; | |
592 | ||
87178dbd | 593 | trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID); |
4f425a32 MH |
594 | State.F1 = State.F0; |
595 | State.a[OP[0]] = SEXT40(State.a[OP[0]]); | |
596 | ||
4c38885c | 597 | if (State.a[OP[0]] < 0 ) |
2934d1c9 | 598 | { |
4c38885c | 599 | tmp = -State.a[OP[0]]; |
2934d1c9 MH |
600 | if (State.ST) |
601 | { | |
4c38885c | 602 | if (tmp > MAX32) |
2934d1c9 | 603 | State.a[OP[0]] = MAX32; |
4c38885c | 604 | else if (tmp < MIN32) |
2934d1c9 MH |
605 | State.a[OP[0]] = MIN32; |
606 | else | |
4f425a32 | 607 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
608 | } |
609 | else | |
4f425a32 | 610 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
611 | State.F0 = 1; |
612 | } | |
613 | else | |
614 | State.F0 = 0; | |
87178dbd | 615 | trace_output (OP_ACCUM); |
2934d1c9 MH |
616 | } |
617 | ||
618 | /* add */ | |
619 | void | |
620 | OP_200 () | |
621 | { | |
622 | uint16 tmp = State.regs[OP[0]]; | |
87178dbd | 623 | trace_input ("add", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
624 | State.regs[OP[0]] += State.regs[OP[1]]; |
625 | if ( tmp > State.regs[OP[0]]) | |
626 | State.C = 1; | |
627 | else | |
628 | State.C = 0; | |
87178dbd | 629 | trace_output (OP_REG); |
2934d1c9 MH |
630 | } |
631 | ||
632 | /* add */ | |
633 | void | |
634 | OP_1201 () | |
635 | { | |
4c38885c | 636 | int64 tmp; |
4f425a32 | 637 | tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
87178dbd MM |
638 | |
639 | trace_input ("add", OP_ACCUM, OP_REG, OP_VOID); | |
4c38885c MH |
640 | if (State.ST) |
641 | { | |
642 | if ( tmp > MAX32) | |
643 | State.a[OP[0]] = MAX32; | |
644 | else if ( tmp < MIN32) | |
645 | State.a[OP[0]] = MIN32; | |
646 | else | |
4f425a32 | 647 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
648 | } |
649 | else | |
4f425a32 | 650 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 651 | trace_output (OP_ACCUM); |
2934d1c9 MH |
652 | } |
653 | ||
654 | /* add */ | |
655 | void | |
656 | OP_1203 () | |
657 | { | |
4c38885c | 658 | int64 tmp; |
4f425a32 | 659 | tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]); |
87178dbd MM |
660 | |
661 | trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4c38885c MH |
662 | if (State.ST) |
663 | { | |
664 | if (tmp > MAX32) | |
665 | State.a[OP[0]] = MAX32; | |
666 | else if ( tmp < MIN32) | |
667 | State.a[OP[0]] = MIN32; | |
668 | else | |
4f425a32 | 669 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
670 | } |
671 | else | |
4f425a32 | 672 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 673 | trace_output (OP_ACCUM); |
2934d1c9 MH |
674 | } |
675 | ||
676 | /* add2w */ | |
677 | void | |
678 | OP_1200 () | |
679 | { | |
680 | uint32 tmp; | |
f4b022d3 MM |
681 | uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]; |
682 | uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
87178dbd MM |
683 | |
684 | trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID); | |
f4b022d3 MM |
685 | tmp = a + b; |
686 | State.C = (tmp < a); | |
2934d1c9 MH |
687 | State.regs[OP[0]] = tmp >> 16; |
688 | State.regs[OP[0]+1] = tmp & 0xFFFF; | |
87178dbd | 689 | trace_output (OP_DREG); |
2934d1c9 MH |
690 | } |
691 | ||
692 | /* add3 */ | |
693 | void | |
694 | OP_1000000 () | |
695 | { | |
f4b022d3 MM |
696 | uint16 tmp = State.regs[OP[1]]; |
697 | State.regs[OP[0]] = tmp + OP[2]; | |
87178dbd MM |
698 | |
699 | trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
f4b022d3 | 700 | State.C = (State.regs[OP[0]] < tmp); |
87178dbd | 701 | trace_output (OP_REG); |
2934d1c9 MH |
702 | } |
703 | ||
704 | /* addac3 */ | |
705 | void | |
706 | OP_17000200 () | |
707 | { | |
4c38885c | 708 | int64 tmp; |
4f425a32 | 709 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
87178dbd MM |
710 | |
711 | trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4c38885c MH |
712 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
713 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 714 | trace_output (OP_DREG); |
2934d1c9 MH |
715 | } |
716 | ||
717 | /* addac3 */ | |
718 | void | |
719 | OP_17000202 () | |
720 | { | |
4c38885c | 721 | int64 tmp; |
4f425a32 | 722 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
87178dbd MM |
723 | |
724 | trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4c38885c MH |
725 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
726 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 727 | trace_output (OP_DREG); |
2934d1c9 MH |
728 | } |
729 | ||
730 | /* addac3s */ | |
731 | void | |
732 | OP_17001200 () | |
733 | { | |
4c38885c | 734 | int64 tmp; |
4c38885c | 735 | State.F1 = State.F0; |
87178dbd MM |
736 | |
737 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 | 738 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
4c38885c MH |
739 | if ( tmp > MAX32) |
740 | { | |
741 | State.regs[OP[0]] = 0x7fff; | |
742 | State.regs[OP[0]+1] = 0xffff; | |
743 | State.F0 = 1; | |
744 | } | |
745 | else if (tmp < MIN32) | |
746 | { | |
747 | State.regs[OP[0]] = 0x8000; | |
748 | State.regs[OP[0]+1] = 0; | |
749 | State.F0 = 1; | |
750 | } | |
751 | else | |
752 | { | |
753 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
754 | State.regs[OP[0]+1] = tmp & 0xffff; | |
755 | State.F0 = 0; | |
756 | } | |
87178dbd | 757 | trace_output (OP_DREG); |
2934d1c9 MH |
758 | } |
759 | ||
760 | /* addac3s */ | |
761 | void | |
762 | OP_17001202 () | |
763 | { | |
4c38885c | 764 | int64 tmp; |
4c38885c | 765 | State.F1 = State.F0; |
87178dbd MM |
766 | |
767 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 | 768 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); |
4c38885c MH |
769 | if ( tmp > MAX32) |
770 | { | |
771 | State.regs[OP[0]] = 0x7fff; | |
772 | State.regs[OP[0]+1] = 0xffff; | |
773 | State.F0 = 1; | |
774 | } | |
775 | else if (tmp < MIN32) | |
776 | { | |
777 | State.regs[OP[0]] = 0x8000; | |
778 | State.regs[OP[0]+1] = 0; | |
779 | State.F0 = 1; | |
780 | } | |
781 | else | |
782 | { | |
783 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
784 | State.regs[OP[0]+1] = tmp & 0xffff; | |
785 | State.F0 = 0; | |
786 | } | |
87178dbd | 787 | trace_output (OP_DREG); |
2934d1c9 MH |
788 | } |
789 | ||
790 | /* addi */ | |
791 | void | |
792 | OP_201 () | |
793 | { | |
2254cd90 | 794 | uint tmp = State.regs[OP[0]]; |
4f425a32 MH |
795 | if (OP[1] == 0) |
796 | OP[1] = 16; | |
f4b022d3 | 797 | |
87178dbd | 798 | trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 799 | State.regs[OP[0]] += OP[1]; |
f4b022d3 | 800 | State.C = (State.regs[OP[0]] < tmp); |
87178dbd | 801 | trace_output (OP_REG); |
2934d1c9 MH |
802 | } |
803 | ||
804 | /* and */ | |
805 | void | |
806 | OP_C00 () | |
807 | { | |
87178dbd | 808 | trace_input ("and", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 809 | State.regs[OP[0]] &= State.regs[OP[1]]; |
87178dbd | 810 | trace_output (OP_REG); |
2934d1c9 MH |
811 | } |
812 | ||
813 | /* and3 */ | |
814 | void | |
815 | OP_6000000 () | |
816 | { | |
87178dbd | 817 | trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 818 | State.regs[OP[0]] = State.regs[OP[1]] & OP[2]; |
87178dbd | 819 | trace_output (OP_REG); |
2934d1c9 MH |
820 | } |
821 | ||
822 | /* bclri */ | |
823 | void | |
824 | OP_C01 () | |
825 | { | |
87178dbd | 826 | trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 827 | State.regs[OP[0]] &= ~(0x8000 >> OP[1]); |
87178dbd | 828 | trace_output (OP_REG); |
2934d1c9 MH |
829 | } |
830 | ||
831 | /* bl.s */ | |
832 | void | |
833 | OP_4900 () | |
834 | { | |
8831cb01 | 835 | trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1); |
2934d1c9 | 836 | State.regs[13] = PC+1; |
fd435e9f | 837 | JMP( PC + SEXT8 (OP[0])); |
87178dbd | 838 | trace_output (OP_VOID); |
2934d1c9 MH |
839 | } |
840 | ||
841 | /* bl.l */ | |
842 | void | |
843 | OP_24800000 () | |
844 | { | |
8831cb01 | 845 | trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1); |
2934d1c9 | 846 | State.regs[13] = PC+1; |
fd435e9f | 847 | JMP (PC + OP[0]); |
87178dbd | 848 | trace_output (OP_VOID); |
2934d1c9 MH |
849 | } |
850 | ||
851 | /* bnoti */ | |
852 | void | |
853 | OP_A01 () | |
854 | { | |
87178dbd | 855 | trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 856 | State.regs[OP[0]] ^= 0x8000 >> OP[1]; |
87178dbd | 857 | trace_output (OP_REG); |
2934d1c9 MH |
858 | } |
859 | ||
860 | /* bra.s */ | |
861 | void | |
862 | OP_4800 () | |
863 | { | |
a18cb100 | 864 | trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
fd435e9f | 865 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 866 | trace_output (OP_VOID); |
2934d1c9 MH |
867 | } |
868 | ||
869 | /* bra.l */ | |
870 | void | |
871 | OP_24000000 () | |
872 | { | |
87178dbd | 873 | trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
fd435e9f | 874 | JMP (PC + OP[0]); |
87178dbd | 875 | trace_output (OP_VOID); |
2934d1c9 MH |
876 | } |
877 | ||
878 | /* brf0f.s */ | |
879 | void | |
880 | OP_4A00 () | |
881 | { | |
a18cb100 | 882 | trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
2934d1c9 | 883 | if (State.F0 == 0) |
fd435e9f | 884 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 885 | trace_output (OP_FLAG); |
2934d1c9 MH |
886 | } |
887 | ||
888 | /* brf0f.l */ | |
889 | void | |
890 | OP_25000000 () | |
891 | { | |
87178dbd | 892 | trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 893 | if (State.F0 == 0) |
fd435e9f | 894 | JMP (PC + OP[0]); |
87178dbd | 895 | trace_output (OP_FLAG); |
2934d1c9 MH |
896 | } |
897 | ||
898 | /* brf0t.s */ | |
899 | void | |
900 | OP_4B00 () | |
901 | { | |
a18cb100 | 902 | trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID); |
2934d1c9 | 903 | if (State.F0) |
fd435e9f | 904 | JMP (PC + SEXT8 (OP[0])); |
87178dbd | 905 | trace_output (OP_FLAG); |
2934d1c9 MH |
906 | } |
907 | ||
908 | /* brf0t.l */ | |
909 | void | |
910 | OP_25800000 () | |
911 | { | |
87178dbd | 912 | trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID); |
2934d1c9 | 913 | if (State.F0) |
fd435e9f | 914 | JMP (PC + OP[0]); |
87178dbd | 915 | trace_output (OP_FLAG); |
2934d1c9 MH |
916 | } |
917 | ||
918 | /* bseti */ | |
919 | void | |
920 | OP_801 () | |
921 | { | |
87178dbd | 922 | trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 923 | State.regs[OP[0]] |= 0x8000 >> OP[1]; |
87178dbd | 924 | trace_output (OP_REG); |
2934d1c9 MH |
925 | } |
926 | ||
927 | /* btsti */ | |
928 | void | |
929 | OP_E01 () | |
930 | { | |
87178dbd | 931 | trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
932 | State.F1 = State.F0; |
933 | State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0; | |
87178dbd | 934 | trace_output (OP_FLAG); |
2934d1c9 MH |
935 | } |
936 | ||
937 | /* clrac */ | |
938 | void | |
939 | OP_5601 () | |
940 | { | |
87178dbd | 941 | trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID); |
2934d1c9 | 942 | State.a[OP[0]] = 0; |
87178dbd | 943 | trace_output (OP_ACCUM); |
2934d1c9 MH |
944 | } |
945 | ||
946 | /* cmp */ | |
947 | void | |
948 | OP_600 () | |
949 | { | |
87178dbd | 950 | trace_input ("cmp", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
951 | State.F1 = State.F0; |
952 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0; | |
87178dbd | 953 | trace_output (OP_FLAG); |
2934d1c9 MH |
954 | } |
955 | ||
956 | /* cmp */ | |
957 | void | |
958 | OP_1603 () | |
959 | { | |
87178dbd | 960 | trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c | 961 | State.F1 = State.F0; |
4f425a32 | 962 | State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0; |
87178dbd | 963 | trace_output (OP_FLAG); |
2934d1c9 MH |
964 | } |
965 | ||
966 | /* cmpeq */ | |
967 | void | |
968 | OP_400 () | |
969 | { | |
87178dbd | 970 | trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
971 | State.F1 = State.F0; |
972 | State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 973 | trace_output (OP_FLAG); |
2934d1c9 MH |
974 | } |
975 | ||
976 | /* cmpeq */ | |
977 | void | |
978 | OP_1403 () | |
979 | { | |
87178dbd | 980 | trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID); |
4c38885c | 981 | State.F1 = State.F0; |
fd435e9f | 982 | State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0; |
87178dbd | 983 | trace_output (OP_FLAG); |
2934d1c9 MH |
984 | } |
985 | ||
986 | /* cmpeqi.s */ | |
987 | void | |
988 | OP_401 () | |
989 | { | |
c12f5c67 | 990 | trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 991 | State.F1 = State.F0; |
c12f5c67 | 992 | State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0; |
87178dbd | 993 | trace_output (OP_FLAG); |
2934d1c9 MH |
994 | } |
995 | ||
996 | /* cmpeqi.l */ | |
997 | void | |
998 | OP_2000000 () | |
999 | { | |
87178dbd | 1000 | trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 1001 | State.F1 = State.F0; |
c12f5c67 | 1002 | State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0; |
87178dbd | 1003 | trace_output (OP_FLAG); |
2934d1c9 MH |
1004 | } |
1005 | ||
1006 | /* cmpi.s */ | |
1007 | void | |
1008 | OP_601 () | |
1009 | { | |
87178dbd | 1010 | trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 1011 | State.F1 = State.F0; |
c12f5c67 | 1012 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0; |
87178dbd | 1013 | trace_output (OP_FLAG); |
2934d1c9 MH |
1014 | } |
1015 | ||
1016 | /* cmpi.l */ | |
1017 | void | |
1018 | OP_3000000 () | |
1019 | { | |
87178dbd | 1020 | trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
1021 | State.F1 = State.F0; |
1022 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0; | |
87178dbd | 1023 | trace_output (OP_FLAG); |
2934d1c9 MH |
1024 | } |
1025 | ||
1026 | /* cmpu */ | |
1027 | void | |
1028 | OP_4600 () | |
1029 | { | |
87178dbd | 1030 | trace_input ("cmpu", OP_REG, OP_REG, OP_VOID); |
2934d1c9 MH |
1031 | State.F1 = State.F0; |
1032 | State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0; | |
87178dbd | 1033 | trace_output (OP_FLAG); |
2934d1c9 MH |
1034 | } |
1035 | ||
1036 | /* cmpui */ | |
1037 | void | |
1038 | OP_23000000 () | |
1039 | { | |
87178dbd | 1040 | trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 1041 | State.F1 = State.F0; |
c12f5c67 | 1042 | State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0; |
87178dbd | 1043 | trace_output (OP_FLAG); |
2934d1c9 MH |
1044 | } |
1045 | ||
1046 | /* cpfg */ | |
1047 | void | |
1048 | OP_4E09 () | |
1049 | { | |
1050 | uint8 *src, *dst; | |
2934d1c9 | 1051 | |
60fc5b72 | 1052 | trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); |
2934d1c9 MH |
1053 | if (OP[0] == 0) |
1054 | dst = &State.F0; | |
1055 | else | |
1056 | dst = &State.F1; | |
1057 | ||
1058 | if (OP[1] == 0) | |
1059 | src = &State.F0; | |
1060 | else if (OP[1] == 1) | |
1061 | src = &State.F1; | |
1062 | else | |
1063 | src = &State.C; | |
1064 | ||
1065 | *dst = *src; | |
87178dbd | 1066 | trace_output (OP_FLAG); |
2934d1c9 MH |
1067 | } |
1068 | ||
1069 | /* dbt */ | |
1070 | void | |
1071 | OP_5F20 () | |
1072 | { | |
a49a15ad | 1073 | /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */ |
4f425a32 | 1074 | State.exception = SIGTRAP; |
2934d1c9 MH |
1075 | } |
1076 | ||
1077 | /* divs */ | |
1078 | void | |
1079 | OP_14002800 () | |
1080 | { | |
1081 | uint16 foo, tmp, tmpf; | |
87178dbd MM |
1082 | |
1083 | trace_input ("divs", OP_DREG, OP_REG, OP_VOID); | |
2934d1c9 MH |
1084 | foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15); |
1085 | tmp = (int16)foo - (int16)(State.regs[OP[1]]); | |
1086 | tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0; | |
1087 | State.regs[OP[0]] = (tmpf == 1) ? tmp : foo; | |
1088 | State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf; | |
87178dbd | 1089 | trace_output (OP_DREG); |
2934d1c9 MH |
1090 | } |
1091 | ||
1092 | /* exef0f */ | |
1093 | void | |
1094 | OP_4E04 () | |
1095 | { | |
87178dbd | 1096 | trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1097 | State.exe = (State.F0 == 0); |
87178dbd | 1098 | trace_output (OP_FLAG); |
2934d1c9 MH |
1099 | } |
1100 | ||
1101 | /* exef0t */ | |
1102 | void | |
1103 | OP_4E24 () | |
1104 | { | |
87178dbd | 1105 | trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1106 | State.exe = (State.F0 != 0); |
87178dbd | 1107 | trace_output (OP_FLAG); |
2934d1c9 MH |
1108 | } |
1109 | ||
1110 | /* exef1f */ | |
1111 | void | |
1112 | OP_4E40 () | |
1113 | { | |
87178dbd | 1114 | trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1115 | State.exe = (State.F1 == 0); |
87178dbd | 1116 | trace_output (OP_FLAG); |
2934d1c9 MH |
1117 | } |
1118 | ||
1119 | /* exef1t */ | |
1120 | void | |
1121 | OP_4E42 () | |
1122 | { | |
87178dbd | 1123 | trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1124 | State.exe = (State.F1 != 0); |
87178dbd | 1125 | trace_output (OP_FLAG); |
2934d1c9 MH |
1126 | } |
1127 | ||
1128 | /* exefaf */ | |
1129 | void | |
1130 | OP_4E00 () | |
1131 | { | |
87178dbd | 1132 | trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1133 | State.exe = (State.F0 == 0) & (State.F1 == 0); |
87178dbd | 1134 | trace_output (OP_FLAG); |
2934d1c9 MH |
1135 | } |
1136 | ||
1137 | /* exefat */ | |
1138 | void | |
1139 | OP_4E02 () | |
1140 | { | |
87178dbd | 1141 | trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1142 | State.exe = (State.F0 == 0) & (State.F1 != 0); |
87178dbd | 1143 | trace_output (OP_FLAG); |
2934d1c9 MH |
1144 | } |
1145 | ||
1146 | /* exetaf */ | |
1147 | void | |
1148 | OP_4E20 () | |
1149 | { | |
87178dbd | 1150 | trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1151 | State.exe = (State.F0 != 0) & (State.F1 == 0); |
87178dbd | 1152 | trace_output (OP_FLAG); |
2934d1c9 MH |
1153 | } |
1154 | ||
1155 | /* exetat */ | |
1156 | void | |
1157 | OP_4E22 () | |
1158 | { | |
87178dbd | 1159 | trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID); |
293c76a3 | 1160 | State.exe = (State.F0 != 0) & (State.F1 != 0); |
87178dbd | 1161 | trace_output (OP_FLAG); |
2934d1c9 MH |
1162 | } |
1163 | ||
1164 | /* exp */ | |
1165 | void | |
1166 | OP_15002A00 () | |
1167 | { | |
1168 | uint32 tmp, foo; | |
1169 | int i; | |
1170 | ||
87178dbd | 1171 | trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID); |
4c38885c MH |
1172 | if (((int16)State.regs[OP[1]]) >= 0) |
1173 | tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1]; | |
2934d1c9 | 1174 | else |
4c38885c | 1175 | tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); |
2934d1c9 MH |
1176 | |
1177 | foo = 0x40000000; | |
4c38885c | 1178 | for (i=1;i<17;i++) |
2934d1c9 MH |
1179 | { |
1180 | if (tmp & foo) | |
1181 | { | |
1182 | State.regs[OP[0]] = i-1; | |
87178dbd | 1183 | trace_output (OP_REG); |
2934d1c9 MH |
1184 | return; |
1185 | } | |
4c38885c | 1186 | foo >>= 1; |
2934d1c9 MH |
1187 | } |
1188 | State.regs[OP[0]] = 16; | |
87178dbd | 1189 | trace_output (OP_REG); |
2934d1c9 MH |
1190 | } |
1191 | ||
1192 | /* exp */ | |
1193 | void | |
1194 | OP_15002A02 () | |
1195 | { | |
4c38885c MH |
1196 | int64 tmp, foo; |
1197 | int i; | |
87178dbd MM |
1198 | |
1199 | trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
fd435e9f MM |
1200 | tmp = SEXT40(State.a[OP[1]]); |
1201 | if (tmp < 0) | |
1202 | tmp = ~tmp & MASK40; | |
4c38885c MH |
1203 | |
1204 | foo = 0x4000000000LL; | |
1205 | for (i=1;i<25;i++) | |
1206 | { | |
1207 | if (tmp & foo) | |
1208 | { | |
1209 | State.regs[OP[0]] = i-9; | |
87178dbd | 1210 | trace_output (OP_REG); |
4c38885c MH |
1211 | return; |
1212 | } | |
1213 | foo >>= 1; | |
1214 | } | |
1215 | State.regs[OP[0]] = 16; | |
87178dbd | 1216 | trace_output (OP_REG); |
2934d1c9 MH |
1217 | } |
1218 | ||
1219 | /* jl */ | |
1220 | void | |
1221 | OP_4D00 () | |
1222 | { | |
8831cb01 | 1223 | trace_input ("jl", OP_REG, OP_R0, OP_R1); |
2934d1c9 | 1224 | State.regs[13] = PC+1; |
fd435e9f | 1225 | JMP (State.regs[OP[0]]); |
87178dbd | 1226 | trace_output (OP_VOID); |
2934d1c9 MH |
1227 | } |
1228 | ||
1229 | /* jmp */ | |
1230 | void | |
1231 | OP_4C00 () | |
1232 | { | |
a18cb100 | 1233 | trace_input ("jmp", OP_REG, |
8831cb01 MM |
1234 | (OP[0] == 13) ? OP_R0 : OP_VOID, |
1235 | (OP[0] == 13) ? OP_R1 : OP_VOID); | |
a18cb100 | 1236 | |
fd435e9f | 1237 | JMP (State.regs[OP[0]]); |
87178dbd | 1238 | trace_output (OP_VOID); |
2934d1c9 MH |
1239 | } |
1240 | ||
1241 | /* ld */ | |
1242 | void | |
1243 | OP_30000000 () | |
1244 | { | |
87178dbd | 1245 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1246 | State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); |
87178dbd | 1247 | trace_output (OP_REG); |
2934d1c9 MH |
1248 | } |
1249 | ||
1250 | /* ld */ | |
1251 | void | |
1252 | OP_6401 () | |
1253 | { | |
87178dbd | 1254 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
4c38885c | 1255 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1256 | INC_ADDR(State.regs[OP[1]],-2); |
87178dbd | 1257 | trace_output (OP_REG); |
2934d1c9 MH |
1258 | } |
1259 | ||
1260 | /* ld */ | |
1261 | void | |
1262 | OP_6001 () | |
1263 | { | |
87178dbd | 1264 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
4c38885c | 1265 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
4f425a32 | 1266 | INC_ADDR(State.regs[OP[1]],2); |
87178dbd | 1267 | trace_output (OP_REG); |
2934d1c9 MH |
1268 | } |
1269 | ||
1270 | /* ld */ | |
1271 | void | |
1272 | OP_6000 () | |
1273 | { | |
87178dbd | 1274 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1275 | State.regs[OP[0]] = RW (State.regs[OP[1]]); |
87178dbd | 1276 | trace_output (OP_REG); |
2934d1c9 MH |
1277 | } |
1278 | ||
1279 | /* ld2w */ | |
1280 | void | |
1281 | OP_31000000 () | |
1282 | { | |
8918b3a7 | 1283 | uint16 addr = State.regs[OP[2]]; |
308f64d3 | 1284 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
8918b3a7 MM |
1285 | State.regs[OP[0]] = RW (OP[1] + addr); |
1286 | State.regs[OP[0]+1] = RW (OP[1] + addr + 2); | |
87178dbd | 1287 | trace_output (OP_DREG); |
2934d1c9 MH |
1288 | } |
1289 | ||
1290 | /* ld2w */ | |
1291 | void | |
1292 | OP_6601 () | |
1293 | { | |
8918b3a7 | 1294 | uint16 addr = State.regs[OP[1]]; |
87178dbd | 1295 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); |
8918b3a7 MM |
1296 | State.regs[OP[0]] = RW (addr); |
1297 | State.regs[OP[0]+1] = RW (addr+2); | |
4f425a32 | 1298 | INC_ADDR(State.regs[OP[1]],-4); |
87178dbd | 1299 | trace_output (OP_DREG); |
2934d1c9 MH |
1300 | } |
1301 | ||
1302 | /* ld2w */ | |
1303 | void | |
1304 | OP_6201 () | |
1305 | { | |
8918b3a7 | 1306 | uint16 addr = State.regs[OP[1]]; |
87178dbd | 1307 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); |
8918b3a7 MM |
1308 | State.regs[OP[0]] = RW (addr); |
1309 | State.regs[OP[0]+1] = RW (addr+2); | |
4f425a32 | 1310 | INC_ADDR(State.regs[OP[1]],4); |
8918b3a7 | 1311 | trace_output (OP_DREG); |
2934d1c9 MH |
1312 | } |
1313 | ||
1314 | /* ld2w */ | |
1315 | void | |
1316 | OP_6200 () | |
1317 | { | |
8918b3a7 | 1318 | uint16 addr = State.regs[OP[1]]; |
addb61a5 | 1319 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
8918b3a7 MM |
1320 | State.regs[OP[0]] = RW (addr); |
1321 | State.regs[OP[0]+1] = RW (addr+2); | |
1322 | trace_output (OP_DREG); | |
2934d1c9 MH |
1323 | } |
1324 | ||
1325 | /* ldb */ | |
1326 | void | |
1327 | OP_38000000 () | |
1328 | { | |
87178dbd | 1329 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
c422ecc7 | 1330 | State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]])); |
87178dbd | 1331 | trace_output (OP_REG); |
2934d1c9 MH |
1332 | } |
1333 | ||
1334 | /* ldb */ | |
1335 | void | |
1336 | OP_7000 () | |
1337 | { | |
87178dbd | 1338 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
c422ecc7 | 1339 | State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]])); |
87178dbd | 1340 | trace_output (OP_REG); |
2934d1c9 MH |
1341 | } |
1342 | ||
1343 | /* ldi.s */ | |
1344 | void | |
1345 | OP_4001 () | |
1346 | { | |
87178dbd | 1347 | trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID); |
2934d1c9 | 1348 | State.regs[OP[0]] = SEXT4(OP[1]); |
87178dbd | 1349 | trace_output (OP_REG); |
2934d1c9 MH |
1350 | } |
1351 | ||
1352 | /* ldi.l */ | |
1353 | void | |
1354 | OP_20000000 () | |
1355 | { | |
fd435e9f | 1356 | trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 1357 | State.regs[OP[0]] = OP[1]; |
87178dbd | 1358 | trace_output (OP_REG); |
2934d1c9 MH |
1359 | } |
1360 | ||
1361 | /* ldub */ | |
1362 | void | |
1363 | OP_39000000 () | |
1364 | { | |
87178dbd | 1365 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); |
2934d1c9 | 1366 | State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]); |
87178dbd | 1367 | trace_output (OP_REG); |
2934d1c9 MH |
1368 | } |
1369 | ||
1370 | /* ldub */ | |
1371 | void | |
1372 | OP_7200 () | |
1373 | { | |
87178dbd | 1374 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); |
2934d1c9 | 1375 | State.regs[OP[0]] = RB (State.regs[OP[1]]); |
87178dbd | 1376 | trace_output (OP_REG); |
2934d1c9 MH |
1377 | } |
1378 | ||
1379 | /* mac */ | |
1380 | void | |
1381 | OP_2A00 () | |
1382 | { | |
4c38885c | 1383 | int64 tmp; |
87178dbd MM |
1384 | |
1385 | trace_input ("mac", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 | 1386 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
4c38885c MH |
1387 | |
1388 | if (State.FX) | |
4f425a32 | 1389 | tmp = SEXT40( (tmp << 1) & MASK40); |
4c38885c MH |
1390 | |
1391 | if (State.ST && tmp > MAX32) | |
1392 | tmp = MAX32; | |
1393 | ||
4f425a32 | 1394 | tmp += SEXT40(State.a[OP[0]]); |
4c38885c MH |
1395 | if (State.ST) |
1396 | { | |
1397 | if (tmp > MAX32) | |
1398 | State.a[OP[0]] = MAX32; | |
1399 | else if (tmp < MIN32) | |
1400 | State.a[OP[0]] = MIN32; | |
1401 | else | |
4f425a32 | 1402 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
1403 | } |
1404 | else | |
4f425a32 | 1405 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1406 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1407 | } |
1408 | ||
1409 | /* macsu */ | |
1410 | void | |
1411 | OP_1A00 () | |
1412 | { | |
4f425a32 | 1413 | int64 tmp; |
87178dbd MM |
1414 | |
1415 | trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1416 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1417 | if (State.FX) | |
1418 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1419 | ||
1420 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; | |
87178dbd | 1421 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1422 | } |
1423 | ||
1424 | /* macu */ | |
1425 | void | |
1426 | OP_3A00 () | |
1427 | { | |
ae558075 AC |
1428 | uint64 tmp; |
1429 | uint32 src1; | |
1430 | uint32 src2; | |
87178dbd MM |
1431 | |
1432 | trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); | |
ae558075 AC |
1433 | src1 = (uint16) State.regs[OP[1]]; |
1434 | src2 = (uint16) State.regs[OP[2]]; | |
1435 | tmp = src1 * src2; | |
4f425a32 | 1436 | if (State.FX) |
ae558075 AC |
1437 | tmp = (tmp << 1); |
1438 | State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40; | |
87178dbd | 1439 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1440 | } |
1441 | ||
1442 | /* max */ | |
1443 | void | |
1444 | OP_2600 () | |
1445 | { | |
87178dbd | 1446 | trace_input ("max", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1447 | State.F1 = State.F0; |
ea2155e8 | 1448 | if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1449 | { |
1450 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1451 | State.F0 = 1; | |
1452 | } | |
1453 | else | |
1454 | State.F0 = 0; | |
87178dbd | 1455 | trace_output (OP_REG); |
2934d1c9 MH |
1456 | } |
1457 | ||
1458 | /* max */ | |
1459 | void | |
1460 | OP_3600 () | |
1461 | { | |
4f425a32 | 1462 | int64 tmp; |
87178dbd MM |
1463 | |
1464 | trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1465 | State.F1 = State.F0; |
1466 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1467 | if (tmp > SEXT40(State.a[OP[0]])) | |
1468 | { | |
1469 | State.a[OP[0]] = tmp & MASK40; | |
1470 | State.F0 = 1; | |
1471 | } | |
1472 | else | |
1473 | State.F0 = 0; | |
87178dbd | 1474 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1475 | } |
1476 | ||
1477 | /* max */ | |
1478 | void | |
1479 | OP_3602 () | |
1480 | { | |
87178dbd | 1481 | trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1482 | State.F1 = State.F0; |
1483 | if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]])) | |
1484 | { | |
1485 | State.a[OP[0]] = State.a[OP[1]]; | |
1486 | State.F0 = 1; | |
1487 | } | |
1488 | else | |
1489 | State.F0 = 0; | |
87178dbd | 1490 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1491 | } |
1492 | ||
4f425a32 | 1493 | |
2934d1c9 MH |
1494 | /* min */ |
1495 | void | |
1496 | OP_2601 () | |
1497 | { | |
87178dbd | 1498 | trace_input ("min", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1499 | State.F1 = State.F0; |
ea2155e8 | 1500 | if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]]) |
2934d1c9 MH |
1501 | { |
1502 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1503 | State.F0 = 1; | |
1504 | } | |
1505 | else | |
1506 | State.F0 = 0; | |
87178dbd | 1507 | trace_output (OP_REG); |
2934d1c9 MH |
1508 | } |
1509 | ||
1510 | /* min */ | |
1511 | void | |
1512 | OP_3601 () | |
1513 | { | |
4f425a32 | 1514 | int64 tmp; |
87178dbd MM |
1515 | |
1516 | trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
1517 | State.F1 = State.F0; |
1518 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1519 | if (tmp < SEXT40(State.a[OP[0]])) | |
1520 | { | |
1521 | State.a[OP[0]] = tmp & MASK40; | |
1522 | State.F0 = 1; | |
1523 | } | |
1524 | else | |
1525 | State.F0 = 0; | |
87178dbd | 1526 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1527 | } |
1528 | ||
1529 | /* min */ | |
1530 | void | |
1531 | OP_3603 () | |
1532 | { | |
87178dbd | 1533 | trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID); |
4f425a32 MH |
1534 | State.F1 = State.F0; |
1535 | if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]])) | |
1536 | { | |
1537 | State.a[OP[0]] = State.a[OP[1]]; | |
1538 | State.F0 = 1; | |
1539 | } | |
1540 | else | |
1541 | State.F0 = 0; | |
87178dbd | 1542 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1543 | } |
1544 | ||
1545 | /* msb */ | |
1546 | void | |
1547 | OP_2800 () | |
1548 | { | |
4f425a32 | 1549 | int64 tmp; |
87178dbd MM |
1550 | |
1551 | trace_input ("msb", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1552 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1553 | ||
1554 | if (State.FX) | |
1555 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1556 | ||
1557 | if (State.ST && tmp > MAX32) | |
1558 | tmp = MAX32; | |
1559 | ||
1560 | tmp = SEXT40(State.a[OP[0]]) - tmp; | |
1561 | if (State.ST) | |
1562 | { | |
1563 | if (tmp > MAX32) | |
1564 | State.a[OP[0]] = MAX32; | |
1565 | else if (tmp < MIN32) | |
1566 | State.a[OP[0]] = MIN32; | |
1567 | else | |
1568 | State.a[OP[0]] = tmp & MASK40; | |
1569 | } | |
1570 | else | |
1571 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1572 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1573 | } |
1574 | ||
1575 | /* msbsu */ | |
1576 | void | |
1577 | OP_1800 () | |
1578 | { | |
4f425a32 | 1579 | int64 tmp; |
87178dbd MM |
1580 | |
1581 | trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG); | |
4f425a32 MH |
1582 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); |
1583 | if (State.FX) | |
1584 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1585 | ||
1586 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; | |
87178dbd | 1587 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1588 | } |
1589 | ||
1590 | /* msbu */ | |
1591 | void | |
1592 | OP_3800 () | |
1593 | { | |
d294a657 AC |
1594 | uint64 tmp; |
1595 | uint32 src1; | |
1596 | uint32 src2; | |
87178dbd MM |
1597 | |
1598 | trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); | |
d294a657 AC |
1599 | src1 = (uint16) State.regs[OP[1]]; |
1600 | src2 = (uint16) State.regs[OP[2]]; | |
1601 | tmp = src1 * src2; | |
4f425a32 | 1602 | if (State.FX) |
d294a657 | 1603 | tmp = (tmp << 1); |
4f425a32 | 1604 | |
d294a657 | 1605 | State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40; |
87178dbd | 1606 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1607 | } |
1608 | ||
1609 | /* mul */ | |
1610 | void | |
1611 | OP_2E00 () | |
1612 | { | |
87178dbd | 1613 | trace_input ("mul", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1614 | State.regs[OP[0]] *= State.regs[OP[1]]; |
87178dbd | 1615 | trace_output (OP_REG); |
2934d1c9 MH |
1616 | } |
1617 | ||
1618 | /* mulx */ | |
1619 | void | |
1620 | OP_2C00 () | |
1621 | { | |
4f425a32 | 1622 | int64 tmp; |
87178dbd MM |
1623 | |
1624 | trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1625 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); |
1626 | ||
1627 | if (State.FX) | |
1628 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1629 | ||
1630 | if (State.ST && tmp > MAX32) | |
1631 | State.a[OP[0]] = MAX32; | |
1632 | else | |
1633 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1634 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1635 | } |
1636 | ||
1637 | /* mulxsu */ | |
1638 | void | |
1639 | OP_1C00 () | |
1640 | { | |
4f425a32 | 1641 | int64 tmp; |
87178dbd MM |
1642 | |
1643 | trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
4f425a32 MH |
1644 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]); |
1645 | ||
1646 | if (State.FX) | |
1647 | tmp <<= 1; | |
1648 | ||
1649 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1650 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1651 | } |
1652 | ||
1653 | /* mulxu */ | |
1654 | void | |
1655 | OP_3C00 () | |
1656 | { | |
9420287e AC |
1657 | uint64 tmp; |
1658 | uint32 src1; | |
1659 | uint32 src2; | |
87178dbd MM |
1660 | |
1661 | trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
9420287e AC |
1662 | src1 = (uint16) State.regs[OP[1]]; |
1663 | src2 = (uint16) State.regs[OP[2]]; | |
1664 | tmp = src1 * src2; | |
4f425a32 MH |
1665 | if (State.FX) |
1666 | tmp <<= 1; | |
1667 | ||
1668 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 1669 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1670 | } |
1671 | ||
1672 | /* mv */ | |
1673 | void | |
1674 | OP_4000 () | |
1675 | { | |
87178dbd | 1676 | trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1677 | State.regs[OP[0]] = State.regs[OP[1]]; |
87178dbd | 1678 | trace_output (OP_REG); |
2934d1c9 MH |
1679 | } |
1680 | ||
1681 | /* mv2w */ | |
1682 | void | |
1683 | OP_5000 () | |
1684 | { | |
87178dbd | 1685 | trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID); |
2934d1c9 MH |
1686 | State.regs[OP[0]] = State.regs[OP[1]]; |
1687 | State.regs[OP[0]+1] = State.regs[OP[1]+1]; | |
87178dbd | 1688 | trace_output (OP_DREG); |
2934d1c9 MH |
1689 | } |
1690 | ||
1691 | /* mv2wfac */ | |
1692 | void | |
1693 | OP_3E00 () | |
1694 | { | |
87178dbd | 1695 | trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1696 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
1697 | State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff; | |
87178dbd | 1698 | trace_output (OP_DREG); |
2934d1c9 MH |
1699 | } |
1700 | ||
1701 | /* mv2wtac */ | |
1702 | void | |
1703 | OP_3E01 () | |
1704 | { | |
fd435e9f | 1705 | trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID); |
4f425a32 | 1706 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40; |
fd435e9f | 1707 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1708 | } |
1709 | ||
1710 | /* mvac */ | |
1711 | void | |
1712 | OP_3E03 () | |
1713 | { | |
87178dbd | 1714 | trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1715 | State.a[OP[0]] = State.a[OP[1]]; |
87178dbd | 1716 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1717 | } |
1718 | ||
1719 | /* mvb */ | |
1720 | void | |
1721 | OP_5400 () | |
1722 | { | |
87178dbd | 1723 | trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1724 | State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff); |
87178dbd | 1725 | trace_output (OP_REG); |
2934d1c9 MH |
1726 | } |
1727 | ||
1728 | /* mvf0f */ | |
1729 | void | |
1730 | OP_4400 () | |
1731 | { | |
87178dbd | 1732 | trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1733 | if (State.F0 == 0) |
1734 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1735 | trace_output (OP_REG); |
2934d1c9 MH |
1736 | } |
1737 | ||
1738 | /* mvf0t */ | |
1739 | void | |
1740 | OP_4401 () | |
1741 | { | |
87178dbd | 1742 | trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 MH |
1743 | if (State.F0) |
1744 | State.regs[OP[0]] = State.regs[OP[1]]; | |
87178dbd | 1745 | trace_output (OP_REG); |
2934d1c9 MH |
1746 | } |
1747 | ||
1748 | /* mvfacg */ | |
1749 | void | |
1750 | OP_1E04 () | |
1751 | { | |
87178dbd | 1752 | trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1753 | State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff; |
87178dbd | 1754 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1755 | } |
1756 | ||
1757 | /* mvfachi */ | |
1758 | void | |
1759 | OP_1E00 () | |
1760 | { | |
87178dbd | 1761 | trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1762 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; |
87178dbd | 1763 | trace_output (OP_REG); |
2934d1c9 MH |
1764 | } |
1765 | ||
1766 | /* mvfaclo */ | |
1767 | void | |
1768 | OP_1E02 () | |
1769 | { | |
87178dbd | 1770 | trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); |
2934d1c9 | 1771 | State.regs[OP[0]] = State.a[OP[1]] & 0xffff; |
87178dbd | 1772 | trace_output (OP_REG); |
2934d1c9 MH |
1773 | } |
1774 | ||
1775 | /* mvfc */ | |
1776 | void | |
1777 | OP_5200 () | |
1778 | { | |
87178dbd | 1779 | trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID); |
bc6df23d | 1780 | State.regs[OP[0]] = move_from_cr (OP[1]); |
87178dbd | 1781 | trace_output (OP_REG); |
2934d1c9 MH |
1782 | } |
1783 | ||
1784 | /* mvtacg */ | |
1785 | void | |
1786 | OP_1E41 () | |
1787 | { | |
87178dbd | 1788 | trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID); |
2934d1c9 MH |
1789 | State.a[OP[1]] &= MASK32; |
1790 | State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32; | |
87178dbd | 1791 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1792 | } |
1793 | ||
1794 | /* mvtachi */ | |
1795 | void | |
1796 | OP_1E01 () | |
1797 | { | |
1798 | uint16 tmp; | |
87178dbd MM |
1799 | |
1800 | trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID); | |
2934d1c9 | 1801 | tmp = State.a[OP[1]] & 0xffff; |
4f425a32 | 1802 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40; |
87178dbd | 1803 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1804 | } |
1805 | ||
1806 | /* mvtaclo */ | |
1807 | void | |
1808 | OP_1E21 () | |
1809 | { | |
87178dbd | 1810 | trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID); |
4f425a32 | 1811 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40; |
87178dbd | 1812 | trace_output (OP_ACCUM_REVERSE); |
2934d1c9 MH |
1813 | } |
1814 | ||
1815 | /* mvtc */ | |
1816 | void | |
1817 | OP_5600 () | |
1818 | { | |
87178dbd | 1819 | trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID); |
bc6df23d | 1820 | move_to_cr (OP[1], State.regs[OP[0]]); |
87178dbd | 1821 | trace_output (OP_CR_REVERSE); |
2934d1c9 MH |
1822 | } |
1823 | ||
1824 | /* mvub */ | |
1825 | void | |
1826 | OP_5401 () | |
1827 | { | |
87178dbd | 1828 | trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID); |
2934d1c9 | 1829 | State.regs[OP[0]] = State.regs[OP[1]] & 0xff; |
87178dbd | 1830 | trace_output (OP_REG); |
2934d1c9 MH |
1831 | } |
1832 | ||
1833 | /* neg */ | |
1834 | void | |
1835 | OP_4605 () | |
1836 | { | |
87178dbd | 1837 | trace_input ("neg", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1838 | State.regs[OP[0]] = 0 - State.regs[OP[0]]; |
87178dbd | 1839 | trace_output (OP_REG); |
2934d1c9 MH |
1840 | } |
1841 | ||
1842 | /* neg */ | |
1843 | void | |
1844 | OP_5605 () | |
1845 | { | |
1846 | int64 tmp; | |
87178dbd MM |
1847 | |
1848 | trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID); | |
4f425a32 | 1849 | tmp = -SEXT40(State.a[OP[0]]); |
2934d1c9 MH |
1850 | if (State.ST) |
1851 | { | |
4c38885c | 1852 | if ( tmp > MAX32) |
2934d1c9 | 1853 | State.a[OP[0]] = MAX32; |
4c38885c | 1854 | else if (tmp < MIN32) |
2934d1c9 MH |
1855 | State.a[OP[0]] = MIN32; |
1856 | else | |
4f425a32 | 1857 | State.a[OP[0]] = tmp & MASK40; |
2934d1c9 MH |
1858 | } |
1859 | else | |
4f425a32 | 1860 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 1861 | trace_output (OP_ACCUM); |
2934d1c9 MH |
1862 | } |
1863 | ||
1864 | ||
1865 | /* nop */ | |
1866 | void | |
1867 | OP_5E00 () | |
1868 | { | |
87178dbd | 1869 | trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); |
7eebfc62 | 1870 | |
c422ecc7 MH |
1871 | ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ |
1872 | switch (State.ins_type) | |
1873 | { | |
1874 | default: | |
1875 | ins_type_counters[ (int)INS_UNKNOWN ]++; | |
1876 | break; | |
1877 | ||
1878 | case INS_LEFT_PARALLEL: | |
1879 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1880 | ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--; | |
1881 | ins_type_counters[ (int)INS_RIGHT ]++; | |
1882 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1883 | break; | |
1884 | ||
1885 | case INS_LEFT: | |
1886 | case INS_LEFT_COND_EXE: | |
1887 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1888 | break; | |
1889 | ||
1890 | case INS_RIGHT_PARALLEL: | |
1891 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1892 | ins_type_counters[ (int)INS_LEFT_PARALLEL ]--; | |
1893 | ins_type_counters[ (int)INS_LEFT ]++; | |
1894 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1895 | break; | |
1896 | ||
1897 | case INS_RIGHT: | |
1898 | case INS_RIGHT_COND_EXE: | |
1899 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1900 | break; | |
1901 | } | |
1902 | ||
1903 | trace_output (OP_VOID); | |
2934d1c9 MH |
1904 | } |
1905 | ||
1906 | /* not */ | |
1907 | void | |
1908 | OP_4603 () | |
1909 | { | |
87178dbd | 1910 | trace_input ("not", OP_REG, OP_VOID, OP_VOID); |
2934d1c9 | 1911 | State.regs[OP[0]] = ~(State.regs[OP[0]]); |
87178dbd | 1912 | trace_output (OP_REG); |
2934d1c9 MH |
1913 | } |
1914 | ||
1915 | /* or */ | |
1916 | void | |
1917 | OP_800 () | |
1918 | { | |
87178dbd | 1919 | trace_input ("or", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 1920 | State.regs[OP[0]] |= State.regs[OP[1]]; |
87178dbd | 1921 | trace_output (OP_REG); |
2934d1c9 MH |
1922 | } |
1923 | ||
1924 | /* or3 */ | |
1925 | void | |
1926 | OP_4000000 () | |
1927 | { | |
87178dbd | 1928 | trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
2934d1c9 | 1929 | State.regs[OP[0]] = State.regs[OP[1]] | OP[2]; |
87178dbd | 1930 | trace_output (OP_REG); |
2934d1c9 MH |
1931 | } |
1932 | ||
1933 | /* rac */ | |
1934 | void | |
1935 | OP_5201 () | |
1936 | { | |
1937 | int64 tmp; | |
1938 | int shift = SEXT3 (OP[2]); | |
87178dbd MM |
1939 | |
1940 | trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
166acb9f MH |
1941 | if (OP[1] != 0) |
1942 | { | |
7eebfc62 MM |
1943 | (*d10v_callback->printf_filtered) (d10v_callback, |
1944 | "ERROR at PC 0x%x: instruction only valid for A0\n", | |
1945 | PC<<2); | |
166acb9f MH |
1946 | State.exception = SIGILL; |
1947 | } | |
1948 | ||
2934d1c9 | 1949 | State.F1 = State.F0; |
aa49c64f | 1950 | tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff)); |
2934d1c9 | 1951 | if (shift >=0) |
aa49c64f | 1952 | tmp <<= shift; |
2934d1c9 | 1953 | else |
aa49c64f AC |
1954 | tmp >>= -shift; |
1955 | tmp += 0x8000; | |
1956 | tmp >>= 16; /* look at bits 0:43 */ | |
1957 | if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) | |
2934d1c9 MH |
1958 | { |
1959 | State.regs[OP[0]] = 0x7fff; | |
1960 | State.regs[OP[0]+1] = 0xffff; | |
1961 | State.F0 = 1; | |
1962 | } | |
aa49c64f | 1963 | else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) |
2934d1c9 MH |
1964 | { |
1965 | State.regs[OP[0]] = 0x8000; | |
1966 | State.regs[OP[0]+1] = 0; | |
1967 | State.F0 = 1; | |
1968 | } | |
1969 | else | |
1970 | { | |
1971 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1972 | State.regs[OP[0]+1] = tmp & 0xffff; | |
1973 | State.F0 = 0; | |
1974 | } | |
87178dbd | 1975 | trace_output (OP_DREG); |
2934d1c9 MH |
1976 | } |
1977 | ||
1978 | /* rachi */ | |
1979 | void | |
1980 | OP_4201 () | |
1981 | { | |
70ee56c5 | 1982 | signed64 tmp; |
4c38885c | 1983 | int shift = SEXT3 (OP[2]); |
87178dbd MM |
1984 | |
1985 | trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
4c38885c MH |
1986 | State.F1 = State.F0; |
1987 | if (shift >=0) | |
70ee56c5 | 1988 | tmp = SEXT40 (State.a[OP[1]]) << shift; |
4c38885c | 1989 | else |
70ee56c5 | 1990 | tmp = SEXT40 (State.a[OP[1]]) >> -shift; |
4c38885c | 1991 | tmp += 0x8000; |
63a91cfb | 1992 | |
70ee56c5 | 1993 | if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) |
4c38885c MH |
1994 | { |
1995 | State.regs[OP[0]] = 0x7fff; | |
1996 | State.F0 = 1; | |
1997 | } | |
70ee56c5 | 1998 | else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) |
4c38885c MH |
1999 | { |
2000 | State.regs[OP[0]] = 0x8000; | |
2001 | State.F0 = 1; | |
2002 | } | |
2003 | else | |
2004 | { | |
2005 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2006 | State.F0 = 0; | |
2007 | } | |
87178dbd | 2008 | trace_output (OP_REG); |
2934d1c9 MH |
2009 | } |
2010 | ||
2011 | /* rep */ | |
2012 | void | |
2013 | OP_27000000 () | |
2014 | { | |
87178dbd | 2015 | trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
2016 | RPT_S = PC + 1; |
2017 | RPT_E = PC + OP[1]; | |
2018 | RPT_C = State.regs[OP[0]]; | |
2019 | State.RP = 1; | |
2020 | if (RPT_C == 0) | |
2021 | { | |
7eebfc62 | 2022 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n"); |
4f425a32 | 2023 | State.exception = SIGILL; |
2934d1c9 | 2024 | } |
4c38885c MH |
2025 | if (OP[1] < 4) |
2026 | { | |
7eebfc62 | 2027 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n"); |
4f425a32 | 2028 | State.exception = SIGILL; |
4c38885c | 2029 | } |
87178dbd | 2030 | trace_output (OP_VOID); |
2934d1c9 MH |
2031 | } |
2032 | ||
2033 | /* repi */ | |
2034 | void | |
2035 | OP_2F000000 () | |
2036 | { | |
87178dbd | 2037 | trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID); |
2934d1c9 MH |
2038 | RPT_S = PC + 1; |
2039 | RPT_E = PC + OP[1]; | |
2040 | RPT_C = OP[0]; | |
2041 | State.RP = 1; | |
2042 | if (RPT_C == 0) | |
2043 | { | |
7eebfc62 | 2044 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n"); |
4f425a32 | 2045 | State.exception = SIGILL; |
4c38885c MH |
2046 | } |
2047 | if (OP[1] < 4) | |
2048 | { | |
7eebfc62 | 2049 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n"); |
4f425a32 | 2050 | State.exception = SIGILL; |
2934d1c9 | 2051 | } |
87178dbd | 2052 | trace_output (OP_VOID); |
2934d1c9 MH |
2053 | } |
2054 | ||
2055 | /* rtd */ | |
2056 | void | |
2057 | OP_5F60 () | |
2058 | { | |
7eebfc62 | 2059 | d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n"); |
87178dbd | 2060 | State.exception = SIGILL; |
2934d1c9 MH |
2061 | } |
2062 | ||
2063 | /* rte */ | |
2064 | void | |
2065 | OP_5F40 () | |
2066 | { | |
87178dbd | 2067 | trace_input ("rte", OP_VOID, OP_VOID, OP_VOID); |
bc6df23d | 2068 | move_to_cr (PSW_CR, BPSW); |
8831cb01 | 2069 | JMP(BPC); |
87178dbd | 2070 | trace_output (OP_VOID); |
2934d1c9 MH |
2071 | } |
2072 | ||
2073 | /* sadd */ | |
2074 | void | |
2075 | OP_1223 () | |
2076 | { | |
4c38885c | 2077 | int64 tmp; |
87178dbd MM |
2078 | |
2079 | trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 | 2080 | tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16); |
4c38885c MH |
2081 | if (State.ST) |
2082 | { | |
2083 | if (tmp > MAX32) | |
2084 | State.a[OP[0]] = MAX32; | |
2085 | else if (tmp < MIN32) | |
2086 | State.a[OP[0]] = MIN32; | |
2087 | else | |
4f425a32 | 2088 | State.a[OP[0]] = tmp & MASK40; |
4c38885c MH |
2089 | } |
2090 | else | |
4f425a32 | 2091 | State.a[OP[0]] = tmp & MASK40; |
87178dbd | 2092 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2093 | } |
2094 | ||
2095 | /* setf0f */ | |
2096 | void | |
2097 | OP_4611 () | |
2098 | { | |
87178dbd | 2099 | trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 2100 | State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0; |
87178dbd | 2101 | trace_output (OP_REG); |
2934d1c9 MH |
2102 | } |
2103 | ||
2104 | /* setf0t */ | |
2105 | void | |
2106 | OP_4613 () | |
2107 | { | |
87178dbd | 2108 | trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID); |
4c38885c | 2109 | State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0; |
87178dbd | 2110 | trace_output (OP_REG); |
2934d1c9 MH |
2111 | } |
2112 | ||
2113 | /* sleep */ | |
2114 | void | |
2115 | OP_5FC0 () | |
2116 | { | |
87178dbd | 2117 | trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 2118 | State.IE = 1; |
87178dbd | 2119 | trace_output (OP_VOID); |
2934d1c9 MH |
2120 | } |
2121 | ||
2122 | /* sll */ | |
2123 | void | |
2124 | OP_2200 () | |
2125 | { | |
87178dbd | 2126 | trace_input ("sll", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2127 | State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf); |
87178dbd | 2128 | trace_output (OP_REG); |
2934d1c9 MH |
2129 | } |
2130 | ||
2131 | /* sll */ | |
2132 | void | |
2133 | OP_3200 () | |
2134 | { | |
4c38885c | 2135 | int64 tmp; |
87178dbd | 2136 | trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2137 | if ((State.regs[OP[1]] & 31) <= 16) |
4c38885c | 2138 | tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31); |
069398aa MM |
2139 | else |
2140 | { | |
2141 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2142 | State.exception = SIGILL; | |
2143 | return; | |
2144 | } | |
4c38885c MH |
2145 | |
2146 | if (State.ST) | |
2147 | { | |
2148 | if (tmp > MAX32) | |
2149 | State.a[OP[0]] = MAX32; | |
2150 | else if (tmp < 0xffffff80000000LL) | |
2151 | State.a[OP[0]] = MIN32; | |
2152 | else | |
2153 | State.a[OP[0]] = tmp & MASK40; | |
2154 | } | |
2155 | else | |
2156 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 2157 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2158 | } |
2159 | ||
2160 | /* slli */ | |
2161 | void | |
2162 | OP_2201 () | |
2163 | { | |
87178dbd | 2164 | trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2165 | State.regs[OP[0]] <<= OP[1]; |
87178dbd | 2166 | trace_output (OP_REG); |
2934d1c9 MH |
2167 | } |
2168 | ||
2169 | /* slli */ | |
2170 | void | |
2171 | OP_3201 () | |
2172 | { | |
4c38885c | 2173 | int64 tmp; |
4f425a32 MH |
2174 | |
2175 | if (OP[1] == 0) | |
2176 | OP[1] = 16; | |
4f425a32 | 2177 | |
87178dbd | 2178 | trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID); |
4f425a32 | 2179 | tmp = SEXT40(State.a[OP[0]]) << OP[1]; |
4c38885c MH |
2180 | |
2181 | if (State.ST) | |
2182 | { | |
2183 | if (tmp > MAX32) | |
2184 | State.a[OP[0]] = MAX32; | |
2185 | else if (tmp < 0xffffff80000000LL) | |
2186 | State.a[OP[0]] = MIN32; | |
2187 | else | |
2188 | State.a[OP[0]] = tmp & MASK40; | |
2189 | } | |
2190 | else | |
2191 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd | 2192 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2193 | } |
2194 | ||
2195 | /* slx */ | |
2196 | void | |
2197 | OP_460B () | |
2198 | { | |
87178dbd | 2199 | trace_input ("slx", OP_REG, OP_FLAG, OP_VOID); |
2934d1c9 | 2200 | State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0; |
87178dbd | 2201 | trace_output (OP_REG); |
2934d1c9 MH |
2202 | } |
2203 | ||
2204 | /* sra */ | |
2205 | void | |
2206 | OP_2400 () | |
2207 | { | |
87178dbd | 2208 | trace_input ("sra", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2209 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf); |
87178dbd | 2210 | trace_output (OP_REG); |
2934d1c9 MH |
2211 | } |
2212 | ||
2213 | /* sra */ | |
2214 | void | |
2215 | OP_3400 () | |
2216 | { | |
87178dbd | 2217 | trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2218 | if ((State.regs[OP[1]] & 31) <= 16) |
fd435e9f | 2219 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40; |
069398aa MM |
2220 | else |
2221 | { | |
2222 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2223 | State.exception = SIGILL; | |
2224 | return; | |
2225 | } | |
2226 | ||
87178dbd | 2227 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2228 | } |
2229 | ||
2230 | /* srai */ | |
2231 | void | |
2232 | OP_2401 () | |
2233 | { | |
87178dbd | 2234 | trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2235 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1]; |
87178dbd | 2236 | trace_output (OP_REG); |
2934d1c9 MH |
2237 | } |
2238 | ||
2239 | /* srai */ | |
2240 | void | |
2241 | OP_3401 () | |
2242 | { | |
4f425a32 MH |
2243 | if (OP[1] == 0) |
2244 | OP[1] = 16; | |
87178dbd MM |
2245 | |
2246 | trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
fd435e9f | 2247 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40; |
87178dbd | 2248 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2249 | } |
2250 | ||
2251 | /* srl */ | |
2252 | void | |
2253 | OP_2000 () | |
2254 | { | |
87178dbd | 2255 | trace_input ("srl", OP_REG, OP_REG, OP_VOID); |
2934d1c9 | 2256 | State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf); |
87178dbd | 2257 | trace_output (OP_REG); |
2934d1c9 MH |
2258 | } |
2259 | ||
2260 | /* srl */ | |
2261 | void | |
2262 | OP_3000 () | |
2263 | { | |
87178dbd | 2264 | trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); |
069398aa | 2265 | if ((State.regs[OP[1]] & 31) <= 16) |
fd435e9f | 2266 | State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31)); |
069398aa MM |
2267 | else |
2268 | { | |
2269 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2270 | State.exception = SIGILL; | |
2271 | return; | |
2272 | } | |
2273 | ||
87178dbd | 2274 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2275 | } |
2276 | ||
2277 | /* srli */ | |
2278 | void | |
2279 | OP_2001 () | |
2280 | { | |
87178dbd | 2281 | trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID); |
2934d1c9 | 2282 | State.regs[OP[0]] >>= OP[1]; |
87178dbd | 2283 | trace_output (OP_REG); |
2934d1c9 MH |
2284 | } |
2285 | ||
2286 | /* srli */ | |
2287 | void | |
2288 | OP_3001 () | |
2289 | { | |
4f425a32 MH |
2290 | if (OP[1] == 0) |
2291 | OP[1] = 16; | |
87178dbd MM |
2292 | |
2293 | trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
fd435e9f | 2294 | State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1]; |
87178dbd | 2295 | trace_output (OP_ACCUM); |
2934d1c9 MH |
2296 | } |
2297 | ||
2298 | /* srx */ | |
2299 | void | |
2300 | OP_4609 () | |
2301 | { | |
2302 | uint16 tmp; | |
87178dbd MM |
2303 | |
2304 | trace_input ("srx", OP_REG, OP_FLAG, OP_VOID); | |
2934d1c9 MH |
2305 | tmp = State.F0 << 15; |
2306 | State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp; | |
87178dbd | 2307 | trace_output (OP_REG); |
2934d1c9 MH |
2308 | } |
2309 | ||
2310 | /* st */ | |
2311 | void | |
2312 | OP_34000000 () | |
2313 | { | |
87178dbd | 2314 | trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); |
2934d1c9 | 2315 | SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]); |
87178dbd | 2316 | trace_output (OP_VOID); |
2934d1c9 MH |
2317 | } |
2318 | ||
2319 | /* st */ | |
2320 | void | |
2321 | OP_6800 () | |
2322 | { | |
87178dbd | 2323 | trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); |
2934d1c9 | 2324 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2325 | trace_output (OP_VOID); |
2934d1c9 MH |
2326 | } |
2327 | ||
2328 | /* st */ | |
2329 | void | |
2330 | OP_6C1F () | |
2331 | { | |
87178dbd | 2332 | trace_input ("st", OP_REG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2333 | if ( OP[1] != 15 ) |
2334 | { | |
7eebfc62 | 2335 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2336 | State.exception = SIGILL; |
2337 | return; | |
4c38885c MH |
2338 | } |
2339 | State.regs[OP[1]] -= 2; | |
2340 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
87178dbd | 2341 | trace_output (OP_VOID); |
2934d1c9 MH |
2342 | } |
2343 | ||
2344 | /* st */ | |
2345 | void | |
2346 | OP_6801 () | |
2347 | { | |
87178dbd | 2348 | trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); |
4c38885c | 2349 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2350 | INC_ADDR (State.regs[OP[1]],2); |
87178dbd | 2351 | trace_output (OP_VOID); |
2934d1c9 MH |
2352 | } |
2353 | ||
2354 | /* st */ | |
2355 | void | |
2356 | OP_6C01 () | |
2357 | { | |
87178dbd | 2358 | trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); |
fd435e9f MM |
2359 | if ( OP[1] == 15 ) |
2360 | { | |
2361 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2362 | State.exception = SIGILL; | |
2363 | return; | |
2364 | } | |
4c38885c | 2365 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
4f425a32 | 2366 | INC_ADDR (State.regs[OP[1]],-2); |
87178dbd | 2367 | trace_output (OP_VOID); |
2934d1c9 MH |
2368 | } |
2369 | ||
2370 | /* st2w */ | |
2371 | void | |
2372 | OP_35000000 () | |
2373 | { | |
87178dbd | 2374 | trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); |
4f425a32 MH |
2375 | SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
2376 | SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]); | |
87178dbd | 2377 | trace_output (OP_VOID); |
2934d1c9 MH |
2378 | } |
2379 | ||
2380 | /* st2w */ | |
2381 | void | |
2382 | OP_6A00 () | |
2383 | { | |
a18cb100 | 2384 | trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID); |
4c38885c MH |
2385 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2386 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2387 | trace_output (OP_VOID); |
2934d1c9 MH |
2388 | } |
2389 | ||
2390 | /* st2w */ | |
2391 | void | |
2392 | OP_6E1F () | |
2393 | { | |
a18cb100 | 2394 | trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID); |
4c38885c MH |
2395 | if ( OP[1] != 15 ) |
2396 | { | |
7eebfc62 | 2397 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); |
4f425a32 MH |
2398 | State.exception = SIGILL; |
2399 | return; | |
4c38885c MH |
2400 | } |
2401 | State.regs[OP[1]] -= 4; | |
2402 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2403 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
87178dbd | 2404 | trace_output (OP_VOID); |
2934d1c9 MH |
2405 | } |
2406 | ||
2407 | /* st2w */ | |
2408 | void | |
2409 | OP_6A01 () | |
2410 | { | |
1155e06e | 2411 | trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID); |
4c38885c MH |
2412 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2413 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2414 | INC_ADDR (State.regs[OP[1]],4); |
87178dbd | 2415 | trace_output (OP_VOID); |
2934d1c9 MH |
2416 | } |
2417 | ||
2418 | /* st2w */ | |
2419 | void | |
2420 | OP_6E01 () | |
2421 | { | |
1155e06e FF |
2422 | trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID); |
2423 | if ( OP[1] == 15 ) | |
2424 | { | |
2425 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2426 | State.exception = SIGILL; | |
2427 | return; | |
2428 | } | |
4c38885c MH |
2429 | SW (State.regs[OP[1]], State.regs[OP[0]]); |
2430 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
4f425a32 | 2431 | INC_ADDR (State.regs[OP[1]],-4); |
87178dbd | 2432 | trace_output (OP_VOID); |
2934d1c9 MH |
2433 | } |
2434 | ||
2435 | /* stb */ | |
2436 | void | |
2437 | OP_3C000000 () | |
2438 | { | |
87178dbd | 2439 | trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID); |
4f425a32 | 2440 | SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); |
87178dbd | 2441 | trace_output (OP_VOID); |
2934d1c9 MH |
2442 | } |
2443 | ||
2444 | /* stb */ | |
2445 | void | |
2446 | OP_7800 () | |
2447 | { | |
87178dbd | 2448 | trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID); |
4c38885c | 2449 | SB (State.regs[OP[1]], State.regs[OP[0]]); |
87178dbd | 2450 | trace_output (OP_VOID); |
2934d1c9 MH |
2451 | } |
2452 | ||
2453 | /* stop */ | |
2454 | void | |
2455 | OP_5FE0 () | |
2456 | { | |
87178dbd | 2457 | trace_input ("stop", OP_VOID, OP_VOID, OP_VOID); |
a49a15ad | 2458 | State.exception = SIG_D10V_STOP; |
87178dbd | 2459 | trace_output (OP_VOID); |
2934d1c9 MH |
2460 | } |
2461 | ||
2462 | /* sub */ | |
2463 | void | |
2464 | OP_0 () | |
4c38885c | 2465 | { |
f4b022d3 | 2466 | uint16 tmp; |
87178dbd MM |
2467 | |
2468 | trace_input ("sub", OP_REG, OP_REG, OP_VOID); | |
aa49c64f AC |
2469 | /* see ../common/sim-alu.h for a more extensive discussion on how to |
2470 | compute the carry/overflow bits. */ | |
f4b022d3 | 2471 | tmp = State.regs[OP[0]] - State.regs[OP[1]]; |
aa49c64f | 2472 | State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]); |
f4b022d3 | 2473 | State.regs[OP[0]] = tmp; |
87178dbd | 2474 | trace_output (OP_REG); |
4c38885c MH |
2475 | } |
2476 | ||
2477 | /* sub */ | |
2478 | void | |
2479 | OP_1001 () | |
2480 | { | |
4f425a32 | 2481 | int64 tmp; |
87178dbd MM |
2482 | |
2483 | trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID); | |
4f425a32 MH |
2484 | tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); |
2485 | if (State.ST) | |
2486 | { | |
2487 | if ( tmp > MAX32) | |
2488 | State.a[OP[0]] = MAX32; | |
2489 | else if ( tmp < MIN32) | |
2490 | State.a[OP[0]] = MIN32; | |
2491 | else | |
2492 | State.a[OP[0]] = tmp & MASK40; | |
2493 | } | |
2494 | else | |
2495 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2496 | |
2497 | trace_output (OP_ACCUM); | |
4c38885c MH |
2498 | } |
2499 | ||
2500 | /* sub */ | |
2501 | ||
2502 | void | |
2503 | OP_1003 () | |
2934d1c9 | 2504 | { |
4f425a32 | 2505 | int64 tmp; |
87178dbd MM |
2506 | |
2507 | trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID); | |
4f425a32 MH |
2508 | tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]); |
2509 | if (State.ST) | |
2510 | { | |
2511 | if (tmp > MAX32) | |
2512 | State.a[OP[0]] = MAX32; | |
2513 | else if ( tmp < MIN32) | |
2514 | State.a[OP[0]] = MIN32; | |
2515 | else | |
2516 | State.a[OP[0]] = tmp & MASK40; | |
2517 | } | |
2518 | else | |
2519 | State.a[OP[0]] = tmp & MASK40; | |
87178dbd MM |
2520 | |
2521 | trace_output (OP_ACCUM); | |
2934d1c9 MH |
2522 | } |
2523 | ||
2524 | /* sub2w */ | |
2525 | void | |
2526 | OP_1000 () | |
2527 | { | |
f4b022d3 | 2528 | uint32 tmp,a,b; |
4c38885c | 2529 | |
87178dbd | 2530 | trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID); |
f4b022d3 MM |
2531 | a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]); |
2532 | b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
70ee56c5 AC |
2533 | /* see ../common/sim-alu.h for a more extensive discussion on how to |
2534 | compute the carry/overflow bits */ | |
2535 | tmp = a - b; | |
51b057f2 | 2536 | State.C = (a >= b); |
4c38885c MH |
2537 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; |
2538 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2539 | trace_output (OP_DREG); |
2934d1c9 MH |
2540 | } |
2541 | ||
2542 | /* subac3 */ | |
2543 | void | |
2544 | OP_17000000 () | |
2545 | { | |
4f425a32 | 2546 | int64 tmp; |
87178dbd MM |
2547 | |
2548 | trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2549 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]); |
2550 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2551 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2552 | trace_output (OP_DREG); |
2934d1c9 MH |
2553 | } |
2554 | ||
2555 | /* subac3 */ | |
2556 | void | |
2557 | OP_17000002 () | |
2558 | { | |
4f425a32 | 2559 | int64 tmp; |
87178dbd MM |
2560 | |
2561 | trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2562 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); |
2563 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2564 | State.regs[OP[0]+1] = tmp & 0xffff; | |
87178dbd | 2565 | trace_output (OP_DREG); |
2934d1c9 MH |
2566 | } |
2567 | ||
2568 | /* subac3s */ | |
2569 | void | |
2570 | OP_17001000 () | |
2571 | { | |
4f425a32 | 2572 | int64 tmp; |
87178dbd MM |
2573 | |
2574 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
4f425a32 MH |
2575 | State.F1 = State.F0; |
2576 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]); | |
2577 | if ( tmp > MAX32) | |
2578 | { | |
2579 | State.regs[OP[0]] = 0x7fff; | |
2580 | State.regs[OP[0]+1] = 0xffff; | |
2581 | State.F0 = 1; | |
2582 | } | |
2583 | else if (tmp < MIN32) | |
2584 | { | |
2585 | State.regs[OP[0]] = 0x8000; | |
2586 | State.regs[OP[0]+1] = 0; | |
2587 | State.F0 = 1; | |
2588 | } | |
2589 | else | |
2590 | { | |
2591 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2592 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2593 | State.F0 = 0; | |
2594 | } | |
87178dbd | 2595 | trace_output (OP_DREG); |
2934d1c9 MH |
2596 | } |
2597 | ||
2598 | /* subac3s */ | |
2599 | void | |
2600 | OP_17001002 () | |
2601 | { | |
4f425a32 | 2602 | int64 tmp; |
87178dbd MM |
2603 | |
2604 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
4f425a32 MH |
2605 | State.F1 = State.F0; |
2606 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); | |
2607 | if ( tmp > MAX32) | |
2608 | { | |
2609 | State.regs[OP[0]] = 0x7fff; | |
2610 | State.regs[OP[0]+1] = 0xffff; | |
2611 | State.F0 = 1; | |
2612 | } | |
2613 | else if (tmp < MIN32) | |
2614 | { | |
2615 | State.regs[OP[0]] = 0x8000; | |
2616 | State.regs[OP[0]+1] = 0; | |
2617 | State.F0 = 1; | |
2618 | } | |
2619 | else | |
2620 | { | |
2621 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2622 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2623 | State.F0 = 0; | |
2624 | } | |
87178dbd | 2625 | trace_output (OP_DREG); |
2934d1c9 MH |
2626 | } |
2627 | ||
2628 | /* subi */ | |
2629 | void | |
2630 | OP_1 () | |
2631 | { | |
70ee56c5 | 2632 | unsigned tmp; |
4f425a32 MH |
2633 | if (OP[1] == 0) |
2634 | OP[1] = 16; | |
87178dbd MM |
2635 | |
2636 | trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); | |
70ee56c5 | 2637 | /* see ../common/sim-alu.h for a more extensive discussion on how to |
51b057f2 AC |
2638 | compute the carry/overflow bits. */ |
2639 | /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */ | |
70ee56c5 AC |
2640 | tmp = ((unsigned)(unsigned16) State.regs[OP[0]] |
2641 | + (unsigned)(unsigned16) ( - OP[1])); | |
2642 | State.C = (tmp >= (1 << 16)); | |
2643 | State.regs[OP[0]] = tmp; | |
87178dbd | 2644 | trace_output (OP_REG); |
2934d1c9 MH |
2645 | } |
2646 | ||
2647 | /* trap */ | |
2648 | void | |
2649 | OP_5F00 () | |
2650 | { | |
a5719092 | 2651 | trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID); |
87178dbd | 2652 | trace_output (OP_VOID); |
8918b3a7 | 2653 | |
63a91cfb | 2654 | switch (OP[0]) |
2934d1c9 | 2655 | { |
63a91cfb | 2656 | default: |
19431a02 | 2657 | #if (DEBUG & DEBUG_TRAP) == 0 |
19d44375 | 2658 | { |
bc6df23d AC |
2659 | uint16 vec = OP[0] + TRAP_VECTOR_START; |
2660 | BPC = PC + 1; | |
2661 | move_to_cr (BPSW_CR, PSW); | |
2662 | move_to_cr (PSW_CR, PSW & PSW_SM_BIT); | |
2663 | JMP (vec); | |
19431a02 | 2664 | break; |
87e43259 | 2665 | } |
19431a02 AC |
2666 | #else /* if debugging use trap to print registers */ |
2667 | { | |
2668 | int i; | |
2669 | static int first_time = 1; | |
2670 | ||
2671 | if (first_time) | |
2672 | { | |
2673 | first_time = 0; | |
2674 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC "); | |
2675 | for (i = 0; i < 16; i++) | |
2676 | (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i); | |
2677 | (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n"); | |
2678 | } | |
2679 | ||
2680 | (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); | |
2681 | ||
2682 | for (i = 0; i < 16; i++) | |
2683 | (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]); | |
2684 | ||
2685 | for (i = 0; i < 2; i++) | |
2686 | (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx", | |
2687 | ((int)(State.a[i] >> 32) & 0xff), | |
2688 | ((unsigned long)State.a[i]) & 0xffffffff); | |
2689 | ||
2690 | (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n", | |
2691 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
2692 | (*d10v_callback->flush_stdout) (d10v_callback); | |
2693 | break; | |
2694 | } | |
2695 | #endif | |
87e43259 AC |
2696 | case 15: /* new system call trap */ |
2697 | /* Trap 15 is used for simulating low-level I/O */ | |
63a91cfb | 2698 | { |
63a91cfb MM |
2699 | errno = 0; |
2700 | ||
2701 | /* Registers passed to trap 0 */ | |
2702 | ||
8831cb01 MM |
2703 | #define FUNC State.regs[4] /* function number */ |
2704 | #define PARM1 State.regs[0] /* optional parm 1 */ | |
2705 | #define PARM2 State.regs[1] /* optional parm 2 */ | |
2706 | #define PARM3 State.regs[2] /* optional parm 3 */ | |
2707 | #define PARM4 State.regs[3] /* optional parm 3 */ | |
63a91cfb MM |
2708 | |
2709 | /* Registers set by trap 0 */ | |
2710 | ||
8831cb01 MM |
2711 | #define RETVAL State.regs[0] /* return value */ |
2712 | #define RETVAL_HIGH State.regs[0] /* return value */ | |
2713 | #define RETVAL_LOW State.regs[1] /* return value */ | |
65c0d7de | 2714 | #define RETERR State.regs[4] /* return error code */ |
63a91cfb MM |
2715 | |
2716 | /* Turn a pointer in a register into a pointer into real memory. */ | |
2717 | ||
c422ecc7 | 2718 | #define MEMPTR(x) ((char *)(dmem_addr(x))) |
63a91cfb MM |
2719 | |
2720 | switch (FUNC) | |
2721 | { | |
2722 | #if !defined(__GO32__) && !defined(_WIN32) | |
63a91cfb MM |
2723 | case SYS_fork: |
2724 | RETVAL = fork (); | |
8918b3a7 | 2725 | trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); |
8831cb01 | 2726 | trace_output (OP_R0); |
63a91cfb | 2727 | break; |
8918b3a7 | 2728 | |
57bc1a72 MM |
2729 | case SYS_getpid: |
2730 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2731 | RETVAL = getpid (); | |
8831cb01 | 2732 | trace_output (OP_R0); |
57bc1a72 MM |
2733 | break; |
2734 | ||
2735 | case SYS_kill: | |
2736 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2737 | if (PARM1 == getpid ()) | |
2738 | { | |
2739 | trace_output (OP_VOID); | |
2740 | State.exception = PARM2; | |
2741 | } | |
2742 | else | |
2743 | { | |
2744 | int os_sig = -1; | |
2745 | switch (PARM2) | |
2746 | { | |
2747 | #ifdef SIGHUP | |
2748 | case 1: os_sig = SIGHUP; break; | |
2749 | #endif | |
2750 | #ifdef SIGINT | |
2751 | case 2: os_sig = SIGINT; break; | |
2752 | #endif | |
2753 | #ifdef SIGQUIT | |
2754 | case 3: os_sig = SIGQUIT; break; | |
2755 | #endif | |
2756 | #ifdef SIGILL | |
2757 | case 4: os_sig = SIGILL; break; | |
2758 | #endif | |
2759 | #ifdef SIGTRAP | |
2760 | case 5: os_sig = SIGTRAP; break; | |
2761 | #endif | |
2762 | #ifdef SIGABRT | |
2763 | case 6: os_sig = SIGABRT; break; | |
2764 | #elif defined(SIGIOT) | |
2765 | case 6: os_sig = SIGIOT; break; | |
2766 | #endif | |
2767 | #ifdef SIGEMT | |
2768 | case 7: os_sig = SIGEMT; break; | |
2769 | #endif | |
2770 | #ifdef SIGFPE | |
2771 | case 8: os_sig = SIGFPE; break; | |
2772 | #endif | |
2773 | #ifdef SIGKILL | |
2774 | case 9: os_sig = SIGKILL; break; | |
2775 | #endif | |
2776 | #ifdef SIGBUS | |
2777 | case 10: os_sig = SIGBUS; break; | |
2778 | #endif | |
2779 | #ifdef SIGSEGV | |
2780 | case 11: os_sig = SIGSEGV; break; | |
2781 | #endif | |
2782 | #ifdef SIGSYS | |
2783 | case 12: os_sig = SIGSYS; break; | |
2784 | #endif | |
2785 | #ifdef SIGPIPE | |
2786 | case 13: os_sig = SIGPIPE; break; | |
2787 | #endif | |
2788 | #ifdef SIGALRM | |
2789 | case 14: os_sig = SIGALRM; break; | |
2790 | #endif | |
2791 | #ifdef SIGTERM | |
2792 | case 15: os_sig = SIGTERM; break; | |
2793 | #endif | |
2794 | #ifdef SIGURG | |
2795 | case 16: os_sig = SIGURG; break; | |
2796 | #endif | |
2797 | #ifdef SIGSTOP | |
2798 | case 17: os_sig = SIGSTOP; break; | |
2799 | #endif | |
2800 | #ifdef SIGTSTP | |
2801 | case 18: os_sig = SIGTSTP; break; | |
2802 | #endif | |
2803 | #ifdef SIGCONT | |
2804 | case 19: os_sig = SIGCONT; break; | |
2805 | #endif | |
2806 | #ifdef SIGCHLD | |
2807 | case 20: os_sig = SIGCHLD; break; | |
2808 | #elif defined(SIGCLD) | |
2809 | case 20: os_sig = SIGCLD; break; | |
2810 | #endif | |
2811 | #ifdef SIGTTIN | |
2812 | case 21: os_sig = SIGTTIN; break; | |
2813 | #endif | |
2814 | #ifdef SIGTTOU | |
2815 | case 22: os_sig = SIGTTOU; break; | |
2816 | #endif | |
2817 | #ifdef SIGIO | |
2818 | case 23: os_sig = SIGIO; break; | |
2819 | #elif defined (SIGPOLL) | |
2820 | case 23: os_sig = SIGPOLL; break; | |
2821 | #endif | |
2822 | #ifdef SIGXCPU | |
2823 | case 24: os_sig = SIGXCPU; break; | |
2824 | #endif | |
2825 | #ifdef SIGXFSZ | |
2826 | case 25: os_sig = SIGXFSZ; break; | |
2827 | #endif | |
2828 | #ifdef SIGVTALRM | |
2829 | case 26: os_sig = SIGVTALRM; break; | |
2830 | #endif | |
2831 | #ifdef SIGPROF | |
2832 | case 27: os_sig = SIGPROF; break; | |
2833 | #endif | |
2834 | #ifdef SIGWINCH | |
2835 | case 28: os_sig = SIGWINCH; break; | |
2836 | #endif | |
2837 | #ifdef SIGLOST | |
2838 | case 29: os_sig = SIGLOST; break; | |
2839 | #endif | |
2840 | #ifdef SIGUSR1 | |
2841 | case 30: os_sig = SIGUSR1; break; | |
2842 | #endif | |
2843 | #ifdef SIGUSR2 | |
2844 | case 31: os_sig = SIGUSR2; break; | |
2845 | #endif | |
2846 | } | |
2847 | ||
2848 | if (os_sig == -1) | |
2849 | { | |
2850 | trace_output (OP_VOID); | |
2851 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2); | |
fd435e9f | 2852 | (*d10v_callback->flush_stdout) (d10v_callback); |
57bc1a72 MM |
2853 | State.exception = SIGILL; |
2854 | } | |
2855 | else | |
2856 | { | |
2857 | RETVAL = kill (PARM1, PARM2); | |
8831cb01 | 2858 | trace_output (OP_R0); |
57bc1a72 MM |
2859 | } |
2860 | } | |
2861 | break; | |
2862 | ||
63a91cfb MM |
2863 | case SYS_execve: |
2864 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), | |
2865 | (char **)MEMPTR (PARM3)); | |
8831cb01 MM |
2866 | trace_input ("<execve>", OP_R0, OP_R1, OP_R2); |
2867 | trace_output (OP_R0); | |
63a91cfb | 2868 | break; |
8918b3a7 | 2869 | |
87e43259 | 2870 | #ifdef SYS_execv |
63a91cfb MM |
2871 | case SYS_execv: |
2872 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); | |
8831cb01 MM |
2873 | trace_input ("<execv>", OP_R0, OP_R1, OP_VOID); |
2874 | trace_output (OP_R0); | |
63a91cfb | 2875 | break; |
87e43259 | 2876 | #endif |
8918b3a7 | 2877 | |
63a91cfb MM |
2878 | case SYS_pipe: |
2879 | { | |
2880 | reg_t buf; | |
2881 | int host_fd[2]; | |
2882 | ||
2883 | buf = PARM1; | |
2884 | RETVAL = pipe (host_fd); | |
2885 | SW (buf, host_fd[0]); | |
2886 | buf += sizeof(uint16); | |
2887 | SW (buf, host_fd[1]); | |
8831cb01 MM |
2888 | trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID); |
2889 | trace_output (OP_R0); | |
63a91cfb MM |
2890 | } |
2891 | break; | |
8918b3a7 | 2892 | |
87e43259 | 2893 | #ifdef SYS_wait |
63a91cfb MM |
2894 | case SYS_wait: |
2895 | { | |
2896 | int status; | |
2897 | ||
2898 | RETVAL = wait (&status); | |
8918b3a7 MM |
2899 | if (PARM1) |
2900 | SW (PARM1, status); | |
8831cb01 MM |
2901 | trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID); |
2902 | trace_output (OP_R0); | |
63a91cfb MM |
2903 | } |
2904 | break; | |
87e43259 | 2905 | #endif |
57bc1a72 MM |
2906 | #else |
2907 | case SYS_getpid: | |
2908 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2909 | RETVAL = 1; | |
8831cb01 | 2910 | trace_output (OP_R0); |
57bc1a72 MM |
2911 | break; |
2912 | ||
2913 | case SYS_kill: | |
2914 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2915 | trace_output (OP_VOID); | |
2916 | State.exception = PARM2; | |
2917 | break; | |
63a91cfb | 2918 | #endif |
8918b3a7 | 2919 | |
63a91cfb MM |
2920 | case SYS_read: |
2921 | RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2), | |
2922 | PARM3); | |
8831cb01 MM |
2923 | trace_input ("<read>", OP_R0, OP_R1, OP_R2); |
2924 | trace_output (OP_R0); | |
63a91cfb | 2925 | break; |
8918b3a7 | 2926 | |
63a91cfb MM |
2927 | case SYS_write: |
2928 | if (PARM1 == 1) | |
2929 | RETVAL = (int)d10v_callback->write_stdout (d10v_callback, | |
2930 | MEMPTR (PARM2), PARM3); | |
2931 | else | |
2932 | RETVAL = (int)d10v_callback->write (d10v_callback, PARM1, | |
2933 | MEMPTR (PARM2), PARM3); | |
8831cb01 MM |
2934 | trace_input ("<write>", OP_R0, OP_R1, OP_R2); |
2935 | trace_output (OP_R0); | |
63a91cfb | 2936 | break; |
8918b3a7 | 2937 | |
63a91cfb | 2938 | case SYS_lseek: |
65c0d7de MA |
2939 | { |
2940 | unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1, | |
2941 | (((unsigned long)PARM2) << 16) || (unsigned long)PARM3, | |
2942 | PARM4); | |
2943 | RETVAL_HIGH = ret >> 16; | |
2944 | RETVAL_LOW = ret & 0xffff; | |
2945 | } | |
8831cb01 MM |
2946 | trace_input ("<lseek>", OP_R0, OP_R1, OP_R2); |
2947 | trace_output (OP_R0R1); | |
63a91cfb | 2948 | break; |
8918b3a7 | 2949 | |
63a91cfb MM |
2950 | case SYS_close: |
2951 | RETVAL = d10v_callback->close (d10v_callback, PARM1); | |
8831cb01 MM |
2952 | trace_input ("<close>", OP_R0, OP_VOID, OP_VOID); |
2953 | trace_output (OP_R0); | |
63a91cfb | 2954 | break; |
8918b3a7 | 2955 | |
63a91cfb MM |
2956 | case SYS_open: |
2957 | RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2); | |
8831cb01 MM |
2958 | trace_input ("<open>", OP_R0, OP_R1, OP_R2); |
2959 | trace_output (OP_R0); | |
2960 | trace_input ("<open>", OP_R0, OP_R1, OP_R2); | |
2961 | trace_output (OP_R0); | |
63a91cfb | 2962 | break; |
8918b3a7 | 2963 | |
63a91cfb | 2964 | case SYS_exit: |
a49a15ad | 2965 | State.exception = SIG_D10V_EXIT; |
8831cb01 | 2966 | trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID); |
8918b3a7 | 2967 | trace_output (OP_VOID); |
63a91cfb | 2968 | break; |
63a91cfb | 2969 | |
8719be26 | 2970 | case SYS_stat: |
63a91cfb MM |
2971 | /* stat system call */ |
2972 | { | |
2973 | struct stat host_stat; | |
2974 | reg_t buf; | |
2975 | ||
2976 | RETVAL = stat (MEMPTR (PARM1), &host_stat); | |
2977 | ||
2978 | buf = PARM2; | |
2979 | ||
2980 | /* The hard-coded offsets and sizes were determined by using | |
2981 | * the D10V compiler on a test program that used struct stat. | |
2982 | */ | |
2983 | SW (buf, host_stat.st_dev); | |
2984 | SW (buf+2, host_stat.st_ino); | |
2985 | SW (buf+4, host_stat.st_mode); | |
2986 | SW (buf+6, host_stat.st_nlink); | |
2987 | SW (buf+8, host_stat.st_uid); | |
2988 | SW (buf+10, host_stat.st_gid); | |
2989 | SW (buf+12, host_stat.st_rdev); | |
2990 | SLW (buf+16, host_stat.st_size); | |
2991 | SLW (buf+20, host_stat.st_atime); | |
2992 | SLW (buf+28, host_stat.st_mtime); | |
2993 | SLW (buf+36, host_stat.st_ctime); | |
2994 | } | |
8831cb01 MM |
2995 | trace_input ("<stat>", OP_R0, OP_R1, OP_VOID); |
2996 | trace_output (OP_R0); | |
63a91cfb | 2997 | break; |
63a91cfb | 2998 | |
63a91cfb MM |
2999 | case SYS_chown: |
3000 | RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); | |
8831cb01 MM |
3001 | trace_input ("<chown>", OP_R0, OP_R1, OP_R2); |
3002 | trace_output (OP_R0); | |
63a91cfb | 3003 | break; |
8918b3a7 | 3004 | |
63a91cfb MM |
3005 | case SYS_chmod: |
3006 | RETVAL = chmod (MEMPTR (PARM1), PARM2); | |
8831cb01 MM |
3007 | trace_input ("<chmod>", OP_R0, OP_R1, OP_R2); |
3008 | trace_output (OP_R0); | |
63a91cfb | 3009 | break; |
8918b3a7 | 3010 | |
87e43259 | 3011 | #ifdef SYS_utime |
63a91cfb MM |
3012 | case SYS_utime: |
3013 | /* Cast the second argument to void *, to avoid type mismatch | |
3014 | if a prototype is present. */ | |
3015 | RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); | |
8831cb01 MM |
3016 | trace_input ("<utime>", OP_R0, OP_R1, OP_R2); |
3017 | trace_output (OP_R0); | |
8918b3a7 | 3018 | break; |
87e43259 | 3019 | #endif |
8918b3a7 | 3020 | |
87e43259 | 3021 | #ifdef SYS_time |
8918b3a7 MM |
3022 | case SYS_time: |
3023 | { | |
3024 | unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL); | |
3025 | RETVAL_HIGH = ret >> 16; | |
3026 | RETVAL_LOW = ret & 0xffff; | |
3027 | } | |
8831cb01 MM |
3028 | trace_input ("<time>", OP_R0, OP_R1, OP_R2); |
3029 | trace_output (OP_R0R1); | |
63a91cfb | 3030 | break; |
87e43259 | 3031 | #endif |
8918b3a7 | 3032 | |
63a91cfb | 3033 | default: |
b41dff6b | 3034 | d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC); |
63a91cfb | 3035 | } |
87e43259 | 3036 | RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0; |
63a91cfb MM |
3037 | break; |
3038 | } | |
2934d1c9 MH |
3039 | } |
3040 | } | |
3041 | ||
3042 | /* tst0i */ | |
3043 | void | |
3044 | OP_7000000 () | |
3045 | { | |
87178dbd | 3046 | trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 3047 | State.F1 = State.F0; |
4f425a32 | 3048 | State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0; |
87178dbd | 3049 | trace_output (OP_FLAG); |
2934d1c9 MH |
3050 | } |
3051 | ||
3052 | /* tst1i */ | |
3053 | void | |
3054 | OP_F000000 () | |
3055 | { | |
87178dbd | 3056 | trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID); |
4c38885c | 3057 | State.F1 = State.F0; |
4f425a32 | 3058 | State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0; |
87178dbd | 3059 | trace_output (OP_FLAG); |
2934d1c9 MH |
3060 | } |
3061 | ||
3062 | /* wait */ | |
3063 | void | |
3064 | OP_5F80 () | |
3065 | { | |
87178dbd | 3066 | trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); |
4c38885c | 3067 | State.IE = 1; |
87178dbd | 3068 | trace_output (OP_VOID); |
2934d1c9 MH |
3069 | } |
3070 | ||
3071 | /* xor */ | |
3072 | void | |
3073 | OP_A00 () | |
3074 | { | |
87178dbd | 3075 | trace_input ("xor", OP_REG, OP_REG, OP_VOID); |
4c38885c | 3076 | State.regs[OP[0]] ^= State.regs[OP[1]]; |
87178dbd | 3077 | trace_output (OP_REG); |
2934d1c9 MH |
3078 | } |
3079 | ||
3080 | /* xor3 */ | |
3081 | void | |
3082 | OP_5000000 () | |
3083 | { | |
87178dbd | 3084 | trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); |
4c38885c | 3085 | State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2]; |
87178dbd | 3086 | trace_output (OP_REG); |
2934d1c9 MH |
3087 | } |
3088 |