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import gdb-1999-09-08 snapshot
[deliverable/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
c906108c
SS		 1#include "config.h"
2
3#include <signal.h>
4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
7#ifdef HAVE_UNISTD_H
8#include <unistd.h>
9#endif
10
11#include "d10v_sim.h"
12#include "simops.h"
13#include "targ-vals.h"
14
15extern char *strrchr ();
16
17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
39 OP_PREDEC,
40 OP_R0,
41 OP_R1,
42 OP_R2,
43};
44
45
46enum {
47 PSW_MASK = (PSW_SM_BIT
48 | PSW_EA_BIT
49 | PSW_DB_BIT
50 | PSW_DM_BIT
51 | PSW_IE_BIT
52 | PSW_RP_BIT
53 | PSW_MD_BIT
54 | PSW_FX_BIT
55 | PSW_ST_BIT
56 | PSW_F0_BIT
57 | PSW_F1_BIT
58 | PSW_C_BIT),
59};
60
61reg_t
62move_to_cr (int cr, reg_t mask, reg_t val)
63{
64 /* A MASK bit is set when the corresponding bit in the CR should
65 be left alone */
66 /* This assumes that (VAL & MASK) == 0 */
67 switch (cr)
68 {
69 case PSW_CR:
70 val &= PSW_MASK;
71 if ((mask & PSW_SM_BIT) == 0)
72 {
73 int new_sm = (val & PSW_SM_BIT) != 0;
74 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
75 if (PSW_SM != new_sm)
76 SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
77 }
78 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
79 {
80 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
81 {
82 (*d10v_callback->printf_filtered)
83 (d10v_callback,
84 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
85 PC<<2);
86 State.exception = SIGILL;
87 }
88 }
89 /* keep an up-to-date psw around for tracing */
90 State.trace.psw = (State.trace.psw & mask) | val;
91 break;
92 case BPSW_CR:
93 case DPSW_CR:
94 val &= PSW_MASK;
95 break;
96 case MOD_S_CR:
97 case MOD_E_CR:
98 val &= ~1;
99 break;
100 default:
101 break;
102 }
103 /* only issue an update if the register is being changed */
104 if ((State.cregs[cr] & ~mask) != val)
105 SLOT_PEND_MASK (State.cregs[cr], mask, val);
106 return val;
107}
108
109#ifdef DEBUG
110static void trace_input_func PARAMS ((char *name,
111 enum op_types in1,
112 enum op_types in2,
113 enum op_types in3));
114
115#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
116
117#ifndef SIZE_INSTRUCTION
118#define SIZE_INSTRUCTION 8
119#endif
120
121#ifndef SIZE_OPERANDS
122#define SIZE_OPERANDS 18
123#endif
124
125#ifndef SIZE_VALUES
126#define SIZE_VALUES 13
127#endif
128
129#ifndef SIZE_LOCATION
130#define SIZE_LOCATION 20
131#endif
132
133#ifndef SIZE_PC
134#define SIZE_PC 6
135#endif
136
137#ifndef SIZE_LINE_NUMBER
138#define SIZE_LINE_NUMBER 4
139#endif
140
141static void
142trace_input_func (name, in1, in2, in3)
143 char *name;
144 enum op_types in1;
145 enum op_types in2;
146 enum op_types in3;
147{
148 char *comma;
149 enum op_types in[3];
150 int i;
151 char buf[1024];
152 char *p;
153 long tmp;
154 char *type;
155 const char *filename;
156 const char *functionname;
157 unsigned int linenumber;
158 bfd_vma byte_pc;
159
160 if ((d10v_debug & DEBUG_TRACE) == 0)
161 return;
162
163 switch (State.ins_type)
164 {
165 default:
166 case INS_UNKNOWN: type = " ?"; break;
167 case INS_LEFT: type = " L"; break;
168 case INS_RIGHT: type = " R"; break;
169 case INS_LEFT_PARALLEL: type = "*L"; break;
170 case INS_RIGHT_PARALLEL: type = "*R"; break;
171 case INS_LEFT_COND_TEST: type = "?L"; break;
172 case INS_RIGHT_COND_TEST: type = "?R"; break;
173 case INS_LEFT_COND_EXE: type = "&L"; break;
174 case INS_RIGHT_COND_EXE: type = "&R"; break;
175 case INS_LONG: type = " B"; break;
176 }
177
178 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
179 (*d10v_callback->printf_filtered) (d10v_callback,
180 "0x%.*x %s: %-*s ",
181 SIZE_PC, (unsigned)PC,
182 type,
183 SIZE_INSTRUCTION, name);
184
185 else
186 {
187 buf[0] = '\0';
188 byte_pc = decode_pc ();
189 if (text && byte_pc >= text_start && byte_pc < text_end)
190 {
191 filename = (const char *)0;
192 functionname = (const char *)0;
193 linenumber = 0;
194 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
195 &filename, &functionname, &linenumber))
196 {
197 p = buf;
198 if (linenumber)
199 {
200 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
201 p += strlen (p);
202 }
203 else
204 {
205 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
206 p += SIZE_LINE_NUMBER+2;
207 }
208
209 if (functionname)
210 {
211 sprintf (p, "%s ", functionname);
212 p += strlen (p);
213 }
214 else if (filename)
215 {
216 char *q = strrchr (filename, '/');
217 sprintf (p, "%s ", (q) ? q+1 : filename);
218 p += strlen (p);
219 }
220
221 if (*p == ' ')
222 *p = '\0';
223 }
224 }
225
226 (*d10v_callback->printf_filtered) (d10v_callback,
227 "0x%.*x %s: %-*.*s %-*s ",
228 SIZE_PC, (unsigned)PC,
229 type,
230 SIZE_LOCATION, SIZE_LOCATION, buf,
231 SIZE_INSTRUCTION, name);
232 }
233
234 in[0] = in1;
235 in[1] = in2;
236 in[2] = in3;
237 comma = "";
238 p = buf;
239 for (i = 0; i < 3; i++)
240 {
241 switch (in[i])
242 {
243 case OP_VOID:
244 case OP_R0:
245 case OP_R1:
246 case OP_R2:
247 break;
248
249 case OP_REG:
250 case OP_REG_OUTPUT:
251 case OP_DREG:
252 case OP_DREG_OUTPUT:
253 sprintf (p, "%sr%d", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_CR:
259 case OP_CR_OUTPUT:
260 case OP_CR_REVERSE:
261 sprintf (p, "%scr%d", comma, OP[i]);
262 p += strlen (p);
263 comma = ",";
264 break;
265
266 case OP_ACCUM:
267 case OP_ACCUM_OUTPUT:
268 case OP_ACCUM_REVERSE:
269 sprintf (p, "%sa%d", comma, OP[i]);
270 p += strlen (p);
271 comma = ",";
272 break;
273
274 case OP_CONSTANT16:
275 sprintf (p, "%s%d", comma, OP[i]);
276 p += strlen (p);
277 comma = ",";
278 break;
279
280 case OP_CONSTANT8:
281 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
282 p += strlen (p);
283 comma = ",";
284 break;
285
286 case OP_CONSTANT4:
287 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
288 p += strlen (p);
289 comma = ",";
290 break;
291
292 case OP_CONSTANT3:
293 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
294 p += strlen (p);
295 comma = ",";
296 break;
297
298 case OP_MEMREF:
299 sprintf (p, "%s@r%d", comma, OP[i]);
300 p += strlen (p);
301 comma = ",";
302 break;
303
304 case OP_MEMREF2:
305 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
306 p += strlen (p);
307 comma = ",";
308 break;
309
310 case OP_POSTINC:
311 sprintf (p, "%s@r%d+", comma, OP[i]);
312 p += strlen (p);
313 comma = ",";
314 break;
315
316 case OP_POSTDEC:
317 sprintf (p, "%s@r%d-", comma, OP[i]);
318 p += strlen (p);
319 comma = ",";
320 break;
321
322 case OP_PREDEC:
323 sprintf (p, "%s@-r%d", comma, OP[i]);
324 p += strlen (p);
325 comma = ",";
326 break;
327
328 case OP_FLAG:
329 case OP_FLAG_OUTPUT:
330 if (OP[i] == 0)
331 sprintf (p, "%sf0", comma);
332
333 else if (OP[i] == 1)
334 sprintf (p, "%sf1", comma);
335
336 else
337 sprintf (p, "%sc", comma);
338
339 p += strlen (p);
340 comma = ",";
341 break;
342 }
343 }
344
345 if ((d10v_debug & DEBUG_VALUES) == 0)
346 {
347 *p++ = '\n';
348 *p = '\0';
349 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
350 }
351 else
352 {
353 *p = '\0';
354 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
355
356 p = buf;
357 for (i = 0; i < 3; i++)
358 {
359 buf[0] = '\0';
360 switch (in[i])
361 {
362 case OP_VOID:
363 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
364 break;
365
366 case OP_REG_OUTPUT:
367 case OP_DREG_OUTPUT:
368 case OP_CR_OUTPUT:
369 case OP_ACCUM_OUTPUT:
370 case OP_FLAG_OUTPUT:
371 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
372 break;
373
374 case OP_REG:
375 case OP_MEMREF:
376 case OP_POSTDEC:
377 case OP_POSTINC:
378 case OP_PREDEC:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16) GPR (OP[i]));
381 break;
382
383 case OP_DREG:
384 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
385 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
386 break;
387
388 case OP_CR:
389 case OP_CR_REVERSE:
390 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
391 (uint16) CREG (OP[i]));
392 break;
393
394 case OP_ACCUM:
395 case OP_ACCUM_REVERSE:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
397 ((int)(ACC (OP[i]) >> 32) & 0xff),
398 ((unsigned long) ACC (OP[i])) & 0xffffffff);
399 break;
400
401 case OP_CONSTANT16:
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
403 (uint16)OP[i]);
404 break;
405
406 case OP_CONSTANT4:
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
408 (uint16)SEXT4(OP[i]));
409 break;
410
411 case OP_CONSTANT8:
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16)SEXT8(OP[i]));
414 break;
415
416 case OP_CONSTANT3:
417 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16)SEXT3(OP[i]));
419 break;
420
421 case OP_FLAG:
422 if (OP[i] == 0)
423 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
424 PSW_F0 != 0);
425
426 else if (OP[i] == 1)
427 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
428 PSW_F1 != 0);
429
430 else
431 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
432 PSW_C != 0);
433
434 break;
435
436 case OP_MEMREF2:
437 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
438 (uint16)OP[i]);
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)GPR (OP[i + 1]));
441 i++;
442 break;
443
444 case OP_R0:
445 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
446 (uint16) GPR (0));
447 break;
448
449 case OP_R1:
450 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
451 (uint16) GPR (1));
452 break;
453
454 case OP_R2:
455 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
456 (uint16) GPR (2));
457 break;
458
459 }
460 }
461 }
462
463 (*d10v_callback->flush_stdout) (d10v_callback);
464}
465
466static void
467do_trace_output_flush (void)
468{
469 (*d10v_callback->flush_stdout) (d10v_callback);
470}
471
472static void
473do_trace_output_finish (void)
474{
475 (*d10v_callback->printf_filtered) (d10v_callback,
476 " F0=%d F1=%d C=%d\n",
477 (State.trace.psw & PSW_F0_BIT) != 0,
478 (State.trace.psw & PSW_F1_BIT) != 0,
479 (State.trace.psw & PSW_C_BIT) != 0);
480 (*d10v_callback->flush_stdout) (d10v_callback);
481}
482
483static void
484trace_output_40 (uint64 val)
485{
486 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
487 {
488 (*d10v_callback->printf_filtered) (d10v_callback,
489 " :: %*s0x%.2x%.8lx",
490 SIZE_VALUES - 12,
491 "",
492 ((int)(val >> 32) & 0xff),
493 ((unsigned long) val) & 0xffffffff);
494 do_trace_output_finish ();
495 }
496}
497
498static void
499trace_output_32 (uint32 val)
500{
501 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
502 {
503 (*d10v_callback->printf_filtered) (d10v_callback,
504 " :: %*s0x%.8x",
505 SIZE_VALUES - 10,
506 "",
507 (int) val);
508 do_trace_output_finish ();
509 }
510}
511
512static void
513trace_output_16 (uint16 val)
514{
515 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
516 {
517 (*d10v_callback->printf_filtered) (d10v_callback,
518 " :: %*s0x%.4x",
519 SIZE_VALUES - 6,
520 "",
521 (int) val);
522 do_trace_output_finish ();
523 }
524}
525
526static void
527trace_output_void ()
528{
529 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
530 {
531 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
532 do_trace_output_flush ();
533 }
534}
535
536static void
537trace_output_flag ()
538{
539 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
540 {
541 (*d10v_callback->printf_filtered) (d10v_callback,
542 " :: %*s",
543 SIZE_VALUES,
544 "");
545 do_trace_output_finish ();
546 }
547}
548
549
550
551
552#else
553#define trace_input(NAME, IN1, IN2, IN3)
554#define trace_output(RESULT)
555#endif
556
557/* abs */
558void
559OP_4607 ()
560{
561 int16 tmp;
562 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
563 SET_PSW_F1 (PSW_F0);
564 tmp = GPR(OP[0]);
565 if (tmp < 0)
566 {
567 tmp = - tmp;
568 SET_PSW_F0 (1);
569 }
570 else
571 SET_PSW_F0 (0);
572 SET_GPR (OP[0], tmp);
573 trace_output_16 (tmp);
574}
575
576/* abs */
577void
578OP_5607 ()
579{
580 int64 tmp;
581 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
582 SET_PSW_F1 (PSW_F0);
583
584 tmp = SEXT40 (ACC (OP[0]));
585 if (tmp < 0 )
586 {
587 tmp = - tmp;
588 if (PSW_ST)
589 {
590 if (tmp > SEXT40(MAX32))
591 tmp = (MAX32);
592 else if (tmp < SEXT40(MIN32))
593 tmp = (MIN32);
594 else
595 tmp = (tmp & MASK40);
596 }
597 else
598 tmp = (tmp & MASK40);
599 SET_PSW_F0 (1);
600 }
601 else
602 {
603 tmp = (tmp & MASK40);
604 SET_PSW_F0 (0);
605 }
606 SET_ACC (OP[0], tmp);
607 trace_output_40 (tmp);
608}
609
610/* add */
611void
612OP_200 ()
613{
614 uint16 a = GPR (OP[0]);
615 uint16 b = GPR (OP[1]);
616 uint16 tmp = (a + b);
617 trace_input ("add", OP_REG, OP_REG, OP_VOID);
618 SET_PSW_C (a > tmp);
619 SET_GPR (OP[0], tmp);
620 trace_output_16 (tmp);
621}
622
623/* add */
624void
625OP_1201 ()
626{
627 int64 tmp;
628 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
629
630 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
631 if (PSW_ST)
632 {
633 if (tmp > SEXT40(MAX32))
634 tmp = (MAX32);
635 else if (tmp < SEXT40(MIN32))
636 tmp = (MIN32);
637 else
638 tmp = (tmp & MASK40);
639 }
640 else
641 tmp = (tmp & MASK40);
642 SET_ACC (OP[0], tmp);
643 trace_output_40 (tmp);
644}
645
646/* add */
647void
648OP_1203 ()
649{
650 int64 tmp;
651 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
652
653 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
654 if (PSW_ST)
655 {
656 if (tmp > SEXT40(MAX32))
657 tmp = (MAX32);
658 else if (tmp < SEXT40(MIN32))
659 tmp = (MIN32);
660 else
661 tmp = (tmp & MASK40);
662 }
663 else
664 tmp = (tmp & MASK40);
665 SET_ACC (OP[0], tmp);
666 trace_output_40 (tmp);
667}
668
669/* add2w */
670void
671OP_1200 ()
672{
673 uint32 tmp;
674 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
675 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
676 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
677 tmp = a + b;
678 SET_PSW_C (tmp < a);
679 SET_GPR (OP[0] + 0, (tmp >> 16));
680 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
681 trace_output_32 (tmp);
682}
683
684/* add3 */
685void
686OP_1000000 ()
687{
688 uint16 a = GPR (OP[1]);
689 uint16 b = OP[2];
690 uint16 tmp = (a + b);
691 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
692 SET_PSW_C (tmp < a);
693 SET_GPR (OP[0], tmp);
694 trace_output_16 (tmp);
695}
696
697/* addac3 */
698void
699OP_17000200 ()
700{
701 int64 tmp;
702 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
703
704 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
705 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
706 SET_GPR (OP[0] + 1, (tmp & 0xffff));
707 trace_output_32 (tmp);
708}
709
710/* addac3 */
711void
712OP_17000202 ()
713{
714 int64 tmp;
715 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
716
717 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
718 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
719 SET_GPR (OP[0] + 1, tmp & 0xffff);
720 trace_output_32 (tmp);
721}
722
723/* addac3s */
724void
725OP_17001200 ()
726{
727 int64 tmp;
728 SET_PSW_F1 (PSW_F0);
729
730 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
731 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
732 if (tmp > SEXT40(MAX32))
733 {
734 tmp = (MAX32);
735 SET_PSW_F0 (1);
736 }
737 else if (tmp < SEXT40(MIN32))
738 {
739 tmp = (MIN32);
740 SET_PSW_F0 (1);
741 }
742 else
743 {
744 SET_PSW_F0 (0);
745 }
746 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
747 SET_GPR (OP[0] + 1, (tmp & 0xffff));
748 trace_output_32 (tmp);
749}
750
751/* addac3s */
752void
753OP_17001202 ()
754{
755 int64 tmp;
756 SET_PSW_F1 (PSW_F0);
757
758 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
759 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
760 if (tmp > SEXT40(MAX32))
761 {
762 tmp = (MAX32);
763 SET_PSW_F0 (1);
764 }
765 else if (tmp < SEXT40(MIN32))
766 {
767 tmp = (MIN32);
768 SET_PSW_F0 (1);
769 }
770 else
771 {
772 SET_PSW_F0 (0);
773 }
774 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
775 SET_GPR (OP[0] + 1, (tmp & 0xffff));
776 trace_output_32 (tmp);
777}
778
779/* addi */
780void
781OP_201 ()
782{
783 uint16 a = GPR (OP[0]);
784 uint16 b;
785 uint16 tmp;
786 if (OP[1] == 0)
787 OP[1] = 16;
788 b = OP[1];
789 tmp = (a + b);
790 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
791 SET_PSW_C (tmp < a);
792 SET_GPR (OP[0], tmp);
793 trace_output_16 (tmp);
794}
795
796/* and */
797void
798OP_C00 ()
799{
800 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
801 trace_input ("and", OP_REG, OP_REG, OP_VOID);
802 SET_GPR (OP[0], tmp);
803 trace_output_16 (tmp);
804}
805
806/* and3 */
807void
808OP_6000000 ()
809{
810 uint16 tmp = GPR (OP[1]) & OP[2];
811 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
812 SET_GPR (OP[0], tmp);
813 trace_output_16 (tmp);
814}
815
816/* bclri */
817void
818OP_C01 ()
819{
820 int16 tmp;
821 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
822 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
823 SET_GPR (OP[0], tmp);
824 trace_output_16 (tmp);
825}
826
827/* bl.s */
828void
829OP_4900 ()
830{
831 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
832 SET_GPR (13, PC + 1);
833 JMP( PC + SEXT8 (OP[0]));
834 trace_output_void ();
835}
836
837/* bl.l */
838void
839OP_24800000 ()
840{
841 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
842 SET_GPR (13, (PC + 1));
843 JMP (PC + OP[0]);
844 trace_output_void ();
845}
846
847/* bnoti */
848void
849OP_A01 ()
850{
851 int16 tmp;
852 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
853 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
854 SET_GPR (OP[0], tmp);
855 trace_output_16 (tmp);
856}
857
858/* bra.s */
859void
860OP_4800 ()
861{
862 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
863 JMP (PC + SEXT8 (OP[0]));
864 trace_output_void ();
865}
866
867/* bra.l */
868void
869OP_24000000 ()
870{
871 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
872 JMP (PC + OP[0]);
873 trace_output_void ();
874}
875
876/* brf0f.s */
877void
878OP_4A00 ()
879{
880 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
881 if (!PSW_F0)
882 JMP (PC + SEXT8 (OP[0]));
883 trace_output_flag ();
884}
885
886/* brf0f.l */
887void
888OP_25000000 ()
889{
890 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
891 if (!PSW_F0)
892 JMP (PC + OP[0]);
893 trace_output_flag ();
894}
895
896/* brf0t.s */
897void
898OP_4B00 ()
899{
900 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
901 if (PSW_F0)
902 JMP (PC + SEXT8 (OP[0]));
903 trace_output_flag ();
904}
905
906/* brf0t.l */
907void
908OP_25800000 ()
909{
910 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
911 if (PSW_F0)
912 JMP (PC + OP[0]);
913 trace_output_flag ();
914}
915
916/* bseti */
917void
918OP_801 ()
919{
920 int16 tmp;
921 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
922 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
923 SET_GPR (OP[0], tmp);
924 trace_output_16 (tmp);
925}
926
927/* btsti */
928void
929OP_E01 ()
930{
931 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
932 SET_PSW_F1 (PSW_F0);
933 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
934 trace_output_flag ();
935}
936
937/* clrac */
938void
939OP_5601 ()
940{
941 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
942 SET_ACC (OP[0], 0);
943 trace_output_40 (0);
944}
945
946/* cmp */
947void
948OP_600 ()
949{
950 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
951 SET_PSW_F1 (PSW_F0);
952 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
953 trace_output_flag ();
954}
955
956/* cmp */
957void
958OP_1603 ()
959{
960 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
961 SET_PSW_F1 (PSW_F0);
962 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
963 trace_output_flag ();
964}
965
966/* cmpeq */
967void
968OP_400 ()
969{
970 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
971 SET_PSW_F1 (PSW_F0);
972 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
973 trace_output_flag ();
974}
975
976/* cmpeq */
977void
978OP_1403 ()
979{
980 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
981 SET_PSW_F1 (PSW_F0);
982 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
983 trace_output_flag ();
984}
985
986/* cmpeqi.s */
987void
988OP_401 ()
989{
990 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
991 SET_PSW_F1 (PSW_F0);
992 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
993 trace_output_flag ();
994}
995
996/* cmpeqi.l */
997void
998OP_2000000 ()
999{
1000 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1001 SET_PSW_F1 (PSW_F0);
1002 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1003 trace_output_flag ();
1004}
1005
1006/* cmpi.s */
1007void
1008OP_601 ()
1009{
1010 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1011 SET_PSW_F1 (PSW_F0);
1012 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1013 trace_output_flag ();
1014}
1015
1016/* cmpi.l */
1017void
1018OP_3000000 ()
1019{
1020 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1021 SET_PSW_F1 (PSW_F0);
1022 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1023 trace_output_flag ();
1024}
1025
1026/* cmpu */
1027void
1028OP_4600 ()
1029{
1030 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1031 SET_PSW_F1 (PSW_F0);
1032 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1033 trace_output_flag ();
1034}
1035
1036/* cmpui */
1037void
1038OP_23000000 ()
1039{
1040 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1041 SET_PSW_F1 (PSW_F0);
1042 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1043 trace_output_flag ();
1044}
1045
1046/* cpfg */
1047void
1048OP_4E09 ()
1049{
1050 uint8 val;
1051
1052 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1053
1054 if (OP[1] == 0)
1055 val = PSW_F0;
1056 else if (OP[1] == 1)
1057 val = PSW_F1;
1058 else
1059 val = PSW_C;
1060 if (OP[0] == 0)
1061 SET_PSW_F0 (val);
1062 else
1063 SET_PSW_F1 (val);
1064
1065 trace_output_flag ();
1066}
1067
1068/* dbt */
1069void
1070OP_5F20 ()
1071{
1072 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1073
1074 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1075 The conditional below is for either of the instruction pairs
1076 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1077 where the dbt instruction should be interpreted.
1078
1079 The module `sim-break' provides a more effective mechanism for
1080 detecting GDB planted breakpoints. The code below may,
1081 eventually, be changed to use that mechanism. */
1082
1083 if (State.ins_type == INS_LEFT
1084 || State.ins_type == INS_RIGHT)
1085 {
1086 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1087 SET_DPC (PC + 1);
1088 SET_DPSW (PSW);
1089 SET_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1090 JMP (DBT_VECTOR_START);
1091 trace_output_void ();
1092 }
1093 else
1094 {
1095 State.exception = SIGTRAP;
1096 }
1097}
1098
1099/* divs */
1100void
1101OP_14002800 ()
1102{
1103 uint16 foo, tmp, tmpf;
1104 uint16 hi;
1105 uint16 lo;
1106
1107 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1108 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1109 tmp = (int16)foo - (int16)(GPR (OP[1]));
1110 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1111 hi = ((tmpf == 1) ? tmp : foo);
1112 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1113 SET_GPR (OP[0] + 0, hi);
1114 SET_GPR (OP[0] + 1, lo);
1115 trace_output_32 (((uint32) hi << 16) | lo);
1116}
1117
1118/* exef0f */
1119void
1120OP_4E04 ()
1121{
1122 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1123 State.exe = (PSW_F0 == 0);
1124 trace_output_flag ();
1125}
1126
1127/* exef0t */
1128void
1129OP_4E24 ()
1130{
1131 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1132 State.exe = (PSW_F0 != 0);
1133 trace_output_flag ();
1134}
1135
1136/* exef1f */
1137void
1138OP_4E40 ()
1139{
1140 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1141 State.exe = (PSW_F1 == 0);
1142 trace_output_flag ();
1143}
1144
1145/* exef1t */
1146void
1147OP_4E42 ()
1148{
1149 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1150 State.exe = (PSW_F1 != 0);
1151 trace_output_flag ();
1152}
1153
1154/* exefaf */
1155void
1156OP_4E00 ()
1157{
1158 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1159 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1160 trace_output_flag ();
1161}
1162
1163/* exefat */
1164void
1165OP_4E02 ()
1166{
1167 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1168 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1169 trace_output_flag ();
1170}
1171
1172/* exetaf */
1173void
1174OP_4E20 ()
1175{
1176 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1177 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1178 trace_output_flag ();
1179}
1180
1181/* exetat */
1182void
1183OP_4E22 ()
1184{
1185 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1186 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1187 trace_output_flag ();
1188}
1189
1190/* exp */
1191void
1192OP_15002A00 ()
1193{
1194 uint32 tmp, foo;
1195 int i;
1196
1197 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1198 if (((int16)GPR (OP[1])) >= 0)
1199 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1200 else
1201 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1202
1203 foo = 0x40000000;
1204 for (i=1;i<17;i++)
1205 {
1206 if (tmp & foo)
1207 {
1208 SET_GPR (OP[0], (i - 1));
1209 trace_output_16 (i - 1);
1210 return;
1211 }
1212 foo >>= 1;
1213 }
1214 SET_GPR (OP[0], 16);
1215 trace_output_16 (16);
1216}
1217
1218/* exp */
1219void
1220OP_15002A02 ()
1221{
1222 int64 tmp, foo;
1223 int i;
1224
1225 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1226 tmp = SEXT40(ACC (OP[1]));
1227 if (tmp < 0)
1228 tmp = ~tmp & MASK40;
1229
1230 foo = 0x4000000000LL;
1231 for (i=1;i<25;i++)
1232 {
1233 if (tmp & foo)
1234 {
1235 SET_GPR (OP[0], i - 9);
1236 trace_output_16 (i - 9);
1237 return;
1238 }
1239 foo >>= 1;
1240 }
1241 SET_GPR (OP[0], 16);
1242 trace_output_16 (16);
1243}
1244
1245/* jl */
1246void
1247OP_4D00 ()
1248{
1249 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1250 SET_GPR (13, PC + 1);
1251 JMP (GPR (OP[0]));
1252 trace_output_void ();
1253}
1254
1255/* jmp */
1256void
1257OP_4C00 ()
1258{
1259 trace_input ("jmp", OP_REG,
1260 (OP[0] == 13) ? OP_R0 : OP_VOID,
1261 (OP[0] == 13) ? OP_R1 : OP_VOID);
1262
1263 JMP (GPR (OP[0]));
1264 trace_output_void ();
1265}
1266
1267/* ld */
1268void
1269OP_30000000 ()
1270{
1271 uint16 tmp;
1272 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1273 tmp = RW (OP[1] + GPR (OP[2]));
1274 SET_GPR (OP[0], tmp);
1275 trace_output_16 (tmp);
1276}
1277
1278/* ld */
1279void
1280OP_6401 ()
1281{
1282 uint16 tmp;
1283 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1284 tmp = RW (GPR (OP[1]));
1285 SET_GPR (OP[0], tmp);
1286 if (OP[0] != OP[1])
1287 INC_ADDR (OP[1], -2);
1288 trace_output_16 (tmp);
1289}
1290
1291/* ld */
1292void
1293OP_6001 ()
1294{
1295 uint16 tmp;
1296 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1297 tmp = RW (GPR (OP[1]));
1298 SET_GPR (OP[0], tmp);
1299 if (OP[0] != OP[1])
1300 INC_ADDR (OP[1], 2);
1301 trace_output_16 (tmp);
1302}
1303
1304/* ld */
1305void
1306OP_6000 ()
1307{
1308 uint16 tmp;
1309 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1310 tmp = RW (GPR (OP[1]));
1311 SET_GPR (OP[0], tmp);
1312 trace_output_16 (tmp);
1313}
1314
1315/* ld2w */
1316void
1317OP_31000000 ()
1318{
1319 int32 tmp;
1320 uint16 addr = GPR (OP[2]);
1321 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1322 tmp = RLW (OP[1] + addr);
1323 SET_GPR32 (OP[0], tmp);
1324 trace_output_32 (tmp);
1325}
1326
1327/* ld2w */
1328void
1329OP_6601 ()
1330{
1331 uint16 addr = GPR (OP[1]);
1332 int32 tmp;
1333 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1334 tmp = RLW (addr);
1335 SET_GPR32 (OP[0], tmp);
d4f3574e 1336 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
7a292a7a 1337 INC_ADDR (OP[1], -4);
c906108c
SS		 1338 trace_output_32 (tmp);
1339}
1340
1341/* ld2w */
1342void
1343OP_6201 ()
1344{
1345 int32 tmp;
1346 uint16 addr = GPR (OP[1]);
1347 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1348 tmp = RLW (addr);
1349 SET_GPR32 (OP[0], tmp);
d4f3574e 1350 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
7a292a7a 1351 INC_ADDR (OP[1], 4);
c906108c
SS		 1352 trace_output_32 (tmp);
1353}
1354
1355/* ld2w */
1356void
1357OP_6200 ()
1358{
1359 uint16 addr = GPR (OP[1]);
1360 int32 tmp;
1361 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1362 tmp = RLW (addr + 0);
1363 SET_GPR32 (OP[0], tmp);
1364 trace_output_32 (tmp);
1365}
1366
1367/* ldb */
1368void
1369OP_38000000 ()
1370{
1371 int16 tmp;
1372 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1373 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1374 SET_GPR (OP[0], tmp);
1375 trace_output_16 (tmp);
1376}
1377
1378/* ldb */
1379void
1380OP_7000 ()
1381{
1382 int16 tmp;
1383 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1384 tmp = SEXT8 (RB (GPR (OP[1])));
1385 SET_GPR (OP[0], tmp);
1386 trace_output_16 (tmp);
1387}
1388
1389/* ldi.s */
1390void
1391OP_4001 ()
1392{
1393 int16 tmp;
1394 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1395 tmp = SEXT4 (OP[1]);
1396 SET_GPR (OP[0], tmp);
1397 trace_output_16 (tmp);
1398}
1399
1400/* ldi.l */
1401void
1402OP_20000000 ()
1403{
1404 int16 tmp;
1405 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1406 tmp = OP[1];
1407 SET_GPR (OP[0], tmp);
1408 trace_output_16 (tmp);
1409}
1410
1411/* ldub */
1412void
1413OP_39000000 ()
1414{
1415 int16 tmp;
1416 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1417 tmp = RB (OP[1] + GPR (OP[2]));
1418 SET_GPR (OP[0], tmp);
1419 trace_output_16 (tmp);
1420}
1421
1422/* ldub */
1423void
1424OP_7200 ()
1425{
1426 int16 tmp;
1427 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1428 tmp = RB (GPR (OP[1]));
1429 SET_GPR (OP[0], tmp);
1430 trace_output_16 (tmp);
1431}
1432
1433/* mac */
1434void
1435OP_2A00 ()
1436{
1437 int64 tmp;
1438
1439 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1440 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1441
1442 if (PSW_FX)
1443 tmp = SEXT40( (tmp << 1) & MASK40);
1444
1445 if (PSW_ST && tmp > SEXT40(MAX32))
1446 tmp = (MAX32);
1447
1448 tmp += SEXT40 (ACC (OP[0]));
1449 if (PSW_ST)
1450 {
1451 if (tmp > SEXT40(MAX32))
1452 tmp = (MAX32);
1453 else if (tmp < SEXT40(MIN32))
1454 tmp = (MIN32);
1455 else
1456 tmp = (tmp & MASK40);
1457 }
1458 else
1459 tmp = (tmp & MASK40);
1460 SET_ACC (OP[0], tmp);
1461 trace_output_40 (tmp);
1462}
1463
1464/* macsu */
1465void
1466OP_1A00 ()
1467{
1468 int64 tmp;
1469
1470 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1471 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1472 if (PSW_FX)
1473 tmp = SEXT40 ((tmp << 1) & MASK40);
1474 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1475 SET_ACC (OP[0], tmp);
1476 trace_output_40 (tmp);
1477}
1478
1479/* macu */
1480void
1481OP_3A00 ()
1482{
1483 uint64 tmp;
1484 uint32 src1;
1485 uint32 src2;
1486
1487 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1488 src1 = (uint16) GPR (OP[1]);
1489 src2 = (uint16) GPR (OP[2]);
1490 tmp = src1 * src2;
1491 if (PSW_FX)
1492 tmp = (tmp << 1);
1493 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1494 SET_ACC (OP[0], tmp);
1495 trace_output_40 (tmp);
1496}
1497
1498/* max */
1499void
1500OP_2600 ()
1501{
1502 int16 tmp;
1503 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1504 SET_PSW_F1 (PSW_F0);
1505 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1506 {
1507 tmp = GPR (OP[1]);
1508 SET_PSW_F0 (1);
1509 }
1510 else
1511 {
1512 tmp = GPR (OP[0]);
1513 SET_PSW_F0 (0);
1514 }
1515 SET_GPR (OP[0], tmp);
1516 trace_output_16 (tmp);
1517}
1518
1519/* max */
1520void
1521OP_3600 ()
1522{
1523 int64 tmp;
1524
1525 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1526 SET_PSW_F1 (PSW_F0);
1527 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1528 if (tmp > SEXT40 (ACC (OP[0])))
1529 {
1530 tmp = (tmp & MASK40);
1531 SET_PSW_F0 (1);
1532 }
1533 else
1534 {
1535 tmp = ACC (OP[0]);
1536 SET_PSW_F0 (0);
1537 }
1538 SET_ACC (OP[0], tmp);
1539 trace_output_40 (tmp);
1540}
1541
1542/* max */
1543void
1544OP_3602 ()
1545{
1546 int64 tmp;
1547 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1548 SET_PSW_F1 (PSW_F0);
1549 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1550 {
1551 tmp = ACC (OP[1]);
1552 SET_PSW_F0 (1);
1553 }
1554 else
1555 {
1556 tmp = ACC (OP[0]);
1557 SET_PSW_F0 (0);
1558 }
1559 SET_ACC (OP[0], tmp);
1560 trace_output_40 (tmp);
1561}
1562
1563
1564/* min */
1565void
1566OP_2601 ()
1567{
1568 int16 tmp;
1569 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1570 SET_PSW_F1 (PSW_F0);
1571 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1572 {
1573 tmp = GPR (OP[1]);
1574 SET_PSW_F0 (1);
1575 }
1576 else
1577 {
1578 tmp = GPR (OP[0]);
1579 SET_PSW_F0 (0);
1580 }
1581 SET_GPR (OP[0], tmp);
1582 trace_output_16 (tmp);
1583}
1584
1585/* min */
1586void
1587OP_3601 ()
1588{
1589 int64 tmp;
1590
1591 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1592 SET_PSW_F1 (PSW_F0);
1593 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1594 if (tmp < SEXT40(ACC (OP[0])))
1595 {
1596 tmp = (tmp & MASK40);
1597 SET_PSW_F0 (1);
1598 }
1599 else
1600 {
1601 tmp = ACC (OP[0]);
1602 SET_PSW_F0 (0);
1603 }
1604 SET_ACC (OP[0], tmp);
1605 trace_output_40 (tmp);
1606}
1607
1608/* min */
1609void
1610OP_3603 ()
1611{
1612 int64 tmp;
1613 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1614 SET_PSW_F1 (PSW_F0);
1615 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1616 {
1617 tmp = ACC (OP[1]);
1618 SET_PSW_F0 (1);
1619 }
1620 else
1621 {
1622 tmp = ACC (OP[0]);
1623 SET_PSW_F0 (0);
1624 }
1625 SET_ACC (OP[0], tmp);
1626 trace_output_40 (tmp);
1627}
1628
1629/* msb */
1630void
1631OP_2800 ()
1632{
1633 int64 tmp;
1634
1635 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1636 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1637
1638 if (PSW_FX)
1639 tmp = SEXT40 ((tmp << 1) & MASK40);
1640
1641 if (PSW_ST && tmp > SEXT40(MAX32))
1642 tmp = (MAX32);
1643
1644 tmp = SEXT40(ACC (OP[0])) - tmp;
1645 if (PSW_ST)
1646 {
1647 if (tmp > SEXT40(MAX32))
1648 tmp = (MAX32);
1649 else if (tmp < SEXT40(MIN32))
1650 tmp = (MIN32);
1651 else
1652 tmp = (tmp & MASK40);
1653 }
1654 else
1655 {
1656 tmp = (tmp & MASK40);
1657 }
1658 SET_ACC (OP[0], tmp);
1659 trace_output_40 (tmp);
1660}
1661
1662/* msbsu */
1663void
1664OP_1800 ()
1665{
1666 int64 tmp;
1667
1668 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1669 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1670 if (PSW_FX)
1671 tmp = SEXT40( (tmp << 1) & MASK40);
1672 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1673 SET_ACC (OP[0], tmp);
1674 trace_output_40 (tmp);
1675}
1676
1677/* msbu */
1678void
1679OP_3800 ()
1680{
1681 uint64 tmp;
1682 uint32 src1;
1683 uint32 src2;
1684
1685 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1686 src1 = (uint16) GPR (OP[1]);
1687 src2 = (uint16) GPR (OP[2]);
1688 tmp = src1 * src2;
1689 if (PSW_FX)
1690 tmp = (tmp << 1);
1691 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1692 SET_ACC (OP[0], tmp);
1693 trace_output_40 (tmp);
1694}
1695
1696/* mul */
1697void
1698OP_2E00 ()
1699{
1700 int16 tmp;
1701 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1702 tmp = GPR (OP[0]) * GPR (OP[1]);
1703 SET_GPR (OP[0], tmp);
1704 trace_output_16 (tmp);
1705}
1706
1707/* mulx */
1708void
1709OP_2C00 ()
1710{
1711 int64 tmp;
1712
1713 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1714 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1715
1716 if (PSW_FX)
1717 tmp = SEXT40 ((tmp << 1) & MASK40);
1718
1719 if (PSW_ST && tmp > SEXT40(MAX32))
1720 tmp = (MAX32);
1721 else
1722 tmp = (tmp & MASK40);
1723 SET_ACC (OP[0], tmp);
1724 trace_output_40 (tmp);
1725}
1726
1727/* mulxsu */
1728void
1729OP_1C00 ()
1730{
1731 int64 tmp;
1732
1733 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1734 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1735
1736 if (PSW_FX)
1737 tmp <<= 1;
1738 tmp = (tmp & MASK40);
1739 SET_ACC (OP[0], tmp);
1740 trace_output_40 (tmp);
1741}
1742
1743/* mulxu */
1744void
1745OP_3C00 ()
1746{
1747 uint64 tmp;
1748 uint32 src1;
1749 uint32 src2;
1750
1751 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1752 src1 = (uint16) GPR (OP[1]);
1753 src2 = (uint16) GPR (OP[2]);
1754 tmp = src1 * src2;
1755 if (PSW_FX)
1756 tmp <<= 1;
1757 tmp = (tmp & MASK40);
1758 SET_ACC (OP[0], tmp);
1759 trace_output_40 (tmp);
1760}
1761
1762/* mv */
1763void
1764OP_4000 ()
1765{
1766 int16 tmp;
1767 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1768 tmp = GPR (OP[1]);
1769 SET_GPR (OP[0], tmp);
1770 trace_output_16 (tmp);
1771}
1772
1773/* mv2w */
1774void
1775OP_5000 ()
1776{
1777 int32 tmp;
1778 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1779 tmp = GPR32 (OP[1]);
1780 SET_GPR32 (OP[0], tmp);
1781 trace_output_32 (tmp);
1782}
1783
1784/* mv2wfac */
1785void
1786OP_3E00 ()
1787{
1788 int32 tmp;
1789 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1790 tmp = ACC (OP[1]);
1791 SET_GPR32 (OP[0], tmp);
1792 trace_output_32 (tmp);
1793}
1794
1795/* mv2wtac */
1796void
1797OP_3E01 ()
1798{
1799 int64 tmp;
1800 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1801 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1802 SET_ACC (OP[1], tmp);
1803 trace_output_40 (tmp);
1804}
1805
1806/* mvac */
1807void
1808OP_3E03 ()
1809{
1810 int64 tmp;
1811 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1812 tmp = ACC (OP[1]);
1813 SET_ACC (OP[0], tmp);
1814 trace_output_40 (tmp);
1815}
1816
1817/* mvb */
1818void
1819OP_5400 ()
1820{
1821 int16 tmp;
1822 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1823 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1824 SET_GPR (OP[0], tmp);
1825 trace_output_16 (tmp);
1826}
1827
1828/* mvf0f */
1829void
1830OP_4400 ()
1831{
1832 int16 tmp;
1833 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1834 if (PSW_F0 == 0)
1835 {
1836 tmp = GPR (OP[1]);
1837 SET_GPR (OP[0], tmp);
1838 }
1839 else
1840 tmp = GPR (OP[0]);
1841 trace_output_16 (tmp);
1842}
1843
1844/* mvf0t */
1845void
1846OP_4401 ()
1847{
1848 int16 tmp;
1849 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1850 if (PSW_F0)
1851 {
1852 tmp = GPR (OP[1]);
1853 SET_GPR (OP[0], tmp);
1854 }
1855 else
1856 tmp = GPR (OP[0]);
1857 trace_output_16 (tmp);
1858}
1859
1860/* mvfacg */
1861void
1862OP_1E04 ()
1863{
1864 int16 tmp;
1865 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1866 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1867 SET_GPR (OP[0], tmp);
1868 trace_output_16 (tmp);
1869}
1870
1871/* mvfachi */
1872void
1873OP_1E00 ()
1874{
1875 int16 tmp;
1876 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1877 tmp = (ACC (OP[1]) >> 16);
1878 SET_GPR (OP[0], tmp);
1879 trace_output_16 (tmp);
1880}
1881
1882/* mvfaclo */
1883void
1884OP_1E02 ()
1885{
1886 int16 tmp;
1887 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1888 tmp = ACC (OP[1]);
1889 SET_GPR (OP[0], tmp);
1890 trace_output_16 (tmp);
1891}
1892
1893/* mvfc */
1894void
1895OP_5200 ()
1896{
1897 int16 tmp;
1898 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1899 tmp = CREG (OP[1]);
1900 SET_GPR (OP[0], tmp);
1901 trace_output_16 (tmp);
1902}
1903
1904/* mvtacg */
1905void
1906OP_1E41 ()
1907{
1908 int64 tmp;
1909 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1910 tmp = ((ACC (OP[1]) & MASK32)
1911 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1912 SET_ACC (OP[1], tmp);
1913 trace_output_40 (tmp);
1914}
1915
1916/* mvtachi */
1917void
1918OP_1E01 ()
1919{
1920 uint64 tmp;
1921 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1922 tmp = ACC (OP[1]) & 0xffff;
1923 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1924 SET_ACC (OP[1], tmp);
1925 trace_output_40 (tmp);
1926}
1927
1928/* mvtaclo */
1929void
1930OP_1E21 ()
1931{
1932 int64 tmp;
1933 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1934 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1935 SET_ACC (OP[1], tmp);
1936 trace_output_40 (tmp);
1937}
1938
1939/* mvtc */
1940void
1941OP_5600 ()
1942{
1943 int16 tmp;
1944 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1945 tmp = GPR (OP[0]);
1946 tmp = SET_CREG (OP[1], tmp);
1947 trace_output_16 (tmp);
1948}
1949
1950/* mvub */
1951void
1952OP_5401 ()
1953{
1954 int16 tmp;
1955 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1956 tmp = (GPR (OP[1]) & 0xff);
1957 SET_GPR (OP[0], tmp);
1958 trace_output_16 (tmp);
1959}
1960
1961/* neg */
1962void
1963OP_4605 ()
1964{
1965 int16 tmp;
1966 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1967 tmp = - GPR (OP[0]);
1968 SET_GPR (OP[0], tmp);
1969 trace_output_16 (tmp);
1970}
1971
1972/* neg */
1973void
1974OP_5605 ()
1975{
1976 int64 tmp;
1977
1978 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1979 tmp = -SEXT40(ACC (OP[0]));
1980 if (PSW_ST)
1981 {
1982 if (tmp > SEXT40(MAX32))
1983 tmp = (MAX32);
1984 else if (tmp < SEXT40(MIN32))
1985 tmp = (MIN32);
1986 else
1987 tmp = (tmp & MASK40);
1988 }
1989 else
1990 tmp = (tmp & MASK40);
1991 SET_ACC (OP[0], tmp);
1992 trace_output_40 (tmp);
1993}
1994
1995
1996/* nop */
1997void
1998OP_5E00 ()
1999{
2000 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2001
2002 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2003 switch (State.ins_type)
2004 {
2005 default:
2006 ins_type_counters[ (int)INS_UNKNOWN ]++;
2007 break;
2008
2009 case INS_LEFT_PARALLEL:
2010 /* Don't count a parallel op that includes a NOP as a true parallel op */
2011 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2012 ins_type_counters[ (int)INS_RIGHT ]++;
2013 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2014 break;
2015
2016 case INS_LEFT:
2017 case INS_LEFT_COND_EXE:
2018 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2019 break;
2020
2021 case INS_RIGHT_PARALLEL:
2022 /* Don't count a parallel op that includes a NOP as a true parallel op */
2023 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2024 ins_type_counters[ (int)INS_LEFT ]++;
2025 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2026 break;
2027
2028 case INS_RIGHT:
2029 case INS_RIGHT_COND_EXE:
2030 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2031 break;
2032 }
2033
2034 trace_output_void ();
2035}
2036
2037/* not */
2038void
2039OP_4603 ()
2040{
2041 int16 tmp;
2042 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2043 tmp = ~GPR (OP[0]);
2044 SET_GPR (OP[0], tmp);
2045 trace_output_16 (tmp);
2046}
2047
2048/* or */
2049void
2050OP_800 ()
2051{
2052 int16 tmp;
2053 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2054 tmp = (GPR (OP[0]) | GPR (OP[1]));
2055 SET_GPR (OP[0], tmp);
2056 trace_output_16 (tmp);
2057}
2058
2059/* or3 */
2060void
2061OP_4000000 ()
2062{
2063 int16 tmp;
2064 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2065 tmp = (GPR (OP[1]) | OP[2]);
2066 SET_GPR (OP[0], tmp);
2067 trace_output_16 (tmp);
2068}
2069
2070/* rac */
2071void
2072OP_5201 ()
2073{
2074 int64 tmp;
2075 int shift = SEXT3 (OP[2]);
2076
2077 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2078 if (OP[1] != 0)
2079 {
2080 (*d10v_callback->printf_filtered) (d10v_callback,
2081 "ERROR at PC 0x%x: instruction only valid for A0\n",
2082 PC<<2);
2083 State.exception = SIGILL;
2084 }
2085
2086 SET_PSW_F1 (PSW_F0);
2087 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2088 if (shift >=0)
2089 tmp <<= shift;
2090 else
2091 tmp >>= -shift;
2092 tmp += 0x8000;
2093 tmp >>= 16; /* look at bits 0:43 */
2094 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2095 {
2096 tmp = 0x7fffffff;
2097 SET_PSW_F0 (1);
2098 }
2099 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2100 {
2101 tmp = 0x80000000;
2102 SET_PSW_F0 (1);
2103 }
2104 else
2105 {
2106 SET_PSW_F0 (0);
2107 }
2108 SET_GPR32 (OP[0], tmp);
2109 trace_output_32 (tmp);
2110}
2111
2112/* rachi */
2113void
2114OP_4201 ()
2115{
2116 signed64 tmp;
2117 int shift = SEXT3 (OP[2]);
2118
2119 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2120 SET_PSW_F1 (PSW_F0);
2121 if (shift >=0)
2122 tmp = SEXT40 (ACC (OP[1])) << shift;
2123 else
2124 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2125 tmp += 0x8000;
2126
2127 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2128 {
2129 tmp = 0x7fff;
2130 SET_PSW_F0 (1);
2131 }
2132 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2133 {
2134 tmp = 0x8000;
2135 SET_PSW_F0 (1);
2136 }
2137 else
2138 {
2139 tmp = (tmp >> 16);
2140 SET_PSW_F0 (0);
2141 }
2142 SET_GPR (OP[0], tmp);
2143 trace_output_16 (tmp);
2144}
2145
2146/* rep */
2147void
2148OP_27000000 ()
2149{
2150 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2151 SET_RPT_S (PC + 1);
2152 SET_RPT_E (PC + OP[1]);
2153 SET_RPT_C (GPR (OP[0]));
2154 SET_PSW_RP (1);
2155 if (GPR (OP[0]) == 0)
2156 {
2157 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2158 State.exception = SIGILL;
2159 }
2160 if (OP[1] < 4)
2161 {
2162 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2163 State.exception = SIGILL;
2164 }
2165 trace_output_void ();
2166}
2167
2168/* repi */
2169void
2170OP_2F000000 ()
2171{
2172 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2173 SET_RPT_S (PC + 1);
2174 SET_RPT_E (PC + OP[1]);
2175 SET_RPT_C (OP[0]);
2176 SET_PSW_RP (1);
2177 if (OP[0] == 0)
2178 {
2179 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2180 State.exception = SIGILL;
2181 }
2182 if (OP[1] < 4)
2183 {
2184 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2185 State.exception = SIGILL;
2186 }
2187 trace_output_void ();
2188}
2189
2190/* rtd */
2191void
2192OP_5F60 ()
2193{
2194 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2195 SET_CREG (PSW_CR, DPSW);
2196 JMP(DPC);
2197 trace_output_void ();
2198}
2199
2200/* rte */
2201void
2202OP_5F40 ()
2203{
2204 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2205 SET_CREG (PSW_CR, BPSW);
2206 JMP(BPC);
2207 trace_output_void ();
2208}
2209
2210/* sadd */
2211void
2212OP_1223 ()
2213{
2214 int64 tmp;
2215
2216 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2217 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2218 if (PSW_ST)
2219 {
2220 if (tmp > SEXT40(MAX32))
2221 tmp = (MAX32);
2222 else if (tmp < SEXT40(MIN32))
2223 tmp = (MIN32);
2224 else
2225 tmp = (tmp & MASK40);
2226 }
2227 else
2228 tmp = (tmp & MASK40);
2229 SET_ACC (OP[0], tmp);
2230 trace_output_40 (tmp);
2231}
2232
2233/* setf0f */
2234void
2235OP_4611 ()
2236{
2237 int16 tmp;
2238 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2239 tmp = ((PSW_F0 == 0) ? 1 : 0);
2240 SET_GPR (OP[0], tmp);
2241 trace_output_16 (tmp);
2242}
2243
2244/* setf0t */
2245void
2246OP_4613 ()
2247{
2248 int16 tmp;
2249 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2250 tmp = ((PSW_F0 == 1) ? 1 : 0);
2251 SET_GPR (OP[0], tmp);
2252 trace_output_16 (tmp);
2253}
2254
2255/* sleep */
2256void
2257OP_5FC0 ()
2258{
2259 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2260 SET_PSW_IE (1);
2261 trace_output_void ();
2262}
2263
2264/* sll */
2265void
2266OP_2200 ()
2267{
2268 int16 tmp;
2269 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2270 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2271 SET_GPR (OP[0], tmp);
2272 trace_output_16 (tmp);
2273}
2274
2275/* sll */
2276void
2277OP_3200 ()
2278{
2279 int64 tmp;
2280 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2281 if ((GPR (OP[1]) & 31) <= 16)
2282 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2283 else
2284 {
2285 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2286 State.exception = SIGILL;
2287 return;
2288 }
2289
2290 if (PSW_ST)
2291 {
2292 if (tmp > SEXT40(MAX32))
2293 tmp = (MAX32);
2294 else if (tmp < SEXT40(MIN32))
2295 tmp = (MIN32);
2296 else
2297 tmp = (tmp & MASK40);
2298 }
2299 else
2300 tmp = (tmp & MASK40);
2301 SET_ACC (OP[0], tmp);
2302 trace_output_40 (tmp);
2303}
2304
2305/* slli */
2306void
2307OP_2201 ()
2308{
2309 int16 tmp;
2310 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2311 tmp = (GPR (OP[0]) << OP[1]);
2312 SET_GPR (OP[0], tmp);
2313 trace_output_16 (tmp);
2314}
2315
2316/* slli */
2317void
2318OP_3201 ()
2319{
2320 int64 tmp;
2321
2322 if (OP[1] == 0)
2323 OP[1] = 16;
2324
2325 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2326 tmp = SEXT40(ACC (OP[0])) << OP[1];
2327
2328 if (PSW_ST)
2329 {
2330 if (tmp > SEXT40(MAX32))
2331 tmp = (MAX32);
2332 else if (tmp < SEXT40(MIN32))
2333 tmp = (MIN32);
2334 else
2335 tmp = (tmp & MASK40);
2336 }
2337 else
2338 tmp = (tmp & MASK40);
2339 SET_ACC (OP[0], tmp);
2340 trace_output_40 (tmp);
2341}
2342
2343/* slx */
2344void
2345OP_460B ()
2346{
2347 int16 tmp;
2348 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2349 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2350 SET_GPR (OP[0], tmp);
2351 trace_output_16 (tmp);
2352}
2353
2354/* sra */
2355void
2356OP_2400 ()
2357{
2358 int16 tmp;
2359 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2360 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2361 SET_GPR (OP[0], tmp);
2362 trace_output_16 (tmp);
2363}
2364
2365/* sra */
2366void
2367OP_3400 ()
2368{
2369 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2370 if ((GPR (OP[1]) & 31) <= 16)
2371 {
2372 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2373 SET_ACC (OP[0], tmp);
2374 trace_output_40 (tmp);
2375 }
2376 else
2377 {
2378 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2379 State.exception = SIGILL;
2380 return;
2381 }
2382}
2383
2384/* srai */
2385void
2386OP_2401 ()
2387{
2388 int16 tmp;
2389 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2390 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2391 SET_GPR (OP[0], tmp);
2392 trace_output_16 (tmp);
2393}
2394
2395/* srai */
2396void
2397OP_3401 ()
2398{
2399 int64 tmp;
2400 if (OP[1] == 0)
2401 OP[1] = 16;
2402
2403 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2404 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2405 SET_ACC (OP[0], tmp);
2406 trace_output_40 (tmp);
2407}
2408
2409/* srl */
2410void
2411OP_2000 ()
2412{
2413 int16 tmp;
2414 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2415 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2416 SET_GPR (OP[0], tmp);
2417 trace_output_16 (tmp);
2418}
2419
2420/* srl */
2421void
2422OP_3000 ()
2423{
2424 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2425 if ((GPR (OP[1]) & 31) <= 16)
2426 {
2427 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2428 SET_ACC (OP[0], tmp);
2429 trace_output_40 (tmp);
2430 }
2431 else
2432 {
2433 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2434 State.exception = SIGILL;
2435 return;
2436 }
2437
2438}
2439
2440/* srli */
2441void
2442OP_2001 ()
2443{
2444 int16 tmp;
2445 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2446 tmp = (GPR (OP[0]) >> OP[1]);
2447 SET_GPR (OP[0], tmp);
2448 trace_output_16 (tmp);
2449}
2450
2451/* srli */
2452void
2453OP_3001 ()
2454{
2455 int64 tmp;
2456 if (OP[1] == 0)
2457 OP[1] = 16;
2458
2459 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2460 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2461 SET_ACC (OP[0], tmp);
2462 trace_output_40 (tmp);
2463}
2464
2465/* srx */
2466void
2467OP_4609 ()
2468{
2469 uint16 tmp;
2470 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2471 tmp = PSW_F0 << 15;
2472 tmp = ((GPR (OP[0]) >> 1) | tmp);
2473 SET_GPR (OP[0], tmp);
2474 trace_output_16 (tmp);
2475}
2476
2477/* st */
2478void
2479OP_34000000 ()
2480{
2481 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2482 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2483 trace_output_void ();
2484}
2485
2486/* st */
2487void
2488OP_6800 ()
2489{
2490 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2491 SW (GPR (OP[1]), GPR (OP[0]));
2492 trace_output_void ();
2493}
2494
2495/* st */
2496void
2497OP_6C1F ()
2498{
2499 uint16 addr = GPR (OP[1]) - 2;
2500 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2501 if (OP[1] != 15)
2502 {
2503 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2504 State.exception = SIGILL;
2505 return;
2506 }
2507 SW (addr, GPR (OP[0]));
2508 SET_GPR (OP[1], addr);
2509 trace_output_void ();
2510}
2511
2512/* st */
2513void
2514OP_6801 ()
2515{
2516 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2517 SW (GPR (OP[1]), GPR (OP[0]));
2518 INC_ADDR (OP[1], 2);
2519 trace_output_void ();
2520}
2521
2522/* st */
2523void
2524OP_6C01 ()
2525{
2526 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2527 if ( OP[1] == 15 )
2528 {
2529 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2530 State.exception = SIGILL;
2531 return;
2532 }
2533 SW (GPR (OP[1]), GPR (OP[0]));
2534 INC_ADDR (OP[1], -2);
2535 trace_output_void ();
2536}
2537
2538/* st2w */
2539void
2540OP_35000000 ()
2541{
2542 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2543 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2544 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2545 trace_output_void ();
2546}
2547
2548/* st2w */
2549void
2550OP_6A00 ()
2551{
2552 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2553 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2554 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2555 trace_output_void ();
2556}
2557
2558/* st2w */
2559void
2560OP_6E1F ()
2561{
2562 uint16 addr = GPR (OP[1]) - 4;
2563 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2564 if ( OP[1] != 15 )
2565 {
2566 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2567 State.exception = SIGILL;
2568 return;
2569 }
2570 SW (addr + 0, GPR (OP[0] + 0));
2571 SW (addr + 2, GPR (OP[0] + 1));
2572 SET_GPR (OP[1], addr);
2573 trace_output_void ();
2574}
2575
2576/* st2w */
2577void
2578OP_6A01 ()
2579{
2580 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2581 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2582 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2583 INC_ADDR (OP[1], 4);
2584 trace_output_void ();
2585}
2586
2587/* st2w */
2588void
2589OP_6E01 ()
2590{
2591 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2592 if ( OP[1] == 15 )
2593 {
2594 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2595 State.exception = SIGILL;
2596 return;
2597 }
2598 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2599 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2600 INC_ADDR (OP[1], -4);
2601 trace_output_void ();
2602}
2603
2604/* stb */
2605void
2606OP_3C000000 ()
2607{
2608 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2609 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2610 trace_output_void ();
2611}
2612
2613/* stb */
2614void
2615OP_7800 ()
2616{
2617 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2618 SB (GPR (OP[1]), GPR (OP[0]));
2619 trace_output_void ();
2620}
2621
2622/* stop */
2623void
2624OP_5FE0 ()
2625{
2626 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2627 State.exception = SIG_D10V_STOP;
2628 trace_output_void ();
2629}
2630
2631/* sub */
2632void
2633OP_0 ()
2634{
2635 uint16 a = GPR (OP[0]);
2636 uint16 b = GPR (OP[1]);
2637 uint16 tmp = (a - b);
2638 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2639 /* see ../common/sim-alu.h for a more extensive discussion on how to
2640 compute the carry/overflow bits. */
2641 SET_PSW_C (a >= b);
2642 SET_GPR (OP[0], tmp);
2643 trace_output_16 (tmp);
2644}
2645
2646/* sub */
2647void
2648OP_1001 ()
2649{
2650 int64 tmp;
2651
2652 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2653 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2654 if (PSW_ST)
2655 {
2656 if (tmp > SEXT40(MAX32))
2657 tmp = (MAX32);
2658 else if (tmp < SEXT40(MIN32))
2659 tmp = (MIN32);
2660 else
2661 tmp = (tmp & MASK40);
2662 }
2663 else
2664 tmp = (tmp & MASK40);
2665 SET_ACC (OP[0], tmp);
2666
2667 trace_output_40 (tmp);
2668}
2669
2670/* sub */
2671
2672void
2673OP_1003 ()
2674{
2675 int64 tmp;
2676
2677 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2678 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2679 if (PSW_ST)
2680 {
2681 if (tmp > SEXT40(MAX32))
2682 tmp = (MAX32);
2683 else if (tmp < SEXT40(MIN32))
2684 tmp = (MIN32);
2685 else
2686 tmp = (tmp & MASK40);
2687 }
2688 else
2689 tmp = (tmp & MASK40);
2690 SET_ACC (OP[0], tmp);
2691
2692 trace_output_40 (tmp);
2693}
2694
2695/* sub2w */
2696void
2697OP_1000 ()
2698{
2699 uint32 tmp, a, b;
2700
2701 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2702 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2703 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2704 /* see ../common/sim-alu.h for a more extensive discussion on how to
2705 compute the carry/overflow bits */
2706 tmp = a - b;
2707 SET_PSW_C (a >= b);
2708 SET_GPR32 (OP[0], tmp);
2709 trace_output_32 (tmp);
2710}
2711
2712/* subac3 */
2713void
2714OP_17000000 ()
2715{
2716 int64 tmp;
2717
2718 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2719 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2720 SET_GPR32 (OP[0], tmp);
2721 trace_output_32 (tmp);
2722}
2723
2724/* subac3 */
2725void
2726OP_17000002 ()
2727{
2728 int64 tmp;
2729
2730 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2731 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2732 SET_GPR32 (OP[0], tmp);
2733 trace_output_32 (tmp);
2734}
2735
2736/* subac3s */
2737void
2738OP_17001000 ()
2739{
2740 int64 tmp;
2741
2742 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2743 SET_PSW_F1 (PSW_F0);
2744 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2745 if (tmp > SEXT40(MAX32))
2746 {
2747 tmp = (MAX32);
2748 SET_PSW_F0 (1);
2749 }
2750 else if (tmp < SEXT40(MIN32))
2751 {
2752 tmp = (MIN32);
2753 SET_PSW_F0 (1);
2754 }
2755 else
2756 {
2757 SET_PSW_F0 (0);
2758 }
2759 SET_GPR32 (OP[0], tmp);
2760 trace_output_32 (tmp);
2761}
2762
2763/* subac3s */
2764void
2765OP_17001002 ()
2766{
2767 int64 tmp;
2768
2769 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2770 SET_PSW_F1 (PSW_F0);
2771 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2772 if (tmp > SEXT40(MAX32))
2773 {
2774 tmp = (MAX32);
2775 SET_PSW_F0 (1);
2776 }
2777 else if (tmp < SEXT40(MIN32))
2778 {
2779 tmp = (MIN32);
2780 SET_PSW_F0 (1);
2781 }
2782 else
2783 {
2784 SET_PSW_F0 (0);
2785 }
2786 SET_GPR32 (OP[0], tmp);
2787 trace_output_32 (tmp);
2788}
2789
2790/* subi */
2791void
2792OP_1 ()
2793{
2794 unsigned tmp;
2795 if (OP[1] == 0)
2796 OP[1] = 16;
2797
2798 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2799 /* see ../common/sim-alu.h for a more extensive discussion on how to
2800 compute the carry/overflow bits. */
2801 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2802 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2803 + (unsigned)(unsigned16) ( - OP[1]));
2804 SET_PSW_C (tmp >= (1 << 16));
2805 SET_GPR (OP[0], tmp);
2806 trace_output_16 (tmp);
2807}
2808
2809/* trap */
2810void
2811OP_5F00 ()
2812{
2813 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2814 trace_output_void ();
2815
2816 switch (OP[0])
2817 {
2818 default:
2819#if (DEBUG & DEBUG_TRAP) == 0
2820 {
2821 uint16 vec = OP[0] + TRAP_VECTOR_START;
2822 SET_BPC (PC + 1);
2823 SET_BPSW (PSW);
2824 SET_PSW (PSW & PSW_SM_BIT);
2825 JMP (vec);
2826 break;
2827 }
2828#else /* if debugging use trap to print registers */
2829 {
2830 int i;
2831 static int first_time = 1;
2832
2833 if (first_time)
2834 {
2835 first_time = 0;
2836 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2837 for (i = 0; i < 16; i++)
2838 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2839 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2840 }
2841
2842 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2843
2844 for (i = 0; i < 16; i++)
2845 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
2846
2847 for (i = 0; i < 2; i++)
2848 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2849 ((int)(ACC (i) >> 32) & 0xff),
2850 ((unsigned long) ACC (i)) & 0xffffffff);
2851
2852 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2853 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
2854 (*d10v_callback->flush_stdout) (d10v_callback);
2855 break;
2856 }
2857#endif
2858 case 15: /* new system call trap */
2859 /* Trap 15 is used for simulating low-level I/O */
2860 {
2861 unsigned32 result = 0;
2862 errno = 0;
2863
2864/* Registers passed to trap 0 */
2865
2866#define FUNC GPR (4) /* function number */
2867#define PARM1 GPR (0) /* optional parm 1 */
2868#define PARM2 GPR (1) /* optional parm 2 */
2869#define PARM3 GPR (2) /* optional parm 3 */
2870#define PARM4 GPR (3) /* optional parm 3 */
2871
2872/* Registers set by trap 0 */
2873
2874#define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
2875#define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
2876#define RETERR(X) SET_GPR (4, (X)) /* return error code */
2877
2878/* Turn a pointer in a register into a pointer into real memory. */
2879
2880#define MEMPTR(x) ((char *)(dmem_addr(x)))
2881
2882 switch (FUNC)
2883 {
2884#if !defined(__GO32__) && !defined(_WIN32)
2885 case TARGET_SYS_fork:
2886 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2887 RETVAL (fork ());
2888 trace_output_16 (result);
2889 break;
2890
2891#define getpid() 47
2892 case TARGET_SYS_getpid:
2893 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2894 RETVAL (getpid ());
2895 trace_output_16 (result);
2896 break;
2897
2898 case TARGET_SYS_kill:
2899 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
2900 if (PARM1 == getpid ())
2901 {
2902 trace_output_void ();
2903 State.exception = PARM2;
2904 }
2905 else
2906 {
2907 int os_sig = -1;
2908 switch (PARM2)
2909 {
2910#ifdef SIGHUP
2911 case 1: os_sig = SIGHUP; break;
2912#endif
2913#ifdef SIGINT
2914 case 2: os_sig = SIGINT; break;
2915#endif
2916#ifdef SIGQUIT
2917 case 3: os_sig = SIGQUIT; break;
2918#endif
2919#ifdef SIGILL
2920 case 4: os_sig = SIGILL; break;
2921#endif
2922#ifdef SIGTRAP
2923 case 5: os_sig = SIGTRAP; break;
2924#endif
2925#ifdef SIGABRT
2926 case 6: os_sig = SIGABRT; break;
2927#elif defined(SIGIOT)
2928 case 6: os_sig = SIGIOT; break;
2929#endif
2930#ifdef SIGEMT
2931 case 7: os_sig = SIGEMT; break;
2932#endif
2933#ifdef SIGFPE
2934 case 8: os_sig = SIGFPE; break;
2935#endif
2936#ifdef SIGKILL
2937 case 9: os_sig = SIGKILL; break;
2938#endif
2939#ifdef SIGBUS
2940 case 10: os_sig = SIGBUS; break;
2941#endif
2942#ifdef SIGSEGV
2943 case 11: os_sig = SIGSEGV; break;
2944#endif
2945#ifdef SIGSYS
2946 case 12: os_sig = SIGSYS; break;
2947#endif
2948#ifdef SIGPIPE
2949 case 13: os_sig = SIGPIPE; break;
2950#endif
2951#ifdef SIGALRM
2952 case 14: os_sig = SIGALRM; break;
2953#endif
2954#ifdef SIGTERM
2955 case 15: os_sig = SIGTERM; break;
2956#endif
2957#ifdef SIGURG
2958 case 16: os_sig = SIGURG; break;
2959#endif
2960#ifdef SIGSTOP
2961 case 17: os_sig = SIGSTOP; break;
2962#endif
2963#ifdef SIGTSTP
2964 case 18: os_sig = SIGTSTP; break;
2965#endif
2966#ifdef SIGCONT
2967 case 19: os_sig = SIGCONT; break;
2968#endif
2969#ifdef SIGCHLD
2970 case 20: os_sig = SIGCHLD; break;
2971#elif defined(SIGCLD)
2972 case 20: os_sig = SIGCLD; break;
2973#endif
2974#ifdef SIGTTIN
2975 case 21: os_sig = SIGTTIN; break;
2976#endif
2977#ifdef SIGTTOU
2978 case 22: os_sig = SIGTTOU; break;
2979#endif
2980#ifdef SIGIO
2981 case 23: os_sig = SIGIO; break;
2982#elif defined (SIGPOLL)
2983 case 23: os_sig = SIGPOLL; break;
2984#endif
2985#ifdef SIGXCPU
2986 case 24: os_sig = SIGXCPU; break;
2987#endif
2988#ifdef SIGXFSZ
2989 case 25: os_sig = SIGXFSZ; break;
2990#endif
2991#ifdef SIGVTALRM
2992 case 26: os_sig = SIGVTALRM; break;
2993#endif
2994#ifdef SIGPROF
2995 case 27: os_sig = SIGPROF; break;
2996#endif
2997#ifdef SIGWINCH
2998 case 28: os_sig = SIGWINCH; break;
2999#endif
3000#ifdef SIGLOST
3001 case 29: os_sig = SIGLOST; break;
3002#endif
3003#ifdef SIGUSR1
3004 case 30: os_sig = SIGUSR1; break;
3005#endif
3006#ifdef SIGUSR2
3007 case 31: os_sig = SIGUSR2; break;
3008#endif
3009 }
3010
3011 if (os_sig == -1)
3012 {
3013 trace_output_void ();
3014 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3015 (*d10v_callback->flush_stdout) (d10v_callback);
3016 State.exception = SIGILL;
3017 }
3018 else
3019 {
3020 RETVAL (kill (PARM1, PARM2));
3021 trace_output_16 (result);
3022 }
3023 }
3024 break;
3025
3026 case TARGET_SYS_execve:
3027 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3028 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3029 (char **)MEMPTR (PARM3)));
3030 trace_output_16 (result);
3031 break;
3032
3033#ifdef TARGET_SYS_execv
3034 case TARGET_SYS_execv:
3035 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3036 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3037 trace_output_16 (result);
3038 break;
3039#endif
3040
3041 case TARGET_SYS_pipe:
3042 {
3043 reg_t buf;
3044 int host_fd[2];
3045
3046 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3047 buf = PARM1;
3048 RETVAL (pipe (host_fd));
3049 SW (buf, host_fd[0]);
3050 buf += sizeof(uint16);
3051 SW (buf, host_fd[1]);
3052 trace_output_16 (result);
3053 }
3054 break;
3055
3056#if 0
3057#ifdef TARGET_SYS_wait
3058 case TARGET_SYS_wait:
3059 {
3060 int status;
3061 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3062 RETVAL (wait (&status));
3063 if (PARM1)
3064 SW (PARM1, status);
3065 trace_output_16 (result);
3066 }
3067 break;
3068#endif
3069#endif
3070#else
3071 case TARGET_SYS_getpid:
3072 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3073 RETVAL (1);
3074 trace_output_16 (result);
3075 break;
3076
3077 case TARGET_SYS_kill:
3078 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3079 trace_output_void ();
3080 State.exception = PARM2;
3081 break;
3082#endif
3083
3084 case TARGET_SYS_read:
3085 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3086 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3087 PARM3));
3088 trace_output_16 (result);
3089 break;
3090
3091 case TARGET_SYS_write:
3092 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3093 if (PARM1 == 1)
3094 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3095 MEMPTR (PARM2), PARM3));
3096 else
3097 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3098 MEMPTR (PARM2), PARM3));
3099 trace_output_16 (result);
3100 break;
3101
3102 case TARGET_SYS_lseek:
3103 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3104 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3105 ((((unsigned long) PARM2) << 16)
3106 || (unsigned long) PARM3),
3107 PARM4));
3108 trace_output_32 (result);
3109 break;
3110
3111 case TARGET_SYS_close:
3112 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3113 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3114 trace_output_16 (result);
3115 break;
3116
3117 case TARGET_SYS_open:
3118 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3119 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3120 trace_output_16 (result);
3121 break;
3122
3123 case TARGET_SYS_exit:
3124 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3125 State.exception = SIG_D10V_EXIT;
3126 trace_output_void ();
3127 break;
3128
7a292a7a 3129#ifdef TARGET_SYS_stat
c906108c
SS		 3130 case TARGET_SYS_stat:
3131 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3132 /* stat system call */
3133 {
3134 struct stat host_stat;
3135 reg_t buf;
3136
3137 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3138
3139 buf = PARM2;
3140
3141 /* The hard-coded offsets and sizes were determined by using
3142 * the D10V compiler on a test program that used struct stat.
3143 */
3144 SW (buf, host_stat.st_dev);
3145 SW (buf+2, host_stat.st_ino);
3146 SW (buf+4, host_stat.st_mode);
3147 SW (buf+6, host_stat.st_nlink);
3148 SW (buf+8, host_stat.st_uid);
3149 SW (buf+10, host_stat.st_gid);
3150 SW (buf+12, host_stat.st_rdev);
3151 SLW (buf+16, host_stat.st_size);
3152 SLW (buf+20, host_stat.st_atime);
3153 SLW (buf+28, host_stat.st_mtime);
3154 SLW (buf+36, host_stat.st_ctime);
3155 }
3156 trace_output_16 (result);
3157 break;
7a292a7a 3158#endif
c906108c
SS		 3159
3160 case TARGET_SYS_chown:
3161 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3162 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3163 trace_output_16 (result);
3164 break;
3165
3166 case TARGET_SYS_chmod:
3167 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3168 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3169 trace_output_16 (result);
3170 break;
3171
3172#if 0
3173#ifdef TARGET_SYS_utime
3174 case TARGET_SYS_utime:
3175 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3176 /* Cast the second argument to void *, to avoid type mismatch
3177 if a prototype is present. */
3178 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3179 trace_output_16 (result);
3180 break;
3181#endif
3182#endif
3183
3184#if 0
3185#ifdef TARGET_SYS_time
3186 case TARGET_SYS_time:
3187 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3188 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3189 trace_output_32 (result);
3190 break;
3191#endif
3192#endif
3193
3194 default:
3195 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3196 }
3197 if ((uint16) result == (uint16) -1)
3198 RETERR (d10v_callback->get_errno(d10v_callback));
3199 else
3200 RETERR (0);
3201 break;
3202 }
3203 }
3204}
3205
3206/* tst0i */
3207void
3208OP_7000000 ()
3209{
3210 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3211 SET_PSW_F1 (PSW_F0);;
3212 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3213 trace_output_flag ();
3214}
3215
3216/* tst1i */
3217void
3218OP_F000000 ()
3219{
3220 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3221 SET_PSW_F1 (PSW_F0);
3222 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3223 trace_output_flag ();
3224}
3225
3226/* wait */
3227void
3228OP_5F80 ()
3229{
3230 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3231 SET_PSW_IE (1);
3232 trace_output_void ();
3233}
3234
3235/* xor */
3236void
3237OP_A00 ()
3238{
3239 int16 tmp;
3240 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3241 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3242 SET_GPR (OP[0], tmp);
3243 trace_output_16 (tmp);
3244}
3245
3246/* xor3 */
3247void
3248OP_5000000 ()
3249{
3250 int16 tmp;
3251 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3252 tmp = (GPR (OP[1]) ^ OP[2]);
3253 SET_GPR (OP[0], tmp);
3254 trace_output_16 (tmp);
3255}
3256
GDB Binutils - Deliverables
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