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Make sure there is a trailing space after the instruction
[deliverable/binutils-gdb.git] / sim / d10v / simops.c
CommitLineData
4f425a32 1#include <signal.h>
63a91cfb
MM		 2#include <errno.h>
3#include <sys/types.h>
4#include <sys/stat.h>
5#include <unistd.h>
6
2934d1c9
MH		 7#include "d10v_sim.h"
8#include "simops.h"
8719be26 9#include "sys/syscall.h"
a49a15ad 10#include "bfd.h"
2934d1c9 11
87178dbd
MM		 12enum op_types {
13 OP_VOID,
14 OP_REG,
15 OP_REG_OUTPUT,
16 OP_DREG,
17 OP_DREG_OUTPUT,
18 OP_ACCUM,
19 OP_ACCUM_OUTPUT,
20 OP_ACCUM_REVERSE,
21 OP_CR,
22 OP_CR_OUTPUT,
23 OP_CR_REVERSE,
24 OP_FLAG,
60fc5b72 25 OP_FLAG_OUTPUT,
87178dbd
MM		 26 OP_CONSTANT16,
27 OP_CONSTANT3,
28 OP_CONSTANT4,
29 OP_MEMREF,
30 OP_MEMREF2,
31 OP_POSTDEC,
32 OP_POSTINC,
33 OP_PREDEC
34};
35
7eebfc62 36#ifdef DEBUG
a49a15ad
MM		 37static void trace_input_func PARAMS ((char *name,
38 enum op_types in1,
39 enum op_types in2,
40 enum op_types in3));
87178dbd 41
a49a15ad
MM		 42#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
43
44static void trace_output_func PARAMS ((enum op_types result));
45
46#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
47
48static int init_text_p = 0;
49static asection *text;
50static bfd_vma text_start;
51static bfd_vma text_end;
0535fa1a 52extern bfd *exec_bfd;
87178dbd
MM		 53
54#ifndef SIZE_INSTRUCTION
a49a15ad 55#define SIZE_INSTRUCTION 8
87178dbd
MM		 56#endif
57
58#ifndef SIZE_OPERANDS
a49a15ad 59#define SIZE_OPERANDS 18
87178dbd
MM		 60#endif
61
62#ifndef SIZE_VALUES
63#define SIZE_VALUES 13
64#endif
65
a49a15ad
MM		 66#ifndef SIZE_LOCATION
67#define SIZE_LOCATION 20
68#endif
69
891513ee
MM		 70#ifndef SIZE_PC
71#define SIZE_PC 6
72#endif
73
74#ifndef SIZE_LINE_NUMBER
75#define SIZE_LINE_NUMBER 4
76#endif
77
87178dbd 78static void
a49a15ad 79trace_input_func (name, in1, in2, in3)
87178dbd
MM		 80 char *name;
81 enum op_types in1;
82 enum op_types in2;
83 enum op_types in3;
84{
85 char *comma;
86 enum op_types in[3];
87 int i;
a49a15ad 88 char buf[1024];
87178dbd
MM		 89 char *p;
90 long tmp;
91 char *type;
a49a15ad
MM		 92 asection *s;
93 const char *filename;
94 const char *functionname;
95 unsigned int linenumber;
96 bfd_vma byte_pc;
87178dbd 97
7eebfc62
MM		 98 if ((d10v_debug & DEBUG_TRACE) == 0)
99 return;
100
87178dbd
MM		 101 switch (State.ins_type)
102 {
103 default:
104 case INS_UNKNOWN: type = " ?"; break;
105 case INS_LEFT: type = " L"; break;
106 case INS_RIGHT: type = " R"; break;
107 case INS_LEFT_PARALLEL: type = "*L"; break;
108 case INS_RIGHT_PARALLEL: type = "*R"; break;
109 case INS_LONG: type = " B"; break;
110 }
111
a49a15ad
MM		 112 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
113 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 114 "0x%.*x %s: %-*s ",
891513ee
MM		 115 SIZE_PC, (unsigned)PC,
116 type,
a49a15ad
MM		 117 SIZE_INSTRUCTION, name);
118
119 else
120 {
a49a15ad
MM		 121 if (!init_text_p)
122 {
123 init_text_p = 1;
0535fa1a
MM		 124 for (s = exec_bfd->sections; s; s = s->next)
125 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
a49a15ad
MM		 126 {
127 text = s;
0535fa1a
MM		 128 text_start = bfd_get_section_vma (exec_bfd, s);
129 text_end = text_start + bfd_section_size (exec_bfd, s);
a49a15ad
MM		 130 break;
131 }
132 }
133
891513ee 134 buf[0] = '\0';
a49a15ad
MM		 135 byte_pc = (bfd_vma)PC << 2;
136 if (text && byte_pc >= text_start && byte_pc < text_end)
137 {
138 filename = (const char *)0;
139 functionname = (const char *)0;
140 linenumber = 0;
0535fa1a 141 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 142 &filename, &functionname, &linenumber))
143 {
144 p = buf;
145 if (linenumber)
146 {
891513ee 147 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 148 p += strlen (p);
149 }
891513ee
MM		 150 else
151 {
152 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
153 p += SIZE_LINE_NUMBER+2;
154 }
a49a15ad
MM		 155
156 if (functionname)
157 {
158 sprintf (p, "%s ", functionname);
159 p += strlen (p);
160 }
161 else if (filename)
162 {
163 char *q = (char *) strrchr (filename, '/');
164 sprintf (p, "%s ", (q) ? q+1 : filename);
165 p += strlen (p);
166 }
167
168 if (*p == ' ')
169 *p = '\0';
170 }
171 }
172
173 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 174 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 175 SIZE_PC, (unsigned)PC,
176 type,
a49a15ad
MM		 177 SIZE_LOCATION, SIZE_LOCATION, buf,
178 SIZE_INSTRUCTION, name);
179 }
87178dbd
MM		 180
181 in[0] = in1;
182 in[1] = in2;
183 in[2] = in3;
184 comma = "";
185 p = buf;
186 for (i = 0; i < 3; i++)
187 {
188 switch (in[i])
189 {
190 case OP_VOID:
191 break;
192
193 case OP_REG:
194 case OP_REG_OUTPUT:
195 case OP_DREG:
196 case OP_DREG_OUTPUT:
197 sprintf (p, "%sr%d", comma, OP[i]);
198 p += strlen (p);
199 comma = ",";
200 break;
201
202 case OP_CR:
203 case OP_CR_OUTPUT:
204 case OP_CR_REVERSE:
205 sprintf (p, "%scr%d", comma, OP[i]);
206 p += strlen (p);
207 comma = ",";
208 break;
209
210 case OP_ACCUM:
211 case OP_ACCUM_OUTPUT:
212 case OP_ACCUM_REVERSE:
213 sprintf (p, "%sa%d", comma, OP[i]);
214 p += strlen (p);
215 comma = ",";
216 break;
217
218 case OP_CONSTANT16:
219 sprintf (p, "%s%d", comma, OP[i]);
220 p += strlen (p);
221 comma = ",";
222 break;
223
224 case OP_CONSTANT4:
225 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
226 p += strlen (p);
227 comma = ",";
228 break;
229
230 case OP_CONSTANT3:
231 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
232 p += strlen (p);
233 comma = ",";
234 break;
235
236 case OP_MEMREF:
237 sprintf (p, "%s@r%d", comma, OP[i]);
238 p += strlen (p);
239 comma = ",";
240 break;
241
242 case OP_MEMREF2:
243 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
244 p += strlen (p);
245 comma = ",";
246 break;
247
248 case OP_POSTINC:
249 sprintf (p, "%s@r%d+", comma, OP[i]);
250 p += strlen (p);
251 comma = ",";
252 break;
253
254 case OP_POSTDEC:
255 sprintf (p, "%s@r%d-", comma, OP[i]);
256 p += strlen (p);
257 comma = ",";
258 break;
259
260 case OP_PREDEC:
261 sprintf (p, "%s@-r%d", comma, OP[i]);
262 p += strlen (p);
263 comma = ",";
264 break;
265
266 case OP_FLAG:
60fc5b72 267 case OP_FLAG_OUTPUT:
87178dbd
MM		 268 if (OP[i] == 0)
269 sprintf (p, "%sf0", comma);
270
271 else if (OP[i] == 1)
272 sprintf (p, "%sf1", comma);
273
274 else
60fc5b72 275 sprintf (p, "%sc", comma);
87178dbd
MM		 276
277 p += strlen (p);
278 comma = ",";
279 break;
280 }
281 }
282
7eebfc62
MM		 283 if ((d10v_debug & DEBUG_VALUES) == 0)
284 {
285 *p++ = '\n';
286 *p = '\0';
287 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
288 }
289 else
290 {
291 *p = '\0';
292 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 293
7eebfc62
MM		 294 p = buf;
295 for (i = 0; i < 3; i++)
296 {
297 buf[0] = '\0';
298 switch (in[i])
299 {
300 case OP_VOID:
301 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
302 break;
303
304 case OP_REG_OUTPUT:
305 case OP_DREG_OUTPUT:
306 case OP_CR_OUTPUT:
307 case OP_ACCUM_OUTPUT:
60fc5b72 308 case OP_FLAG_OUTPUT:
7eebfc62
MM		 309 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
310 break;
311
312 case OP_REG:
313 case OP_MEMREF:
314 case OP_POSTDEC:
315 case OP_POSTINC:
316 case OP_PREDEC:
317 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
318 (uint16)State.regs[OP[i]]);
319 break;
320
321 case OP_DREG:
322 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
323 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
324 break;
325
326 case OP_CR:
327 case OP_CR_REVERSE:
328 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
329 (uint16)State.cregs[OP[i]]);
330 break;
331
332 case OP_ACCUM:
333 case OP_ACCUM_REVERSE:
334 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
335 ((int)(State.a[OP[i]] >> 32) & 0xff),
336 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
337 break;
338
339 case OP_CONSTANT16:
340 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
341 (uint16)OP[i]);
342 break;
343
344 case OP_CONSTANT4:
345 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
346 (uint16)SEXT4(OP[i]));
347 break;
348
349 case OP_CONSTANT3:
350 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
351 (uint16)SEXT3(OP[i]));
352 break;
353
354 case OP_FLAG:
355 if (OP[i] == 0)
356 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
357 State.F0 != 0);
358
359 else if (OP[i] == 1)
360 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
361 State.F1 != 0);
362
363 else
364 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
365 State.C != 0);
366
367 break;
368
369 case OP_MEMREF2:
370 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
371 (uint16)OP[i]);
372 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
373 (uint16)State.regs[OP[++i]]);
374 break;
375 }
376 }
377 }
378}
87178dbd 379
7eebfc62 380static void
a49a15ad 381trace_output_func (result)
7eebfc62
MM		 382 enum op_types result;
383{
384 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 385 {
7eebfc62 386 long tmp;
87178dbd 387
7eebfc62
MM		 388 switch (result)
389 {
390 default:
391 putchar ('\n');
87178dbd
MM		 392 break;
393
394 case OP_REG:
7eebfc62
MM		 395 case OP_REG_OUTPUT:
396 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
397 (uint16)State.regs[OP[0]],
398 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 399 break;
400
401 case OP_DREG:
7eebfc62
MM		 402 case OP_DREG_OUTPUT:
403 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
404 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
405 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 406 break;
407
408 case OP_CR:
7eebfc62
MM		 409 case OP_CR_OUTPUT:
410 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
411 (uint16)State.cregs[OP[0]],
412 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 413 break;
414
7eebfc62
MM		 415 case OP_CR_REVERSE:
416 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
417 (uint16)State.cregs[OP[1]],
418 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 419 break;
420
7eebfc62
MM		 421 case OP_ACCUM:
422 case OP_ACCUM_OUTPUT:
069398aa 423 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 424 ((int)(State.a[OP[0]] >> 32) & 0xff),
425 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
426 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 427 break;
428
7eebfc62 429 case OP_ACCUM_REVERSE:
069398aa 430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 431 ((int)(State.a[OP[1]] >> 32) & 0xff),
432 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
433 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 434 break;
435
436 case OP_FLAG:
60fc5b72 437 case OP_FLAG_OUTPUT:
7eebfc62
MM		 438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
439 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 440 break;
441 }
442 }
87178dbd
MM		 443}
444
445#else
446#define trace_input(NAME, IN1, IN2, IN3)
447#define trace_output(RESULT)
448#endif
2934d1c9
MH		 449
450/* abs */
451void
452OP_4607 ()
453{
87178dbd 454 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 455 State.F1 = State.F0;
456 if ((int16)(State.regs[OP[0]]) < 0)
457 {
458 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
459 State.F0 = 1;
460 }
461 else
462 State.F0 = 0;
87178dbd 463 trace_output (OP_REG);
2934d1c9
MH		 464}
465
466/* abs */
467void
468OP_5607 ()
469{
470 int64 tmp;
471
87178dbd 472 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 473 State.F1 = State.F0;
474 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
475
4c38885c 476 if (State.a[OP[0]] < 0 )
2934d1c9 477 {
4c38885c 478 tmp = -State.a[OP[0]];
2934d1c9
MH		 479 if (State.ST)
480 {
4c38885c 481 if (tmp > MAX32)
2934d1c9 482 State.a[OP[0]] = MAX32;
4c38885c 483 else if (tmp < MIN32)
2934d1c9
MH		 484 State.a[OP[0]] = MIN32;
485 else
4f425a32 486 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 487 }
488 else
4f425a32 489 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 490 State.F0 = 1;
491 }
492 else
493 State.F0 = 0;
87178dbd 494 trace_output (OP_ACCUM);
2934d1c9
MH		 495}
496
497/* add */
498void
499OP_200 ()
500{
501 uint16 tmp = State.regs[OP[0]];
87178dbd 502 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 503 State.regs[OP[0]] += State.regs[OP[1]];
504 if ( tmp > State.regs[OP[0]])
505 State.C = 1;
506 else
507 State.C = 0;
87178dbd 508 trace_output (OP_REG);
2934d1c9
MH		 509}
510
511/* add */
512void
513OP_1201 ()
514{
4c38885c 515 int64 tmp;
4f425a32 516 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 517
518 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 519 if (State.ST)
520 {
521 if ( tmp > MAX32)
522 State.a[OP[0]] = MAX32;
523 else if ( tmp < MIN32)
524 State.a[OP[0]] = MIN32;
525 else
4f425a32 526 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 527 }
528 else
4f425a32 529 State.a[OP[0]] = tmp & MASK40;
87178dbd 530 trace_output (OP_ACCUM);
2934d1c9
MH		 531}
532
533/* add */
534void
535OP_1203 ()
536{
4c38885c 537 int64 tmp;
4f425a32 538 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 539
540 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 541 if (State.ST)
542 {
543 if (tmp > MAX32)
544 State.a[OP[0]] = MAX32;
545 else if ( tmp < MIN32)
546 State.a[OP[0]] = MIN32;
547 else
4f425a32 548 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 549 }
550 else
4f425a32 551 State.a[OP[0]] = tmp & MASK40;
87178dbd 552 trace_output (OP_ACCUM);
2934d1c9
MH		 553}
554
555/* add2w */
556void
557OP_1200 ()
558{
559 uint32 tmp;
560 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
561 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 562
563 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
2934d1c9
MH		 564 tmp = tmp1 + tmp2;
565 if ( (tmp < tmp1) || (tmp < tmp2) )
566 State.C = 1;
567 else
568 State.C = 0;
569 State.regs[OP[0]] = tmp >> 16;
570 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 571 trace_output (OP_DREG);
2934d1c9
MH		 572}
573
574/* add3 */
575void
576OP_1000000 ()
577{
578 uint16 tmp = State.regs[OP[0]];
2934d1c9 579 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
87178dbd
MM		 580
581 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9
MH		 582 if ( tmp > State.regs[OP[0]])
583 State.C = 1;
584 else
585 State.C = 0;
87178dbd 586 trace_output (OP_REG);
2934d1c9
MH		 587}
588
589/* addac3 */
590void
591OP_17000200 ()
592{
4c38885c 593 int64 tmp;
4f425a32 594 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 595
596 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 597 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
598 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 599 trace_output (OP_DREG);
2934d1c9
MH		 600}
601
602/* addac3 */
603void
604OP_17000202 ()
605{
4c38885c 606 int64 tmp;
4f425a32 607 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 608
609 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 610 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
611 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 612 trace_output (OP_DREG);
2934d1c9
MH		 613}
614
615/* addac3s */
616void
617OP_17001200 ()
618{
4c38885c 619 int64 tmp;
4c38885c 620 State.F1 = State.F0;
87178dbd
MM		 621
622 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 623 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 624 if ( tmp > MAX32)
625 {
626 State.regs[OP[0]] = 0x7fff;
627 State.regs[OP[0]+1] = 0xffff;
628 State.F0 = 1;
629 }
630 else if (tmp < MIN32)
631 {
632 State.regs[OP[0]] = 0x8000;
633 State.regs[OP[0]+1] = 0;
634 State.F0 = 1;
635 }
636 else
637 {
638 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
639 State.regs[OP[0]+1] = tmp & 0xffff;
640 State.F0 = 0;
641 }
87178dbd 642 trace_output (OP_DREG);
2934d1c9
MH		 643}
644
645/* addac3s */
646void
647OP_17001202 ()
648{
4c38885c 649 int64 tmp;
4c38885c 650 State.F1 = State.F0;
87178dbd
MM		 651
652 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 653 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 654 if ( tmp > MAX32)
655 {
656 State.regs[OP[0]] = 0x7fff;
657 State.regs[OP[0]+1] = 0xffff;
658 State.F0 = 1;
659 }
660 else if (tmp < MIN32)
661 {
662 State.regs[OP[0]] = 0x8000;
663 State.regs[OP[0]+1] = 0;
664 State.F0 = 1;
665 }
666 else
667 {
668 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
669 State.regs[OP[0]+1] = tmp & 0xffff;
670 State.F0 = 0;
671 }
87178dbd 672 trace_output (OP_DREG);
2934d1c9
MH		 673}
674
675/* addi */
676void
677OP_201 ()
678{
2254cd90 679 uint tmp = State.regs[OP[0]];
4f425a32
MH		 680 if (OP[1] == 0)
681 OP[1] = 16;
87178dbd 682 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 683 State.regs[OP[0]] += OP[1];
2254cd90
MM		 684 if (tmp > State.regs[OP[0]])
685 State.C = 1;
686 else
687 State.C = 0;
87178dbd 688 trace_output (OP_REG);
2934d1c9
MH		 689}
690
691/* and */
692void
693OP_C00 ()
694{
87178dbd 695 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 696 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 697 trace_output (OP_REG);
2934d1c9
MH		 698}
699
700/* and3 */
701void
702OP_6000000 ()
703{
87178dbd 704 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 705 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 706 trace_output (OP_REG);
2934d1c9
MH		 707}
708
709/* bclri */
710void
711OP_C01 ()
712{
87178dbd 713 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 714 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 715 trace_output (OP_REG);
2934d1c9
MH		 716}
717
718/* bl.s */
719void
720OP_4900 ()
721{
87178dbd 722 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 723 State.regs[13] = PC+1;
724 PC += SEXT8 (OP[0]);
87178dbd 725 trace_output (OP_VOID);
2934d1c9
MH		 726}
727
728/* bl.l */
729void
730OP_24800000 ()
731{
87178dbd 732 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 733 State.regs[13] = PC+1;
734 PC += OP[0];
87178dbd 735 trace_output (OP_VOID);
2934d1c9
MH		 736}
737
738/* bnoti */
739void
740OP_A01 ()
741{
87178dbd 742 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 743 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 744 trace_output (OP_REG);
2934d1c9
MH		 745}
746
747/* bra.s */
748void
749OP_4800 ()
750{
87178dbd 751 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 752 PC += SEXT8 (OP[0]);
87178dbd 753 trace_output (OP_VOID);
2934d1c9
MH		 754}
755
756/* bra.l */
757void
758OP_24000000 ()
759{
87178dbd 760 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 761 PC += OP[0];
87178dbd 762 trace_output (OP_VOID);
2934d1c9
MH		 763}
764
765/* brf0f.s */
766void
767OP_4A00 ()
768{
87178dbd 769 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 770 if (State.F0 == 0)
771 PC += SEXT8 (OP[0]);
87178dbd 772 trace_output (OP_FLAG);
2934d1c9
MH		 773}
774
775/* brf0f.l */
776void
777OP_25000000 ()
778{
87178dbd 779 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 780 if (State.F0 == 0)
781 PC += OP[0];
87178dbd 782 trace_output (OP_FLAG);
2934d1c9
MH		 783}
784
785/* brf0t.s */
786void
787OP_4B00 ()
788{
87178dbd 789 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 790 if (State.F0)
791 PC += SEXT8 (OP[0]);
87178dbd 792 trace_output (OP_FLAG);
2934d1c9
MH		 793}
794
795/* brf0t.l */
796void
797OP_25800000 ()
798{
87178dbd 799 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9
MH		 800 if (State.F0)
801 PC += OP[0];
87178dbd 802 trace_output (OP_FLAG);
2934d1c9
MH		 803}
804
805/* bseti */
806void
807OP_801 ()
808{
87178dbd 809 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 810 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 811 trace_output (OP_REG);
2934d1c9
MH		 812}
813
814/* btsti */
815void
816OP_E01 ()
817{
87178dbd 818 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 819 State.F1 = State.F0;
820 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 821 trace_output (OP_FLAG);
2934d1c9
MH		 822}
823
824/* clrac */
825void
826OP_5601 ()
827{
87178dbd 828 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 829 State.a[OP[0]] = 0;
87178dbd 830 trace_output (OP_ACCUM);
2934d1c9
MH		 831}
832
833/* cmp */
834void
835OP_600 ()
836{
87178dbd 837 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 838 State.F1 = State.F0;
839 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 840 trace_output (OP_FLAG);
2934d1c9
MH		 841}
842
843/* cmp */
844void
845OP_1603 ()
846{
87178dbd 847 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 848 State.F1 = State.F0;
4f425a32 849 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 850 trace_output (OP_FLAG);
2934d1c9
MH		 851}
852
853/* cmpeq */
854void
855OP_400 ()
856{
87178dbd 857 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 858 State.F1 = State.F0;
859 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 860 trace_output (OP_FLAG);
2934d1c9
MH		 861}
862
863/* cmpeq */
864void
865OP_1403 ()
866{
87178dbd 867 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 868 State.F1 = State.F0;
869 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
87178dbd 870 trace_output (OP_FLAG);
2934d1c9
MH		 871}
872
873/* cmpeqi.s */
874void
875OP_401 ()
876{
87178dbd 877 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 878 State.F1 = State.F0;
879 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
87178dbd 880 trace_output (OP_FLAG);
2934d1c9
MH		 881}
882
883/* cmpeqi.l */
884void
885OP_2000000 ()
886{
87178dbd 887 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 888 State.F1 = State.F0;
889 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
87178dbd 890 trace_output (OP_FLAG);
2934d1c9
MH		 891}
892
893/* cmpi.s */
894void
895OP_601 ()
896{
87178dbd 897 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9
MH		 898 State.F1 = State.F0;
899 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
87178dbd 900 trace_output (OP_FLAG);
2934d1c9
MH		 901}
902
903/* cmpi.l */
904void
905OP_3000000 ()
906{
87178dbd 907 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 908 State.F1 = State.F0;
909 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 910 trace_output (OP_FLAG);
2934d1c9
MH		 911}
912
913/* cmpu */
914void
915OP_4600 ()
916{
87178dbd 917 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 918 State.F1 = State.F0;
919 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 920 trace_output (OP_FLAG);
2934d1c9
MH		 921}
922
923/* cmpui */
924void
925OP_23000000 ()
926{
87178dbd 927 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 928 State.F1 = State.F0;
929 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
87178dbd 930 trace_output (OP_FLAG);
2934d1c9
MH		 931}
932
933/* cpfg */
934void
935OP_4E09 ()
936{
937 uint8 *src, *dst;
2934d1c9 938
60fc5b72 939 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 940 if (OP[0] == 0)
941 dst = &State.F0;
942 else
943 dst = &State.F1;
944
945 if (OP[1] == 0)
946 src = &State.F0;
947 else if (OP[1] == 1)
948 src = &State.F1;
949 else
950 src = &State.C;
951
952 *dst = *src;
87178dbd 953 trace_output (OP_FLAG);
2934d1c9
MH		 954}
955
956/* dbt */
957void
958OP_5F20 ()
959{
a49a15ad 960 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 961 State.exception = SIGTRAP;
2934d1c9
MH		 962}
963
964/* divs */
965void
966OP_14002800 ()
967{
968 uint16 foo, tmp, tmpf;
87178dbd
MM		 969
970 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 971 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
972 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
973 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
974 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
975 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 976 trace_output (OP_DREG);
2934d1c9
MH		 977}
978
979/* exef0f */
980void
981OP_4E04 ()
982{
87178dbd 983 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 984 State.exe = (State.F0 == 0);
87178dbd 985 trace_output (OP_FLAG);
2934d1c9
MH		 986}
987
988/* exef0t */
989void
990OP_4E24 ()
991{
87178dbd 992 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 993 State.exe = (State.F0 != 0);
87178dbd 994 trace_output (OP_FLAG);
2934d1c9
MH		 995}
996
997/* exef1f */
998void
999OP_4E40 ()
1000{
87178dbd 1001 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1002 State.exe = (State.F1 == 0);
87178dbd 1003 trace_output (OP_FLAG);
2934d1c9
MH		 1004}
1005
1006/* exef1t */
1007void
1008OP_4E42 ()
1009{
87178dbd 1010 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1011 State.exe = (State.F1 != 0);
87178dbd 1012 trace_output (OP_FLAG);
2934d1c9
MH		 1013}
1014
1015/* exefaf */
1016void
1017OP_4E00 ()
1018{
87178dbd 1019 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1020 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1021 trace_output (OP_FLAG);
2934d1c9
MH		 1022}
1023
1024/* exefat */
1025void
1026OP_4E02 ()
1027{
87178dbd 1028 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1029 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1030 trace_output (OP_FLAG);
2934d1c9
MH		 1031}
1032
1033/* exetaf */
1034void
1035OP_4E20 ()
1036{
87178dbd 1037 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1038 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1039 trace_output (OP_FLAG);
2934d1c9
MH		 1040}
1041
1042/* exetat */
1043void
1044OP_4E22 ()
1045{
87178dbd 1046 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1047 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1048 trace_output (OP_FLAG);
2934d1c9
MH		 1049}
1050
1051/* exp */
1052void
1053OP_15002A00 ()
1054{
1055 uint32 tmp, foo;
1056 int i;
1057
87178dbd 1058 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1059 if (((int16)State.regs[OP[1]]) >= 0)
1060 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1061 else
4c38885c 1062 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1063
1064 foo = 0x40000000;
4c38885c 1065 for (i=1;i<17;i++)
2934d1c9
MH		 1066 {
1067 if (tmp & foo)
1068 {
1069 State.regs[OP[0]] = i-1;
87178dbd 1070 trace_output (OP_REG);
2934d1c9
MH		 1071 return;
1072 }
4c38885c 1073 foo >>= 1;
2934d1c9
MH		 1074 }
1075 State.regs[OP[0]] = 16;
87178dbd 1076 trace_output (OP_REG);
2934d1c9
MH		 1077}
1078
1079/* exp */
1080void
1081OP_15002A02 ()
1082{
4c38885c
MH		 1083 int64 tmp, foo;
1084 int i;
87178dbd
MM		 1085
1086 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
4f425a32 1087 if (SEXT40(State.a[OP[1]]) >= 0)
4c38885c
MH		 1088 tmp = State.a[OP[1]];
1089 else
1090 tmp = ~(State.a[OP[1]]);
1091
1092 foo = 0x4000000000LL;
1093 for (i=1;i<25;i++)
1094 {
1095 if (tmp & foo)
1096 {
1097 State.regs[OP[0]] = i-9;
87178dbd 1098 trace_output (OP_REG);
4c38885c
MH		 1099 return;
1100 }
1101 foo >>= 1;
1102 }
1103 State.regs[OP[0]] = 16;
87178dbd 1104 trace_output (OP_REG);
2934d1c9
MH		 1105}
1106
1107/* jl */
1108void
1109OP_4D00 ()
1110{
87178dbd 1111 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 1112 State.regs[13] = PC+1;
1113 PC = State.regs[OP[0]];
87178dbd 1114 trace_output (OP_VOID);
2934d1c9
MH		 1115}
1116
1117/* jmp */
1118void
1119OP_4C00 ()
1120{
87178dbd 1121 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1122 PC = State.regs[OP[0]];
87178dbd 1123 trace_output (OP_VOID);
2934d1c9
MH		 1124}
1125
1126/* ld */
1127void
1128OP_30000000 ()
1129{
87178dbd 1130 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1131 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1132 trace_output (OP_REG);
2934d1c9
MH		 1133}
1134
1135/* ld */
1136void
1137OP_6401 ()
1138{
87178dbd 1139 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c 1140 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1141 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1142 trace_output (OP_REG);
2934d1c9
MH		 1143}
1144
1145/* ld */
1146void
1147OP_6001 ()
1148{
87178dbd 1149 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1150 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1151 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1152 trace_output (OP_REG);
2934d1c9
MH		 1153}
1154
1155/* ld */
1156void
1157OP_6000 ()
1158{
87178dbd 1159 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1160 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1161 trace_output (OP_REG);
2934d1c9
MH		 1162}
1163
1164/* ld2w */
1165void
1166OP_31000000 ()
1167{
308f64d3 1168 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1169 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1170 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
87178dbd 1171 trace_output (OP_DREG);
2934d1c9
MH		 1172}
1173
1174/* ld2w */
1175void
1176OP_6601 ()
1177{
87178dbd 1178 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
4c38885c
MH		 1179 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1180 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1181 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1182 trace_output (OP_DREG);
2934d1c9
MH		 1183}
1184
1185/* ld2w */
1186void
1187OP_6201 ()
1188{
87178dbd 1189 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c
MH		 1190 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1191 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
4f425a32 1192 INC_ADDR(State.regs[OP[1]],4);
87178dbd 1193 trace_output (OP_REG);
2934d1c9
MH		 1194}
1195
1196/* ld2w */
1197void
1198OP_6200 ()
1199{
87178dbd 1200 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
4c38885c
MH		 1201 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1202 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
87178dbd 1203 trace_output (OP_REG);
2934d1c9
MH		 1204}
1205
1206/* ldb */
1207void
1208OP_38000000 ()
1209{
87178dbd 1210 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9
MH		 1211 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1212 SEXT8 (State.regs[OP[0]]);
87178dbd 1213 trace_output (OP_REG);
2934d1c9
MH		 1214}
1215
1216/* ldb */
1217void
1218OP_7000 ()
1219{
87178dbd 1220 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9
MH		 1221 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1222 SEXT8 (State.regs[OP[0]]);
87178dbd 1223 trace_output (OP_REG);
2934d1c9
MH		 1224}
1225
1226/* ldi.s */
1227void
1228OP_4001 ()
1229{
87178dbd 1230 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1231 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1232 trace_output (OP_REG);
2934d1c9
MH		 1233}
1234
1235/* ldi.l */
1236void
1237OP_20000000 ()
1238{
87178dbd 1239 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1240 State.regs[OP[0]] = OP[1];
87178dbd 1241 trace_output (OP_REG);
2934d1c9
MH		 1242}
1243
1244/* ldub */
1245void
1246OP_39000000 ()
1247{
87178dbd 1248 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1249 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1250 trace_output (OP_REG);
2934d1c9
MH		 1251}
1252
1253/* ldub */
1254void
1255OP_7200 ()
1256{
87178dbd 1257 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1258 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1259 trace_output (OP_REG);
2934d1c9
MH		 1260}
1261
1262/* mac */
1263void
1264OP_2A00 ()
1265{
4c38885c 1266 int64 tmp;
87178dbd
MM		 1267
1268 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1269 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1270
1271 if (State.FX)
4f425a32 1272 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1273
1274 if (State.ST && tmp > MAX32)
1275 tmp = MAX32;
1276
4f425a32 1277 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1278 if (State.ST)
1279 {
1280 if (tmp > MAX32)
1281 State.a[OP[0]] = MAX32;
1282 else if (tmp < MIN32)
1283 State.a[OP[0]] = MIN32;
1284 else
4f425a32 1285 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1286 }
1287 else
4f425a32 1288 State.a[OP[0]] = tmp & MASK40;
87178dbd 1289 trace_output (OP_ACCUM);
2934d1c9
MH		 1290}
1291
1292/* macsu */
1293void
1294OP_1A00 ()
1295{
4f425a32 1296 int64 tmp;
87178dbd
MM		 1297
1298 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1299 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1300 if (State.FX)
1301 tmp = SEXT40( (tmp << 1) & MASK40);
1302
1303 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1304 trace_output (OP_ACCUM);
2934d1c9
MH		 1305}
1306
1307/* macu */
1308void
1309OP_3A00 ()
1310{
4f425a32 1311 int64 tmp;
87178dbd
MM		 1312
1313 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1314 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1315 if (State.FX)
1316 tmp = SEXT40( (tmp << 1) & MASK40);
1317 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1318 trace_output (OP_ACCUM);
2934d1c9
MH		 1319}
1320
1321/* max */
1322void
1323OP_2600 ()
1324{
87178dbd 1325 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1326 State.F1 = State.F0;
ea2155e8 1327 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1328 {
1329 State.regs[OP[0]] = State.regs[OP[1]];
1330 State.F0 = 1;
1331 }
1332 else
1333 State.F0 = 0;
87178dbd 1334 trace_output (OP_REG);
2934d1c9
MH		 1335}
1336
1337/* max */
1338void
1339OP_3600 ()
1340{
4f425a32 1341 int64 tmp;
87178dbd
MM		 1342
1343 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1344 State.F1 = State.F0;
1345 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1346 if (tmp > SEXT40(State.a[OP[0]]))
1347 {
1348 State.a[OP[0]] = tmp & MASK40;
1349 State.F0 = 1;
1350 }
1351 else
1352 State.F0 = 0;
87178dbd 1353 trace_output (OP_ACCUM);
2934d1c9
MH		 1354}
1355
1356/* max */
1357void
1358OP_3602 ()
1359{
87178dbd 1360 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1361 State.F1 = State.F0;
1362 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1363 {
1364 State.a[OP[0]] = State.a[OP[1]];
1365 State.F0 = 1;
1366 }
1367 else
1368 State.F0 = 0;
87178dbd 1369 trace_output (OP_ACCUM);
2934d1c9
MH		 1370}
1371
4f425a32 1372
2934d1c9
MH		 1373/* min */
1374void
1375OP_2601 ()
1376{
87178dbd 1377 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1378 State.F1 = State.F0;
ea2155e8 1379 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1380 {
1381 State.regs[OP[0]] = State.regs[OP[1]];
1382 State.F0 = 1;
1383 }
1384 else
1385 State.F0 = 0;
87178dbd 1386 trace_output (OP_REG);
2934d1c9
MH		 1387}
1388
1389/* min */
1390void
1391OP_3601 ()
1392{
4f425a32 1393 int64 tmp;
87178dbd
MM		 1394
1395 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1396 State.F1 = State.F0;
1397 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1398 if (tmp < SEXT40(State.a[OP[0]]))
1399 {
1400 State.a[OP[0]] = tmp & MASK40;
1401 State.F0 = 1;
1402 }
1403 else
1404 State.F0 = 0;
87178dbd 1405 trace_output (OP_ACCUM);
2934d1c9
MH		 1406}
1407
1408/* min */
1409void
1410OP_3603 ()
1411{
87178dbd 1412 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1413 State.F1 = State.F0;
1414 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1415 {
1416 State.a[OP[0]] = State.a[OP[1]];
1417 State.F0 = 1;
1418 }
1419 else
1420 State.F0 = 0;
87178dbd 1421 trace_output (OP_ACCUM);
2934d1c9
MH		 1422}
1423
1424/* msb */
1425void
1426OP_2800 ()
1427{
4f425a32 1428 int64 tmp;
87178dbd
MM		 1429
1430 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1431 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1432
1433 if (State.FX)
1434 tmp = SEXT40 ((tmp << 1) & MASK40);
1435
1436 if (State.ST && tmp > MAX32)
1437 tmp = MAX32;
1438
1439 tmp = SEXT40(State.a[OP[0]]) - tmp;
1440 if (State.ST)
1441 {
1442 if (tmp > MAX32)
1443 State.a[OP[0]] = MAX32;
1444 else if (tmp < MIN32)
1445 State.a[OP[0]] = MIN32;
1446 else
1447 State.a[OP[0]] = tmp & MASK40;
1448 }
1449 else
1450 State.a[OP[0]] = tmp & MASK40;
87178dbd 1451 trace_output (OP_ACCUM);
2934d1c9
MH		 1452}
1453
1454/* msbsu */
1455void
1456OP_1800 ()
1457{
4f425a32 1458 int64 tmp;
87178dbd
MM		 1459
1460 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1461 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1462 if (State.FX)
1463 tmp = SEXT40( (tmp << 1) & MASK40);
1464
1465 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1466 trace_output (OP_ACCUM);
2934d1c9
MH		 1467}
1468
1469/* msbu */
1470void
1471OP_3800 ()
1472{
4f425a32 1473 int64 tmp;
87178dbd
MM		 1474
1475 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1476 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1477 if (State.FX)
1478 tmp = SEXT40( (tmp << 1) & MASK40);
1479
1480 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1481 trace_output (OP_ACCUM);
2934d1c9
MH		 1482}
1483
1484/* mul */
1485void
1486OP_2E00 ()
1487{
87178dbd 1488 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1489 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1490 trace_output (OP_REG);
2934d1c9
MH		 1491}
1492
1493/* mulx */
1494void
1495OP_2C00 ()
1496{
4f425a32 1497 int64 tmp;
87178dbd
MM		 1498
1499 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1500 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1501
1502 if (State.FX)
1503 tmp = SEXT40 ((tmp << 1) & MASK40);
1504
1505 if (State.ST && tmp > MAX32)
1506 State.a[OP[0]] = MAX32;
1507 else
1508 State.a[OP[0]] = tmp & MASK40;
87178dbd 1509 trace_output (OP_ACCUM);
2934d1c9
MH		 1510}
1511
1512/* mulxsu */
1513void
1514OP_1C00 ()
1515{
4f425a32 1516 int64 tmp;
87178dbd
MM		 1517
1518 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1519 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1520
1521 if (State.FX)
1522 tmp <<= 1;
1523
1524 State.a[OP[0]] = tmp & MASK40;
87178dbd 1525 trace_output (OP_ACCUM);
2934d1c9
MH		 1526}
1527
1528/* mulxu */
1529void
1530OP_3C00 ()
1531{
4f425a32 1532 int64 tmp;
87178dbd
MM		 1533
1534 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1535 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1536
1537 if (State.FX)
1538 tmp <<= 1;
1539
1540 State.a[OP[0]] = tmp & MASK40;
87178dbd 1541 trace_output (OP_ACCUM);
2934d1c9
MH		 1542}
1543
1544/* mv */
1545void
1546OP_4000 ()
1547{
87178dbd 1548 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1549 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1550 trace_output (OP_REG);
2934d1c9
MH		 1551}
1552
1553/* mv2w */
1554void
1555OP_5000 ()
1556{
87178dbd 1557 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1558 State.regs[OP[0]] = State.regs[OP[1]];
1559 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1560 trace_output (OP_DREG);
2934d1c9
MH		 1561}
1562
1563/* mv2wfac */
1564void
1565OP_3E00 ()
1566{
87178dbd 1567 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1568 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1569 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1570 trace_output (OP_DREG);
2934d1c9
MH		 1571}
1572
1573/* mv2wtac */
1574void
1575OP_3E01 ()
1576{
87178dbd 1577 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
4f425a32 1578 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
87178dbd 1579 trace_output (OP_ACCUM);
2934d1c9
MH		 1580}
1581
1582/* mvac */
1583void
1584OP_3E03 ()
1585{
87178dbd 1586 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1587 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1588 trace_output (OP_ACCUM);
2934d1c9
MH		 1589}
1590
1591/* mvb */
1592void
1593OP_5400 ()
1594{
87178dbd 1595 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1596 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1597 trace_output (OP_REG);
2934d1c9
MH		 1598}
1599
1600/* mvf0f */
1601void
1602OP_4400 ()
1603{
87178dbd 1604 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1605 if (State.F0 == 0)
1606 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1607 trace_output (OP_REG);
2934d1c9
MH		 1608}
1609
1610/* mvf0t */
1611void
1612OP_4401 ()
1613{
87178dbd 1614 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1615 if (State.F0)
1616 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1617 trace_output (OP_REG);
2934d1c9
MH		 1618}
1619
1620/* mvfacg */
1621void
1622OP_1E04 ()
1623{
87178dbd 1624 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1625 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1626 trace_output (OP_ACCUM);
2934d1c9
MH		 1627}
1628
1629/* mvfachi */
1630void
1631OP_1E00 ()
1632{
87178dbd 1633 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1634 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1635 trace_output (OP_REG);
2934d1c9
MH		 1636}
1637
1638/* mvfaclo */
1639void
1640OP_1E02 ()
1641{
87178dbd 1642 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1643 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1644 trace_output (OP_REG);
2934d1c9
MH		 1645}
1646
1647/* mvfc */
1648void
1649OP_5200 ()
1650{
87178dbd 1651 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1652 if (OP[1] == 0)
1653 {
1654 /* PSW is treated specially */
1655 PSW = 0;
1656 if (State.SM) PSW |= 0x8000;
1657 if (State.EA) PSW |= 0x2000;
1658 if (State.DB) PSW |= 0x1000;
1659 if (State.IE) PSW |= 0x400;
1660 if (State.RP) PSW |= 0x200;
1661 if (State.MD) PSW |= 0x100;
1662 if (State.FX) PSW |= 0x80;
1663 if (State.ST) PSW |= 0x40;
1664 if (State.F0) PSW |= 8;
1665 if (State.F1) PSW |= 4;
1666 if (State.C) PSW |= 1;
1667 }
1668 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1669 trace_output (OP_REG);
2934d1c9
MH		 1670}
1671
1672/* mvtacg */
1673void
1674OP_1E41 ()
1675{
87178dbd 1676 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1677 State.a[OP[1]] &= MASK32;
1678 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1679 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1680}
1681
1682/* mvtachi */
1683void
1684OP_1E01 ()
1685{
1686 uint16 tmp;
87178dbd
MM		 1687
1688 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1689 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1690 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1691 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1692}
1693
1694/* mvtaclo */
1695void
1696OP_1E21 ()
1697{
87178dbd 1698 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1699 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1700 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1701}
1702
1703/* mvtc */
1704void
1705OP_5600 ()
1706{
87178dbd 1707 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1708 State.cregs[OP[1]] = State.regs[OP[0]];
1709 if (OP[1] == 0)
1710 {
1711 /* PSW is treated specially */
1712 State.SM = (PSW & 0x8000) ? 1 : 0;
1713 State.EA = (PSW & 0x2000) ? 1 : 0;
1714 State.DB = (PSW & 0x1000) ? 1 : 0;
1715 State.IE = (PSW & 0x400) ? 1 : 0;
1716 State.RP = (PSW & 0x200) ? 1 : 0;
1717 State.MD = (PSW & 0x100) ? 1 : 0;
1718 State.FX = (PSW & 0x80) ? 1 : 0;
1719 State.ST = (PSW & 0x40) ? 1 : 0;
1720 State.F0 = (PSW & 8) ? 1 : 0;
1721 State.F1 = (PSW & 4) ? 1 : 0;
1722 State.C = PSW & 1;
1723 if (State.ST && !State.FX)
1724 {
7eebfc62
MM		 1725 (*d10v_callback->printf_filtered) (d10v_callback,
1726 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1727 PC<<2);
4f425a32 1728 State.exception = SIGILL;
2934d1c9
MH		 1729 }
1730 }
87178dbd 1731 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1732}
1733
1734/* mvub */
1735void
1736OP_5401 ()
1737{
87178dbd 1738 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1739 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1740 trace_output (OP_REG);
2934d1c9
MH		 1741}
1742
1743/* neg */
1744void
1745OP_4605 ()
1746{
87178dbd 1747 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1748 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1749 trace_output (OP_REG);
2934d1c9
MH		 1750}
1751
1752/* neg */
1753void
1754OP_5605 ()
1755{
1756 int64 tmp;
87178dbd
MM		 1757
1758 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1759 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1760 if (State.ST)
1761 {
4c38885c 1762 if ( tmp > MAX32)
2934d1c9 1763 State.a[OP[0]] = MAX32;
4c38885c 1764 else if (tmp < MIN32)
2934d1c9
MH		 1765 State.a[OP[0]] = MIN32;
1766 else
4f425a32 1767 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1768 }
1769 else
4f425a32 1770 State.a[OP[0]] = tmp & MASK40;
87178dbd 1771 trace_output (OP_ACCUM);
2934d1c9
MH		 1772}
1773
1774
1775/* nop */
1776void
1777OP_5E00 ()
1778{
87178dbd
MM		 1779 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1780 trace_output (OP_VOID);
7eebfc62
MM		 1781
1782 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1783 left_nops++;
1784 else
1785 right_nops++;
2934d1c9
MH		 1786}
1787
1788/* not */
1789void
1790OP_4603 ()
1791{
87178dbd 1792 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1793 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1794 trace_output (OP_REG);
2934d1c9
MH		 1795}
1796
1797/* or */
1798void
1799OP_800 ()
1800{
87178dbd 1801 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1802 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1803 trace_output (OP_REG);
2934d1c9
MH		 1804}
1805
1806/* or3 */
1807void
1808OP_4000000 ()
1809{
87178dbd 1810 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1811 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1812 trace_output (OP_REG);
2934d1c9
MH		 1813}
1814
1815/* rac */
1816void
1817OP_5201 ()
1818{
1819 int64 tmp;
1820 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1821
1822 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1823 if (OP[1] != 0)
1824 {
7eebfc62
MM		 1825 (*d10v_callback->printf_filtered) (d10v_callback,
1826 "ERROR at PC 0x%x: instruction only valid for A0\n",
1827 PC<<2);
166acb9f
MH		 1828 State.exception = SIGILL;
1829 }
1830
2934d1c9
MH		 1831 State.F1 = State.F0;
1832 if (shift >=0)
1833 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1834 else
1835 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1836 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1837 if (tmp > MAX32)
2934d1c9
MH		 1838 {
1839 State.regs[OP[0]] = 0x7fff;
1840 State.regs[OP[0]+1] = 0xffff;
1841 State.F0 = 1;
1842 }
4c38885c 1843 else if (tmp < MIN32)
2934d1c9
MH		 1844 {
1845 State.regs[OP[0]] = 0x8000;
1846 State.regs[OP[0]+1] = 0;
1847 State.F0 = 1;
1848 }
1849 else
1850 {
1851 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1852 State.regs[OP[0]+1] = tmp & 0xffff;
1853 State.F0 = 0;
1854 }
87178dbd 1855 trace_output (OP_DREG);
2934d1c9
MH		 1856}
1857
1858/* rachi */
1859void
1860OP_4201 ()
1861{
4c38885c
MH		 1862 int64 tmp;
1863 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1864
1865 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1866 State.F1 = State.F0;
1867 if (shift >=0)
166acb9f 1868 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1869 else
166acb9f 1870 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1871 tmp += 0x8000;
63a91cfb 1872
4c38885c
MH		 1873 if (tmp > MAX32)
1874 {
1875 State.regs[OP[0]] = 0x7fff;
1876 State.F0 = 1;
1877 }
1878 else if (tmp < 0xfff80000000LL)
1879 {
1880 State.regs[OP[0]] = 0x8000;
1881 State.F0 = 1;
1882 }
1883 else
1884 {
1885 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1886 State.F0 = 0;
1887 }
87178dbd 1888 trace_output (OP_REG);
2934d1c9
MH		 1889}
1890
1891/* rep */
1892void
1893OP_27000000 ()
1894{
87178dbd 1895 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1896 RPT_S = PC + 1;
1897 RPT_E = PC + OP[1];
1898 RPT_C = State.regs[OP[0]];
1899 State.RP = 1;
1900 if (RPT_C == 0)
1901 {
7eebfc62 1902 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1903 State.exception = SIGILL;
2934d1c9 1904 }
4c38885c
MH		 1905 if (OP[1] < 4)
1906 {
7eebfc62 1907 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1908 State.exception = SIGILL;
4c38885c 1909 }
87178dbd 1910 trace_output (OP_VOID);
2934d1c9
MH		 1911}
1912
1913/* repi */
1914void
1915OP_2F000000 ()
1916{
87178dbd 1917 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1918 RPT_S = PC + 1;
1919 RPT_E = PC + OP[1];
1920 RPT_C = OP[0];
1921 State.RP = 1;
1922 if (RPT_C == 0)
1923 {
7eebfc62 1924 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 1925 State.exception = SIGILL;
4c38885c
MH		 1926 }
1927 if (OP[1] < 4)
1928 {
7eebfc62 1929 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 1930 State.exception = SIGILL;
2934d1c9 1931 }
87178dbd 1932 trace_output (OP_VOID);
2934d1c9
MH		 1933}
1934
1935/* rtd */
1936void
1937OP_5F60 ()
1938{
7eebfc62 1939 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 1940 State.exception = SIGILL;
2934d1c9
MH		 1941}
1942
1943/* rte */
1944void
1945OP_5F40 ()
1946{
87178dbd 1947 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 1948 PC = BPC;
1949 PSW = BPSW;
87178dbd 1950 trace_output (OP_VOID);
2934d1c9
MH		 1951}
1952
1953/* sadd */
1954void
1955OP_1223 ()
1956{
4c38885c 1957 int64 tmp;
87178dbd
MM		 1958
1959 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 1960 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 1961 if (State.ST)
1962 {
1963 if (tmp > MAX32)
1964 State.a[OP[0]] = MAX32;
1965 else if (tmp < MIN32)
1966 State.a[OP[0]] = MIN32;
1967 else
4f425a32 1968 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1969 }
1970 else
4f425a32 1971 State.a[OP[0]] = tmp & MASK40;
87178dbd 1972 trace_output (OP_ACCUM);
2934d1c9
MH		 1973}
1974
1975/* setf0f */
1976void
1977OP_4611 ()
1978{
87178dbd 1979 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 1980 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 1981 trace_output (OP_REG);
2934d1c9
MH		 1982}
1983
1984/* setf0t */
1985void
1986OP_4613 ()
1987{
87178dbd 1988 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 1989 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 1990 trace_output (OP_REG);
2934d1c9
MH		 1991}
1992
1993/* sleep */
1994void
1995OP_5FC0 ()
1996{
87178dbd 1997 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 1998 State.IE = 1;
87178dbd 1999 trace_output (OP_VOID);
2934d1c9
MH		 2000}
2001
2002/* sll */
2003void
2004OP_2200 ()
2005{
87178dbd 2006 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2007 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2008 trace_output (OP_REG);
2934d1c9
MH		 2009}
2010
2011/* sll */
2012void
2013OP_3200 ()
2014{
4c38885c 2015 int64 tmp;
87178dbd 2016 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2017 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2018 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2019 else
2020 {
2021 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2022 State.exception = SIGILL;
2023 return;
2024 }
4c38885c
MH		 2025
2026 if (State.ST)
2027 {
2028 if (tmp > MAX32)
2029 State.a[OP[0]] = MAX32;
2030 else if (tmp < 0xffffff80000000LL)
2031 State.a[OP[0]] = MIN32;
2032 else
2033 State.a[OP[0]] = tmp & MASK40;
2034 }
2035 else
2036 State.a[OP[0]] = tmp & MASK40;
87178dbd 2037 trace_output (OP_ACCUM);
2934d1c9
MH		 2038}
2039
2040/* slli */
2041void
2042OP_2201 ()
2043{
87178dbd 2044 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2045 State.regs[OP[0]] <<= OP[1];
87178dbd 2046 trace_output (OP_REG);
2934d1c9
MH		 2047}
2048
2049/* slli */
2050void
2051OP_3201 ()
2052{
4c38885c 2053 int64 tmp;
4f425a32
MH		 2054
2055 if (OP[1] == 0)
2056 OP[1] = 16;
4f425a32 2057
87178dbd 2058 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2059 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2060
2061 if (State.ST)
2062 {
2063 if (tmp > MAX32)
2064 State.a[OP[0]] = MAX32;
2065 else if (tmp < 0xffffff80000000LL)
2066 State.a[OP[0]] = MIN32;
2067 else
2068 State.a[OP[0]] = tmp & MASK40;
2069 }
2070 else
2071 State.a[OP[0]] = tmp & MASK40;
87178dbd 2072 trace_output (OP_ACCUM);
2934d1c9
MH		 2073}
2074
2075/* slx */
2076void
2077OP_460B ()
2078{
2079 uint16 tmp;
87178dbd
MM		 2080
2081 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2082 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2083 trace_output (OP_REG);
2934d1c9
MH		 2084}
2085
2086/* sra */
2087void
2088OP_2400 ()
2089{
87178dbd 2090 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2091 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2092 trace_output (OP_REG);
2934d1c9
MH		 2093}
2094
2095/* sra */
2096void
2097OP_3400 ()
2098{
87178dbd 2099 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2100 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2101 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2102 else
2103 {
2104 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2105 State.exception = SIGILL;
2106 return;
2107 }
2108
87178dbd 2109 trace_output (OP_ACCUM);
2934d1c9
MH		 2110}
2111
2112/* srai */
2113void
2114OP_2401 ()
2115{
87178dbd 2116 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2117 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2118 trace_output (OP_REG);
2934d1c9
MH		 2119}
2120
2121/* srai */
2122void
2123OP_3401 ()
2124{
4f425a32
MH		 2125 if (OP[1] == 0)
2126 OP[1] = 16;
87178dbd
MM		 2127
2128 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2129 State.a[OP[0]] >>= OP[1];
2130 trace_output (OP_ACCUM);
2934d1c9
MH		 2131}
2132
2133/* srl */
2134void
2135OP_2000 ()
2136{
87178dbd 2137 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2138 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2139 trace_output (OP_REG);
2934d1c9
MH		 2140}
2141
2142/* srl */
2143void
2144OP_3000 ()
2145{
87178dbd 2146 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2147 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2148 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
069398aa
MM		 2149 else
2150 {
2151 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2152 State.exception = SIGILL;
2153 return;
2154 }
2155
87178dbd 2156 trace_output (OP_ACCUM);
2934d1c9
MH		 2157}
2158
2159/* srli */
2160void
2161OP_2001 ()
2162{
87178dbd 2163 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2164 State.regs[OP[0]] >>= OP[1];
87178dbd 2165 trace_output (OP_REG);
2934d1c9
MH		 2166}
2167
2168/* srli */
2169void
2170OP_3001 ()
2171{
4f425a32
MH		 2172 if (OP[1] == 0)
2173 OP[1] = 16;
87178dbd
MM		 2174
2175 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2176 State.a[OP[0]] >>= OP[1];
2177 trace_output (OP_ACCUM);
2934d1c9
MH		 2178}
2179
2180/* srx */
2181void
2182OP_4609 ()
2183{
2184 uint16 tmp;
87178dbd
MM		 2185
2186 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2187 tmp = State.F0 << 15;
2188 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2189 trace_output (OP_REG);
2934d1c9
MH		 2190}
2191
2192/* st */
2193void
2194OP_34000000 ()
2195{
87178dbd 2196 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2197 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2198 trace_output (OP_VOID);
2934d1c9
MH		 2199}
2200
2201/* st */
2202void
2203OP_6800 ()
2204{
87178dbd 2205 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2206 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2207 trace_output (OP_VOID);
2934d1c9
MH		 2208}
2209
2210/* st */
2211void
2212OP_6C1F ()
2213{
87178dbd 2214 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2215 if ( OP[1] != 15 )
2216 {
7eebfc62 2217 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2218 State.exception = SIGILL;
2219 return;
4c38885c
MH		 2220 }
2221 State.regs[OP[1]] -= 2;
2222 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2223 trace_output (OP_VOID);
2934d1c9
MH		 2224}
2225
2226/* st */
2227void
2228OP_6801 ()
2229{
87178dbd 2230 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2231 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2232 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2233 trace_output (OP_VOID);
2934d1c9
MH		 2234}
2235
2236/* st */
2237void
2238OP_6C01 ()
2239{
87178dbd 2240 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c 2241 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2242 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2243 trace_output (OP_VOID);
2934d1c9
MH		 2244}
2245
2246/* st2w */
2247void
2248OP_35000000 ()
2249{
87178dbd 2250 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2251 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2252 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2253 trace_output (OP_VOID);
2934d1c9
MH		 2254}
2255
2256/* st2w */
2257void
2258OP_6A00 ()
2259{
87178dbd 2260 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2261 SW (State.regs[OP[1]], State.regs[OP[0]]);
2262 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2263 trace_output (OP_VOID);
2934d1c9
MH		 2264}
2265
2266/* st2w */
2267void
2268OP_6E1F ()
2269{
87178dbd 2270 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2271 if ( OP[1] != 15 )
2272 {
7eebfc62 2273 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2274 State.exception = SIGILL;
2275 return;
4c38885c
MH		 2276 }
2277 State.regs[OP[1]] -= 4;
2278 SW (State.regs[OP[1]], State.regs[OP[0]]);
2279 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2280 trace_output (OP_VOID);
2934d1c9
MH		 2281}
2282
2283/* st2w */
2284void
2285OP_6A01 ()
2286{
87178dbd 2287 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
4c38885c
MH		 2288 SW (State.regs[OP[1]], State.regs[OP[0]]);
2289 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2290 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2291 trace_output (OP_VOID);
2934d1c9
MH		 2292}
2293
2294/* st2w */
2295void
2296OP_6E01 ()
2297{
87178dbd 2298 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2299 SW (State.regs[OP[1]], State.regs[OP[0]]);
2300 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2301 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2302 trace_output (OP_VOID);
2934d1c9
MH		 2303}
2304
2305/* stb */
2306void
2307OP_3C000000 ()
2308{
87178dbd 2309 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2310 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2311 trace_output (OP_VOID);
2934d1c9
MH		 2312}
2313
2314/* stb */
2315void
2316OP_7800 ()
2317{
87178dbd 2318 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2319 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2320 trace_output (OP_VOID);
2934d1c9
MH		 2321}
2322
2323/* stop */
2324void
2325OP_5FE0 ()
2326{
87178dbd 2327 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2328 State.exception = SIG_D10V_STOP;
87178dbd 2329 trace_output (OP_VOID);
2934d1c9
MH		 2330}
2331
2332/* sub */
2333void
2334OP_0 ()
4c38885c
MH		 2335{
2336 int32 tmp;
87178dbd
MM		 2337
2338 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
4c38885c
MH		 2339 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2340 State.C = (tmp & 0xffff0000) ? 1 : 0;
2341 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2342 trace_output (OP_REG);
4c38885c
MH		 2343}
2344
2345/* sub */
2346void
2347OP_1001 ()
2348{
4f425a32 2349 int64 tmp;
87178dbd
MM		 2350
2351 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2352 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2353 if (State.ST)
2354 {
2355 if ( tmp > MAX32)
2356 State.a[OP[0]] = MAX32;
2357 else if ( tmp < MIN32)
2358 State.a[OP[0]] = MIN32;
2359 else
2360 State.a[OP[0]] = tmp & MASK40;
2361 }
2362 else
2363 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2364
2365 trace_output (OP_ACCUM);
4c38885c
MH		 2366}
2367
2368/* sub */
2369
2370void
2371OP_1003 ()
2934d1c9 2372{
4f425a32 2373 int64 tmp;
87178dbd
MM		 2374
2375 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2376 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2377 if (State.ST)
2378 {
2379 if (tmp > MAX32)
2380 State.a[OP[0]] = MAX32;
2381 else if ( tmp < MIN32)
2382 State.a[OP[0]] = MIN32;
2383 else
2384 State.a[OP[0]] = tmp & MASK40;
2385 }
2386 else
2387 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2388
2389 trace_output (OP_ACCUM);
2934d1c9
MH		 2390}
2391
2392/* sub2w */
2393void
2394OP_1000 ()
2395{
4c38885c
MH		 2396 int64 tmp;
2397 int32 a,b;
4c38885c 2398
87178dbd 2399 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
4c38885c
MH		 2400 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2401 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2402 tmp = a-b;
2403 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2404 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2405 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2406 trace_output (OP_DREG);
2934d1c9
MH		 2407}
2408
2409/* subac3 */
2410void
2411OP_17000000 ()
2412{
4f425a32 2413 int64 tmp;
87178dbd
MM		 2414
2415 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2416 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2417 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2418 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2419 trace_output (OP_DREG);
2934d1c9
MH		 2420}
2421
2422/* subac3 */
2423void
2424OP_17000002 ()
2425{
4f425a32 2426 int64 tmp;
87178dbd
MM		 2427
2428 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2429 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2430 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2431 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2432 trace_output (OP_DREG);
2934d1c9
MH		 2433}
2434
2435/* subac3s */
2436void
2437OP_17001000 ()
2438{
4f425a32 2439 int64 tmp;
87178dbd
MM		 2440
2441 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2442 State.F1 = State.F0;
2443 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2444 if ( tmp > MAX32)
2445 {
2446 State.regs[OP[0]] = 0x7fff;
2447 State.regs[OP[0]+1] = 0xffff;
2448 State.F0 = 1;
2449 }
2450 else if (tmp < MIN32)
2451 {
2452 State.regs[OP[0]] = 0x8000;
2453 State.regs[OP[0]+1] = 0;
2454 State.F0 = 1;
2455 }
2456 else
2457 {
2458 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2459 State.regs[OP[0]+1] = tmp & 0xffff;
2460 State.F0 = 0;
2461 }
87178dbd 2462 trace_output (OP_DREG);
2934d1c9
MH		 2463}
2464
2465/* subac3s */
2466void
2467OP_17001002 ()
2468{
4f425a32 2469 int64 tmp;
87178dbd
MM		 2470
2471 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2472 State.F1 = State.F0;
2473 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2474 if ( tmp > MAX32)
2475 {
2476 State.regs[OP[0]] = 0x7fff;
2477 State.regs[OP[0]+1] = 0xffff;
2478 State.F0 = 1;
2479 }
2480 else if (tmp < MIN32)
2481 {
2482 State.regs[OP[0]] = 0x8000;
2483 State.regs[OP[0]+1] = 0;
2484 State.F0 = 1;
2485 }
2486 else
2487 {
2488 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2489 State.regs[OP[0]+1] = tmp & 0xffff;
2490 State.F0 = 0;
2491 }
87178dbd 2492 trace_output (OP_DREG);
2934d1c9
MH		 2493}
2494
2495/* subi */
2496void
2497OP_1 ()
2498{
4c38885c 2499 int32 tmp;
4f425a32
MH		 2500 if (OP[1] == 0)
2501 OP[1] = 16;
87178dbd
MM		 2502
2503 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c
MH		 2504 tmp = (int16)State.regs[OP[0]] - OP[1];
2505 State.C = (tmp & 0xffff0000) ? 1 : 0;
2506 State.regs[OP[0]] = tmp & 0xffff;
87178dbd 2507 trace_output (OP_REG);
2934d1c9
MH		 2508}
2509
2510/* trap */
2511void
2512OP_5F00 ()
2513{
a5719092 2514 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2515 trace_output (OP_VOID);
2934d1c9 2516
63a91cfb 2517 switch (OP[0])
2934d1c9 2518 {
63a91cfb 2519 default:
19d44375 2520#if 0
7eebfc62 2521 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2522 State.exception = SIGILL;
19d44375
MM		 2523#else
2524 /* Use any other traps for batch debugging. */
2525 {
2526 int i;
2527 static int first_time = 1;
2528
2529 if (first_time)
2530 {
2531 first_time = 0;
2532 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2533 for (i = 0; i < 16; i++)
2534 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2535 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2536 }
2537
2538 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2539
2540 for (i = 0; i < 16; i++)
2541 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2542
2543 for (i = 0; i < 2; i++)
2544 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2545 ((int)(State.a[OP[i]] >> 32) & 0xff),
2546 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
2547
2548 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2549 State.F0 != 0, State.F1 != 0, State.C != 0);
2550 break;
2551#endif
63a91cfb
MM		 2552
2553 case 0:
2554 /* Trap 0 is used for simulating low-level I/O */
2555 {
2556 int save_errno = errno;
2557 errno = 0;
2558
2559/* Registers passed to trap 0 */
2560
65c0d7de
MA		 2561#define FUNC State.regs[6] /* function number */
2562#define PARM1 State.regs[2] /* optional parm 1 */
2563#define PARM2 State.regs[3] /* optional parm 2 */
2564#define PARM3 State.regs[4] /* optional parm 3 */
2565#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2566
2567/* Registers set by trap 0 */
2568
65c0d7de
MA		 2569#define RETVAL State.regs[2] /* return value */
2570#define RETVAL_HIGH State.regs[2] /* return value */
2571#define RETVAL_LOW State.regs[3] /* return value */
2572#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2573
2574/* Turn a pointer in a register into a pointer into real memory. */
2575
2576#define MEMPTR(x) ((char *)((x) + State.imem))
2577
2578 switch (FUNC)
2579 {
2580#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2581 case SYS_fork:
2582 RETVAL = fork ();
2583 break;
63a91cfb
MM		 2584 case SYS_execve:
2585 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2586 (char **)MEMPTR (PARM3));
2587 break;
63a91cfb
MM		 2588 case SYS_execv:
2589 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2590 break;
63a91cfb
MM		 2591 case SYS_pipe:
2592 {
2593 reg_t buf;
2594 int host_fd[2];
2595
2596 buf = PARM1;
2597 RETVAL = pipe (host_fd);
2598 SW (buf, host_fd[0]);
2599 buf += sizeof(uint16);
2600 SW (buf, host_fd[1]);
2601 }
2602 break;
63a91cfb
MM		 2603 case SYS_wait:
2604 {
2605 int status;
2606
2607 RETVAL = wait (&status);
2608 SW (PARM1, status);
2609 }
2610 break;
2611#endif
63a91cfb
MM		 2612 case SYS_read:
2613 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2614 PARM3);
2615 break;
63a91cfb
MM		 2616 case SYS_write:
2617 if (PARM1 == 1)
2618 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2619 MEMPTR (PARM2), PARM3);
2620 else
2621 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2622 MEMPTR (PARM2), PARM3);
2623 break;
63a91cfb 2624 case SYS_lseek:
65c0d7de
MA		 2625 {
2626 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2627 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2628 PARM4);
2629 RETVAL_HIGH = ret >> 16;
2630 RETVAL_LOW = ret & 0xffff;
2631 }
63a91cfb 2632 break;
63a91cfb
MM		 2633 case SYS_close:
2634 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2635 break;
63a91cfb
MM		 2636 case SYS_open:
2637 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2638 break;
63a91cfb 2639 case SYS_exit:
a49a15ad 2640 State.exception = SIG_D10V_EXIT;
63a91cfb 2641 break;
63a91cfb 2642
8719be26 2643 case SYS_stat:
63a91cfb
MM		 2644 /* stat system call */
2645 {
2646 struct stat host_stat;
2647 reg_t buf;
2648
2649 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2650
2651 buf = PARM2;
2652
2653 /* The hard-coded offsets and sizes were determined by using
2654 * the D10V compiler on a test program that used struct stat.
2655 */
2656 SW (buf, host_stat.st_dev);
2657 SW (buf+2, host_stat.st_ino);
2658 SW (buf+4, host_stat.st_mode);
2659 SW (buf+6, host_stat.st_nlink);
2660 SW (buf+8, host_stat.st_uid);
2661 SW (buf+10, host_stat.st_gid);
2662 SW (buf+12, host_stat.st_rdev);
2663 SLW (buf+16, host_stat.st_size);
2664 SLW (buf+20, host_stat.st_atime);
2665 SLW (buf+28, host_stat.st_mtime);
2666 SLW (buf+36, host_stat.st_ctime);
2667 }
2668 break;
63a91cfb 2669
63a91cfb
MM		 2670 case SYS_chown:
2671 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2672 break;
63a91cfb
MM		 2673 case SYS_chmod:
2674 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2675 break;
63a91cfb
MM		 2676 case SYS_utime:
2677 /* Cast the second argument to void *, to avoid type mismatch
2678 if a prototype is present. */
2679 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2680 break;
63a91cfb
MM		 2681 default:
2682 abort ();
2683 }
65c0d7de 2684 RETERR = d10v_callback->get_errno(d10v_callback);
63a91cfb
MM		 2685 break;
2686 }
2687
2688 case 1:
2689 /* Trap 1 prints a string */
2690 {
2691 char *fstr = State.regs[2] + State.imem;
2692 fputs (fstr, stdout);
2693 break;
2694 }
2695
2696 case 2:
2697 /* Trap 2 calls printf */
2698 {
2699 char *fstr = State.regs[2] + State.imem;
7eebfc62
MM		 2700 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2701 (int16)State.regs[3],
2702 (int16)State.regs[4],
2703 (int16)State.regs[5]);
63a91cfb
MM		 2704 break;
2705 }
2706
2707 case 3:
2708 /* Trap 3 writes a character */
2709 putchar (State.regs[2]);
2710 break;
19d44375 2711 }
2934d1c9
MH		 2712 }
2713}
2714
2715/* tst0i */
2716void
2717OP_7000000 ()
2718{
87178dbd 2719 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2720 State.F1 = State.F0;
4f425a32 2721 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 2722 trace_output (OP_FLAG);
2934d1c9
MH		 2723}
2724
2725/* tst1i */
2726void
2727OP_F000000 ()
2728{
87178dbd 2729 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 2730 State.F1 = State.F0;
4f425a32 2731 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 2732 trace_output (OP_FLAG);
2934d1c9
MH		 2733}
2734
2735/* wait */
2736void
2737OP_5F80 ()
2738{
87178dbd 2739 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2740 State.IE = 1;
87178dbd 2741 trace_output (OP_VOID);
2934d1c9
MH		 2742}
2743
2744/* xor */
2745void
2746OP_A00 ()
2747{
87178dbd 2748 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 2749 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 2750 trace_output (OP_REG);
2934d1c9
MH		 2751}
2752
2753/* xor3 */
2754void
2755OP_5000000 ()
2756{
87178dbd 2757 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 2758 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 2759 trace_output (OP_REG);
2934d1c9
MH		 2760}
2761
GDB Binutils - Deliverables
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