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c906108c SS |
1 | /* |
2 | * This file is part of SIS. | |
3 | * | |
4 | * ERC32SIM, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, | |
5 | * European Space Agency | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it under | |
8 | * the terms of the GNU General Public License as published by the Free | |
3fd725ef | 9 | * Software Foundation; either version 3 of the License, or (at your option) |
c906108c SS |
10 | * any later version. |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
51b318de | 18 | * this program; if not, see <http://www.gnu.org/licenses/>. |
c906108c SS |
19 | * |
20 | */ | |
21 | ||
9a210f30 | 22 | #include "config.h" |
c906108c | 23 | #include "ansidecl.h" |
3c25f8c7 AC |
24 | #include "gdb/callback.h" |
25 | #include "gdb/remote-sim.h" | |
9c5f41df | 26 | #include <sim-config.h> |
638fcdad JG |
27 | #include <stdint.h> |
28 | ||
9c5f41df JG |
29 | #if WITH_HOST_BYTE_ORDER == BIG_ENDIAN |
30 | #define HOST_BIG_ENDIAN | |
31 | #else | |
32 | #define HOST_LITTLE_ENDIAN | |
33 | #endif | |
c906108c SS |
34 | |
35 | #define I_ACC_EXC 1 | |
36 | ||
37 | /* Maximum events in event queue */ | |
38 | #define EVENT_MAX 256 | |
39 | ||
40 | /* Maximum # of floating point queue */ | |
41 | #define FPUQN 1 | |
42 | ||
43 | /* Maximum # of breakpoints */ | |
44 | #define BPT_MAX 256 | |
45 | ||
46 | struct histype { | |
47 | unsigned addr; | |
48 | unsigned time; | |
49 | }; | |
50 | ||
51 | /* type definitions */ | |
52 | ||
53 | typedef short int int16; /* 16-bit signed int */ | |
54 | typedef unsigned short int uint16; /* 16-bit unsigned int */ | |
55 | typedef int int32; /* 32-bit signed int */ | |
56 | typedef unsigned int uint32; /* 32-bit unsigned int */ | |
57 | typedef float float32; /* 32-bit float */ | |
58 | typedef double float64; /* 64-bit float */ | |
59 | ||
638fcdad JG |
60 | typedef uint64_t uint64; /* 64-bit unsigned int */ |
61 | typedef int64_t int64; /* 64-bit signed int */ | |
c906108c SS |
62 | |
63 | struct pstate { | |
64 | ||
65 | float64 fd[16]; /* FPU registers */ | |
9c5f41df | 66 | #ifdef HOST_LITTLE_ENDIAN |
c906108c SS |
67 | float32 fs[32]; |
68 | float32 *fdp; | |
69 | #else | |
70 | float32 *fs; | |
71 | #endif | |
72 | int32 *fsi; | |
73 | uint32 fsr; | |
74 | int32 fpstate; | |
75 | uint32 fpq[FPUQN * 2]; | |
76 | uint32 fpqn; | |
77 | uint32 ftime; | |
78 | uint32 flrd; | |
79 | uint32 frd; | |
80 | uint32 frs1; | |
81 | uint32 frs2; | |
82 | uint32 fpu_pres; /* FPU present (0 = No, 1 = Yes) */ | |
83 | ||
84 | uint32 psr; /* IU registers */ | |
85 | uint32 tbr; | |
86 | uint32 wim; | |
87 | uint32 g[8]; | |
88 | uint32 r[128]; | |
89 | uint32 y; | |
90 | uint32 asr17; /* Single vector trapping */ | |
91 | uint32 pc, npc; | |
92 | ||
93 | ||
94 | uint32 trap; /* Current trap type */ | |
95 | uint32 annul; /* Instruction annul */ | |
96 | uint32 data; /* Loaded data */ | |
97 | uint32 inst; /* Current instruction */ | |
98 | uint32 asi; /* Current ASI */ | |
99 | uint32 err_mode; /* IU error mode */ | |
100 | uint32 breakpoint; | |
101 | uint32 bptnum; | |
102 | uint32 bphit; | |
103 | uint32 bpts[BPT_MAX]; /* Breakpoints */ | |
104 | ||
105 | uint32 ltime; /* Load interlock time */ | |
106 | uint32 hold; /* IU hold cycles in current inst */ | |
107 | uint32 fhold; /* FPU hold cycles in current inst */ | |
108 | uint32 icnt; /* Instruction cycles in curr inst */ | |
109 | ||
110 | uint32 histlen; /* Trace history management */ | |
111 | uint32 histind; | |
112 | struct histype *histbuf; | |
113 | float32 freq; /* Simulated processor frequency */ | |
114 | ||
115 | ||
96d67095 | 116 | double tottime; |
94110024 JS |
117 | uint64 ninst; |
118 | uint64 fholdt; | |
119 | uint64 holdt; | |
120 | uint64 icntt; | |
121 | uint64 finst; | |
122 | uint64 simstart; | |
96d67095 | 123 | double starttime; |
94110024 JS |
124 | uint64 tlimit; /* Simulation time limit */ |
125 | uint64 pwdtime; /* Cycles in power-down mode */ | |
126 | uint64 nstore; /* Number of load instructions */ | |
127 | uint64 nload; /* Number of store instructions */ | |
128 | uint64 nannul; /* Number of annuled instructions */ | |
129 | uint64 nbranch; /* Number of branch instructions */ | |
c906108c | 130 | uint32 ildreg; /* Destination of last load instruction */ |
94110024 | 131 | uint64 ildtime; /* Last time point for load dependency */ |
c906108c SS |
132 | |
133 | int rett_err; /* IU in jmpl/restore error state (Rev.0) */ | |
134 | int jmpltime; | |
135 | }; | |
136 | ||
137 | struct evcell { | |
138 | void (*cfunc) (); | |
139 | int32 arg; | |
94110024 | 140 | uint64 time; |
c906108c SS |
141 | struct evcell *nxt; |
142 | }; | |
143 | ||
144 | struct estate { | |
145 | struct evcell eq; | |
146 | struct evcell *freeq; | |
94110024 | 147 | uint64 simtime; |
c906108c SS |
148 | }; |
149 | ||
150 | struct irqcell { | |
151 | void (*callback) (); | |
152 | int32 arg; | |
153 | }; | |
154 | ||
155 | ||
156 | #define OK 0 | |
157 | #define TIME_OUT 1 | |
158 | #define BPT_HIT 2 | |
159 | #define ERROR 3 | |
160 | #define CTRL_C 4 | |
161 | ||
162 | /* Prototypes */ | |
163 | ||
164 | /* erc32.c */ | |
bdca5ee4 TT |
165 | extern void init_sim (void); |
166 | extern void reset (void); | |
167 | extern void error_mode (uint32 pc); | |
168 | extern void sim_halt (void); | |
169 | extern void exit_sim (void); | |
170 | extern void init_stdio (void); | |
171 | extern void restore_stdio (void); | |
172 | extern int memory_read (int32 asi, uint32 addr, uint32 *data, | |
173 | int32 sz, int32 *ws); | |
174 | extern int memory_write (int32 asi, uint32 addr, uint32 *data, | |
175 | int32 sz, int32 *ws); | |
176 | extern int sis_memory_write (uint32 addr, | |
177 | const unsigned char *data, uint32 length); | |
178 | extern int sis_memory_read (uint32 addr, char *data, | |
179 | uint32 length); | |
c906108c SS |
180 | |
181 | /* func.c */ | |
bdca5ee4 TT |
182 | extern void set_regi (struct pstate *sregs, int32 reg, |
183 | uint32 rval); | |
184 | extern void get_regi (struct pstate *sregs, int32 reg, char *buf); | |
185 | extern int exec_cmd (struct pstate *sregs, char *cmd); | |
186 | extern void reset_stat (struct pstate *sregs); | |
187 | extern void show_stat (struct pstate *sregs); | |
188 | extern void init_bpt (struct pstate *sregs); | |
189 | extern void init_signals (void); | |
c906108c SS |
190 | |
191 | struct disassemble_info; | |
bdca5ee4 TT |
192 | extern void dis_mem (uint32 addr, uint32 len, |
193 | struct disassemble_info *info); | |
194 | extern void event (void (*cfunc) (), int32 arg, uint64 delta); | |
195 | extern void set_int (int32 level, void (*callback) (), int32 arg); | |
196 | extern void advance_time (struct pstate *sregs); | |
197 | extern uint32 now (void); | |
198 | extern int wait_for_irq (void); | |
199 | extern int check_bpt (struct pstate *sregs); | |
200 | extern void reset_all (void); | |
201 | extern void sys_reset (void); | |
202 | extern void sys_halt (void); | |
203 | extern int bfd_load (char *fname); | |
96d67095 | 204 | extern double get_time (void); |
c906108c SS |
205 | |
206 | /* exec.c */ | |
bdca5ee4 TT |
207 | extern int dispatch_instruction (struct pstate *sregs); |
208 | extern int execute_trap (struct pstate *sregs); | |
209 | extern int check_interrupts (struct pstate *sregs); | |
210 | extern void init_regs (struct pstate *sregs); | |
c906108c SS |
211 | |
212 | /* interf.c */ | |
bdca5ee4 TT |
213 | extern int run_sim (struct pstate *sregs, |
214 | uint64 icount, int dis); | |
c906108c SS |
215 | |
216 | /* float.c */ | |
bdca5ee4 TT |
217 | extern int get_accex (void); |
218 | extern void clear_accex (void); | |
219 | extern void set_fsr (uint32 fsr); | |
c906108c SS |
220 | |
221 | /* help.c */ | |
bdca5ee4 TT |
222 | extern void usage (void); |
223 | extern void gen_help (void); |