Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* CPU family header for fr30bf. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifndef CPU_FR30BF_H | |
26 | #define CPU_FR30BF_H | |
27 | ||
28 | /* Maximum number of instructions that are fetched at a time. | |
29 | This is for LIW type instructions sets (e.g. m32r). */ | |
30 | #define MAX_LIW_INSNS 1 | |
31 | ||
32 | /* Maximum number of instructions that can be executed in parallel. */ | |
33 | #define MAX_PARALLEL_INSNS 1 | |
34 | ||
35 | /* CPU state information. */ | |
36 | typedef struct { | |
37 | /* Hardware elements. */ | |
38 | struct { | |
39 | /* program counter */ | |
40 | USI h_pc; | |
41 | #define GET_H_PC() CPU (h_pc) | |
42 | #define SET_H_PC(x) (CPU (h_pc) = (x)) | |
43 | /* general registers */ | |
44 | SI h_gr[16]; | |
45 | #define GET_H_GR(a1) CPU (h_gr)[a1] | |
46 | #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) | |
47 | /* coprocessor registers */ | |
48 | SI h_cr[16]; | |
49 | #define GET_H_CR(a1) CPU (h_cr)[a1] | |
50 | #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x)) | |
51 | /* dedicated registers */ | |
52 | SI h_dr[6]; | |
7a292a7a SS |
53 | #define GET_H_DR(index) fr30bf_h_dr_get_handler (current_cpu, index) |
54 | #define SET_H_DR(index, x) \ | |
55 | do { \ | |
56 | fr30bf_h_dr_set_handler (current_cpu, (index), (x));\ | |
57 | } while (0) | |
58 | /* processor status */ | |
c906108c | 59 | USI h_ps; |
7a292a7a SS |
60 | #define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu) |
61 | #define SET_H_PS(x) \ | |
62 | do { \ | |
63 | fr30bf_h_ps_set_handler (current_cpu, (x));\ | |
64 | } while (0) | |
65 | /* General Register 13 explicitly required */ | |
c906108c SS |
66 | SI h_r13; |
67 | #define GET_H_R13() CPU (h_r13) | |
68 | #define SET_H_R13(x) (CPU (h_r13) = (x)) | |
7a292a7a | 69 | /* General Register 14 explicitly required */ |
c906108c SS |
70 | SI h_r14; |
71 | #define GET_H_R14() CPU (h_r14) | |
72 | #define SET_H_R14(x) (CPU (h_r14) = (x)) | |
7a292a7a | 73 | /* General Register 15 explicitly required */ |
c906108c SS |
74 | SI h_r15; |
75 | #define GET_H_R15() CPU (h_r15) | |
76 | #define SET_H_R15(x) (CPU (h_r15) = (x)) | |
77 | /* negative bit */ | |
78 | BI h_nbit; | |
79 | #define GET_H_NBIT() CPU (h_nbit) | |
80 | #define SET_H_NBIT(x) (CPU (h_nbit) = (x)) | |
81 | /* zero bit */ | |
82 | BI h_zbit; | |
83 | #define GET_H_ZBIT() CPU (h_zbit) | |
84 | #define SET_H_ZBIT(x) (CPU (h_zbit) = (x)) | |
85 | /* overflow bit */ | |
86 | BI h_vbit; | |
87 | #define GET_H_VBIT() CPU (h_vbit) | |
88 | #define SET_H_VBIT(x) (CPU (h_vbit) = (x)) | |
89 | /* carry bit */ | |
90 | BI h_cbit; | |
91 | #define GET_H_CBIT() CPU (h_cbit) | |
92 | #define SET_H_CBIT(x) (CPU (h_cbit) = (x)) | |
93 | /* interrupt enable bit */ | |
94 | BI h_ibit; | |
95 | #define GET_H_IBIT() CPU (h_ibit) | |
96 | #define SET_H_IBIT(x) (CPU (h_ibit) = (x)) | |
7a292a7a | 97 | /* stack bit */ |
c906108c | 98 | BI h_sbit; |
7a292a7a SS |
99 | #define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu) |
100 | #define SET_H_SBIT(x) \ | |
101 | do { \ | |
102 | fr30bf_h_sbit_set_handler (current_cpu, (x));\ | |
103 | } while (0) | |
c906108c SS |
104 | /* trace trap bit */ |
105 | BI h_tbit; | |
106 | #define GET_H_TBIT() CPU (h_tbit) | |
107 | #define SET_H_TBIT(x) (CPU (h_tbit) = (x)) | |
108 | /* division 0 bit */ | |
109 | BI h_d0bit; | |
110 | #define GET_H_D0BIT() CPU (h_d0bit) | |
111 | #define SET_H_D0BIT(x) (CPU (h_d0bit) = (x)) | |
112 | /* division 1 bit */ | |
113 | BI h_d1bit; | |
114 | #define GET_H_D1BIT() CPU (h_d1bit) | |
115 | #define SET_H_D1BIT(x) (CPU (h_d1bit) = (x)) | |
7a292a7a | 116 | /* condition code bits */ |
c906108c | 117 | UQI h_ccr; |
7a292a7a SS |
118 | #define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu) |
119 | #define SET_H_CCR(x) \ | |
120 | do { \ | |
121 | fr30bf_h_ccr_set_handler (current_cpu, (x));\ | |
122 | } while (0) | |
c906108c SS |
123 | /* system condition bits */ |
124 | UQI h_scr; | |
7a292a7a SS |
125 | #define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu) |
126 | #define SET_H_SCR(x) \ | |
127 | do { \ | |
128 | fr30bf_h_scr_set_handler (current_cpu, (x));\ | |
129 | } while (0) | |
130 | /* interrupt level mask */ | |
c906108c | 131 | UQI h_ilm; |
7a292a7a SS |
132 | #define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu) |
133 | #define SET_H_ILM(x) \ | |
134 | do { \ | |
135 | fr30bf_h_ilm_set_handler (current_cpu, (x));\ | |
136 | } while (0) | |
c906108c SS |
137 | } hardware; |
138 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) | |
139 | } FR30BF_CPU_DATA; | |
140 | ||
141 | /* Cover fns for register access. */ | |
142 | USI fr30bf_h_pc_get (SIM_CPU *); | |
143 | void fr30bf_h_pc_set (SIM_CPU *, USI); | |
144 | SI fr30bf_h_gr_get (SIM_CPU *, UINT); | |
145 | void fr30bf_h_gr_set (SIM_CPU *, UINT, SI); | |
146 | SI fr30bf_h_cr_get (SIM_CPU *, UINT); | |
147 | void fr30bf_h_cr_set (SIM_CPU *, UINT, SI); | |
148 | SI fr30bf_h_dr_get (SIM_CPU *, UINT); | |
149 | void fr30bf_h_dr_set (SIM_CPU *, UINT, SI); | |
150 | USI fr30bf_h_ps_get (SIM_CPU *); | |
151 | void fr30bf_h_ps_set (SIM_CPU *, USI); | |
152 | SI fr30bf_h_r13_get (SIM_CPU *); | |
153 | void fr30bf_h_r13_set (SIM_CPU *, SI); | |
154 | SI fr30bf_h_r14_get (SIM_CPU *); | |
155 | void fr30bf_h_r14_set (SIM_CPU *, SI); | |
156 | SI fr30bf_h_r15_get (SIM_CPU *); | |
157 | void fr30bf_h_r15_set (SIM_CPU *, SI); | |
158 | BI fr30bf_h_nbit_get (SIM_CPU *); | |
159 | void fr30bf_h_nbit_set (SIM_CPU *, BI); | |
160 | BI fr30bf_h_zbit_get (SIM_CPU *); | |
161 | void fr30bf_h_zbit_set (SIM_CPU *, BI); | |
162 | BI fr30bf_h_vbit_get (SIM_CPU *); | |
163 | void fr30bf_h_vbit_set (SIM_CPU *, BI); | |
164 | BI fr30bf_h_cbit_get (SIM_CPU *); | |
165 | void fr30bf_h_cbit_set (SIM_CPU *, BI); | |
166 | BI fr30bf_h_ibit_get (SIM_CPU *); | |
167 | void fr30bf_h_ibit_set (SIM_CPU *, BI); | |
168 | BI fr30bf_h_sbit_get (SIM_CPU *); | |
169 | void fr30bf_h_sbit_set (SIM_CPU *, BI); | |
170 | BI fr30bf_h_tbit_get (SIM_CPU *); | |
171 | void fr30bf_h_tbit_set (SIM_CPU *, BI); | |
172 | BI fr30bf_h_d0bit_get (SIM_CPU *); | |
173 | void fr30bf_h_d0bit_set (SIM_CPU *, BI); | |
174 | BI fr30bf_h_d1bit_get (SIM_CPU *); | |
175 | void fr30bf_h_d1bit_set (SIM_CPU *, BI); | |
176 | UQI fr30bf_h_ccr_get (SIM_CPU *); | |
177 | void fr30bf_h_ccr_set (SIM_CPU *, UQI); | |
178 | UQI fr30bf_h_scr_get (SIM_CPU *); | |
179 | void fr30bf_h_scr_set (SIM_CPU *, UQI); | |
180 | UQI fr30bf_h_ilm_get (SIM_CPU *); | |
181 | void fr30bf_h_ilm_set (SIM_CPU *, UQI); | |
182 | ||
183 | /* These must be hand-written. */ | |
184 | extern CPUREG_FETCH_FN fr30bf_fetch_register; | |
185 | extern CPUREG_STORE_FN fr30bf_store_register; | |
186 | ||
187 | typedef struct { | |
188 | UINT load_regs; | |
189 | UINT load_regs_pending; | |
190 | } MODEL_FR30_1_DATA; | |
191 | ||
192 | union sem_fields { | |
193 | struct { /* empty sformat for unspecified field list */ | |
194 | int empty; | |
195 | } fmt_empty; | |
196 | struct { /* e.g. add $Rj,$Ri */ | |
197 | SI * i_Ri; | |
198 | SI * i_Rj; | |
199 | unsigned char in_Ri; | |
200 | unsigned char in_Rj; | |
201 | unsigned char out_Ri; | |
202 | } fmt_add; | |
203 | struct { /* e.g. add $u4,$Ri */ | |
204 | UINT f_u4; | |
205 | SI * i_Ri; | |
206 | unsigned char in_Ri; | |
207 | unsigned char out_Ri; | |
208 | } fmt_addi; | |
209 | struct { /* e.g. add2 $m4,$Ri */ | |
210 | SI f_m4; | |
211 | SI * i_Ri; | |
212 | unsigned char in_Ri; | |
213 | unsigned char out_Ri; | |
214 | } fmt_add2; | |
215 | struct { /* e.g. addc $Rj,$Ri */ | |
216 | SI * i_Ri; | |
217 | SI * i_Rj; | |
218 | unsigned char in_Ri; | |
219 | unsigned char in_Rj; | |
220 | unsigned char out_Ri; | |
221 | } fmt_addc; | |
222 | struct { /* e.g. addn $Rj,$Ri */ | |
223 | SI * i_Ri; | |
224 | SI * i_Rj; | |
225 | unsigned char in_Ri; | |
226 | unsigned char in_Rj; | |
227 | unsigned char out_Ri; | |
228 | } fmt_addn; | |
229 | struct { /* e.g. addn $u4,$Ri */ | |
230 | UINT f_u4; | |
231 | SI * i_Ri; | |
232 | unsigned char in_Ri; | |
233 | unsigned char out_Ri; | |
234 | } fmt_addni; | |
235 | struct { /* e.g. addn2 $m4,$Ri */ | |
236 | SI f_m4; | |
237 | SI * i_Ri; | |
238 | unsigned char in_Ri; | |
239 | unsigned char out_Ri; | |
240 | } fmt_addn2; | |
241 | struct { /* e.g. cmp $Rj,$Ri */ | |
242 | SI * i_Ri; | |
243 | SI * i_Rj; | |
244 | unsigned char in_Ri; | |
245 | unsigned char in_Rj; | |
246 | } fmt_cmp; | |
247 | struct { /* e.g. cmp $u4,$Ri */ | |
248 | UINT f_u4; | |
249 | SI * i_Ri; | |
250 | unsigned char in_Ri; | |
251 | } fmt_cmpi; | |
252 | struct { /* e.g. cmp2 $m4,$Ri */ | |
253 | SI f_m4; | |
254 | SI * i_Ri; | |
255 | unsigned char in_Ri; | |
256 | } fmt_cmp2; | |
257 | struct { /* e.g. and $Rj,$Ri */ | |
258 | SI * i_Ri; | |
259 | SI * i_Rj; | |
260 | unsigned char in_Ri; | |
261 | unsigned char in_Rj; | |
262 | unsigned char out_Ri; | |
263 | } fmt_and; | |
264 | struct { /* e.g. and $Rj,@$Ri */ | |
265 | SI * i_Ri; | |
266 | SI * i_Rj; | |
267 | unsigned char in_Ri; | |
268 | unsigned char in_Rj; | |
269 | } fmt_andm; | |
270 | struct { /* e.g. andh $Rj,@$Ri */ | |
271 | SI * i_Ri; | |
272 | SI * i_Rj; | |
273 | unsigned char in_Ri; | |
274 | unsigned char in_Rj; | |
275 | } fmt_andh; | |
276 | struct { /* e.g. andb $Rj,@$Ri */ | |
277 | SI * i_Ri; | |
278 | SI * i_Rj; | |
279 | unsigned char in_Ri; | |
280 | unsigned char in_Rj; | |
281 | } fmt_andb; | |
282 | struct { /* e.g. bandl $u4,@$Ri */ | |
283 | UINT f_u4; | |
284 | SI * i_Ri; | |
285 | unsigned char in_Ri; | |
286 | } fmt_bandl; | |
287 | struct { /* e.g. btstl $u4,@$Ri */ | |
288 | UINT f_u4; | |
289 | SI * i_Ri; | |
290 | unsigned char in_Ri; | |
291 | } fmt_btstl; | |
292 | struct { /* e.g. mul $Rj,$Ri */ | |
293 | SI * i_Ri; | |
294 | SI * i_Rj; | |
295 | unsigned char in_Ri; | |
296 | unsigned char in_Rj; | |
297 | } fmt_mul; | |
298 | struct { /* e.g. mulu $Rj,$Ri */ | |
299 | SI * i_Ri; | |
300 | SI * i_Rj; | |
301 | unsigned char in_Ri; | |
302 | unsigned char in_Rj; | |
303 | } fmt_mulu; | |
304 | struct { /* e.g. mulh $Rj,$Ri */ | |
305 | SI * i_Ri; | |
306 | SI * i_Rj; | |
307 | unsigned char in_Ri; | |
308 | unsigned char in_Rj; | |
309 | } fmt_mulh; | |
310 | struct { /* e.g. div0s $Ri */ | |
311 | SI * i_Ri; | |
312 | unsigned char in_Ri; | |
313 | } fmt_div0s; | |
314 | struct { /* e.g. div0u $Ri */ | |
315 | int empty; | |
316 | } fmt_div0u; | |
317 | struct { /* e.g. div1 $Ri */ | |
318 | SI * i_Ri; | |
319 | unsigned char in_Ri; | |
320 | } fmt_div1; | |
321 | struct { /* e.g. div2 $Ri */ | |
322 | SI * i_Ri; | |
323 | unsigned char in_Ri; | |
324 | } fmt_div2; | |
325 | struct { /* e.g. div3 */ | |
326 | int empty; | |
327 | } fmt_div3; | |
328 | struct { /* e.g. div4s */ | |
329 | int empty; | |
330 | } fmt_div4s; | |
331 | struct { /* e.g. lsl $Rj,$Ri */ | |
332 | SI * i_Ri; | |
333 | SI * i_Rj; | |
334 | unsigned char in_Ri; | |
335 | unsigned char in_Rj; | |
336 | unsigned char out_Ri; | |
337 | } fmt_lsl; | |
338 | struct { /* e.g. lsl $u4,$Ri */ | |
339 | UINT f_u4; | |
340 | SI * i_Ri; | |
341 | unsigned char in_Ri; | |
342 | unsigned char out_Ri; | |
343 | } fmt_lsli; | |
344 | struct { /* e.g. ldi:8 $i8,$Ri */ | |
345 | UINT f_i8; | |
346 | SI * i_Ri; | |
347 | unsigned char out_Ri; | |
348 | } fmt_ldi8; | |
349 | struct { /* e.g. ldi:20 $i20,$Ri */ | |
350 | UINT f_i20; | |
351 | SI * i_Ri; | |
352 | unsigned char out_Ri; | |
353 | } fmt_ldi20; | |
354 | struct { /* e.g. ldi:32 $i32,$Ri */ | |
355 | UINT f_i32; | |
356 | SI * i_Ri; | |
357 | unsigned char out_Ri; | |
358 | } fmt_ldi32; | |
359 | struct { /* e.g. ld @$Rj,$Ri */ | |
360 | SI * i_Rj; | |
361 | SI * i_Ri; | |
362 | unsigned char in_Rj; | |
363 | unsigned char out_Ri; | |
364 | } fmt_ld; | |
365 | struct { /* e.g. lduh @$Rj,$Ri */ | |
366 | SI * i_Rj; | |
367 | SI * i_Ri; | |
368 | unsigned char in_Rj; | |
369 | unsigned char out_Ri; | |
370 | } fmt_lduh; | |
371 | struct { /* e.g. ldub @$Rj,$Ri */ | |
372 | SI * i_Rj; | |
373 | SI * i_Ri; | |
374 | unsigned char in_Rj; | |
375 | unsigned char out_Ri; | |
376 | } fmt_ldub; | |
377 | struct { /* e.g. ld @($R13,$Rj),$Ri */ | |
378 | SI * i_Rj; | |
379 | SI * i_Ri; | |
380 | unsigned char in_Rj; | |
381 | unsigned char in_h_gr_13; | |
382 | unsigned char out_Ri; | |
383 | } fmt_ldr13; | |
384 | struct { /* e.g. lduh @($R13,$Rj),$Ri */ | |
385 | SI * i_Rj; | |
386 | SI * i_Ri; | |
387 | unsigned char in_Rj; | |
388 | unsigned char in_h_gr_13; | |
389 | unsigned char out_Ri; | |
390 | } fmt_ldr13uh; | |
391 | struct { /* e.g. ldub @($R13,$Rj),$Ri */ | |
392 | SI * i_Rj; | |
393 | SI * i_Ri; | |
394 | unsigned char in_Rj; | |
395 | unsigned char in_h_gr_13; | |
396 | unsigned char out_Ri; | |
397 | } fmt_ldr13ub; | |
398 | struct { /* e.g. ld @($R14,$disp10),$Ri */ | |
399 | SI f_disp10; | |
400 | SI * i_Ri; | |
401 | unsigned char in_h_gr_14; | |
402 | unsigned char out_Ri; | |
403 | } fmt_ldr14; | |
404 | struct { /* e.g. lduh @($R14,$disp9),$Ri */ | |
405 | SI f_disp9; | |
406 | SI * i_Ri; | |
407 | unsigned char in_h_gr_14; | |
408 | unsigned char out_Ri; | |
409 | } fmt_ldr14uh; | |
410 | struct { /* e.g. ldub @($R14,$disp8),$Ri */ | |
411 | INT f_disp8; | |
412 | SI * i_Ri; | |
413 | unsigned char in_h_gr_14; | |
414 | unsigned char out_Ri; | |
415 | } fmt_ldr14ub; | |
416 | struct { /* e.g. ld @($R15,$udisp6),$Ri */ | |
417 | USI f_udisp6; | |
418 | SI * i_Ri; | |
419 | unsigned char in_h_gr_15; | |
420 | unsigned char out_Ri; | |
421 | } fmt_ldr15; | |
422 | struct { /* e.g. ld @$R15+,$Ri */ | |
423 | UINT f_Ri; | |
424 | SI * i_Ri; | |
425 | unsigned char in_h_gr_15; | |
426 | unsigned char out_Ri; | |
427 | unsigned char out_h_gr_15; | |
428 | } fmt_ldr15gr; | |
429 | struct { /* e.g. ld @$R15+,$Rs2 */ | |
430 | UINT f_Rs2; | |
431 | unsigned char in_h_gr_15; | |
432 | unsigned char out_h_gr_15; | |
433 | } fmt_ldr15dr; | |
434 | struct { /* e.g. ld @$R15+,$ps */ | |
435 | int empty; | |
436 | unsigned char in_h_gr_15; | |
437 | unsigned char out_h_gr_15; | |
438 | } fmt_ldr15ps; | |
439 | struct { /* e.g. st $Ri,@$Rj */ | |
440 | SI * i_Ri; | |
441 | SI * i_Rj; | |
442 | unsigned char in_Ri; | |
443 | unsigned char in_Rj; | |
444 | } fmt_st; | |
445 | struct { /* e.g. sth $Ri,@$Rj */ | |
446 | SI * i_Ri; | |
447 | SI * i_Rj; | |
448 | unsigned char in_Ri; | |
449 | unsigned char in_Rj; | |
450 | } fmt_sth; | |
451 | struct { /* e.g. stb $Ri,@$Rj */ | |
452 | SI * i_Ri; | |
453 | SI * i_Rj; | |
454 | unsigned char in_Ri; | |
455 | unsigned char in_Rj; | |
456 | } fmt_stb; | |
457 | struct { /* e.g. st $Ri,@($R13,$Rj) */ | |
458 | SI * i_Ri; | |
459 | SI * i_Rj; | |
460 | unsigned char in_Ri; | |
461 | unsigned char in_Rj; | |
462 | unsigned char in_h_gr_13; | |
463 | } fmt_str13; | |
464 | struct { /* e.g. sth $Ri,@($R13,$Rj) */ | |
465 | SI * i_Ri; | |
466 | SI * i_Rj; | |
467 | unsigned char in_Ri; | |
468 | unsigned char in_Rj; | |
469 | unsigned char in_h_gr_13; | |
470 | } fmt_str13h; | |
471 | struct { /* e.g. stb $Ri,@($R13,$Rj) */ | |
472 | SI * i_Ri; | |
473 | SI * i_Rj; | |
474 | unsigned char in_Ri; | |
475 | unsigned char in_Rj; | |
476 | unsigned char in_h_gr_13; | |
477 | } fmt_str13b; | |
478 | struct { /* e.g. st $Ri,@($R14,$disp10) */ | |
479 | SI f_disp10; | |
480 | SI * i_Ri; | |
481 | unsigned char in_Ri; | |
482 | unsigned char in_h_gr_14; | |
483 | } fmt_str14; | |
484 | struct { /* e.g. sth $Ri,@($R14,$disp9) */ | |
485 | SI f_disp9; | |
486 | SI * i_Ri; | |
487 | unsigned char in_Ri; | |
488 | unsigned char in_h_gr_14; | |
489 | } fmt_str14h; | |
490 | struct { /* e.g. stb $Ri,@($R14,$disp8) */ | |
491 | INT f_disp8; | |
492 | SI * i_Ri; | |
493 | unsigned char in_Ri; | |
494 | unsigned char in_h_gr_14; | |
495 | } fmt_str14b; | |
496 | struct { /* e.g. st $Ri,@($R15,$udisp6) */ | |
497 | USI f_udisp6; | |
498 | SI * i_Ri; | |
499 | unsigned char in_Ri; | |
500 | unsigned char in_h_gr_15; | |
501 | } fmt_str15; | |
502 | struct { /* e.g. st $Ri,@-$R15 */ | |
503 | SI * i_Ri; | |
504 | unsigned char in_Ri; | |
505 | unsigned char in_h_gr_15; | |
506 | unsigned char out_h_gr_15; | |
507 | } fmt_str15gr; | |
508 | struct { /* e.g. st $Rs2,@-$R15 */ | |
509 | UINT f_Rs2; | |
510 | unsigned char in_h_gr_15; | |
511 | unsigned char out_h_gr_15; | |
512 | } fmt_str15dr; | |
513 | struct { /* e.g. st $ps,@-$R15 */ | |
514 | int empty; | |
515 | unsigned char in_h_gr_15; | |
516 | unsigned char out_h_gr_15; | |
517 | } fmt_str15ps; | |
518 | struct { /* e.g. mov $Rj,$Ri */ | |
519 | SI * i_Rj; | |
520 | SI * i_Ri; | |
521 | unsigned char in_Rj; | |
522 | unsigned char out_Ri; | |
523 | } fmt_mov; | |
524 | struct { /* e.g. mov $Rs1,$Ri */ | |
525 | UINT f_Rs1; | |
526 | SI * i_Ri; | |
527 | unsigned char out_Ri; | |
528 | } fmt_movdr; | |
529 | struct { /* e.g. mov $ps,$Ri */ | |
530 | SI * i_Ri; | |
531 | unsigned char out_Ri; | |
532 | } fmt_movps; | |
533 | struct { /* e.g. mov $Ri,$Rs1 */ | |
534 | UINT f_Rs1; | |
535 | SI * i_Ri; | |
536 | unsigned char in_Ri; | |
537 | } fmt_mov2dr; | |
538 | struct { /* e.g. mov $Ri,$ps */ | |
539 | SI * i_Ri; | |
540 | unsigned char in_Ri; | |
541 | } fmt_mov2ps; | |
542 | struct { /* e.g. bno:d $label9 */ | |
543 | int empty; | |
544 | } fmt_bnod; | |
545 | struct { /* e.g. dmov $R13,@$dir10 */ | |
546 | USI f_dir10; | |
547 | unsigned char in_h_gr_13; | |
548 | } fmt_dmovr13; | |
549 | struct { /* e.g. dmovh $R13,@$dir9 */ | |
550 | USI f_dir9; | |
551 | unsigned char in_h_gr_13; | |
552 | } fmt_dmovr13h; | |
553 | struct { /* e.g. dmovb $R13,@$dir8 */ | |
554 | UINT f_dir8; | |
555 | unsigned char in_h_gr_13; | |
556 | } fmt_dmovr13b; | |
557 | struct { /* e.g. dmov @$R13+,@$dir10 */ | |
558 | USI f_dir10; | |
559 | unsigned char in_h_gr_13; | |
560 | unsigned char out_h_gr_13; | |
561 | } fmt_dmovr13pi; | |
562 | struct { /* e.g. dmovh @$R13+,@$dir9 */ | |
563 | USI f_dir9; | |
564 | unsigned char in_h_gr_13; | |
565 | unsigned char out_h_gr_13; | |
566 | } fmt_dmovr13pih; | |
567 | struct { /* e.g. dmovb @$R13+,@$dir8 */ | |
568 | UINT f_dir8; | |
569 | unsigned char in_h_gr_13; | |
570 | unsigned char out_h_gr_13; | |
571 | } fmt_dmovr13pib; | |
572 | struct { /* e.g. dmov @$R15+,@$dir10 */ | |
573 | USI f_dir10; | |
574 | unsigned char in_h_gr_15; | |
575 | unsigned char out_h_gr_15; | |
576 | } fmt_dmovr15pi; | |
577 | struct { /* e.g. dmov @$dir10,$R13 */ | |
578 | USI f_dir10; | |
579 | unsigned char out_h_gr_13; | |
580 | } fmt_dmov2r13; | |
581 | struct { /* e.g. dmovh @$dir9,$R13 */ | |
582 | USI f_dir9; | |
583 | unsigned char out_h_gr_13; | |
584 | } fmt_dmov2r13h; | |
585 | struct { /* e.g. dmovb @$dir8,$R13 */ | |
586 | UINT f_dir8; | |
587 | unsigned char out_h_gr_13; | |
588 | } fmt_dmov2r13b; | |
589 | struct { /* e.g. dmov @$dir10,@$R13+ */ | |
590 | USI f_dir10; | |
591 | unsigned char in_h_gr_13; | |
592 | unsigned char out_h_gr_13; | |
593 | } fmt_dmov2r13pi; | |
594 | struct { /* e.g. dmovh @$dir9,@$R13+ */ | |
595 | USI f_dir9; | |
596 | unsigned char in_h_gr_13; | |
597 | unsigned char out_h_gr_13; | |
598 | } fmt_dmov2r13pih; | |
599 | struct { /* e.g. dmovb @$dir8,@$R13+ */ | |
600 | UINT f_dir8; | |
601 | unsigned char in_h_gr_13; | |
602 | unsigned char out_h_gr_13; | |
603 | } fmt_dmov2r13pib; | |
604 | struct { /* e.g. dmov @$dir10,@-$R15 */ | |
605 | USI f_dir10; | |
606 | unsigned char in_h_gr_15; | |
607 | unsigned char out_h_gr_15; | |
608 | } fmt_dmov2r15pd; | |
609 | struct { /* e.g. ldres @$Ri+,$u4 */ | |
610 | SI * i_Ri; | |
611 | unsigned char in_Ri; | |
612 | unsigned char out_Ri; | |
613 | } fmt_ldres; | |
614 | struct { /* e.g. copop $u4c,$ccc,$CRj,$CRi */ | |
615 | int empty; | |
616 | } fmt_copop; | |
617 | struct { /* e.g. copld $u4c,$ccc,$Rjc,$CRi */ | |
618 | int empty; | |
619 | } fmt_copld; | |
620 | struct { /* e.g. copst $u4c,$ccc,$CRj,$Ric */ | |
621 | int empty; | |
622 | } fmt_copst; | |
623 | struct { /* e.g. nop */ | |
624 | int empty; | |
625 | } fmt_nop; | |
626 | struct { /* e.g. andccr $u8 */ | |
627 | UINT f_u8; | |
628 | } fmt_andccr; | |
629 | struct { /* e.g. stilm $u8 */ | |
630 | UINT f_u8; | |
631 | } fmt_stilm; | |
632 | struct { /* e.g. addsp $s10 */ | |
633 | SI f_s10; | |
634 | unsigned char in_h_gr_15; | |
635 | unsigned char out_h_gr_15; | |
636 | } fmt_addsp; | |
637 | struct { /* e.g. extsb $Ri */ | |
638 | SI * i_Ri; | |
639 | unsigned char in_Ri; | |
640 | unsigned char out_Ri; | |
641 | } fmt_extsb; | |
642 | struct { /* e.g. extub $Ri */ | |
643 | SI * i_Ri; | |
644 | unsigned char in_Ri; | |
645 | unsigned char out_Ri; | |
646 | } fmt_extub; | |
647 | struct { /* e.g. extsh $Ri */ | |
648 | SI * i_Ri; | |
649 | unsigned char in_Ri; | |
650 | unsigned char out_Ri; | |
651 | } fmt_extsh; | |
652 | struct { /* e.g. extuh $Ri */ | |
653 | SI * i_Ri; | |
654 | unsigned char in_Ri; | |
655 | unsigned char out_Ri; | |
656 | } fmt_extuh; | |
657 | struct { /* e.g. ldm0 ($reglist_low_ld) */ | |
658 | UINT f_reglist_low_ld; | |
659 | unsigned char in_h_gr_15; | |
660 | unsigned char out_h_gr_0; | |
661 | unsigned char out_h_gr_1; | |
662 | unsigned char out_h_gr_15; | |
663 | unsigned char out_h_gr_2; | |
664 | unsigned char out_h_gr_3; | |
665 | unsigned char out_h_gr_4; | |
666 | unsigned char out_h_gr_5; | |
667 | unsigned char out_h_gr_6; | |
668 | unsigned char out_h_gr_7; | |
669 | } fmt_ldm0; | |
670 | struct { /* e.g. ldm1 ($reglist_hi_ld) */ | |
671 | UINT f_reglist_hi_ld; | |
672 | unsigned char in_h_gr_15; | |
673 | unsigned char out_h_gr_10; | |
674 | unsigned char out_h_gr_11; | |
675 | unsigned char out_h_gr_12; | |
676 | unsigned char out_h_gr_13; | |
677 | unsigned char out_h_gr_14; | |
678 | unsigned char out_h_gr_15; | |
679 | unsigned char out_h_gr_8; | |
680 | unsigned char out_h_gr_9; | |
681 | } fmt_ldm1; | |
682 | struct { /* e.g. stm0 ($reglist_low_st) */ | |
683 | UINT f_reglist_low_st; | |
684 | unsigned char in_h_gr_0; | |
685 | unsigned char in_h_gr_1; | |
686 | unsigned char in_h_gr_15; | |
687 | unsigned char in_h_gr_2; | |
688 | unsigned char in_h_gr_3; | |
689 | unsigned char in_h_gr_4; | |
690 | unsigned char in_h_gr_5; | |
691 | unsigned char in_h_gr_6; | |
692 | unsigned char in_h_gr_7; | |
693 | unsigned char out_h_gr_15; | |
694 | } fmt_stm0; | |
695 | struct { /* e.g. stm1 ($reglist_hi_st) */ | |
696 | UINT f_reglist_hi_st; | |
697 | unsigned char in_h_gr_10; | |
698 | unsigned char in_h_gr_11; | |
699 | unsigned char in_h_gr_12; | |
700 | unsigned char in_h_gr_13; | |
701 | unsigned char in_h_gr_14; | |
702 | unsigned char in_h_gr_15; | |
703 | unsigned char in_h_gr_8; | |
704 | unsigned char in_h_gr_9; | |
705 | unsigned char out_h_gr_15; | |
706 | } fmt_stm1; | |
707 | struct { /* e.g. enter $u10 */ | |
708 | USI f_u10; | |
709 | unsigned char in_h_gr_14; | |
710 | unsigned char in_h_gr_15; | |
711 | unsigned char out_h_gr_14; | |
712 | unsigned char out_h_gr_15; | |
713 | } fmt_enter; | |
714 | struct { /* e.g. leave */ | |
715 | int empty; | |
716 | unsigned char in_h_gr_14; | |
717 | unsigned char in_h_gr_15; | |
718 | unsigned char out_h_gr_14; | |
719 | unsigned char out_h_gr_15; | |
720 | } fmt_leave; | |
721 | struct { /* e.g. xchb @$Rj,$Ri */ | |
722 | SI * i_Ri; | |
723 | SI * i_Rj; | |
724 | unsigned char in_Ri; | |
725 | unsigned char in_Rj; | |
726 | unsigned char out_Ri; | |
727 | } fmt_xchb; | |
728 | /* cti insns, kept separately so addr_cache is in fixed place */ | |
729 | struct { | |
730 | union { | |
731 | struct { /* e.g. jmp @$Ri */ | |
732 | SI * i_Ri; | |
733 | unsigned char in_Ri; | |
734 | } fmt_jmp; | |
735 | struct { /* e.g. call @$Ri */ | |
736 | SI * i_Ri; | |
737 | unsigned char in_Ri; | |
738 | } fmt_callr; | |
739 | struct { /* e.g. call $label12 */ | |
740 | IADDR i_label12; | |
741 | } fmt_call; | |
742 | struct { /* e.g. ret */ | |
743 | int empty; | |
744 | } fmt_ret; | |
745 | struct { /* e.g. int $u8 */ | |
746 | UINT f_u8; | |
747 | } fmt_int; | |
748 | struct { /* e.g. inte */ | |
749 | int empty; | |
750 | } fmt_inte; | |
751 | struct { /* e.g. reti */ | |
752 | int empty; | |
753 | } fmt_reti; | |
754 | struct { /* e.g. bra:d $label9 */ | |
755 | IADDR i_label9; | |
756 | } fmt_brad; | |
757 | struct { /* e.g. beq:d $label9 */ | |
758 | IADDR i_label9; | |
759 | } fmt_beqd; | |
760 | struct { /* e.g. bc:d $label9 */ | |
761 | IADDR i_label9; | |
762 | } fmt_bcd; | |
763 | struct { /* e.g. bn:d $label9 */ | |
764 | IADDR i_label9; | |
765 | } fmt_bnd; | |
766 | struct { /* e.g. bv:d $label9 */ | |
767 | IADDR i_label9; | |
768 | } fmt_bvd; | |
769 | struct { /* e.g. blt:d $label9 */ | |
770 | IADDR i_label9; | |
771 | } fmt_bltd; | |
772 | struct { /* e.g. ble:d $label9 */ | |
773 | IADDR i_label9; | |
774 | } fmt_bled; | |
775 | struct { /* e.g. bls:d $label9 */ | |
776 | IADDR i_label9; | |
777 | } fmt_blsd; | |
778 | } fields; | |
779 | #if WITH_SCACHE_PBB | |
780 | SEM_PC addr_cache; | |
781 | #endif | |
782 | } cti; | |
783 | #if WITH_SCACHE_PBB | |
784 | /* Writeback handler. */ | |
785 | struct { | |
786 | /* Pointer to argbuf entry for insn whose results need writing back. */ | |
787 | const struct argbuf *abuf; | |
788 | } write; | |
789 | /* x-before handler */ | |
790 | struct { | |
791 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ | |
792 | int first_p; | |
793 | } before; | |
794 | /* x-after handler */ | |
795 | struct { | |
796 | int empty; | |
797 | } after; | |
798 | /* This entry is used to terminate each pbb. */ | |
799 | struct { | |
800 | /* Number of insns in pbb. */ | |
801 | int insn_count; | |
802 | /* Next pbb to execute. */ | |
803 | SCACHE *next; | |
804 | } chain; | |
805 | #endif | |
806 | }; | |
807 | ||
808 | /* The ARGBUF struct. */ | |
809 | struct argbuf { | |
810 | /* These are the baseclass definitions. */ | |
811 | IADDR addr; | |
812 | const IDESC *idesc; | |
813 | char trace_p; | |
814 | char profile_p; | |
815 | /* cpu specific data follows */ | |
816 | union sem semantic; | |
817 | int written; | |
818 | union sem_fields fields; | |
819 | }; | |
820 | ||
821 | /* A cached insn. | |
822 | ||
823 | ??? SCACHE used to contain more than just argbuf. We could delete the | |
824 | type entirely and always just use ARGBUF, but for future concerns and as | |
825 | a level of abstraction it is left in. */ | |
826 | ||
827 | struct scache { | |
828 | struct argbuf argbuf; | |
829 | }; | |
830 | ||
831 | /* Macros to simplify extraction, reading and semantic code. | |
832 | These define and assign the local vars that contain the insn's fields. */ | |
833 | ||
834 | #define EXTRACT_IFMT_EMPTY_VARS \ | |
835 | /* Instruction fields. */ \ | |
836 | unsigned int length; | |
837 | #define EXTRACT_IFMT_EMPTY_CODE \ | |
838 | length = 0; \ | |
839 | ||
840 | #define EXTRACT_IFMT_ADD_VARS \ | |
841 | /* Instruction fields. */ \ | |
842 | UINT f_op1; \ | |
843 | UINT f_op2; \ | |
844 | UINT f_Rj; \ | |
845 | UINT f_Ri; \ | |
846 | unsigned int length; | |
847 | #define EXTRACT_IFMT_ADD_CODE \ | |
848 | length = 2; \ | |
849 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
850 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
851 | f_Rj = EXTRACT_UINT (insn, 16, 8, 4); \ | |
852 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
853 | ||
854 | #define EXTRACT_IFMT_ADDI_VARS \ | |
855 | /* Instruction fields. */ \ | |
856 | UINT f_op1; \ | |
857 | UINT f_op2; \ | |
858 | UINT f_u4; \ | |
859 | UINT f_Ri; \ | |
860 | unsigned int length; | |
861 | #define EXTRACT_IFMT_ADDI_CODE \ | |
862 | length = 2; \ | |
863 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
864 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
865 | f_u4 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
866 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
867 | ||
868 | #define EXTRACT_IFMT_ADD2_VARS \ | |
869 | /* Instruction fields. */ \ | |
870 | UINT f_op1; \ | |
871 | UINT f_op2; \ | |
872 | SI f_m4; \ | |
873 | UINT f_Ri; \ | |
874 | unsigned int length; | |
875 | #define EXTRACT_IFMT_ADD2_CODE \ | |
876 | length = 2; \ | |
877 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
878 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
879 | f_m4 = ((EXTRACT_UINT (insn, 16, 8, 4)) | (((-1) << (4)))); \ | |
880 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
881 | ||
882 | #define EXTRACT_IFMT_DIV0S_VARS \ | |
883 | /* Instruction fields. */ \ | |
884 | UINT f_op1; \ | |
885 | UINT f_op2; \ | |
886 | UINT f_op3; \ | |
887 | UINT f_Ri; \ | |
888 | unsigned int length; | |
889 | #define EXTRACT_IFMT_DIV0S_CODE \ | |
890 | length = 2; \ | |
891 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
892 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
893 | f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
894 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
895 | ||
896 | #define EXTRACT_IFMT_DIV3_VARS \ | |
897 | /* Instruction fields. */ \ | |
898 | UINT f_op1; \ | |
899 | UINT f_op2; \ | |
900 | UINT f_op3; \ | |
901 | UINT f_op4; \ | |
902 | unsigned int length; | |
903 | #define EXTRACT_IFMT_DIV3_CODE \ | |
904 | length = 2; \ | |
905 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
906 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
907 | f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
908 | f_op4 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
909 | ||
910 | #define EXTRACT_IFMT_LDI8_VARS \ | |
911 | /* Instruction fields. */ \ | |
912 | UINT f_op1; \ | |
913 | UINT f_i8; \ | |
914 | UINT f_Ri; \ | |
915 | unsigned int length; | |
916 | #define EXTRACT_IFMT_LDI8_CODE \ | |
917 | length = 2; \ | |
918 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
919 | f_i8 = EXTRACT_UINT (insn, 16, 4, 8); \ | |
920 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
921 | ||
922 | #define EXTRACT_IFMT_LDI20_VARS \ | |
923 | /* Instruction fields. */ \ | |
924 | UINT f_op1; \ | |
925 | UINT f_i20; \ | |
926 | UINT f_i20_4; \ | |
927 | UINT f_i20_16; \ | |
928 | UINT f_op2; \ | |
929 | UINT f_Ri; \ | |
930 | /* Contents of trailing part of insn. */ \ | |
931 | UINT word_1; \ | |
932 | unsigned int length; | |
933 | #define EXTRACT_IFMT_LDI20_CODE \ | |
934 | length = 4; \ | |
935 | word_1 = GETIMEMUHI (current_cpu, pc + 2); \ | |
936 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
937 | f_i20_4 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
938 | f_i20_16 = (0|(EXTRACT_UINT (word_1, 16, 0, 16) << 0)); \ | |
7a292a7a | 939 | {\ |
c906108c | 940 | f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\ |
7a292a7a | 941 | }\ |
c906108c SS |
942 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ |
943 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
944 | ||
945 | #define EXTRACT_IFMT_LDI32_VARS \ | |
946 | /* Instruction fields. */ \ | |
947 | UINT f_op1; \ | |
948 | UINT f_i32; \ | |
949 | UINT f_op2; \ | |
950 | UINT f_op3; \ | |
951 | UINT f_Ri; \ | |
952 | /* Contents of trailing part of insn. */ \ | |
953 | UINT word_1; \ | |
7a292a7a | 954 | UINT word_2; \ |
c906108c SS |
955 | unsigned int length; |
956 | #define EXTRACT_IFMT_LDI32_CODE \ | |
957 | length = 6; \ | |
7a292a7a SS |
958 | word_1 = GETIMEMUHI (current_cpu, pc + 2); \ |
959 | word_2 = GETIMEMUHI (current_cpu, pc + 4); \ | |
c906108c | 960 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ |
7a292a7a | 961 | f_i32 = (0|(EXTRACT_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_UINT (word_1, 16, 0, 16) << 16)); \ |
c906108c SS |
962 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ |
963 | f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
964 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
965 | ||
966 | #define EXTRACT_IFMT_LDR14_VARS \ | |
967 | /* Instruction fields. */ \ | |
968 | UINT f_op1; \ | |
969 | SI f_disp10; \ | |
970 | UINT f_Ri; \ | |
971 | unsigned int length; | |
972 | #define EXTRACT_IFMT_LDR14_CODE \ | |
973 | length = 2; \ | |
974 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
975 | f_disp10 = ((EXTRACT_INT (insn, 16, 4, 8)) << (2)); \ | |
976 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
977 | ||
978 | #define EXTRACT_IFMT_LDR14UH_VARS \ | |
979 | /* Instruction fields. */ \ | |
980 | UINT f_op1; \ | |
981 | SI f_disp9; \ | |
982 | UINT f_Ri; \ | |
983 | unsigned int length; | |
984 | #define EXTRACT_IFMT_LDR14UH_CODE \ | |
985 | length = 2; \ | |
986 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
987 | f_disp9 = ((EXTRACT_INT (insn, 16, 4, 8)) << (1)); \ | |
988 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
989 | ||
990 | #define EXTRACT_IFMT_LDR14UB_VARS \ | |
991 | /* Instruction fields. */ \ | |
992 | UINT f_op1; \ | |
993 | INT f_disp8; \ | |
994 | UINT f_Ri; \ | |
995 | unsigned int length; | |
996 | #define EXTRACT_IFMT_LDR14UB_CODE \ | |
997 | length = 2; \ | |
998 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
999 | f_disp8 = EXTRACT_INT (insn, 16, 4, 8); \ | |
1000 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
1001 | ||
1002 | #define EXTRACT_IFMT_LDR15_VARS \ | |
1003 | /* Instruction fields. */ \ | |
1004 | UINT f_op1; \ | |
1005 | UINT f_op2; \ | |
1006 | USI f_udisp6; \ | |
1007 | UINT f_Ri; \ | |
1008 | unsigned int length; | |
1009 | #define EXTRACT_IFMT_LDR15_CODE \ | |
1010 | length = 2; \ | |
1011 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1012 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1013 | f_udisp6 = ((EXTRACT_UINT (insn, 16, 8, 4)) << (2)); \ | |
1014 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
1015 | ||
1016 | #define EXTRACT_IFMT_LDR15DR_VARS \ | |
1017 | /* Instruction fields. */ \ | |
1018 | UINT f_op1; \ | |
1019 | UINT f_op2; \ | |
1020 | UINT f_op3; \ | |
1021 | UINT f_Rs2; \ | |
1022 | unsigned int length; | |
1023 | #define EXTRACT_IFMT_LDR15DR_CODE \ | |
1024 | length = 2; \ | |
1025 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1026 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1027 | f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1028 | f_Rs2 = EXTRACT_UINT (insn, 16, 12, 4); \ | |
1029 | ||
1030 | #define EXTRACT_IFMT_MOVDR_VARS \ | |
1031 | /* Instruction fields. */ \ | |
1032 | UINT f_op1; \ | |
1033 | UINT f_op2; \ | |
1034 | UINT f_Rs1; \ | |
1035 | UINT f_Ri; \ | |
1036 | unsigned int length; | |
1037 | #define EXTRACT_IFMT_MOVDR_CODE \ | |
1038 | length = 2; \ | |
1039 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1040 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1041 | f_Rs1 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1042 | f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ | |
1043 | ||
1044 | #define EXTRACT_IFMT_CALL_VARS \ | |
1045 | /* Instruction fields. */ \ | |
1046 | UINT f_op1; \ | |
1047 | UINT f_op5; \ | |
1048 | SI f_rel12; \ | |
1049 | unsigned int length; | |
1050 | #define EXTRACT_IFMT_CALL_CODE \ | |
1051 | length = 2; \ | |
1052 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1053 | f_op5 = EXTRACT_UINT (insn, 16, 4, 1); \ | |
1054 | f_rel12 = ((((EXTRACT_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \ | |
1055 | ||
1056 | #define EXTRACT_IFMT_INT_VARS \ | |
1057 | /* Instruction fields. */ \ | |
1058 | UINT f_op1; \ | |
1059 | UINT f_op2; \ | |
1060 | UINT f_u8; \ | |
1061 | unsigned int length; | |
1062 | #define EXTRACT_IFMT_INT_CODE \ | |
1063 | length = 2; \ | |
1064 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1065 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1066 | f_u8 = EXTRACT_UINT (insn, 16, 8, 8); \ | |
1067 | ||
1068 | #define EXTRACT_IFMT_BRAD_VARS \ | |
1069 | /* Instruction fields. */ \ | |
1070 | UINT f_op1; \ | |
1071 | UINT f_cc; \ | |
1072 | SI f_rel9; \ | |
1073 | unsigned int length; | |
1074 | #define EXTRACT_IFMT_BRAD_CODE \ | |
1075 | length = 2; \ | |
1076 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1077 | f_cc = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1078 | f_rel9 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \ | |
1079 | ||
1080 | #define EXTRACT_IFMT_DMOVR13_VARS \ | |
1081 | /* Instruction fields. */ \ | |
1082 | UINT f_op1; \ | |
1083 | UINT f_op2; \ | |
1084 | USI f_dir10; \ | |
1085 | unsigned int length; | |
1086 | #define EXTRACT_IFMT_DMOVR13_CODE \ | |
1087 | length = 2; \ | |
1088 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1089 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1090 | f_dir10 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (2)); \ | |
1091 | ||
1092 | #define EXTRACT_IFMT_DMOVR13H_VARS \ | |
1093 | /* Instruction fields. */ \ | |
1094 | UINT f_op1; \ | |
1095 | UINT f_op2; \ | |
1096 | USI f_dir9; \ | |
1097 | unsigned int length; | |
1098 | #define EXTRACT_IFMT_DMOVR13H_CODE \ | |
1099 | length = 2; \ | |
1100 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1101 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1102 | f_dir9 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (1)); \ | |
1103 | ||
1104 | #define EXTRACT_IFMT_DMOVR13B_VARS \ | |
1105 | /* Instruction fields. */ \ | |
1106 | UINT f_op1; \ | |
1107 | UINT f_op2; \ | |
1108 | UINT f_dir8; \ | |
1109 | unsigned int length; | |
1110 | #define EXTRACT_IFMT_DMOVR13B_CODE \ | |
1111 | length = 2; \ | |
1112 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1113 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1114 | f_dir8 = EXTRACT_UINT (insn, 16, 8, 8); \ | |
1115 | ||
1116 | #define EXTRACT_IFMT_COPOP_VARS \ | |
1117 | /* Instruction fields. */ \ | |
1118 | UINT f_op1; \ | |
1119 | UINT f_ccc; \ | |
1120 | UINT f_op2; \ | |
1121 | UINT f_op3; \ | |
1122 | UINT f_CRj; \ | |
1123 | UINT f_u4c; \ | |
1124 | UINT f_CRi; \ | |
1125 | /* Contents of trailing part of insn. */ \ | |
1126 | UINT word_1; \ | |
1127 | unsigned int length; | |
1128 | #define EXTRACT_IFMT_COPOP_CODE \ | |
1129 | length = 4; \ | |
1130 | word_1 = GETIMEMUHI (current_cpu, pc + 2); \ | |
1131 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1132 | f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \ | |
1133 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1134 | f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1135 | f_CRj = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \ | |
1136 | f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \ | |
1137 | f_CRi = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \ | |
1138 | ||
1139 | #define EXTRACT_IFMT_COPLD_VARS \ | |
1140 | /* Instruction fields. */ \ | |
1141 | UINT f_op1; \ | |
1142 | UINT f_ccc; \ | |
1143 | UINT f_op2; \ | |
1144 | UINT f_op3; \ | |
1145 | UINT f_Rjc; \ | |
1146 | UINT f_u4c; \ | |
1147 | UINT f_CRi; \ | |
1148 | /* Contents of trailing part of insn. */ \ | |
1149 | UINT word_1; \ | |
1150 | unsigned int length; | |
1151 | #define EXTRACT_IFMT_COPLD_CODE \ | |
1152 | length = 4; \ | |
1153 | word_1 = GETIMEMUHI (current_cpu, pc + 2); \ | |
1154 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1155 | f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \ | |
1156 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1157 | f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1158 | f_Rjc = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \ | |
1159 | f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \ | |
1160 | f_CRi = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \ | |
1161 | ||
1162 | #define EXTRACT_IFMT_COPST_VARS \ | |
1163 | /* Instruction fields. */ \ | |
1164 | UINT f_op1; \ | |
1165 | UINT f_ccc; \ | |
1166 | UINT f_op2; \ | |
1167 | UINT f_op3; \ | |
1168 | UINT f_CRj; \ | |
1169 | UINT f_u4c; \ | |
1170 | UINT f_Ric; \ | |
1171 | /* Contents of trailing part of insn. */ \ | |
1172 | UINT word_1; \ | |
1173 | unsigned int length; | |
1174 | #define EXTRACT_IFMT_COPST_CODE \ | |
1175 | length = 4; \ | |
1176 | word_1 = GETIMEMUHI (current_cpu, pc + 2); \ | |
1177 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1178 | f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \ | |
1179 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1180 | f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ | |
1181 | f_CRj = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \ | |
1182 | f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \ | |
1183 | f_Ric = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \ | |
1184 | ||
1185 | #define EXTRACT_IFMT_ADDSP_VARS \ | |
1186 | /* Instruction fields. */ \ | |
1187 | UINT f_op1; \ | |
1188 | UINT f_op2; \ | |
1189 | SI f_s10; \ | |
1190 | unsigned int length; | |
1191 | #define EXTRACT_IFMT_ADDSP_CODE \ | |
1192 | length = 2; \ | |
1193 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1194 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1195 | f_s10 = ((EXTRACT_INT (insn, 16, 8, 8)) << (2)); \ | |
1196 | ||
1197 | #define EXTRACT_IFMT_LDM0_VARS \ | |
1198 | /* Instruction fields. */ \ | |
1199 | UINT f_op1; \ | |
1200 | UINT f_op2; \ | |
1201 | UINT f_reglist_low_ld; \ | |
1202 | unsigned int length; | |
1203 | #define EXTRACT_IFMT_LDM0_CODE \ | |
1204 | length = 2; \ | |
1205 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1206 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1207 | f_reglist_low_ld = EXTRACT_UINT (insn, 16, 8, 8); \ | |
1208 | ||
1209 | #define EXTRACT_IFMT_LDM1_VARS \ | |
1210 | /* Instruction fields. */ \ | |
1211 | UINT f_op1; \ | |
1212 | UINT f_op2; \ | |
1213 | UINT f_reglist_hi_ld; \ | |
1214 | unsigned int length; | |
1215 | #define EXTRACT_IFMT_LDM1_CODE \ | |
1216 | length = 2; \ | |
1217 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1218 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1219 | f_reglist_hi_ld = EXTRACT_UINT (insn, 16, 8, 8); \ | |
1220 | ||
1221 | #define EXTRACT_IFMT_STM0_VARS \ | |
1222 | /* Instruction fields. */ \ | |
1223 | UINT f_op1; \ | |
1224 | UINT f_op2; \ | |
1225 | UINT f_reglist_low_st; \ | |
1226 | unsigned int length; | |
1227 | #define EXTRACT_IFMT_STM0_CODE \ | |
1228 | length = 2; \ | |
1229 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1230 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1231 | f_reglist_low_st = EXTRACT_UINT (insn, 16, 8, 8); \ | |
1232 | ||
1233 | #define EXTRACT_IFMT_STM1_VARS \ | |
1234 | /* Instruction fields. */ \ | |
1235 | UINT f_op1; \ | |
1236 | UINT f_op2; \ | |
1237 | UINT f_reglist_hi_st; \ | |
1238 | unsigned int length; | |
1239 | #define EXTRACT_IFMT_STM1_CODE \ | |
1240 | length = 2; \ | |
1241 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1242 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1243 | f_reglist_hi_st = EXTRACT_UINT (insn, 16, 8, 8); \ | |
1244 | ||
1245 | #define EXTRACT_IFMT_ENTER_VARS \ | |
1246 | /* Instruction fields. */ \ | |
1247 | UINT f_op1; \ | |
1248 | UINT f_op2; \ | |
1249 | USI f_u10; \ | |
1250 | unsigned int length; | |
1251 | #define EXTRACT_IFMT_ENTER_CODE \ | |
1252 | length = 2; \ | |
1253 | f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ | |
1254 | f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ | |
1255 | f_u10 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (2)); \ | |
1256 | ||
1257 | /* Collection of various things for the trace handler to use. */ | |
1258 | ||
1259 | typedef struct trace_record { | |
1260 | IADDR pc; | |
1261 | /* FIXME:wip */ | |
1262 | } TRACE_RECORD; | |
1263 | ||
1264 | #endif /* CPU_FR30BF_H */ |