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f46e4eb7 JB |
1 | /* Simulator for the FT32 processor |
2 | ||
3666a048 | 3 | Copyright (C) 2008-2021 Free Software Foundation, Inc. |
f46e4eb7 JB |
4 | Contributed by FTDI <support@ftdichip.com> |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
6df01ab8 MF |
21 | /* This must come before any other includes. */ |
22 | #include "defs.h" | |
23 | ||
f46e4eb7 JB |
24 | #include <fcntl.h> |
25 | #include <signal.h> | |
26 | #include <stdlib.h> | |
27 | #include <stdint.h> | |
28 | ||
29 | #include "bfd.h" | |
df68e12b | 30 | #include "sim/callback.h" |
f46e4eb7 | 31 | #include "libiberty.h" |
df68e12b | 32 | #include "sim/sim.h" |
f46e4eb7 JB |
33 | |
34 | #include "sim-main.h" | |
35 | #include "sim-options.h" | |
1fef66b0 | 36 | #include "sim-signal.h" |
f46e4eb7 JB |
37 | |
38 | #include "opcode/ft32.h" | |
39 | ||
40 | /* | |
41 | * FT32 is a Harvard architecture: RAM and code occupy | |
42 | * different address spaces. | |
43 | * | |
44 | * sim and gdb model FT32 memory by adding 0x800000 to RAM | |
45 | * addresses. This means that sim/gdb can treat all addresses | |
46 | * similarly. | |
47 | * | |
48 | * The address space looks like: | |
49 | * | |
50 | * 00000 start of code memory | |
51 | * 3ffff end of code memory | |
52 | * 800000 start of RAM | |
53 | * 80ffff end of RAM | |
54 | */ | |
55 | ||
56 | #define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */ | |
57 | ||
58 | static unsigned long | |
59 | ft32_extract_unsigned_integer (unsigned char *addr, int len) | |
60 | { | |
61 | unsigned long retval; | |
62 | unsigned char *p; | |
63 | unsigned char *startaddr = (unsigned char *) addr; | |
64 | unsigned char *endaddr = startaddr + len; | |
65 | ||
66 | /* Start at the most significant end of the integer, and work towards | |
67 | the least significant. */ | |
68 | retval = 0; | |
69 | ||
70 | for (p = endaddr; p > startaddr;) | |
71 | retval = (retval << 8) | * -- p; | |
72 | ||
73 | return retval; | |
74 | } | |
75 | ||
76 | static void | |
77 | ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val) | |
78 | { | |
79 | unsigned char *p; | |
80 | unsigned char *startaddr = (unsigned char *)addr; | |
81 | unsigned char *endaddr = startaddr + len; | |
82 | ||
83 | for (p = startaddr; p < endaddr; p++) | |
84 | { | |
85 | *p = val & 0xff; | |
86 | val >>= 8; | |
87 | } | |
88 | } | |
89 | ||
90 | /* | |
91 | * Align EA according to its size DW. | |
92 | * The FT32 ignores the low bit of a 16-bit addresss, | |
93 | * and the low two bits of a 32-bit address. | |
94 | */ | |
95 | static uint32_t ft32_align (uint32_t dw, uint32_t ea) | |
96 | { | |
97 | switch (dw) | |
98 | { | |
99 | case 1: | |
100 | ea &= ~1; | |
101 | break; | |
102 | case 2: | |
103 | ea &= ~3; | |
104 | break; | |
105 | default: | |
106 | break; | |
107 | } | |
108 | return ea; | |
109 | } | |
110 | ||
111 | /* Read an item from memory address EA, sized DW. */ | |
112 | static uint32_t | |
113 | ft32_read_item (SIM_DESC sd, int dw, uint32_t ea) | |
114 | { | |
115 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
034685f9 | 116 | address_word cia = CPU_PC_GET (cpu); |
f46e4eb7 JB |
117 | uint8_t byte[4]; |
118 | uint32_t r; | |
119 | ||
120 | ea = ft32_align (dw, ea); | |
121 | ||
122 | switch (dw) { | |
123 | case 0: | |
124 | return sim_core_read_aligned_1 (cpu, cia, read_map, ea); | |
125 | case 1: | |
126 | return sim_core_read_aligned_2 (cpu, cia, read_map, ea); | |
127 | case 2: | |
128 | return sim_core_read_aligned_4 (cpu, cia, read_map, ea); | |
129 | default: | |
130 | abort (); | |
131 | } | |
132 | } | |
133 | ||
134 | /* Write item V to memory address EA, sized DW. */ | |
135 | static void | |
136 | ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v) | |
137 | { | |
138 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
034685f9 | 139 | address_word cia = CPU_PC_GET (cpu); |
f46e4eb7 JB |
140 | uint8_t byte[4]; |
141 | ||
142 | ea = ft32_align (dw, ea); | |
143 | ||
144 | switch (dw) { | |
145 | case 0: | |
146 | sim_core_write_aligned_1 (cpu, cia, write_map, ea, v); | |
147 | break; | |
148 | case 1: | |
149 | sim_core_write_aligned_2 (cpu, cia, write_map, ea, v); | |
150 | break; | |
151 | case 2: | |
152 | sim_core_write_aligned_4 (cpu, cia, write_map, ea, v); | |
153 | break; | |
154 | default: | |
155 | abort (); | |
156 | } | |
157 | } | |
158 | ||
159 | #define ILLEGAL() \ | |
160 | sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL) | |
161 | ||
162 | static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea) | |
163 | { | |
164 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
165 | uint32_t insnpc = cpu->state.pc; | |
166 | uint32_t r; | |
167 | uint8_t byte[4]; | |
168 | ||
169 | ea &= 0x1ffff; | |
170 | if (ea & ~0xffff) | |
171 | { | |
172 | /* Simulate some IO devices */ | |
173 | switch (ea) | |
174 | { | |
bcd68f9e JB |
175 | case 0x10000: |
176 | return getchar (); | |
f46e4eb7 JB |
177 | case 0x1fff4: |
178 | /* Read the simulator cycle timer. */ | |
179 | return cpu->state.cycles / 100; | |
180 | default: | |
181 | sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n", | |
182 | ea, insnpc); | |
183 | ILLEGAL (); | |
184 | } | |
185 | } | |
186 | return ft32_read_item (sd, dw, RAM_BIAS + ea); | |
187 | } | |
188 | ||
189 | static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d) | |
190 | { | |
191 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
192 | ea &= 0x1ffff; | |
193 | if (ea & 0x10000) | |
194 | { | |
195 | /* Simulate some IO devices */ | |
196 | switch (ea) | |
197 | { | |
198 | case 0x10000: | |
199 | /* Console output */ | |
200 | putchar (d & 0xff); | |
201 | break; | |
202 | case 0x1fc80: | |
203 | /* Unlock the PM write port */ | |
204 | cpu->state.pm_unlock = (d == 0x1337f7d1); | |
205 | break; | |
206 | case 0x1fc84: | |
207 | /* Set the PM write address register */ | |
208 | cpu->state.pm_addr = d; | |
209 | break; | |
210 | case 0x1fc88: | |
71c34ca7 JB |
211 | if (cpu->state.pm_unlock) |
212 | { | |
213 | /* Write to PM. */ | |
214 | ft32_write_item (sd, dw, cpu->state.pm_addr, d); | |
215 | cpu->state.pm_addr += 4; | |
216 | } | |
f46e4eb7 JB |
217 | break; |
218 | case 0x1fffc: | |
219 | /* Normal exit. */ | |
220 | sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]); | |
221 | break; | |
222 | case 0x1fff8: | |
223 | sim_io_printf (sd, "Debug write %08x\n", d); | |
224 | break; | |
225 | default: | |
226 | sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea); | |
227 | } | |
228 | } | |
229 | else | |
230 | ft32_write_item (sd, dw, RAM_BIAS + ea, d); | |
231 | } | |
232 | ||
233 | #define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea)) | |
234 | #define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d)) | |
235 | ||
236 | /* LSBS (n) is a mask of the least significant N bits. */ | |
237 | #define LSBS(n) ((1U << (n)) - 1) | |
238 | ||
239 | static void ft32_push (SIM_DESC sd, uint32_t v) | |
240 | { | |
241 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
242 | cpu->state.regs[FT32_HARD_SP] -= 4; | |
243 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; | |
244 | cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v); | |
245 | } | |
246 | ||
247 | static uint32_t ft32_pop (SIM_DESC sd) | |
248 | { | |
249 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
250 | uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]); | |
251 | cpu->state.regs[FT32_HARD_SP] += 4; | |
252 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; | |
253 | return r; | |
254 | } | |
255 | ||
256 | /* Extract the low SIZ bits of N as an unsigned number. */ | |
257 | static int nunsigned (int siz, int n) | |
258 | { | |
259 | return n & LSBS (siz); | |
260 | } | |
261 | ||
262 | /* Extract the low SIZ bits of N as a signed number. */ | |
263 | static int nsigned (int siz, int n) | |
264 | { | |
265 | int shift = (sizeof (int) * 8) - siz; | |
266 | return (n << shift) >> shift; | |
267 | } | |
268 | ||
269 | /* Signed division N / D, matching hw behavior for (MIN_INT, -1). */ | |
270 | static uint32_t ft32sdiv (uint32_t n, uint32_t d) | |
271 | { | |
272 | if (n == 0x80000000UL && d == 0xffffffffUL) | |
273 | return 0x80000000UL; | |
274 | else | |
275 | return (uint32_t)((int)n / (int)d); | |
276 | } | |
277 | ||
278 | /* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */ | |
279 | static uint32_t ft32smod (uint32_t n, uint32_t d) | |
280 | { | |
281 | if (n == 0x80000000UL && d == 0xffffffffUL) | |
282 | return 0; | |
283 | else | |
284 | return (uint32_t)((int)n % (int)d); | |
285 | } | |
286 | ||
287 | /* Circular rotate right N by B bits. */ | |
288 | static uint32_t ror (uint32_t n, uint32_t b) | |
289 | { | |
290 | b &= 31; | |
291 | return (n >> b) | (n << (32 - b)); | |
292 | } | |
293 | ||
294 | /* Implement the BINS machine instruction. | |
295 | See FT32 Programmer's Reference for details. */ | |
296 | static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos) | |
297 | { | |
298 | uint32_t bitmask = LSBS (len) << pos; | |
299 | return (d & ~bitmask) | ((f << pos) & bitmask); | |
300 | } | |
301 | ||
302 | /* Implement the FLIP machine instruction. | |
303 | See FT32 Programmer's Reference for details. */ | |
304 | static uint32_t flip (uint32_t x, uint32_t b) | |
305 | { | |
306 | if (b & 1) | |
307 | x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1; | |
308 | if (b & 2) | |
309 | x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2; | |
310 | if (b & 4) | |
311 | x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4; | |
312 | if (b & 8) | |
313 | x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8; | |
314 | if (b & 16) | |
315 | x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16; | |
316 | return x; | |
317 | } | |
318 | ||
319 | static void | |
320 | step_once (SIM_DESC sd) | |
321 | { | |
322 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
034685f9 | 323 | address_word cia = CPU_PC_GET (cpu); |
f46e4eb7 JB |
324 | uint32_t inst; |
325 | uint32_t dw; | |
326 | uint32_t cb; | |
327 | uint32_t r_d; | |
328 | uint32_t cr; | |
329 | uint32_t cv; | |
330 | uint32_t bt; | |
331 | uint32_t r_1; | |
332 | uint32_t rimm; | |
333 | uint32_t r_2; | |
334 | uint32_t k20; | |
335 | uint32_t pa; | |
336 | uint32_t aa; | |
337 | uint32_t k16; | |
3b4b0a62 | 338 | uint32_t k15; |
f46e4eb7 JB |
339 | uint32_t al; |
340 | uint32_t r_1v; | |
341 | uint32_t rimmv; | |
342 | uint32_t bit_pos; | |
343 | uint32_t bit_len; | |
344 | uint32_t upper; | |
345 | uint32_t insnpc; | |
dcc31d28 JB |
346 | unsigned int sc[2]; |
347 | int isize; | |
f46e4eb7 | 348 | |
f46e4eb7 JB |
349 | inst = ft32_read_item (sd, 2, cpu->state.pc); |
350 | cpu->state.cycles += 1; | |
351 | ||
dcc31d28 JB |
352 | if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b) |
353 | && ft32_decode_shortcode (cpu->state.pc, inst, sc)) | |
354 | { | |
355 | if ((cpu->state.pc & 3) == 0) | |
356 | inst = sc[0]; | |
357 | else | |
358 | inst = sc[1]; | |
359 | isize = 2; | |
360 | } | |
361 | else | |
362 | isize = 4; | |
363 | ||
f46e4eb7 JB |
364 | /* Handle "call 8" (which is FT32's "break" equivalent) here. */ |
365 | if (inst == 0x00340002) | |
366 | { | |
367 | sim_engine_halt (sd, cpu, NULL, | |
368 | cpu->state.pc, | |
369 | sim_stopped, SIM_SIGTRAP); | |
370 | goto escape; | |
371 | } | |
372 | ||
373 | dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ); | |
374 | cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ); | |
375 | r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ); | |
376 | cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ); | |
377 | cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ); | |
378 | bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ); | |
379 | r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ); | |
380 | rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ); | |
381 | r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ); | |
382 | k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ)); | |
383 | pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ); | |
384 | aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ); | |
385 | k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ); | |
3b4b0a62 JB |
386 | k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ); |
387 | if (k15 & 0x80) | |
388 | k15 ^= 0x7f00; | |
389 | if (k15 & 0x4000) | |
390 | k15 -= 0x8000; | |
f46e4eb7 JB |
391 | al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ); |
392 | ||
393 | r_1v = cpu->state.regs[r_1]; | |
394 | rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f]; | |
395 | ||
396 | bit_pos = rimmv & 31; | |
397 | bit_len = 0xf & (rimmv >> 5); | |
398 | if (bit_len == 0) | |
399 | bit_len = 16; | |
400 | ||
401 | upper = (inst >> 27); | |
402 | ||
403 | insnpc = cpu->state.pc; | |
dcc31d28 | 404 | cpu->state.pc += isize; |
f46e4eb7 JB |
405 | switch (upper) |
406 | { | |
407 | case FT32_PAT_TOC: | |
408 | case FT32_PAT_TOCI: | |
409 | { | |
410 | int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv); | |
411 | if (take) | |
412 | { | |
413 | cpu->state.cycles += 1; | |
414 | if (bt) | |
415 | ft32_push (sd, cpu->state.pc); /* this is a call. */ | |
416 | if (upper == FT32_PAT_TOC) | |
417 | cpu->state.pc = pa << 2; | |
418 | else | |
419 | cpu->state.pc = cpu->state.regs[r_2]; | |
420 | if (cpu->state.pc == 0x8) | |
421 | goto escape; | |
422 | } | |
423 | } | |
424 | break; | |
425 | ||
426 | case FT32_PAT_ALUOP: | |
427 | case FT32_PAT_CMPOP: | |
428 | { | |
429 | uint32_t result; | |
430 | switch (al) | |
431 | { | |
432 | case 0x0: result = r_1v + rimmv; break; | |
433 | case 0x1: result = ror (r_1v, rimmv); break; | |
434 | case 0x2: result = r_1v - rimmv; break; | |
435 | case 0x3: result = (r_1v << 10) | (1023 & rimmv); break; | |
436 | case 0x4: result = r_1v & rimmv; break; | |
437 | case 0x5: result = r_1v | rimmv; break; | |
438 | case 0x6: result = r_1v ^ rimmv; break; | |
439 | case 0x7: result = ~(r_1v ^ rimmv); break; | |
440 | case 0x8: result = r_1v << rimmv; break; | |
441 | case 0x9: result = r_1v >> rimmv; break; | |
442 | case 0xa: result = (int32_t)r_1v >> rimmv; break; | |
443 | case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break; | |
444 | case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break; | |
445 | case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break; | |
446 | case 0xe: result = flip (r_1v, rimmv); break; | |
447 | default: | |
448 | sim_io_eprintf (sd, "Unhandled alu %#x\n", al); | |
449 | ILLEGAL (); | |
450 | } | |
451 | if (upper == FT32_PAT_ALUOP) | |
452 | cpu->state.regs[r_d] = result; | |
453 | else | |
454 | { | |
455 | uint32_t dwmask = 0; | |
456 | int dwsiz = 0; | |
457 | int zero; | |
458 | int sign; | |
459 | int ahi; | |
460 | int bhi; | |
461 | int overflow; | |
462 | int carry; | |
463 | int bit; | |
464 | uint64_t ra; | |
465 | uint64_t rb; | |
466 | int above; | |
467 | int greater; | |
468 | int greatereq; | |
469 | ||
470 | switch (dw) | |
471 | { | |
472 | case 0: dwsiz = 7; dwmask = 0xffU; break; | |
473 | case 1: dwsiz = 15; dwmask = 0xffffU; break; | |
474 | case 2: dwsiz = 31; dwmask = 0xffffffffU; break; | |
475 | } | |
476 | ||
477 | zero = (0 == (result & dwmask)); | |
478 | sign = 1 & (result >> dwsiz); | |
479 | ahi = 1 & (r_1v >> dwsiz); | |
480 | bhi = 1 & (rimmv >> dwsiz); | |
481 | overflow = (sign != ahi) & (ahi == !bhi); | |
482 | bit = (dwsiz + 1); | |
483 | ra = r_1v & dwmask; | |
484 | rb = rimmv & dwmask; | |
485 | switch (al) | |
486 | { | |
487 | case 0x0: carry = 1 & ((ra + rb) >> bit); break; | |
488 | case 0x2: carry = 1 & ((ra - rb) >> bit); break; | |
489 | default: carry = 0; break; | |
490 | } | |
491 | above = (!carry & !zero); | |
492 | greater = (sign == overflow) & !zero; | |
493 | greatereq = (sign == overflow); | |
494 | ||
495 | cpu->state.regs[r_d] = ( | |
496 | (above << 6) | | |
497 | (greater << 5) | | |
498 | (greatereq << 4) | | |
499 | (sign << 3) | | |
500 | (overflow << 2) | | |
501 | (carry << 1) | | |
502 | (zero << 0)); | |
503 | } | |
504 | } | |
505 | break; | |
506 | ||
507 | case FT32_PAT_LDK: | |
508 | cpu->state.regs[r_d] = k20; | |
509 | break; | |
510 | ||
511 | case FT32_PAT_LPM: | |
512 | cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2); | |
513 | cpu->state.cycles += 1; | |
514 | break; | |
515 | ||
516 | case FT32_PAT_LPMI: | |
3b4b0a62 | 517 | cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k15); |
f46e4eb7 JB |
518 | cpu->state.cycles += 1; |
519 | break; | |
520 | ||
521 | case FT32_PAT_STA: | |
522 | cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); | |
523 | break; | |
524 | ||
525 | case FT32_PAT_STI: | |
3b4b0a62 | 526 | cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r_1]); |
f46e4eb7 JB |
527 | break; |
528 | ||
529 | case FT32_PAT_LDA: | |
530 | cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa); | |
531 | cpu->state.cycles += 1; | |
532 | break; | |
533 | ||
534 | case FT32_PAT_LDI: | |
3b4b0a62 | 535 | cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15); |
f46e4eb7 JB |
536 | cpu->state.cycles += 1; |
537 | break; | |
538 | ||
539 | case FT32_PAT_EXA: | |
540 | { | |
541 | uint32_t tmp; | |
542 | tmp = cpu_mem_read (sd, dw, aa); | |
543 | cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]); | |
544 | cpu->state.regs[r_d] = tmp; | |
545 | cpu->state.cycles += 1; | |
546 | } | |
547 | break; | |
548 | ||
549 | case FT32_PAT_EXI: | |
550 | { | |
551 | uint32_t tmp; | |
3b4b0a62 JB |
552 | tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15); |
553 | cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]); | |
f46e4eb7 JB |
554 | cpu->state.regs[r_d] = tmp; |
555 | cpu->state.cycles += 1; | |
556 | } | |
557 | break; | |
558 | ||
559 | case FT32_PAT_PUSH: | |
560 | ft32_push (sd, r_1v); | |
561 | break; | |
562 | ||
563 | case FT32_PAT_LINK: | |
564 | ft32_push (sd, cpu->state.regs[r_d]); | |
565 | cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP]; | |
566 | cpu->state.regs[FT32_HARD_SP] -= k16; | |
567 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; | |
568 | break; | |
569 | ||
570 | case FT32_PAT_UNLINK: | |
571 | cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d]; | |
572 | cpu->state.regs[FT32_HARD_SP] &= 0xffff; | |
573 | cpu->state.regs[r_d] = ft32_pop (sd); | |
574 | break; | |
575 | ||
576 | case FT32_PAT_POP: | |
577 | cpu->state.cycles += 1; | |
578 | cpu->state.regs[r_d] = ft32_pop (sd); | |
579 | break; | |
580 | ||
581 | case FT32_PAT_RETURN: | |
582 | cpu->state.pc = ft32_pop (sd); | |
583 | break; | |
584 | ||
585 | case FT32_PAT_FFUOP: | |
586 | switch (al) | |
587 | { | |
588 | case 0x0: | |
589 | cpu->state.regs[r_d] = r_1v / rimmv; | |
590 | break; | |
591 | case 0x1: | |
592 | cpu->state.regs[r_d] = r_1v % rimmv; | |
593 | break; | |
594 | case 0x2: | |
595 | cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv); | |
596 | break; | |
597 | case 0x3: | |
598 | cpu->state.regs[r_d] = ft32smod (r_1v, rimmv); | |
599 | break; | |
600 | ||
601 | case 0x4: | |
602 | { | |
603 | /* strcmp instruction. */ | |
604 | uint32_t a = r_1v; | |
605 | uint32_t b = rimmv; | |
606 | uint32_t i = 0; | |
607 | while ((GET_BYTE (a + i) != 0) && | |
608 | (GET_BYTE (a + i) == GET_BYTE (b + i))) | |
609 | i++; | |
610 | cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i); | |
611 | } | |
612 | break; | |
613 | ||
614 | case 0x5: | |
615 | { | |
616 | /* memcpy instruction. */ | |
617 | uint32_t src = r_1v; | |
618 | uint32_t dst = cpu->state.regs[r_d]; | |
619 | uint32_t i; | |
395b0d8a | 620 | for (i = 0; i < (rimmv & 0x7fff); i++) |
f46e4eb7 JB |
621 | PUT_BYTE (dst + i, GET_BYTE (src + i)); |
622 | } | |
623 | break; | |
624 | case 0x6: | |
625 | { | |
626 | /* strlen instruction. */ | |
627 | uint32_t src = r_1v; | |
628 | uint32_t i; | |
629 | for (i = 0; GET_BYTE (src + i) != 0; i++) | |
630 | ; | |
631 | cpu->state.regs[r_d] = i; | |
632 | } | |
633 | break; | |
634 | case 0x7: | |
635 | { | |
636 | /* memset instruction. */ | |
637 | uint32_t dst = cpu->state.regs[r_d]; | |
638 | uint32_t i; | |
395b0d8a | 639 | for (i = 0; i < (rimmv & 0x7fff); i++) |
f46e4eb7 JB |
640 | PUT_BYTE (dst + i, r_1v); |
641 | } | |
642 | break; | |
643 | case 0x8: | |
644 | cpu->state.regs[r_d] = r_1v * rimmv; | |
645 | break; | |
646 | case 0x9: | |
647 | cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32; | |
648 | break; | |
649 | case 0xa: | |
650 | { | |
651 | /* stpcpy instruction. */ | |
652 | uint32_t src = r_1v; | |
653 | uint32_t dst = cpu->state.regs[r_d]; | |
654 | uint32_t i; | |
655 | for (i = 0; GET_BYTE (src + i) != 0; i++) | |
656 | PUT_BYTE (dst + i, GET_BYTE (src + i)); | |
657 | PUT_BYTE (dst + i, 0); | |
658 | cpu->state.regs[r_d] = dst + i; | |
659 | } | |
660 | break; | |
661 | case 0xe: | |
662 | { | |
663 | /* streamout instruction. */ | |
664 | uint32_t i; | |
665 | uint32_t src = cpu->state.regs[r_1]; | |
666 | for (i = 0; i < rimmv; i += (1 << dw)) | |
667 | { | |
668 | cpu_mem_write (sd, | |
669 | dw, | |
670 | cpu->state.regs[r_d], | |
671 | cpu_mem_read (sd, dw, src)); | |
672 | src += (1 << dw); | |
673 | } | |
674 | } | |
675 | break; | |
676 | default: | |
677 | sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc); | |
678 | ILLEGAL (); | |
679 | } | |
680 | break; | |
681 | ||
682 | default: | |
683 | sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc); | |
684 | ILLEGAL (); | |
685 | } | |
686 | cpu->state.num_i++; | |
687 | ||
688 | escape: | |
689 | ; | |
690 | } | |
691 | ||
692 | void | |
693 | sim_engine_run (SIM_DESC sd, | |
694 | int next_cpu_nr, /* ignore */ | |
695 | int nr_cpus, /* ignore */ | |
696 | int siggnal) /* ignore */ | |
697 | { | |
698 | sim_cpu *cpu; | |
699 | ||
700 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
701 | ||
702 | cpu = STATE_CPU (sd, 0); | |
703 | ||
704 | while (1) | |
705 | { | |
706 | step_once (sd); | |
707 | if (sim_events_tick (sd)) | |
708 | sim_events_process (sd); | |
709 | } | |
710 | } | |
711 | ||
f46e4eb7 JB |
712 | static uint32_t * |
713 | ft32_lookup_register (SIM_CPU *cpu, int nr) | |
714 | { | |
715 | /* Handle the register number translation here. | |
716 | * Sim registers are 0-31. | |
717 | * Other tools (gcc, gdb) use: | |
718 | * 0 - fp | |
719 | * 1 - sp | |
720 | * 2 - r0 | |
721 | * 31 - cc | |
722 | */ | |
723 | ||
724 | if ((nr < 0) || (nr > 32)) | |
725 | { | |
726 | sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr); | |
727 | abort (); | |
728 | } | |
729 | ||
730 | switch (nr) | |
731 | { | |
732 | case FT32_FP_REGNUM: | |
733 | return &cpu->state.regs[FT32_HARD_FP]; | |
734 | case FT32_SP_REGNUM: | |
735 | return &cpu->state.regs[FT32_HARD_SP]; | |
736 | case FT32_CC_REGNUM: | |
737 | return &cpu->state.regs[FT32_HARD_CC]; | |
738 | case FT32_PC_REGNUM: | |
739 | return &cpu->state.pc; | |
740 | default: | |
741 | return &cpu->state.regs[nr - 2]; | |
742 | } | |
743 | } | |
744 | ||
745 | static int | |
746 | ft32_reg_store (SIM_CPU *cpu, | |
747 | int rn, | |
748 | unsigned char *memory, | |
749 | int length) | |
750 | { | |
751 | if (0 <= rn && rn <= 32) | |
752 | { | |
753 | if (length == 4) | |
754 | *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4); | |
755 | ||
756 | return 4; | |
757 | } | |
758 | else | |
759 | return 0; | |
760 | } | |
761 | ||
762 | static int | |
763 | ft32_reg_fetch (SIM_CPU *cpu, | |
764 | int rn, | |
765 | unsigned char *memory, | |
766 | int length) | |
767 | { | |
768 | if (0 <= rn && rn <= 32) | |
769 | { | |
770 | if (length == 4) | |
771 | ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn)); | |
772 | ||
773 | return 4; | |
774 | } | |
775 | else | |
776 | return 0; | |
777 | } | |
778 | ||
779 | static sim_cia | |
780 | ft32_pc_get (SIM_CPU *cpu) | |
781 | { | |
65f90968 | 782 | return cpu->state.pc; |
f46e4eb7 JB |
783 | } |
784 | ||
785 | static void | |
786 | ft32_pc_set (SIM_CPU *cpu, sim_cia newpc) | |
787 | { | |
788 | cpu->state.pc = newpc; | |
789 | } | |
790 | ||
791 | /* Cover function of sim_state_free to free the cpu buffers as well. */ | |
792 | ||
793 | static void | |
794 | free_state (SIM_DESC sd) | |
795 | { | |
796 | if (STATE_MODULES (sd) != NULL) | |
797 | sim_module_uninstall (sd); | |
798 | sim_cpu_free_all (sd); | |
799 | sim_state_free (sd); | |
800 | } | |
801 | ||
802 | SIM_DESC | |
803 | sim_open (SIM_OPEN_KIND kind, | |
804 | host_callback *cb, | |
805 | struct bfd *abfd, | |
2e3d4f4d | 806 | char * const *argv) |
f46e4eb7 JB |
807 | { |
808 | char c; | |
809 | size_t i; | |
810 | SIM_DESC sd = sim_state_alloc (kind, cb); | |
811 | ||
ba307cdd MF |
812 | /* Set default options before parsing user options. */ |
813 | current_alignment = STRICT_ALIGNMENT; | |
f9a4d543 | 814 | current_target_byte_order = BFD_ENDIAN_LITTLE; |
ba307cdd | 815 | |
f46e4eb7 | 816 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
d5a71b11 | 817 | if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) |
f46e4eb7 JB |
818 | { |
819 | free_state (sd); | |
820 | return 0; | |
821 | } | |
822 | ||
823 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) | |
824 | { | |
825 | free_state (sd); | |
826 | return 0; | |
827 | } | |
828 | ||
77cf2ef5 | 829 | /* The parser will print an error message for us, so we silently return. */ |
f46e4eb7 JB |
830 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
831 | { | |
832 | free_state (sd); | |
833 | return 0; | |
834 | } | |
835 | ||
836 | /* Allocate external memory if none specified by user. | |
837 | Use address 4 here in case the user wanted address 0 unmapped. */ | |
838 | if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) | |
839 | { | |
840 | sim_do_command (sd, "memory region 0x00000000,0x40000"); | |
841 | sim_do_command (sd, "memory region 0x800000,0x10000"); | |
842 | } | |
843 | ||
844 | /* Check for/establish the reference program image. */ | |
845 | if (sim_analyze_program (sd, | |
846 | (STATE_PROG_ARGV (sd) != NULL | |
847 | ? *STATE_PROG_ARGV (sd) | |
848 | : NULL), abfd) != SIM_RC_OK) | |
849 | { | |
850 | free_state (sd); | |
851 | return 0; | |
852 | } | |
853 | ||
854 | /* Configure/verify the target byte order and other runtime | |
855 | configuration options. */ | |
856 | if (sim_config (sd) != SIM_RC_OK) | |
857 | { | |
858 | free_state (sd); | |
859 | return 0; | |
860 | } | |
861 | ||
862 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
863 | { | |
864 | free_state (sd); | |
865 | return 0; | |
866 | } | |
867 | ||
868 | /* CPU specific initialization. */ | |
869 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) | |
870 | { | |
871 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
872 | ||
873 | CPU_REG_FETCH (cpu) = ft32_reg_fetch; | |
874 | CPU_REG_STORE (cpu) = ft32_reg_store; | |
875 | CPU_PC_FETCH (cpu) = ft32_pc_get; | |
876 | CPU_PC_STORE (cpu) = ft32_pc_set; | |
877 | } | |
878 | ||
879 | return sd; | |
880 | } | |
881 | ||
f46e4eb7 JB |
882 | SIM_RC |
883 | sim_create_inferior (SIM_DESC sd, | |
884 | struct bfd *abfd, | |
2e3d4f4d MF |
885 | char * const *argv, |
886 | char * const *env) | |
f46e4eb7 JB |
887 | { |
888 | uint32_t addr; | |
889 | sim_cpu *cpu = STATE_CPU (sd, 0); | |
890 | ||
891 | /* Set the PC. */ | |
892 | if (abfd != NULL) | |
893 | addr = bfd_get_start_address (abfd); | |
894 | else | |
895 | addr = 0; | |
896 | ||
0e967299 MF |
897 | /* Standalone mode (i.e. `run`) will take care of the argv for us in |
898 | sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim' | |
899 | with `gdb`), we need to handle it because the user can change the | |
900 | argv on the fly via gdb's 'run'. */ | |
901 | if (STATE_PROG_ARGV (sd) != argv) | |
f46e4eb7 JB |
902 | { |
903 | freeargv (STATE_PROG_ARGV (sd)); | |
904 | STATE_PROG_ARGV (sd) = dupargv (argv); | |
905 | } | |
906 | cpu->state.regs[FT32_HARD_SP] = addr; | |
907 | cpu->state.num_i = 0; | |
908 | cpu->state.cycles = 0; | |
909 | cpu->state.next_tick_cycle = 100000; | |
910 | ||
911 | return SIM_RC_OK; | |
912 | } |