Commit | Line | Data |
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ce51bde6 DE |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
ce51bde6 DE |
18 | */ |
19 | ||
e656ecf9 DE |
20 | #include "config.h" |
21 | ||
ce51bde6 | 22 | #include <signal.h> |
e656ecf9 DE |
23 | #ifdef HAVE_TIME_H |
24 | #include <time.h> | |
25 | #endif | |
26 | #ifdef HAVE_STDLIB_H | |
27 | #include <stdlib.h> | |
7478904c | 28 | #endif |
ce51bde6 | 29 | #include <sys/param.h> |
4dfb4ffc | 30 | #include "wait.h" |
0693d363 | 31 | #include "ansidecl.h" |
e656ecf9 | 32 | #include "callback.h" |
a415cf0a | 33 | #include "remote-sim.h" |
7478904c | 34 | #include "bfd.h" |
ce51bde6 DE |
35 | |
36 | int debug; | |
37 | ||
38 | ||
39 | #define X(op, size) op*4+size | |
40 | ||
28655f00 | 41 | #define SP (h8300hmode ? SL:SW) |
ce51bde6 DE |
42 | #define SB 0 |
43 | #define SW 1 | |
44 | #define SL 2 | |
45 | #define OP_REG 1 | |
46 | #define OP_DEC 2 | |
47 | #define OP_DISP 3 | |
48 | #define OP_INC 4 | |
49 | #define OP_PCREL 5 | |
50 | #define OP_MEM 6 | |
51 | #define OP_CCR 7 | |
52 | #define OP_IMM 8 | |
53 | #define OP_ABS 10 | |
54 | #define h8_opcodes ops | |
55 | #define DEFINE_TABLE | |
56 | #include "opcode/h8300.h" | |
57 | ||
58 | #include "inst.h" | |
59 | ||
60 | #define LOW_BYTE(x) ((x) & 0xff) | |
61 | #define HIGH_BYTE(x) (((x)>>8) & 0xff) | |
62 | #define P(X,Y) ((X<<8) | Y) | |
63 | ||
64 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; | |
65 | ||
66 | #define GETSR() \ | |
67 | c = (cpu.ccr >> 0) & 1;\ | |
68 | v = (cpu.ccr >> 1) & 1;\ | |
69 | nz = !((cpu.ccr >> 2) & 1);\ | |
70 | n = (cpu.ccr >> 3) & 1; | |
71 | ||
72 | #ifdef __CHAR_IS_SIGNED__ | |
73 | #define SEXTCHAR(x) ((char)(x)) | |
74 | #endif | |
75 | ||
76 | #ifndef SEXTCHAR | |
77 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff):x) | |
78 | #endif | |
79 | ||
80 | #define UEXTCHAR(x) ((x) & 0xff) | |
81 | #define UEXTSHORT(x) ((x) & 0xffff) | |
82 | #define SEXTSHORT(x) ((short)(x)) | |
83 | ||
84 | static cpu_state_type cpu; | |
85 | ||
28655f00 | 86 | int h8300hmode = 0; |
ce51bde6 | 87 | |
e656ecf9 DE |
88 | static int memory_size; |
89 | ||
ce51bde6 DE |
90 | |
91 | static int | |
92 | get_now () | |
93 | { | |
7478904c | 94 | #ifndef WIN32 |
0693d363 | 95 | return time (0); |
28655f00 | 96 | #endif |
7478904c | 97 | return 0; |
ce51bde6 DE |
98 | } |
99 | ||
100 | static int | |
101 | now_persec () | |
102 | { | |
28655f00 | 103 | return 1; |
ce51bde6 DE |
104 | } |
105 | ||
106 | ||
107 | static int | |
108 | bitfrom (x) | |
109 | { | |
ce51bde6 DE |
110 | switch (x & SIZE) |
111 | { | |
112 | case L_8: | |
113 | return SB; | |
114 | case L_16: | |
115 | return SW; | |
116 | case L_32: | |
117 | return SL; | |
118 | case L_P: | |
28655f00 | 119 | return h8300hmode ? SL : SW; |
ce51bde6 | 120 | } |
ce51bde6 DE |
121 | } |
122 | ||
123 | static | |
124 | unsigned int | |
125 | lvalue (x, rn) | |
126 | { | |
127 | switch (x / 4) | |
128 | { | |
129 | case OP_DISP: | |
0693d363 | 130 | if (rn == 8) |
ce51bde6 | 131 | { |
0693d363 | 132 | return X (OP_IMM, SP); |
ce51bde6 | 133 | } |
0693d363 DE |
134 | return X (OP_REG, SP); |
135 | ||
ce51bde6 DE |
136 | case OP_MEM: |
137 | ||
138 | return X (OP_MEM, SP); | |
139 | default: | |
140 | abort (); | |
141 | } | |
142 | } | |
143 | ||
144 | static unsigned int | |
145 | decode (addr, data, dst) | |
146 | int addr; | |
147 | unsigned char *data; | |
148 | decoded_inst *dst; | |
149 | ||
150 | { | |
151 | int rs = 0; | |
152 | int rd = 0; | |
153 | int rdisp = 0; | |
154 | int abs = 0; | |
155 | int plen = 0; | |
e24146ec | 156 | int bit = 0; |
ce51bde6 DE |
157 | |
158 | struct h8_opcode *q = h8_opcodes; | |
159 | int size = 0; | |
160 | dst->dst.type = -1; | |
161 | dst->src.type = -1; | |
162 | /* Find the exact opcode/arg combo */ | |
163 | while (q->name) | |
164 | { | |
165 | op_type *nib; | |
166 | unsigned int len = 0; | |
167 | ||
168 | nib = q->data.nib; | |
169 | ||
170 | while (1) | |
171 | { | |
172 | op_type looking_for = *nib; | |
173 | int thisnib = data[len >> 1]; | |
174 | ||
175 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
176 | ||
0693d363 | 177 | if (looking_for < 16 && looking_for >= 0) |
ce51bde6 | 178 | { |
ce51bde6 DE |
179 | if (looking_for != thisnib) |
180 | goto fail; | |
181 | } | |
182 | else | |
183 | { | |
ce51bde6 DE |
184 | if ((int) looking_for & (int) B31) |
185 | { | |
186 | if (!(((int) thisnib & 0x8) != 0)) | |
187 | goto fail; | |
188 | looking_for = (op_type) ((int) looking_for & ~(int) | |
189 | B31); | |
190 | thisnib &= 0x7; | |
ce51bde6 DE |
191 | } |
192 | if ((int) looking_for & (int) B30) | |
193 | { | |
194 | if (!(((int) thisnib & 0x8) == 0)) | |
195 | goto fail; | |
196 | looking_for = (op_type) ((int) looking_for & ~(int) B30); | |
197 | } | |
198 | if (looking_for & DBIT) | |
199 | { | |
0693d363 DE |
200 | if ((looking_for & 5) != (thisnib & 5)) |
201 | goto fail; | |
ce51bde6 DE |
202 | abs = (thisnib & 0x8) ? 2 : 1; |
203 | } | |
204 | else if (looking_for & (REG | IND | INC | DEC)) | |
205 | { | |
206 | if (looking_for & REG) | |
207 | { | |
208 | /* | |
209 | * Can work out size from the | |
210 | * register | |
211 | */ | |
212 | size = bitfrom (looking_for); | |
213 | } | |
214 | if (looking_for & SRC) | |
215 | { | |
216 | rs = thisnib; | |
217 | } | |
218 | else | |
219 | { | |
220 | rd = thisnib; | |
221 | } | |
222 | } | |
223 | else if (looking_for & L_16) | |
224 | { | |
225 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
226 | plen = 16; | |
0693d363 | 227 | if (looking_for & (PCREL | DISP)) |
ce51bde6 DE |
228 | { |
229 | abs = (short) (abs); | |
230 | } | |
231 | } | |
232 | else if (looking_for & ABSJMP) | |
233 | { | |
234 | abs = | |
235 | (data[1] << 16) | |
236 | | (data[2] << 8) | |
237 | | (data[3]); | |
238 | } | |
0693d363 DE |
239 | else if (looking_for & MEMIND) |
240 | { | |
241 | abs = data[1]; | |
242 | } | |
ce51bde6 DE |
243 | else if (looking_for & L_32) |
244 | { | |
245 | int i = len >> 1; | |
246 | abs = (data[i] << 24) | |
247 | | (data[i + 1] << 16) | |
248 | | (data[i + 2] << 8) | |
249 | | (data[i + 3]); | |
250 | ||
251 | plen = 32; | |
ce51bde6 DE |
252 | } |
253 | else if (looking_for & L_24) | |
254 | { | |
255 | int i = len >> 1; | |
0693d363 | 256 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
ce51bde6 DE |
257 | plen = 24; |
258 | } | |
259 | else if (looking_for & IGNORE) | |
260 | { | |
0693d363 | 261 | /* nothing to do */ |
ce51bde6 DE |
262 | } |
263 | else if (looking_for & DISPREG) | |
264 | { | |
265 | rdisp = thisnib & 0x7; | |
266 | } | |
267 | else if (looking_for & KBIT) | |
268 | { | |
269 | switch (thisnib) | |
270 | { | |
271 | case 9: | |
272 | abs = 4; | |
273 | break; | |
274 | case 8: | |
275 | abs = 2; | |
276 | break; | |
277 | case 0: | |
278 | abs = 1; | |
279 | break; | |
280 | } | |
281 | } | |
282 | else if (looking_for & L_8) | |
283 | { | |
284 | plen = 8; | |
285 | ||
286 | if (looking_for & PCREL) | |
287 | { | |
288 | abs = SEXTCHAR (data[len >> 1]); | |
289 | } | |
e24146ec JL |
290 | else if (looking_for & ABS8MEM) |
291 | { | |
292 | plen = 8; | |
293 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
294 | abs |= data[len >> 1] & 0xff ; | |
295 | } | |
296 | else | |
ce51bde6 DE |
297 | { |
298 | abs = data[len >> 1] & 0xff; | |
299 | } | |
300 | } | |
301 | else if (looking_for & L_3) | |
302 | { | |
303 | plen = 3; | |
304 | ||
e24146ec | 305 | bit = thisnib; |
ce51bde6 DE |
306 | } |
307 | else if (looking_for == E) | |
308 | { | |
309 | dst->op = q; | |
310 | ||
311 | /* Fill in the args */ | |
312 | { | |
313 | op_type *args = q->args.nib; | |
314 | int hadone = 0; | |
315 | ||
ce51bde6 DE |
316 | while (*args != E) |
317 | { | |
318 | int x = *args; | |
319 | int rn = (x & DST) ? rd : rs; | |
320 | ea_type *p; | |
321 | ||
322 | if (x & DST) | |
323 | { | |
324 | p = &(dst->dst); | |
325 | } | |
326 | else | |
327 | { | |
328 | p = &(dst->src); | |
329 | } | |
330 | ||
e24146ec JL |
331 | if (x & (L_3)) |
332 | { | |
333 | p->type = X (OP_IMM, size); | |
334 | p->literal = bit; | |
335 | } | |
336 | else if (x & (IMM | KBIT | DBIT)) | |
ce51bde6 DE |
337 | { |
338 | p->type = X (OP_IMM, size); | |
339 | p->literal = abs; | |
340 | } | |
341 | else if (x & REG) | |
342 | { | |
0693d363 DE |
343 | /* Reset the size, some |
344 | ops (like mul) have two sizes */ | |
345 | ||
ce51bde6 DE |
346 | size = bitfrom (x); |
347 | p->type = X (OP_REG, size); | |
348 | p->reg = rn; | |
349 | } | |
350 | else if (x & INC) | |
351 | { | |
352 | p->type = X (OP_INC, size); | |
353 | p->reg = rn & 0x7; | |
354 | } | |
355 | else if (x & DEC) | |
356 | { | |
357 | p->type = X (OP_DEC, size); | |
358 | p->reg = rn & 0x7; | |
359 | } | |
360 | else if (x & IND) | |
361 | { | |
362 | p->type = X (OP_DISP, size); | |
363 | p->reg = rn & 0x7; | |
364 | p->literal = 0; | |
365 | } | |
e24146ec | 366 | else if (x & (ABS | ABSJMP | ABS8MEM)) |
ce51bde6 DE |
367 | { |
368 | p->type = X (OP_DISP, size); | |
369 | p->literal = abs; | |
370 | p->reg = 8; | |
371 | } | |
372 | else if (x & MEMIND) | |
373 | { | |
374 | p->type = X (OP_MEM, size); | |
375 | p->literal = abs; | |
376 | } | |
377 | else if (x & PCREL) | |
378 | { | |
379 | p->type = X (OP_PCREL, size); | |
380 | p->literal = abs + addr + 2; | |
0693d363 DE |
381 | if (x & L_16) |
382 | p->literal += 2; | |
ce51bde6 DE |
383 | } |
384 | else if (x & ABSJMP) | |
385 | { | |
386 | p->type = X (OP_IMM, SP); | |
387 | p->literal = abs; | |
388 | } | |
389 | else if (x & DISP) | |
390 | { | |
391 | p->type = X (OP_DISP, size); | |
392 | p->literal = abs; | |
393 | p->reg = rdisp & 0x7; | |
394 | } | |
395 | else if (x & CCR) | |
396 | { | |
397 | p->type = OP_CCR; | |
398 | } | |
399 | else | |
400 | printf ("Hmmmm %x", x); | |
401 | ||
ce51bde6 DE |
402 | args++; |
403 | } | |
404 | } | |
405 | ||
406 | /* | |
0693d363 DE |
407 | * But a jmp or a jsr gets |
408 | * automagically lvalued, since we | |
409 | * branch to their address not their | |
410 | * contents | |
411 | */ | |
ce51bde6 DE |
412 | if (q->how == O (O_JSR, SB) |
413 | || q->how == O (O_JMP, SB)) | |
414 | { | |
415 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
416 | } | |
417 | ||
ce51bde6 DE |
418 | if (dst->dst.type == -1) |
419 | dst->dst = dst->src; | |
0693d363 | 420 | |
ce51bde6 DE |
421 | dst->opcode = q->how; |
422 | dst->cycles = q->time; | |
423 | ||
424 | /* And a jsr to 0xc4 is turned into a magic trap */ | |
0693d363 DE |
425 | |
426 | if (dst->opcode == O (O_JSR, SB)) | |
ce51bde6 | 427 | { |
0693d363 | 428 | if (dst->src.literal == 0xc4) |
ce51bde6 | 429 | { |
0693d363 | 430 | dst->opcode = O (O_SYSCALL, SB); |
ce51bde6 DE |
431 | } |
432 | } | |
0693d363 | 433 | |
ce51bde6 DE |
434 | dst->next_pc = addr + len / 2; |
435 | return; | |
436 | } | |
437 | else | |
438 | { | |
439 | printf ("Dont understand %x \n", looking_for); | |
440 | } | |
441 | } | |
0693d363 | 442 | |
ce51bde6 DE |
443 | len++; |
444 | nib++; | |
445 | } | |
0693d363 | 446 | |
ce51bde6 DE |
447 | fail: |
448 | q++; | |
449 | } | |
0693d363 | 450 | |
ce51bde6 DE |
451 | dst->opcode = O (O_ILL, SB); |
452 | } | |
453 | ||
454 | ||
455 | static void | |
456 | compile (pc) | |
457 | { | |
458 | int idx; | |
0693d363 | 459 | |
ce51bde6 | 460 | /* find the next cache entry to use */ |
0693d363 | 461 | |
ce51bde6 DE |
462 | idx = cpu.cache_top + 1; |
463 | cpu.compiles++; | |
464 | if (idx >= cpu.csize) | |
465 | { | |
466 | idx = 1; | |
467 | } | |
468 | cpu.cache_top = idx; | |
0693d363 | 469 | |
ce51bde6 DE |
470 | /* Throw away its old meaning */ |
471 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; | |
0693d363 | 472 | |
ce51bde6 DE |
473 | /* set to new address */ |
474 | cpu.cache[idx].oldpc = pc; | |
0693d363 | 475 | |
ce51bde6 DE |
476 | /* fill in instruction info */ |
477 | decode (pc, cpu.memory + pc, cpu.cache + idx); | |
0693d363 | 478 | |
ce51bde6 DE |
479 | /* point to new cache entry */ |
480 | cpu.cache_idx[pc] = idx; | |
481 | } | |
482 | ||
483 | ||
484 | static unsigned char *breg[18]; | |
485 | static unsigned short *wreg[18]; | |
486 | static unsigned int *lreg[18]; | |
487 | ||
488 | #define GET_B_REG(x) *(breg[x]) | |
489 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
490 | #define GET_W_REG(x) *(wreg[x]) | |
491 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
492 | ||
493 | #define GET_L_REG(x) *(lreg[x]) | |
494 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
495 | ||
496 | #define GET_MEMORY_L(x) \ | |
497 | ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) | |
498 | ||
499 | #define GET_MEMORY_W(x) \ | |
500 | ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) | |
501 | ||
502 | ||
503 | #define SET_MEMORY_B(x,y) \ | |
504 | (cpu.memory[(x)] = y) | |
505 | ||
506 | #define SET_MEMORY_W(x,y) \ | |
507 | {register unsigned char *_p = cpu.memory+x;\ | |
508 | register int __y = y;\ | |
509 | _p[0] = (__y)>>8;\ | |
510 | _p[1] =(__y); } | |
511 | ||
512 | #define SET_MEMORY_L(x,y) \ | |
513 | {register unsigned char *_p = cpu.memory+x;register int __y = y;\ | |
514 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
515 | ||
516 | #define GET_MEMORY_B(x) (cpu.memory[x]) | |
517 | ||
518 | int | |
89a2c4fd | 519 | fetch (arg, n) |
0693d363 | 520 | ea_type *arg; |
ce51bde6 DE |
521 | { |
522 | int rn = arg->reg; | |
523 | int abs = arg->literal; | |
524 | int r; | |
525 | int t; | |
0693d363 | 526 | |
ce51bde6 DE |
527 | switch (arg->type) |
528 | { | |
529 | case X (OP_REG, SB): | |
530 | return GET_B_REG (rn); | |
531 | case X (OP_REG, SW): | |
532 | return GET_W_REG (rn); | |
533 | case X (OP_REG, SL): | |
534 | return GET_L_REG (rn); | |
535 | case X (OP_IMM, SB): | |
536 | case X (OP_IMM, SW): | |
537 | case X (OP_IMM, SL): | |
538 | return abs; | |
539 | case X (OP_DEC, SB): | |
0693d363 | 540 | abort (); |
ce51bde6 | 541 | |
0693d363 DE |
542 | case X (OP_INC, SB): |
543 | t = GET_L_REG (rn); | |
ce51bde6 | 544 | t &= cpu.mask; |
0693d363 DE |
545 | r = GET_MEMORY_B (t); |
546 | t++; | |
ce51bde6 | 547 | t = t & cpu.mask; |
0693d363 | 548 | SET_L_REG (rn, t); |
ce51bde6 DE |
549 | return r; |
550 | break; | |
0693d363 DE |
551 | case X (OP_INC, SW): |
552 | t = GET_L_REG (rn); | |
ce51bde6 | 553 | t &= cpu.mask; |
0693d363 DE |
554 | r = GET_MEMORY_W (t); |
555 | t += 2; | |
ce51bde6 | 556 | t = t & cpu.mask; |
0693d363 | 557 | SET_L_REG (rn, t); |
ce51bde6 | 558 | return r; |
0693d363 DE |
559 | case X (OP_INC, SL): |
560 | t = GET_L_REG (rn); | |
ce51bde6 | 561 | t &= cpu.mask; |
0693d363 DE |
562 | r = GET_MEMORY_L (t); |
563 | ||
564 | t += 4; | |
ce51bde6 | 565 | t = t & cpu.mask; |
0693d363 | 566 | SET_L_REG (rn, t); |
ce51bde6 | 567 | return r; |
0693d363 | 568 | |
ce51bde6 DE |
569 | case X (OP_DISP, SB): |
570 | t = GET_L_REG (rn) + abs; | |
571 | t &= cpu.mask; | |
572 | return GET_MEMORY_B (t); | |
0693d363 | 573 | |
ce51bde6 DE |
574 | case X (OP_DISP, SW): |
575 | t = GET_L_REG (rn) + abs; | |
576 | t &= cpu.mask; | |
577 | return GET_MEMORY_W (t); | |
0693d363 | 578 | |
ce51bde6 DE |
579 | case X (OP_DISP, SL): |
580 | t = GET_L_REG (rn) + abs; | |
581 | t &= cpu.mask; | |
582 | return GET_MEMORY_L (t); | |
0693d363 DE |
583 | |
584 | case X (OP_MEM, SL): | |
585 | t = GET_MEMORY_L (abs); | |
586 | t &= cpu.mask; | |
587 | return t; | |
588 | ||
e24146ec JL |
589 | case X (OP_MEM, SW): |
590 | t = GET_MEMORY_W (abs); | |
591 | t &= cpu.mask; | |
592 | return t; | |
593 | ||
ce51bde6 DE |
594 | default: |
595 | abort (); | |
0693d363 | 596 | |
ce51bde6 DE |
597 | } |
598 | } | |
599 | ||
600 | ||
0693d363 DE |
601 | static |
602 | void | |
603 | store (arg, n) | |
604 | ea_type *arg; | |
605 | int n; | |
ce51bde6 DE |
606 | { |
607 | int rn = arg->reg; | |
608 | int abs = arg->literal; | |
609 | int t; | |
0693d363 | 610 | |
ce51bde6 DE |
611 | switch (arg->type) |
612 | { | |
613 | case X (OP_REG, SB): | |
614 | SET_B_REG (rn, n); | |
615 | break; | |
616 | case X (OP_REG, SW): | |
617 | SET_W_REG (rn, n); | |
618 | break; | |
619 | case X (OP_REG, SL): | |
620 | SET_L_REG (rn, n); | |
621 | break; | |
0693d363 | 622 | |
ce51bde6 | 623 | case X (OP_DEC, SB): |
0693d363 | 624 | t = GET_L_REG (rn) - 1; |
ce51bde6 | 625 | t &= cpu.mask; |
0693d363 | 626 | SET_L_REG (rn, t); |
ce51bde6 DE |
627 | SET_MEMORY_B (t, n); |
628 | ||
629 | break; | |
630 | case X (OP_DEC, SW): | |
0693d363 | 631 | t = (GET_L_REG (rn) - 2) & cpu.mask; |
ce51bde6 DE |
632 | SET_L_REG (rn, t); |
633 | SET_MEMORY_W (t, n); | |
634 | break; | |
635 | ||
636 | case X (OP_DEC, SL): | |
0693d363 | 637 | t = (GET_L_REG (rn) - 4) & cpu.mask; |
89a2c4fd | 638 | SET_L_REG (rn, t); |
0693d363 | 639 | SET_MEMORY_L (t, n); |
ce51bde6 DE |
640 | break; |
641 | ||
ce51bde6 DE |
642 | case X (OP_DISP, SB): |
643 | t = GET_L_REG (rn) + abs; | |
644 | t &= cpu.mask; | |
645 | SET_MEMORY_B (t, n); | |
646 | break; | |
647 | ||
648 | case X (OP_DISP, SW): | |
649 | t = GET_L_REG (rn) + abs; | |
650 | t &= cpu.mask; | |
651 | SET_MEMORY_W (t, n); | |
652 | break; | |
653 | ||
654 | case X (OP_DISP, SL): | |
655 | t = GET_L_REG (rn) + abs; | |
656 | t &= cpu.mask; | |
657 | SET_MEMORY_L (t, n); | |
658 | break; | |
659 | default: | |
660 | abort (); | |
661 | } | |
662 | } | |
663 | ||
664 | ||
665 | static union | |
0693d363 DE |
666 | { |
667 | short int i; | |
668 | struct | |
669 | { | |
670 | char low; | |
671 | char high; | |
672 | } | |
673 | u; | |
674 | } | |
ce51bde6 DE |
675 | |
676 | littleendian; | |
677 | ||
678 | static | |
679 | void | |
680 | init_pointers () | |
681 | { | |
682 | static int init; | |
683 | ||
684 | if (!init) | |
685 | { | |
686 | int i; | |
687 | ||
688 | init = 1; | |
689 | littleendian.i = 1; | |
690 | ||
e656ecf9 DE |
691 | if (h8300hmode) |
692 | memory_size = H8300H_MSIZE; | |
693 | else | |
694 | memory_size = H8300_MSIZE; | |
695 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
696 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
697 | ||
698 | /* `msize' must be a power of two */ | |
699 | if ((memory_size & (memory_size - 1)) != 0) | |
700 | abort (); | |
701 | cpu.mask = memory_size - 1; | |
0693d363 | 702 | |
ce51bde6 DE |
703 | for (i = 0; i < 9; i++) |
704 | { | |
705 | cpu.regs[i] = 0; | |
706 | } | |
707 | ||
708 | for (i = 0; i < 8; i++) | |
709 | { | |
710 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
711 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
712 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
713 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
714 | cpu.regs[i] = 0x00112233; | |
715 | while (p < e) | |
716 | { | |
717 | if (*p == 0x22) | |
718 | { | |
719 | breg[i] = p; | |
720 | } | |
721 | if (*p == 0x33) | |
722 | { | |
0693d363 | 723 | breg[i + 8] = p; |
ce51bde6 DE |
724 | } |
725 | p++; | |
726 | } | |
727 | while (q < u) | |
728 | { | |
729 | if (*q == 0x2233) | |
730 | { | |
731 | wreg[i] = q; | |
732 | } | |
733 | if (*q == 0x0011) | |
734 | { | |
735 | wreg[i + 8] = q; | |
736 | } | |
737 | q++; | |
738 | } | |
739 | cpu.regs[i] = 0; | |
740 | lreg[i] = &cpu.regs[i]; | |
741 | } | |
742 | ||
ce51bde6 | 743 | lreg[8] = &cpu.regs[8]; |
0693d363 | 744 | |
ce51bde6 DE |
745 | /* initialize the seg registers */ |
746 | if (!cpu.cache) | |
747 | sim_csize (CSIZE); | |
ce51bde6 DE |
748 | } |
749 | } | |
750 | ||
751 | static void | |
752 | control_c (sig, code, scp, addr) | |
753 | int sig; | |
754 | int code; | |
755 | char *scp; | |
756 | char *addr; | |
757 | { | |
758 | cpu.exception = SIGINT; | |
759 | } | |
760 | ||
761 | #define C (c != 0) | |
762 | #define Z (nz == 0) | |
763 | #define V (v != 0) | |
764 | #define N (n != 0) | |
765 | ||
28655f00 | 766 | static int |
0693d363 | 767 | mop (code, bsize, sign) |
28655f00 SC |
768 | decoded_inst *code; |
769 | int bsize; | |
0693d363 DE |
770 | int sign; |
771 | { | |
772 | int multiplier; | |
773 | int multiplicand; | |
774 | int result; | |
775 | int n, nz; | |
776 | ||
777 | if (sign) | |
778 | { | |
779 | multiplicand = | |
780 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
781 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
782 | multiplier = | |
783 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
784 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
785 | } | |
786 | else | |
787 | { | |
788 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
789 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
790 | multiplier = | |
791 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
792 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
793 | ||
794 | } | |
795 | result = multiplier * multiplicand; | |
796 | ||
797 | if (sign) | |
798 | { | |
799 | n = result & (bsize ? 0x8000 : 0x80000000); | |
800 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
801 | } | |
802 | if (bsize) | |
803 | { | |
804 | SET_W_REG (code->dst.reg, result); | |
805 | } | |
806 | else | |
807 | { | |
808 | SET_L_REG (code->dst.reg, result); | |
809 | } | |
810 | /* return ((n==1) << 1) | (nz==1); */ | |
811 | ||
812 | } | |
813 | ||
814 | #define OSHIFTS(name, how) \ | |
815 | case O(name, SB): \ | |
816 | { \ | |
817 | int t; \ | |
818 | int hm = 0x80; \ | |
819 | rd = GET_B_REG (code->src.reg); \ | |
820 | how; \ | |
821 | goto shift8; \ | |
822 | } \ | |
823 | case O(name, SW): \ | |
824 | { \ | |
825 | int t; \ | |
826 | int hm = 0x8000; \ | |
827 | rd = GET_W_REG (code->src.reg); \ | |
828 | how; \ | |
829 | goto shift16; \ | |
830 | } \ | |
831 | case O(name, SL): \ | |
832 | { \ | |
833 | int t; \ | |
834 | int hm = 0x80000000; \ | |
835 | rd = GET_L_REG (code->src.reg); \ | |
836 | how; \ | |
837 | goto shift32; \ | |
838 | } | |
839 | ||
840 | #define OBITOP(name,f, s, op) \ | |
841 | case O(name, SB): \ | |
842 | { \ | |
843 | int m; \ | |
844 | int b; \ | |
845 | if (f) ea = fetch (&code->dst); \ | |
846 | m=1<< fetch(&code->src); \ | |
847 | op; \ | |
848 | if(s) store (&code->dst,ea); goto next; \ | |
849 | } | |
28655f00 | 850 | |
7478904c | 851 | void |
a415cf0a | 852 | sim_resume (step, siggnal) |
ce51bde6 DE |
853 | { |
854 | static int init1; | |
855 | int cycles = 0; | |
856 | int insts = 0; | |
857 | int tick_start = get_now (); | |
858 | void (*prev) (); | |
0693d363 | 859 | int poll_count = 0; |
ce51bde6 DE |
860 | int res; |
861 | int tmp; | |
862 | int rd; | |
863 | int ea; | |
864 | int bit; | |
865 | int pc; | |
866 | int c, nz, v, n; | |
7478904c | 867 | int oldmask; |
ce51bde6 DE |
868 | init_pointers (); |
869 | ||
870 | prev = signal (SIGINT, control_c); | |
871 | ||
872 | if (step) | |
873 | { | |
874 | cpu.exception = SIGTRAP; | |
875 | } | |
876 | else | |
877 | { | |
878 | cpu.exception = 0; | |
879 | } | |
880 | ||
881 | pc = cpu.pc; | |
882 | ||
883 | GETSR (); | |
7478904c SC |
884 | oldmask = cpu.mask; |
885 | if (!h8300hmode) | |
886 | cpu.mask = 0xffff; | |
ce51bde6 DE |
887 | do |
888 | { | |
889 | int cidx; | |
890 | decoded_inst *code; | |
891 | ||
892 | top: | |
893 | cidx = cpu.cache_idx[pc]; | |
894 | code = cpu.cache + cidx; | |
895 | ||
896 | ||
897 | #define ALUOP(STORE, NAME, HOW) \ | |
898 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
899 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
900 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
901 | ||
902 | ||
903 | #define LOGOP(NAME, HOW) \ | |
904 | case O(NAME,SB): HOW; goto log8;\ | |
905 | case O(NAME, SW): HOW; goto log16;\ | |
906 | case O(NAME,SL): HOW; goto log32; | |
907 | ||
908 | ||
909 | ||
910 | #if ADEBUG | |
911 | if (debug) | |
912 | { | |
913 | printf ("%x %d %s\n", pc, code->opcode, | |
914 | code->op ? code->op->name : "**"); | |
915 | } | |
916 | cpu.stats[code->opcode]++; | |
0693d363 | 917 | |
ce51bde6 DE |
918 | #endif |
919 | ||
920 | cycles += code->cycles; | |
921 | insts++; | |
922 | switch (code->opcode) | |
923 | { | |
924 | case 0: | |
925 | /* | |
926 | * This opcode is a fake for when we get to an | |
927 | * instruction which hasnt been compiled | |
928 | */ | |
929 | compile (pc); | |
930 | goto top; | |
931 | break; | |
932 | ||
933 | ||
934 | case O (O_SUBX, SB): | |
935 | rd = fetch (&code->dst); | |
936 | ea = fetch (&code->src); | |
0693d363 | 937 | ea = -(ea + C); |
ce51bde6 DE |
938 | res = rd + ea; |
939 | goto alu8; | |
940 | ||
941 | case O (O_ADDX, SB): | |
942 | rd = fetch (&code->dst); | |
943 | ea = fetch (&code->src); | |
944 | ea = C + ea; | |
945 | res = rd + ea; | |
946 | goto alu8; | |
947 | ||
cf5b4aa6 DE |
948 | #define EA ea = fetch(&code->src); |
949 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
ce51bde6 | 950 | |
0693d363 DE |
951 | ALUOP (1, O_SUB, RD_EA; |
952 | ea = -ea; | |
953 | res = rd + ea); | |
954 | ALUOP (1, O_NEG, EA; | |
955 | ea = -ea; | |
956 | rd = 0; | |
957 | res = rd + ea); | |
ce51bde6 | 958 | |
0693d363 DE |
959 | case O (O_ADD, SB): |
960 | rd = GET_B_REG (code->dst.reg); | |
961 | ea = fetch (&code->src); | |
ce51bde6 DE |
962 | res = rd + ea; |
963 | goto alu8; | |
0693d363 DE |
964 | case O (O_ADD, SW): |
965 | rd = GET_W_REG (code->dst.reg); | |
966 | ea = fetch (&code->src); | |
ce51bde6 DE |
967 | res = rd + ea; |
968 | goto alu16; | |
0693d363 DE |
969 | case O (O_ADD, SL): |
970 | rd = GET_L_REG (code->dst.reg); | |
971 | ea = fetch (&code->src); | |
ce51bde6 DE |
972 | res = rd + ea; |
973 | goto alu32; | |
ce51bde6 | 974 | |
ce51bde6 | 975 | |
0693d363 DE |
976 | LOGOP (O_AND, RD_EA; |
977 | res = rd & ea); | |
978 | ||
979 | LOGOP (O_OR, RD_EA; | |
980 | res = rd | ea); | |
ce51bde6 | 981 | |
0693d363 DE |
982 | LOGOP (O_XOR, RD_EA; |
983 | res = rd ^ ea); | |
ce51bde6 DE |
984 | |
985 | ||
0693d363 DE |
986 | case O (O_MOV_TO_MEM, SB): |
987 | res = GET_B_REG (code->src.reg); | |
ce51bde6 | 988 | goto log8; |
0693d363 DE |
989 | case O (O_MOV_TO_MEM, SW): |
990 | res = GET_W_REG (code->src.reg); | |
ce51bde6 | 991 | goto log16; |
0693d363 DE |
992 | case O (O_MOV_TO_MEM, SL): |
993 | res = GET_L_REG (code->src.reg); | |
ce51bde6 DE |
994 | goto log32; |
995 | ||
996 | ||
0693d363 DE |
997 | case O (O_MOV_TO_REG, SB): |
998 | res = fetch (&code->src); | |
999 | SET_B_REG (code->dst.reg, res); | |
ce51bde6 | 1000 | goto just_flags_log8; |
0693d363 DE |
1001 | case O (O_MOV_TO_REG, SW): |
1002 | res = fetch (&code->src); | |
1003 | SET_W_REG (code->dst.reg, res); | |
ce51bde6 | 1004 | goto just_flags_log16; |
0693d363 DE |
1005 | case O (O_MOV_TO_REG, SL): |
1006 | res = fetch (&code->src); | |
1007 | SET_L_REG (code->dst.reg, res); | |
ce51bde6 DE |
1008 | goto just_flags_log32; |
1009 | ||
1010 | ||
0693d363 DE |
1011 | case O (O_ADDS, SL): |
1012 | SET_L_REG (code->dst.reg, | |
1013 | GET_L_REG (code->dst.reg) | |
1014 | + code->src.literal); | |
1015 | ||
ce51bde6 DE |
1016 | goto next; |
1017 | ||
0693d363 DE |
1018 | case O (O_SUBS, SL): |
1019 | SET_L_REG (code->dst.reg, | |
1020 | GET_L_REG (code->dst.reg) | |
1021 | - code->src.literal); | |
ce51bde6 | 1022 | goto next; |
0693d363 | 1023 | |
ce51bde6 DE |
1024 | case O (O_CMP, SB): |
1025 | rd = fetch (&code->dst); | |
1026 | ea = fetch (&code->src); | |
1027 | ea = -ea; | |
1028 | res = rd + ea; | |
1029 | goto just_flags_alu8; | |
1030 | ||
1031 | case O (O_CMP, SW): | |
1032 | rd = fetch (&code->dst); | |
1033 | ea = fetch (&code->src); | |
1034 | ea = -ea; | |
1035 | res = rd + ea; | |
1036 | goto just_flags_alu16; | |
1037 | ||
1038 | case O (O_CMP, SL): | |
1039 | rd = fetch (&code->dst); | |
1040 | ea = fetch (&code->src); | |
1041 | ea = -ea; | |
1042 | res = rd + ea; | |
1043 | goto just_flags_alu32; | |
1044 | ||
1045 | ||
1046 | case O (O_DEC, SB): | |
1047 | rd = GET_B_REG (code->src.reg); | |
1048 | ea = -1; | |
1049 | res = rd + ea; | |
1050 | SET_B_REG (code->src.reg, res); | |
1051 | goto just_flags_inc8; | |
1052 | ||
1053 | case O (O_DEC, SW): | |
1054 | rd = GET_W_REG (code->dst.reg); | |
0693d363 | 1055 | ea = -code->src.literal; |
ce51bde6 DE |
1056 | res = rd + ea; |
1057 | SET_W_REG (code->dst.reg, res); | |
1058 | goto just_flags_inc16; | |
1059 | ||
1060 | case O (O_DEC, SL): | |
1061 | rd = GET_L_REG (code->dst.reg); | |
1062 | ea = -code->src.literal; | |
1063 | res = rd + ea; | |
1064 | SET_L_REG (code->dst.reg, res); | |
1065 | goto just_flags_inc32; | |
1066 | ||
1067 | ||
1068 | case O (O_INC, SB): | |
1069 | rd = GET_B_REG (code->src.reg); | |
1070 | ea = 1; | |
1071 | res = rd + ea; | |
1072 | SET_B_REG (code->src.reg, res); | |
1073 | goto just_flags_inc8; | |
1074 | ||
1075 | case O (O_INC, SW): | |
1076 | rd = GET_W_REG (code->dst.reg); | |
1077 | ea = code->src.literal; | |
1078 | res = rd + ea; | |
1079 | SET_W_REG (code->dst.reg, res); | |
1080 | goto just_flags_inc16; | |
1081 | ||
1082 | case O (O_INC, SL): | |
1083 | rd = GET_L_REG (code->dst.reg); | |
1084 | ea = code->src.literal; | |
1085 | res = rd + ea; | |
1086 | SET_L_REG (code->dst.reg, res); | |
1087 | goto just_flags_inc32; | |
1088 | ||
1089 | ||
1090 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
0693d363 | 1091 | |
ce51bde6 DE |
1092 | case O (O_ANDC, SB): |
1093 | GET_CCR (rd); | |
1094 | ea = code->src.literal; | |
1095 | res = rd & ea; | |
1096 | goto setc; | |
1097 | ||
0693d363 DE |
1098 | case O (O_ORC, SB): |
1099 | GET_CCR (rd); | |
1100 | ea = code->src.literal; | |
1101 | res = rd | ea; | |
1102 | goto setc; | |
1103 | ||
1104 | case O (O_XORC, SB): | |
1105 | GET_CCR (rd); | |
1106 | ea = code->src.literal; | |
1107 | res = rd ^ ea; | |
1108 | goto setc; | |
1109 | ||
ce51bde6 DE |
1110 | |
1111 | case O (O_BRA, SB): | |
1112 | if (1) | |
1113 | goto condtrue; | |
1114 | goto next; | |
1115 | ||
1116 | case O (O_BRN, SB): | |
1117 | if (0) | |
1118 | goto condtrue; | |
1119 | goto next; | |
1120 | ||
1121 | case O (O_BHI, SB): | |
1122 | if ((C || Z) == 0) | |
1123 | goto condtrue; | |
1124 | goto next; | |
1125 | ||
1126 | ||
1127 | case O (O_BLS, SB): | |
1128 | if ((C || Z)) | |
1129 | goto condtrue; | |
1130 | goto next; | |
1131 | ||
1132 | case O (O_BCS, SB): | |
1133 | if ((C == 1)) | |
1134 | goto condtrue; | |
1135 | goto next; | |
1136 | ||
1137 | case O (O_BCC, SB): | |
1138 | if ((C == 0)) | |
1139 | goto condtrue; | |
1140 | goto next; | |
1141 | ||
1142 | case O (O_BEQ, SB): | |
1143 | if (Z) | |
1144 | goto condtrue; | |
1145 | goto next; | |
1146 | case O (O_BGT, SB): | |
1147 | if (((Z || (N ^ V)) == 0)) | |
1148 | goto condtrue; | |
1149 | goto next; | |
1150 | ||
1151 | ||
1152 | case O (O_BLE, SB): | |
1153 | if (((Z || (N ^ V)) == 1)) | |
1154 | goto condtrue; | |
1155 | goto next; | |
1156 | ||
1157 | case O (O_BGE, SB): | |
1158 | if ((N ^ V) == 0) | |
1159 | goto condtrue; | |
1160 | goto next; | |
1161 | case O (O_BLT, SB): | |
1162 | if ((N ^ V)) | |
1163 | goto condtrue; | |
1164 | goto next; | |
1165 | case O (O_BMI, SB): | |
1166 | if ((N)) | |
1167 | goto condtrue; | |
1168 | goto next; | |
1169 | case O (O_BNE, SB): | |
1170 | if ((Z == 0)) | |
1171 | goto condtrue; | |
1172 | goto next; | |
1173 | ||
1174 | case O (O_BPL, SB): | |
1175 | if (N == 0) | |
1176 | goto condtrue; | |
1177 | goto next; | |
1178 | case O (O_BVC, SB): | |
1179 | if ((V == 0)) | |
1180 | goto condtrue; | |
1181 | goto next; | |
1182 | case O (O_BVS, SB): | |
1183 | if ((V == 1)) | |
1184 | goto condtrue; | |
1185 | goto next; | |
1186 | ||
0693d363 DE |
1187 | case O (O_SYSCALL, SB): |
1188 | printf ("%c", cpu.regs[2]); | |
ce51bde6 | 1189 | goto next; |
ce51bde6 | 1190 | |
5d06fa80 DE |
1191 | OSHIFTS (O_NOT, rd = ~rd; v = 0;); |
1192 | OSHIFTS (O_SHLL, c = rd & hm; v = 0; | |
0693d363 | 1193 | rd <<= 1); |
5d06fa80 | 1194 | OSHIFTS (O_SHLR, c = rd & 1; v = 0; |
0693d363 DE |
1195 | rd = (unsigned int) rd >> 1); |
1196 | OSHIFTS (O_SHAL, c = rd & hm; | |
5d06fa80 | 1197 | v = (rd & hm) != ((rd & (hm >> 1)) << 1); |
0693d363 DE |
1198 | rd <<= 1); |
1199 | OSHIFTS (O_SHAR, t = rd & hm; | |
1200 | c = rd & 1; | |
5d06fa80 | 1201 | v = 0; |
0693d363 DE |
1202 | rd >>= 1; |
1203 | rd |= t; | |
7478904c | 1204 | ); |
0693d363 | 1205 | OSHIFTS (O_ROTL, c = rd & hm; |
5d06fa80 | 1206 | v = 0; |
0693d363 DE |
1207 | rd <<= 1; |
1208 | rd |= C); | |
1209 | OSHIFTS (O_ROTR, c = rd & 1; | |
5d06fa80 | 1210 | v = 0; |
0693d363 DE |
1211 | rd = (unsigned int) rd >> 1; |
1212 | if (c) rd |= hm;); | |
1213 | OSHIFTS (O_ROTXL, t = rd & hm; | |
1214 | rd <<= 1; | |
1215 | rd |= C; | |
1216 | c = t; | |
5d06fa80 | 1217 | v = 0; |
7478904c | 1218 | ); |
0693d363 DE |
1219 | OSHIFTS (O_ROTXR, t = rd & 1; |
1220 | rd = (unsigned int) rd >> 1; | |
5d06fa80 DE |
1221 | if (C) rd |= hm; c = t; |
1222 | v = 0;); | |
0693d363 DE |
1223 | |
1224 | case O (O_JMP, SB): | |
ce51bde6 DE |
1225 | { |
1226 | pc = fetch (&code->src); | |
1227 | goto end; | |
0693d363 | 1228 | |
ce51bde6 | 1229 | } |
0693d363 | 1230 | |
ce51bde6 DE |
1231 | case O (O_JSR, SB): |
1232 | { | |
1233 | int tmp; | |
1234 | pc = fetch (&code->src); | |
1235 | call: | |
1236 | tmp = cpu.regs[7]; | |
1237 | ||
28655f00 | 1238 | if (h8300hmode) |
ce51bde6 DE |
1239 | { |
1240 | tmp -= 4; | |
1241 | SET_MEMORY_L (tmp, code->next_pc); | |
1242 | } | |
1243 | else | |
1244 | { | |
1245 | tmp -= 2; | |
1246 | SET_MEMORY_W (tmp, code->next_pc); | |
1247 | } | |
1248 | cpu.regs[7] = tmp; | |
1249 | ||
1250 | goto end; | |
1251 | } | |
0693d363 | 1252 | case O (O_BSR, SB): |
ce51bde6 DE |
1253 | pc = code->src.literal; |
1254 | goto call; | |
0693d363 | 1255 | |
ce51bde6 DE |
1256 | case O (O_RTS, SB): |
1257 | { | |
1258 | int tmp; | |
1259 | ||
ce51bde6 DE |
1260 | tmp = cpu.regs[7]; |
1261 | ||
28655f00 | 1262 | if (h8300hmode) |
ce51bde6 DE |
1263 | { |
1264 | pc = GET_MEMORY_L (tmp); | |
1265 | tmp += 4; | |
ce51bde6 DE |
1266 | } |
1267 | else | |
1268 | { | |
1269 | pc = GET_MEMORY_W (tmp); | |
1270 | tmp += 2; | |
1271 | } | |
1272 | ||
1273 | cpu.regs[7] = tmp; | |
1274 | goto end; | |
1275 | } | |
1276 | ||
1277 | case O (O_ILL, SB): | |
1278 | cpu.exception = SIGILL; | |
1279 | goto end; | |
0693d363 | 1280 | case O (O_SLEEP, SB): |
4dfb4ffc DE |
1281 | /* The format of r0 is defined by devo/include/wait.h. |
1282 | cpu.exception handling needs some cleanup: we need to make the | |
1283 | the handling of normal exits vs signals, etc. more sensible. */ | |
1284 | if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) | |
e656ecf9 DE |
1285 | cpu.exception = SIGILL; |
1286 | else | |
1287 | cpu.exception = SIGTRAP; | |
1288 | goto end; | |
0693d363 | 1289 | case O (O_BPT, SB): |
ce51bde6 DE |
1290 | cpu.exception = SIGTRAP; |
1291 | goto end; | |
1292 | ||
0693d363 DE |
1293 | OBITOP (O_BNOT, 1, 1, ea ^= m); |
1294 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1295 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1296 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1297 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1298 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1299 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1300 | if (C) ea |= m); | |
1301 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1302 | if (!C) ea |= m); | |
1303 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1304 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1305 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1306 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1307 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1308 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
ce51bde6 DE |
1309 | |
1310 | ||
28655f00 | 1311 | #define MOP(bsize, signed) mop(code, bsize,signed); goto next; |
ce51bde6 | 1312 | |
0693d363 DE |
1313 | case O (O_MULS, SB): |
1314 | MOP (1, 1); | |
1315 | break; | |
1316 | case O (O_MULS, SW): | |
1317 | MOP (0, 1); | |
1318 | break; | |
1319 | case O (O_MULU, SB): | |
1320 | MOP (1, 0); | |
1321 | break; | |
1322 | case O (O_MULU, SW): | |
1323 | MOP (0, 0); | |
1324 | break; | |
ce51bde6 | 1325 | |
ce51bde6 | 1326 | |
0693d363 DE |
1327 | case O (O_DIVU, SB): |
1328 | { | |
1329 | rd = GET_W_REG (code->dst.reg); | |
1330 | ea = GET_B_REG (code->src.reg); | |
1331 | if (ea) | |
1332 | { | |
1333 | tmp = rd % ea; | |
1334 | rd = rd / ea; | |
1335 | } | |
1336 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1337 | n = ea & 0x80; | |
1338 | nz = ea & 0xff; | |
ce51bde6 | 1339 | |
0693d363 DE |
1340 | goto next; |
1341 | } | |
1342 | case O (O_DIVU, SW): | |
1343 | { | |
1344 | rd = GET_L_REG (code->dst.reg); | |
1345 | ea = GET_W_REG (code->src.reg); | |
1346 | n = ea & 0x8000; | |
1347 | nz = ea & 0xffff; | |
1348 | if (ea) | |
1349 | { | |
1350 | tmp = rd % ea; | |
1351 | rd = rd / ea; | |
1352 | } | |
1353 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1354 | goto next; | |
1355 | } | |
ce51bde6 | 1356 | |
0693d363 DE |
1357 | case O (O_DIVS, SB): |
1358 | { | |
ce51bde6 | 1359 | |
0693d363 DE |
1360 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); |
1361 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1362 | if (ea) | |
1363 | { | |
1364 | tmp = (int) rd % (int) ea; | |
1365 | rd = (int) rd / (int) ea; | |
1366 | n = rd & 0x8000; | |
1367 | nz = 1; | |
1368 | } | |
1369 | else | |
1370 | nz = 0; | |
1371 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1372 | goto next; | |
1373 | } | |
1374 | case O (O_DIVS, SW): | |
1375 | { | |
1376 | rd = GET_L_REG (code->dst.reg); | |
1377 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1378 | if (ea) | |
1379 | { | |
1380 | tmp = (int) rd % (int) ea; | |
1381 | rd = (int) rd / (int) ea; | |
1382 | n = rd & 0x80000000; | |
1383 | nz = 1; | |
1384 | } | |
1385 | else | |
1386 | nz = 0; | |
1387 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1388 | goto next; | |
1389 | } | |
1390 | case O (O_EXTS, SW): | |
7478904c | 1391 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ |
0693d363 DE |
1392 | ea = rd & 0x80 ? -256 : 0; |
1393 | res = rd + ea; | |
1394 | goto log16; | |
1395 | case O (O_EXTS, SL): | |
1396 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1397 | ea = rd & 0x8000 ? -65536 : 0; | |
1398 | res = rd + ea; | |
1399 | goto log32; | |
1400 | case O (O_EXTU, SW): | |
1401 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1402 | ea = 0; | |
1403 | res = rd + ea; | |
1404 | goto log16; | |
1405 | case O (O_EXTU, SL): | |
1406 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1407 | ea = 0; | |
1408 | res = rd + ea; | |
1409 | goto log32; | |
ce51bde6 | 1410 | |
0693d363 DE |
1411 | case O (O_NOP, SB): |
1412 | goto next; | |
ce51bde6 | 1413 | |
0693d363 | 1414 | default: |
7478904c | 1415 | cpu.exception = SIGILL; |
0693d363 | 1416 | goto end; |
ce51bde6 DE |
1417 | |
1418 | } | |
0693d363 DE |
1419 | abort (); |
1420 | ||
1421 | setc: | |
1422 | cpu.ccr = res; | |
1423 | GETSR (); | |
28655f00 SC |
1424 | goto next; |
1425 | ||
0693d363 DE |
1426 | condtrue: |
1427 | /* When a branch works */ | |
1428 | pc = code->src.literal; | |
ce51bde6 DE |
1429 | goto end; |
1430 | ||
0693d363 DE |
1431 | /* Set the cond codes from res */ |
1432 | bitop: | |
ce51bde6 | 1433 | |
0693d363 DE |
1434 | /* Set the flags after an 8 bit inc/dec operation */ |
1435 | just_flags_inc8: | |
1436 | n = res & 0x80; | |
1437 | nz = res & 0xff; | |
1438 | v = (rd & 0x7f) == 0x7f; | |
1439 | goto next; | |
ce51bde6 | 1440 | |
ce51bde6 | 1441 | |
0693d363 DE |
1442 | /* Set the flags after an 16 bit inc/dec operation */ |
1443 | just_flags_inc16: | |
1444 | n = res & 0x8000; | |
1445 | nz = res & 0xffff; | |
1446 | v = (rd & 0x7fff) == 0x7fff; | |
1447 | goto next; | |
1448 | ||
1449 | ||
1450 | /* Set the flags after an 32 bit inc/dec operation */ | |
1451 | just_flags_inc32: | |
1452 | n = res & 0x80000000; | |
1453 | nz = res & 0xffffffff; | |
1454 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1455 | goto next; | |
1456 | ||
1457 | ||
1458 | shift8: | |
5d06fa80 | 1459 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ |
0693d363 | 1460 | n = (rd & 0x80); |
0693d363 DE |
1461 | nz = rd & 0xff; |
1462 | SET_B_REG (code->src.reg, rd); | |
1463 | goto next; | |
1464 | ||
0693d363 | 1465 | shift16: |
5d06fa80 | 1466 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ |
0693d363 | 1467 | n = (rd & 0x8000); |
0693d363 | 1468 | nz = rd & 0xffff; |
0693d363 DE |
1469 | SET_W_REG (code->src.reg, rd); |
1470 | goto next; | |
1471 | ||
1472 | shift32: | |
5d06fa80 | 1473 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ |
0693d363 | 1474 | n = (rd & 0x80000000); |
0693d363 DE |
1475 | nz = rd & 0xffffffff; |
1476 | SET_L_REG (code->src.reg, rd); | |
1477 | goto next; | |
1478 | ||
1479 | log32: | |
1480 | store (&code->dst, res); | |
1481 | just_flags_log32: | |
1482 | /* flags after a 32bit logical operation */ | |
1483 | n = res & 0x80000000; | |
1484 | nz = res & 0xffffffff; | |
1485 | v = 0; | |
1486 | goto next; | |
1487 | ||
1488 | log16: | |
1489 | store (&code->dst, res); | |
1490 | just_flags_log16: | |
1491 | /* flags after a 16bit logical operation */ | |
1492 | n = res & 0x8000; | |
1493 | nz = res & 0xffff; | |
1494 | v = 0; | |
1495 | goto next; | |
1496 | ||
1497 | ||
1498 | log8: | |
1499 | store (&code->dst, res); | |
1500 | just_flags_log8: | |
1501 | n = res & 0x80; | |
1502 | nz = res & 0xff; | |
1503 | v = 0; | |
1504 | goto next; | |
1505 | ||
1506 | alu8: | |
1507 | SET_B_REG (code->dst.reg, res); | |
1508 | just_flags_alu8: | |
1509 | n = res & 0x80; | |
1510 | nz = res & 0xff; | |
0693d363 | 1511 | c = (res & 0x100); |
50d45d1b JL |
1512 | switch (code->opcode / 4) |
1513 | { | |
1514 | case O_ADD: | |
1515 | v = ((rd & 0x80) == (ea & 0x80) | |
1516 | && (rd & 0x80) != (res & 0x80)); | |
1517 | break; | |
1518 | case O_SUB: | |
1519 | case O_CMP: | |
1520 | v = ((rd & 0x80) != (-ea & 0x80) | |
1521 | && (rd & 0x80) != (res & 0x80)); | |
1522 | break; | |
1523 | case O_NEG: | |
1524 | v = (rd == 0x80); | |
1525 | break; | |
1526 | } | |
0693d363 DE |
1527 | goto next; |
1528 | ||
1529 | alu16: | |
1530 | SET_W_REG (code->dst.reg, res); | |
1531 | just_flags_alu16: | |
1532 | n = res & 0x8000; | |
1533 | nz = res & 0xffff; | |
0693d363 | 1534 | c = (res & 0x10000); |
50d45d1b JL |
1535 | switch (code->opcode / 4) |
1536 | { | |
1537 | case O_ADD: | |
1538 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1539 | && (rd & 0x8000) != (res & 0x8000)); | |
1540 | break; | |
1541 | case O_SUB: | |
1542 | case O_CMP: | |
1543 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1544 | && (rd & 0x8000) != (res & 0x8000)); | |
1545 | break; | |
1546 | case O_NEG: | |
1547 | v = (rd == 0x8000); | |
1548 | break; | |
1549 | } | |
0693d363 DE |
1550 | goto next; |
1551 | ||
1552 | alu32: | |
1553 | SET_L_REG (code->dst.reg, res); | |
1554 | just_flags_alu32: | |
1555 | n = res & 0x80000000; | |
1556 | nz = res & 0xffffffff; | |
50d45d1b JL |
1557 | switch (code->opcode / 4) |
1558 | { | |
1559 | case O_ADD: | |
1560 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1561 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1562 | break; | |
1563 | case O_SUB: | |
1564 | case O_CMP: | |
1565 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1566 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1567 | break; | |
1568 | case O_NEG: | |
1569 | v = (rd == 0x80000000); | |
1570 | break; | |
1571 | } | |
1572 | goto next; | |
0693d363 DE |
1573 | switch (code->opcode / 4) |
1574 | { | |
1575 | case O_ADD: | |
1576 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1577 | break; | |
1578 | case O_SUB: | |
1579 | case O_CMP: | |
1580 | c = (unsigned) rd < (unsigned) -ea; | |
1581 | break; | |
1582 | case O_NEG: | |
1583 | c = res != 0; | |
1584 | break; | |
1585 | } | |
1586 | goto next; | |
1587 | ||
1588 | next:; | |
1589 | pc = code->next_pc; | |
1590 | ||
1591 | end: | |
1592 | ; | |
1593 | /* if (cpu.regs[8] ) abort(); */ | |
1594 | ||
7478904c SC |
1595 | #if defined (WIN32) |
1596 | /* Poll after every 100th insn, */ | |
1597 | if (poll_count++ > 100) | |
1598 | { | |
1599 | poll_count = 0; | |
1600 | if (win32pollquit()) | |
1601 | { | |
1602 | control_c(); | |
1603 | } | |
1604 | } | |
1605 | #endif | |
1606 | #if defined(__GO32__) | |
0693d363 DE |
1607 | /* Poll after every 100th insn, */ |
1608 | if (poll_count++ > 100) | |
1609 | { | |
1610 | poll_count = 0; | |
1611 | if (kbhit ()) | |
1612 | { | |
1613 | int c = getkey (); | |
1614 | control_c (); | |
1615 | } | |
1616 | } | |
1617 | #endif | |
1618 | ||
1619 | } | |
ce51bde6 DE |
1620 | while (!cpu.exception); |
1621 | cpu.ticks += get_now () - tick_start; | |
1622 | cpu.cycles += cycles; | |
1623 | cpu.insts += insts; | |
7478904c | 1624 | |
ce51bde6 DE |
1625 | cpu.pc = pc; |
1626 | BUILDSR (); | |
7478904c | 1627 | cpu.mask = oldmask; |
ce51bde6 DE |
1628 | signal (SIGINT, prev); |
1629 | } | |
1630 | ||
1631 | ||
28655f00 | 1632 | int |
ce51bde6 | 1633 | sim_write (addr, buffer, size) |
a415cf0a | 1634 | SIM_ADDR addr; |
ce51bde6 DE |
1635 | unsigned char *buffer; |
1636 | int size; | |
1637 | { | |
1638 | int i; | |
1639 | ||
1640 | init_pointers (); | |
e656ecf9 | 1641 | if (addr < 0 || addr + size > memory_size) |
a415cf0a | 1642 | return 0; |
ce51bde6 DE |
1643 | for (i = 0; i < size; i++) |
1644 | { | |
1645 | cpu.memory[addr + i] = buffer[i]; | |
1646 | cpu.cache_idx[addr + i] = 0; | |
1647 | } | |
a415cf0a | 1648 | return size; |
ce51bde6 DE |
1649 | } |
1650 | ||
28655f00 | 1651 | int |
ce51bde6 | 1652 | sim_read (addr, buffer, size) |
a415cf0a DE |
1653 | SIM_ADDR addr; |
1654 | unsigned char *buffer; | |
ce51bde6 DE |
1655 | int size; |
1656 | { | |
1657 | init_pointers (); | |
e656ecf9 | 1658 | if (addr < 0 || addr + size > memory_size) |
a415cf0a | 1659 | return 0; |
ce51bde6 | 1660 | memcpy (buffer, cpu.memory + addr, size); |
28655f00 | 1661 | return size; |
ce51bde6 DE |
1662 | } |
1663 | ||
1664 | ||
ce51bde6 DE |
1665 | #define R0_REGNUM 0 |
1666 | #define R1_REGNUM 1 | |
1667 | #define R2_REGNUM 2 | |
1668 | #define R3_REGNUM 3 | |
1669 | #define R4_REGNUM 4 | |
1670 | #define R5_REGNUM 5 | |
1671 | #define R6_REGNUM 6 | |
1672 | #define R7_REGNUM 7 | |
1673 | ||
1674 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1675 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
0693d363 | 1676 | * stack frame */ |
ce51bde6 DE |
1677 | |
1678 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1679 | #define PC_REGNUM 9 /* Contains program counter */ | |
1680 | ||
1681 | #define CYCLE_REGNUM 10 | |
1682 | #define INST_REGNUM 11 | |
1683 | #define TICK_REGNUM 12 | |
1684 | ||
1685 | ||
7478904c | 1686 | void |
ce51bde6 DE |
1687 | sim_store_register (rn, value) |
1688 | int rn; | |
28655f00 | 1689 | unsigned char *value; |
ce51bde6 | 1690 | { |
28655f00 SC |
1691 | int longval; |
1692 | int shortval; | |
1693 | int intval; | |
0693d363 DE |
1694 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; |
1695 | shortval = (value[0] << 8) | (value[1]); | |
28655f00 | 1696 | intval = h8300hmode ? longval : shortval; |
ce51bde6 DE |
1697 | |
1698 | init_pointers (); | |
1699 | switch (rn) | |
1700 | { | |
1701 | case PC_REGNUM: | |
28655f00 | 1702 | cpu.pc = intval; |
ce51bde6 DE |
1703 | break; |
1704 | default: | |
1705 | abort (); | |
1706 | case R0_REGNUM: | |
1707 | case R1_REGNUM: | |
1708 | case R2_REGNUM: | |
1709 | case R3_REGNUM: | |
1710 | case R4_REGNUM: | |
1711 | case R5_REGNUM: | |
1712 | case R6_REGNUM: | |
1713 | case R7_REGNUM: | |
28655f00 | 1714 | cpu.regs[rn] = intval; |
ce51bde6 DE |
1715 | break; |
1716 | case CCR_REGNUM: | |
28655f00 | 1717 | cpu.ccr = intval; |
ce51bde6 DE |
1718 | break; |
1719 | case CYCLE_REGNUM: | |
28655f00 | 1720 | cpu.cycles = longval; |
ce51bde6 DE |
1721 | break; |
1722 | ||
1723 | case INST_REGNUM: | |
28655f00 | 1724 | cpu.insts = longval; |
ce51bde6 DE |
1725 | break; |
1726 | ||
1727 | case TICK_REGNUM: | |
28655f00 | 1728 | cpu.ticks = longval; |
ce51bde6 DE |
1729 | break; |
1730 | } | |
1731 | } | |
1732 | ||
7478904c | 1733 | void |
ce51bde6 DE |
1734 | sim_fetch_register (rn, buf) |
1735 | int rn; | |
a415cf0a | 1736 | unsigned char *buf; |
ce51bde6 DE |
1737 | { |
1738 | int v; | |
1739 | int longreg = 0; | |
1740 | ||
1741 | init_pointers (); | |
1742 | ||
1743 | switch (rn) | |
1744 | { | |
1745 | default: | |
1746 | abort (); | |
1747 | case 8: | |
1748 | v = cpu.ccr; | |
1749 | break; | |
1750 | case 9: | |
1751 | v = cpu.pc; | |
1752 | break; | |
1753 | case R0_REGNUM: | |
1754 | case R1_REGNUM: | |
1755 | case R2_REGNUM: | |
1756 | case R3_REGNUM: | |
1757 | case R4_REGNUM: | |
1758 | case R5_REGNUM: | |
1759 | case R6_REGNUM: | |
1760 | case R7_REGNUM: | |
1761 | v = cpu.regs[rn]; | |
1762 | break; | |
1763 | case 10: | |
1764 | v = cpu.cycles; | |
1765 | longreg = 1; | |
ce51bde6 DE |
1766 | break; |
1767 | case 11: | |
1768 | v = cpu.ticks; | |
1769 | longreg = 1; | |
1770 | break; | |
1771 | case 12: | |
1772 | v = cpu.insts; | |
1773 | longreg = 1; | |
1774 | break; | |
ce51bde6 | 1775 | } |
28655f00 | 1776 | if (h8300hmode || longreg) |
ce51bde6 DE |
1777 | { |
1778 | buf[0] = v >> 24; | |
1779 | buf[1] = v >> 16; | |
1780 | buf[2] = v >> 8; | |
1781 | buf[3] = v >> 0; | |
1782 | } | |
1783 | else | |
1784 | { | |
1785 | buf[0] = v >> 8; | |
1786 | buf[1] = v; | |
1787 | } | |
1788 | } | |
1789 | ||
7478904c | 1790 | void |
a415cf0a DE |
1791 | sim_stop_reason (reason, sigrc) |
1792 | enum sim_stop *reason; | |
1793 | int *sigrc; | |
ce51bde6 | 1794 | { |
a415cf0a | 1795 | *reason = sim_stopped; |
7db9345b | 1796 | *sigrc = cpu.exception; |
ce51bde6 DE |
1797 | } |
1798 | ||
ce51bde6 DE |
1799 | sim_csize (n) |
1800 | { | |
1801 | if (cpu.cache) | |
1802 | free (cpu.cache); | |
1803 | if (n < 2) | |
1804 | n = 2; | |
1805 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1806 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1807 | cpu.csize = n; | |
1808 | } | |
1809 | ||
1810 | ||
7478904c SC |
1811 | void |
1812 | sim_info (verbose) | |
ce51bde6 | 1813 | int verbose; |
ce51bde6 DE |
1814 | { |
1815 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1816 | double virttime = cpu.cycles / 10.0e6; | |
1817 | ||
7478904c SC |
1818 | printf_filtered ("\n\n#instructions executed %10d\n", cpu.insts); |
1819 | printf_filtered ("#cycles (v approximate) %10d\n", cpu.cycles); | |
1820 | printf_filtered ("#real time taken %10.4f\n", timetaken); | |
1821 | printf_filtered ("#virtual time taked %10.4f\n", virttime); | |
0693d363 | 1822 | if (timetaken != 0.0) |
7478904c SC |
1823 | printf_filtered ("#simulation ratio %10.4f\n", virttime / timetaken); |
1824 | printf_filtered ("#compiles %10d\n", cpu.compiles); | |
1825 | printf_filtered ("#cache size %10d\n", cpu.csize); | |
ce51bde6 DE |
1826 | |
1827 | #ifdef ADEBUG | |
0693d363 | 1828 | if (verbose) |
ce51bde6 DE |
1829 | { |
1830 | int i; | |
0693d363 | 1831 | for (i = 0; i < O_LAST; i++) |
ce51bde6 DE |
1832 | { |
1833 | if (cpu.stats[i]) | |
7478904c | 1834 | printf_filtered ("%d: %d\n", i, cpu.stats[i]); |
ce51bde6 DE |
1835 | } |
1836 | } | |
1837 | #endif | |
1838 | } | |
1839 | ||
7478904c SC |
1840 | /* Indicate whether the cpu is an h8/300 or h8/300h. |
1841 | FLAG is non-zero for the h8/300h. */ | |
1842 | ||
89a2c4fd | 1843 | void |
7478904c SC |
1844 | set_h8300h (flag) |
1845 | int flag; | |
89a2c4fd | 1846 | { |
7478904c | 1847 | h8300hmode = flag; |
89a2c4fd | 1848 | } |
28655f00 | 1849 | |
7478904c | 1850 | void |
0693d363 | 1851 | sim_kill () |
7db9345b | 1852 | { |
7478904c | 1853 | /* nothing to do */ |
7db9345b DE |
1854 | } |
1855 | ||
7478904c SC |
1856 | void |
1857 | sim_open (args) | |
1858 | char *args; | |
7db9345b | 1859 | { |
7478904c | 1860 | /* nothing to do */ |
7db9345b DE |
1861 | } |
1862 | ||
7478904c SC |
1863 | void |
1864 | sim_close (quitting) | |
1865 | int quitting; | |
1866 | { | |
1867 | /* nothing to do */ | |
1868 | } | |
1869 | ||
1870 | /* Called by gdb to load a program into memory. */ | |
1871 | ||
1872 | int | |
1873 | sim_load (prog, from_tty) | |
1874 | char *prog; | |
1875 | int from_tty; | |
1876 | { | |
1877 | bfd *abfd; | |
1878 | ||
1879 | /* See if the file is for the h8/300 or h8/300h. */ | |
1880 | /* ??? This may not be the most efficient way. The z8k simulator | |
1881 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
1882 | if ((abfd = bfd_openr (prog, "coff-h8300")) != 0) | |
1883 | { | |
1884 | if (bfd_check_format (abfd, bfd_object)) | |
1885 | set_h8300h (abfd->arch_info->mach == bfd_mach_h8300h); | |
1886 | bfd_close (abfd); | |
1887 | } | |
1888 | ||
1889 | /* Return non-zero so gdb will handle it. */ | |
1890 | return 1; | |
1891 | } | |
1892 | ||
1893 | void | |
1894 | sim_create_inferior (start_address, argv, env) | |
1895 | SIM_ADDR start_address; | |
a415cf0a DE |
1896 | char **argv; |
1897 | char **env; | |
7db9345b | 1898 | { |
7478904c | 1899 | cpu.pc = start_address; |
7db9345b | 1900 | } |
e656ecf9 DE |
1901 | |
1902 | void | |
1903 | sim_do_command (cmd) | |
1904 | char *cmd; | |
1905 | { | |
1906 | printf_filtered ("This simulator does not accept any commands.\n"); | |
1907 | } | |
1908 | ||
1909 | ||
1910 | ||
1911 | void | |
1912 | sim_set_callbacks (ptr) | |
1913 | struct host_callback_struct *ptr; | |
1914 | { | |
1915 | ||
1916 | } | |
1917 |