Commit | Line | Data |
---|---|---|
7ecaa5af SC |
1 | #define DEBUG |
2 | ||
3 | #define MPOWER 16 | |
4 | #define MSIZE (1<<MPOWER) | |
5 | #define CSIZE 1000 | |
6 | /* Local register names */ | |
7 | typedef enum | |
8 | { | |
9 | R0, R1, R2, R3, R4, R5, R6, R7, | |
10 | R_ZERO, | |
11 | R_PC, | |
12 | R_CCR, | |
13 | R_HARD_0, | |
14 | R_LAST, | |
15 | } reg_type; | |
16 | ||
17 | ||
18 | /* Structure used to describe addressing */ | |
19 | ||
20 | typedef struct | |
21 | { | |
22 | int type; | |
23 | int reg; | |
24 | int literal; | |
25 | } ea_type; | |
26 | ||
27 | ||
28 | ||
29 | typedef struct | |
30 | { | |
31 | ea_type src; | |
32 | ea_type dst; | |
33 | int opcode; | |
34 | int next_pc; | |
35 | int oldpc; | |
36 | int cycles; | |
37 | #ifdef DEBUG | |
38 | struct h8_opcode *op; | |
39 | #endif | |
40 | } | |
41 | ||
42 | decoded_inst; | |
43 | ||
44 | ||
45 | ||
46 | typedef struct | |
47 | { | |
48 | int exception; | |
49 | unsigned int regs[9]; | |
50 | int pc; | |
51 | int ccr; | |
52 | ||
53 | ||
54 | unsigned char *memory; | |
55 | unsigned short *cache_idx; | |
56 | int cache_top; | |
57 | int maximum; | |
58 | int csize; | |
59 | int mask; | |
60 | ||
61 | decoded_inst *cache; | |
62 | int cycles; | |
63 | int insts; | |
64 | int ticks; | |
65 | int compiles; | |
66 | #ifdef ADEBUG | |
67 | int stats[O_LAST]; | |
68 | #endif | |
69 | } | |
70 | ||
71 | cpu_state_type; |