projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| ea6bbfba SC |
1 | /* |
| 2 | Written by Steve Chamberlain of Cygnus Support. | |
| 3 | sac@cygnus.com | |
| 4 | ||
| 5 | This file is part of H8/300 sim | |
| 6 | ||
| 7 | ||
| 8 | THIS SOFTWARE IS NOT COPYRIGHTED | |
| 9 | ||
| 10 | Cygnus offers the following for use in the public domain. Cygnus | |
| 11 | makes no warranty with regard to the software or it's performance | |
| 12 | and the user accepts the software "AS IS" with all faults. | |
| 13 | ||
| 14 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
| 15 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
| 16 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
| 17 | ||
| 18 | */ | |
| 18079b9e | 19 | #include "../endian.h" |
| 69488a77 SC |
20 | #define SET_WORD_MEM(x,y) {saved_state.mem[(x)>>1] = y;} |
| 21 | #define SET_BYTE_MEM(x,y) {BYTE_MEM(x)=y;} | |
| 22 | ||
| 23 | #define WORD_MEM(x) (saved_state.mem[(x)>>1]) | |
| 24 | #define BYTE_MEM(x) (*(((char *)(saved_state.mem))+((x)^HOST_IS_LITTLE_ENDIAN))) | |
| 25 | ||
| 26 | #define CCR 8 | |
| 27 | #define PC 9 | |
| 28 | #define CYCLES 10 | |
| 29 | #define HCHECK 11 | |
| 30 | #define TIER 12 | |
| 31 | #define TCSR 13 | |
| 32 | #define FRC 14 | |
| 33 | #define OCRA 15 | |
| 34 | #define OCRB 16 | |
| 35 | #define TCR 17 | |
| 36 | #define TOCR 18 | |
| 37 | #define ICRA 19 | |
| 38 | #define NREG 20 | |
| 39 | struct state | |
| 40 | { | |
| 41 | unsigned short int reg[NREG]; | |
| 42 | unsigned char *(bregp[16]); | |
| 43 | unsigned char *(bregp_NNNNxxxx[256]); | |
| 44 | unsigned char *(bregp_xxxxNNNN[256]); | |
| 45 | unsigned short int *(wregp_xNNNxxxx[256]); | |
| 46 | unsigned short int *(wregp_xxxxxNNN[256]); | |
| 47 | int exception; | |
| 48 | int ienable; | |
| 49 | unsigned short *mem; | |
| 50 | } | |
| 51 | ||
| 52 | saved_state; | |
| 53 | ||
| 54 | ||
| 55 | ||
| 56 | #define OCFA (1<<3) | |
| 57 | #define OCFB (1<<2) | |
| 58 | #define CCLRA (1<<0) | |
| 59 | /* TCR bits */ | |
| 60 | #define OCIEA (1<<3) | |
| 61 | #define OCIEB (1<<2) | |
| 62 | #define OVIE (1<<1) | |
| 63 | #define OVF (1<<1) | |
| 64 | ||
| 65 | /* TOCR bits */ | |
| 66 | #define OCRS (1<<4) | |
| 67 | ||
| 68 | ||
| 18079b9e | 69 | #ifdef LITTLE_ENDIAN_HOST |
| 69488a77 SC |
70 | #define HOST_IS_LITTLE_ENDIAN 1 |
| 71 | #else | |
| 72 | #define HOST_IS_LITTLE_ENDIAN 0 | |
| 73 | #endif | |
| 74 | ||
| 75 | #define SAVE_INTERPRETER_STATE() \ | |
| 76 | saved_state.reg[CYCLES] = cycles; \ | |
| 77 | saved_state.reg[PC] = (pc - saved_state.mem) <<1; \ | |
| 78 | saved_state.reg[CCR] = GET_CCR(); \ | |
| 79 | store_timer_state_to_mem(); | |
| 80 | ||
| 81 | #define LOAD_INTERPRETER_STATE() \ | |
| 82 | SET_CCR (saved_state.reg[CCR]); \ | |
| 83 | checkfreq = saved_state.reg[HCHECK]; \ | |
| 84 | pc = (saved_state.reg[PC]>>1) + saved_state.mem; \ | |
| 85 | load_timer_state_from_mem(); \ | |
| 86 | cycles=saved_state.reg[CYCLES]; |