Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* Simulator instruction decoder for i960base. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Simulators. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #define WANT_CPU i960base | |
26 | #define WANT_CPU_I960BASE | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "sim-assert.h" | |
30 | ||
31 | /* FIXME: Need to review choices for the following. */ | |
32 | ||
33 | #if WITH_SEM_SWITCH_FULL | |
34 | #define FULL(fn) | |
35 | #else | |
36 | #define FULL(fn) CONCAT3 (i960base,_sem_,fn) , | |
37 | #endif | |
38 | ||
39 | #if WITH_FAST | |
40 | #if WITH_SEM_SWITCH_FAST | |
41 | #define FAST(fn) | |
42 | #else | |
43 | #define FAST(fn) CONCAT3 (i960base,_semf_,fn) , /* f for fast */ | |
44 | #endif | |
45 | #else | |
46 | #define FAST(fn) | |
47 | #endif | |
48 | ||
49 | /* The instruction descriptor array. | |
50 | This is computed at runtime. Space for it is not malloc'd to save a | |
51 | teensy bit of cpu in the decoder. Moving it to malloc space is trivial | |
52 | but won't be done until necessary (we don't currently support the runtime | |
53 | addition of instructions nor an SMP machine with different cpus). */ | |
54 | static IDESC i960base_insn_data[I960BASE_INSN_MAX]; | |
55 | ||
56 | /* The INSN_ prefix is not here and is instead part of the `insn' argument | |
57 | to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ | |
58 | #define IDX(insn) CONCAT2 (I960BASE_,insn) | |
59 | #define TYPE(insn) CONCAT2 (I960_,insn) | |
60 | ||
61 | /* Commas between elements are contained in the macros. | |
62 | Some of these are conditionally compiled out. */ | |
63 | ||
64 | static const struct insn_sem i960base_insn_sem[] = | |
65 | { | |
66 | { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, | |
67 | { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, | |
68 | { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, | |
69 | { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, | |
70 | { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, | |
71 | { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, | |
72 | { TYPE (INSN_MULO), IDX (INSN_MULO), FULL (mulo) FAST (mulo) }, | |
73 | { TYPE (INSN_MULO1), IDX (INSN_MULO1), FULL (mulo1) FAST (mulo1) }, | |
74 | { TYPE (INSN_MULO2), IDX (INSN_MULO2), FULL (mulo2) FAST (mulo2) }, | |
75 | { TYPE (INSN_MULO3), IDX (INSN_MULO3), FULL (mulo3) FAST (mulo3) }, | |
76 | { TYPE (INSN_REMO), IDX (INSN_REMO), FULL (remo) FAST (remo) }, | |
77 | { TYPE (INSN_REMO1), IDX (INSN_REMO1), FULL (remo1) FAST (remo1) }, | |
78 | { TYPE (INSN_REMO2), IDX (INSN_REMO2), FULL (remo2) FAST (remo2) }, | |
79 | { TYPE (INSN_REMO3), IDX (INSN_REMO3), FULL (remo3) FAST (remo3) }, | |
80 | { TYPE (INSN_DIVO), IDX (INSN_DIVO), FULL (divo) FAST (divo) }, | |
81 | { TYPE (INSN_DIVO1), IDX (INSN_DIVO1), FULL (divo1) FAST (divo1) }, | |
82 | { TYPE (INSN_DIVO2), IDX (INSN_DIVO2), FULL (divo2) FAST (divo2) }, | |
83 | { TYPE (INSN_DIVO3), IDX (INSN_DIVO3), FULL (divo3) FAST (divo3) }, | |
84 | { TYPE (INSN_REMI), IDX (INSN_REMI), FULL (remi) FAST (remi) }, | |
85 | { TYPE (INSN_REMI1), IDX (INSN_REMI1), FULL (remi1) FAST (remi1) }, | |
86 | { TYPE (INSN_REMI2), IDX (INSN_REMI2), FULL (remi2) FAST (remi2) }, | |
87 | { TYPE (INSN_REMI3), IDX (INSN_REMI3), FULL (remi3) FAST (remi3) }, | |
88 | { TYPE (INSN_DIVI), IDX (INSN_DIVI), FULL (divi) FAST (divi) }, | |
89 | { TYPE (INSN_DIVI1), IDX (INSN_DIVI1), FULL (divi1) FAST (divi1) }, | |
90 | { TYPE (INSN_DIVI2), IDX (INSN_DIVI2), FULL (divi2) FAST (divi2) }, | |
91 | { TYPE (INSN_DIVI3), IDX (INSN_DIVI3), FULL (divi3) FAST (divi3) }, | |
92 | { TYPE (INSN_ADDO), IDX (INSN_ADDO), FULL (addo) FAST (addo) }, | |
93 | { TYPE (INSN_ADDO1), IDX (INSN_ADDO1), FULL (addo1) FAST (addo1) }, | |
94 | { TYPE (INSN_ADDO2), IDX (INSN_ADDO2), FULL (addo2) FAST (addo2) }, | |
95 | { TYPE (INSN_ADDO3), IDX (INSN_ADDO3), FULL (addo3) FAST (addo3) }, | |
96 | { TYPE (INSN_SUBO), IDX (INSN_SUBO), FULL (subo) FAST (subo) }, | |
97 | { TYPE (INSN_SUBO1), IDX (INSN_SUBO1), FULL (subo1) FAST (subo1) }, | |
98 | { TYPE (INSN_SUBO2), IDX (INSN_SUBO2), FULL (subo2) FAST (subo2) }, | |
99 | { TYPE (INSN_SUBO3), IDX (INSN_SUBO3), FULL (subo3) FAST (subo3) }, | |
100 | { TYPE (INSN_NOTBIT), IDX (INSN_NOTBIT), FULL (notbit) FAST (notbit) }, | |
101 | { TYPE (INSN_NOTBIT1), IDX (INSN_NOTBIT1), FULL (notbit1) FAST (notbit1) }, | |
102 | { TYPE (INSN_NOTBIT2), IDX (INSN_NOTBIT2), FULL (notbit2) FAST (notbit2) }, | |
103 | { TYPE (INSN_NOTBIT3), IDX (INSN_NOTBIT3), FULL (notbit3) FAST (notbit3) }, | |
104 | { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, | |
105 | { TYPE (INSN_AND1), IDX (INSN_AND1), FULL (and1) FAST (and1) }, | |
106 | { TYPE (INSN_AND2), IDX (INSN_AND2), FULL (and2) FAST (and2) }, | |
107 | { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) }, | |
108 | { TYPE (INSN_ANDNOT), IDX (INSN_ANDNOT), FULL (andnot) FAST (andnot) }, | |
109 | { TYPE (INSN_ANDNOT1), IDX (INSN_ANDNOT1), FULL (andnot1) FAST (andnot1) }, | |
110 | { TYPE (INSN_ANDNOT2), IDX (INSN_ANDNOT2), FULL (andnot2) FAST (andnot2) }, | |
111 | { TYPE (INSN_ANDNOT3), IDX (INSN_ANDNOT3), FULL (andnot3) FAST (andnot3) }, | |
112 | { TYPE (INSN_SETBIT), IDX (INSN_SETBIT), FULL (setbit) FAST (setbit) }, | |
113 | { TYPE (INSN_SETBIT1), IDX (INSN_SETBIT1), FULL (setbit1) FAST (setbit1) }, | |
114 | { TYPE (INSN_SETBIT2), IDX (INSN_SETBIT2), FULL (setbit2) FAST (setbit2) }, | |
115 | { TYPE (INSN_SETBIT3), IDX (INSN_SETBIT3), FULL (setbit3) FAST (setbit3) }, | |
116 | { TYPE (INSN_NOTAND), IDX (INSN_NOTAND), FULL (notand) FAST (notand) }, | |
117 | { TYPE (INSN_NOTAND1), IDX (INSN_NOTAND1), FULL (notand1) FAST (notand1) }, | |
118 | { TYPE (INSN_NOTAND2), IDX (INSN_NOTAND2), FULL (notand2) FAST (notand2) }, | |
119 | { TYPE (INSN_NOTAND3), IDX (INSN_NOTAND3), FULL (notand3) FAST (notand3) }, | |
120 | { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) }, | |
121 | { TYPE (INSN_XOR1), IDX (INSN_XOR1), FULL (xor1) FAST (xor1) }, | |
122 | { TYPE (INSN_XOR2), IDX (INSN_XOR2), FULL (xor2) FAST (xor2) }, | |
123 | { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) }, | |
124 | { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, | |
125 | { TYPE (INSN_OR1), IDX (INSN_OR1), FULL (or1) FAST (or1) }, | |
126 | { TYPE (INSN_OR2), IDX (INSN_OR2), FULL (or2) FAST (or2) }, | |
127 | { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) }, | |
128 | { TYPE (INSN_NOR), IDX (INSN_NOR), FULL (nor) FAST (nor) }, | |
129 | { TYPE (INSN_NOR1), IDX (INSN_NOR1), FULL (nor1) FAST (nor1) }, | |
130 | { TYPE (INSN_NOR2), IDX (INSN_NOR2), FULL (nor2) FAST (nor2) }, | |
131 | { TYPE (INSN_NOR3), IDX (INSN_NOR3), FULL (nor3) FAST (nor3) }, | |
132 | { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) }, | |
133 | { TYPE (INSN_NOT1), IDX (INSN_NOT1), FULL (not1) FAST (not1) }, | |
134 | { TYPE (INSN_NOT2), IDX (INSN_NOT2), FULL (not2) FAST (not2) }, | |
135 | { TYPE (INSN_NOT3), IDX (INSN_NOT3), FULL (not3) FAST (not3) }, | |
136 | { TYPE (INSN_CLRBIT), IDX (INSN_CLRBIT), FULL (clrbit) FAST (clrbit) }, | |
137 | { TYPE (INSN_CLRBIT1), IDX (INSN_CLRBIT1), FULL (clrbit1) FAST (clrbit1) }, | |
138 | { TYPE (INSN_CLRBIT2), IDX (INSN_CLRBIT2), FULL (clrbit2) FAST (clrbit2) }, | |
139 | { TYPE (INSN_CLRBIT3), IDX (INSN_CLRBIT3), FULL (clrbit3) FAST (clrbit3) }, | |
140 | { TYPE (INSN_SHLO), IDX (INSN_SHLO), FULL (shlo) FAST (shlo) }, | |
141 | { TYPE (INSN_SHLO1), IDX (INSN_SHLO1), FULL (shlo1) FAST (shlo1) }, | |
142 | { TYPE (INSN_SHLO2), IDX (INSN_SHLO2), FULL (shlo2) FAST (shlo2) }, | |
143 | { TYPE (INSN_SHLO3), IDX (INSN_SHLO3), FULL (shlo3) FAST (shlo3) }, | |
144 | { TYPE (INSN_SHRO), IDX (INSN_SHRO), FULL (shro) FAST (shro) }, | |
145 | { TYPE (INSN_SHRO1), IDX (INSN_SHRO1), FULL (shro1) FAST (shro1) }, | |
146 | { TYPE (INSN_SHRO2), IDX (INSN_SHRO2), FULL (shro2) FAST (shro2) }, | |
147 | { TYPE (INSN_SHRO3), IDX (INSN_SHRO3), FULL (shro3) FAST (shro3) }, | |
148 | { TYPE (INSN_SHLI), IDX (INSN_SHLI), FULL (shli) FAST (shli) }, | |
149 | { TYPE (INSN_SHLI1), IDX (INSN_SHLI1), FULL (shli1) FAST (shli1) }, | |
150 | { TYPE (INSN_SHLI2), IDX (INSN_SHLI2), FULL (shli2) FAST (shli2) }, | |
151 | { TYPE (INSN_SHLI3), IDX (INSN_SHLI3), FULL (shli3) FAST (shli3) }, | |
152 | { TYPE (INSN_SHRI), IDX (INSN_SHRI), FULL (shri) FAST (shri) }, | |
153 | { TYPE (INSN_SHRI1), IDX (INSN_SHRI1), FULL (shri1) FAST (shri1) }, | |
154 | { TYPE (INSN_SHRI2), IDX (INSN_SHRI2), FULL (shri2) FAST (shri2) }, | |
155 | { TYPE (INSN_SHRI3), IDX (INSN_SHRI3), FULL (shri3) FAST (shri3) }, | |
156 | { TYPE (INSN_EMUL), IDX (INSN_EMUL), FULL (emul) FAST (emul) }, | |
157 | { TYPE (INSN_EMUL1), IDX (INSN_EMUL1), FULL (emul1) FAST (emul1) }, | |
158 | { TYPE (INSN_EMUL2), IDX (INSN_EMUL2), FULL (emul2) FAST (emul2) }, | |
159 | { TYPE (INSN_EMUL3), IDX (INSN_EMUL3), FULL (emul3) FAST (emul3) }, | |
160 | { TYPE (INSN_MOV), IDX (INSN_MOV), FULL (mov) FAST (mov) }, | |
161 | { TYPE (INSN_MOV1), IDX (INSN_MOV1), FULL (mov1) FAST (mov1) }, | |
162 | { TYPE (INSN_MOVL), IDX (INSN_MOVL), FULL (movl) FAST (movl) }, | |
163 | { TYPE (INSN_MOVL1), IDX (INSN_MOVL1), FULL (movl1) FAST (movl1) }, | |
164 | { TYPE (INSN_MOVT), IDX (INSN_MOVT), FULL (movt) FAST (movt) }, | |
165 | { TYPE (INSN_MOVT1), IDX (INSN_MOVT1), FULL (movt1) FAST (movt1) }, | |
166 | { TYPE (INSN_MOVQ), IDX (INSN_MOVQ), FULL (movq) FAST (movq) }, | |
167 | { TYPE (INSN_MOVQ1), IDX (INSN_MOVQ1), FULL (movq1) FAST (movq1) }, | |
168 | { TYPE (INSN_MODPC), IDX (INSN_MODPC), FULL (modpc) FAST (modpc) }, | |
169 | { TYPE (INSN_MODAC), IDX (INSN_MODAC), FULL (modac) FAST (modac) }, | |
170 | { TYPE (INSN_LDA_OFFSET), IDX (INSN_LDA_OFFSET), FULL (lda_offset) FAST (lda_offset) }, | |
171 | { TYPE (INSN_LDA_INDIRECT_OFFSET), IDX (INSN_LDA_INDIRECT_OFFSET), FULL (lda_indirect_offset) FAST (lda_indirect_offset) }, | |
172 | { TYPE (INSN_LDA_INDIRECT), IDX (INSN_LDA_INDIRECT), FULL (lda_indirect) FAST (lda_indirect) }, | |
173 | { TYPE (INSN_LDA_INDIRECT_INDEX), IDX (INSN_LDA_INDIRECT_INDEX), FULL (lda_indirect_index) FAST (lda_indirect_index) }, | |
174 | { TYPE (INSN_LDA_DISP), IDX (INSN_LDA_DISP), FULL (lda_disp) FAST (lda_disp) }, | |
175 | { TYPE (INSN_LDA_INDIRECT_DISP), IDX (INSN_LDA_INDIRECT_DISP), FULL (lda_indirect_disp) FAST (lda_indirect_disp) }, | |
176 | { TYPE (INSN_LDA_INDEX_DISP), IDX (INSN_LDA_INDEX_DISP), FULL (lda_index_disp) FAST (lda_index_disp) }, | |
177 | { TYPE (INSN_LDA_INDIRECT_INDEX_DISP), IDX (INSN_LDA_INDIRECT_INDEX_DISP), FULL (lda_indirect_index_disp) FAST (lda_indirect_index_disp) }, | |
178 | { TYPE (INSN_LD_OFFSET), IDX (INSN_LD_OFFSET), FULL (ld_offset) FAST (ld_offset) }, | |
179 | { TYPE (INSN_LD_INDIRECT_OFFSET), IDX (INSN_LD_INDIRECT_OFFSET), FULL (ld_indirect_offset) FAST (ld_indirect_offset) }, | |
180 | { TYPE (INSN_LD_INDIRECT), IDX (INSN_LD_INDIRECT), FULL (ld_indirect) FAST (ld_indirect) }, | |
181 | { TYPE (INSN_LD_INDIRECT_INDEX), IDX (INSN_LD_INDIRECT_INDEX), FULL (ld_indirect_index) FAST (ld_indirect_index) }, | |
182 | { TYPE (INSN_LD_DISP), IDX (INSN_LD_DISP), FULL (ld_disp) FAST (ld_disp) }, | |
183 | { TYPE (INSN_LD_INDIRECT_DISP), IDX (INSN_LD_INDIRECT_DISP), FULL (ld_indirect_disp) FAST (ld_indirect_disp) }, | |
184 | { TYPE (INSN_LD_INDEX_DISP), IDX (INSN_LD_INDEX_DISP), FULL (ld_index_disp) FAST (ld_index_disp) }, | |
185 | { TYPE (INSN_LD_INDIRECT_INDEX_DISP), IDX (INSN_LD_INDIRECT_INDEX_DISP), FULL (ld_indirect_index_disp) FAST (ld_indirect_index_disp) }, | |
186 | { TYPE (INSN_LDOB_OFFSET), IDX (INSN_LDOB_OFFSET), FULL (ldob_offset) FAST (ldob_offset) }, | |
187 | { TYPE (INSN_LDOB_INDIRECT_OFFSET), IDX (INSN_LDOB_INDIRECT_OFFSET), FULL (ldob_indirect_offset) FAST (ldob_indirect_offset) }, | |
188 | { TYPE (INSN_LDOB_INDIRECT), IDX (INSN_LDOB_INDIRECT), FULL (ldob_indirect) FAST (ldob_indirect) }, | |
189 | { TYPE (INSN_LDOB_INDIRECT_INDEX), IDX (INSN_LDOB_INDIRECT_INDEX), FULL (ldob_indirect_index) FAST (ldob_indirect_index) }, | |
190 | { TYPE (INSN_LDOB_DISP), IDX (INSN_LDOB_DISP), FULL (ldob_disp) FAST (ldob_disp) }, | |
191 | { TYPE (INSN_LDOB_INDIRECT_DISP), IDX (INSN_LDOB_INDIRECT_DISP), FULL (ldob_indirect_disp) FAST (ldob_indirect_disp) }, | |
192 | { TYPE (INSN_LDOB_INDEX_DISP), IDX (INSN_LDOB_INDEX_DISP), FULL (ldob_index_disp) FAST (ldob_index_disp) }, | |
193 | { TYPE (INSN_LDOB_INDIRECT_INDEX_DISP), IDX (INSN_LDOB_INDIRECT_INDEX_DISP), FULL (ldob_indirect_index_disp) FAST (ldob_indirect_index_disp) }, | |
194 | { TYPE (INSN_LDOS_OFFSET), IDX (INSN_LDOS_OFFSET), FULL (ldos_offset) FAST (ldos_offset) }, | |
195 | { TYPE (INSN_LDOS_INDIRECT_OFFSET), IDX (INSN_LDOS_INDIRECT_OFFSET), FULL (ldos_indirect_offset) FAST (ldos_indirect_offset) }, | |
196 | { TYPE (INSN_LDOS_INDIRECT), IDX (INSN_LDOS_INDIRECT), FULL (ldos_indirect) FAST (ldos_indirect) }, | |
197 | { TYPE (INSN_LDOS_INDIRECT_INDEX), IDX (INSN_LDOS_INDIRECT_INDEX), FULL (ldos_indirect_index) FAST (ldos_indirect_index) }, | |
198 | { TYPE (INSN_LDOS_DISP), IDX (INSN_LDOS_DISP), FULL (ldos_disp) FAST (ldos_disp) }, | |
199 | { TYPE (INSN_LDOS_INDIRECT_DISP), IDX (INSN_LDOS_INDIRECT_DISP), FULL (ldos_indirect_disp) FAST (ldos_indirect_disp) }, | |
200 | { TYPE (INSN_LDOS_INDEX_DISP), IDX (INSN_LDOS_INDEX_DISP), FULL (ldos_index_disp) FAST (ldos_index_disp) }, | |
201 | { TYPE (INSN_LDOS_INDIRECT_INDEX_DISP), IDX (INSN_LDOS_INDIRECT_INDEX_DISP), FULL (ldos_indirect_index_disp) FAST (ldos_indirect_index_disp) }, | |
202 | { TYPE (INSN_LDIB_OFFSET), IDX (INSN_LDIB_OFFSET), FULL (ldib_offset) FAST (ldib_offset) }, | |
203 | { TYPE (INSN_LDIB_INDIRECT_OFFSET), IDX (INSN_LDIB_INDIRECT_OFFSET), FULL (ldib_indirect_offset) FAST (ldib_indirect_offset) }, | |
204 | { TYPE (INSN_LDIB_INDIRECT), IDX (INSN_LDIB_INDIRECT), FULL (ldib_indirect) FAST (ldib_indirect) }, | |
205 | { TYPE (INSN_LDIB_INDIRECT_INDEX), IDX (INSN_LDIB_INDIRECT_INDEX), FULL (ldib_indirect_index) FAST (ldib_indirect_index) }, | |
206 | { TYPE (INSN_LDIB_DISP), IDX (INSN_LDIB_DISP), FULL (ldib_disp) FAST (ldib_disp) }, | |
207 | { TYPE (INSN_LDIB_INDIRECT_DISP), IDX (INSN_LDIB_INDIRECT_DISP), FULL (ldib_indirect_disp) FAST (ldib_indirect_disp) }, | |
208 | { TYPE (INSN_LDIB_INDEX_DISP), IDX (INSN_LDIB_INDEX_DISP), FULL (ldib_index_disp) FAST (ldib_index_disp) }, | |
209 | { TYPE (INSN_LDIB_INDIRECT_INDEX_DISP), IDX (INSN_LDIB_INDIRECT_INDEX_DISP), FULL (ldib_indirect_index_disp) FAST (ldib_indirect_index_disp) }, | |
210 | { TYPE (INSN_LDIS_OFFSET), IDX (INSN_LDIS_OFFSET), FULL (ldis_offset) FAST (ldis_offset) }, | |
211 | { TYPE (INSN_LDIS_INDIRECT_OFFSET), IDX (INSN_LDIS_INDIRECT_OFFSET), FULL (ldis_indirect_offset) FAST (ldis_indirect_offset) }, | |
212 | { TYPE (INSN_LDIS_INDIRECT), IDX (INSN_LDIS_INDIRECT), FULL (ldis_indirect) FAST (ldis_indirect) }, | |
213 | { TYPE (INSN_LDIS_INDIRECT_INDEX), IDX (INSN_LDIS_INDIRECT_INDEX), FULL (ldis_indirect_index) FAST (ldis_indirect_index) }, | |
214 | { TYPE (INSN_LDIS_DISP), IDX (INSN_LDIS_DISP), FULL (ldis_disp) FAST (ldis_disp) }, | |
215 | { TYPE (INSN_LDIS_INDIRECT_DISP), IDX (INSN_LDIS_INDIRECT_DISP), FULL (ldis_indirect_disp) FAST (ldis_indirect_disp) }, | |
216 | { TYPE (INSN_LDIS_INDEX_DISP), IDX (INSN_LDIS_INDEX_DISP), FULL (ldis_index_disp) FAST (ldis_index_disp) }, | |
217 | { TYPE (INSN_LDIS_INDIRECT_INDEX_DISP), IDX (INSN_LDIS_INDIRECT_INDEX_DISP), FULL (ldis_indirect_index_disp) FAST (ldis_indirect_index_disp) }, | |
218 | { TYPE (INSN_LDL_OFFSET), IDX (INSN_LDL_OFFSET), FULL (ldl_offset) FAST (ldl_offset) }, | |
219 | { TYPE (INSN_LDL_INDIRECT_OFFSET), IDX (INSN_LDL_INDIRECT_OFFSET), FULL (ldl_indirect_offset) FAST (ldl_indirect_offset) }, | |
220 | { TYPE (INSN_LDL_INDIRECT), IDX (INSN_LDL_INDIRECT), FULL (ldl_indirect) FAST (ldl_indirect) }, | |
221 | { TYPE (INSN_LDL_INDIRECT_INDEX), IDX (INSN_LDL_INDIRECT_INDEX), FULL (ldl_indirect_index) FAST (ldl_indirect_index) }, | |
222 | { TYPE (INSN_LDL_DISP), IDX (INSN_LDL_DISP), FULL (ldl_disp) FAST (ldl_disp) }, | |
223 | { TYPE (INSN_LDL_INDIRECT_DISP), IDX (INSN_LDL_INDIRECT_DISP), FULL (ldl_indirect_disp) FAST (ldl_indirect_disp) }, | |
224 | { TYPE (INSN_LDL_INDEX_DISP), IDX (INSN_LDL_INDEX_DISP), FULL (ldl_index_disp) FAST (ldl_index_disp) }, | |
225 | { TYPE (INSN_LDL_INDIRECT_INDEX_DISP), IDX (INSN_LDL_INDIRECT_INDEX_DISP), FULL (ldl_indirect_index_disp) FAST (ldl_indirect_index_disp) }, | |
226 | { TYPE (INSN_LDT_OFFSET), IDX (INSN_LDT_OFFSET), FULL (ldt_offset) FAST (ldt_offset) }, | |
227 | { TYPE (INSN_LDT_INDIRECT_OFFSET), IDX (INSN_LDT_INDIRECT_OFFSET), FULL (ldt_indirect_offset) FAST (ldt_indirect_offset) }, | |
228 | { TYPE (INSN_LDT_INDIRECT), IDX (INSN_LDT_INDIRECT), FULL (ldt_indirect) FAST (ldt_indirect) }, | |
229 | { TYPE (INSN_LDT_INDIRECT_INDEX), IDX (INSN_LDT_INDIRECT_INDEX), FULL (ldt_indirect_index) FAST (ldt_indirect_index) }, | |
230 | { TYPE (INSN_LDT_DISP), IDX (INSN_LDT_DISP), FULL (ldt_disp) FAST (ldt_disp) }, | |
231 | { TYPE (INSN_LDT_INDIRECT_DISP), IDX (INSN_LDT_INDIRECT_DISP), FULL (ldt_indirect_disp) FAST (ldt_indirect_disp) }, | |
232 | { TYPE (INSN_LDT_INDEX_DISP), IDX (INSN_LDT_INDEX_DISP), FULL (ldt_index_disp) FAST (ldt_index_disp) }, | |
233 | { TYPE (INSN_LDT_INDIRECT_INDEX_DISP), IDX (INSN_LDT_INDIRECT_INDEX_DISP), FULL (ldt_indirect_index_disp) FAST (ldt_indirect_index_disp) }, | |
234 | { TYPE (INSN_LDQ_OFFSET), IDX (INSN_LDQ_OFFSET), FULL (ldq_offset) FAST (ldq_offset) }, | |
235 | { TYPE (INSN_LDQ_INDIRECT_OFFSET), IDX (INSN_LDQ_INDIRECT_OFFSET), FULL (ldq_indirect_offset) FAST (ldq_indirect_offset) }, | |
236 | { TYPE (INSN_LDQ_INDIRECT), IDX (INSN_LDQ_INDIRECT), FULL (ldq_indirect) FAST (ldq_indirect) }, | |
237 | { TYPE (INSN_LDQ_INDIRECT_INDEX), IDX (INSN_LDQ_INDIRECT_INDEX), FULL (ldq_indirect_index) FAST (ldq_indirect_index) }, | |
238 | { TYPE (INSN_LDQ_DISP), IDX (INSN_LDQ_DISP), FULL (ldq_disp) FAST (ldq_disp) }, | |
239 | { TYPE (INSN_LDQ_INDIRECT_DISP), IDX (INSN_LDQ_INDIRECT_DISP), FULL (ldq_indirect_disp) FAST (ldq_indirect_disp) }, | |
240 | { TYPE (INSN_LDQ_INDEX_DISP), IDX (INSN_LDQ_INDEX_DISP), FULL (ldq_index_disp) FAST (ldq_index_disp) }, | |
241 | { TYPE (INSN_LDQ_INDIRECT_INDEX_DISP), IDX (INSN_LDQ_INDIRECT_INDEX_DISP), FULL (ldq_indirect_index_disp) FAST (ldq_indirect_index_disp) }, | |
242 | { TYPE (INSN_ST_OFFSET), IDX (INSN_ST_OFFSET), FULL (st_offset) FAST (st_offset) }, | |
243 | { TYPE (INSN_ST_INDIRECT_OFFSET), IDX (INSN_ST_INDIRECT_OFFSET), FULL (st_indirect_offset) FAST (st_indirect_offset) }, | |
244 | { TYPE (INSN_ST_INDIRECT), IDX (INSN_ST_INDIRECT), FULL (st_indirect) FAST (st_indirect) }, | |
245 | { TYPE (INSN_ST_INDIRECT_INDEX), IDX (INSN_ST_INDIRECT_INDEX), FULL (st_indirect_index) FAST (st_indirect_index) }, | |
246 | { TYPE (INSN_ST_DISP), IDX (INSN_ST_DISP), FULL (st_disp) FAST (st_disp) }, | |
247 | { TYPE (INSN_ST_INDIRECT_DISP), IDX (INSN_ST_INDIRECT_DISP), FULL (st_indirect_disp) FAST (st_indirect_disp) }, | |
248 | { TYPE (INSN_ST_INDEX_DISP), IDX (INSN_ST_INDEX_DISP), FULL (st_index_disp) FAST (st_index_disp) }, | |
249 | { TYPE (INSN_ST_INDIRECT_INDEX_DISP), IDX (INSN_ST_INDIRECT_INDEX_DISP), FULL (st_indirect_index_disp) FAST (st_indirect_index_disp) }, | |
250 | { TYPE (INSN_STOB_OFFSET), IDX (INSN_STOB_OFFSET), FULL (stob_offset) FAST (stob_offset) }, | |
251 | { TYPE (INSN_STOB_INDIRECT_OFFSET), IDX (INSN_STOB_INDIRECT_OFFSET), FULL (stob_indirect_offset) FAST (stob_indirect_offset) }, | |
252 | { TYPE (INSN_STOB_INDIRECT), IDX (INSN_STOB_INDIRECT), FULL (stob_indirect) FAST (stob_indirect) }, | |
253 | { TYPE (INSN_STOB_INDIRECT_INDEX), IDX (INSN_STOB_INDIRECT_INDEX), FULL (stob_indirect_index) FAST (stob_indirect_index) }, | |
254 | { TYPE (INSN_STOB_DISP), IDX (INSN_STOB_DISP), FULL (stob_disp) FAST (stob_disp) }, | |
255 | { TYPE (INSN_STOB_INDIRECT_DISP), IDX (INSN_STOB_INDIRECT_DISP), FULL (stob_indirect_disp) FAST (stob_indirect_disp) }, | |
256 | { TYPE (INSN_STOB_INDEX_DISP), IDX (INSN_STOB_INDEX_DISP), FULL (stob_index_disp) FAST (stob_index_disp) }, | |
257 | { TYPE (INSN_STOB_INDIRECT_INDEX_DISP), IDX (INSN_STOB_INDIRECT_INDEX_DISP), FULL (stob_indirect_index_disp) FAST (stob_indirect_index_disp) }, | |
258 | { TYPE (INSN_STOS_OFFSET), IDX (INSN_STOS_OFFSET), FULL (stos_offset) FAST (stos_offset) }, | |
259 | { TYPE (INSN_STOS_INDIRECT_OFFSET), IDX (INSN_STOS_INDIRECT_OFFSET), FULL (stos_indirect_offset) FAST (stos_indirect_offset) }, | |
260 | { TYPE (INSN_STOS_INDIRECT), IDX (INSN_STOS_INDIRECT), FULL (stos_indirect) FAST (stos_indirect) }, | |
261 | { TYPE (INSN_STOS_INDIRECT_INDEX), IDX (INSN_STOS_INDIRECT_INDEX), FULL (stos_indirect_index) FAST (stos_indirect_index) }, | |
262 | { TYPE (INSN_STOS_DISP), IDX (INSN_STOS_DISP), FULL (stos_disp) FAST (stos_disp) }, | |
263 | { TYPE (INSN_STOS_INDIRECT_DISP), IDX (INSN_STOS_INDIRECT_DISP), FULL (stos_indirect_disp) FAST (stos_indirect_disp) }, | |
264 | { TYPE (INSN_STOS_INDEX_DISP), IDX (INSN_STOS_INDEX_DISP), FULL (stos_index_disp) FAST (stos_index_disp) }, | |
265 | { TYPE (INSN_STOS_INDIRECT_INDEX_DISP), IDX (INSN_STOS_INDIRECT_INDEX_DISP), FULL (stos_indirect_index_disp) FAST (stos_indirect_index_disp) }, | |
266 | { TYPE (INSN_STL_OFFSET), IDX (INSN_STL_OFFSET), FULL (stl_offset) FAST (stl_offset) }, | |
267 | { TYPE (INSN_STL_INDIRECT_OFFSET), IDX (INSN_STL_INDIRECT_OFFSET), FULL (stl_indirect_offset) FAST (stl_indirect_offset) }, | |
268 | { TYPE (INSN_STL_INDIRECT), IDX (INSN_STL_INDIRECT), FULL (stl_indirect) FAST (stl_indirect) }, | |
269 | { TYPE (INSN_STL_INDIRECT_INDEX), IDX (INSN_STL_INDIRECT_INDEX), FULL (stl_indirect_index) FAST (stl_indirect_index) }, | |
270 | { TYPE (INSN_STL_DISP), IDX (INSN_STL_DISP), FULL (stl_disp) FAST (stl_disp) }, | |
271 | { TYPE (INSN_STL_INDIRECT_DISP), IDX (INSN_STL_INDIRECT_DISP), FULL (stl_indirect_disp) FAST (stl_indirect_disp) }, | |
272 | { TYPE (INSN_STL_INDEX_DISP), IDX (INSN_STL_INDEX_DISP), FULL (stl_index_disp) FAST (stl_index_disp) }, | |
273 | { TYPE (INSN_STL_INDIRECT_INDEX_DISP), IDX (INSN_STL_INDIRECT_INDEX_DISP), FULL (stl_indirect_index_disp) FAST (stl_indirect_index_disp) }, | |
274 | { TYPE (INSN_STT_OFFSET), IDX (INSN_STT_OFFSET), FULL (stt_offset) FAST (stt_offset) }, | |
275 | { TYPE (INSN_STT_INDIRECT_OFFSET), IDX (INSN_STT_INDIRECT_OFFSET), FULL (stt_indirect_offset) FAST (stt_indirect_offset) }, | |
276 | { TYPE (INSN_STT_INDIRECT), IDX (INSN_STT_INDIRECT), FULL (stt_indirect) FAST (stt_indirect) }, | |
277 | { TYPE (INSN_STT_INDIRECT_INDEX), IDX (INSN_STT_INDIRECT_INDEX), FULL (stt_indirect_index) FAST (stt_indirect_index) }, | |
278 | { TYPE (INSN_STT_DISP), IDX (INSN_STT_DISP), FULL (stt_disp) FAST (stt_disp) }, | |
279 | { TYPE (INSN_STT_INDIRECT_DISP), IDX (INSN_STT_INDIRECT_DISP), FULL (stt_indirect_disp) FAST (stt_indirect_disp) }, | |
280 | { TYPE (INSN_STT_INDEX_DISP), IDX (INSN_STT_INDEX_DISP), FULL (stt_index_disp) FAST (stt_index_disp) }, | |
281 | { TYPE (INSN_STT_INDIRECT_INDEX_DISP), IDX (INSN_STT_INDIRECT_INDEX_DISP), FULL (stt_indirect_index_disp) FAST (stt_indirect_index_disp) }, | |
282 | { TYPE (INSN_STQ_OFFSET), IDX (INSN_STQ_OFFSET), FULL (stq_offset) FAST (stq_offset) }, | |
283 | { TYPE (INSN_STQ_INDIRECT_OFFSET), IDX (INSN_STQ_INDIRECT_OFFSET), FULL (stq_indirect_offset) FAST (stq_indirect_offset) }, | |
284 | { TYPE (INSN_STQ_INDIRECT), IDX (INSN_STQ_INDIRECT), FULL (stq_indirect) FAST (stq_indirect) }, | |
285 | { TYPE (INSN_STQ_INDIRECT_INDEX), IDX (INSN_STQ_INDIRECT_INDEX), FULL (stq_indirect_index) FAST (stq_indirect_index) }, | |
286 | { TYPE (INSN_STQ_DISP), IDX (INSN_STQ_DISP), FULL (stq_disp) FAST (stq_disp) }, | |
287 | { TYPE (INSN_STQ_INDIRECT_DISP), IDX (INSN_STQ_INDIRECT_DISP), FULL (stq_indirect_disp) FAST (stq_indirect_disp) }, | |
288 | { TYPE (INSN_STQ_INDEX_DISP), IDX (INSN_STQ_INDEX_DISP), FULL (stq_index_disp) FAST (stq_index_disp) }, | |
289 | { TYPE (INSN_STQ_INDIRECT_INDEX_DISP), IDX (INSN_STQ_INDIRECT_INDEX_DISP), FULL (stq_indirect_index_disp) FAST (stq_indirect_index_disp) }, | |
290 | { TYPE (INSN_CMPOBE_REG), IDX (INSN_CMPOBE_REG), FULL (cmpobe_reg) FAST (cmpobe_reg) }, | |
291 | { TYPE (INSN_CMPOBE_LIT), IDX (INSN_CMPOBE_LIT), FULL (cmpobe_lit) FAST (cmpobe_lit) }, | |
292 | { TYPE (INSN_CMPOBNE_REG), IDX (INSN_CMPOBNE_REG), FULL (cmpobne_reg) FAST (cmpobne_reg) }, | |
293 | { TYPE (INSN_CMPOBNE_LIT), IDX (INSN_CMPOBNE_LIT), FULL (cmpobne_lit) FAST (cmpobne_lit) }, | |
294 | { TYPE (INSN_CMPOBL_REG), IDX (INSN_CMPOBL_REG), FULL (cmpobl_reg) FAST (cmpobl_reg) }, | |
295 | { TYPE (INSN_CMPOBL_LIT), IDX (INSN_CMPOBL_LIT), FULL (cmpobl_lit) FAST (cmpobl_lit) }, | |
296 | { TYPE (INSN_CMPOBLE_REG), IDX (INSN_CMPOBLE_REG), FULL (cmpoble_reg) FAST (cmpoble_reg) }, | |
297 | { TYPE (INSN_CMPOBLE_LIT), IDX (INSN_CMPOBLE_LIT), FULL (cmpoble_lit) FAST (cmpoble_lit) }, | |
298 | { TYPE (INSN_CMPOBG_REG), IDX (INSN_CMPOBG_REG), FULL (cmpobg_reg) FAST (cmpobg_reg) }, | |
299 | { TYPE (INSN_CMPOBG_LIT), IDX (INSN_CMPOBG_LIT), FULL (cmpobg_lit) FAST (cmpobg_lit) }, | |
300 | { TYPE (INSN_CMPOBGE_REG), IDX (INSN_CMPOBGE_REG), FULL (cmpobge_reg) FAST (cmpobge_reg) }, | |
301 | { TYPE (INSN_CMPOBGE_LIT), IDX (INSN_CMPOBGE_LIT), FULL (cmpobge_lit) FAST (cmpobge_lit) }, | |
302 | { TYPE (INSN_CMPIBE_REG), IDX (INSN_CMPIBE_REG), FULL (cmpibe_reg) FAST (cmpibe_reg) }, | |
303 | { TYPE (INSN_CMPIBE_LIT), IDX (INSN_CMPIBE_LIT), FULL (cmpibe_lit) FAST (cmpibe_lit) }, | |
304 | { TYPE (INSN_CMPIBNE_REG), IDX (INSN_CMPIBNE_REG), FULL (cmpibne_reg) FAST (cmpibne_reg) }, | |
305 | { TYPE (INSN_CMPIBNE_LIT), IDX (INSN_CMPIBNE_LIT), FULL (cmpibne_lit) FAST (cmpibne_lit) }, | |
306 | { TYPE (INSN_CMPIBL_REG), IDX (INSN_CMPIBL_REG), FULL (cmpibl_reg) FAST (cmpibl_reg) }, | |
307 | { TYPE (INSN_CMPIBL_LIT), IDX (INSN_CMPIBL_LIT), FULL (cmpibl_lit) FAST (cmpibl_lit) }, | |
308 | { TYPE (INSN_CMPIBLE_REG), IDX (INSN_CMPIBLE_REG), FULL (cmpible_reg) FAST (cmpible_reg) }, | |
309 | { TYPE (INSN_CMPIBLE_LIT), IDX (INSN_CMPIBLE_LIT), FULL (cmpible_lit) FAST (cmpible_lit) }, | |
310 | { TYPE (INSN_CMPIBG_REG), IDX (INSN_CMPIBG_REG), FULL (cmpibg_reg) FAST (cmpibg_reg) }, | |
311 | { TYPE (INSN_CMPIBG_LIT), IDX (INSN_CMPIBG_LIT), FULL (cmpibg_lit) FAST (cmpibg_lit) }, | |
312 | { TYPE (INSN_CMPIBGE_REG), IDX (INSN_CMPIBGE_REG), FULL (cmpibge_reg) FAST (cmpibge_reg) }, | |
313 | { TYPE (INSN_CMPIBGE_LIT), IDX (INSN_CMPIBGE_LIT), FULL (cmpibge_lit) FAST (cmpibge_lit) }, | |
314 | { TYPE (INSN_BBC_REG), IDX (INSN_BBC_REG), FULL (bbc_reg) FAST (bbc_reg) }, | |
315 | { TYPE (INSN_BBC_LIT), IDX (INSN_BBC_LIT), FULL (bbc_lit) FAST (bbc_lit) }, | |
316 | { TYPE (INSN_BBS_REG), IDX (INSN_BBS_REG), FULL (bbs_reg) FAST (bbs_reg) }, | |
317 | { TYPE (INSN_BBS_LIT), IDX (INSN_BBS_LIT), FULL (bbs_lit) FAST (bbs_lit) }, | |
318 | { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) }, | |
319 | { TYPE (INSN_CMPI1), IDX (INSN_CMPI1), FULL (cmpi1) FAST (cmpi1) }, | |
320 | { TYPE (INSN_CMPI2), IDX (INSN_CMPI2), FULL (cmpi2) FAST (cmpi2) }, | |
321 | { TYPE (INSN_CMPI3), IDX (INSN_CMPI3), FULL (cmpi3) FAST (cmpi3) }, | |
322 | { TYPE (INSN_CMPO), IDX (INSN_CMPO), FULL (cmpo) FAST (cmpo) }, | |
323 | { TYPE (INSN_CMPO1), IDX (INSN_CMPO1), FULL (cmpo1) FAST (cmpo1) }, | |
324 | { TYPE (INSN_CMPO2), IDX (INSN_CMPO2), FULL (cmpo2) FAST (cmpo2) }, | |
325 | { TYPE (INSN_CMPO3), IDX (INSN_CMPO3), FULL (cmpo3) FAST (cmpo3) }, | |
326 | { TYPE (INSN_TESTNO_REG), IDX (INSN_TESTNO_REG), FULL (testno_reg) FAST (testno_reg) }, | |
327 | { TYPE (INSN_TESTG_REG), IDX (INSN_TESTG_REG), FULL (testg_reg) FAST (testg_reg) }, | |
328 | { TYPE (INSN_TESTE_REG), IDX (INSN_TESTE_REG), FULL (teste_reg) FAST (teste_reg) }, | |
329 | { TYPE (INSN_TESTGE_REG), IDX (INSN_TESTGE_REG), FULL (testge_reg) FAST (testge_reg) }, | |
330 | { TYPE (INSN_TESTL_REG), IDX (INSN_TESTL_REG), FULL (testl_reg) FAST (testl_reg) }, | |
331 | { TYPE (INSN_TESTNE_REG), IDX (INSN_TESTNE_REG), FULL (testne_reg) FAST (testne_reg) }, | |
332 | { TYPE (INSN_TESTLE_REG), IDX (INSN_TESTLE_REG), FULL (testle_reg) FAST (testle_reg) }, | |
333 | { TYPE (INSN_TESTO_REG), IDX (INSN_TESTO_REG), FULL (testo_reg) FAST (testo_reg) }, | |
334 | { TYPE (INSN_BNO), IDX (INSN_BNO), FULL (bno) FAST (bno) }, | |
335 | { TYPE (INSN_BG), IDX (INSN_BG), FULL (bg) FAST (bg) }, | |
336 | { TYPE (INSN_BE), IDX (INSN_BE), FULL (be) FAST (be) }, | |
337 | { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) }, | |
338 | { TYPE (INSN_BL), IDX (INSN_BL), FULL (bl) FAST (bl) }, | |
339 | { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, | |
340 | { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) }, | |
341 | { TYPE (INSN_BO), IDX (INSN_BO), FULL (bo) FAST (bo) }, | |
342 | { TYPE (INSN_B), IDX (INSN_B), FULL (b) FAST (b) }, | |
343 | { TYPE (INSN_BX_INDIRECT_OFFSET), IDX (INSN_BX_INDIRECT_OFFSET), FULL (bx_indirect_offset) FAST (bx_indirect_offset) }, | |
344 | { TYPE (INSN_BX_INDIRECT), IDX (INSN_BX_INDIRECT), FULL (bx_indirect) FAST (bx_indirect) }, | |
345 | { TYPE (INSN_BX_INDIRECT_INDEX), IDX (INSN_BX_INDIRECT_INDEX), FULL (bx_indirect_index) FAST (bx_indirect_index) }, | |
346 | { TYPE (INSN_BX_DISP), IDX (INSN_BX_DISP), FULL (bx_disp) FAST (bx_disp) }, | |
347 | { TYPE (INSN_BX_INDIRECT_DISP), IDX (INSN_BX_INDIRECT_DISP), FULL (bx_indirect_disp) FAST (bx_indirect_disp) }, | |
348 | { TYPE (INSN_CALLX_DISP), IDX (INSN_CALLX_DISP), FULL (callx_disp) FAST (callx_disp) }, | |
349 | { TYPE (INSN_CALLX_INDIRECT), IDX (INSN_CALLX_INDIRECT), FULL (callx_indirect) FAST (callx_indirect) }, | |
350 | { TYPE (INSN_CALLX_INDIRECT_OFFSET), IDX (INSN_CALLX_INDIRECT_OFFSET), FULL (callx_indirect_offset) FAST (callx_indirect_offset) }, | |
351 | { TYPE (INSN_RET), IDX (INSN_RET), FULL (ret) FAST (ret) }, | |
352 | { TYPE (INSN_CALLS), IDX (INSN_CALLS), FULL (calls) FAST (calls) }, | |
353 | { TYPE (INSN_FMARK), IDX (INSN_FMARK), FULL (fmark) FAST (fmark) }, | |
354 | { TYPE (INSN_FLUSHREG), IDX (INSN_FLUSHREG), FULL (flushreg) FAST (flushreg) }, | |
355 | }; | |
356 | ||
357 | static const struct insn_sem i960base_insn_sem_invalid = | |
358 | { | |
359 | VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) | |
360 | }; | |
361 | ||
362 | #undef IDX | |
363 | #undef TYPE | |
364 | ||
365 | /* Initialize an IDESC from the compile-time computable parts. */ | |
366 | ||
367 | static INLINE void | |
368 | init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) | |
369 | { | |
370 | const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; | |
371 | ||
372 | id->num = t->index; | |
373 | if ((int) t->type <= 0) | |
374 | id->idata = & cgen_virtual_insn_table[- (int) t->type]; | |
375 | else | |
376 | id->idata = & insn_table[t->type]; | |
377 | id->attrs = CGEN_INSN_ATTRS (id->idata); | |
378 | /* Oh my god, a magic number. */ | |
379 | id->length = CGEN_INSN_BITSIZE (id->idata) / 8; | |
380 | #if ! WITH_SEM_SWITCH_FULL | |
381 | id->sem_full = t->sem_full; | |
382 | #endif | |
383 | #if WITH_FAST && ! WITH_SEM_SWITCH_FAST | |
384 | id->sem_fast = t->sem_fast; | |
385 | #endif | |
386 | #if WITH_PROFILE_MODEL_P | |
387 | id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; | |
388 | { | |
389 | SIM_DESC sd = CPU_STATE (cpu); | |
390 | SIM_ASSERT (t->index == id->timing->num); | |
391 | } | |
392 | #endif | |
393 | } | |
394 | ||
395 | /* Initialize the instruction descriptor table. */ | |
396 | ||
397 | void | |
398 | i960base_init_idesc_table (SIM_CPU *cpu) | |
399 | { | |
400 | IDESC *id,*tabend; | |
401 | const struct insn_sem *t,*tend; | |
402 | int tabsize = I960BASE_INSN_MAX; | |
403 | IDESC *table = i960base_insn_data; | |
404 | ||
405 | memset (table, 0, tabsize * sizeof (IDESC)); | |
406 | ||
407 | /* First set all entries to the `invalid insn'. */ | |
408 | t = & i960base_insn_sem_invalid; | |
409 | for (id = table, tabend = table + tabsize; id < tabend; ++id) | |
410 | init_idesc (cpu, id, t); | |
411 | ||
412 | /* Now fill in the values for the chosen cpu. */ | |
413 | for (t = i960base_insn_sem, tend = t + sizeof (i960base_insn_sem) / sizeof (*t); | |
414 | t != tend; ++t) | |
415 | { | |
416 | init_idesc (cpu, & table[t->index], t); | |
417 | } | |
418 | ||
419 | /* Link the IDESC table into the cpu. */ | |
420 | CPU_IDESC (cpu) = table; | |
421 | } | |
422 | ||
423 | /* Enum declaration for all instruction semantic formats. */ | |
424 | typedef enum sfmt { | |
425 | FMT_EMPTY, FMT_MULO, FMT_MULO1, FMT_MULO2 | |
426 | , FMT_MULO3, FMT_NOTBIT, FMT_NOTBIT1, FMT_NOTBIT2 | |
427 | , FMT_NOTBIT3, FMT_NOT, FMT_NOT1, FMT_NOT2 | |
428 | , FMT_NOT3, FMT_EMUL, FMT_EMUL1, FMT_EMUL2 | |
429 | , FMT_EMUL3, FMT_MOVL, FMT_MOVL1, FMT_MOVT | |
430 | , FMT_MOVT1, FMT_MOVQ, FMT_MOVQ1, FMT_MODPC | |
431 | , FMT_LDA_OFFSET, FMT_LDA_INDIRECT_OFFSET, FMT_LDA_INDIRECT, FMT_LDA_INDIRECT_INDEX | |
432 | , FMT_LDA_DISP, FMT_LDA_INDIRECT_DISP, FMT_LDA_INDEX_DISP, FMT_LDA_INDIRECT_INDEX_DISP | |
433 | , FMT_LD_OFFSET, FMT_LD_INDIRECT_OFFSET, FMT_LD_INDIRECT, FMT_LD_INDIRECT_INDEX | |
434 | , FMT_LD_DISP, FMT_LD_INDIRECT_DISP, FMT_LD_INDEX_DISP, FMT_LD_INDIRECT_INDEX_DISP | |
435 | , FMT_LDOB_OFFSET, FMT_LDOB_INDIRECT_OFFSET, FMT_LDOB_INDIRECT, FMT_LDOB_INDIRECT_INDEX | |
436 | , FMT_LDOB_DISP, FMT_LDOB_INDIRECT_DISP, FMT_LDOB_INDEX_DISP, FMT_LDOB_INDIRECT_INDEX_DISP | |
437 | , FMT_LDOS_OFFSET, FMT_LDOS_INDIRECT_OFFSET, FMT_LDOS_INDIRECT, FMT_LDOS_INDIRECT_INDEX | |
438 | , FMT_LDOS_DISP, FMT_LDOS_INDIRECT_DISP, FMT_LDOS_INDEX_DISP, FMT_LDOS_INDIRECT_INDEX_DISP | |
439 | , FMT_LDIB_OFFSET, FMT_LDIB_INDIRECT_OFFSET, FMT_LDIB_INDIRECT, FMT_LDIB_INDIRECT_INDEX | |
440 | , FMT_LDIB_DISP, FMT_LDIB_INDIRECT_DISP, FMT_LDIB_INDEX_DISP, FMT_LDIB_INDIRECT_INDEX_DISP | |
441 | , FMT_LDIS_OFFSET, FMT_LDIS_INDIRECT_OFFSET, FMT_LDIS_INDIRECT, FMT_LDIS_INDIRECT_INDEX | |
442 | , FMT_LDIS_DISP, FMT_LDIS_INDIRECT_DISP, FMT_LDIS_INDEX_DISP, FMT_LDIS_INDIRECT_INDEX_DISP | |
443 | , FMT_LDL_OFFSET, FMT_LDL_INDIRECT_OFFSET, FMT_LDL_INDIRECT, FMT_LDL_INDIRECT_INDEX | |
444 | , FMT_LDL_DISP, FMT_LDL_INDIRECT_DISP, FMT_LDL_INDEX_DISP, FMT_LDL_INDIRECT_INDEX_DISP | |
445 | , FMT_LDT_OFFSET, FMT_LDT_INDIRECT_OFFSET, FMT_LDT_INDIRECT, FMT_LDT_INDIRECT_INDEX | |
446 | , FMT_LDT_DISP, FMT_LDT_INDIRECT_DISP, FMT_LDT_INDEX_DISP, FMT_LDT_INDIRECT_INDEX_DISP | |
447 | , FMT_LDQ_OFFSET, FMT_LDQ_INDIRECT_OFFSET, FMT_LDQ_INDIRECT, FMT_LDQ_INDIRECT_INDEX | |
448 | , FMT_LDQ_DISP, FMT_LDQ_INDIRECT_DISP, FMT_LDQ_INDEX_DISP, FMT_LDQ_INDIRECT_INDEX_DISP | |
449 | , FMT_ST_OFFSET, FMT_ST_INDIRECT_OFFSET, FMT_ST_INDIRECT, FMT_ST_INDIRECT_INDEX | |
450 | , FMT_ST_DISP, FMT_ST_INDIRECT_DISP, FMT_ST_INDEX_DISP, FMT_ST_INDIRECT_INDEX_DISP | |
451 | , FMT_STOB_OFFSET, FMT_STOB_INDIRECT_OFFSET, FMT_STOB_INDIRECT, FMT_STOB_INDIRECT_INDEX | |
452 | , FMT_STOB_DISP, FMT_STOB_INDIRECT_DISP, FMT_STOB_INDEX_DISP, FMT_STOB_INDIRECT_INDEX_DISP | |
453 | , FMT_STOS_OFFSET, FMT_STOS_INDIRECT_OFFSET, FMT_STOS_INDIRECT, FMT_STOS_INDIRECT_INDEX | |
454 | , FMT_STOS_DISP, FMT_STOS_INDIRECT_DISP, FMT_STOS_INDEX_DISP, FMT_STOS_INDIRECT_INDEX_DISP | |
455 | , FMT_STL_OFFSET, FMT_STL_INDIRECT_OFFSET, FMT_STL_INDIRECT, FMT_STL_INDIRECT_INDEX | |
456 | , FMT_STL_DISP, FMT_STL_INDIRECT_DISP, FMT_STL_INDEX_DISP, FMT_STL_INDIRECT_INDEX_DISP | |
457 | , FMT_STT_OFFSET, FMT_STT_INDIRECT_OFFSET, FMT_STT_INDIRECT, FMT_STT_INDIRECT_INDEX | |
458 | , FMT_STT_DISP, FMT_STT_INDIRECT_DISP, FMT_STT_INDEX_DISP, FMT_STT_INDIRECT_INDEX_DISP | |
459 | , FMT_STQ_OFFSET, FMT_STQ_INDIRECT_OFFSET, FMT_STQ_INDIRECT, FMT_STQ_INDIRECT_INDEX | |
460 | , FMT_STQ_DISP, FMT_STQ_INDIRECT_DISP, FMT_STQ_INDEX_DISP, FMT_STQ_INDIRECT_INDEX_DISP | |
461 | , FMT_CMPOBE_REG, FMT_CMPOBE_LIT, FMT_CMPOBL_REG, FMT_CMPOBL_LIT | |
462 | , FMT_BBC_REG, FMT_BBC_LIT, FMT_CMPI, FMT_CMPI1 | |
463 | , FMT_CMPI2, FMT_CMPI3, FMT_CMPO, FMT_CMPO1 | |
464 | , FMT_CMPO2, FMT_CMPO3, FMT_TESTNO_REG, FMT_BNO | |
465 | , FMT_B, FMT_BX_INDIRECT_OFFSET, FMT_BX_INDIRECT, FMT_BX_INDIRECT_INDEX | |
466 | , FMT_BX_DISP, FMT_BX_INDIRECT_DISP, FMT_CALLX_DISP, FMT_CALLX_INDIRECT | |
467 | , FMT_CALLX_INDIRECT_OFFSET, FMT_RET, FMT_CALLS, FMT_FMARK | |
468 | , FMT_FLUSHREG | |
469 | } SFMT; | |
470 | ||
471 | /* The decoder uses this to record insns and direct extraction handling. */ | |
472 | ||
473 | typedef struct { | |
474 | const IDESC *idesc; | |
475 | #ifdef __GNUC__ | |
476 | void *sfmt; | |
477 | #else | |
478 | enum sfmt sfmt; | |
479 | #endif | |
480 | } DECODE_DESC; | |
481 | ||
482 | /* Macro to go from decode phase to extraction phase. */ | |
483 | ||
484 | #ifdef __GNUC__ | |
485 | #define GOTO_EXTRACT(id) goto *(id)->sfmt | |
486 | #else | |
487 | #define GOTO_EXTRACT(id) goto extract | |
488 | #endif | |
489 | ||
490 | /* The decoder needs a slightly different computed goto switch control. */ | |
491 | #ifdef __GNUC__ | |
492 | #define DECODE_SWITCH(N, X) goto *labels_##N[X]; | |
493 | #else | |
494 | #define DECODE_SWITCH(N, X) switch (X) | |
495 | #endif | |
496 | ||
497 | /* Given an instruction, return a pointer to its IDESC entry. */ | |
498 | ||
499 | const IDESC * | |
500 | i960base_decode (SIM_CPU *current_cpu, IADDR pc, | |
501 | CGEN_INSN_INT base_insn, | |
502 | ARGBUF *abuf) | |
503 | { | |
504 | /* Result of decoder, used by extractor. */ | |
505 | const DECODE_DESC *idecode; | |
506 | ||
507 | /* First decode the instruction. */ | |
508 | ||
509 | { | |
510 | #define I(insn) & i960base_insn_data[CONCAT2 (I960BASE_,insn)] | |
511 | #ifdef __GNUC__ | |
512 | #define E(fmt) && case_ex_##fmt | |
513 | #else | |
514 | #define E(fmt) fmt | |
515 | #endif | |
516 | CGEN_INSN_INT insn = base_insn; | |
517 | static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) }; | |
518 | ||
519 | { | |
520 | #ifdef __GNUC__ | |
521 | static const void *labels_0[256] = { | |
522 | && default_0, && default_0, && default_0, && default_0, | |
523 | && default_0, && default_0, && default_0, && default_0, | |
524 | && default_0, && default_0, && default_0, && default_0, | |
525 | && default_0, && default_0, && default_0, && default_0, | |
526 | && default_0, && default_0, && default_0, && default_0, | |
527 | && default_0, && default_0, && default_0, && default_0, | |
528 | && default_0, && default_0, && default_0, && default_0, | |
529 | && default_0, && default_0, && default_0, && default_0, | |
530 | && default_0, && default_0, && default_0, && default_0, | |
531 | && default_0, && default_0, && default_0, && default_0, | |
532 | && default_0, && default_0, && default_0, && default_0, | |
533 | && default_0, && default_0, && default_0, && default_0, | |
534 | && case_0_48, && case_0_49, && case_0_50, && case_0_51, | |
535 | && case_0_52, && case_0_53, && case_0_54, && case_0_55, | |
536 | && default_0, && case_0_57, && case_0_58, && case_0_59, | |
537 | && case_0_60, && case_0_61, && case_0_62, && default_0, | |
538 | && default_0, && default_0, && default_0, && default_0, | |
539 | && default_0, && default_0, && default_0, && default_0, | |
540 | && default_0, && default_0, && default_0, && default_0, | |
541 | && default_0, && default_0, && default_0, && default_0, | |
542 | && default_0, && default_0, && default_0, && default_0, | |
543 | && default_0, && default_0, && default_0, && default_0, | |
544 | && case_0_88, && case_0_89, && case_0_90, && default_0, | |
545 | && case_0_92, && case_0_93, && case_0_94, && case_0_95, | |
546 | && default_0, && default_0, && default_0, && default_0, | |
547 | && default_0, && default_0, && case_0_102, && case_0_103, | |
548 | && default_0, && default_0, && default_0, && default_0, | |
549 | && default_0, && default_0, && default_0, && default_0, | |
550 | && case_0_112, && default_0, && default_0, && default_0, | |
551 | && case_0_116, && default_0, && default_0, && default_0, | |
552 | && default_0, && default_0, && default_0, && default_0, | |
553 | && default_0, && default_0, && default_0, && default_0, | |
554 | && case_0_128, && default_0, && case_0_130, && default_0, | |
555 | && case_0_132, && default_0, && case_0_134, && default_0, | |
556 | && case_0_136, && default_0, && case_0_138, && default_0, | |
557 | && case_0_140, && default_0, && default_0, && default_0, | |
558 | && case_0_144, && default_0, && case_0_146, && default_0, | |
559 | && default_0, && default_0, && default_0, && default_0, | |
560 | && case_0_152, && default_0, && case_0_154, && default_0, | |
561 | && default_0, && default_0, && default_0, && default_0, | |
562 | && case_0_160, && default_0, && case_0_162, && default_0, | |
563 | && default_0, && default_0, && default_0, && default_0, | |
564 | && default_0, && default_0, && default_0, && default_0, | |
565 | && default_0, && default_0, && default_0, && default_0, | |
566 | && case_0_176, && default_0, && case_0_178, && default_0, | |
567 | && default_0, && default_0, && default_0, && default_0, | |
568 | && default_0, && default_0, && default_0, && default_0, | |
569 | && default_0, && default_0, && default_0, && default_0, | |
570 | && case_0_192, && default_0, && default_0, && default_0, | |
571 | && default_0, && default_0, && default_0, && default_0, | |
572 | && case_0_200, && default_0, && default_0, && default_0, | |
573 | && default_0, && default_0, && default_0, && default_0, | |
574 | && default_0, && default_0, && default_0, && default_0, | |
575 | && default_0, && default_0, && default_0, && default_0, | |
576 | && default_0, && default_0, && default_0, && default_0, | |
577 | && default_0, && default_0, && default_0, && default_0, | |
578 | && default_0, && default_0, && default_0, && default_0, | |
579 | && default_0, && default_0, && default_0, && default_0, | |
580 | && default_0, && default_0, && default_0, && default_0, | |
581 | && default_0, && default_0, && default_0, && default_0, | |
582 | && default_0, && default_0, && default_0, && default_0, | |
583 | && default_0, && default_0, && default_0, && default_0, | |
584 | && default_0, && default_0, && default_0, && default_0, | |
585 | && default_0, && default_0, && default_0, && default_0, | |
586 | }; | |
587 | #endif | |
588 | static const DECODE_DESC insns[256] = { | |
589 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
590 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
591 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
592 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
593 | { I (INSN_B), E (FMT_B) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
594 | { I (INSN_RET), E (FMT_RET) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
595 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
596 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
597 | { I (INSN_BNO), E (FMT_BNO) }, { I (INSN_BG), E (FMT_BNO) }, | |
598 | { I (INSN_BE), E (FMT_BNO) }, { I (INSN_BGE), E (FMT_BNO) }, | |
599 | { I (INSN_BL), E (FMT_BNO) }, { I (INSN_BNE), E (FMT_BNO) }, | |
600 | { I (INSN_BLE), E (FMT_BNO) }, { I (INSN_BO), E (FMT_BNO) }, | |
601 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
602 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
603 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
604 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
605 | { I (INSN_TESTNO_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTG_REG), E (FMT_TESTNO_REG) }, | |
606 | { I (INSN_TESTE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTGE_REG), E (FMT_TESTNO_REG) }, | |
607 | { I (INSN_TESTL_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTNE_REG), E (FMT_TESTNO_REG) }, | |
608 | { I (INSN_TESTLE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTO_REG), E (FMT_TESTNO_REG) }, | |
609 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
610 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
611 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
612 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
613 | { 0 }, { 0 }, | |
614 | { 0 }, { 0 }, | |
615 | { 0 }, { 0 }, | |
616 | { 0 }, { 0 }, | |
617 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, | |
618 | { 0 }, { 0 }, | |
619 | { 0 }, { 0 }, | |
620 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
621 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
622 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
623 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
624 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
625 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
626 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
627 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
628 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
629 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
630 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
631 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
632 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
633 | { 0 }, { 0 }, | |
634 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
635 | { 0 }, { 0 }, | |
636 | { 0 }, { 0 }, | |
637 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
638 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
639 | { I (INSN_MODAC), E (FMT_MODPC) }, { I (INSN_MODPC), E (FMT_MODPC) }, | |
640 | { 0 }, { 0 }, | |
641 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
642 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
643 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
644 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
645 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
646 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
647 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
648 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
649 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
650 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
651 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
652 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
653 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
654 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
655 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
656 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
657 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
658 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
659 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
660 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
661 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
662 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
663 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
664 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
665 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
666 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
667 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
668 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
669 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
670 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
671 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
672 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
673 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
674 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
675 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
676 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
677 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
678 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
679 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
680 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
681 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
682 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
683 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
684 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
685 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
686 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
687 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
688 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
689 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
690 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
691 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
692 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
693 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
694 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
695 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
696 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
697 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
698 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
699 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
700 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
701 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
702 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
703 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
704 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
705 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
706 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
707 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
708 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
709 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
710 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
711 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
712 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
713 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
714 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
715 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
716 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
717 | }; | |
718 | unsigned int val; | |
719 | val = (((insn >> 24) & (255 << 0))); | |
720 | DECODE_SWITCH (0, val) | |
721 | { | |
722 | CASE (0, 48) : | |
723 | { | |
724 | static const DECODE_DESC insns[8] = { | |
725 | { I (INSN_BBC_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
726 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
727 | { I (INSN_BBC_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
728 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
729 | }; | |
730 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
731 | idecode = &insns[val]; | |
732 | GOTO_EXTRACT (idecode); | |
733 | } | |
734 | CASE (0, 49) : | |
735 | { | |
736 | static const DECODE_DESC insns[8] = { | |
737 | { I (INSN_CMPOBG_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
738 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
739 | { I (INSN_CMPOBG_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
740 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
741 | }; | |
742 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
743 | idecode = &insns[val]; | |
744 | GOTO_EXTRACT (idecode); | |
745 | } | |
746 | CASE (0, 50) : | |
747 | { | |
748 | static const DECODE_DESC insns[8] = { | |
749 | { I (INSN_CMPOBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
750 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
751 | { I (INSN_CMPOBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
752 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
753 | }; | |
754 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
755 | idecode = &insns[val]; | |
756 | GOTO_EXTRACT (idecode); | |
757 | } | |
758 | CASE (0, 51) : | |
759 | { | |
760 | static const DECODE_DESC insns[8] = { | |
761 | { I (INSN_CMPOBGE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
762 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
763 | { I (INSN_CMPOBGE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
764 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
765 | }; | |
766 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
767 | idecode = &insns[val]; | |
768 | GOTO_EXTRACT (idecode); | |
769 | } | |
770 | CASE (0, 52) : | |
771 | { | |
772 | static const DECODE_DESC insns[8] = { | |
773 | { I (INSN_CMPOBL_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
774 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
775 | { I (INSN_CMPOBL_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
776 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
777 | }; | |
778 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
779 | idecode = &insns[val]; | |
780 | GOTO_EXTRACT (idecode); | |
781 | } | |
782 | CASE (0, 53) : | |
783 | { | |
784 | static const DECODE_DESC insns[8] = { | |
785 | { I (INSN_CMPOBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
786 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
787 | { I (INSN_CMPOBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
788 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
789 | }; | |
790 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
791 | idecode = &insns[val]; | |
792 | GOTO_EXTRACT (idecode); | |
793 | } | |
794 | CASE (0, 54) : | |
795 | { | |
796 | static const DECODE_DESC insns[8] = { | |
797 | { I (INSN_CMPOBLE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
798 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
799 | { I (INSN_CMPOBLE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
800 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
801 | }; | |
802 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
803 | idecode = &insns[val]; | |
804 | GOTO_EXTRACT (idecode); | |
805 | } | |
806 | CASE (0, 55) : | |
807 | { | |
808 | static const DECODE_DESC insns[8] = { | |
809 | { I (INSN_BBS_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
810 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
811 | { I (INSN_BBS_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
812 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
813 | }; | |
814 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
815 | idecode = &insns[val]; | |
816 | GOTO_EXTRACT (idecode); | |
817 | } | |
818 | CASE (0, 57) : | |
819 | { | |
820 | static const DECODE_DESC insns[8] = { | |
821 | { I (INSN_CMPIBG_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
822 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
823 | { I (INSN_CMPIBG_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
824 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
825 | }; | |
826 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
827 | idecode = &insns[val]; | |
828 | GOTO_EXTRACT (idecode); | |
829 | } | |
830 | CASE (0, 58) : | |
831 | { | |
832 | static const DECODE_DESC insns[8] = { | |
833 | { I (INSN_CMPIBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
834 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
835 | { I (INSN_CMPIBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
836 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
837 | }; | |
838 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
839 | idecode = &insns[val]; | |
840 | GOTO_EXTRACT (idecode); | |
841 | } | |
842 | CASE (0, 59) : | |
843 | { | |
844 | static const DECODE_DESC insns[8] = { | |
845 | { I (INSN_CMPIBGE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
846 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
847 | { I (INSN_CMPIBGE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
848 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
849 | }; | |
850 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
851 | idecode = &insns[val]; | |
852 | GOTO_EXTRACT (idecode); | |
853 | } | |
854 | CASE (0, 60) : | |
855 | { | |
856 | static const DECODE_DESC insns[8] = { | |
857 | { I (INSN_CMPIBL_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
858 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
859 | { I (INSN_CMPIBL_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
860 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
861 | }; | |
862 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
863 | idecode = &insns[val]; | |
864 | GOTO_EXTRACT (idecode); | |
865 | } | |
866 | CASE (0, 61) : | |
867 | { | |
868 | static const DECODE_DESC insns[8] = { | |
869 | { I (INSN_CMPIBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
870 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
871 | { I (INSN_CMPIBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
872 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
873 | }; | |
874 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
875 | idecode = &insns[val]; | |
876 | GOTO_EXTRACT (idecode); | |
877 | } | |
878 | CASE (0, 62) : | |
879 | { | |
880 | static const DECODE_DESC insns[8] = { | |
881 | { I (INSN_CMPIBLE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
882 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
883 | { I (INSN_CMPIBLE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
884 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
885 | }; | |
886 | unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); | |
887 | idecode = &insns[val]; | |
888 | GOTO_EXTRACT (idecode); | |
889 | } | |
890 | CASE (0, 88) : | |
891 | { | |
892 | #ifdef __GNUC__ | |
893 | static const void *labels_0_88[16] = { | |
894 | && case_0_88_0, && case_0_88_1, && case_0_88_2, && case_0_88_3, | |
895 | && case_0_88_4, && case_0_88_5, && case_0_88_6, && case_0_88_7, | |
896 | && default_0_88, && default_0_88, && default_0_88, && default_0_88, | |
897 | && default_0_88, && default_0_88, && default_0_88, && default_0_88, | |
898 | }; | |
899 | #endif | |
900 | static const DECODE_DESC insns[16] = { | |
901 | { 0 }, { 0 }, | |
902 | { 0 }, { 0 }, | |
903 | { 0 }, { 0 }, | |
904 | { 0 }, { 0 }, | |
905 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
906 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
907 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
908 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
909 | }; | |
910 | unsigned int val; | |
911 | val = (((insn >> 10) & (15 << 0))); | |
912 | DECODE_SWITCH (0_88, val) | |
913 | { | |
914 | CASE (0_88, 0) : | |
915 | { | |
916 | static const DECODE_DESC insns[16] = { | |
917 | { I (INSN_NOTBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
918 | { I (INSN_AND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
919 | { I (INSN_ANDNOT), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
920 | { I (INSN_SETBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
921 | { I (INSN_NOTAND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
922 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
923 | { I (INSN_XOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
924 | { I (INSN_OR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
925 | }; | |
926 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
927 | idecode = &insns[val]; | |
928 | GOTO_EXTRACT (idecode); | |
929 | } | |
930 | CASE (0_88, 1) : | |
931 | { | |
932 | static const DECODE_DESC insns[16] = { | |
933 | { I (INSN_NOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
934 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
935 | { I (INSN_NOT), E (FMT_NOT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
936 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
937 | { I (INSN_CLRBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
938 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
939 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
940 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
941 | }; | |
942 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
943 | idecode = &insns[val]; | |
944 | GOTO_EXTRACT (idecode); | |
945 | } | |
946 | CASE (0_88, 2) : | |
947 | { | |
948 | static const DECODE_DESC insns[16] = { | |
949 | { I (INSN_NOTBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
950 | { I (INSN_AND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
951 | { I (INSN_ANDNOT1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
952 | { I (INSN_SETBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
953 | { I (INSN_NOTAND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
954 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
955 | { I (INSN_XOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
956 | { I (INSN_OR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
957 | }; | |
958 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
959 | idecode = &insns[val]; | |
960 | GOTO_EXTRACT (idecode); | |
961 | } | |
962 | CASE (0_88, 3) : | |
963 | { | |
964 | static const DECODE_DESC insns[16] = { | |
965 | { I (INSN_NOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
966 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
967 | { I (INSN_NOT1), E (FMT_NOT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
968 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
969 | { I (INSN_CLRBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
970 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
971 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
972 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
973 | }; | |
974 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
975 | idecode = &insns[val]; | |
976 | GOTO_EXTRACT (idecode); | |
977 | } | |
978 | CASE (0_88, 4) : | |
979 | { | |
980 | static const DECODE_DESC insns[16] = { | |
981 | { I (INSN_NOTBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
982 | { I (INSN_AND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
983 | { I (INSN_ANDNOT2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
984 | { I (INSN_SETBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
985 | { I (INSN_NOTAND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
986 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
987 | { I (INSN_XOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
988 | { I (INSN_OR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
989 | }; | |
990 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
991 | idecode = &insns[val]; | |
992 | GOTO_EXTRACT (idecode); | |
993 | } | |
994 | CASE (0_88, 5) : | |
995 | { | |
996 | static const DECODE_DESC insns[16] = { | |
997 | { I (INSN_NOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
998 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
999 | { I (INSN_NOT2), E (FMT_NOT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1000 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1001 | { I (INSN_CLRBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1002 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1003 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1004 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1005 | }; | |
1006 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1007 | idecode = &insns[val]; | |
1008 | GOTO_EXTRACT (idecode); | |
1009 | } | |
1010 | CASE (0_88, 6) : | |
1011 | { | |
1012 | static const DECODE_DESC insns[16] = { | |
1013 | { I (INSN_NOTBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1014 | { I (INSN_AND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1015 | { I (INSN_ANDNOT3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1016 | { I (INSN_SETBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1017 | { I (INSN_NOTAND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1018 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1019 | { I (INSN_XOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1020 | { I (INSN_OR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1021 | }; | |
1022 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1023 | idecode = &insns[val]; | |
1024 | GOTO_EXTRACT (idecode); | |
1025 | } | |
1026 | CASE (0_88, 7) : | |
1027 | { | |
1028 | static const DECODE_DESC insns[16] = { | |
1029 | { I (INSN_NOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1030 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1031 | { I (INSN_NOT3), E (FMT_NOT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1032 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1033 | { I (INSN_CLRBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1034 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1035 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1036 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1037 | }; | |
1038 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1039 | idecode = &insns[val]; | |
1040 | GOTO_EXTRACT (idecode); | |
1041 | } | |
1042 | DEFAULT (0_88) : | |
1043 | idecode = &insns[val]; | |
1044 | GOTO_EXTRACT (idecode); | |
1045 | } | |
1046 | ENDSWITCH (0_88) | |
1047 | } | |
1048 | CASE (0, 89) : | |
1049 | { | |
1050 | #ifdef __GNUC__ | |
1051 | static const void *labels_0_89[16] = { | |
1052 | && case_0_89_0, && case_0_89_1, && case_0_89_2, && case_0_89_3, | |
1053 | && case_0_89_4, && case_0_89_5, && case_0_89_6, && case_0_89_7, | |
1054 | && default_0_89, && default_0_89, && default_0_89, && default_0_89, | |
1055 | && default_0_89, && default_0_89, && default_0_89, && default_0_89, | |
1056 | }; | |
1057 | #endif | |
1058 | static const DECODE_DESC insns[16] = { | |
1059 | { 0 }, { 0 }, | |
1060 | { 0 }, { 0 }, | |
1061 | { 0 }, { 0 }, | |
1062 | { 0 }, { 0 }, | |
1063 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1064 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1065 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1066 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1067 | }; | |
1068 | unsigned int val; | |
1069 | val = (((insn >> 10) & (15 << 0))); | |
1070 | DECODE_SWITCH (0_89, val) | |
1071 | { | |
1072 | CASE (0_89, 0) : | |
1073 | { | |
1074 | static const DECODE_DESC insns[16] = { | |
1075 | { I (INSN_ADDO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1076 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1077 | { I (INSN_SUBO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1078 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1079 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1080 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1081 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1082 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1083 | }; | |
1084 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1085 | idecode = &insns[val]; | |
1086 | GOTO_EXTRACT (idecode); | |
1087 | } | |
1088 | CASE (0_89, 1) : | |
1089 | { | |
1090 | static const DECODE_DESC insns[16] = { | |
1091 | { I (INSN_SHRO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1092 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1093 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1094 | { I (INSN_SHRI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1095 | { I (INSN_SHLO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1096 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1097 | { I (INSN_SHLI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1098 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1099 | }; | |
1100 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1101 | idecode = &insns[val]; | |
1102 | GOTO_EXTRACT (idecode); | |
1103 | } | |
1104 | CASE (0_89, 2) : | |
1105 | { | |
1106 | static const DECODE_DESC insns[16] = { | |
1107 | { I (INSN_ADDO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1108 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1109 | { I (INSN_SUBO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1110 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1111 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1112 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1113 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1114 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1115 | }; | |
1116 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1117 | idecode = &insns[val]; | |
1118 | GOTO_EXTRACT (idecode); | |
1119 | } | |
1120 | CASE (0_89, 3) : | |
1121 | { | |
1122 | static const DECODE_DESC insns[16] = { | |
1123 | { I (INSN_SHRO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1124 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1125 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1126 | { I (INSN_SHRI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1127 | { I (INSN_SHLO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1128 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1129 | { I (INSN_SHLI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1130 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1131 | }; | |
1132 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1133 | idecode = &insns[val]; | |
1134 | GOTO_EXTRACT (idecode); | |
1135 | } | |
1136 | CASE (0_89, 4) : | |
1137 | { | |
1138 | static const DECODE_DESC insns[16] = { | |
1139 | { I (INSN_ADDO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1140 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1141 | { I (INSN_SUBO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1142 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1143 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1144 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1145 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1146 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1147 | }; | |
1148 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1149 | idecode = &insns[val]; | |
1150 | GOTO_EXTRACT (idecode); | |
1151 | } | |
1152 | CASE (0_89, 5) : | |
1153 | { | |
1154 | static const DECODE_DESC insns[16] = { | |
1155 | { I (INSN_SHRO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1156 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1157 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1158 | { I (INSN_SHRI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1159 | { I (INSN_SHLO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1160 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1161 | { I (INSN_SHLI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1162 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1163 | }; | |
1164 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1165 | idecode = &insns[val]; | |
1166 | GOTO_EXTRACT (idecode); | |
1167 | } | |
1168 | CASE (0_89, 6) : | |
1169 | { | |
1170 | static const DECODE_DESC insns[16] = { | |
1171 | { I (INSN_ADDO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1172 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1173 | { I (INSN_SUBO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1174 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1175 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1176 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1177 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1178 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1179 | }; | |
1180 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1181 | idecode = &insns[val]; | |
1182 | GOTO_EXTRACT (idecode); | |
1183 | } | |
1184 | CASE (0_89, 7) : | |
1185 | { | |
1186 | static const DECODE_DESC insns[16] = { | |
1187 | { I (INSN_SHRO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1188 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1189 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1190 | { I (INSN_SHRI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1191 | { I (INSN_SHLO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1192 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1193 | { I (INSN_SHLI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1194 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1195 | }; | |
1196 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1197 | idecode = &insns[val]; | |
1198 | GOTO_EXTRACT (idecode); | |
1199 | } | |
1200 | DEFAULT (0_89) : | |
1201 | idecode = &insns[val]; | |
1202 | GOTO_EXTRACT (idecode); | |
1203 | } | |
1204 | ENDSWITCH (0_89) | |
1205 | } | |
1206 | CASE (0, 90) : | |
1207 | { | |
1208 | #ifdef __GNUC__ | |
1209 | static const void *labels_0_90[16] = { | |
1210 | && default_0_90, && default_0_90, && default_0_90, && default_0_90, | |
1211 | && default_0_90, && default_0_90, && default_0_90, && default_0_90, | |
1212 | && case_0_90_8, && default_0_90, && case_0_90_10, && default_0_90, | |
1213 | && case_0_90_12, && default_0_90, && case_0_90_14, && default_0_90, | |
1214 | }; | |
1215 | #endif | |
1216 | static const DECODE_DESC insns[16] = { | |
1217 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1218 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1219 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1220 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1221 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1222 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1223 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1224 | { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1225 | }; | |
1226 | unsigned int val; | |
1227 | val = (((insn >> 10) & (15 << 0))); | |
1228 | DECODE_SWITCH (0_90, val) | |
1229 | { | |
1230 | CASE (0_90, 8) : | |
1231 | { | |
1232 | static const DECODE_DESC insns[16] = { | |
1233 | { I (INSN_CMPO), E (FMT_CMPO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1234 | { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1235 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1236 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1237 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1238 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1239 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1240 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1241 | }; | |
1242 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1243 | idecode = &insns[val]; | |
1244 | GOTO_EXTRACT (idecode); | |
1245 | } | |
1246 | CASE (0_90, 10) : | |
1247 | { | |
1248 | static const DECODE_DESC insns[16] = { | |
1249 | { I (INSN_CMPO1), E (FMT_CMPO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1250 | { I (INSN_CMPI1), E (FMT_CMPI1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1251 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1252 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1253 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1254 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1255 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1256 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1257 | }; | |
1258 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1259 | idecode = &insns[val]; | |
1260 | GOTO_EXTRACT (idecode); | |
1261 | } | |
1262 | CASE (0_90, 12) : | |
1263 | { | |
1264 | static const DECODE_DESC insns[16] = { | |
1265 | { I (INSN_CMPO2), E (FMT_CMPO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1266 | { I (INSN_CMPI2), E (FMT_CMPI2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1267 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1268 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1269 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1270 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1271 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1272 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1273 | }; | |
1274 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1275 | idecode = &insns[val]; | |
1276 | GOTO_EXTRACT (idecode); | |
1277 | } | |
1278 | CASE (0_90, 14) : | |
1279 | { | |
1280 | static const DECODE_DESC insns[16] = { | |
1281 | { I (INSN_CMPO3), E (FMT_CMPO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1282 | { I (INSN_CMPI3), E (FMT_CMPI3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1283 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1284 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1285 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1286 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1287 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1288 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1289 | }; | |
1290 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1291 | idecode = &insns[val]; | |
1292 | GOTO_EXTRACT (idecode); | |
1293 | } | |
1294 | DEFAULT (0_90) : | |
1295 | idecode = &insns[val]; | |
1296 | GOTO_EXTRACT (idecode); | |
1297 | } | |
1298 | ENDSWITCH (0_90) | |
1299 | } | |
1300 | CASE (0, 92) : | |
1301 | { | |
1302 | static const DECODE_DESC insns[16] = { | |
1303 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1304 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1305 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV), E (FMT_NOT2) }, | |
1306 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV1), E (FMT_NOT3) }, | |
1307 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1308 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1309 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1310 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1311 | }; | |
1312 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1313 | idecode = &insns[val]; | |
1314 | GOTO_EXTRACT (idecode); | |
1315 | } | |
1316 | CASE (0, 93) : | |
1317 | { | |
1318 | static const DECODE_DESC insns[16] = { | |
1319 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1320 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1321 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL), E (FMT_MOVL) }, | |
1322 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL1), E (FMT_MOVL1) }, | |
1323 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1324 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1325 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1326 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1327 | }; | |
1328 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1329 | idecode = &insns[val]; | |
1330 | GOTO_EXTRACT (idecode); | |
1331 | } | |
1332 | CASE (0, 94) : | |
1333 | { | |
1334 | static const DECODE_DESC insns[16] = { | |
1335 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1336 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1337 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT), E (FMT_MOVT) }, | |
1338 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT1), E (FMT_MOVT1) }, | |
1339 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1340 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1341 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1342 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1343 | }; | |
1344 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1345 | idecode = &insns[val]; | |
1346 | GOTO_EXTRACT (idecode); | |
1347 | } | |
1348 | CASE (0, 95) : | |
1349 | { | |
1350 | static const DECODE_DESC insns[16] = { | |
1351 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1352 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1353 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ), E (FMT_MOVQ) }, | |
1354 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ1), E (FMT_MOVQ1) }, | |
1355 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1356 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1357 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1358 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1359 | }; | |
1360 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1361 | idecode = &insns[val]; | |
1362 | GOTO_EXTRACT (idecode); | |
1363 | } | |
1364 | CASE (0, 102) : | |
1365 | { | |
1366 | #ifdef __GNUC__ | |
1367 | static const void *labels_0_102[16] = { | |
1368 | && default_0_102, && default_0_102, && default_0_102, && default_0_102, | |
1369 | && default_0_102, && default_0_102, && default_0_102, && default_0_102, | |
1370 | && default_0_102, && default_0_102, && default_0_102, && default_0_102, | |
1371 | && default_0_102, && default_0_102, && default_0_102, && case_0_102_15, | |
1372 | }; | |
1373 | #endif | |
1374 | static const DECODE_DESC insns[16] = { | |
1375 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1376 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1377 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1378 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1379 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1380 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1381 | { I (INSN_CALLS), E (FMT_CALLS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1382 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, | |
1383 | }; | |
1384 | unsigned int val; | |
1385 | val = (((insn >> 10) & (15 << 0))); | |
1386 | DECODE_SWITCH (0_102, val) | |
1387 | { | |
1388 | CASE (0_102, 15) : | |
1389 | { | |
1390 | static const DECODE_DESC insns[16] = { | |
1391 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1392 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1393 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1394 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1395 | { I (INSN_FMARK), E (FMT_FMARK) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1396 | { I (INSN_FLUSHREG), E (FMT_FLUSHREG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1397 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1398 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1399 | }; | |
1400 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1401 | idecode = &insns[val]; | |
1402 | GOTO_EXTRACT (idecode); | |
1403 | } | |
1404 | DEFAULT (0_102) : | |
1405 | idecode = &insns[val]; | |
1406 | GOTO_EXTRACT (idecode); | |
1407 | } | |
1408 | ENDSWITCH (0_102) | |
1409 | } | |
1410 | CASE (0, 103) : | |
1411 | { | |
1412 | static const DECODE_DESC insns[16] = { | |
1413 | { I (INSN_EMUL), E (FMT_EMUL) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1414 | { I (INSN_EMUL1), E (FMT_EMUL1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1415 | { I (INSN_EMUL2), E (FMT_EMUL2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1416 | { I (INSN_EMUL3), E (FMT_EMUL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1417 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1418 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1419 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1420 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1421 | }; | |
1422 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1423 | idecode = &insns[val]; | |
1424 | GOTO_EXTRACT (idecode); | |
1425 | } | |
1426 | CASE (0, 112) : | |
1427 | { | |
1428 | #ifdef __GNUC__ | |
1429 | static const void *labels_0_112[16] = { | |
1430 | && default_0_112, && case_0_112_1, && default_0_112, && case_0_112_3, | |
1431 | && default_0_112, && case_0_112_5, && default_0_112, && case_0_112_7, | |
1432 | && default_0_112, && default_0_112, && default_0_112, && default_0_112, | |
1433 | && default_0_112, && default_0_112, && default_0_112, && default_0_112, | |
1434 | }; | |
1435 | #endif | |
1436 | static const DECODE_DESC insns[16] = { | |
1437 | { I (INSN_MULO), E (FMT_MULO) }, { 0 }, | |
1438 | { I (INSN_MULO1), E (FMT_MULO1) }, { 0 }, | |
1439 | { I (INSN_MULO2), E (FMT_MULO2) }, { 0 }, | |
1440 | { I (INSN_MULO3), E (FMT_MULO3) }, { 0 }, | |
1441 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1442 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1443 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1444 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1445 | }; | |
1446 | unsigned int val; | |
1447 | val = (((insn >> 10) & (15 << 0))); | |
1448 | DECODE_SWITCH (0_112, val) | |
1449 | { | |
1450 | CASE (0_112, 1) : | |
1451 | { | |
1452 | static const DECODE_DESC insns[16] = { | |
1453 | { I (INSN_REMO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1454 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1455 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1456 | { I (INSN_DIVO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1457 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1458 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1459 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1460 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1461 | }; | |
1462 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1463 | idecode = &insns[val]; | |
1464 | GOTO_EXTRACT (idecode); | |
1465 | } | |
1466 | CASE (0_112, 3) : | |
1467 | { | |
1468 | static const DECODE_DESC insns[16] = { | |
1469 | { I (INSN_REMO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1470 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1471 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1472 | { I (INSN_DIVO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1473 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1474 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1475 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1476 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1477 | }; | |
1478 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1479 | idecode = &insns[val]; | |
1480 | GOTO_EXTRACT (idecode); | |
1481 | } | |
1482 | CASE (0_112, 5) : | |
1483 | { | |
1484 | static const DECODE_DESC insns[16] = { | |
1485 | { I (INSN_REMO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1486 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1487 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1488 | { I (INSN_DIVO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1489 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1490 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1491 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1492 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1493 | }; | |
1494 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1495 | idecode = &insns[val]; | |
1496 | GOTO_EXTRACT (idecode); | |
1497 | } | |
1498 | CASE (0_112, 7) : | |
1499 | { | |
1500 | static const DECODE_DESC insns[16] = { | |
1501 | { I (INSN_REMO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1502 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1503 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1504 | { I (INSN_DIVO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1505 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1506 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1507 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1508 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1509 | }; | |
1510 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1511 | idecode = &insns[val]; | |
1512 | GOTO_EXTRACT (idecode); | |
1513 | } | |
1514 | DEFAULT (0_112) : | |
1515 | idecode = &insns[val]; | |
1516 | GOTO_EXTRACT (idecode); | |
1517 | } | |
1518 | ENDSWITCH (0_112) | |
1519 | } | |
1520 | CASE (0, 116) : | |
1521 | { | |
1522 | #ifdef __GNUC__ | |
1523 | static const void *labels_0_116[16] = { | |
1524 | && default_0_116, && case_0_116_1, && default_0_116, && case_0_116_3, | |
1525 | && default_0_116, && case_0_116_5, && default_0_116, && case_0_116_7, | |
1526 | && default_0_116, && default_0_116, && default_0_116, && default_0_116, | |
1527 | && default_0_116, && default_0_116, && default_0_116, && default_0_116, | |
1528 | }; | |
1529 | #endif | |
1530 | static const DECODE_DESC insns[16] = { | |
1531 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, | |
1532 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, | |
1533 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, | |
1534 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, | |
1535 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1536 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1537 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1538 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1539 | }; | |
1540 | unsigned int val; | |
1541 | val = (((insn >> 10) & (15 << 0))); | |
1542 | DECODE_SWITCH (0_116, val) | |
1543 | { | |
1544 | CASE (0_116, 1) : | |
1545 | { | |
1546 | static const DECODE_DESC insns[16] = { | |
1547 | { I (INSN_REMI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1548 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1549 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1550 | { I (INSN_DIVI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1551 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1552 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1553 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1554 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1555 | }; | |
1556 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1557 | idecode = &insns[val]; | |
1558 | GOTO_EXTRACT (idecode); | |
1559 | } | |
1560 | CASE (0_116, 3) : | |
1561 | { | |
1562 | static const DECODE_DESC insns[16] = { | |
1563 | { I (INSN_REMI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1564 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1565 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1566 | { I (INSN_DIVI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1567 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1568 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1569 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1570 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1571 | }; | |
1572 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1573 | idecode = &insns[val]; | |
1574 | GOTO_EXTRACT (idecode); | |
1575 | } | |
1576 | CASE (0_116, 5) : | |
1577 | { | |
1578 | static const DECODE_DESC insns[16] = { | |
1579 | { I (INSN_REMI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1580 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1581 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1582 | { I (INSN_DIVI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1583 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1584 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1585 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1586 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1587 | }; | |
1588 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1589 | idecode = &insns[val]; | |
1590 | GOTO_EXTRACT (idecode); | |
1591 | } | |
1592 | CASE (0_116, 7) : | |
1593 | { | |
1594 | static const DECODE_DESC insns[16] = { | |
1595 | { I (INSN_REMI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1596 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1597 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1598 | { I (INSN_DIVI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1599 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1600 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1601 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1602 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1603 | }; | |
1604 | unsigned int val = (((insn >> 6) & (15 << 0))); | |
1605 | idecode = &insns[val]; | |
1606 | GOTO_EXTRACT (idecode); | |
1607 | } | |
1608 | DEFAULT (0_116) : | |
1609 | idecode = &insns[val]; | |
1610 | GOTO_EXTRACT (idecode); | |
1611 | } | |
1612 | ENDSWITCH (0_116) | |
1613 | } | |
1614 | CASE (0, 128) : | |
1615 | { | |
1616 | static const DECODE_DESC insns[16] = { | |
1617 | { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, | |
1618 | { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, | |
1619 | { I (INSN_LDOB_INDIRECT), E (FMT_LDOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1620 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOB_INDIRECT_INDEX), E (FMT_LDOB_INDIRECT_INDEX) }, | |
1621 | { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, | |
1622 | { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, | |
1623 | { I (INSN_LDOB_DISP), E (FMT_LDOB_DISP) }, { I (INSN_LDOB_INDIRECT_DISP), E (FMT_LDOB_INDIRECT_DISP) }, | |
1624 | { I (INSN_LDOB_INDEX_DISP), E (FMT_LDOB_INDEX_DISP) }, { I (INSN_LDOB_INDIRECT_INDEX_DISP), E (FMT_LDOB_INDIRECT_INDEX_DISP) }, | |
1625 | }; | |
1626 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1627 | idecode = &insns[val]; | |
1628 | GOTO_EXTRACT (idecode); | |
1629 | } | |
1630 | CASE (0, 130) : | |
1631 | { | |
1632 | static const DECODE_DESC insns[16] = { | |
1633 | { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, | |
1634 | { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, | |
1635 | { I (INSN_STOB_INDIRECT), E (FMT_STOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1636 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOB_INDIRECT_INDEX), E (FMT_STOB_INDIRECT_INDEX) }, | |
1637 | { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, | |
1638 | { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, | |
1639 | { I (INSN_STOB_DISP), E (FMT_STOB_DISP) }, { I (INSN_STOB_INDIRECT_DISP), E (FMT_STOB_INDIRECT_DISP) }, | |
1640 | { I (INSN_STOB_INDEX_DISP), E (FMT_STOB_INDEX_DISP) }, { I (INSN_STOB_INDIRECT_INDEX_DISP), E (FMT_STOB_INDIRECT_INDEX_DISP) }, | |
1641 | }; | |
1642 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1643 | idecode = &insns[val]; | |
1644 | GOTO_EXTRACT (idecode); | |
1645 | } | |
1646 | CASE (0, 132) : | |
1647 | { | |
1648 | static const DECODE_DESC insns[16] = { | |
1649 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1650 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1651 | { I (INSN_BX_INDIRECT), E (FMT_BX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1652 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_BX_INDIRECT_INDEX), E (FMT_BX_INDIRECT_INDEX) }, | |
1653 | { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, | |
1654 | { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, | |
1655 | { I (INSN_BX_DISP), E (FMT_BX_DISP) }, { I (INSN_BX_INDIRECT_DISP), E (FMT_BX_INDIRECT_DISP) }, | |
1656 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1657 | }; | |
1658 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1659 | idecode = &insns[val]; | |
1660 | GOTO_EXTRACT (idecode); | |
1661 | } | |
1662 | CASE (0, 134) : | |
1663 | { | |
1664 | static const DECODE_DESC insns[16] = { | |
1665 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1666 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1667 | { I (INSN_CALLX_INDIRECT), E (FMT_CALLX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1668 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1669 | { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, | |
1670 | { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, | |
1671 | { I (INSN_CALLX_DISP), E (FMT_CALLX_DISP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1672 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1673 | }; | |
1674 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1675 | idecode = &insns[val]; | |
1676 | GOTO_EXTRACT (idecode); | |
1677 | } | |
1678 | CASE (0, 136) : | |
1679 | { | |
1680 | static const DECODE_DESC insns[16] = { | |
1681 | { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, | |
1682 | { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, | |
1683 | { I (INSN_LDOS_INDIRECT), E (FMT_LDOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1684 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOS_INDIRECT_INDEX), E (FMT_LDOS_INDIRECT_INDEX) }, | |
1685 | { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, | |
1686 | { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, | |
1687 | { I (INSN_LDOS_DISP), E (FMT_LDOS_DISP) }, { I (INSN_LDOS_INDIRECT_DISP), E (FMT_LDOS_INDIRECT_DISP) }, | |
1688 | { I (INSN_LDOS_INDEX_DISP), E (FMT_LDOS_INDEX_DISP) }, { I (INSN_LDOS_INDIRECT_INDEX_DISP), E (FMT_LDOS_INDIRECT_INDEX_DISP) }, | |
1689 | }; | |
1690 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1691 | idecode = &insns[val]; | |
1692 | GOTO_EXTRACT (idecode); | |
1693 | } | |
1694 | CASE (0, 138) : | |
1695 | { | |
1696 | static const DECODE_DESC insns[16] = { | |
1697 | { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, | |
1698 | { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, | |
1699 | { I (INSN_STOS_INDIRECT), E (FMT_STOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1700 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOS_INDIRECT_INDEX), E (FMT_STOS_INDIRECT_INDEX) }, | |
1701 | { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, | |
1702 | { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, | |
1703 | { I (INSN_STOS_DISP), E (FMT_STOS_DISP) }, { I (INSN_STOS_INDIRECT_DISP), E (FMT_STOS_INDIRECT_DISP) }, | |
1704 | { I (INSN_STOS_INDEX_DISP), E (FMT_STOS_INDEX_DISP) }, { I (INSN_STOS_INDIRECT_INDEX_DISP), E (FMT_STOS_INDIRECT_INDEX_DISP) }, | |
1705 | }; | |
1706 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1707 | idecode = &insns[val]; | |
1708 | GOTO_EXTRACT (idecode); | |
1709 | } | |
1710 | CASE (0, 140) : | |
1711 | { | |
1712 | static const DECODE_DESC insns[16] = { | |
1713 | { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, | |
1714 | { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, | |
1715 | { I (INSN_LDA_INDIRECT), E (FMT_LDA_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1716 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDA_INDIRECT_INDEX), E (FMT_LDA_INDIRECT_INDEX) }, | |
1717 | { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, | |
1718 | { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, | |
1719 | { I (INSN_LDA_DISP), E (FMT_LDA_DISP) }, { I (INSN_LDA_INDIRECT_DISP), E (FMT_LDA_INDIRECT_DISP) }, | |
1720 | { I (INSN_LDA_INDEX_DISP), E (FMT_LDA_INDEX_DISP) }, { I (INSN_LDA_INDIRECT_INDEX_DISP), E (FMT_LDA_INDIRECT_INDEX_DISP) }, | |
1721 | }; | |
1722 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1723 | idecode = &insns[val]; | |
1724 | GOTO_EXTRACT (idecode); | |
1725 | } | |
1726 | CASE (0, 144) : | |
1727 | { | |
1728 | static const DECODE_DESC insns[16] = { | |
1729 | { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, | |
1730 | { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, | |
1731 | { I (INSN_LD_INDIRECT), E (FMT_LD_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1732 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LD_INDIRECT_INDEX), E (FMT_LD_INDIRECT_INDEX) }, | |
1733 | { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, | |
1734 | { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, | |
1735 | { I (INSN_LD_DISP), E (FMT_LD_DISP) }, { I (INSN_LD_INDIRECT_DISP), E (FMT_LD_INDIRECT_DISP) }, | |
1736 | { I (INSN_LD_INDEX_DISP), E (FMT_LD_INDEX_DISP) }, { I (INSN_LD_INDIRECT_INDEX_DISP), E (FMT_LD_INDIRECT_INDEX_DISP) }, | |
1737 | }; | |
1738 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1739 | idecode = &insns[val]; | |
1740 | GOTO_EXTRACT (idecode); | |
1741 | } | |
1742 | CASE (0, 146) : | |
1743 | { | |
1744 | static const DECODE_DESC insns[16] = { | |
1745 | { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, | |
1746 | { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, | |
1747 | { I (INSN_ST_INDIRECT), E (FMT_ST_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1748 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_ST_INDIRECT_INDEX), E (FMT_ST_INDIRECT_INDEX) }, | |
1749 | { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, | |
1750 | { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, | |
1751 | { I (INSN_ST_DISP), E (FMT_ST_DISP) }, { I (INSN_ST_INDIRECT_DISP), E (FMT_ST_INDIRECT_DISP) }, | |
1752 | { I (INSN_ST_INDEX_DISP), E (FMT_ST_INDEX_DISP) }, { I (INSN_ST_INDIRECT_INDEX_DISP), E (FMT_ST_INDIRECT_INDEX_DISP) }, | |
1753 | }; | |
1754 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1755 | idecode = &insns[val]; | |
1756 | GOTO_EXTRACT (idecode); | |
1757 | } | |
1758 | CASE (0, 152) : | |
1759 | { | |
1760 | static const DECODE_DESC insns[16] = { | |
1761 | { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, | |
1762 | { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, | |
1763 | { I (INSN_LDL_INDIRECT), E (FMT_LDL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1764 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDL_INDIRECT_INDEX), E (FMT_LDL_INDIRECT_INDEX) }, | |
1765 | { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, | |
1766 | { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, | |
1767 | { I (INSN_LDL_DISP), E (FMT_LDL_DISP) }, { I (INSN_LDL_INDIRECT_DISP), E (FMT_LDL_INDIRECT_DISP) }, | |
1768 | { I (INSN_LDL_INDEX_DISP), E (FMT_LDL_INDEX_DISP) }, { I (INSN_LDL_INDIRECT_INDEX_DISP), E (FMT_LDL_INDIRECT_INDEX_DISP) }, | |
1769 | }; | |
1770 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1771 | idecode = &insns[val]; | |
1772 | GOTO_EXTRACT (idecode); | |
1773 | } | |
1774 | CASE (0, 154) : | |
1775 | { | |
1776 | static const DECODE_DESC insns[16] = { | |
1777 | { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, | |
1778 | { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, | |
1779 | { I (INSN_STL_INDIRECT), E (FMT_STL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1780 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STL_INDIRECT_INDEX), E (FMT_STL_INDIRECT_INDEX) }, | |
1781 | { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, | |
1782 | { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, | |
1783 | { I (INSN_STL_DISP), E (FMT_STL_DISP) }, { I (INSN_STL_INDIRECT_DISP), E (FMT_STL_INDIRECT_DISP) }, | |
1784 | { I (INSN_STL_INDEX_DISP), E (FMT_STL_INDEX_DISP) }, { I (INSN_STL_INDIRECT_INDEX_DISP), E (FMT_STL_INDIRECT_INDEX_DISP) }, | |
1785 | }; | |
1786 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1787 | idecode = &insns[val]; | |
1788 | GOTO_EXTRACT (idecode); | |
1789 | } | |
1790 | CASE (0, 160) : | |
1791 | { | |
1792 | static const DECODE_DESC insns[16] = { | |
1793 | { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, | |
1794 | { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, | |
1795 | { I (INSN_LDT_INDIRECT), E (FMT_LDT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1796 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDT_INDIRECT_INDEX), E (FMT_LDT_INDIRECT_INDEX) }, | |
1797 | { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, | |
1798 | { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, | |
1799 | { I (INSN_LDT_DISP), E (FMT_LDT_DISP) }, { I (INSN_LDT_INDIRECT_DISP), E (FMT_LDT_INDIRECT_DISP) }, | |
1800 | { I (INSN_LDT_INDEX_DISP), E (FMT_LDT_INDEX_DISP) }, { I (INSN_LDT_INDIRECT_INDEX_DISP), E (FMT_LDT_INDIRECT_INDEX_DISP) }, | |
1801 | }; | |
1802 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1803 | idecode = &insns[val]; | |
1804 | GOTO_EXTRACT (idecode); | |
1805 | } | |
1806 | CASE (0, 162) : | |
1807 | { | |
1808 | static const DECODE_DESC insns[16] = { | |
1809 | { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, | |
1810 | { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, | |
1811 | { I (INSN_STT_INDIRECT), E (FMT_STT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1812 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STT_INDIRECT_INDEX), E (FMT_STT_INDIRECT_INDEX) }, | |
1813 | { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, | |
1814 | { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, | |
1815 | { I (INSN_STT_DISP), E (FMT_STT_DISP) }, { I (INSN_STT_INDIRECT_DISP), E (FMT_STT_INDIRECT_DISP) }, | |
1816 | { I (INSN_STT_INDEX_DISP), E (FMT_STT_INDEX_DISP) }, { I (INSN_STT_INDIRECT_INDEX_DISP), E (FMT_STT_INDIRECT_INDEX_DISP) }, | |
1817 | }; | |
1818 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1819 | idecode = &insns[val]; | |
1820 | GOTO_EXTRACT (idecode); | |
1821 | } | |
1822 | CASE (0, 176) : | |
1823 | { | |
1824 | static const DECODE_DESC insns[16] = { | |
1825 | { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, | |
1826 | { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, | |
1827 | { I (INSN_LDQ_INDIRECT), E (FMT_LDQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1828 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDQ_INDIRECT_INDEX), E (FMT_LDQ_INDIRECT_INDEX) }, | |
1829 | { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, | |
1830 | { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, | |
1831 | { I (INSN_LDQ_DISP), E (FMT_LDQ_DISP) }, { I (INSN_LDQ_INDIRECT_DISP), E (FMT_LDQ_INDIRECT_DISP) }, | |
1832 | { I (INSN_LDQ_INDEX_DISP), E (FMT_LDQ_INDEX_DISP) }, { I (INSN_LDQ_INDIRECT_INDEX_DISP), E (FMT_LDQ_INDIRECT_INDEX_DISP) }, | |
1833 | }; | |
1834 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1835 | idecode = &insns[val]; | |
1836 | GOTO_EXTRACT (idecode); | |
1837 | } | |
1838 | CASE (0, 178) : | |
1839 | { | |
1840 | static const DECODE_DESC insns[16] = { | |
1841 | { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, | |
1842 | { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, | |
1843 | { I (INSN_STQ_INDIRECT), E (FMT_STQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1844 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STQ_INDIRECT_INDEX), E (FMT_STQ_INDIRECT_INDEX) }, | |
1845 | { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, | |
1846 | { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, | |
1847 | { I (INSN_STQ_DISP), E (FMT_STQ_DISP) }, { I (INSN_STQ_INDIRECT_DISP), E (FMT_STQ_INDIRECT_DISP) }, | |
1848 | { I (INSN_STQ_INDEX_DISP), E (FMT_STQ_INDEX_DISP) }, { I (INSN_STQ_INDIRECT_INDEX_DISP), E (FMT_STQ_INDIRECT_INDEX_DISP) }, | |
1849 | }; | |
1850 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1851 | idecode = &insns[val]; | |
1852 | GOTO_EXTRACT (idecode); | |
1853 | } | |
1854 | CASE (0, 192) : | |
1855 | { | |
1856 | static const DECODE_DESC insns[16] = { | |
1857 | { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, | |
1858 | { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, | |
1859 | { I (INSN_LDIB_INDIRECT), E (FMT_LDIB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1860 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIB_INDIRECT_INDEX), E (FMT_LDIB_INDIRECT_INDEX) }, | |
1861 | { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, | |
1862 | { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, | |
1863 | { I (INSN_LDIB_DISP), E (FMT_LDIB_DISP) }, { I (INSN_LDIB_INDIRECT_DISP), E (FMT_LDIB_INDIRECT_DISP) }, | |
1864 | { I (INSN_LDIB_INDEX_DISP), E (FMT_LDIB_INDEX_DISP) }, { I (INSN_LDIB_INDIRECT_INDEX_DISP), E (FMT_LDIB_INDIRECT_INDEX_DISP) }, | |
1865 | }; | |
1866 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1867 | idecode = &insns[val]; | |
1868 | GOTO_EXTRACT (idecode); | |
1869 | } | |
1870 | CASE (0, 200) : | |
1871 | { | |
1872 | static const DECODE_DESC insns[16] = { | |
1873 | { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, | |
1874 | { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, | |
1875 | { I (INSN_LDIS_INDIRECT), E (FMT_LDIS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, | |
1876 | { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIS_INDIRECT_INDEX), E (FMT_LDIS_INDIRECT_INDEX) }, | |
1877 | { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, | |
1878 | { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, | |
1879 | { I (INSN_LDIS_DISP), E (FMT_LDIS_DISP) }, { I (INSN_LDIS_INDIRECT_DISP), E (FMT_LDIS_INDIRECT_DISP) }, | |
1880 | { I (INSN_LDIS_INDEX_DISP), E (FMT_LDIS_INDEX_DISP) }, { I (INSN_LDIS_INDIRECT_INDEX_DISP), E (FMT_LDIS_INDIRECT_INDEX_DISP) }, | |
1881 | }; | |
1882 | unsigned int val = (((insn >> 10) & (15 << 0))); | |
1883 | idecode = &insns[val]; | |
1884 | GOTO_EXTRACT (idecode); | |
1885 | } | |
1886 | DEFAULT (0) : | |
1887 | idecode = &insns[val]; | |
1888 | GOTO_EXTRACT (idecode); | |
1889 | } | |
1890 | ENDSWITCH (0) | |
1891 | } | |
1892 | #undef I | |
1893 | #undef E | |
1894 | } | |
1895 | ||
1896 | /* The instruction has been decoded, now extract the fields. */ | |
1897 | ||
1898 | extract: | |
1899 | { | |
1900 | #ifndef __GNUC__ | |
1901 | switch (idecode->sfmt) | |
1902 | #endif | |
1903 | { | |
1904 | ||
1905 | CASE (ex, FMT_EMPTY) : | |
1906 | { | |
1907 | CGEN_INSN_INT insn = base_insn; | |
1908 | #define FLD(f) abuf->fields.fmt_empty.f | |
1909 | EXTRACT_IFMT_EMPTY_VARS /* */ | |
1910 | ||
1911 | EXTRACT_IFMT_EMPTY_CODE | |
1912 | ||
1913 | /* Record the fields for the semantic handler. */ | |
1914 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); | |
1915 | ||
1916 | #undef FLD | |
1917 | BREAK (ex); | |
1918 | } | |
1919 | ||
1920 | CASE (ex, FMT_MULO) : | |
1921 | { | |
1922 | CGEN_INSN_INT insn = base_insn; | |
1923 | #define FLD(f) abuf->fields.fmt_mulo.f | |
1924 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
1925 | ||
1926 | EXTRACT_IFMT_MULO_CODE | |
1927 | ||
1928 | /* Record the fields for the semantic handler. */ | |
1929 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
1930 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
1931 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
1932 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
1933 | ||
1934 | #if WITH_PROFILE_MODEL_P | |
1935 | /* Record the fields for profiling. */ | |
1936 | if (PROFILE_MODEL_P (current_cpu)) | |
1937 | { | |
1938 | FLD (in_src1) = f_src1; | |
1939 | FLD (in_src2) = f_src2; | |
1940 | FLD (out_dst) = f_srcdst; | |
1941 | } | |
1942 | #endif | |
1943 | #undef FLD | |
1944 | BREAK (ex); | |
1945 | } | |
1946 | ||
1947 | CASE (ex, FMT_MULO1) : | |
1948 | { | |
1949 | CGEN_INSN_INT insn = base_insn; | |
1950 | #define FLD(f) abuf->fields.fmt_mulo1.f | |
1951 | EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
1952 | ||
1953 | EXTRACT_IFMT_MULO1_CODE | |
1954 | ||
1955 | /* Record the fields for the semantic handler. */ | |
1956 | FLD (f_src1) = f_src1; | |
1957 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
1958 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
1959 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
1960 | ||
1961 | #if WITH_PROFILE_MODEL_P | |
1962 | /* Record the fields for profiling. */ | |
1963 | if (PROFILE_MODEL_P (current_cpu)) | |
1964 | { | |
1965 | FLD (in_src2) = f_src2; | |
1966 | FLD (out_dst) = f_srcdst; | |
1967 | } | |
1968 | #endif | |
1969 | #undef FLD | |
1970 | BREAK (ex); | |
1971 | } | |
1972 | ||
1973 | CASE (ex, FMT_MULO2) : | |
1974 | { | |
1975 | CGEN_INSN_INT insn = base_insn; | |
1976 | #define FLD(f) abuf->fields.fmt_mulo2.f | |
1977 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
1978 | ||
1979 | EXTRACT_IFMT_MULO2_CODE | |
1980 | ||
1981 | /* Record the fields for the semantic handler. */ | |
1982 | FLD (f_src2) = f_src2; | |
1983 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
1984 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
1985 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
1986 | ||
1987 | #if WITH_PROFILE_MODEL_P | |
1988 | /* Record the fields for profiling. */ | |
1989 | if (PROFILE_MODEL_P (current_cpu)) | |
1990 | { | |
1991 | FLD (in_src1) = f_src1; | |
1992 | FLD (out_dst) = f_srcdst; | |
1993 | } | |
1994 | #endif | |
1995 | #undef FLD | |
1996 | BREAK (ex); | |
1997 | } | |
1998 | ||
1999 | CASE (ex, FMT_MULO3) : | |
2000 | { | |
2001 | CGEN_INSN_INT insn = base_insn; | |
2002 | #define FLD(f) abuf->fields.fmt_mulo3.f | |
2003 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2004 | ||
2005 | EXTRACT_IFMT_MULO3_CODE | |
2006 | ||
2007 | /* Record the fields for the semantic handler. */ | |
2008 | FLD (f_src1) = f_src1; | |
2009 | FLD (f_src2) = f_src2; | |
2010 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2011 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2012 | ||
2013 | #if WITH_PROFILE_MODEL_P | |
2014 | /* Record the fields for profiling. */ | |
2015 | if (PROFILE_MODEL_P (current_cpu)) | |
2016 | { | |
2017 | FLD (out_dst) = f_srcdst; | |
2018 | } | |
2019 | #endif | |
2020 | #undef FLD | |
2021 | BREAK (ex); | |
2022 | } | |
2023 | ||
2024 | CASE (ex, FMT_NOTBIT) : | |
2025 | { | |
2026 | CGEN_INSN_INT insn = base_insn; | |
2027 | #define FLD(f) abuf->fields.fmt_notbit.f | |
2028 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2029 | ||
2030 | EXTRACT_IFMT_MULO_CODE | |
2031 | ||
2032 | /* Record the fields for the semantic handler. */ | |
2033 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2034 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
2035 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2036 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2037 | ||
2038 | #if WITH_PROFILE_MODEL_P | |
2039 | /* Record the fields for profiling. */ | |
2040 | if (PROFILE_MODEL_P (current_cpu)) | |
2041 | { | |
2042 | FLD (in_src1) = f_src1; | |
2043 | FLD (in_src2) = f_src2; | |
2044 | FLD (out_dst) = f_srcdst; | |
2045 | } | |
2046 | #endif | |
2047 | #undef FLD | |
2048 | BREAK (ex); | |
2049 | } | |
2050 | ||
2051 | CASE (ex, FMT_NOTBIT1) : | |
2052 | { | |
2053 | CGEN_INSN_INT insn = base_insn; | |
2054 | #define FLD(f) abuf->fields.fmt_notbit1.f | |
2055 | EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2056 | ||
2057 | EXTRACT_IFMT_MULO1_CODE | |
2058 | ||
2059 | /* Record the fields for the semantic handler. */ | |
2060 | FLD (f_src1) = f_src1; | |
2061 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
2062 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2063 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2064 | ||
2065 | #if WITH_PROFILE_MODEL_P | |
2066 | /* Record the fields for profiling. */ | |
2067 | if (PROFILE_MODEL_P (current_cpu)) | |
2068 | { | |
2069 | FLD (in_src2) = f_src2; | |
2070 | FLD (out_dst) = f_srcdst; | |
2071 | } | |
2072 | #endif | |
2073 | #undef FLD | |
2074 | BREAK (ex); | |
2075 | } | |
2076 | ||
2077 | CASE (ex, FMT_NOTBIT2) : | |
2078 | { | |
2079 | CGEN_INSN_INT insn = base_insn; | |
2080 | #define FLD(f) abuf->fields.fmt_notbit2.f | |
2081 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2082 | ||
2083 | EXTRACT_IFMT_MULO2_CODE | |
2084 | ||
2085 | /* Record the fields for the semantic handler. */ | |
2086 | FLD (f_src2) = f_src2; | |
2087 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2088 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2089 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2090 | ||
2091 | #if WITH_PROFILE_MODEL_P | |
2092 | /* Record the fields for profiling. */ | |
2093 | if (PROFILE_MODEL_P (current_cpu)) | |
2094 | { | |
2095 | FLD (in_src1) = f_src1; | |
2096 | FLD (out_dst) = f_srcdst; | |
2097 | } | |
2098 | #endif | |
2099 | #undef FLD | |
2100 | BREAK (ex); | |
2101 | } | |
2102 | ||
2103 | CASE (ex, FMT_NOTBIT3) : | |
2104 | { | |
2105 | CGEN_INSN_INT insn = base_insn; | |
2106 | #define FLD(f) abuf->fields.fmt_notbit3.f | |
2107 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2108 | ||
2109 | EXTRACT_IFMT_MULO3_CODE | |
2110 | ||
2111 | /* Record the fields for the semantic handler. */ | |
2112 | FLD (f_src1) = f_src1; | |
2113 | FLD (f_src2) = f_src2; | |
2114 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2115 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2116 | ||
2117 | #if WITH_PROFILE_MODEL_P | |
2118 | /* Record the fields for profiling. */ | |
2119 | if (PROFILE_MODEL_P (current_cpu)) | |
2120 | { | |
2121 | FLD (out_dst) = f_srcdst; | |
2122 | } | |
2123 | #endif | |
2124 | #undef FLD | |
2125 | BREAK (ex); | |
2126 | } | |
2127 | ||
2128 | CASE (ex, FMT_NOT) : | |
2129 | { | |
2130 | CGEN_INSN_INT insn = base_insn; | |
2131 | #define FLD(f) abuf->fields.fmt_not.f | |
2132 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2133 | ||
2134 | EXTRACT_IFMT_MULO_CODE | |
2135 | ||
2136 | /* Record the fields for the semantic handler. */ | |
2137 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2138 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2139 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not", "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2140 | ||
2141 | #if WITH_PROFILE_MODEL_P | |
2142 | /* Record the fields for profiling. */ | |
2143 | if (PROFILE_MODEL_P (current_cpu)) | |
2144 | { | |
2145 | FLD (in_src1) = f_src1; | |
2146 | FLD (out_dst) = f_srcdst; | |
2147 | } | |
2148 | #endif | |
2149 | #undef FLD | |
2150 | BREAK (ex); | |
2151 | } | |
2152 | ||
2153 | CASE (ex, FMT_NOT1) : | |
2154 | { | |
2155 | CGEN_INSN_INT insn = base_insn; | |
2156 | #define FLD(f) abuf->fields.fmt_not1.f | |
2157 | EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2158 | ||
2159 | EXTRACT_IFMT_MULO1_CODE | |
2160 | ||
2161 | /* Record the fields for the semantic handler. */ | |
2162 | FLD (f_src1) = f_src1; | |
2163 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2164 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not1", "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2165 | ||
2166 | #if WITH_PROFILE_MODEL_P | |
2167 | /* Record the fields for profiling. */ | |
2168 | if (PROFILE_MODEL_P (current_cpu)) | |
2169 | { | |
2170 | FLD (out_dst) = f_srcdst; | |
2171 | } | |
2172 | #endif | |
2173 | #undef FLD | |
2174 | BREAK (ex); | |
2175 | } | |
2176 | ||
2177 | CASE (ex, FMT_NOT2) : | |
2178 | { | |
2179 | CGEN_INSN_INT insn = base_insn; | |
2180 | #define FLD(f) abuf->fields.fmt_not2.f | |
2181 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2182 | ||
2183 | EXTRACT_IFMT_MULO2_CODE | |
2184 | ||
2185 | /* Record the fields for the semantic handler. */ | |
2186 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2187 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2188 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not2", "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2189 | ||
2190 | #if WITH_PROFILE_MODEL_P | |
2191 | /* Record the fields for profiling. */ | |
2192 | if (PROFILE_MODEL_P (current_cpu)) | |
2193 | { | |
2194 | FLD (in_src1) = f_src1; | |
2195 | FLD (out_dst) = f_srcdst; | |
2196 | } | |
2197 | #endif | |
2198 | #undef FLD | |
2199 | BREAK (ex); | |
2200 | } | |
2201 | ||
2202 | CASE (ex, FMT_NOT3) : | |
2203 | { | |
2204 | CGEN_INSN_INT insn = base_insn; | |
2205 | #define FLD(f) abuf->fields.fmt_not3.f | |
2206 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2207 | ||
2208 | EXTRACT_IFMT_MULO3_CODE | |
2209 | ||
2210 | /* Record the fields for the semantic handler. */ | |
2211 | FLD (f_src1) = f_src1; | |
2212 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2213 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not3", "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2214 | ||
2215 | #if WITH_PROFILE_MODEL_P | |
2216 | /* Record the fields for profiling. */ | |
2217 | if (PROFILE_MODEL_P (current_cpu)) | |
2218 | { | |
2219 | FLD (out_dst) = f_srcdst; | |
2220 | } | |
2221 | #endif | |
2222 | #undef FLD | |
2223 | BREAK (ex); | |
2224 | } | |
2225 | ||
2226 | CASE (ex, FMT_EMUL) : | |
2227 | { | |
2228 | CGEN_INSN_INT insn = base_insn; | |
2229 | #define FLD(f) abuf->fields.fmt_emul.f | |
2230 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2231 | ||
2232 | EXTRACT_IFMT_MULO_CODE | |
2233 | ||
2234 | /* Record the fields for the semantic handler. */ | |
2235 | FLD (f_srcdst) = f_srcdst; | |
2236 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2237 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
2238 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2239 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul", "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2240 | ||
2241 | #if WITH_PROFILE_MODEL_P | |
2242 | /* Record the fields for profiling. */ | |
2243 | if (PROFILE_MODEL_P (current_cpu)) | |
2244 | { | |
2245 | FLD (in_src1) = f_src1; | |
2246 | FLD (in_src2) = f_src2; | |
2247 | FLD (out_dst) = f_srcdst; | |
2248 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2249 | } | |
2250 | #endif | |
2251 | #undef FLD | |
2252 | BREAK (ex); | |
2253 | } | |
2254 | ||
2255 | CASE (ex, FMT_EMUL1) : | |
2256 | { | |
2257 | CGEN_INSN_INT insn = base_insn; | |
2258 | #define FLD(f) abuf->fields.fmt_emul1.f | |
2259 | EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2260 | ||
2261 | EXTRACT_IFMT_MULO1_CODE | |
2262 | ||
2263 | /* Record the fields for the semantic handler. */ | |
2264 | FLD (f_srcdst) = f_srcdst; | |
2265 | FLD (f_src1) = f_src1; | |
2266 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
2267 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2268 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2269 | ||
2270 | #if WITH_PROFILE_MODEL_P | |
2271 | /* Record the fields for profiling. */ | |
2272 | if (PROFILE_MODEL_P (current_cpu)) | |
2273 | { | |
2274 | FLD (in_src2) = f_src2; | |
2275 | FLD (out_dst) = f_srcdst; | |
2276 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2277 | } | |
2278 | #endif | |
2279 | #undef FLD | |
2280 | BREAK (ex); | |
2281 | } | |
2282 | ||
2283 | CASE (ex, FMT_EMUL2) : | |
2284 | { | |
2285 | CGEN_INSN_INT insn = base_insn; | |
2286 | #define FLD(f) abuf->fields.fmt_emul2.f | |
2287 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2288 | ||
2289 | EXTRACT_IFMT_MULO2_CODE | |
2290 | ||
2291 | /* Record the fields for the semantic handler. */ | |
2292 | FLD (f_srcdst) = f_srcdst; | |
2293 | FLD (f_src2) = f_src2; | |
2294 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2295 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2296 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul2", "f_srcdst 0x%x", 'x', f_srcdst, "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2297 | ||
2298 | #if WITH_PROFILE_MODEL_P | |
2299 | /* Record the fields for profiling. */ | |
2300 | if (PROFILE_MODEL_P (current_cpu)) | |
2301 | { | |
2302 | FLD (in_src1) = f_src1; | |
2303 | FLD (out_dst) = f_srcdst; | |
2304 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2305 | } | |
2306 | #endif | |
2307 | #undef FLD | |
2308 | BREAK (ex); | |
2309 | } | |
2310 | ||
2311 | CASE (ex, FMT_EMUL3) : | |
2312 | { | |
2313 | CGEN_INSN_INT insn = base_insn; | |
2314 | #define FLD(f) abuf->fields.fmt_emul3.f | |
2315 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2316 | ||
2317 | EXTRACT_IFMT_MULO3_CODE | |
2318 | ||
2319 | /* Record the fields for the semantic handler. */ | |
2320 | FLD (f_srcdst) = f_srcdst; | |
2321 | FLD (f_src1) = f_src1; | |
2322 | FLD (f_src2) = f_src2; | |
2323 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2324 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul3", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2325 | ||
2326 | #if WITH_PROFILE_MODEL_P | |
2327 | /* Record the fields for profiling. */ | |
2328 | if (PROFILE_MODEL_P (current_cpu)) | |
2329 | { | |
2330 | FLD (out_dst) = f_srcdst; | |
2331 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2332 | } | |
2333 | #endif | |
2334 | #undef FLD | |
2335 | BREAK (ex); | |
2336 | } | |
2337 | ||
2338 | CASE (ex, FMT_MOVL) : | |
2339 | { | |
2340 | CGEN_INSN_INT insn = base_insn; | |
2341 | #define FLD(f) abuf->fields.fmt_movl.f | |
2342 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2343 | ||
2344 | EXTRACT_IFMT_MULO2_CODE | |
2345 | ||
2346 | /* Record the fields for the semantic handler. */ | |
2347 | FLD (f_src1) = f_src1; | |
2348 | FLD (f_srcdst) = f_srcdst; | |
2349 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2350 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2351 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movl", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2352 | ||
2353 | #if WITH_PROFILE_MODEL_P | |
2354 | /* Record the fields for profiling. */ | |
2355 | if (PROFILE_MODEL_P (current_cpu)) | |
2356 | { | |
2357 | FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1)); | |
2358 | FLD (in_src1) = f_src1; | |
2359 | FLD (out_dst) = f_srcdst; | |
2360 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2361 | } | |
2362 | #endif | |
2363 | #undef FLD | |
2364 | BREAK (ex); | |
2365 | } | |
2366 | ||
2367 | CASE (ex, FMT_MOVL1) : | |
2368 | { | |
2369 | CGEN_INSN_INT insn = base_insn; | |
2370 | #define FLD(f) abuf->fields.fmt_movl1.f | |
2371 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2372 | ||
2373 | EXTRACT_IFMT_MULO3_CODE | |
2374 | ||
2375 | /* Record the fields for the semantic handler. */ | |
2376 | FLD (f_srcdst) = f_srcdst; | |
2377 | FLD (f_src1) = f_src1; | |
2378 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2379 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movl1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2380 | ||
2381 | #if WITH_PROFILE_MODEL_P | |
2382 | /* Record the fields for profiling. */ | |
2383 | if (PROFILE_MODEL_P (current_cpu)) | |
2384 | { | |
2385 | FLD (out_dst) = f_srcdst; | |
2386 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2387 | } | |
2388 | #endif | |
2389 | #undef FLD | |
2390 | BREAK (ex); | |
2391 | } | |
2392 | ||
2393 | CASE (ex, FMT_MOVT) : | |
2394 | { | |
2395 | CGEN_INSN_INT insn = base_insn; | |
2396 | #define FLD(f) abuf->fields.fmt_movt.f | |
2397 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2398 | ||
2399 | EXTRACT_IFMT_MULO2_CODE | |
2400 | ||
2401 | /* Record the fields for the semantic handler. */ | |
2402 | FLD (f_src1) = f_src1; | |
2403 | FLD (f_srcdst) = f_srcdst; | |
2404 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2405 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2406 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movt", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2407 | ||
2408 | #if WITH_PROFILE_MODEL_P | |
2409 | /* Record the fields for profiling. */ | |
2410 | if (PROFILE_MODEL_P (current_cpu)) | |
2411 | { | |
2412 | FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1)); | |
2413 | FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2)); | |
2414 | FLD (in_src1) = f_src1; | |
2415 | FLD (out_dst) = f_srcdst; | |
2416 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2417 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
2418 | } | |
2419 | #endif | |
2420 | #undef FLD | |
2421 | BREAK (ex); | |
2422 | } | |
2423 | ||
2424 | CASE (ex, FMT_MOVT1) : | |
2425 | { | |
2426 | CGEN_INSN_INT insn = base_insn; | |
2427 | #define FLD(f) abuf->fields.fmt_movt1.f | |
2428 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2429 | ||
2430 | EXTRACT_IFMT_MULO3_CODE | |
2431 | ||
2432 | /* Record the fields for the semantic handler. */ | |
2433 | FLD (f_srcdst) = f_srcdst; | |
2434 | FLD (f_src1) = f_src1; | |
2435 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2436 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movt1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2437 | ||
2438 | #if WITH_PROFILE_MODEL_P | |
2439 | /* Record the fields for profiling. */ | |
2440 | if (PROFILE_MODEL_P (current_cpu)) | |
2441 | { | |
2442 | FLD (out_dst) = f_srcdst; | |
2443 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2444 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
2445 | } | |
2446 | #endif | |
2447 | #undef FLD | |
2448 | BREAK (ex); | |
2449 | } | |
2450 | ||
2451 | CASE (ex, FMT_MOVQ) : | |
2452 | { | |
2453 | CGEN_INSN_INT insn = base_insn; | |
2454 | #define FLD(f) abuf->fields.fmt_movq.f | |
2455 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2456 | ||
2457 | EXTRACT_IFMT_MULO2_CODE | |
2458 | ||
2459 | /* Record the fields for the semantic handler. */ | |
2460 | FLD (f_src1) = f_src1; | |
2461 | FLD (f_srcdst) = f_srcdst; | |
2462 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
2463 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2464 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movq", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2465 | ||
2466 | #if WITH_PROFILE_MODEL_P | |
2467 | /* Record the fields for profiling. */ | |
2468 | if (PROFILE_MODEL_P (current_cpu)) | |
2469 | { | |
2470 | FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1)); | |
2471 | FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2)); | |
2472 | FLD (in_h_gr_add__VM_index_of_src1_const__WI_3) = ((FLD (f_src1)) + (3)); | |
2473 | FLD (in_src1) = f_src1; | |
2474 | FLD (out_dst) = f_srcdst; | |
2475 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2476 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
2477 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
2478 | } | |
2479 | #endif | |
2480 | #undef FLD | |
2481 | BREAK (ex); | |
2482 | } | |
2483 | ||
2484 | CASE (ex, FMT_MOVQ1) : | |
2485 | { | |
2486 | CGEN_INSN_INT insn = base_insn; | |
2487 | #define FLD(f) abuf->fields.fmt_movq1.f | |
2488 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2489 | ||
2490 | EXTRACT_IFMT_MULO3_CODE | |
2491 | ||
2492 | /* Record the fields for the semantic handler. */ | |
2493 | FLD (f_srcdst) = f_srcdst; | |
2494 | FLD (f_src1) = f_src1; | |
2495 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2496 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movq1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2497 | ||
2498 | #if WITH_PROFILE_MODEL_P | |
2499 | /* Record the fields for profiling. */ | |
2500 | if (PROFILE_MODEL_P (current_cpu)) | |
2501 | { | |
2502 | FLD (out_dst) = f_srcdst; | |
2503 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
2504 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
2505 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
2506 | } | |
2507 | #endif | |
2508 | #undef FLD | |
2509 | BREAK (ex); | |
2510 | } | |
2511 | ||
2512 | CASE (ex, FMT_MODPC) : | |
2513 | { | |
2514 | CGEN_INSN_INT insn = base_insn; | |
2515 | #define FLD(f) abuf->fields.fmt_modpc.f | |
2516 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
2517 | ||
2518 | EXTRACT_IFMT_MULO_CODE | |
2519 | ||
2520 | /* Record the fields for the semantic handler. */ | |
2521 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
2522 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2523 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_modpc", "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2524 | ||
2525 | #if WITH_PROFILE_MODEL_P | |
2526 | /* Record the fields for profiling. */ | |
2527 | if (PROFILE_MODEL_P (current_cpu)) | |
2528 | { | |
2529 | FLD (in_src2) = f_src2; | |
2530 | FLD (out_dst) = f_srcdst; | |
2531 | } | |
2532 | #endif | |
2533 | #undef FLD | |
2534 | BREAK (ex); | |
2535 | } | |
2536 | ||
2537 | CASE (ex, FMT_LDA_OFFSET) : | |
2538 | { | |
2539 | CGEN_INSN_INT insn = base_insn; | |
2540 | #define FLD(f) abuf->fields.fmt_lda_offset.f | |
2541 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
2542 | ||
2543 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
2544 | ||
2545 | /* Record the fields for the semantic handler. */ | |
2546 | FLD (f_offset) = f_offset; | |
2547 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2548 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2549 | ||
2550 | #if WITH_PROFILE_MODEL_P | |
2551 | /* Record the fields for profiling. */ | |
2552 | if (PROFILE_MODEL_P (current_cpu)) | |
2553 | { | |
2554 | FLD (out_dst) = f_srcdst; | |
2555 | } | |
2556 | #endif | |
2557 | #undef FLD | |
2558 | BREAK (ex); | |
2559 | } | |
2560 | ||
2561 | CASE (ex, FMT_LDA_INDIRECT_OFFSET) : | |
2562 | { | |
2563 | CGEN_INSN_INT insn = base_insn; | |
2564 | #define FLD(f) abuf->fields.fmt_lda_indirect_offset.f | |
2565 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
2566 | ||
2567 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
2568 | ||
2569 | /* Record the fields for the semantic handler. */ | |
2570 | FLD (f_offset) = f_offset; | |
2571 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2572 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2573 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2574 | ||
2575 | #if WITH_PROFILE_MODEL_P | |
2576 | /* Record the fields for profiling. */ | |
2577 | if (PROFILE_MODEL_P (current_cpu)) | |
2578 | { | |
2579 | FLD (in_abase) = f_abase; | |
2580 | FLD (out_dst) = f_srcdst; | |
2581 | } | |
2582 | #endif | |
2583 | #undef FLD | |
2584 | BREAK (ex); | |
2585 | } | |
2586 | ||
2587 | CASE (ex, FMT_LDA_INDIRECT) : | |
2588 | { | |
2589 | CGEN_INSN_INT insn = base_insn; | |
2590 | #define FLD(f) abuf->fields.fmt_lda_indirect.f | |
2591 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2592 | ||
2593 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
2594 | ||
2595 | /* Record the fields for the semantic handler. */ | |
2596 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2597 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2598 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2599 | ||
2600 | #if WITH_PROFILE_MODEL_P | |
2601 | /* Record the fields for profiling. */ | |
2602 | if (PROFILE_MODEL_P (current_cpu)) | |
2603 | { | |
2604 | FLD (in_abase) = f_abase; | |
2605 | FLD (out_dst) = f_srcdst; | |
2606 | } | |
2607 | #endif | |
2608 | #undef FLD | |
2609 | BREAK (ex); | |
2610 | } | |
2611 | ||
2612 | CASE (ex, FMT_LDA_INDIRECT_INDEX) : | |
2613 | { | |
2614 | CGEN_INSN_INT insn = base_insn; | |
2615 | #define FLD(f) abuf->fields.fmt_lda_indirect_index.f | |
2616 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2617 | ||
2618 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
2619 | ||
2620 | /* Record the fields for the semantic handler. */ | |
2621 | FLD (f_scale) = f_scale; | |
2622 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2623 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
2624 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2625 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2626 | ||
2627 | #if WITH_PROFILE_MODEL_P | |
2628 | /* Record the fields for profiling. */ | |
2629 | if (PROFILE_MODEL_P (current_cpu)) | |
2630 | { | |
2631 | FLD (in_abase) = f_abase; | |
2632 | FLD (in_index) = f_index; | |
2633 | FLD (out_dst) = f_srcdst; | |
2634 | } | |
2635 | #endif | |
2636 | #undef FLD | |
2637 | BREAK (ex); | |
2638 | } | |
2639 | ||
2640 | CASE (ex, FMT_LDA_DISP) : | |
2641 | { | |
2642 | CGEN_INSN_INT insn = base_insn; | |
2643 | #define FLD(f) abuf->fields.fmt_lda_disp.f | |
2644 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2645 | ||
2646 | EXTRACT_IFMT_LDA_DISP_CODE | |
2647 | ||
2648 | /* Record the fields for the semantic handler. */ | |
2649 | FLD (f_optdisp) = f_optdisp; | |
2650 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2651 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2652 | ||
2653 | #if WITH_PROFILE_MODEL_P | |
2654 | /* Record the fields for profiling. */ | |
2655 | if (PROFILE_MODEL_P (current_cpu)) | |
2656 | { | |
2657 | FLD (out_dst) = f_srcdst; | |
2658 | } | |
2659 | #endif | |
2660 | #undef FLD | |
2661 | BREAK (ex); | |
2662 | } | |
2663 | ||
2664 | CASE (ex, FMT_LDA_INDIRECT_DISP) : | |
2665 | { | |
2666 | CGEN_INSN_INT insn = base_insn; | |
2667 | #define FLD(f) abuf->fields.fmt_lda_indirect_disp.f | |
2668 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2669 | ||
2670 | EXTRACT_IFMT_LDA_DISP_CODE | |
2671 | ||
2672 | /* Record the fields for the semantic handler. */ | |
2673 | FLD (f_optdisp) = f_optdisp; | |
2674 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2675 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2676 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2677 | ||
2678 | #if WITH_PROFILE_MODEL_P | |
2679 | /* Record the fields for profiling. */ | |
2680 | if (PROFILE_MODEL_P (current_cpu)) | |
2681 | { | |
2682 | FLD (in_abase) = f_abase; | |
2683 | FLD (out_dst) = f_srcdst; | |
2684 | } | |
2685 | #endif | |
2686 | #undef FLD | |
2687 | BREAK (ex); | |
2688 | } | |
2689 | ||
2690 | CASE (ex, FMT_LDA_INDEX_DISP) : | |
2691 | { | |
2692 | CGEN_INSN_INT insn = base_insn; | |
2693 | #define FLD(f) abuf->fields.fmt_lda_index_disp.f | |
2694 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2695 | ||
2696 | EXTRACT_IFMT_LDA_DISP_CODE | |
2697 | ||
2698 | /* Record the fields for the semantic handler. */ | |
2699 | FLD (f_optdisp) = f_optdisp; | |
2700 | FLD (f_scale) = f_scale; | |
2701 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
2702 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2703 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2704 | ||
2705 | #if WITH_PROFILE_MODEL_P | |
2706 | /* Record the fields for profiling. */ | |
2707 | if (PROFILE_MODEL_P (current_cpu)) | |
2708 | { | |
2709 | FLD (in_index) = f_index; | |
2710 | FLD (out_dst) = f_srcdst; | |
2711 | } | |
2712 | #endif | |
2713 | #undef FLD | |
2714 | BREAK (ex); | |
2715 | } | |
2716 | ||
2717 | CASE (ex, FMT_LDA_INDIRECT_INDEX_DISP) : | |
2718 | { | |
2719 | CGEN_INSN_INT insn = base_insn; | |
2720 | #define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f | |
2721 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2722 | ||
2723 | EXTRACT_IFMT_LDA_DISP_CODE | |
2724 | ||
2725 | /* Record the fields for the semantic handler. */ | |
2726 | FLD (f_optdisp) = f_optdisp; | |
2727 | FLD (f_scale) = f_scale; | |
2728 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2729 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
2730 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2731 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2732 | ||
2733 | #if WITH_PROFILE_MODEL_P | |
2734 | /* Record the fields for profiling. */ | |
2735 | if (PROFILE_MODEL_P (current_cpu)) | |
2736 | { | |
2737 | FLD (in_abase) = f_abase; | |
2738 | FLD (in_index) = f_index; | |
2739 | FLD (out_dst) = f_srcdst; | |
2740 | } | |
2741 | #endif | |
2742 | #undef FLD | |
2743 | BREAK (ex); | |
2744 | } | |
2745 | ||
2746 | CASE (ex, FMT_LD_OFFSET) : | |
2747 | { | |
2748 | CGEN_INSN_INT insn = base_insn; | |
2749 | #define FLD(f) abuf->fields.fmt_ld_offset.f | |
2750 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
2751 | ||
2752 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
2753 | ||
2754 | /* Record the fields for the semantic handler. */ | |
2755 | FLD (f_offset) = f_offset; | |
2756 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2757 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2758 | ||
2759 | #if WITH_PROFILE_MODEL_P | |
2760 | /* Record the fields for profiling. */ | |
2761 | if (PROFILE_MODEL_P (current_cpu)) | |
2762 | { | |
2763 | FLD (out_dst) = f_srcdst; | |
2764 | } | |
2765 | #endif | |
2766 | #undef FLD | |
2767 | BREAK (ex); | |
2768 | } | |
2769 | ||
2770 | CASE (ex, FMT_LD_INDIRECT_OFFSET) : | |
2771 | { | |
2772 | CGEN_INSN_INT insn = base_insn; | |
2773 | #define FLD(f) abuf->fields.fmt_ld_indirect_offset.f | |
2774 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
2775 | ||
2776 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
2777 | ||
2778 | /* Record the fields for the semantic handler. */ | |
2779 | FLD (f_offset) = f_offset; | |
2780 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2781 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2782 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2783 | ||
2784 | #if WITH_PROFILE_MODEL_P | |
2785 | /* Record the fields for profiling. */ | |
2786 | if (PROFILE_MODEL_P (current_cpu)) | |
2787 | { | |
2788 | FLD (in_abase) = f_abase; | |
2789 | FLD (out_dst) = f_srcdst; | |
2790 | } | |
2791 | #endif | |
2792 | #undef FLD | |
2793 | BREAK (ex); | |
2794 | } | |
2795 | ||
2796 | CASE (ex, FMT_LD_INDIRECT) : | |
2797 | { | |
2798 | CGEN_INSN_INT insn = base_insn; | |
2799 | #define FLD(f) abuf->fields.fmt_ld_indirect.f | |
2800 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2801 | ||
2802 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
2803 | ||
2804 | /* Record the fields for the semantic handler. */ | |
2805 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2806 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2807 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2808 | ||
2809 | #if WITH_PROFILE_MODEL_P | |
2810 | /* Record the fields for profiling. */ | |
2811 | if (PROFILE_MODEL_P (current_cpu)) | |
2812 | { | |
2813 | FLD (in_abase) = f_abase; | |
2814 | FLD (out_dst) = f_srcdst; | |
2815 | } | |
2816 | #endif | |
2817 | #undef FLD | |
2818 | BREAK (ex); | |
2819 | } | |
2820 | ||
2821 | CASE (ex, FMT_LD_INDIRECT_INDEX) : | |
2822 | { | |
2823 | CGEN_INSN_INT insn = base_insn; | |
2824 | #define FLD(f) abuf->fields.fmt_ld_indirect_index.f | |
2825 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2826 | ||
2827 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
2828 | ||
2829 | /* Record the fields for the semantic handler. */ | |
2830 | FLD (f_scale) = f_scale; | |
2831 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2832 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
2833 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2834 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2835 | ||
2836 | #if WITH_PROFILE_MODEL_P | |
2837 | /* Record the fields for profiling. */ | |
2838 | if (PROFILE_MODEL_P (current_cpu)) | |
2839 | { | |
2840 | FLD (in_abase) = f_abase; | |
2841 | FLD (in_index) = f_index; | |
2842 | FLD (out_dst) = f_srcdst; | |
2843 | } | |
2844 | #endif | |
2845 | #undef FLD | |
2846 | BREAK (ex); | |
2847 | } | |
2848 | ||
2849 | CASE (ex, FMT_LD_DISP) : | |
2850 | { | |
2851 | CGEN_INSN_INT insn = base_insn; | |
2852 | #define FLD(f) abuf->fields.fmt_ld_disp.f | |
2853 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2854 | ||
2855 | EXTRACT_IFMT_LDA_DISP_CODE | |
2856 | ||
2857 | /* Record the fields for the semantic handler. */ | |
2858 | FLD (f_optdisp) = f_optdisp; | |
2859 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2860 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2861 | ||
2862 | #if WITH_PROFILE_MODEL_P | |
2863 | /* Record the fields for profiling. */ | |
2864 | if (PROFILE_MODEL_P (current_cpu)) | |
2865 | { | |
2866 | FLD (out_dst) = f_srcdst; | |
2867 | } | |
2868 | #endif | |
2869 | #undef FLD | |
2870 | BREAK (ex); | |
2871 | } | |
2872 | ||
2873 | CASE (ex, FMT_LD_INDIRECT_DISP) : | |
2874 | { | |
2875 | CGEN_INSN_INT insn = base_insn; | |
2876 | #define FLD(f) abuf->fields.fmt_ld_indirect_disp.f | |
2877 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2878 | ||
2879 | EXTRACT_IFMT_LDA_DISP_CODE | |
2880 | ||
2881 | /* Record the fields for the semantic handler. */ | |
2882 | FLD (f_optdisp) = f_optdisp; | |
2883 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2884 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2885 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2886 | ||
2887 | #if WITH_PROFILE_MODEL_P | |
2888 | /* Record the fields for profiling. */ | |
2889 | if (PROFILE_MODEL_P (current_cpu)) | |
2890 | { | |
2891 | FLD (in_abase) = f_abase; | |
2892 | FLD (out_dst) = f_srcdst; | |
2893 | } | |
2894 | #endif | |
2895 | #undef FLD | |
2896 | BREAK (ex); | |
2897 | } | |
2898 | ||
2899 | CASE (ex, FMT_LD_INDEX_DISP) : | |
2900 | { | |
2901 | CGEN_INSN_INT insn = base_insn; | |
2902 | #define FLD(f) abuf->fields.fmt_ld_index_disp.f | |
2903 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2904 | ||
2905 | EXTRACT_IFMT_LDA_DISP_CODE | |
2906 | ||
2907 | /* Record the fields for the semantic handler. */ | |
2908 | FLD (f_optdisp) = f_optdisp; | |
2909 | FLD (f_scale) = f_scale; | |
2910 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
2911 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2912 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2913 | ||
2914 | #if WITH_PROFILE_MODEL_P | |
2915 | /* Record the fields for profiling. */ | |
2916 | if (PROFILE_MODEL_P (current_cpu)) | |
2917 | { | |
2918 | FLD (in_index) = f_index; | |
2919 | FLD (out_dst) = f_srcdst; | |
2920 | } | |
2921 | #endif | |
2922 | #undef FLD | |
2923 | BREAK (ex); | |
2924 | } | |
2925 | ||
2926 | CASE (ex, FMT_LD_INDIRECT_INDEX_DISP) : | |
2927 | { | |
2928 | CGEN_INSN_INT insn = base_insn; | |
2929 | #define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f | |
2930 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
2931 | ||
2932 | EXTRACT_IFMT_LDA_DISP_CODE | |
2933 | ||
2934 | /* Record the fields for the semantic handler. */ | |
2935 | FLD (f_optdisp) = f_optdisp; | |
2936 | FLD (f_scale) = f_scale; | |
2937 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2938 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
2939 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2940 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2941 | ||
2942 | #if WITH_PROFILE_MODEL_P | |
2943 | /* Record the fields for profiling. */ | |
2944 | if (PROFILE_MODEL_P (current_cpu)) | |
2945 | { | |
2946 | FLD (in_abase) = f_abase; | |
2947 | FLD (in_index) = f_index; | |
2948 | FLD (out_dst) = f_srcdst; | |
2949 | } | |
2950 | #endif | |
2951 | #undef FLD | |
2952 | BREAK (ex); | |
2953 | } | |
2954 | ||
2955 | CASE (ex, FMT_LDOB_OFFSET) : | |
2956 | { | |
2957 | CGEN_INSN_INT insn = base_insn; | |
2958 | #define FLD(f) abuf->fields.fmt_ldob_offset.f | |
2959 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
2960 | ||
2961 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
2962 | ||
2963 | /* Record the fields for the semantic handler. */ | |
2964 | FLD (f_offset) = f_offset; | |
2965 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2966 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2967 | ||
2968 | #if WITH_PROFILE_MODEL_P | |
2969 | /* Record the fields for profiling. */ | |
2970 | if (PROFILE_MODEL_P (current_cpu)) | |
2971 | { | |
2972 | FLD (out_dst) = f_srcdst; | |
2973 | } | |
2974 | #endif | |
2975 | #undef FLD | |
2976 | BREAK (ex); | |
2977 | } | |
2978 | ||
2979 | CASE (ex, FMT_LDOB_INDIRECT_OFFSET) : | |
2980 | { | |
2981 | CGEN_INSN_INT insn = base_insn; | |
2982 | #define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f | |
2983 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
2984 | ||
2985 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
2986 | ||
2987 | /* Record the fields for the semantic handler. */ | |
2988 | FLD (f_offset) = f_offset; | |
2989 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
2990 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
2991 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
2992 | ||
2993 | #if WITH_PROFILE_MODEL_P | |
2994 | /* Record the fields for profiling. */ | |
2995 | if (PROFILE_MODEL_P (current_cpu)) | |
2996 | { | |
2997 | FLD (in_abase) = f_abase; | |
2998 | FLD (out_dst) = f_srcdst; | |
2999 | } | |
3000 | #endif | |
3001 | #undef FLD | |
3002 | BREAK (ex); | |
3003 | } | |
3004 | ||
3005 | CASE (ex, FMT_LDOB_INDIRECT) : | |
3006 | { | |
3007 | CGEN_INSN_INT insn = base_insn; | |
3008 | #define FLD(f) abuf->fields.fmt_ldob_indirect.f | |
3009 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3010 | ||
3011 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3012 | ||
3013 | /* Record the fields for the semantic handler. */ | |
3014 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3015 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3016 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3017 | ||
3018 | #if WITH_PROFILE_MODEL_P | |
3019 | /* Record the fields for profiling. */ | |
3020 | if (PROFILE_MODEL_P (current_cpu)) | |
3021 | { | |
3022 | FLD (in_abase) = f_abase; | |
3023 | FLD (out_dst) = f_srcdst; | |
3024 | } | |
3025 | #endif | |
3026 | #undef FLD | |
3027 | BREAK (ex); | |
3028 | } | |
3029 | ||
3030 | CASE (ex, FMT_LDOB_INDIRECT_INDEX) : | |
3031 | { | |
3032 | CGEN_INSN_INT insn = base_insn; | |
3033 | #define FLD(f) abuf->fields.fmt_ldob_indirect_index.f | |
3034 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3035 | ||
3036 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3037 | ||
3038 | /* Record the fields for the semantic handler. */ | |
3039 | FLD (f_scale) = f_scale; | |
3040 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3041 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3042 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3043 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3044 | ||
3045 | #if WITH_PROFILE_MODEL_P | |
3046 | /* Record the fields for profiling. */ | |
3047 | if (PROFILE_MODEL_P (current_cpu)) | |
3048 | { | |
3049 | FLD (in_abase) = f_abase; | |
3050 | FLD (in_index) = f_index; | |
3051 | FLD (out_dst) = f_srcdst; | |
3052 | } | |
3053 | #endif | |
3054 | #undef FLD | |
3055 | BREAK (ex); | |
3056 | } | |
3057 | ||
3058 | CASE (ex, FMT_LDOB_DISP) : | |
3059 | { | |
3060 | CGEN_INSN_INT insn = base_insn; | |
3061 | #define FLD(f) abuf->fields.fmt_ldob_disp.f | |
3062 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3063 | ||
3064 | EXTRACT_IFMT_LDA_DISP_CODE | |
3065 | ||
3066 | /* Record the fields for the semantic handler. */ | |
3067 | FLD (f_optdisp) = f_optdisp; | |
3068 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3069 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3070 | ||
3071 | #if WITH_PROFILE_MODEL_P | |
3072 | /* Record the fields for profiling. */ | |
3073 | if (PROFILE_MODEL_P (current_cpu)) | |
3074 | { | |
3075 | FLD (out_dst) = f_srcdst; | |
3076 | } | |
3077 | #endif | |
3078 | #undef FLD | |
3079 | BREAK (ex); | |
3080 | } | |
3081 | ||
3082 | CASE (ex, FMT_LDOB_INDIRECT_DISP) : | |
3083 | { | |
3084 | CGEN_INSN_INT insn = base_insn; | |
3085 | #define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f | |
3086 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3087 | ||
3088 | EXTRACT_IFMT_LDA_DISP_CODE | |
3089 | ||
3090 | /* Record the fields for the semantic handler. */ | |
3091 | FLD (f_optdisp) = f_optdisp; | |
3092 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3093 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3094 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3095 | ||
3096 | #if WITH_PROFILE_MODEL_P | |
3097 | /* Record the fields for profiling. */ | |
3098 | if (PROFILE_MODEL_P (current_cpu)) | |
3099 | { | |
3100 | FLD (in_abase) = f_abase; | |
3101 | FLD (out_dst) = f_srcdst; | |
3102 | } | |
3103 | #endif | |
3104 | #undef FLD | |
3105 | BREAK (ex); | |
3106 | } | |
3107 | ||
3108 | CASE (ex, FMT_LDOB_INDEX_DISP) : | |
3109 | { | |
3110 | CGEN_INSN_INT insn = base_insn; | |
3111 | #define FLD(f) abuf->fields.fmt_ldob_index_disp.f | |
3112 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3113 | ||
3114 | EXTRACT_IFMT_LDA_DISP_CODE | |
3115 | ||
3116 | /* Record the fields for the semantic handler. */ | |
3117 | FLD (f_optdisp) = f_optdisp; | |
3118 | FLD (f_scale) = f_scale; | |
3119 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3120 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3121 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3122 | ||
3123 | #if WITH_PROFILE_MODEL_P | |
3124 | /* Record the fields for profiling. */ | |
3125 | if (PROFILE_MODEL_P (current_cpu)) | |
3126 | { | |
3127 | FLD (in_index) = f_index; | |
3128 | FLD (out_dst) = f_srcdst; | |
3129 | } | |
3130 | #endif | |
3131 | #undef FLD | |
3132 | BREAK (ex); | |
3133 | } | |
3134 | ||
3135 | CASE (ex, FMT_LDOB_INDIRECT_INDEX_DISP) : | |
3136 | { | |
3137 | CGEN_INSN_INT insn = base_insn; | |
3138 | #define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f | |
3139 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3140 | ||
3141 | EXTRACT_IFMT_LDA_DISP_CODE | |
3142 | ||
3143 | /* Record the fields for the semantic handler. */ | |
3144 | FLD (f_optdisp) = f_optdisp; | |
3145 | FLD (f_scale) = f_scale; | |
3146 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3147 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3148 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3149 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3150 | ||
3151 | #if WITH_PROFILE_MODEL_P | |
3152 | /* Record the fields for profiling. */ | |
3153 | if (PROFILE_MODEL_P (current_cpu)) | |
3154 | { | |
3155 | FLD (in_abase) = f_abase; | |
3156 | FLD (in_index) = f_index; | |
3157 | FLD (out_dst) = f_srcdst; | |
3158 | } | |
3159 | #endif | |
3160 | #undef FLD | |
3161 | BREAK (ex); | |
3162 | } | |
3163 | ||
3164 | CASE (ex, FMT_LDOS_OFFSET) : | |
3165 | { | |
3166 | CGEN_INSN_INT insn = base_insn; | |
3167 | #define FLD(f) abuf->fields.fmt_ldos_offset.f | |
3168 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3169 | ||
3170 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3171 | ||
3172 | /* Record the fields for the semantic handler. */ | |
3173 | FLD (f_offset) = f_offset; | |
3174 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3175 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3176 | ||
3177 | #if WITH_PROFILE_MODEL_P | |
3178 | /* Record the fields for profiling. */ | |
3179 | if (PROFILE_MODEL_P (current_cpu)) | |
3180 | { | |
3181 | FLD (out_dst) = f_srcdst; | |
3182 | } | |
3183 | #endif | |
3184 | #undef FLD | |
3185 | BREAK (ex); | |
3186 | } | |
3187 | ||
3188 | CASE (ex, FMT_LDOS_INDIRECT_OFFSET) : | |
3189 | { | |
3190 | CGEN_INSN_INT insn = base_insn; | |
3191 | #define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f | |
3192 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3193 | ||
3194 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3195 | ||
3196 | /* Record the fields for the semantic handler. */ | |
3197 | FLD (f_offset) = f_offset; | |
3198 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3199 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3200 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3201 | ||
3202 | #if WITH_PROFILE_MODEL_P | |
3203 | /* Record the fields for profiling. */ | |
3204 | if (PROFILE_MODEL_P (current_cpu)) | |
3205 | { | |
3206 | FLD (in_abase) = f_abase; | |
3207 | FLD (out_dst) = f_srcdst; | |
3208 | } | |
3209 | #endif | |
3210 | #undef FLD | |
3211 | BREAK (ex); | |
3212 | } | |
3213 | ||
3214 | CASE (ex, FMT_LDOS_INDIRECT) : | |
3215 | { | |
3216 | CGEN_INSN_INT insn = base_insn; | |
3217 | #define FLD(f) abuf->fields.fmt_ldos_indirect.f | |
3218 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3219 | ||
3220 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3221 | ||
3222 | /* Record the fields for the semantic handler. */ | |
3223 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3224 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3225 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3226 | ||
3227 | #if WITH_PROFILE_MODEL_P | |
3228 | /* Record the fields for profiling. */ | |
3229 | if (PROFILE_MODEL_P (current_cpu)) | |
3230 | { | |
3231 | FLD (in_abase) = f_abase; | |
3232 | FLD (out_dst) = f_srcdst; | |
3233 | } | |
3234 | #endif | |
3235 | #undef FLD | |
3236 | BREAK (ex); | |
3237 | } | |
3238 | ||
3239 | CASE (ex, FMT_LDOS_INDIRECT_INDEX) : | |
3240 | { | |
3241 | CGEN_INSN_INT insn = base_insn; | |
3242 | #define FLD(f) abuf->fields.fmt_ldos_indirect_index.f | |
3243 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3244 | ||
3245 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3246 | ||
3247 | /* Record the fields for the semantic handler. */ | |
3248 | FLD (f_scale) = f_scale; | |
3249 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3250 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3251 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3252 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3253 | ||
3254 | #if WITH_PROFILE_MODEL_P | |
3255 | /* Record the fields for profiling. */ | |
3256 | if (PROFILE_MODEL_P (current_cpu)) | |
3257 | { | |
3258 | FLD (in_abase) = f_abase; | |
3259 | FLD (in_index) = f_index; | |
3260 | FLD (out_dst) = f_srcdst; | |
3261 | } | |
3262 | #endif | |
3263 | #undef FLD | |
3264 | BREAK (ex); | |
3265 | } | |
3266 | ||
3267 | CASE (ex, FMT_LDOS_DISP) : | |
3268 | { | |
3269 | CGEN_INSN_INT insn = base_insn; | |
3270 | #define FLD(f) abuf->fields.fmt_ldos_disp.f | |
3271 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3272 | ||
3273 | EXTRACT_IFMT_LDA_DISP_CODE | |
3274 | ||
3275 | /* Record the fields for the semantic handler. */ | |
3276 | FLD (f_optdisp) = f_optdisp; | |
3277 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3278 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3279 | ||
3280 | #if WITH_PROFILE_MODEL_P | |
3281 | /* Record the fields for profiling. */ | |
3282 | if (PROFILE_MODEL_P (current_cpu)) | |
3283 | { | |
3284 | FLD (out_dst) = f_srcdst; | |
3285 | } | |
3286 | #endif | |
3287 | #undef FLD | |
3288 | BREAK (ex); | |
3289 | } | |
3290 | ||
3291 | CASE (ex, FMT_LDOS_INDIRECT_DISP) : | |
3292 | { | |
3293 | CGEN_INSN_INT insn = base_insn; | |
3294 | #define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f | |
3295 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3296 | ||
3297 | EXTRACT_IFMT_LDA_DISP_CODE | |
3298 | ||
3299 | /* Record the fields for the semantic handler. */ | |
3300 | FLD (f_optdisp) = f_optdisp; | |
3301 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3302 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3303 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3304 | ||
3305 | #if WITH_PROFILE_MODEL_P | |
3306 | /* Record the fields for profiling. */ | |
3307 | if (PROFILE_MODEL_P (current_cpu)) | |
3308 | { | |
3309 | FLD (in_abase) = f_abase; | |
3310 | FLD (out_dst) = f_srcdst; | |
3311 | } | |
3312 | #endif | |
3313 | #undef FLD | |
3314 | BREAK (ex); | |
3315 | } | |
3316 | ||
3317 | CASE (ex, FMT_LDOS_INDEX_DISP) : | |
3318 | { | |
3319 | CGEN_INSN_INT insn = base_insn; | |
3320 | #define FLD(f) abuf->fields.fmt_ldos_index_disp.f | |
3321 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3322 | ||
3323 | EXTRACT_IFMT_LDA_DISP_CODE | |
3324 | ||
3325 | /* Record the fields for the semantic handler. */ | |
3326 | FLD (f_optdisp) = f_optdisp; | |
3327 | FLD (f_scale) = f_scale; | |
3328 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3329 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3330 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3331 | ||
3332 | #if WITH_PROFILE_MODEL_P | |
3333 | /* Record the fields for profiling. */ | |
3334 | if (PROFILE_MODEL_P (current_cpu)) | |
3335 | { | |
3336 | FLD (in_index) = f_index; | |
3337 | FLD (out_dst) = f_srcdst; | |
3338 | } | |
3339 | #endif | |
3340 | #undef FLD | |
3341 | BREAK (ex); | |
3342 | } | |
3343 | ||
3344 | CASE (ex, FMT_LDOS_INDIRECT_INDEX_DISP) : | |
3345 | { | |
3346 | CGEN_INSN_INT insn = base_insn; | |
3347 | #define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f | |
3348 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3349 | ||
3350 | EXTRACT_IFMT_LDA_DISP_CODE | |
3351 | ||
3352 | /* Record the fields for the semantic handler. */ | |
3353 | FLD (f_optdisp) = f_optdisp; | |
3354 | FLD (f_scale) = f_scale; | |
3355 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3356 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3357 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3358 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3359 | ||
3360 | #if WITH_PROFILE_MODEL_P | |
3361 | /* Record the fields for profiling. */ | |
3362 | if (PROFILE_MODEL_P (current_cpu)) | |
3363 | { | |
3364 | FLD (in_abase) = f_abase; | |
3365 | FLD (in_index) = f_index; | |
3366 | FLD (out_dst) = f_srcdst; | |
3367 | } | |
3368 | #endif | |
3369 | #undef FLD | |
3370 | BREAK (ex); | |
3371 | } | |
3372 | ||
3373 | CASE (ex, FMT_LDIB_OFFSET) : | |
3374 | { | |
3375 | CGEN_INSN_INT insn = base_insn; | |
3376 | #define FLD(f) abuf->fields.fmt_ldib_offset.f | |
3377 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3378 | ||
3379 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3380 | ||
3381 | /* Record the fields for the semantic handler. */ | |
3382 | FLD (f_offset) = f_offset; | |
3383 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3384 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3385 | ||
3386 | #if WITH_PROFILE_MODEL_P | |
3387 | /* Record the fields for profiling. */ | |
3388 | if (PROFILE_MODEL_P (current_cpu)) | |
3389 | { | |
3390 | FLD (out_dst) = f_srcdst; | |
3391 | } | |
3392 | #endif | |
3393 | #undef FLD | |
3394 | BREAK (ex); | |
3395 | } | |
3396 | ||
3397 | CASE (ex, FMT_LDIB_INDIRECT_OFFSET) : | |
3398 | { | |
3399 | CGEN_INSN_INT insn = base_insn; | |
3400 | #define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f | |
3401 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3402 | ||
3403 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3404 | ||
3405 | /* Record the fields for the semantic handler. */ | |
3406 | FLD (f_offset) = f_offset; | |
3407 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3408 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3409 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3410 | ||
3411 | #if WITH_PROFILE_MODEL_P | |
3412 | /* Record the fields for profiling. */ | |
3413 | if (PROFILE_MODEL_P (current_cpu)) | |
3414 | { | |
3415 | FLD (in_abase) = f_abase; | |
3416 | FLD (out_dst) = f_srcdst; | |
3417 | } | |
3418 | #endif | |
3419 | #undef FLD | |
3420 | BREAK (ex); | |
3421 | } | |
3422 | ||
3423 | CASE (ex, FMT_LDIB_INDIRECT) : | |
3424 | { | |
3425 | CGEN_INSN_INT insn = base_insn; | |
3426 | #define FLD(f) abuf->fields.fmt_ldib_indirect.f | |
3427 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3428 | ||
3429 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3430 | ||
3431 | /* Record the fields for the semantic handler. */ | |
3432 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3433 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3434 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3435 | ||
3436 | #if WITH_PROFILE_MODEL_P | |
3437 | /* Record the fields for profiling. */ | |
3438 | if (PROFILE_MODEL_P (current_cpu)) | |
3439 | { | |
3440 | FLD (in_abase) = f_abase; | |
3441 | FLD (out_dst) = f_srcdst; | |
3442 | } | |
3443 | #endif | |
3444 | #undef FLD | |
3445 | BREAK (ex); | |
3446 | } | |
3447 | ||
3448 | CASE (ex, FMT_LDIB_INDIRECT_INDEX) : | |
3449 | { | |
3450 | CGEN_INSN_INT insn = base_insn; | |
3451 | #define FLD(f) abuf->fields.fmt_ldib_indirect_index.f | |
3452 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3453 | ||
3454 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3455 | ||
3456 | /* Record the fields for the semantic handler. */ | |
3457 | FLD (f_scale) = f_scale; | |
3458 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3459 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3460 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3461 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3462 | ||
3463 | #if WITH_PROFILE_MODEL_P | |
3464 | /* Record the fields for profiling. */ | |
3465 | if (PROFILE_MODEL_P (current_cpu)) | |
3466 | { | |
3467 | FLD (in_abase) = f_abase; | |
3468 | FLD (in_index) = f_index; | |
3469 | FLD (out_dst) = f_srcdst; | |
3470 | } | |
3471 | #endif | |
3472 | #undef FLD | |
3473 | BREAK (ex); | |
3474 | } | |
3475 | ||
3476 | CASE (ex, FMT_LDIB_DISP) : | |
3477 | { | |
3478 | CGEN_INSN_INT insn = base_insn; | |
3479 | #define FLD(f) abuf->fields.fmt_ldib_disp.f | |
3480 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3481 | ||
3482 | EXTRACT_IFMT_LDA_DISP_CODE | |
3483 | ||
3484 | /* Record the fields for the semantic handler. */ | |
3485 | FLD (f_optdisp) = f_optdisp; | |
3486 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3487 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3488 | ||
3489 | #if WITH_PROFILE_MODEL_P | |
3490 | /* Record the fields for profiling. */ | |
3491 | if (PROFILE_MODEL_P (current_cpu)) | |
3492 | { | |
3493 | FLD (out_dst) = f_srcdst; | |
3494 | } | |
3495 | #endif | |
3496 | #undef FLD | |
3497 | BREAK (ex); | |
3498 | } | |
3499 | ||
3500 | CASE (ex, FMT_LDIB_INDIRECT_DISP) : | |
3501 | { | |
3502 | CGEN_INSN_INT insn = base_insn; | |
3503 | #define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f | |
3504 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3505 | ||
3506 | EXTRACT_IFMT_LDA_DISP_CODE | |
3507 | ||
3508 | /* Record the fields for the semantic handler. */ | |
3509 | FLD (f_optdisp) = f_optdisp; | |
3510 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3511 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3512 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3513 | ||
3514 | #if WITH_PROFILE_MODEL_P | |
3515 | /* Record the fields for profiling. */ | |
3516 | if (PROFILE_MODEL_P (current_cpu)) | |
3517 | { | |
3518 | FLD (in_abase) = f_abase; | |
3519 | FLD (out_dst) = f_srcdst; | |
3520 | } | |
3521 | #endif | |
3522 | #undef FLD | |
3523 | BREAK (ex); | |
3524 | } | |
3525 | ||
3526 | CASE (ex, FMT_LDIB_INDEX_DISP) : | |
3527 | { | |
3528 | CGEN_INSN_INT insn = base_insn; | |
3529 | #define FLD(f) abuf->fields.fmt_ldib_index_disp.f | |
3530 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3531 | ||
3532 | EXTRACT_IFMT_LDA_DISP_CODE | |
3533 | ||
3534 | /* Record the fields for the semantic handler. */ | |
3535 | FLD (f_optdisp) = f_optdisp; | |
3536 | FLD (f_scale) = f_scale; | |
3537 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3538 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3539 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3540 | ||
3541 | #if WITH_PROFILE_MODEL_P | |
3542 | /* Record the fields for profiling. */ | |
3543 | if (PROFILE_MODEL_P (current_cpu)) | |
3544 | { | |
3545 | FLD (in_index) = f_index; | |
3546 | FLD (out_dst) = f_srcdst; | |
3547 | } | |
3548 | #endif | |
3549 | #undef FLD | |
3550 | BREAK (ex); | |
3551 | } | |
3552 | ||
3553 | CASE (ex, FMT_LDIB_INDIRECT_INDEX_DISP) : | |
3554 | { | |
3555 | CGEN_INSN_INT insn = base_insn; | |
3556 | #define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f | |
3557 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3558 | ||
3559 | EXTRACT_IFMT_LDA_DISP_CODE | |
3560 | ||
3561 | /* Record the fields for the semantic handler. */ | |
3562 | FLD (f_optdisp) = f_optdisp; | |
3563 | FLD (f_scale) = f_scale; | |
3564 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3565 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3566 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3567 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3568 | ||
3569 | #if WITH_PROFILE_MODEL_P | |
3570 | /* Record the fields for profiling. */ | |
3571 | if (PROFILE_MODEL_P (current_cpu)) | |
3572 | { | |
3573 | FLD (in_abase) = f_abase; | |
3574 | FLD (in_index) = f_index; | |
3575 | FLD (out_dst) = f_srcdst; | |
3576 | } | |
3577 | #endif | |
3578 | #undef FLD | |
3579 | BREAK (ex); | |
3580 | } | |
3581 | ||
3582 | CASE (ex, FMT_LDIS_OFFSET) : | |
3583 | { | |
3584 | CGEN_INSN_INT insn = base_insn; | |
3585 | #define FLD(f) abuf->fields.fmt_ldis_offset.f | |
3586 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3587 | ||
3588 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3589 | ||
3590 | /* Record the fields for the semantic handler. */ | |
3591 | FLD (f_offset) = f_offset; | |
3592 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3593 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3594 | ||
3595 | #if WITH_PROFILE_MODEL_P | |
3596 | /* Record the fields for profiling. */ | |
3597 | if (PROFILE_MODEL_P (current_cpu)) | |
3598 | { | |
3599 | FLD (out_dst) = f_srcdst; | |
3600 | } | |
3601 | #endif | |
3602 | #undef FLD | |
3603 | BREAK (ex); | |
3604 | } | |
3605 | ||
3606 | CASE (ex, FMT_LDIS_INDIRECT_OFFSET) : | |
3607 | { | |
3608 | CGEN_INSN_INT insn = base_insn; | |
3609 | #define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f | |
3610 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3611 | ||
3612 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3613 | ||
3614 | /* Record the fields for the semantic handler. */ | |
3615 | FLD (f_offset) = f_offset; | |
3616 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3617 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3618 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3619 | ||
3620 | #if WITH_PROFILE_MODEL_P | |
3621 | /* Record the fields for profiling. */ | |
3622 | if (PROFILE_MODEL_P (current_cpu)) | |
3623 | { | |
3624 | FLD (in_abase) = f_abase; | |
3625 | FLD (out_dst) = f_srcdst; | |
3626 | } | |
3627 | #endif | |
3628 | #undef FLD | |
3629 | BREAK (ex); | |
3630 | } | |
3631 | ||
3632 | CASE (ex, FMT_LDIS_INDIRECT) : | |
3633 | { | |
3634 | CGEN_INSN_INT insn = base_insn; | |
3635 | #define FLD(f) abuf->fields.fmt_ldis_indirect.f | |
3636 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3637 | ||
3638 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3639 | ||
3640 | /* Record the fields for the semantic handler. */ | |
3641 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3642 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3643 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3644 | ||
3645 | #if WITH_PROFILE_MODEL_P | |
3646 | /* Record the fields for profiling. */ | |
3647 | if (PROFILE_MODEL_P (current_cpu)) | |
3648 | { | |
3649 | FLD (in_abase) = f_abase; | |
3650 | FLD (out_dst) = f_srcdst; | |
3651 | } | |
3652 | #endif | |
3653 | #undef FLD | |
3654 | BREAK (ex); | |
3655 | } | |
3656 | ||
3657 | CASE (ex, FMT_LDIS_INDIRECT_INDEX) : | |
3658 | { | |
3659 | CGEN_INSN_INT insn = base_insn; | |
3660 | #define FLD(f) abuf->fields.fmt_ldis_indirect_index.f | |
3661 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3662 | ||
3663 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3664 | ||
3665 | /* Record the fields for the semantic handler. */ | |
3666 | FLD (f_scale) = f_scale; | |
3667 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3668 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3669 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3670 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3671 | ||
3672 | #if WITH_PROFILE_MODEL_P | |
3673 | /* Record the fields for profiling. */ | |
3674 | if (PROFILE_MODEL_P (current_cpu)) | |
3675 | { | |
3676 | FLD (in_abase) = f_abase; | |
3677 | FLD (in_index) = f_index; | |
3678 | FLD (out_dst) = f_srcdst; | |
3679 | } | |
3680 | #endif | |
3681 | #undef FLD | |
3682 | BREAK (ex); | |
3683 | } | |
3684 | ||
3685 | CASE (ex, FMT_LDIS_DISP) : | |
3686 | { | |
3687 | CGEN_INSN_INT insn = base_insn; | |
3688 | #define FLD(f) abuf->fields.fmt_ldis_disp.f | |
3689 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3690 | ||
3691 | EXTRACT_IFMT_LDA_DISP_CODE | |
3692 | ||
3693 | /* Record the fields for the semantic handler. */ | |
3694 | FLD (f_optdisp) = f_optdisp; | |
3695 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3696 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3697 | ||
3698 | #if WITH_PROFILE_MODEL_P | |
3699 | /* Record the fields for profiling. */ | |
3700 | if (PROFILE_MODEL_P (current_cpu)) | |
3701 | { | |
3702 | FLD (out_dst) = f_srcdst; | |
3703 | } | |
3704 | #endif | |
3705 | #undef FLD | |
3706 | BREAK (ex); | |
3707 | } | |
3708 | ||
3709 | CASE (ex, FMT_LDIS_INDIRECT_DISP) : | |
3710 | { | |
3711 | CGEN_INSN_INT insn = base_insn; | |
3712 | #define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f | |
3713 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3714 | ||
3715 | EXTRACT_IFMT_LDA_DISP_CODE | |
3716 | ||
3717 | /* Record the fields for the semantic handler. */ | |
3718 | FLD (f_optdisp) = f_optdisp; | |
3719 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3720 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3721 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3722 | ||
3723 | #if WITH_PROFILE_MODEL_P | |
3724 | /* Record the fields for profiling. */ | |
3725 | if (PROFILE_MODEL_P (current_cpu)) | |
3726 | { | |
3727 | FLD (in_abase) = f_abase; | |
3728 | FLD (out_dst) = f_srcdst; | |
3729 | } | |
3730 | #endif | |
3731 | #undef FLD | |
3732 | BREAK (ex); | |
3733 | } | |
3734 | ||
3735 | CASE (ex, FMT_LDIS_INDEX_DISP) : | |
3736 | { | |
3737 | CGEN_INSN_INT insn = base_insn; | |
3738 | #define FLD(f) abuf->fields.fmt_ldis_index_disp.f | |
3739 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3740 | ||
3741 | EXTRACT_IFMT_LDA_DISP_CODE | |
3742 | ||
3743 | /* Record the fields for the semantic handler. */ | |
3744 | FLD (f_optdisp) = f_optdisp; | |
3745 | FLD (f_scale) = f_scale; | |
3746 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3747 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3748 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3749 | ||
3750 | #if WITH_PROFILE_MODEL_P | |
3751 | /* Record the fields for profiling. */ | |
3752 | if (PROFILE_MODEL_P (current_cpu)) | |
3753 | { | |
3754 | FLD (in_index) = f_index; | |
3755 | FLD (out_dst) = f_srcdst; | |
3756 | } | |
3757 | #endif | |
3758 | #undef FLD | |
3759 | BREAK (ex); | |
3760 | } | |
3761 | ||
3762 | CASE (ex, FMT_LDIS_INDIRECT_INDEX_DISP) : | |
3763 | { | |
3764 | CGEN_INSN_INT insn = base_insn; | |
3765 | #define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f | |
3766 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3767 | ||
3768 | EXTRACT_IFMT_LDA_DISP_CODE | |
3769 | ||
3770 | /* Record the fields for the semantic handler. */ | |
3771 | FLD (f_optdisp) = f_optdisp; | |
3772 | FLD (f_scale) = f_scale; | |
3773 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3774 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3775 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3776 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3777 | ||
3778 | #if WITH_PROFILE_MODEL_P | |
3779 | /* Record the fields for profiling. */ | |
3780 | if (PROFILE_MODEL_P (current_cpu)) | |
3781 | { | |
3782 | FLD (in_abase) = f_abase; | |
3783 | FLD (in_index) = f_index; | |
3784 | FLD (out_dst) = f_srcdst; | |
3785 | } | |
3786 | #endif | |
3787 | #undef FLD | |
3788 | BREAK (ex); | |
3789 | } | |
3790 | ||
3791 | CASE (ex, FMT_LDL_OFFSET) : | |
3792 | { | |
3793 | CGEN_INSN_INT insn = base_insn; | |
3794 | #define FLD(f) abuf->fields.fmt_ldl_offset.f | |
3795 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3796 | ||
3797 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3798 | ||
3799 | /* Record the fields for the semantic handler. */ | |
3800 | FLD (f_srcdst) = f_srcdst; | |
3801 | FLD (f_offset) = f_offset; | |
3802 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3803 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3804 | ||
3805 | #if WITH_PROFILE_MODEL_P | |
3806 | /* Record the fields for profiling. */ | |
3807 | if (PROFILE_MODEL_P (current_cpu)) | |
3808 | { | |
3809 | FLD (out_dst) = f_srcdst; | |
3810 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
3811 | } | |
3812 | #endif | |
3813 | #undef FLD | |
3814 | BREAK (ex); | |
3815 | } | |
3816 | ||
3817 | CASE (ex, FMT_LDL_INDIRECT_OFFSET) : | |
3818 | { | |
3819 | CGEN_INSN_INT insn = base_insn; | |
3820 | #define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f | |
3821 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
3822 | ||
3823 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
3824 | ||
3825 | /* Record the fields for the semantic handler. */ | |
3826 | FLD (f_srcdst) = f_srcdst; | |
3827 | FLD (f_offset) = f_offset; | |
3828 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3829 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3830 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3831 | ||
3832 | #if WITH_PROFILE_MODEL_P | |
3833 | /* Record the fields for profiling. */ | |
3834 | if (PROFILE_MODEL_P (current_cpu)) | |
3835 | { | |
3836 | FLD (in_abase) = f_abase; | |
3837 | FLD (out_dst) = f_srcdst; | |
3838 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
3839 | } | |
3840 | #endif | |
3841 | #undef FLD | |
3842 | BREAK (ex); | |
3843 | } | |
3844 | ||
3845 | CASE (ex, FMT_LDL_INDIRECT) : | |
3846 | { | |
3847 | CGEN_INSN_INT insn = base_insn; | |
3848 | #define FLD(f) abuf->fields.fmt_ldl_indirect.f | |
3849 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3850 | ||
3851 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3852 | ||
3853 | /* Record the fields for the semantic handler. */ | |
3854 | FLD (f_srcdst) = f_srcdst; | |
3855 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3856 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3857 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3858 | ||
3859 | #if WITH_PROFILE_MODEL_P | |
3860 | /* Record the fields for profiling. */ | |
3861 | if (PROFILE_MODEL_P (current_cpu)) | |
3862 | { | |
3863 | FLD (in_abase) = f_abase; | |
3864 | FLD (out_dst) = f_srcdst; | |
3865 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
3866 | } | |
3867 | #endif | |
3868 | #undef FLD | |
3869 | BREAK (ex); | |
3870 | } | |
3871 | ||
3872 | CASE (ex, FMT_LDL_INDIRECT_INDEX) : | |
3873 | { | |
3874 | CGEN_INSN_INT insn = base_insn; | |
3875 | #define FLD(f) abuf->fields.fmt_ldl_indirect_index.f | |
3876 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3877 | ||
3878 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
3879 | ||
3880 | /* Record the fields for the semantic handler. */ | |
3881 | FLD (f_srcdst) = f_srcdst; | |
3882 | FLD (f_scale) = f_scale; | |
3883 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3884 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3885 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3886 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3887 | ||
3888 | #if WITH_PROFILE_MODEL_P | |
3889 | /* Record the fields for profiling. */ | |
3890 | if (PROFILE_MODEL_P (current_cpu)) | |
3891 | { | |
3892 | FLD (in_abase) = f_abase; | |
3893 | FLD (in_index) = f_index; | |
3894 | FLD (out_dst) = f_srcdst; | |
3895 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
3896 | } | |
3897 | #endif | |
3898 | #undef FLD | |
3899 | BREAK (ex); | |
3900 | } | |
3901 | ||
3902 | CASE (ex, FMT_LDL_DISP) : | |
3903 | { | |
3904 | CGEN_INSN_INT insn = base_insn; | |
3905 | #define FLD(f) abuf->fields.fmt_ldl_disp.f | |
3906 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3907 | ||
3908 | EXTRACT_IFMT_LDA_DISP_CODE | |
3909 | ||
3910 | /* Record the fields for the semantic handler. */ | |
3911 | FLD (f_srcdst) = f_srcdst; | |
3912 | FLD (f_optdisp) = f_optdisp; | |
3913 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3914 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3915 | ||
3916 | #if WITH_PROFILE_MODEL_P | |
3917 | /* Record the fields for profiling. */ | |
3918 | if (PROFILE_MODEL_P (current_cpu)) | |
3919 | { | |
3920 | FLD (out_dst) = f_srcdst; | |
3921 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
3922 | } | |
3923 | #endif | |
3924 | #undef FLD | |
3925 | BREAK (ex); | |
3926 | } | |
3927 | ||
3928 | CASE (ex, FMT_LDL_INDIRECT_DISP) : | |
3929 | { | |
3930 | CGEN_INSN_INT insn = base_insn; | |
3931 | #define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f | |
3932 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3933 | ||
3934 | EXTRACT_IFMT_LDA_DISP_CODE | |
3935 | ||
3936 | /* Record the fields for the semantic handler. */ | |
3937 | FLD (f_srcdst) = f_srcdst; | |
3938 | FLD (f_optdisp) = f_optdisp; | |
3939 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3940 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3941 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3942 | ||
3943 | #if WITH_PROFILE_MODEL_P | |
3944 | /* Record the fields for profiling. */ | |
3945 | if (PROFILE_MODEL_P (current_cpu)) | |
3946 | { | |
3947 | FLD (in_abase) = f_abase; | |
3948 | FLD (out_dst) = f_srcdst; | |
3949 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
3950 | } | |
3951 | #endif | |
3952 | #undef FLD | |
3953 | BREAK (ex); | |
3954 | } | |
3955 | ||
3956 | CASE (ex, FMT_LDL_INDEX_DISP) : | |
3957 | { | |
3958 | CGEN_INSN_INT insn = base_insn; | |
3959 | #define FLD(f) abuf->fields.fmt_ldl_index_disp.f | |
3960 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3961 | ||
3962 | EXTRACT_IFMT_LDA_DISP_CODE | |
3963 | ||
3964 | /* Record the fields for the semantic handler. */ | |
3965 | FLD (f_srcdst) = f_srcdst; | |
3966 | FLD (f_optdisp) = f_optdisp; | |
3967 | FLD (f_scale) = f_scale; | |
3968 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3969 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
3970 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
3971 | ||
3972 | #if WITH_PROFILE_MODEL_P | |
3973 | /* Record the fields for profiling. */ | |
3974 | if (PROFILE_MODEL_P (current_cpu)) | |
3975 | { | |
3976 | FLD (in_index) = f_index; | |
3977 | FLD (out_dst) = f_srcdst; | |
3978 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
3979 | } | |
3980 | #endif | |
3981 | #undef FLD | |
3982 | BREAK (ex); | |
3983 | } | |
3984 | ||
3985 | CASE (ex, FMT_LDL_INDIRECT_INDEX_DISP) : | |
3986 | { | |
3987 | CGEN_INSN_INT insn = base_insn; | |
3988 | #define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f | |
3989 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
3990 | ||
3991 | EXTRACT_IFMT_LDA_DISP_CODE | |
3992 | ||
3993 | /* Record the fields for the semantic handler. */ | |
3994 | FLD (f_srcdst) = f_srcdst; | |
3995 | FLD (f_optdisp) = f_optdisp; | |
3996 | FLD (f_scale) = f_scale; | |
3997 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
3998 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
3999 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4000 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4001 | ||
4002 | #if WITH_PROFILE_MODEL_P | |
4003 | /* Record the fields for profiling. */ | |
4004 | if (PROFILE_MODEL_P (current_cpu)) | |
4005 | { | |
4006 | FLD (in_abase) = f_abase; | |
4007 | FLD (in_index) = f_index; | |
4008 | FLD (out_dst) = f_srcdst; | |
4009 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4010 | } | |
4011 | #endif | |
4012 | #undef FLD | |
4013 | BREAK (ex); | |
4014 | } | |
4015 | ||
4016 | CASE (ex, FMT_LDT_OFFSET) : | |
4017 | { | |
4018 | CGEN_INSN_INT insn = base_insn; | |
4019 | #define FLD(f) abuf->fields.fmt_ldt_offset.f | |
4020 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4021 | ||
4022 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
4023 | ||
4024 | /* Record the fields for the semantic handler. */ | |
4025 | FLD (f_srcdst) = f_srcdst; | |
4026 | FLD (f_offset) = f_offset; | |
4027 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4028 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4029 | ||
4030 | #if WITH_PROFILE_MODEL_P | |
4031 | /* Record the fields for profiling. */ | |
4032 | if (PROFILE_MODEL_P (current_cpu)) | |
4033 | { | |
4034 | FLD (out_dst) = f_srcdst; | |
4035 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4036 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4037 | } | |
4038 | #endif | |
4039 | #undef FLD | |
4040 | BREAK (ex); | |
4041 | } | |
4042 | ||
4043 | CASE (ex, FMT_LDT_INDIRECT_OFFSET) : | |
4044 | { | |
4045 | CGEN_INSN_INT insn = base_insn; | |
4046 | #define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f | |
4047 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4048 | ||
4049 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
4050 | ||
4051 | /* Record the fields for the semantic handler. */ | |
4052 | FLD (f_srcdst) = f_srcdst; | |
4053 | FLD (f_offset) = f_offset; | |
4054 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4055 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4056 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4057 | ||
4058 | #if WITH_PROFILE_MODEL_P | |
4059 | /* Record the fields for profiling. */ | |
4060 | if (PROFILE_MODEL_P (current_cpu)) | |
4061 | { | |
4062 | FLD (in_abase) = f_abase; | |
4063 | FLD (out_dst) = f_srcdst; | |
4064 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4065 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4066 | } | |
4067 | #endif | |
4068 | #undef FLD | |
4069 | BREAK (ex); | |
4070 | } | |
4071 | ||
4072 | CASE (ex, FMT_LDT_INDIRECT) : | |
4073 | { | |
4074 | CGEN_INSN_INT insn = base_insn; | |
4075 | #define FLD(f) abuf->fields.fmt_ldt_indirect.f | |
4076 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4077 | ||
4078 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
4079 | ||
4080 | /* Record the fields for the semantic handler. */ | |
4081 | FLD (f_srcdst) = f_srcdst; | |
4082 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4083 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4084 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4085 | ||
4086 | #if WITH_PROFILE_MODEL_P | |
4087 | /* Record the fields for profiling. */ | |
4088 | if (PROFILE_MODEL_P (current_cpu)) | |
4089 | { | |
4090 | FLD (in_abase) = f_abase; | |
4091 | FLD (out_dst) = f_srcdst; | |
4092 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4093 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4094 | } | |
4095 | #endif | |
4096 | #undef FLD | |
4097 | BREAK (ex); | |
4098 | } | |
4099 | ||
4100 | CASE (ex, FMT_LDT_INDIRECT_INDEX) : | |
4101 | { | |
4102 | CGEN_INSN_INT insn = base_insn; | |
4103 | #define FLD(f) abuf->fields.fmt_ldt_indirect_index.f | |
4104 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4105 | ||
4106 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
4107 | ||
4108 | /* Record the fields for the semantic handler. */ | |
4109 | FLD (f_srcdst) = f_srcdst; | |
4110 | FLD (f_scale) = f_scale; | |
4111 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4112 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4113 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4114 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4115 | ||
4116 | #if WITH_PROFILE_MODEL_P | |
4117 | /* Record the fields for profiling. */ | |
4118 | if (PROFILE_MODEL_P (current_cpu)) | |
4119 | { | |
4120 | FLD (in_abase) = f_abase; | |
4121 | FLD (in_index) = f_index; | |
4122 | FLD (out_dst) = f_srcdst; | |
4123 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4124 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4125 | } | |
4126 | #endif | |
4127 | #undef FLD | |
4128 | BREAK (ex); | |
4129 | } | |
4130 | ||
4131 | CASE (ex, FMT_LDT_DISP) : | |
4132 | { | |
4133 | CGEN_INSN_INT insn = base_insn; | |
4134 | #define FLD(f) abuf->fields.fmt_ldt_disp.f | |
4135 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4136 | ||
4137 | EXTRACT_IFMT_LDA_DISP_CODE | |
4138 | ||
4139 | /* Record the fields for the semantic handler. */ | |
4140 | FLD (f_srcdst) = f_srcdst; | |
4141 | FLD (f_optdisp) = f_optdisp; | |
4142 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4143 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4144 | ||
4145 | #if WITH_PROFILE_MODEL_P | |
4146 | /* Record the fields for profiling. */ | |
4147 | if (PROFILE_MODEL_P (current_cpu)) | |
4148 | { | |
4149 | FLD (out_dst) = f_srcdst; | |
4150 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4151 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4152 | } | |
4153 | #endif | |
4154 | #undef FLD | |
4155 | BREAK (ex); | |
4156 | } | |
4157 | ||
4158 | CASE (ex, FMT_LDT_INDIRECT_DISP) : | |
4159 | { | |
4160 | CGEN_INSN_INT insn = base_insn; | |
4161 | #define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f | |
4162 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4163 | ||
4164 | EXTRACT_IFMT_LDA_DISP_CODE | |
4165 | ||
4166 | /* Record the fields for the semantic handler. */ | |
4167 | FLD (f_srcdst) = f_srcdst; | |
4168 | FLD (f_optdisp) = f_optdisp; | |
4169 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4170 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4171 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4172 | ||
4173 | #if WITH_PROFILE_MODEL_P | |
4174 | /* Record the fields for profiling. */ | |
4175 | if (PROFILE_MODEL_P (current_cpu)) | |
4176 | { | |
4177 | FLD (in_abase) = f_abase; | |
4178 | FLD (out_dst) = f_srcdst; | |
4179 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4180 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4181 | } | |
4182 | #endif | |
4183 | #undef FLD | |
4184 | BREAK (ex); | |
4185 | } | |
4186 | ||
4187 | CASE (ex, FMT_LDT_INDEX_DISP) : | |
4188 | { | |
4189 | CGEN_INSN_INT insn = base_insn; | |
4190 | #define FLD(f) abuf->fields.fmt_ldt_index_disp.f | |
4191 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4192 | ||
4193 | EXTRACT_IFMT_LDA_DISP_CODE | |
4194 | ||
4195 | /* Record the fields for the semantic handler. */ | |
4196 | FLD (f_srcdst) = f_srcdst; | |
4197 | FLD (f_optdisp) = f_optdisp; | |
4198 | FLD (f_scale) = f_scale; | |
4199 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4200 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4201 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4202 | ||
4203 | #if WITH_PROFILE_MODEL_P | |
4204 | /* Record the fields for profiling. */ | |
4205 | if (PROFILE_MODEL_P (current_cpu)) | |
4206 | { | |
4207 | FLD (in_index) = f_index; | |
4208 | FLD (out_dst) = f_srcdst; | |
4209 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4210 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4211 | } | |
4212 | #endif | |
4213 | #undef FLD | |
4214 | BREAK (ex); | |
4215 | } | |
4216 | ||
4217 | CASE (ex, FMT_LDT_INDIRECT_INDEX_DISP) : | |
4218 | { | |
4219 | CGEN_INSN_INT insn = base_insn; | |
4220 | #define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f | |
4221 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4222 | ||
4223 | EXTRACT_IFMT_LDA_DISP_CODE | |
4224 | ||
4225 | /* Record the fields for the semantic handler. */ | |
4226 | FLD (f_srcdst) = f_srcdst; | |
4227 | FLD (f_optdisp) = f_optdisp; | |
4228 | FLD (f_scale) = f_scale; | |
4229 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4230 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4231 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4232 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4233 | ||
4234 | #if WITH_PROFILE_MODEL_P | |
4235 | /* Record the fields for profiling. */ | |
4236 | if (PROFILE_MODEL_P (current_cpu)) | |
4237 | { | |
4238 | FLD (in_abase) = f_abase; | |
4239 | FLD (in_index) = f_index; | |
4240 | FLD (out_dst) = f_srcdst; | |
4241 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4242 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4243 | } | |
4244 | #endif | |
4245 | #undef FLD | |
4246 | BREAK (ex); | |
4247 | } | |
4248 | ||
4249 | CASE (ex, FMT_LDQ_OFFSET) : | |
4250 | { | |
4251 | CGEN_INSN_INT insn = base_insn; | |
4252 | #define FLD(f) abuf->fields.fmt_ldq_offset.f | |
4253 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4254 | ||
4255 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
4256 | ||
4257 | /* Record the fields for the semantic handler. */ | |
4258 | FLD (f_srcdst) = f_srcdst; | |
4259 | FLD (f_offset) = f_offset; | |
4260 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4261 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4262 | ||
4263 | #if WITH_PROFILE_MODEL_P | |
4264 | /* Record the fields for profiling. */ | |
4265 | if (PROFILE_MODEL_P (current_cpu)) | |
4266 | { | |
4267 | FLD (out_dst) = f_srcdst; | |
4268 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4269 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4270 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4271 | } | |
4272 | #endif | |
4273 | #undef FLD | |
4274 | BREAK (ex); | |
4275 | } | |
4276 | ||
4277 | CASE (ex, FMT_LDQ_INDIRECT_OFFSET) : | |
4278 | { | |
4279 | CGEN_INSN_INT insn = base_insn; | |
4280 | #define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f | |
4281 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4282 | ||
4283 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
4284 | ||
4285 | /* Record the fields for the semantic handler. */ | |
4286 | FLD (f_srcdst) = f_srcdst; | |
4287 | FLD (f_offset) = f_offset; | |
4288 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4289 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4290 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4291 | ||
4292 | #if WITH_PROFILE_MODEL_P | |
4293 | /* Record the fields for profiling. */ | |
4294 | if (PROFILE_MODEL_P (current_cpu)) | |
4295 | { | |
4296 | FLD (in_abase) = f_abase; | |
4297 | FLD (out_dst) = f_srcdst; | |
4298 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4299 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4300 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4301 | } | |
4302 | #endif | |
4303 | #undef FLD | |
4304 | BREAK (ex); | |
4305 | } | |
4306 | ||
4307 | CASE (ex, FMT_LDQ_INDIRECT) : | |
4308 | { | |
4309 | CGEN_INSN_INT insn = base_insn; | |
4310 | #define FLD(f) abuf->fields.fmt_ldq_indirect.f | |
4311 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4312 | ||
4313 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
4314 | ||
4315 | /* Record the fields for the semantic handler. */ | |
4316 | FLD (f_srcdst) = f_srcdst; | |
4317 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4318 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4319 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4320 | ||
4321 | #if WITH_PROFILE_MODEL_P | |
4322 | /* Record the fields for profiling. */ | |
4323 | if (PROFILE_MODEL_P (current_cpu)) | |
4324 | { | |
4325 | FLD (in_abase) = f_abase; | |
4326 | FLD (out_dst) = f_srcdst; | |
4327 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4328 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4329 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4330 | } | |
4331 | #endif | |
4332 | #undef FLD | |
4333 | BREAK (ex); | |
4334 | } | |
4335 | ||
4336 | CASE (ex, FMT_LDQ_INDIRECT_INDEX) : | |
4337 | { | |
4338 | CGEN_INSN_INT insn = base_insn; | |
4339 | #define FLD(f) abuf->fields.fmt_ldq_indirect_index.f | |
4340 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4341 | ||
4342 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
4343 | ||
4344 | /* Record the fields for the semantic handler. */ | |
4345 | FLD (f_srcdst) = f_srcdst; | |
4346 | FLD (f_scale) = f_scale; | |
4347 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4348 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4349 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4350 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4351 | ||
4352 | #if WITH_PROFILE_MODEL_P | |
4353 | /* Record the fields for profiling. */ | |
4354 | if (PROFILE_MODEL_P (current_cpu)) | |
4355 | { | |
4356 | FLD (in_abase) = f_abase; | |
4357 | FLD (in_index) = f_index; | |
4358 | FLD (out_dst) = f_srcdst; | |
4359 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4360 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4361 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4362 | } | |
4363 | #endif | |
4364 | #undef FLD | |
4365 | BREAK (ex); | |
4366 | } | |
4367 | ||
4368 | CASE (ex, FMT_LDQ_DISP) : | |
4369 | { | |
4370 | CGEN_INSN_INT insn = base_insn; | |
4371 | #define FLD(f) abuf->fields.fmt_ldq_disp.f | |
4372 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4373 | ||
4374 | EXTRACT_IFMT_LDA_DISP_CODE | |
4375 | ||
4376 | /* Record the fields for the semantic handler. */ | |
4377 | FLD (f_srcdst) = f_srcdst; | |
4378 | FLD (f_optdisp) = f_optdisp; | |
4379 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4380 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4381 | ||
4382 | #if WITH_PROFILE_MODEL_P | |
4383 | /* Record the fields for profiling. */ | |
4384 | if (PROFILE_MODEL_P (current_cpu)) | |
4385 | { | |
4386 | FLD (out_dst) = f_srcdst; | |
4387 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4388 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4389 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4390 | } | |
4391 | #endif | |
4392 | #undef FLD | |
4393 | BREAK (ex); | |
4394 | } | |
4395 | ||
4396 | CASE (ex, FMT_LDQ_INDIRECT_DISP) : | |
4397 | { | |
4398 | CGEN_INSN_INT insn = base_insn; | |
4399 | #define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f | |
4400 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4401 | ||
4402 | EXTRACT_IFMT_LDA_DISP_CODE | |
4403 | ||
4404 | /* Record the fields for the semantic handler. */ | |
4405 | FLD (f_srcdst) = f_srcdst; | |
4406 | FLD (f_optdisp) = f_optdisp; | |
4407 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4408 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4409 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4410 | ||
4411 | #if WITH_PROFILE_MODEL_P | |
4412 | /* Record the fields for profiling. */ | |
4413 | if (PROFILE_MODEL_P (current_cpu)) | |
4414 | { | |
4415 | FLD (in_abase) = f_abase; | |
4416 | FLD (out_dst) = f_srcdst; | |
4417 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4418 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4419 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4420 | } | |
4421 | #endif | |
4422 | #undef FLD | |
4423 | BREAK (ex); | |
4424 | } | |
4425 | ||
4426 | CASE (ex, FMT_LDQ_INDEX_DISP) : | |
4427 | { | |
4428 | CGEN_INSN_INT insn = base_insn; | |
4429 | #define FLD(f) abuf->fields.fmt_ldq_index_disp.f | |
4430 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4431 | ||
4432 | EXTRACT_IFMT_LDA_DISP_CODE | |
4433 | ||
4434 | /* Record the fields for the semantic handler. */ | |
4435 | FLD (f_srcdst) = f_srcdst; | |
4436 | FLD (f_optdisp) = f_optdisp; | |
4437 | FLD (f_scale) = f_scale; | |
4438 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4439 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4440 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4441 | ||
4442 | #if WITH_PROFILE_MODEL_P | |
4443 | /* Record the fields for profiling. */ | |
4444 | if (PROFILE_MODEL_P (current_cpu)) | |
4445 | { | |
4446 | FLD (in_index) = f_index; | |
4447 | FLD (out_dst) = f_srcdst; | |
4448 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4449 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4450 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4451 | } | |
4452 | #endif | |
4453 | #undef FLD | |
4454 | BREAK (ex); | |
4455 | } | |
4456 | ||
4457 | CASE (ex, FMT_LDQ_INDIRECT_INDEX_DISP) : | |
4458 | { | |
4459 | CGEN_INSN_INT insn = base_insn; | |
4460 | #define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f | |
4461 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4462 | ||
4463 | EXTRACT_IFMT_LDA_DISP_CODE | |
4464 | ||
4465 | /* Record the fields for the semantic handler. */ | |
4466 | FLD (f_srcdst) = f_srcdst; | |
4467 | FLD (f_optdisp) = f_optdisp; | |
4468 | FLD (f_scale) = f_scale; | |
4469 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4470 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4471 | FLD (i_dst) = & CPU (h_gr)[f_srcdst]; | |
4472 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); | |
4473 | ||
4474 | #if WITH_PROFILE_MODEL_P | |
4475 | /* Record the fields for profiling. */ | |
4476 | if (PROFILE_MODEL_P (current_cpu)) | |
4477 | { | |
4478 | FLD (in_abase) = f_abase; | |
4479 | FLD (in_index) = f_index; | |
4480 | FLD (out_dst) = f_srcdst; | |
4481 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
4482 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
4483 | FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
4484 | } | |
4485 | #endif | |
4486 | #undef FLD | |
4487 | BREAK (ex); | |
4488 | } | |
4489 | ||
4490 | CASE (ex, FMT_ST_OFFSET) : | |
4491 | { | |
4492 | CGEN_INSN_INT insn = base_insn; | |
4493 | #define FLD(f) abuf->fields.fmt_st_offset.f | |
4494 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4495 | ||
4496 | EXTRACT_IFMT_ST_OFFSET_CODE | |
4497 | ||
4498 | /* Record the fields for the semantic handler. */ | |
4499 | FLD (f_offset) = f_offset; | |
4500 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4501 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4502 | ||
4503 | #if WITH_PROFILE_MODEL_P | |
4504 | /* Record the fields for profiling. */ | |
4505 | if (PROFILE_MODEL_P (current_cpu)) | |
4506 | { | |
4507 | FLD (in_st_src) = f_srcdst; | |
4508 | } | |
4509 | #endif | |
4510 | #undef FLD | |
4511 | BREAK (ex); | |
4512 | } | |
4513 | ||
4514 | CASE (ex, FMT_ST_INDIRECT_OFFSET) : | |
4515 | { | |
4516 | CGEN_INSN_INT insn = base_insn; | |
4517 | #define FLD(f) abuf->fields.fmt_st_indirect_offset.f | |
4518 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4519 | ||
4520 | EXTRACT_IFMT_ST_OFFSET_CODE | |
4521 | ||
4522 | /* Record the fields for the semantic handler. */ | |
4523 | FLD (f_offset) = f_offset; | |
4524 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4525 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4526 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4527 | ||
4528 | #if WITH_PROFILE_MODEL_P | |
4529 | /* Record the fields for profiling. */ | |
4530 | if (PROFILE_MODEL_P (current_cpu)) | |
4531 | { | |
4532 | FLD (in_abase) = f_abase; | |
4533 | FLD (in_st_src) = f_srcdst; | |
4534 | } | |
4535 | #endif | |
4536 | #undef FLD | |
4537 | BREAK (ex); | |
4538 | } | |
4539 | ||
4540 | CASE (ex, FMT_ST_INDIRECT) : | |
4541 | { | |
4542 | CGEN_INSN_INT insn = base_insn; | |
4543 | #define FLD(f) abuf->fields.fmt_st_indirect.f | |
4544 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4545 | ||
4546 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
4547 | ||
4548 | /* Record the fields for the semantic handler. */ | |
4549 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4550 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4551 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4552 | ||
4553 | #if WITH_PROFILE_MODEL_P | |
4554 | /* Record the fields for profiling. */ | |
4555 | if (PROFILE_MODEL_P (current_cpu)) | |
4556 | { | |
4557 | FLD (in_abase) = f_abase; | |
4558 | FLD (in_st_src) = f_srcdst; | |
4559 | } | |
4560 | #endif | |
4561 | #undef FLD | |
4562 | BREAK (ex); | |
4563 | } | |
4564 | ||
4565 | CASE (ex, FMT_ST_INDIRECT_INDEX) : | |
4566 | { | |
4567 | CGEN_INSN_INT insn = base_insn; | |
4568 | #define FLD(f) abuf->fields.fmt_st_indirect_index.f | |
4569 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4570 | ||
4571 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
4572 | ||
4573 | /* Record the fields for the semantic handler. */ | |
4574 | FLD (f_scale) = f_scale; | |
4575 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4576 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4577 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4578 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4579 | ||
4580 | #if WITH_PROFILE_MODEL_P | |
4581 | /* Record the fields for profiling. */ | |
4582 | if (PROFILE_MODEL_P (current_cpu)) | |
4583 | { | |
4584 | FLD (in_abase) = f_abase; | |
4585 | FLD (in_index) = f_index; | |
4586 | FLD (in_st_src) = f_srcdst; | |
4587 | } | |
4588 | #endif | |
4589 | #undef FLD | |
4590 | BREAK (ex); | |
4591 | } | |
4592 | ||
4593 | CASE (ex, FMT_ST_DISP) : | |
4594 | { | |
4595 | CGEN_INSN_INT insn = base_insn; | |
4596 | #define FLD(f) abuf->fields.fmt_st_disp.f | |
4597 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4598 | ||
4599 | EXTRACT_IFMT_ST_DISP_CODE | |
4600 | ||
4601 | /* Record the fields for the semantic handler. */ | |
4602 | FLD (f_optdisp) = f_optdisp; | |
4603 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4604 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4605 | ||
4606 | #if WITH_PROFILE_MODEL_P | |
4607 | /* Record the fields for profiling. */ | |
4608 | if (PROFILE_MODEL_P (current_cpu)) | |
4609 | { | |
4610 | FLD (in_st_src) = f_srcdst; | |
4611 | } | |
4612 | #endif | |
4613 | #undef FLD | |
4614 | BREAK (ex); | |
4615 | } | |
4616 | ||
4617 | CASE (ex, FMT_ST_INDIRECT_DISP) : | |
4618 | { | |
4619 | CGEN_INSN_INT insn = base_insn; | |
4620 | #define FLD(f) abuf->fields.fmt_st_indirect_disp.f | |
4621 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4622 | ||
4623 | EXTRACT_IFMT_ST_DISP_CODE | |
4624 | ||
4625 | /* Record the fields for the semantic handler. */ | |
4626 | FLD (f_optdisp) = f_optdisp; | |
4627 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4628 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4629 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4630 | ||
4631 | #if WITH_PROFILE_MODEL_P | |
4632 | /* Record the fields for profiling. */ | |
4633 | if (PROFILE_MODEL_P (current_cpu)) | |
4634 | { | |
4635 | FLD (in_abase) = f_abase; | |
4636 | FLD (in_st_src) = f_srcdst; | |
4637 | } | |
4638 | #endif | |
4639 | #undef FLD | |
4640 | BREAK (ex); | |
4641 | } | |
4642 | ||
4643 | CASE (ex, FMT_ST_INDEX_DISP) : | |
4644 | { | |
4645 | CGEN_INSN_INT insn = base_insn; | |
4646 | #define FLD(f) abuf->fields.fmt_st_index_disp.f | |
4647 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4648 | ||
4649 | EXTRACT_IFMT_ST_DISP_CODE | |
4650 | ||
4651 | /* Record the fields for the semantic handler. */ | |
4652 | FLD (f_optdisp) = f_optdisp; | |
4653 | FLD (f_scale) = f_scale; | |
4654 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4655 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4656 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4657 | ||
4658 | #if WITH_PROFILE_MODEL_P | |
4659 | /* Record the fields for profiling. */ | |
4660 | if (PROFILE_MODEL_P (current_cpu)) | |
4661 | { | |
4662 | FLD (in_index) = f_index; | |
4663 | FLD (in_st_src) = f_srcdst; | |
4664 | } | |
4665 | #endif | |
4666 | #undef FLD | |
4667 | BREAK (ex); | |
4668 | } | |
4669 | ||
4670 | CASE (ex, FMT_ST_INDIRECT_INDEX_DISP) : | |
4671 | { | |
4672 | CGEN_INSN_INT insn = base_insn; | |
4673 | #define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f | |
4674 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4675 | ||
4676 | EXTRACT_IFMT_ST_DISP_CODE | |
4677 | ||
4678 | /* Record the fields for the semantic handler. */ | |
4679 | FLD (f_optdisp) = f_optdisp; | |
4680 | FLD (f_scale) = f_scale; | |
4681 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4682 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4683 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4684 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4685 | ||
4686 | #if WITH_PROFILE_MODEL_P | |
4687 | /* Record the fields for profiling. */ | |
4688 | if (PROFILE_MODEL_P (current_cpu)) | |
4689 | { | |
4690 | FLD (in_abase) = f_abase; | |
4691 | FLD (in_index) = f_index; | |
4692 | FLD (in_st_src) = f_srcdst; | |
4693 | } | |
4694 | #endif | |
4695 | #undef FLD | |
4696 | BREAK (ex); | |
4697 | } | |
4698 | ||
4699 | CASE (ex, FMT_STOB_OFFSET) : | |
4700 | { | |
4701 | CGEN_INSN_INT insn = base_insn; | |
4702 | #define FLD(f) abuf->fields.fmt_stob_offset.f | |
4703 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4704 | ||
4705 | EXTRACT_IFMT_ST_OFFSET_CODE | |
4706 | ||
4707 | /* Record the fields for the semantic handler. */ | |
4708 | FLD (f_offset) = f_offset; | |
4709 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4710 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4711 | ||
4712 | #if WITH_PROFILE_MODEL_P | |
4713 | /* Record the fields for profiling. */ | |
4714 | if (PROFILE_MODEL_P (current_cpu)) | |
4715 | { | |
4716 | FLD (in_st_src) = f_srcdst; | |
4717 | } | |
4718 | #endif | |
4719 | #undef FLD | |
4720 | BREAK (ex); | |
4721 | } | |
4722 | ||
4723 | CASE (ex, FMT_STOB_INDIRECT_OFFSET) : | |
4724 | { | |
4725 | CGEN_INSN_INT insn = base_insn; | |
4726 | #define FLD(f) abuf->fields.fmt_stob_indirect_offset.f | |
4727 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4728 | ||
4729 | EXTRACT_IFMT_ST_OFFSET_CODE | |
4730 | ||
4731 | /* Record the fields for the semantic handler. */ | |
4732 | FLD (f_offset) = f_offset; | |
4733 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4734 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4735 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4736 | ||
4737 | #if WITH_PROFILE_MODEL_P | |
4738 | /* Record the fields for profiling. */ | |
4739 | if (PROFILE_MODEL_P (current_cpu)) | |
4740 | { | |
4741 | FLD (in_abase) = f_abase; | |
4742 | FLD (in_st_src) = f_srcdst; | |
4743 | } | |
4744 | #endif | |
4745 | #undef FLD | |
4746 | BREAK (ex); | |
4747 | } | |
4748 | ||
4749 | CASE (ex, FMT_STOB_INDIRECT) : | |
4750 | { | |
4751 | CGEN_INSN_INT insn = base_insn; | |
4752 | #define FLD(f) abuf->fields.fmt_stob_indirect.f | |
4753 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4754 | ||
4755 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
4756 | ||
4757 | /* Record the fields for the semantic handler. */ | |
4758 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4759 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4760 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4761 | ||
4762 | #if WITH_PROFILE_MODEL_P | |
4763 | /* Record the fields for profiling. */ | |
4764 | if (PROFILE_MODEL_P (current_cpu)) | |
4765 | { | |
4766 | FLD (in_abase) = f_abase; | |
4767 | FLD (in_st_src) = f_srcdst; | |
4768 | } | |
4769 | #endif | |
4770 | #undef FLD | |
4771 | BREAK (ex); | |
4772 | } | |
4773 | ||
4774 | CASE (ex, FMT_STOB_INDIRECT_INDEX) : | |
4775 | { | |
4776 | CGEN_INSN_INT insn = base_insn; | |
4777 | #define FLD(f) abuf->fields.fmt_stob_indirect_index.f | |
4778 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4779 | ||
4780 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
4781 | ||
4782 | /* Record the fields for the semantic handler. */ | |
4783 | FLD (f_scale) = f_scale; | |
4784 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4785 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4786 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4787 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4788 | ||
4789 | #if WITH_PROFILE_MODEL_P | |
4790 | /* Record the fields for profiling. */ | |
4791 | if (PROFILE_MODEL_P (current_cpu)) | |
4792 | { | |
4793 | FLD (in_abase) = f_abase; | |
4794 | FLD (in_index) = f_index; | |
4795 | FLD (in_st_src) = f_srcdst; | |
4796 | } | |
4797 | #endif | |
4798 | #undef FLD | |
4799 | BREAK (ex); | |
4800 | } | |
4801 | ||
4802 | CASE (ex, FMT_STOB_DISP) : | |
4803 | { | |
4804 | CGEN_INSN_INT insn = base_insn; | |
4805 | #define FLD(f) abuf->fields.fmt_stob_disp.f | |
4806 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4807 | ||
4808 | EXTRACT_IFMT_ST_DISP_CODE | |
4809 | ||
4810 | /* Record the fields for the semantic handler. */ | |
4811 | FLD (f_optdisp) = f_optdisp; | |
4812 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4813 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4814 | ||
4815 | #if WITH_PROFILE_MODEL_P | |
4816 | /* Record the fields for profiling. */ | |
4817 | if (PROFILE_MODEL_P (current_cpu)) | |
4818 | { | |
4819 | FLD (in_st_src) = f_srcdst; | |
4820 | } | |
4821 | #endif | |
4822 | #undef FLD | |
4823 | BREAK (ex); | |
4824 | } | |
4825 | ||
4826 | CASE (ex, FMT_STOB_INDIRECT_DISP) : | |
4827 | { | |
4828 | CGEN_INSN_INT insn = base_insn; | |
4829 | #define FLD(f) abuf->fields.fmt_stob_indirect_disp.f | |
4830 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4831 | ||
4832 | EXTRACT_IFMT_ST_DISP_CODE | |
4833 | ||
4834 | /* Record the fields for the semantic handler. */ | |
4835 | FLD (f_optdisp) = f_optdisp; | |
4836 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4837 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4838 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4839 | ||
4840 | #if WITH_PROFILE_MODEL_P | |
4841 | /* Record the fields for profiling. */ | |
4842 | if (PROFILE_MODEL_P (current_cpu)) | |
4843 | { | |
4844 | FLD (in_abase) = f_abase; | |
4845 | FLD (in_st_src) = f_srcdst; | |
4846 | } | |
4847 | #endif | |
4848 | #undef FLD | |
4849 | BREAK (ex); | |
4850 | } | |
4851 | ||
4852 | CASE (ex, FMT_STOB_INDEX_DISP) : | |
4853 | { | |
4854 | CGEN_INSN_INT insn = base_insn; | |
4855 | #define FLD(f) abuf->fields.fmt_stob_index_disp.f | |
4856 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4857 | ||
4858 | EXTRACT_IFMT_ST_DISP_CODE | |
4859 | ||
4860 | /* Record the fields for the semantic handler. */ | |
4861 | FLD (f_optdisp) = f_optdisp; | |
4862 | FLD (f_scale) = f_scale; | |
4863 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4864 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4865 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4866 | ||
4867 | #if WITH_PROFILE_MODEL_P | |
4868 | /* Record the fields for profiling. */ | |
4869 | if (PROFILE_MODEL_P (current_cpu)) | |
4870 | { | |
4871 | FLD (in_index) = f_index; | |
4872 | FLD (in_st_src) = f_srcdst; | |
4873 | } | |
4874 | #endif | |
4875 | #undef FLD | |
4876 | BREAK (ex); | |
4877 | } | |
4878 | ||
4879 | CASE (ex, FMT_STOB_INDIRECT_INDEX_DISP) : | |
4880 | { | |
4881 | CGEN_INSN_INT insn = base_insn; | |
4882 | #define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f | |
4883 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4884 | ||
4885 | EXTRACT_IFMT_ST_DISP_CODE | |
4886 | ||
4887 | /* Record the fields for the semantic handler. */ | |
4888 | FLD (f_optdisp) = f_optdisp; | |
4889 | FLD (f_scale) = f_scale; | |
4890 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4891 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4892 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4893 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4894 | ||
4895 | #if WITH_PROFILE_MODEL_P | |
4896 | /* Record the fields for profiling. */ | |
4897 | if (PROFILE_MODEL_P (current_cpu)) | |
4898 | { | |
4899 | FLD (in_abase) = f_abase; | |
4900 | FLD (in_index) = f_index; | |
4901 | FLD (in_st_src) = f_srcdst; | |
4902 | } | |
4903 | #endif | |
4904 | #undef FLD | |
4905 | BREAK (ex); | |
4906 | } | |
4907 | ||
4908 | CASE (ex, FMT_STOS_OFFSET) : | |
4909 | { | |
4910 | CGEN_INSN_INT insn = base_insn; | |
4911 | #define FLD(f) abuf->fields.fmt_stos_offset.f | |
4912 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4913 | ||
4914 | EXTRACT_IFMT_ST_OFFSET_CODE | |
4915 | ||
4916 | /* Record the fields for the semantic handler. */ | |
4917 | FLD (f_offset) = f_offset; | |
4918 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4919 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4920 | ||
4921 | #if WITH_PROFILE_MODEL_P | |
4922 | /* Record the fields for profiling. */ | |
4923 | if (PROFILE_MODEL_P (current_cpu)) | |
4924 | { | |
4925 | FLD (in_st_src) = f_srcdst; | |
4926 | } | |
4927 | #endif | |
4928 | #undef FLD | |
4929 | BREAK (ex); | |
4930 | } | |
4931 | ||
4932 | CASE (ex, FMT_STOS_INDIRECT_OFFSET) : | |
4933 | { | |
4934 | CGEN_INSN_INT insn = base_insn; | |
4935 | #define FLD(f) abuf->fields.fmt_stos_indirect_offset.f | |
4936 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
4937 | ||
4938 | EXTRACT_IFMT_ST_OFFSET_CODE | |
4939 | ||
4940 | /* Record the fields for the semantic handler. */ | |
4941 | FLD (f_offset) = f_offset; | |
4942 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4943 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4944 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4945 | ||
4946 | #if WITH_PROFILE_MODEL_P | |
4947 | /* Record the fields for profiling. */ | |
4948 | if (PROFILE_MODEL_P (current_cpu)) | |
4949 | { | |
4950 | FLD (in_abase) = f_abase; | |
4951 | FLD (in_st_src) = f_srcdst; | |
4952 | } | |
4953 | #endif | |
4954 | #undef FLD | |
4955 | BREAK (ex); | |
4956 | } | |
4957 | ||
4958 | CASE (ex, FMT_STOS_INDIRECT) : | |
4959 | { | |
4960 | CGEN_INSN_INT insn = base_insn; | |
4961 | #define FLD(f) abuf->fields.fmt_stos_indirect.f | |
4962 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4963 | ||
4964 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
4965 | ||
4966 | /* Record the fields for the semantic handler. */ | |
4967 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4968 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4969 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4970 | ||
4971 | #if WITH_PROFILE_MODEL_P | |
4972 | /* Record the fields for profiling. */ | |
4973 | if (PROFILE_MODEL_P (current_cpu)) | |
4974 | { | |
4975 | FLD (in_abase) = f_abase; | |
4976 | FLD (in_st_src) = f_srcdst; | |
4977 | } | |
4978 | #endif | |
4979 | #undef FLD | |
4980 | BREAK (ex); | |
4981 | } | |
4982 | ||
4983 | CASE (ex, FMT_STOS_INDIRECT_INDEX) : | |
4984 | { | |
4985 | CGEN_INSN_INT insn = base_insn; | |
4986 | #define FLD(f) abuf->fields.fmt_stos_indirect_index.f | |
4987 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
4988 | ||
4989 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
4990 | ||
4991 | /* Record the fields for the semantic handler. */ | |
4992 | FLD (f_scale) = f_scale; | |
4993 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
4994 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
4995 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
4996 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
4997 | ||
4998 | #if WITH_PROFILE_MODEL_P | |
4999 | /* Record the fields for profiling. */ | |
5000 | if (PROFILE_MODEL_P (current_cpu)) | |
5001 | { | |
5002 | FLD (in_abase) = f_abase; | |
5003 | FLD (in_index) = f_index; | |
5004 | FLD (in_st_src) = f_srcdst; | |
5005 | } | |
5006 | #endif | |
5007 | #undef FLD | |
5008 | BREAK (ex); | |
5009 | } | |
5010 | ||
5011 | CASE (ex, FMT_STOS_DISP) : | |
5012 | { | |
5013 | CGEN_INSN_INT insn = base_insn; | |
5014 | #define FLD(f) abuf->fields.fmt_stos_disp.f | |
5015 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5016 | ||
5017 | EXTRACT_IFMT_ST_DISP_CODE | |
5018 | ||
5019 | /* Record the fields for the semantic handler. */ | |
5020 | FLD (f_optdisp) = f_optdisp; | |
5021 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5022 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5023 | ||
5024 | #if WITH_PROFILE_MODEL_P | |
5025 | /* Record the fields for profiling. */ | |
5026 | if (PROFILE_MODEL_P (current_cpu)) | |
5027 | { | |
5028 | FLD (in_st_src) = f_srcdst; | |
5029 | } | |
5030 | #endif | |
5031 | #undef FLD | |
5032 | BREAK (ex); | |
5033 | } | |
5034 | ||
5035 | CASE (ex, FMT_STOS_INDIRECT_DISP) : | |
5036 | { | |
5037 | CGEN_INSN_INT insn = base_insn; | |
5038 | #define FLD(f) abuf->fields.fmt_stos_indirect_disp.f | |
5039 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5040 | ||
5041 | EXTRACT_IFMT_ST_DISP_CODE | |
5042 | ||
5043 | /* Record the fields for the semantic handler. */ | |
5044 | FLD (f_optdisp) = f_optdisp; | |
5045 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5046 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5047 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5048 | ||
5049 | #if WITH_PROFILE_MODEL_P | |
5050 | /* Record the fields for profiling. */ | |
5051 | if (PROFILE_MODEL_P (current_cpu)) | |
5052 | { | |
5053 | FLD (in_abase) = f_abase; | |
5054 | FLD (in_st_src) = f_srcdst; | |
5055 | } | |
5056 | #endif | |
5057 | #undef FLD | |
5058 | BREAK (ex); | |
5059 | } | |
5060 | ||
5061 | CASE (ex, FMT_STOS_INDEX_DISP) : | |
5062 | { | |
5063 | CGEN_INSN_INT insn = base_insn; | |
5064 | #define FLD(f) abuf->fields.fmt_stos_index_disp.f | |
5065 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5066 | ||
5067 | EXTRACT_IFMT_ST_DISP_CODE | |
5068 | ||
5069 | /* Record the fields for the semantic handler. */ | |
5070 | FLD (f_optdisp) = f_optdisp; | |
5071 | FLD (f_scale) = f_scale; | |
5072 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5073 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5074 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5075 | ||
5076 | #if WITH_PROFILE_MODEL_P | |
5077 | /* Record the fields for profiling. */ | |
5078 | if (PROFILE_MODEL_P (current_cpu)) | |
5079 | { | |
5080 | FLD (in_index) = f_index; | |
5081 | FLD (in_st_src) = f_srcdst; | |
5082 | } | |
5083 | #endif | |
5084 | #undef FLD | |
5085 | BREAK (ex); | |
5086 | } | |
5087 | ||
5088 | CASE (ex, FMT_STOS_INDIRECT_INDEX_DISP) : | |
5089 | { | |
5090 | CGEN_INSN_INT insn = base_insn; | |
5091 | #define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f | |
5092 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5093 | ||
5094 | EXTRACT_IFMT_ST_DISP_CODE | |
5095 | ||
5096 | /* Record the fields for the semantic handler. */ | |
5097 | FLD (f_optdisp) = f_optdisp; | |
5098 | FLD (f_scale) = f_scale; | |
5099 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5100 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5101 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5102 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5103 | ||
5104 | #if WITH_PROFILE_MODEL_P | |
5105 | /* Record the fields for profiling. */ | |
5106 | if (PROFILE_MODEL_P (current_cpu)) | |
5107 | { | |
5108 | FLD (in_abase) = f_abase; | |
5109 | FLD (in_index) = f_index; | |
5110 | FLD (in_st_src) = f_srcdst; | |
5111 | } | |
5112 | #endif | |
5113 | #undef FLD | |
5114 | BREAK (ex); | |
5115 | } | |
5116 | ||
5117 | CASE (ex, FMT_STL_OFFSET) : | |
5118 | { | |
5119 | CGEN_INSN_INT insn = base_insn; | |
5120 | #define FLD(f) abuf->fields.fmt_stl_offset.f | |
5121 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
5122 | ||
5123 | EXTRACT_IFMT_ST_OFFSET_CODE | |
5124 | ||
5125 | /* Record the fields for the semantic handler. */ | |
5126 | FLD (f_srcdst) = f_srcdst; | |
5127 | FLD (f_offset) = f_offset; | |
5128 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5129 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5130 | ||
5131 | #if WITH_PROFILE_MODEL_P | |
5132 | /* Record the fields for profiling. */ | |
5133 | if (PROFILE_MODEL_P (current_cpu)) | |
5134 | { | |
5135 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5136 | FLD (in_st_src) = f_srcdst; | |
5137 | } | |
5138 | #endif | |
5139 | #undef FLD | |
5140 | BREAK (ex); | |
5141 | } | |
5142 | ||
5143 | CASE (ex, FMT_STL_INDIRECT_OFFSET) : | |
5144 | { | |
5145 | CGEN_INSN_INT insn = base_insn; | |
5146 | #define FLD(f) abuf->fields.fmt_stl_indirect_offset.f | |
5147 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
5148 | ||
5149 | EXTRACT_IFMT_ST_OFFSET_CODE | |
5150 | ||
5151 | /* Record the fields for the semantic handler. */ | |
5152 | FLD (f_srcdst) = f_srcdst; | |
5153 | FLD (f_offset) = f_offset; | |
5154 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5155 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5156 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5157 | ||
5158 | #if WITH_PROFILE_MODEL_P | |
5159 | /* Record the fields for profiling. */ | |
5160 | if (PROFILE_MODEL_P (current_cpu)) | |
5161 | { | |
5162 | FLD (in_abase) = f_abase; | |
5163 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5164 | FLD (in_st_src) = f_srcdst; | |
5165 | } | |
5166 | #endif | |
5167 | #undef FLD | |
5168 | BREAK (ex); | |
5169 | } | |
5170 | ||
5171 | CASE (ex, FMT_STL_INDIRECT) : | |
5172 | { | |
5173 | CGEN_INSN_INT insn = base_insn; | |
5174 | #define FLD(f) abuf->fields.fmt_stl_indirect.f | |
5175 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5176 | ||
5177 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
5178 | ||
5179 | /* Record the fields for the semantic handler. */ | |
5180 | FLD (f_srcdst) = f_srcdst; | |
5181 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5182 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5183 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5184 | ||
5185 | #if WITH_PROFILE_MODEL_P | |
5186 | /* Record the fields for profiling. */ | |
5187 | if (PROFILE_MODEL_P (current_cpu)) | |
5188 | { | |
5189 | FLD (in_abase) = f_abase; | |
5190 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5191 | FLD (in_st_src) = f_srcdst; | |
5192 | } | |
5193 | #endif | |
5194 | #undef FLD | |
5195 | BREAK (ex); | |
5196 | } | |
5197 | ||
5198 | CASE (ex, FMT_STL_INDIRECT_INDEX) : | |
5199 | { | |
5200 | CGEN_INSN_INT insn = base_insn; | |
5201 | #define FLD(f) abuf->fields.fmt_stl_indirect_index.f | |
5202 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5203 | ||
5204 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
5205 | ||
5206 | /* Record the fields for the semantic handler. */ | |
5207 | FLD (f_srcdst) = f_srcdst; | |
5208 | FLD (f_scale) = f_scale; | |
5209 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5210 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5211 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5212 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5213 | ||
5214 | #if WITH_PROFILE_MODEL_P | |
5215 | /* Record the fields for profiling. */ | |
5216 | if (PROFILE_MODEL_P (current_cpu)) | |
5217 | { | |
5218 | FLD (in_abase) = f_abase; | |
5219 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5220 | FLD (in_index) = f_index; | |
5221 | FLD (in_st_src) = f_srcdst; | |
5222 | } | |
5223 | #endif | |
5224 | #undef FLD | |
5225 | BREAK (ex); | |
5226 | } | |
5227 | ||
5228 | CASE (ex, FMT_STL_DISP) : | |
5229 | { | |
5230 | CGEN_INSN_INT insn = base_insn; | |
5231 | #define FLD(f) abuf->fields.fmt_stl_disp.f | |
5232 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5233 | ||
5234 | EXTRACT_IFMT_ST_DISP_CODE | |
5235 | ||
5236 | /* Record the fields for the semantic handler. */ | |
5237 | FLD (f_srcdst) = f_srcdst; | |
5238 | FLD (f_optdisp) = f_optdisp; | |
5239 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5240 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5241 | ||
5242 | #if WITH_PROFILE_MODEL_P | |
5243 | /* Record the fields for profiling. */ | |
5244 | if (PROFILE_MODEL_P (current_cpu)) | |
5245 | { | |
5246 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5247 | FLD (in_st_src) = f_srcdst; | |
5248 | } | |
5249 | #endif | |
5250 | #undef FLD | |
5251 | BREAK (ex); | |
5252 | } | |
5253 | ||
5254 | CASE (ex, FMT_STL_INDIRECT_DISP) : | |
5255 | { | |
5256 | CGEN_INSN_INT insn = base_insn; | |
5257 | #define FLD(f) abuf->fields.fmt_stl_indirect_disp.f | |
5258 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5259 | ||
5260 | EXTRACT_IFMT_ST_DISP_CODE | |
5261 | ||
5262 | /* Record the fields for the semantic handler. */ | |
5263 | FLD (f_srcdst) = f_srcdst; | |
5264 | FLD (f_optdisp) = f_optdisp; | |
5265 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5266 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5267 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5268 | ||
5269 | #if WITH_PROFILE_MODEL_P | |
5270 | /* Record the fields for profiling. */ | |
5271 | if (PROFILE_MODEL_P (current_cpu)) | |
5272 | { | |
5273 | FLD (in_abase) = f_abase; | |
5274 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5275 | FLD (in_st_src) = f_srcdst; | |
5276 | } | |
5277 | #endif | |
5278 | #undef FLD | |
5279 | BREAK (ex); | |
5280 | } | |
5281 | ||
5282 | CASE (ex, FMT_STL_INDEX_DISP) : | |
5283 | { | |
5284 | CGEN_INSN_INT insn = base_insn; | |
5285 | #define FLD(f) abuf->fields.fmt_stl_index_disp.f | |
5286 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5287 | ||
5288 | EXTRACT_IFMT_ST_DISP_CODE | |
5289 | ||
5290 | /* Record the fields for the semantic handler. */ | |
5291 | FLD (f_srcdst) = f_srcdst; | |
5292 | FLD (f_optdisp) = f_optdisp; | |
5293 | FLD (f_scale) = f_scale; | |
5294 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5295 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5296 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5297 | ||
5298 | #if WITH_PROFILE_MODEL_P | |
5299 | /* Record the fields for profiling. */ | |
5300 | if (PROFILE_MODEL_P (current_cpu)) | |
5301 | { | |
5302 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5303 | FLD (in_index) = f_index; | |
5304 | FLD (in_st_src) = f_srcdst; | |
5305 | } | |
5306 | #endif | |
5307 | #undef FLD | |
5308 | BREAK (ex); | |
5309 | } | |
5310 | ||
5311 | CASE (ex, FMT_STL_INDIRECT_INDEX_DISP) : | |
5312 | { | |
5313 | CGEN_INSN_INT insn = base_insn; | |
5314 | #define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f | |
5315 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5316 | ||
5317 | EXTRACT_IFMT_ST_DISP_CODE | |
5318 | ||
5319 | /* Record the fields for the semantic handler. */ | |
5320 | FLD (f_srcdst) = f_srcdst; | |
5321 | FLD (f_optdisp) = f_optdisp; | |
5322 | FLD (f_scale) = f_scale; | |
5323 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5324 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5325 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5326 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5327 | ||
5328 | #if WITH_PROFILE_MODEL_P | |
5329 | /* Record the fields for profiling. */ | |
5330 | if (PROFILE_MODEL_P (current_cpu)) | |
5331 | { | |
5332 | FLD (in_abase) = f_abase; | |
5333 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5334 | FLD (in_index) = f_index; | |
5335 | FLD (in_st_src) = f_srcdst; | |
5336 | } | |
5337 | #endif | |
5338 | #undef FLD | |
5339 | BREAK (ex); | |
5340 | } | |
5341 | ||
5342 | CASE (ex, FMT_STT_OFFSET) : | |
5343 | { | |
5344 | CGEN_INSN_INT insn = base_insn; | |
5345 | #define FLD(f) abuf->fields.fmt_stt_offset.f | |
5346 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
5347 | ||
5348 | EXTRACT_IFMT_ST_OFFSET_CODE | |
5349 | ||
5350 | /* Record the fields for the semantic handler. */ | |
5351 | FLD (f_srcdst) = f_srcdst; | |
5352 | FLD (f_offset) = f_offset; | |
5353 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5354 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5355 | ||
5356 | #if WITH_PROFILE_MODEL_P | |
5357 | /* Record the fields for profiling. */ | |
5358 | if (PROFILE_MODEL_P (current_cpu)) | |
5359 | { | |
5360 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5361 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5362 | FLD (in_st_src) = f_srcdst; | |
5363 | } | |
5364 | #endif | |
5365 | #undef FLD | |
5366 | BREAK (ex); | |
5367 | } | |
5368 | ||
5369 | CASE (ex, FMT_STT_INDIRECT_OFFSET) : | |
5370 | { | |
5371 | CGEN_INSN_INT insn = base_insn; | |
5372 | #define FLD(f) abuf->fields.fmt_stt_indirect_offset.f | |
5373 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
5374 | ||
5375 | EXTRACT_IFMT_ST_OFFSET_CODE | |
5376 | ||
5377 | /* Record the fields for the semantic handler. */ | |
5378 | FLD (f_srcdst) = f_srcdst; | |
5379 | FLD (f_offset) = f_offset; | |
5380 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5381 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5382 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5383 | ||
5384 | #if WITH_PROFILE_MODEL_P | |
5385 | /* Record the fields for profiling. */ | |
5386 | if (PROFILE_MODEL_P (current_cpu)) | |
5387 | { | |
5388 | FLD (in_abase) = f_abase; | |
5389 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5390 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5391 | FLD (in_st_src) = f_srcdst; | |
5392 | } | |
5393 | #endif | |
5394 | #undef FLD | |
5395 | BREAK (ex); | |
5396 | } | |
5397 | ||
5398 | CASE (ex, FMT_STT_INDIRECT) : | |
5399 | { | |
5400 | CGEN_INSN_INT insn = base_insn; | |
5401 | #define FLD(f) abuf->fields.fmt_stt_indirect.f | |
5402 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5403 | ||
5404 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
5405 | ||
5406 | /* Record the fields for the semantic handler. */ | |
5407 | FLD (f_srcdst) = f_srcdst; | |
5408 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5409 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5410 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5411 | ||
5412 | #if WITH_PROFILE_MODEL_P | |
5413 | /* Record the fields for profiling. */ | |
5414 | if (PROFILE_MODEL_P (current_cpu)) | |
5415 | { | |
5416 | FLD (in_abase) = f_abase; | |
5417 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5418 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5419 | FLD (in_st_src) = f_srcdst; | |
5420 | } | |
5421 | #endif | |
5422 | #undef FLD | |
5423 | BREAK (ex); | |
5424 | } | |
5425 | ||
5426 | CASE (ex, FMT_STT_INDIRECT_INDEX) : | |
5427 | { | |
5428 | CGEN_INSN_INT insn = base_insn; | |
5429 | #define FLD(f) abuf->fields.fmt_stt_indirect_index.f | |
5430 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5431 | ||
5432 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
5433 | ||
5434 | /* Record the fields for the semantic handler. */ | |
5435 | FLD (f_srcdst) = f_srcdst; | |
5436 | FLD (f_scale) = f_scale; | |
5437 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5438 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5439 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5440 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5441 | ||
5442 | #if WITH_PROFILE_MODEL_P | |
5443 | /* Record the fields for profiling. */ | |
5444 | if (PROFILE_MODEL_P (current_cpu)) | |
5445 | { | |
5446 | FLD (in_abase) = f_abase; | |
5447 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5448 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5449 | FLD (in_index) = f_index; | |
5450 | FLD (in_st_src) = f_srcdst; | |
5451 | } | |
5452 | #endif | |
5453 | #undef FLD | |
5454 | BREAK (ex); | |
5455 | } | |
5456 | ||
5457 | CASE (ex, FMT_STT_DISP) : | |
5458 | { | |
5459 | CGEN_INSN_INT insn = base_insn; | |
5460 | #define FLD(f) abuf->fields.fmt_stt_disp.f | |
5461 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5462 | ||
5463 | EXTRACT_IFMT_ST_DISP_CODE | |
5464 | ||
5465 | /* Record the fields for the semantic handler. */ | |
5466 | FLD (f_srcdst) = f_srcdst; | |
5467 | FLD (f_optdisp) = f_optdisp; | |
5468 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5469 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5470 | ||
5471 | #if WITH_PROFILE_MODEL_P | |
5472 | /* Record the fields for profiling. */ | |
5473 | if (PROFILE_MODEL_P (current_cpu)) | |
5474 | { | |
5475 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5476 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5477 | FLD (in_st_src) = f_srcdst; | |
5478 | } | |
5479 | #endif | |
5480 | #undef FLD | |
5481 | BREAK (ex); | |
5482 | } | |
5483 | ||
5484 | CASE (ex, FMT_STT_INDIRECT_DISP) : | |
5485 | { | |
5486 | CGEN_INSN_INT insn = base_insn; | |
5487 | #define FLD(f) abuf->fields.fmt_stt_indirect_disp.f | |
5488 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5489 | ||
5490 | EXTRACT_IFMT_ST_DISP_CODE | |
5491 | ||
5492 | /* Record the fields for the semantic handler. */ | |
5493 | FLD (f_srcdst) = f_srcdst; | |
5494 | FLD (f_optdisp) = f_optdisp; | |
5495 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5496 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5497 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5498 | ||
5499 | #if WITH_PROFILE_MODEL_P | |
5500 | /* Record the fields for profiling. */ | |
5501 | if (PROFILE_MODEL_P (current_cpu)) | |
5502 | { | |
5503 | FLD (in_abase) = f_abase; | |
5504 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5505 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5506 | FLD (in_st_src) = f_srcdst; | |
5507 | } | |
5508 | #endif | |
5509 | #undef FLD | |
5510 | BREAK (ex); | |
5511 | } | |
5512 | ||
5513 | CASE (ex, FMT_STT_INDEX_DISP) : | |
5514 | { | |
5515 | CGEN_INSN_INT insn = base_insn; | |
5516 | #define FLD(f) abuf->fields.fmt_stt_index_disp.f | |
5517 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5518 | ||
5519 | EXTRACT_IFMT_ST_DISP_CODE | |
5520 | ||
5521 | /* Record the fields for the semantic handler. */ | |
5522 | FLD (f_srcdst) = f_srcdst; | |
5523 | FLD (f_optdisp) = f_optdisp; | |
5524 | FLD (f_scale) = f_scale; | |
5525 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5526 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5527 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5528 | ||
5529 | #if WITH_PROFILE_MODEL_P | |
5530 | /* Record the fields for profiling. */ | |
5531 | if (PROFILE_MODEL_P (current_cpu)) | |
5532 | { | |
5533 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5534 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5535 | FLD (in_index) = f_index; | |
5536 | FLD (in_st_src) = f_srcdst; | |
5537 | } | |
5538 | #endif | |
5539 | #undef FLD | |
5540 | BREAK (ex); | |
5541 | } | |
5542 | ||
5543 | CASE (ex, FMT_STT_INDIRECT_INDEX_DISP) : | |
5544 | { | |
5545 | CGEN_INSN_INT insn = base_insn; | |
5546 | #define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f | |
5547 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5548 | ||
5549 | EXTRACT_IFMT_ST_DISP_CODE | |
5550 | ||
5551 | /* Record the fields for the semantic handler. */ | |
5552 | FLD (f_srcdst) = f_srcdst; | |
5553 | FLD (f_optdisp) = f_optdisp; | |
5554 | FLD (f_scale) = f_scale; | |
5555 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5556 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5557 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5558 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5559 | ||
5560 | #if WITH_PROFILE_MODEL_P | |
5561 | /* Record the fields for profiling. */ | |
5562 | if (PROFILE_MODEL_P (current_cpu)) | |
5563 | { | |
5564 | FLD (in_abase) = f_abase; | |
5565 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5566 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5567 | FLD (in_index) = f_index; | |
5568 | FLD (in_st_src) = f_srcdst; | |
5569 | } | |
5570 | #endif | |
5571 | #undef FLD | |
5572 | BREAK (ex); | |
5573 | } | |
5574 | ||
5575 | CASE (ex, FMT_STQ_OFFSET) : | |
5576 | { | |
5577 | CGEN_INSN_INT insn = base_insn; | |
5578 | #define FLD(f) abuf->fields.fmt_stq_offset.f | |
5579 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
5580 | ||
5581 | EXTRACT_IFMT_ST_OFFSET_CODE | |
5582 | ||
5583 | /* Record the fields for the semantic handler. */ | |
5584 | FLD (f_srcdst) = f_srcdst; | |
5585 | FLD (f_offset) = f_offset; | |
5586 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5587 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5588 | ||
5589 | #if WITH_PROFILE_MODEL_P | |
5590 | /* Record the fields for profiling. */ | |
5591 | if (PROFILE_MODEL_P (current_cpu)) | |
5592 | { | |
5593 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5594 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5595 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5596 | FLD (in_st_src) = f_srcdst; | |
5597 | } | |
5598 | #endif | |
5599 | #undef FLD | |
5600 | BREAK (ex); | |
5601 | } | |
5602 | ||
5603 | CASE (ex, FMT_STQ_INDIRECT_OFFSET) : | |
5604 | { | |
5605 | CGEN_INSN_INT insn = base_insn; | |
5606 | #define FLD(f) abuf->fields.fmt_stq_indirect_offset.f | |
5607 | EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
5608 | ||
5609 | EXTRACT_IFMT_ST_OFFSET_CODE | |
5610 | ||
5611 | /* Record the fields for the semantic handler. */ | |
5612 | FLD (f_srcdst) = f_srcdst; | |
5613 | FLD (f_offset) = f_offset; | |
5614 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5615 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5616 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5617 | ||
5618 | #if WITH_PROFILE_MODEL_P | |
5619 | /* Record the fields for profiling. */ | |
5620 | if (PROFILE_MODEL_P (current_cpu)) | |
5621 | { | |
5622 | FLD (in_abase) = f_abase; | |
5623 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5624 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5625 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5626 | FLD (in_st_src) = f_srcdst; | |
5627 | } | |
5628 | #endif | |
5629 | #undef FLD | |
5630 | BREAK (ex); | |
5631 | } | |
5632 | ||
5633 | CASE (ex, FMT_STQ_INDIRECT) : | |
5634 | { | |
5635 | CGEN_INSN_INT insn = base_insn; | |
5636 | #define FLD(f) abuf->fields.fmt_stq_indirect.f | |
5637 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5638 | ||
5639 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
5640 | ||
5641 | /* Record the fields for the semantic handler. */ | |
5642 | FLD (f_srcdst) = f_srcdst; | |
5643 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5644 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5645 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5646 | ||
5647 | #if WITH_PROFILE_MODEL_P | |
5648 | /* Record the fields for profiling. */ | |
5649 | if (PROFILE_MODEL_P (current_cpu)) | |
5650 | { | |
5651 | FLD (in_abase) = f_abase; | |
5652 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5653 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5654 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5655 | FLD (in_st_src) = f_srcdst; | |
5656 | } | |
5657 | #endif | |
5658 | #undef FLD | |
5659 | BREAK (ex); | |
5660 | } | |
5661 | ||
5662 | CASE (ex, FMT_STQ_INDIRECT_INDEX) : | |
5663 | { | |
5664 | CGEN_INSN_INT insn = base_insn; | |
5665 | #define FLD(f) abuf->fields.fmt_stq_indirect_index.f | |
5666 | EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5667 | ||
5668 | EXTRACT_IFMT_ST_INDIRECT_CODE | |
5669 | ||
5670 | /* Record the fields for the semantic handler. */ | |
5671 | FLD (f_srcdst) = f_srcdst; | |
5672 | FLD (f_scale) = f_scale; | |
5673 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5674 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5675 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5676 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5677 | ||
5678 | #if WITH_PROFILE_MODEL_P | |
5679 | /* Record the fields for profiling. */ | |
5680 | if (PROFILE_MODEL_P (current_cpu)) | |
5681 | { | |
5682 | FLD (in_abase) = f_abase; | |
5683 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5684 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5685 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5686 | FLD (in_index) = f_index; | |
5687 | FLD (in_st_src) = f_srcdst; | |
5688 | } | |
5689 | #endif | |
5690 | #undef FLD | |
5691 | BREAK (ex); | |
5692 | } | |
5693 | ||
5694 | CASE (ex, FMT_STQ_DISP) : | |
5695 | { | |
5696 | CGEN_INSN_INT insn = base_insn; | |
5697 | #define FLD(f) abuf->fields.fmt_stq_disp.f | |
5698 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5699 | ||
5700 | EXTRACT_IFMT_ST_DISP_CODE | |
5701 | ||
5702 | /* Record the fields for the semantic handler. */ | |
5703 | FLD (f_srcdst) = f_srcdst; | |
5704 | FLD (f_optdisp) = f_optdisp; | |
5705 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5706 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5707 | ||
5708 | #if WITH_PROFILE_MODEL_P | |
5709 | /* Record the fields for profiling. */ | |
5710 | if (PROFILE_MODEL_P (current_cpu)) | |
5711 | { | |
5712 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5713 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5714 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5715 | FLD (in_st_src) = f_srcdst; | |
5716 | } | |
5717 | #endif | |
5718 | #undef FLD | |
5719 | BREAK (ex); | |
5720 | } | |
5721 | ||
5722 | CASE (ex, FMT_STQ_INDIRECT_DISP) : | |
5723 | { | |
5724 | CGEN_INSN_INT insn = base_insn; | |
5725 | #define FLD(f) abuf->fields.fmt_stq_indirect_disp.f | |
5726 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5727 | ||
5728 | EXTRACT_IFMT_ST_DISP_CODE | |
5729 | ||
5730 | /* Record the fields for the semantic handler. */ | |
5731 | FLD (f_srcdst) = f_srcdst; | |
5732 | FLD (f_optdisp) = f_optdisp; | |
5733 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5734 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5735 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5736 | ||
5737 | #if WITH_PROFILE_MODEL_P | |
5738 | /* Record the fields for profiling. */ | |
5739 | if (PROFILE_MODEL_P (current_cpu)) | |
5740 | { | |
5741 | FLD (in_abase) = f_abase; | |
5742 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5743 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5744 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5745 | FLD (in_st_src) = f_srcdst; | |
5746 | } | |
5747 | #endif | |
5748 | #undef FLD | |
5749 | BREAK (ex); | |
5750 | } | |
5751 | ||
5752 | CASE (ex, FMT_STQ_INDEX_DISP) : | |
5753 | { | |
5754 | CGEN_INSN_INT insn = base_insn; | |
5755 | #define FLD(f) abuf->fields.fmt_stq_index_disp.f | |
5756 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5757 | ||
5758 | EXTRACT_IFMT_ST_DISP_CODE | |
5759 | ||
5760 | /* Record the fields for the semantic handler. */ | |
5761 | FLD (f_srcdst) = f_srcdst; | |
5762 | FLD (f_optdisp) = f_optdisp; | |
5763 | FLD (f_scale) = f_scale; | |
5764 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5765 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5766 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5767 | ||
5768 | #if WITH_PROFILE_MODEL_P | |
5769 | /* Record the fields for profiling. */ | |
5770 | if (PROFILE_MODEL_P (current_cpu)) | |
5771 | { | |
5772 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5773 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5774 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5775 | FLD (in_index) = f_index; | |
5776 | FLD (in_st_src) = f_srcdst; | |
5777 | } | |
5778 | #endif | |
5779 | #undef FLD | |
5780 | BREAK (ex); | |
5781 | } | |
5782 | ||
5783 | CASE (ex, FMT_STQ_INDIRECT_INDEX_DISP) : | |
5784 | { | |
5785 | CGEN_INSN_INT insn = base_insn; | |
5786 | #define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f | |
5787 | EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
5788 | ||
5789 | EXTRACT_IFMT_ST_DISP_CODE | |
5790 | ||
5791 | /* Record the fields for the semantic handler. */ | |
5792 | FLD (f_srcdst) = f_srcdst; | |
5793 | FLD (f_optdisp) = f_optdisp; | |
5794 | FLD (f_scale) = f_scale; | |
5795 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
5796 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
5797 | FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; | |
5798 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); | |
5799 | ||
5800 | #if WITH_PROFILE_MODEL_P | |
5801 | /* Record the fields for profiling. */ | |
5802 | if (PROFILE_MODEL_P (current_cpu)) | |
5803 | { | |
5804 | FLD (in_abase) = f_abase; | |
5805 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); | |
5806 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); | |
5807 | FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); | |
5808 | FLD (in_index) = f_index; | |
5809 | FLD (in_st_src) = f_srcdst; | |
5810 | } | |
5811 | #endif | |
5812 | #undef FLD | |
5813 | BREAK (ex); | |
5814 | } | |
5815 | ||
5816 | CASE (ex, FMT_CMPOBE_REG) : | |
5817 | { | |
5818 | CGEN_INSN_INT insn = base_insn; | |
5819 | #define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f | |
5820 | EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ | |
5821 | ||
5822 | EXTRACT_IFMT_CMPOBE_REG_CODE | |
5823 | ||
5824 | /* Record the fields for the semantic handler. */ | |
5825 | FLD (i_br_disp) = f_br_disp; | |
5826 | FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; | |
5827 | FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; | |
5828 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
5829 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobe_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); | |
5830 | ||
5831 | #if WITH_PROFILE_MODEL_P | |
5832 | /* Record the fields for profiling. */ | |
5833 | if (PROFILE_MODEL_P (current_cpu)) | |
5834 | { | |
5835 | FLD (in_br_src1) = f_br_src1; | |
5836 | FLD (in_br_src2) = f_br_src2; | |
5837 | } | |
5838 | #endif | |
5839 | #undef FLD | |
5840 | BREAK (ex); | |
5841 | } | |
5842 | ||
5843 | CASE (ex, FMT_CMPOBE_LIT) : | |
5844 | { | |
5845 | CGEN_INSN_INT insn = base_insn; | |
5846 | #define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f | |
5847 | EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ | |
5848 | ||
5849 | EXTRACT_IFMT_CMPOBE_LIT_CODE | |
5850 | ||
5851 | /* Record the fields for the semantic handler. */ | |
5852 | FLD (f_br_src1) = f_br_src1; | |
5853 | FLD (i_br_disp) = f_br_disp; | |
5854 | FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; | |
5855 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
5856 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobe_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); | |
5857 | ||
5858 | #if WITH_PROFILE_MODEL_P | |
5859 | /* Record the fields for profiling. */ | |
5860 | if (PROFILE_MODEL_P (current_cpu)) | |
5861 | { | |
5862 | FLD (in_br_src2) = f_br_src2; | |
5863 | } | |
5864 | #endif | |
5865 | #undef FLD | |
5866 | BREAK (ex); | |
5867 | } | |
5868 | ||
5869 | CASE (ex, FMT_CMPOBL_REG) : | |
5870 | { | |
5871 | CGEN_INSN_INT insn = base_insn; | |
5872 | #define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f | |
5873 | EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ | |
5874 | ||
5875 | EXTRACT_IFMT_CMPOBE_REG_CODE | |
5876 | ||
5877 | /* Record the fields for the semantic handler. */ | |
5878 | FLD (i_br_disp) = f_br_disp; | |
5879 | FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; | |
5880 | FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; | |
5881 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
5882 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobl_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); | |
5883 | ||
5884 | #if WITH_PROFILE_MODEL_P | |
5885 | /* Record the fields for profiling. */ | |
5886 | if (PROFILE_MODEL_P (current_cpu)) | |
5887 | { | |
5888 | FLD (in_br_src1) = f_br_src1; | |
5889 | FLD (in_br_src2) = f_br_src2; | |
5890 | } | |
5891 | #endif | |
5892 | #undef FLD | |
5893 | BREAK (ex); | |
5894 | } | |
5895 | ||
5896 | CASE (ex, FMT_CMPOBL_LIT) : | |
5897 | { | |
5898 | CGEN_INSN_INT insn = base_insn; | |
5899 | #define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f | |
5900 | EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ | |
5901 | ||
5902 | EXTRACT_IFMT_CMPOBE_LIT_CODE | |
5903 | ||
5904 | /* Record the fields for the semantic handler. */ | |
5905 | FLD (f_br_src1) = f_br_src1; | |
5906 | FLD (i_br_disp) = f_br_disp; | |
5907 | FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; | |
5908 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
5909 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobl_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); | |
5910 | ||
5911 | #if WITH_PROFILE_MODEL_P | |
5912 | /* Record the fields for profiling. */ | |
5913 | if (PROFILE_MODEL_P (current_cpu)) | |
5914 | { | |
5915 | FLD (in_br_src2) = f_br_src2; | |
5916 | } | |
5917 | #endif | |
5918 | #undef FLD | |
5919 | BREAK (ex); | |
5920 | } | |
5921 | ||
5922 | CASE (ex, FMT_BBC_REG) : | |
5923 | { | |
5924 | CGEN_INSN_INT insn = base_insn; | |
5925 | #define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f | |
5926 | EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ | |
5927 | ||
5928 | EXTRACT_IFMT_CMPOBE_REG_CODE | |
5929 | ||
5930 | /* Record the fields for the semantic handler. */ | |
5931 | FLD (i_br_disp) = f_br_disp; | |
5932 | FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; | |
5933 | FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; | |
5934 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
5935 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bbc_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); | |
5936 | ||
5937 | #if WITH_PROFILE_MODEL_P | |
5938 | /* Record the fields for profiling. */ | |
5939 | if (PROFILE_MODEL_P (current_cpu)) | |
5940 | { | |
5941 | FLD (in_br_src1) = f_br_src1; | |
5942 | FLD (in_br_src2) = f_br_src2; | |
5943 | } | |
5944 | #endif | |
5945 | #undef FLD | |
5946 | BREAK (ex); | |
5947 | } | |
5948 | ||
5949 | CASE (ex, FMT_BBC_LIT) : | |
5950 | { | |
5951 | CGEN_INSN_INT insn = base_insn; | |
5952 | #define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f | |
5953 | EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ | |
5954 | ||
5955 | EXTRACT_IFMT_CMPOBE_LIT_CODE | |
5956 | ||
5957 | /* Record the fields for the semantic handler. */ | |
5958 | FLD (f_br_src1) = f_br_src1; | |
5959 | FLD (i_br_disp) = f_br_disp; | |
5960 | FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; | |
5961 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
5962 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bbc_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); | |
5963 | ||
5964 | #if WITH_PROFILE_MODEL_P | |
5965 | /* Record the fields for profiling. */ | |
5966 | if (PROFILE_MODEL_P (current_cpu)) | |
5967 | { | |
5968 | FLD (in_br_src2) = f_br_src2; | |
5969 | } | |
5970 | #endif | |
5971 | #undef FLD | |
5972 | BREAK (ex); | |
5973 | } | |
5974 | ||
5975 | CASE (ex, FMT_CMPI) : | |
5976 | { | |
5977 | CGEN_INSN_INT insn = base_insn; | |
5978 | #define FLD(f) abuf->fields.fmt_cmpi.f | |
5979 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
5980 | ||
5981 | EXTRACT_IFMT_MULO_CODE | |
5982 | ||
5983 | /* Record the fields for the semantic handler. */ | |
5984 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
5985 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
5986 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); | |
5987 | ||
5988 | #if WITH_PROFILE_MODEL_P | |
5989 | /* Record the fields for profiling. */ | |
5990 | if (PROFILE_MODEL_P (current_cpu)) | |
5991 | { | |
5992 | FLD (in_src1) = f_src1; | |
5993 | FLD (in_src2) = f_src2; | |
5994 | } | |
5995 | #endif | |
5996 | #undef FLD | |
5997 | BREAK (ex); | |
5998 | } | |
5999 | ||
6000 | CASE (ex, FMT_CMPI1) : | |
6001 | { | |
6002 | CGEN_INSN_INT insn = base_insn; | |
6003 | #define FLD(f) abuf->fields.fmt_cmpi1.f | |
6004 | EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6005 | ||
6006 | EXTRACT_IFMT_MULO1_CODE | |
6007 | ||
6008 | /* Record the fields for the semantic handler. */ | |
6009 | FLD (f_src1) = f_src1; | |
6010 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
6011 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); | |
6012 | ||
6013 | #if WITH_PROFILE_MODEL_P | |
6014 | /* Record the fields for profiling. */ | |
6015 | if (PROFILE_MODEL_P (current_cpu)) | |
6016 | { | |
6017 | FLD (in_src2) = f_src2; | |
6018 | } | |
6019 | #endif | |
6020 | #undef FLD | |
6021 | BREAK (ex); | |
6022 | } | |
6023 | ||
6024 | CASE (ex, FMT_CMPI2) : | |
6025 | { | |
6026 | CGEN_INSN_INT insn = base_insn; | |
6027 | #define FLD(f) abuf->fields.fmt_cmpi2.f | |
6028 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6029 | ||
6030 | EXTRACT_IFMT_MULO2_CODE | |
6031 | ||
6032 | /* Record the fields for the semantic handler. */ | |
6033 | FLD (f_src2) = f_src2; | |
6034 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
6035 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0)); | |
6036 | ||
6037 | #if WITH_PROFILE_MODEL_P | |
6038 | /* Record the fields for profiling. */ | |
6039 | if (PROFILE_MODEL_P (current_cpu)) | |
6040 | { | |
6041 | FLD (in_src1) = f_src1; | |
6042 | } | |
6043 | #endif | |
6044 | #undef FLD | |
6045 | BREAK (ex); | |
6046 | } | |
6047 | ||
6048 | CASE (ex, FMT_CMPI3) : | |
6049 | { | |
6050 | CGEN_INSN_INT insn = base_insn; | |
6051 | #define FLD(f) abuf->fields.fmt_cmpi3.f | |
6052 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6053 | ||
6054 | EXTRACT_IFMT_MULO3_CODE | |
6055 | ||
6056 | /* Record the fields for the semantic handler. */ | |
6057 | FLD (f_src1) = f_src1; | |
6058 | FLD (f_src2) = f_src2; | |
6059 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0)); | |
6060 | ||
6061 | #if WITH_PROFILE_MODEL_P | |
6062 | /* Record the fields for profiling. */ | |
6063 | if (PROFILE_MODEL_P (current_cpu)) | |
6064 | { | |
6065 | } | |
6066 | #endif | |
6067 | #undef FLD | |
6068 | BREAK (ex); | |
6069 | } | |
6070 | ||
6071 | CASE (ex, FMT_CMPO) : | |
6072 | { | |
6073 | CGEN_INSN_INT insn = base_insn; | |
6074 | #define FLD(f) abuf->fields.fmt_cmpo.f | |
6075 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6076 | ||
6077 | EXTRACT_IFMT_MULO_CODE | |
6078 | ||
6079 | /* Record the fields for the semantic handler. */ | |
6080 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
6081 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
6082 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); | |
6083 | ||
6084 | #if WITH_PROFILE_MODEL_P | |
6085 | /* Record the fields for profiling. */ | |
6086 | if (PROFILE_MODEL_P (current_cpu)) | |
6087 | { | |
6088 | FLD (in_src1) = f_src1; | |
6089 | FLD (in_src2) = f_src2; | |
6090 | } | |
6091 | #endif | |
6092 | #undef FLD | |
6093 | BREAK (ex); | |
6094 | } | |
6095 | ||
6096 | CASE (ex, FMT_CMPO1) : | |
6097 | { | |
6098 | CGEN_INSN_INT insn = base_insn; | |
6099 | #define FLD(f) abuf->fields.fmt_cmpo1.f | |
6100 | EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6101 | ||
6102 | EXTRACT_IFMT_MULO1_CODE | |
6103 | ||
6104 | /* Record the fields for the semantic handler. */ | |
6105 | FLD (f_src1) = f_src1; | |
6106 | FLD (i_src2) = & CPU (h_gr)[f_src2]; | |
6107 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); | |
6108 | ||
6109 | #if WITH_PROFILE_MODEL_P | |
6110 | /* Record the fields for profiling. */ | |
6111 | if (PROFILE_MODEL_P (current_cpu)) | |
6112 | { | |
6113 | FLD (in_src2) = f_src2; | |
6114 | } | |
6115 | #endif | |
6116 | #undef FLD | |
6117 | BREAK (ex); | |
6118 | } | |
6119 | ||
6120 | CASE (ex, FMT_CMPO2) : | |
6121 | { | |
6122 | CGEN_INSN_INT insn = base_insn; | |
6123 | #define FLD(f) abuf->fields.fmt_cmpo2.f | |
6124 | EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6125 | ||
6126 | EXTRACT_IFMT_MULO2_CODE | |
6127 | ||
6128 | /* Record the fields for the semantic handler. */ | |
6129 | FLD (f_src2) = f_src2; | |
6130 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
6131 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0)); | |
6132 | ||
6133 | #if WITH_PROFILE_MODEL_P | |
6134 | /* Record the fields for profiling. */ | |
6135 | if (PROFILE_MODEL_P (current_cpu)) | |
6136 | { | |
6137 | FLD (in_src1) = f_src1; | |
6138 | } | |
6139 | #endif | |
6140 | #undef FLD | |
6141 | BREAK (ex); | |
6142 | } | |
6143 | ||
6144 | CASE (ex, FMT_CMPO3) : | |
6145 | { | |
6146 | CGEN_INSN_INT insn = base_insn; | |
6147 | #define FLD(f) abuf->fields.fmt_cmpo3.f | |
6148 | EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6149 | ||
6150 | EXTRACT_IFMT_MULO3_CODE | |
6151 | ||
6152 | /* Record the fields for the semantic handler. */ | |
6153 | FLD (f_src1) = f_src1; | |
6154 | FLD (f_src2) = f_src2; | |
6155 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0)); | |
6156 | ||
6157 | #if WITH_PROFILE_MODEL_P | |
6158 | /* Record the fields for profiling. */ | |
6159 | if (PROFILE_MODEL_P (current_cpu)) | |
6160 | { | |
6161 | } | |
6162 | #endif | |
6163 | #undef FLD | |
6164 | BREAK (ex); | |
6165 | } | |
6166 | ||
6167 | CASE (ex, FMT_TESTNO_REG) : | |
6168 | { | |
6169 | CGEN_INSN_INT insn = base_insn; | |
6170 | #define FLD(f) abuf->fields.fmt_testno_reg.f | |
6171 | EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ | |
6172 | ||
6173 | EXTRACT_IFMT_CMPOBE_REG_CODE | |
6174 | ||
6175 | /* Record the fields for the semantic handler. */ | |
6176 | FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; | |
6177 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_testno_reg", "br_src1 0x%x", 'x', f_br_src1, (char *) 0)); | |
6178 | ||
6179 | #if WITH_PROFILE_MODEL_P | |
6180 | /* Record the fields for profiling. */ | |
6181 | if (PROFILE_MODEL_P (current_cpu)) | |
6182 | { | |
6183 | FLD (out_br_src1) = f_br_src1; | |
6184 | } | |
6185 | #endif | |
6186 | #undef FLD | |
6187 | BREAK (ex); | |
6188 | } | |
6189 | ||
6190 | CASE (ex, FMT_BNO) : | |
6191 | { | |
6192 | CGEN_INSN_INT insn = base_insn; | |
6193 | #define FLD(f) abuf->fields.cti.fields.fmt_bno.f | |
6194 | EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ | |
6195 | ||
6196 | EXTRACT_IFMT_BNO_CODE | |
6197 | ||
6198 | /* Record the fields for the semantic handler. */ | |
6199 | FLD (i_ctrl_disp) = f_ctrl_disp; | |
6200 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6201 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bno", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0)); | |
6202 | ||
6203 | #if WITH_PROFILE_MODEL_P | |
6204 | /* Record the fields for profiling. */ | |
6205 | if (PROFILE_MODEL_P (current_cpu)) | |
6206 | { | |
6207 | } | |
6208 | #endif | |
6209 | #undef FLD | |
6210 | BREAK (ex); | |
6211 | } | |
6212 | ||
6213 | CASE (ex, FMT_B) : | |
6214 | { | |
6215 | CGEN_INSN_INT insn = base_insn; | |
6216 | #define FLD(f) abuf->fields.cti.fields.fmt_b.f | |
6217 | EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ | |
6218 | ||
6219 | EXTRACT_IFMT_BNO_CODE | |
6220 | ||
6221 | /* Record the fields for the semantic handler. */ | |
6222 | FLD (i_ctrl_disp) = f_ctrl_disp; | |
6223 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6224 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_b", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0)); | |
6225 | ||
6226 | #if WITH_PROFILE_MODEL_P | |
6227 | /* Record the fields for profiling. */ | |
6228 | if (PROFILE_MODEL_P (current_cpu)) | |
6229 | { | |
6230 | } | |
6231 | #endif | |
6232 | #undef FLD | |
6233 | BREAK (ex); | |
6234 | } | |
6235 | ||
6236 | CASE (ex, FMT_BX_INDIRECT_OFFSET) : | |
6237 | { | |
6238 | CGEN_INSN_INT insn = base_insn; | |
6239 | #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f | |
6240 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
6241 | ||
6242 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
6243 | ||
6244 | /* Record the fields for the semantic handler. */ | |
6245 | FLD (f_offset) = f_offset; | |
6246 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
6247 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6248 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0)); | |
6249 | ||
6250 | #if WITH_PROFILE_MODEL_P | |
6251 | /* Record the fields for profiling. */ | |
6252 | if (PROFILE_MODEL_P (current_cpu)) | |
6253 | { | |
6254 | FLD (in_abase) = f_abase; | |
6255 | } | |
6256 | #endif | |
6257 | #undef FLD | |
6258 | BREAK (ex); | |
6259 | } | |
6260 | ||
6261 | CASE (ex, FMT_BX_INDIRECT) : | |
6262 | { | |
6263 | CGEN_INSN_INT insn = base_insn; | |
6264 | #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f | |
6265 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
6266 | ||
6267 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
6268 | ||
6269 | /* Record the fields for the semantic handler. */ | |
6270 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
6271 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6272 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0)); | |
6273 | ||
6274 | #if WITH_PROFILE_MODEL_P | |
6275 | /* Record the fields for profiling. */ | |
6276 | if (PROFILE_MODEL_P (current_cpu)) | |
6277 | { | |
6278 | FLD (in_abase) = f_abase; | |
6279 | } | |
6280 | #endif | |
6281 | #undef FLD | |
6282 | BREAK (ex); | |
6283 | } | |
6284 | ||
6285 | CASE (ex, FMT_BX_INDIRECT_INDEX) : | |
6286 | { | |
6287 | CGEN_INSN_INT insn = base_insn; | |
6288 | #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f | |
6289 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
6290 | ||
6291 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
6292 | ||
6293 | /* Record the fields for the semantic handler. */ | |
6294 | FLD (f_scale) = f_scale; | |
6295 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
6296 | FLD (i_index) = & CPU (h_gr)[f_index]; | |
6297 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6298 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, (char *) 0)); | |
6299 | ||
6300 | #if WITH_PROFILE_MODEL_P | |
6301 | /* Record the fields for profiling. */ | |
6302 | if (PROFILE_MODEL_P (current_cpu)) | |
6303 | { | |
6304 | FLD (in_abase) = f_abase; | |
6305 | FLD (in_index) = f_index; | |
6306 | } | |
6307 | #endif | |
6308 | #undef FLD | |
6309 | BREAK (ex); | |
6310 | } | |
6311 | ||
6312 | CASE (ex, FMT_BX_DISP) : | |
6313 | { | |
6314 | CGEN_INSN_INT insn = base_insn; | |
6315 | #define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f | |
6316 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
6317 | ||
6318 | EXTRACT_IFMT_LDA_DISP_CODE | |
6319 | ||
6320 | /* Record the fields for the semantic handler. */ | |
6321 | FLD (f_optdisp) = f_optdisp; | |
6322 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6323 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0)); | |
6324 | ||
6325 | #if WITH_PROFILE_MODEL_P | |
6326 | /* Record the fields for profiling. */ | |
6327 | if (PROFILE_MODEL_P (current_cpu)) | |
6328 | { | |
6329 | } | |
6330 | #endif | |
6331 | #undef FLD | |
6332 | BREAK (ex); | |
6333 | } | |
6334 | ||
6335 | CASE (ex, FMT_BX_INDIRECT_DISP) : | |
6336 | { | |
6337 | CGEN_INSN_INT insn = base_insn; | |
6338 | #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f | |
6339 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
6340 | ||
6341 | EXTRACT_IFMT_LDA_DISP_CODE | |
6342 | ||
6343 | /* Record the fields for the semantic handler. */ | |
6344 | FLD (f_optdisp) = f_optdisp; | |
6345 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
6346 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6347 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, (char *) 0)); | |
6348 | ||
6349 | #if WITH_PROFILE_MODEL_P | |
6350 | /* Record the fields for profiling. */ | |
6351 | if (PROFILE_MODEL_P (current_cpu)) | |
6352 | { | |
6353 | FLD (in_abase) = f_abase; | |
6354 | } | |
6355 | #endif | |
6356 | #undef FLD | |
6357 | BREAK (ex); | |
6358 | } | |
6359 | ||
6360 | CASE (ex, FMT_CALLX_DISP) : | |
6361 | { | |
6362 | CGEN_INSN_INT insn = base_insn; | |
6363 | #define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f | |
6364 | EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
6365 | ||
6366 | EXTRACT_IFMT_LDA_DISP_CODE | |
6367 | ||
6368 | /* Record the fields for the semantic handler. */ | |
6369 | FLD (f_optdisp) = f_optdisp; | |
6370 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6371 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0)); | |
6372 | ||
6373 | #if WITH_PROFILE_MODEL_P | |
6374 | /* Record the fields for profiling. */ | |
6375 | if (PROFILE_MODEL_P (current_cpu)) | |
6376 | { | |
6377 | FLD (in_h_gr_0) = 0; | |
6378 | FLD (in_h_gr_1) = 1; | |
6379 | FLD (in_h_gr_10) = 10; | |
6380 | FLD (in_h_gr_11) = 11; | |
6381 | FLD (in_h_gr_12) = 12; | |
6382 | FLD (in_h_gr_13) = 13; | |
6383 | FLD (in_h_gr_14) = 14; | |
6384 | FLD (in_h_gr_15) = 15; | |
6385 | FLD (in_h_gr_2) = 2; | |
6386 | FLD (in_h_gr_3) = 3; | |
6387 | FLD (in_h_gr_31) = 31; | |
6388 | FLD (in_h_gr_4) = 4; | |
6389 | FLD (in_h_gr_5) = 5; | |
6390 | FLD (in_h_gr_6) = 6; | |
6391 | FLD (in_h_gr_7) = 7; | |
6392 | FLD (in_h_gr_8) = 8; | |
6393 | FLD (in_h_gr_9) = 9; | |
6394 | FLD (out_h_gr_0) = 0; | |
6395 | FLD (out_h_gr_1) = 1; | |
6396 | FLD (out_h_gr_10) = 10; | |
6397 | FLD (out_h_gr_11) = 11; | |
6398 | FLD (out_h_gr_12) = 12; | |
6399 | FLD (out_h_gr_13) = 13; | |
6400 | FLD (out_h_gr_14) = 14; | |
6401 | FLD (out_h_gr_15) = 15; | |
6402 | FLD (out_h_gr_2) = 2; | |
6403 | FLD (out_h_gr_3) = 3; | |
6404 | FLD (out_h_gr_31) = 31; | |
6405 | FLD (out_h_gr_4) = 4; | |
6406 | FLD (out_h_gr_5) = 5; | |
6407 | FLD (out_h_gr_6) = 6; | |
6408 | FLD (out_h_gr_7) = 7; | |
6409 | FLD (out_h_gr_8) = 8; | |
6410 | FLD (out_h_gr_9) = 9; | |
6411 | } | |
6412 | #endif | |
6413 | #undef FLD | |
6414 | BREAK (ex); | |
6415 | } | |
6416 | ||
6417 | CASE (ex, FMT_CALLX_INDIRECT) : | |
6418 | { | |
6419 | CGEN_INSN_INT insn = base_insn; | |
6420 | #define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f | |
6421 | EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ | |
6422 | ||
6423 | EXTRACT_IFMT_LDA_INDIRECT_CODE | |
6424 | ||
6425 | /* Record the fields for the semantic handler. */ | |
6426 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
6427 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6428 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0)); | |
6429 | ||
6430 | #if WITH_PROFILE_MODEL_P | |
6431 | /* Record the fields for profiling. */ | |
6432 | if (PROFILE_MODEL_P (current_cpu)) | |
6433 | { | |
6434 | FLD (in_abase) = f_abase; | |
6435 | FLD (in_h_gr_0) = 0; | |
6436 | FLD (in_h_gr_1) = 1; | |
6437 | FLD (in_h_gr_10) = 10; | |
6438 | FLD (in_h_gr_11) = 11; | |
6439 | FLD (in_h_gr_12) = 12; | |
6440 | FLD (in_h_gr_13) = 13; | |
6441 | FLD (in_h_gr_14) = 14; | |
6442 | FLD (in_h_gr_15) = 15; | |
6443 | FLD (in_h_gr_2) = 2; | |
6444 | FLD (in_h_gr_3) = 3; | |
6445 | FLD (in_h_gr_31) = 31; | |
6446 | FLD (in_h_gr_4) = 4; | |
6447 | FLD (in_h_gr_5) = 5; | |
6448 | FLD (in_h_gr_6) = 6; | |
6449 | FLD (in_h_gr_7) = 7; | |
6450 | FLD (in_h_gr_8) = 8; | |
6451 | FLD (in_h_gr_9) = 9; | |
6452 | FLD (out_h_gr_0) = 0; | |
6453 | FLD (out_h_gr_1) = 1; | |
6454 | FLD (out_h_gr_10) = 10; | |
6455 | FLD (out_h_gr_11) = 11; | |
6456 | FLD (out_h_gr_12) = 12; | |
6457 | FLD (out_h_gr_13) = 13; | |
6458 | FLD (out_h_gr_14) = 14; | |
6459 | FLD (out_h_gr_15) = 15; | |
6460 | FLD (out_h_gr_2) = 2; | |
6461 | FLD (out_h_gr_3) = 3; | |
6462 | FLD (out_h_gr_31) = 31; | |
6463 | FLD (out_h_gr_4) = 4; | |
6464 | FLD (out_h_gr_5) = 5; | |
6465 | FLD (out_h_gr_6) = 6; | |
6466 | FLD (out_h_gr_7) = 7; | |
6467 | FLD (out_h_gr_8) = 8; | |
6468 | FLD (out_h_gr_9) = 9; | |
6469 | } | |
6470 | #endif | |
6471 | #undef FLD | |
6472 | BREAK (ex); | |
6473 | } | |
6474 | ||
6475 | CASE (ex, FMT_CALLX_INDIRECT_OFFSET) : | |
6476 | { | |
6477 | CGEN_INSN_INT insn = base_insn; | |
6478 | #define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f | |
6479 | EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ | |
6480 | ||
6481 | EXTRACT_IFMT_LDA_OFFSET_CODE | |
6482 | ||
6483 | /* Record the fields for the semantic handler. */ | |
6484 | FLD (f_offset) = f_offset; | |
6485 | FLD (i_abase) = & CPU (h_gr)[f_abase]; | |
6486 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6487 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0)); | |
6488 | ||
6489 | #if WITH_PROFILE_MODEL_P | |
6490 | /* Record the fields for profiling. */ | |
6491 | if (PROFILE_MODEL_P (current_cpu)) | |
6492 | { | |
6493 | FLD (in_abase) = f_abase; | |
6494 | FLD (in_h_gr_0) = 0; | |
6495 | FLD (in_h_gr_1) = 1; | |
6496 | FLD (in_h_gr_10) = 10; | |
6497 | FLD (in_h_gr_11) = 11; | |
6498 | FLD (in_h_gr_12) = 12; | |
6499 | FLD (in_h_gr_13) = 13; | |
6500 | FLD (in_h_gr_14) = 14; | |
6501 | FLD (in_h_gr_15) = 15; | |
6502 | FLD (in_h_gr_2) = 2; | |
6503 | FLD (in_h_gr_3) = 3; | |
6504 | FLD (in_h_gr_31) = 31; | |
6505 | FLD (in_h_gr_4) = 4; | |
6506 | FLD (in_h_gr_5) = 5; | |
6507 | FLD (in_h_gr_6) = 6; | |
6508 | FLD (in_h_gr_7) = 7; | |
6509 | FLD (in_h_gr_8) = 8; | |
6510 | FLD (in_h_gr_9) = 9; | |
6511 | FLD (out_h_gr_0) = 0; | |
6512 | FLD (out_h_gr_1) = 1; | |
6513 | FLD (out_h_gr_10) = 10; | |
6514 | FLD (out_h_gr_11) = 11; | |
6515 | FLD (out_h_gr_12) = 12; | |
6516 | FLD (out_h_gr_13) = 13; | |
6517 | FLD (out_h_gr_14) = 14; | |
6518 | FLD (out_h_gr_15) = 15; | |
6519 | FLD (out_h_gr_2) = 2; | |
6520 | FLD (out_h_gr_3) = 3; | |
6521 | FLD (out_h_gr_31) = 31; | |
6522 | FLD (out_h_gr_4) = 4; | |
6523 | FLD (out_h_gr_5) = 5; | |
6524 | FLD (out_h_gr_6) = 6; | |
6525 | FLD (out_h_gr_7) = 7; | |
6526 | FLD (out_h_gr_8) = 8; | |
6527 | FLD (out_h_gr_9) = 9; | |
6528 | } | |
6529 | #endif | |
6530 | #undef FLD | |
6531 | BREAK (ex); | |
6532 | } | |
6533 | ||
6534 | CASE (ex, FMT_RET) : | |
6535 | { | |
6536 | CGEN_INSN_INT insn = base_insn; | |
6537 | #define FLD(f) abuf->fields.cti.fields.fmt_ret.f | |
6538 | EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ | |
6539 | ||
6540 | EXTRACT_IFMT_BNO_CODE | |
6541 | ||
6542 | /* Record the fields for the semantic handler. */ | |
6543 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6544 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ret", (char *) 0)); | |
6545 | ||
6546 | #if WITH_PROFILE_MODEL_P | |
6547 | /* Record the fields for profiling. */ | |
6548 | if (PROFILE_MODEL_P (current_cpu)) | |
6549 | { | |
6550 | FLD (in_h_gr_0) = 0; | |
6551 | FLD (in_h_gr_2) = 2; | |
6552 | FLD (in_h_gr_31) = 31; | |
6553 | FLD (out_h_gr_0) = 0; | |
6554 | FLD (out_h_gr_1) = 1; | |
6555 | FLD (out_h_gr_10) = 10; | |
6556 | FLD (out_h_gr_11) = 11; | |
6557 | FLD (out_h_gr_12) = 12; | |
6558 | FLD (out_h_gr_13) = 13; | |
6559 | FLD (out_h_gr_14) = 14; | |
6560 | FLD (out_h_gr_15) = 15; | |
6561 | FLD (out_h_gr_2) = 2; | |
6562 | FLD (out_h_gr_3) = 3; | |
6563 | FLD (out_h_gr_31) = 31; | |
6564 | FLD (out_h_gr_4) = 4; | |
6565 | FLD (out_h_gr_5) = 5; | |
6566 | FLD (out_h_gr_6) = 6; | |
6567 | FLD (out_h_gr_7) = 7; | |
6568 | FLD (out_h_gr_8) = 8; | |
6569 | FLD (out_h_gr_9) = 9; | |
6570 | } | |
6571 | #endif | |
6572 | #undef FLD | |
6573 | BREAK (ex); | |
6574 | } | |
6575 | ||
6576 | CASE (ex, FMT_CALLS) : | |
6577 | { | |
6578 | CGEN_INSN_INT insn = base_insn; | |
6579 | #define FLD(f) abuf->fields.cti.fields.fmt_calls.f | |
6580 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6581 | ||
6582 | EXTRACT_IFMT_MULO_CODE | |
6583 | ||
6584 | /* Record the fields for the semantic handler. */ | |
6585 | FLD (i_src1) = & CPU (h_gr)[f_src1]; | |
6586 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6587 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_calls", "src1 0x%x", 'x', f_src1, (char *) 0)); | |
6588 | ||
6589 | #if WITH_PROFILE_MODEL_P | |
6590 | /* Record the fields for profiling. */ | |
6591 | if (PROFILE_MODEL_P (current_cpu)) | |
6592 | { | |
6593 | FLD (in_src1) = f_src1; | |
6594 | } | |
6595 | #endif | |
6596 | #undef FLD | |
6597 | BREAK (ex); | |
6598 | } | |
6599 | ||
6600 | CASE (ex, FMT_FMARK) : | |
6601 | { | |
6602 | CGEN_INSN_INT insn = base_insn; | |
6603 | #define FLD(f) abuf->fields.cti.fields.fmt_fmark.f | |
6604 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6605 | ||
6606 | EXTRACT_IFMT_MULO_CODE | |
6607 | ||
6608 | /* Record the fields for the semantic handler. */ | |
6609 | SEM_BRANCH_INIT_EXTRACT (abuf); | |
6610 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_fmark", (char *) 0)); | |
6611 | ||
6612 | #if WITH_PROFILE_MODEL_P | |
6613 | /* Record the fields for profiling. */ | |
6614 | if (PROFILE_MODEL_P (current_cpu)) | |
6615 | { | |
6616 | } | |
6617 | #endif | |
6618 | #undef FLD | |
6619 | BREAK (ex); | |
6620 | } | |
6621 | ||
6622 | CASE (ex, FMT_FLUSHREG) : | |
6623 | { | |
6624 | CGEN_INSN_INT insn = base_insn; | |
6625 | #define FLD(f) abuf->fields.fmt_flushreg.f | |
6626 | EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ | |
6627 | ||
6628 | EXTRACT_IFMT_MULO_CODE | |
6629 | ||
6630 | /* Record the fields for the semantic handler. */ | |
6631 | TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_flushreg", (char *) 0)); | |
6632 | ||
6633 | #undef FLD | |
6634 | BREAK (ex); | |
6635 | } | |
6636 | ||
6637 | ||
6638 | } | |
6639 | ENDSWITCH (ex) | |
6640 | ||
6641 | } | |
6642 | ||
6643 | return idecode->idesc; | |
6644 | } |