[deliverable/binutils-gdb.git] / sim / m32r / Makefile.in

# Makefile template for Configure for the m32r simulator
# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003, 2004
# Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of GDB, the GNU debugger.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

## COMMON_PRE_CONFIG_FRAG

M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
TRAPS_OBJ = @traps_obj@

CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =

SIM_OBJS = \
	$(SIM_NEW_COMMON_OBJS) \
	sim-cpu.o \
	sim-hload.o \
	sim-hrw.o \
	sim-model.o \
	sim-reg.o \
	cgen-utils.o cgen-trace.o cgen-scache.o \
	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
	sim-if.o arch.o \
	$(M32R_OBJS) \
	$(M32RX_OBJS) \
	$(M32R2_OBJS) \
	$(TRAPS_OBJ) \
	devices.o \
	$(CONFIG_DEVICES)

# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
	$(CGEN_INCLUDE_DEPS) \
	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h

SIM_EXTRA_CFLAGS = @sim_extra_cflags@

SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = m32r-clean

# This selects the m32r newlib/libgloss syscall definitions.
NL_TARGET = -DNL_TARGET_m32r

## COMMON_POST_CONFIG_FRAG

arch = m32r

sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h

arch.o: arch.c $(SIM_MAIN_DEPS)

traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
devices.o: devices.c $(SIM_MAIN_DEPS)

# M32R objs

M32RBF_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu.h decode.h eng.h

m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloop.c eng.h: stamp-mloop
stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -fast -pbb -switch sem-switch.c \
		-cpu m32rbf -infile $(srcdir)/mloop.in
	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
	touch stamp-mloop
mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)

cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
model.o: model.c $(M32RBF_INCLUDE_DEPS)

# M32RX objs

M32RXF_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpux.h decodex.h engx.h

m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloopx.c engx.h: stamp-xmloop
stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
		-cpu m32rxf -infile $(srcdir)/mloopx.in \
		-outfile-suffix x
	$(SHELL) $(srcroot)/move-if-change engx.hin engx.h
	$(SHELL) $(srcroot)/move-if-change mloopx.cin mloopx.c
	touch stamp-xmloop
mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)

cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)

# M32R2 objs

M32R2F_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu2.h decode2.h eng2.h

m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloop2.c eng2.h: stamp-2mloop
stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
	$(SHELL) $(srccom)/genmloop.sh \
		-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
		-cpu m32r2f -infile $(srcdir)/mloop2.in \
		-outfile-suffix 2
	$(SHELL) $(srcroot)/move-if-change eng2.hin eng2.h
	$(SHELL) $(srcroot)/move-if-change mloop2.cin mloop2.c
	touch stamp-2mloop

mloop2.o:  mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
cpu2.o:    cpu2.c    $(M32R2F_INCLUDE_DEPS)
decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
sem2.o:    sem2.c    $(M32R2F_INCLUDE_DEPS)
model2.o:  model2.c  $(M32R2F_INCLUDE_DEPS)

m32r-clean:
	rm -f mloop.c eng.h stamp-mloop
	rm -f mloopx.c engx.h stamp-xmloop
	rm -f mloop2.c eng2.h stamp-2mloop
	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
	rm -f tmp-*

# cgen support, enable with --enable-cgen-maint
CGEN_MAINT = ; @true
# The following line is commented in or out depending upon --enable-cgen-maint.
@CGEN_MAINT@CGEN_MAINT =

stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn"
	touch stamp-arch
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch

stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32rbf mach=m32r SUFFIX= \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	touch stamp-cpu
cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu

stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32rxf mach=m32rx SUFFIX=x \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
	touch stamp-xcpu
cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu

stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32r2f mach=m32r2 SUFFIX=2 \
	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
	touch stamp-2cpu
cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu
Commit	Line	Data
c906108c	1	# Makefile template for Configure for the m32r simulator
4d06b60c DJ	2	# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003, 2004
4d06b60c DJ	3	# Free Software Foundation, Inc.
c906108c SS	4	# Contributed by Cygnus Support.
	5	#
	6	# This file is part of GDB, the GNU debugger.
	7	#
	8	# This program is free software; you can redistribute it and/or modify
	9	# it under the terms of the GNU General Public License as published by
	10	# the Free Software Foundation; either version 2 of the License, or
	11	# (at your option) any later version.
	12	#
	13	# This program is distributed in the hope that it will be useful,
	14	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	# GNU General Public License for more details.
	17	#
	18	# You should have received a copy of the GNU General Public License along
	19	# with this program; if not, write to the Free Software Foundation, Inc.,
	20	# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	21
	22	## COMMON_PRE_CONFIG_FRAG
	23
	24	M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
2df3850c	25	M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
16b47b25	26	M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
6edf0760	27	TRAPS_OBJ = @traps_obj@
c906108c SS	28
	29	CONFIG_DEVICES = dv-sockser.o
	30	CONFIG_DEVICES =
	31
	32	SIM_OBJS = \
	33	$(SIM_NEW_COMMON_OBJS) \
	34	sim-cpu.o \
	35	sim-hload.o \
	36	sim-hrw.o \
	37	sim-model.o \
	38	sim-reg.o \
	39	cgen-utils.o cgen-trace.o cgen-scache.o \
	40	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
	41	sim-if.o arch.o \
	42	$(M32R_OBJS) \
2df3850c	43	$(M32RX_OBJS) \
16b47b25	44	$(M32R2_OBJS) \
6edf0760 NC	45	$(TRAPS_OBJ) \
6edf0760 NC	46	devices.o \
c906108c SS	47	$(CONFIG_DEVICES)
	48
	49	# Extra headers included by sim-main.h.
	50	SIM_EXTRA_DEPS = \
	51	$(CGEN_INCLUDE_DEPS) \
	52	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h
	53
6edf0760	54	SIM_EXTRA_CFLAGS = @sim_extra_cflags@
c906108c SS	55
	56	SIM_RUN_OBJS = nrun.o
	57	SIM_EXTRA_CLEAN = m32r-clean
	58
	59	# This selects the m32r newlib/libgloss syscall definitions.
	60	NL_TARGET = -DNL_TARGET_m32r
	61
	62	## COMMON_POST_CONFIG_FRAG
	63
	64	arch = m32r
	65
	66	sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
	67
	68	arch.o: arch.c $(SIM_MAIN_DEPS)
	69
	70	traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
6edf0760	71	traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
c906108c SS	72	devices.o: devices.c $(SIM_MAIN_DEPS)
	73
	74	# M32R objs
	75
	76	M32RBF_INCLUDE_DEPS = \
	77	$(CGEN_MAIN_CPU_DEPS) \
	78	cpu.h decode.h eng.h
	79
	80	m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)
	81
	82	# FIXME: Use of `mono' is wip.
	83	mloop.c eng.h: stamp-mloop
	84	stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	85	$(SHELL) $(srccom)/genmloop.sh \
	86	-mono -fast -pbb -switch sem-switch.c \
	87	-cpu m32rbf -infile $(srcdir)/mloop.in
	88	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
	89	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
	90	touch stamp-mloop
	91	mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)
	92
	93	cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
	94	decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
	95	sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
	96	model.o: model.c $(M32RBF_INCLUDE_DEPS)
	97
2df3850c JM	98	# M32RX objs
	99
	100	M32RXF_INCLUDE_DEPS = \
	101	$(CGEN_MAIN_CPU_DEPS) \
	102	cpux.h decodex.h engx.h
	103
	104	m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
	105
	106	# FIXME: Use of `mono' is wip.
	107	mloopx.c engx.h: stamp-xmloop
	108	stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
	109	$(SHELL) $(srccom)/genmloop.sh \
	110	-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
4d06b60c DJ	111	-cpu m32rxf -infile $(srcdir)/mloopx.in \
	112	-outfile-suffix x
	113	$(SHELL) $(srcroot)/move-if-change engx.hin engx.h
	114	$(SHELL) $(srcroot)/move-if-change mloopx.cin mloopx.c
2df3850c JM	115	touch stamp-xmloop
	116	mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
	117
	118	cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
	119	decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
	120	semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
	121	modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
c906108c	122
16b47b25 NC	123	# M32R2 objs
	124
	125	M32R2F_INCLUDE_DEPS = \
	126	$(CGEN_MAIN_CPU_DEPS) \
	127	cpu2.h decode2.h eng2.h
	128
	129	m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
	130
	131	# FIXME: Use of `mono' is wip.
	132	mloop2.c eng2.h: stamp-2mloop
	133	stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
	134	$(SHELL) $(srccom)/genmloop.sh \
	135	-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
4d06b60c DJ	136	-cpu m32r2f -infile $(srcdir)/mloop2.in \
	137	-outfile-suffix 2
	138	$(SHELL) $(srcroot)/move-if-change eng2.hin eng2.h
	139	$(SHELL) $(srcroot)/move-if-change mloop2.cin mloop2.c
16b47b25 NC	140	touch stamp-2mloop
	141
	142	mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
	143	cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
	144	decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
	145	sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
	146	model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
	147
c906108c SS	148	m32r-clean:
c906108c SS	149	rm -f mloop.c eng.h stamp-mloop
2df3850c	150	rm -f mloopx.c engx.h stamp-xmloop
16b47b25 NC	151	rm -f mloop2.c eng2.h stamp-2mloop
16b47b25 NC	152	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
c906108c SS	153	rm -f tmp-*
c906108c SS	154
604259a0 FCE	155	# cgen support, enable with --enable-cgen-maint
	156	CGEN_MAINT = ; @true
	157	# The following line is commented in or out depending upon --enable-cgen-maint.
	158	@CGEN_MAINT@CGEN_MAINT =
	159
e3e473da	160	stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/m32r.cpu
604259a0	161	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
a6fc1778	162	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
604259a0 FCE	163	FLAGS="with-scache with-profile=fn"
	164	touch stamp-arch
	165	arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
604259a0	166
e3e473da	167	stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
604259a0 FCE	168	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
604259a0 FCE	169	cpu=m32rbf mach=m32r SUFFIX= \
a6fc1778	170	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
604259a0 FCE	171	FLAGS="with-scache with-profile=fn" \
	172	EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	173	touch stamp-cpu
	174	cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
604259a0	175
e3e473da	176	stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
604259a0	177	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
a6fc1778 DB	178	cpu=m32rxf mach=m32rx SUFFIX=x \
	179	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	180	FLAGS="with-scache with-profile=fn" \
	181	EXTRAFILES="$(CGEN_CPU_SEMSW)"
604259a0 FCE	182	touch stamp-xcpu
604259a0 FCE	183	cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
16b47b25 NC	184
	185	stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
	186	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	187	cpu=m32r2f mach=m32r2 SUFFIX=2 \
	188	archfile=$(CGEN_CPU_DIR)/m32r.cpu \
	189	FLAGS="with-scache with-profile=fn" \
	190	EXTRAFILES="$(CGEN_CPU_SEMSW)"
	191	touch stamp-2cpu
	192	cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu