[deliverable/binutils-gdb.git] / sim / m32r / Makefile.in

# Makefile template for Configure for the m32r simulator
# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of GDB, the GNU debugger.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

## COMMON_PRE_CONFIG_FRAG

M32R_OBJS = m32r.o cpu.o decode.o extract.o sem.o model.o mloop.o
# start-sanitize-m32rx
M32RX_OBJS = m32rx.o cpux.o decodex.o semx.o modelx.o mloopx.o
# end-sanitize-m32rx

SIM_OBJS = \
	$(SIM_NEW_COMMON_OBJS) \
	sim-engine.o \
	sim-hload.o \
	sim-hrw.o \
	sim-model.o \
	sim-reason.o \
	cgen-utils.o cgen-trace.o cgen-scache.o \
	sim-if.o arch.o \
	$(start-sanitize-m32rx) \
	$(M32RX_OBJS) \
	$(end-sanitize-m32rx) \
	$(M32R_OBJS)

# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
	$(srcdir)/../common/cgen-types.h \
	$(srcdir)/../common/cgen-sim.h \
	$(srcdir)/../common/cgen-trace.h \
	arch.h cpuall.h m32r-sim.h cpu-opc.h

SIM_EXTRA_CFLAGS =

SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = m32r-clean

# This selects the m32r newlib/libgloss syscall definitions.
NL_TARGET = -DNL_TARGET_m32r

## COMMON_POST_CONFIG_FRAG

arch = m32r

MAIN_INCLUDE_DEPS = \
	sim-main.h \
	$(srcdir)/../common/sim-config.h \
	$(srcdir)/../common/sim-base.h \
	$(srcdir)/../common/sim-basics.h \
	$(srcdir)/../common/sim-module.h \
	$(srcdir)/../common/sim-trace.h \
	$(srcdir)/../common/sim-profile.h \
	tconfig.h
INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS) cpu-sim.h
OPS_INCLUDE_DEPS = \
	$(srcdir)/../common/cgen-mem.h \
	$(srcdir)/../common/cgen-ops.h

sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h

arch.o: arch.c $(INCLUDE_DEPS)

# M32R objs

m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h

# FIXME: Use of `mono' is wip.
mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	rm -f mloop.c
	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
		-mono -scache -fast m32r $(srcdir)/mloop.in \
		| sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
mloop.o: mloop.c sem-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h

cpu.o: cpu.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
decode.o: decode.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
extract.o: extract.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
	$(CC) -c $(srcdir)/extract.c $(ALL_CFLAGS) -DSCACHE_P
sem.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
	$(CC) -c $(srcdir)/sem.c $(ALL_CFLAGS) -DSCACHE_P
model.o: model.c $(INCLUDE_DEPS) cpu.h

#sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
#	$(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)

# start-sanitize-m32rx
# M32RX objs

m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h

# FIXME: Use of `mono' is wip.
mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
	rm -f mloopx.c
	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
		-mono -no-scache -no-fast -parallel \
		m32r $(srcdir)/mloopx.in \
		| sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
mloopx.o: mloopx.c readx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h

cpux.o: cpux.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
decodex.o: decodex.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
semx.o: semx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
modelx.o: modelx.c $(INCLUDE_DEPS) cpux.h
# end-sanitize-m32rx

m32r-clean:
	rm -f mloop.c stamp-arch stamp-cpu stamp-decode
# start-sanitize-m32rx
	rm -f mloopx.c stamp-xcpu stamp-xdecode
# end-sanitize-m32rx
	rm -f tmp-*

# start-sanitize-cygnus
# cgen support
# For now, require developers to configure with --enable-maintainer-mode.
# ??? Do we need to use a different option?

stamp-arch: $(CGEN_MAIN_SCM) $(srccgen)/m32r.cpu
	$(MAKE) cgen-arch
	touch stamp-arch
arch.h arch.c cpuall.h: @MAINT@ stamp-arch
	@true

stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
	$(MAKE) cgen-cpu cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	touch stamp-cpu
cpu.h extract.c sem.c sem-switch.c model.c: @MAINT@ stamp-cpu
	@true

stamp-decode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
	$(MAKE) cgen-decode cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn"
	touch stamp-decode
decode.h decode.c: @MAINT@ stamp-decode
	@true
# start-sanitize-cygnus

# start-sanitize-m32rx
stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
	$(MAKE) cgen-cpu cpu=m32rx mach=m32rx SUFFIX=x FLAGS="" EXTRAFILES="$(CGEN_CPU_READ) $(CGEN_CPU_SEM)"
	touch stamp-xcpu
cpux.h readx.c semx.c modelx.c: @MAINT@ stamp-xcpu
	@true

stamp-xdecode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
	$(MAKE) cgen-decode cpu=m32rx mach=m32rx SUFFIX=x
	touch stamp-xdecode
decodex.h decodex.c: @MAINT@ stamp-xdecode
	@true
# end-sanitize-m32rx
Commit	Line	Data
fafce69a	1	# Makefile template for Configure for the m32r simulator
369fba30	2	# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
fafce69a AC	3	# Contributed by Cygnus Support.
	4	#
	5	# This file is part of GDB, the GNU debugger.
	6	#
	7	# This program is free software; you can redistribute it and/or modify
	8	# it under the terms of the GNU General Public License as published by
	9	# the Free Software Foundation; either version 2 of the License, or
	10	# (at your option) any later version.
	11	#
	12	# This program is distributed in the hope that it will be useful,
	13	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	# GNU General Public License for more details.
	16	#
	17	# You should have received a copy of the GNU General Public License along
	18	# with this program; if not, write to the Free Software Foundation, Inc.,
	19	# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	20
	21	## COMMON_PRE_CONFIG_FRAG
	22
0e701ac3	23	M32R_OBJS = m32r.o cpu.o decode.o extract.o sem.o model.o mloop.o
369fba30	24	# start-sanitize-m32rx
0e701ac3	25	M32RX_OBJS = m32rx.o cpux.o decodex.o semx.o modelx.o mloopx.o
369fba30 DE	26	# end-sanitize-m32rx
	27
	28	SIM_OBJS = \
	29	$(SIM_NEW_COMMON_OBJS) \
0e701ac3 AC	30	sim-engine.o \
	31	sim-hload.o \
	32	sim-hrw.o \
	33	sim-model.o \
	34	sim-reason.o \
369fba30 DE	35	cgen-utils.o cgen-trace.o cgen-scache.o \
369fba30 DE	36	sim-if.o arch.o \
8e420152 DE	37	$(start-sanitize-m32rx) \
	38	$(M32RX_OBJS) \
	39	$(end-sanitize-m32rx) \
369fba30	40	$(M32R_OBJS)
fafce69a AC	41
	42	# Extra headers included by sim-main.h.
	43	SIM_EXTRA_DEPS = \
	44	$(srcdir)/../common/cgen-types.h \
	45	$(srcdir)/../common/cgen-sim.h \
	46	$(srcdir)/../common/cgen-trace.h \
599bae21	47	arch.h cpuall.h m32r-sim.h cpu-opc.h
fafce69a	48
369fba30	49	SIM_EXTRA_CFLAGS =
fafce69a AC	50
	51	SIM_RUN_OBJS = nrun.o
	52	SIM_EXTRA_CLEAN = m32r-clean
	53
0e701ac3 AC	54	# This selects the m32r newlib/libgloss syscall definitions.
	55	NL_TARGET = -DNL_TARGET_m32r
	56
fafce69a AC	57	## COMMON_POST_CONFIG_FRAG
fafce69a AC	58
369fba30 DE	59	arch = m32r
369fba30 DE	60
fafce69a AC	61	MAIN_INCLUDE_DEPS = \
	62	sim-main.h \
	63	$(srcdir)/../common/sim-config.h \
	64	$(srcdir)/../common/sim-base.h \
	65	$(srcdir)/../common/sim-basics.h \
	66	$(srcdir)/../common/sim-module.h \
	67	$(srcdir)/../common/sim-trace.h \
	68	$(srcdir)/../common/sim-profile.h \
	69	tconfig.h
	70	INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS) cpu-sim.h
369fba30 DE	71	OPS_INCLUDE_DEPS = \
	72	$(srcdir)/../common/cgen-mem.h \
	73	$(srcdir)/../common/cgen-ops.h
fafce69a AC	74
fafce69a AC	75	sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h
fafce69a	76
599bae21	77	arch.o: arch.c $(INCLUDE_DEPS)
369fba30 DE	78
	79	# M32R objs
	80
b8a9943d DE	81	m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
b8a9943d DE	82
369fba30 DE	83	# FIXME: Use of `mono' is wip.
	84	mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	85	rm -f mloop.c
b8a9943d DE	86	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
	87	-mono -scache -fast m32r $(srcdir)/mloop.in \
	88	\| sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
369fba30 DE	89	mloop.o: mloop.c sem-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
369fba30 DE	90
0e701ac3	91	cpu.o: cpu.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
599bae21	92	decode.o: decode.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
369fba30	93	extract.o: extract.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
b8a9943d	94	$(CC) -c $(srcdir)/extract.c $(ALL_CFLAGS) -DSCACHE_P
369fba30	95	sem.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
0e701ac3	96	$(CC) -c $(srcdir)/sem.c $(ALL_CFLAGS) -DSCACHE_P
599bae21	97	model.o: model.c $(INCLUDE_DEPS) cpu.h
369fba30	98
b8a9943d DE	99	#sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
b8a9943d DE	100	# $(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
369fba30 DE	101
	102	# start-sanitize-m32rx
	103	# M32RX objs
	104
b8a9943d DE	105	m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
b8a9943d DE	106
fafce69a	107	# FIXME: Use of `mono' is wip.
369fba30 DE	108	mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
369fba30 DE	109	rm -f mloopx.c
b8a9943d	110	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
0e701ac3	111	-mono -no-scache -no-fast -parallel \
b8a9943d DE	112	m32r $(srcdir)/mloopx.in \
b8a9943d DE	113	\| sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
8e420152	114	mloopx.o: mloopx.c readx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
fafce69a	115
0e701ac3	116	cpux.o: cpux.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
599bae21	117	decodex.o: decodex.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
369fba30	118	semx.o: semx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
599bae21	119	modelx.o: modelx.c $(INCLUDE_DEPS) cpux.h
369fba30	120	# end-sanitize-m32rx
fafce69a AC	121
fafce69a AC	122	m32r-clean:
369fba30 DE	123	rm -f mloop.c stamp-arch stamp-cpu stamp-decode
	124	# start-sanitize-m32rx
	125	rm -f mloopx.c stamp-xcpu stamp-xdecode
	126	# end-sanitize-m32rx
	127	rm -f tmp-*
	128
	129	# start-sanitize-cygnus
	130	# cgen support
	131	# For now, require developers to configure with --enable-maintainer-mode.
	132	# ??? Do we need to use a different option?
	133
	134	stamp-arch: $(CGEN_MAIN_SCM) $(srccgen)/m32r.cpu
	135	$(MAKE) cgen-arch
	136	touch stamp-arch
	137	arch.h arch.c cpuall.h: @MAINT@ stamp-arch
	138	@true
	139
	140	stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
	141	$(MAKE) cgen-cpu cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	142	touch stamp-cpu
	143	cpu.h extract.c sem.c sem-switch.c model.c: @MAINT@ stamp-cpu
	144	@true
	145
	146	stamp-decode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
	147	$(MAKE) cgen-decode cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn"
	148	touch stamp-decode
	149	decode.h decode.c: @MAINT@ stamp-decode
	150	@true
	151	# start-sanitize-cygnus
	152
	153	# start-sanitize-m32rx
	154	stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
8e420152	155	$(MAKE) cgen-cpu cpu=m32rx mach=m32rx SUFFIX=x FLAGS="" EXTRAFILES="$(CGEN_CPU_READ) $(CGEN_CPU_SEM)"
369fba30	156	touch stamp-xcpu
8e420152	157	cpux.h readx.c semx.c modelx.c: @MAINT@ stamp-xcpu
369fba30 DE	158	@true
	159
	160	stamp-xdecode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
	161	$(MAKE) cgen-decode cpu=m32rx mach=m32rx SUFFIX=x
	162	touch stamp-xdecode
	163	decodex.h decodex.c: @MAINT@ stamp-xdecode
	164	@true
	165	# end-sanitize-m32rx