[deliverable/binutils-gdb.git] / sim / m32r / Makefile.in

# Makefile template for Configure for the m32r simulator
# Copyright (C) 1996-2015 Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of GDB, the GNU debugger.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.

## COMMON_PRE_CONFIG_FRAG

M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
TRAPS_OBJ = @traps_obj@

SIM_OBJS = \
	$(SIM_NEW_COMMON_OBJS) \
	sim-hload.o \
	sim-model.o \
	cgen-utils.o cgen-trace.o cgen-scache.o \
	cgen-run.o \
	sim-if.o arch.o \
	$(M32R_OBJS) \
	$(M32RX_OBJS) \
	$(M32R2_OBJS) \
	$(TRAPS_OBJ) \
	devices.o

# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
	$(CGEN_INCLUDE_DEPS) \
	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h

SIM_EXTRA_CFLAGS = @sim_extra_cflags@

SIM_EXTRA_CLEAN = m32r-clean

# This selects the m32r newlib/libgloss syscall definitions.
NL_TARGET = -DNL_TARGET_m32r

## COMMON_POST_CONFIG_FRAG

arch = m32r

sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h

arch.o: arch.c $(SIM_MAIN_DEPS)

traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
devices.o: devices.c $(SIM_MAIN_DEPS)

# M32R objs

M32RBF_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu.h decode.h eng.h

m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloop.c eng.h: stamp-mloop ; @true
stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
		-mono -fast -pbb -switch sem-switch.c \
		-cpu m32rbf -infile $(srcdir)/mloop.in
	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
	touch stamp-mloop
mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)

cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
model.o: model.c $(M32RBF_INCLUDE_DEPS)

# M32RX objs

M32RXF_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpux.h decodex.h engx.h

m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloopx.c engx.h: stamp-xmloop ; @true
stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
		-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
		-cpu m32rxf -infile $(srcdir)/mloopx.in \
		-outfile-suffix x
	$(SHELL) $(srcroot)/move-if-change engx.hin engx.h
	$(SHELL) $(srcroot)/move-if-change mloopx.cin mloopx.c
	touch stamp-xmloop
mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)

cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)

# M32R2 objs

M32R2F_INCLUDE_DEPS = \
	$(CGEN_MAIN_CPU_DEPS) \
	cpu2.h decode2.h eng2.h

m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)

# FIXME: Use of `mono' is wip.
mloop2.c eng2.h: stamp-2mloop ; @true
stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
		-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
		-cpu m32r2f -infile $(srcdir)/mloop2.in \
		-outfile-suffix 2
	$(SHELL) $(srcroot)/move-if-change eng2.hin eng2.h
	$(SHELL) $(srcroot)/move-if-change mloop2.cin mloop2.c
	touch stamp-2mloop

mloop2.o: mloop2.c $(srcdir)/sem2-switch.c $(M32R2F_INCLUDE_DEPS)
cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
model2.o: model2.c $(M32R2F_INCLUDE_DEPS)

m32r-clean:
	rm -f mloop.c eng.h stamp-mloop
	rm -f mloopx.c engx.h stamp-xmloop
	rm -f mloop2.c eng2.h stamp-2mloop
	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
	rm -f tmp-*

# cgen support, enable with --enable-cgen-maint
CGEN_MAINT = ; @true
# The following line is commented in or out depending upon --enable-cgen-maint.
@CGEN_MAINT@CGEN_MAINT =

# NOTE: Generated source files are specified as full paths,
# e.g. $(srcdir)/arch.c, because make may decide the files live
# in objdir otherwise.

stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CPU_DIR)/m32r.cpu Makefile
	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
	  archfile=$(CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn"
	touch stamp-arch
$(srcdir)/arch.h $(srcdir)/arch.c $(srcdir)/cpuall.h: $(CGEN_MAINT) stamp-arch
	@true

stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/m32r.cpu Makefile
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32rbf mach=m32r SUFFIX= \
	  archfile=$(CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	touch stamp-cpu
$(srcdir)/cpu.h $(srcdir)/sem.c $(srcdir)/sem-switch.c $(srcdir)/model.c $(srcdir)/decode.c $(srcdir)/decode.h: $(CGEN_MAINT) stamp-cpu
	@true

stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/m32r.cpu Makefile
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32rxf mach=m32rx SUFFIX=x \
	  archfile=$(CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
	touch stamp-xcpu
$(srcdir)/cpux.h $(srcdir)/semx-switch.c $(srcdir)/modelx.c $(srcdir)/decodex.c $(srcdir)/decodex.h: $(CGEN_MAINT) stamp-xcpu
	@true

stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/m32r.cpu Makefile
	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
	  cpu=m32r2f mach=m32r2 SUFFIX=2 \
	  archfile=$(CPU_DIR)/m32r.cpu \
	  FLAGS="with-scache with-profile=fn" \
	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
	touch stamp-2cpu
$(srcdir)/cpu2.h $(srcdir)/sem2-switch.c $(srcdir)/model2.c $(srcdir)/decode2.c $(srcdir)/decode2.h: $(CGEN_MAINT) stamp-2cpu
	@true
Commit	Line	Data
c906108c	1	# Makefile template for Configure for the m32r simulator
32d0add0	2	# Copyright (C) 1996-2015 Free Software Foundation, Inc.
c906108c SS	3	# Contributed by Cygnus Support.
	4	#
	5	# This file is part of GDB, the GNU debugger.
	6	#
	7	# This program is free software; you can redistribute it and/or modify
	8	# it under the terms of the GNU General Public License as published by
4744ac1b	9	# the Free Software Foundation; either version 3 of the License, or
c906108c SS	10	# (at your option) any later version.
	11	#
	12	# This program is distributed in the hope that it will be useful,
	13	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	# GNU General Public License for more details.
	16	#
4744ac1b JB	17	# You should have received a copy of the GNU General Public License
4744ac1b JB	18	# along with this program. If not, see <http://www.gnu.org/licenses/>.
c906108c SS	19
	20	## COMMON_PRE_CONFIG_FRAG
	21
	22	M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
2df3850c	23	M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
16b47b25	24	M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
6edf0760	25	TRAPS_OBJ = @traps_obj@
c906108c	26
c906108c SS	27	SIM_OBJS = \
c906108c SS	28	$(SIM_NEW_COMMON_OBJS) \
c906108c	29	sim-hload.o \
c906108c	30	sim-model.o \
c906108c	31	cgen-utils.o cgen-trace.o cgen-scache.o \
797eee42	32	cgen-run.o \
c906108c SS	33	sim-if.o arch.o \
c906108c SS	34	$(M32R_OBJS) \
2df3850c	35	$(M32RX_OBJS) \
16b47b25	36	$(M32R2_OBJS) \
6edf0760	37	$(TRAPS_OBJ) \
9e3042ec	38	devices.o
c906108c SS	39
	40	# Extra headers included by sim-main.h.
	41	SIM_EXTRA_DEPS = \
	42	$(CGEN_INCLUDE_DEPS) \
	43	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h
	44
6edf0760	45	SIM_EXTRA_CFLAGS = @sim_extra_cflags@
c906108c	46
c906108c SS	47	SIM_EXTRA_CLEAN = m32r-clean
	48
	49	# This selects the m32r newlib/libgloss syscall definitions.
	50	NL_TARGET = -DNL_TARGET_m32r
	51
	52	## COMMON_POST_CONFIG_FRAG
	53
	54	arch = m32r
	55
	56	sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
	57
	58	arch.o: arch.c $(SIM_MAIN_DEPS)
	59
	60	traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
6edf0760	61	traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
c906108c SS	62	devices.o: devices.c $(SIM_MAIN_DEPS)
	63
	64	# M32R objs
	65
	66	M32RBF_INCLUDE_DEPS = \
	67	$(CGEN_MAIN_CPU_DEPS) \
	68	cpu.h decode.h eng.h
	69
	70	m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)
	71
	72	# FIXME: Use of `mono' is wip.
894a1d7b	73	mloop.c eng.h: stamp-mloop ; @true
c906108c	74	stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
086c6838	75	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
c906108c SS	76	-mono -fast -pbb -switch sem-switch.c \
	77	-cpu m32rbf -infile $(srcdir)/mloop.in
	78	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
	79	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
	80	touch stamp-mloop
	81	mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)
	82
	83	cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
	84	decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
	85	sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
	86	model.o: model.c $(M32RBF_INCLUDE_DEPS)
	87
2df3850c JM	88	# M32RX objs
	89
	90	M32RXF_INCLUDE_DEPS = \
	91	$(CGEN_MAIN_CPU_DEPS) \
	92	cpux.h decodex.h engx.h
	93
	94	m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
	95
	96	# FIXME: Use of `mono' is wip.
894a1d7b	97	mloopx.c engx.h: stamp-xmloop ; @true
2df3850c	98	stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
086c6838	99	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
2df3850c	100	-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
4d06b60c DJ	101	-cpu m32rxf -infile $(srcdir)/mloopx.in \
	102	-outfile-suffix x
	103	$(SHELL) $(srcroot)/move-if-change engx.hin engx.h
	104	$(SHELL) $(srcroot)/move-if-change mloopx.cin mloopx.c
2df3850c JM	105	touch stamp-xmloop
	106	mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
	107
	108	cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
	109	decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
	110	semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
	111	modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
c906108c	112
16b47b25 NC	113	# M32R2 objs
	114
	115	M32R2F_INCLUDE_DEPS = \
	116	$(CGEN_MAIN_CPU_DEPS) \
	117	cpu2.h decode2.h eng2.h
	118
	119	m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
	120
	121	# FIXME: Use of `mono' is wip.
894a1d7b	122	mloop2.c eng2.h: stamp-2mloop ; @true
16b47b25	123	stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
086c6838	124	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
16b47b25	125	-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
4d06b60c DJ	126	-cpu m32r2f -infile $(srcdir)/mloop2.in \
	127	-outfile-suffix 2
	128	$(SHELL) $(srcroot)/move-if-change eng2.hin eng2.h
	129	$(SHELL) $(srcroot)/move-if-change mloop2.cin mloop2.c
16b47b25 NC	130	touch stamp-2mloop
16b47b25 NC	131
894a1d7b DE	132	mloop2.o: mloop2.c $(srcdir)/sem2-switch.c $(M32R2F_INCLUDE_DEPS)
894a1d7b DE	133	cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
16b47b25	134	decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
894a1d7b DE	135	sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
894a1d7b DE	136	model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
16b47b25	137
c906108c SS	138	m32r-clean:
c906108c SS	139	rm -f mloop.c eng.h stamp-mloop
2df3850c	140	rm -f mloopx.c engx.h stamp-xmloop
16b47b25 NC	141	rm -f mloop2.c eng2.h stamp-2mloop
16b47b25 NC	142	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
c906108c SS	143	rm -f tmp-*
c906108c SS	144
604259a0 FCE	145	# cgen support, enable with --enable-cgen-maint
	146	CGEN_MAINT = ; @true
	147	# The following line is commented in or out depending upon --enable-cgen-maint.
	148	@CGEN_MAINT@CGEN_MAINT =
	149
894a1d7b DE	150	# NOTE: Generated source files are specified as full paths,
	151	# e.g. $(srcdir)/arch.c, because make may decide the files live
	152	# in objdir otherwise.
	153
	154	stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CPU_DIR)/m32r.cpu Makefile
604259a0	155	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
6a8b8615	156	archfile=$(CPU_DIR)/m32r.cpu \
604259a0 FCE	157	FLAGS="with-scache with-profile=fn"
604259a0 FCE	158	touch stamp-arch
894a1d7b DE	159	$(srcdir)/arch.h $(srcdir)/arch.c $(srcdir)/cpuall.h: $(CGEN_MAINT) stamp-arch
894a1d7b DE	160	@true
604259a0	161
894a1d7b	162	stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/m32r.cpu Makefile
604259a0 FCE	163	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
604259a0 FCE	164	cpu=m32rbf mach=m32r SUFFIX= \
6a8b8615	165	archfile=$(CPU_DIR)/m32r.cpu \
604259a0 FCE	166	FLAGS="with-scache with-profile=fn" \
	167	EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
	168	touch stamp-cpu
894a1d7b DE	169	$(srcdir)/cpu.h $(srcdir)/sem.c $(srcdir)/sem-switch.c $(srcdir)/model.c $(srcdir)/decode.c $(srcdir)/decode.h: $(CGEN_MAINT) stamp-cpu
894a1d7b DE	170	@true
604259a0	171
894a1d7b	172	stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/m32r.cpu Makefile
604259a0	173	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
a6fc1778	174	cpu=m32rxf mach=m32rx SUFFIX=x \
6a8b8615	175	archfile=$(CPU_DIR)/m32r.cpu \
a6fc1778 DB	176	FLAGS="with-scache with-profile=fn" \
a6fc1778 DB	177	EXTRAFILES="$(CGEN_CPU_SEMSW)"
604259a0	178	touch stamp-xcpu
894a1d7b DE	179	$(srcdir)/cpux.h $(srcdir)/semx-switch.c $(srcdir)/modelx.c $(srcdir)/decodex.c $(srcdir)/decodex.h: $(CGEN_MAINT) stamp-xcpu
894a1d7b DE	180	@true
16b47b25	181
894a1d7b	182	stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/m32r.cpu Makefile
16b47b25 NC	183	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
16b47b25 NC	184	cpu=m32r2f mach=m32r2 SUFFIX=2 \
6a8b8615	185	archfile=$(CPU_DIR)/m32r.cpu \
16b47b25 NC	186	FLAGS="with-scache with-profile=fn" \
	187	EXTRAFILES="$(CGEN_CPU_SEMSW)"
	188	touch stamp-2cpu
894a1d7b DE	189	$(srcdir)/cpu2.h $(srcdir)/sem2-switch.c $(srcdir)/model2.c $(srcdir)/decode2.c $(srcdir)/decode2.h: $(CGEN_MAINT) stamp-2cpu
894a1d7b DE	190	@true